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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.71 96.51 89.73 97.22 69.05 93.48 98.44 90.53


Total test records in report: 1632
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T88 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2145439219 Jul 06 06:57:22 PM PDT 24 Jul 06 06:57:24 PM PDT 24 300560895 ps
T1537 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2179378493 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 54305371 ps
T1538 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1409454413 Jul 06 06:56:06 PM PDT 24 Jul 06 06:56:52 PM PDT 24 16957813 ps
T1539 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1766058908 Jul 06 06:57:26 PM PDT 24 Jul 06 06:57:28 PM PDT 24 32104588 ps
T1540 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2287898913 Jul 06 06:55:39 PM PDT 24 Jul 06 06:56:27 PM PDT 24 39713700 ps
T171 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.585830466 Jul 06 06:57:06 PM PDT 24 Jul 06 06:57:13 PM PDT 24 35403202 ps
T89 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1066479334 Jul 06 06:55:47 PM PDT 24 Jul 06 06:56:38 PM PDT 24 351173628 ps
T210 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1831627149 Jul 06 06:56:55 PM PDT 24 Jul 06 06:57:10 PM PDT 24 38042905 ps
T1541 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3723050904 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:31 PM PDT 24 20768192 ps
T172 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3785641215 Jul 06 06:56:12 PM PDT 24 Jul 06 06:56:57 PM PDT 24 26292076 ps
T90 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1090425986 Jul 06 06:55:49 PM PDT 24 Jul 06 06:56:43 PM PDT 24 912789400 ps
T1542 /workspace/coverage/cover_reg_top/32.i2c_intr_test.973230253 Jul 06 06:57:25 PM PDT 24 Jul 06 06:57:27 PM PDT 24 18094636 ps
T195 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2053342426 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 55824517 ps
T1543 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1166490095 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 19205768 ps
T91 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2948367021 Jul 06 06:55:44 PM PDT 24 Jul 06 06:56:38 PM PDT 24 474550482 ps
T92 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2449188490 Jul 06 06:55:45 PM PDT 24 Jul 06 06:56:36 PM PDT 24 29101459 ps
T193 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.699787660 Jul 06 06:55:59 PM PDT 24 Jul 06 06:56:49 PM PDT 24 176031795 ps
T1544 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2866989887 Jul 06 06:57:23 PM PDT 24 Jul 06 06:57:25 PM PDT 24 24776486 ps
T1545 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2769720340 Jul 06 06:57:18 PM PDT 24 Jul 06 06:57:20 PM PDT 24 18260863 ps
T196 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2858898924 Jul 06 06:56:01 PM PDT 24 Jul 06 06:56:50 PM PDT 24 19018398 ps
T184 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3653281846 Jul 06 06:56:08 PM PDT 24 Jul 06 06:56:55 PM PDT 24 195251152 ps
T197 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.860805274 Jul 06 06:56:28 PM PDT 24 Jul 06 06:57:03 PM PDT 24 48154736 ps
T1546 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3777528185 Jul 06 06:55:45 PM PDT 24 Jul 06 06:56:36 PM PDT 24 96644156 ps
T1547 /workspace/coverage/cover_reg_top/12.i2c_intr_test.137209297 Jul 06 06:56:29 PM PDT 24 Jul 06 06:57:04 PM PDT 24 14458570 ps
T1548 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1235207006 Jul 06 06:56:56 PM PDT 24 Jul 06 06:57:12 PM PDT 24 142323888 ps
T1549 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.889810263 Jul 06 06:57:22 PM PDT 24 Jul 06 06:57:24 PM PDT 24 20027612 ps
T93 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1566525459 Jul 06 06:55:49 PM PDT 24 Jul 06 06:56:39 PM PDT 24 31426336 ps
T1550 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1137183633 Jul 06 06:55:49 PM PDT 24 Jul 06 06:56:38 PM PDT 24 43998789 ps
T94 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1445115154 Jul 06 06:57:27 PM PDT 24 Jul 06 06:57:29 PM PDT 24 74087075 ps
T1551 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1511511023 Jul 06 06:57:29 PM PDT 24 Jul 06 06:57:31 PM PDT 24 27116429 ps
T1552 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2593958070 Jul 06 06:57:25 PM PDT 24 Jul 06 06:57:27 PM PDT 24 29728117 ps
T1553 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1900213359 Jul 06 06:55:50 PM PDT 24 Jul 06 06:56:41 PM PDT 24 41134271 ps
T1554 /workspace/coverage/cover_reg_top/7.i2c_intr_test.659758070 Jul 06 06:56:06 PM PDT 24 Jul 06 06:56:52 PM PDT 24 54863512 ps
T181 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1528359495 Jul 06 06:55:56 PM PDT 24 Jul 06 06:56:47 PM PDT 24 117430416 ps
T130 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.619690453 Jul 06 06:56:09 PM PDT 24 Jul 06 06:56:54 PM PDT 24 26214813 ps
T106 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.586217884 Jul 06 06:55:55 PM PDT 24 Jul 06 06:56:48 PM PDT 24 348855139 ps
T198 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.89514388 Jul 06 06:57:05 PM PDT 24 Jul 06 06:57:12 PM PDT 24 26475812 ps
T1555 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3724214878 Jul 06 06:56:45 PM PDT 24 Jul 06 06:57:09 PM PDT 24 84543591 ps
T1556 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1065607944 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 34586683 ps
T182 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1352133883 Jul 06 06:57:23 PM PDT 24 Jul 06 06:57:26 PM PDT 24 289760163 ps
T1557 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1004775804 Jul 06 06:57:19 PM PDT 24 Jul 06 06:57:21 PM PDT 24 67453476 ps
T1558 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1016750721 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 29169472 ps
T177 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1799054496 Jul 06 06:55:39 PM PDT 24 Jul 06 06:56:29 PM PDT 24 152770526 ps
T1559 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1194223000 Jul 06 06:55:44 PM PDT 24 Jul 06 06:56:36 PM PDT 24 47514933 ps
T1560 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3961922959 Jul 06 06:55:55 PM PDT 24 Jul 06 06:56:46 PM PDT 24 94001667 ps
T1561 /workspace/coverage/cover_reg_top/1.i2c_intr_test.774577423 Jul 06 06:55:46 PM PDT 24 Jul 06 06:56:36 PM PDT 24 61274171 ps
T1562 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2686279811 Jul 06 06:56:07 PM PDT 24 Jul 06 06:56:53 PM PDT 24 108257307 ps
T174 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4287742378 Jul 06 06:56:24 PM PDT 24 Jul 06 06:57:03 PM PDT 24 632811489 ps
T199 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3109324317 Jul 06 06:57:11 PM PDT 24 Jul 06 06:57:13 PM PDT 24 30750295 ps
T1563 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2932400887 Jul 06 06:56:02 PM PDT 24 Jul 06 06:56:50 PM PDT 24 74832110 ps
T1564 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3997194136 Jul 06 06:57:18 PM PDT 24 Jul 06 06:57:20 PM PDT 24 68707902 ps
T1565 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.785320712 Jul 06 06:57:23 PM PDT 24 Jul 06 06:57:25 PM PDT 24 97427182 ps
T183 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.765576621 Jul 06 06:56:02 PM PDT 24 Jul 06 06:56:51 PM PDT 24 131232064 ps
T1566 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.399490441 Jul 06 06:56:44 PM PDT 24 Jul 06 06:57:11 PM PDT 24 115298892 ps
T1567 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2529305568 Jul 06 06:56:04 PM PDT 24 Jul 06 06:56:52 PM PDT 24 334123500 ps
T1568 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2856636420 Jul 06 06:56:01 PM PDT 24 Jul 06 06:56:50 PM PDT 24 22396292 ps
T1569 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1594364232 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 51256382 ps
T1570 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2630375340 Jul 06 06:57:18 PM PDT 24 Jul 06 06:57:19 PM PDT 24 42491747 ps
T200 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.688804176 Jul 06 06:55:37 PM PDT 24 Jul 06 06:56:24 PM PDT 24 63258653 ps
T1571 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3514548779 Jul 06 06:57:27 PM PDT 24 Jul 06 06:57:29 PM PDT 24 69031986 ps
T1572 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4291989092 Jul 06 06:56:02 PM PDT 24 Jul 06 06:56:50 PM PDT 24 59806040 ps
T1573 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3474539610 Jul 06 06:55:47 PM PDT 24 Jul 06 06:56:37 PM PDT 24 21541197 ps
T178 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3417048843 Jul 06 06:56:05 PM PDT 24 Jul 06 06:56:54 PM PDT 24 140783024 ps
T1574 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3429459117 Jul 06 06:55:56 PM PDT 24 Jul 06 06:56:47 PM PDT 24 58531614 ps
T1575 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2617157039 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 44776839 ps
T1576 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.840524527 Jul 06 06:55:55 PM PDT 24 Jul 06 06:56:46 PM PDT 24 50875808 ps
T1577 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1092662699 Jul 06 06:55:56 PM PDT 24 Jul 06 06:56:46 PM PDT 24 26057379 ps
T201 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2624477778 Jul 06 06:55:48 PM PDT 24 Jul 06 06:56:39 PM PDT 24 42235093 ps
T1578 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1928709248 Jul 06 06:56:56 PM PDT 24 Jul 06 06:57:10 PM PDT 24 40402611 ps
T1579 /workspace/coverage/cover_reg_top/19.i2c_intr_test.335522612 Jul 06 06:57:27 PM PDT 24 Jul 06 06:57:29 PM PDT 24 17644769 ps
T1580 /workspace/coverage/cover_reg_top/28.i2c_intr_test.4065902944 Jul 06 06:57:25 PM PDT 24 Jul 06 06:57:27 PM PDT 24 24649288 ps
T1581 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2008422468 Jul 06 06:55:52 PM PDT 24 Jul 06 06:56:43 PM PDT 24 174478958 ps
T1582 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2879353979 Jul 06 06:55:46 PM PDT 24 Jul 06 06:56:37 PM PDT 24 168172463 ps
T202 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.516530548 Jul 06 06:56:13 PM PDT 24 Jul 06 06:56:57 PM PDT 24 147403900 ps
T1583 /workspace/coverage/cover_reg_top/29.i2c_intr_test.595298861 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 25456347 ps
T1584 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1088207487 Jul 06 06:56:06 PM PDT 24 Jul 06 06:56:52 PM PDT 24 26371987 ps
T1585 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3858446974 Jul 06 06:55:44 PM PDT 24 Jul 06 06:56:37 PM PDT 24 187815304 ps
T1586 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3033675351 Jul 06 06:57:14 PM PDT 24 Jul 06 06:57:15 PM PDT 24 16243159 ps
T1587 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1455756290 Jul 06 06:57:20 PM PDT 24 Jul 06 06:57:22 PM PDT 24 410369002 ps
T1588 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2865340199 Jul 06 06:55:49 PM PDT 24 Jul 06 06:56:40 PM PDT 24 248943238 ps
T1589 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3664927984 Jul 06 06:55:55 PM PDT 24 Jul 06 06:56:45 PM PDT 24 410886436 ps
T1590 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.263631629 Jul 06 06:55:47 PM PDT 24 Jul 06 06:56:37 PM PDT 24 37236366 ps
T1591 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1018574415 Jul 06 06:55:55 PM PDT 24 Jul 06 06:56:46 PM PDT 24 18462452 ps
T179 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.50437383 Jul 06 06:56:44 PM PDT 24 Jul 06 06:57:10 PM PDT 24 88618098 ps
T1592 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.896644516 Jul 06 06:56:06 PM PDT 24 Jul 06 06:56:52 PM PDT 24 42102114 ps
T1593 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3841028925 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 41277168 ps
T1594 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4258798770 Jul 06 06:57:20 PM PDT 24 Jul 06 06:57:22 PM PDT 24 44208904 ps
T1595 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3524985701 Jul 06 06:57:25 PM PDT 24 Jul 06 06:57:28 PM PDT 24 51628418 ps
T1596 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1663554672 Jul 06 06:57:20 PM PDT 24 Jul 06 06:57:22 PM PDT 24 82257656 ps
T1597 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3213926138 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 17793950 ps
T1598 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1648519845 Jul 06 06:56:07 PM PDT 24 Jul 06 06:56:53 PM PDT 24 82184714 ps
T1599 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3474939591 Jul 06 06:55:45 PM PDT 24 Jul 06 06:56:38 PM PDT 24 238885648 ps
T1600 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1437153716 Jul 06 06:56:01 PM PDT 24 Jul 06 06:56:50 PM PDT 24 45845522 ps
T1601 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4128027153 Jul 06 06:56:07 PM PDT 24 Jul 06 06:56:52 PM PDT 24 34880018 ps
T1602 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2726972744 Jul 06 06:56:13 PM PDT 24 Jul 06 06:57:00 PM PDT 24 49515282 ps
T1603 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3512209510 Jul 06 06:56:00 PM PDT 24 Jul 06 06:56:50 PM PDT 24 63148734 ps
T1604 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2701995329 Jul 06 06:56:07 PM PDT 24 Jul 06 06:56:52 PM PDT 24 168421211 ps
T1605 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3259288024 Jul 06 06:57:30 PM PDT 24 Jul 06 06:57:32 PM PDT 24 14953953 ps
T185 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1028531007 Jul 06 06:56:54 PM PDT 24 Jul 06 06:57:11 PM PDT 24 48536673 ps
T1606 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1788962539 Jul 06 06:57:29 PM PDT 24 Jul 06 06:57:31 PM PDT 24 18348488 ps
T1607 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2816782564 Jul 06 06:56:41 PM PDT 24 Jul 06 06:57:08 PM PDT 24 32273851 ps
T1608 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4067031680 Jul 06 06:56:25 PM PDT 24 Jul 06 06:57:04 PM PDT 24 62375886 ps
T203 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1446114903 Jul 06 06:56:08 PM PDT 24 Jul 06 06:56:54 PM PDT 24 25295628 ps
T1609 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1961673273 Jul 06 06:57:18 PM PDT 24 Jul 06 06:57:21 PM PDT 24 583021561 ps
T1610 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2631291680 Jul 06 06:56:08 PM PDT 24 Jul 06 06:56:55 PM PDT 24 40987595 ps
T1611 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1297566973 Jul 06 06:57:11 PM PDT 24 Jul 06 06:57:14 PM PDT 24 93970899 ps
T1612 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1709299462 Jul 06 06:57:17 PM PDT 24 Jul 06 06:57:18 PM PDT 24 94071322 ps
T204 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2916162046 Jul 06 06:55:39 PM PDT 24 Jul 06 06:56:29 PM PDT 24 121532123 ps
T173 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1384452918 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:27 PM PDT 24 79875636 ps
T1613 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.337236551 Jul 06 06:57:24 PM PDT 24 Jul 06 06:57:26 PM PDT 24 76282059 ps
T180 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1264355990 Jul 06 06:56:06 PM PDT 24 Jul 06 06:56:54 PM PDT 24 578435924 ps
T175 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.568977829 Jul 06 06:57:19 PM PDT 24 Jul 06 06:57:21 PM PDT 24 277506926 ps
T1614 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.699583685 Jul 06 06:57:13 PM PDT 24 Jul 06 06:57:15 PM PDT 24 429580575 ps
T1615 /workspace/coverage/cover_reg_top/13.i2c_intr_test.939328545 Jul 06 06:56:50 PM PDT 24 Jul 06 06:57:09 PM PDT 24 38839686 ps
T1616 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3205290560 Jul 06 06:56:12 PM PDT 24 Jul 06 06:56:56 PM PDT 24 56524539 ps
T1617 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2387085151 Jul 06 06:56:14 PM PDT 24 Jul 06 06:56:58 PM PDT 24 38237596 ps
T1618 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1409732953 Jul 06 06:57:05 PM PDT 24 Jul 06 06:57:12 PM PDT 24 33099004 ps
T1619 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2977118969 Jul 06 06:57:28 PM PDT 24 Jul 06 06:57:30 PM PDT 24 67815394 ps
T1620 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.870867223 Jul 06 06:55:47 PM PDT 24 Jul 06 06:56:37 PM PDT 24 44138373 ps
T1621 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.533299309 Jul 06 06:56:12 PM PDT 24 Jul 06 06:56:57 PM PDT 24 145008483 ps
T1622 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2849006496 Jul 06 06:55:45 PM PDT 24 Jul 06 06:56:37 PM PDT 24 389959911 ps
T1623 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1697026437 Jul 06 06:56:04 PM PDT 24 Jul 06 06:56:52 PM PDT 24 18085135 ps
T1624 /workspace/coverage/cover_reg_top/48.i2c_intr_test.143100641 Jul 06 06:57:31 PM PDT 24 Jul 06 06:57:33 PM PDT 24 37849592 ps
T1625 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2745741344 Jul 06 06:57:20 PM PDT 24 Jul 06 06:57:22 PM PDT 24 205759202 ps
T176 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2124831629 Jul 06 06:56:01 PM PDT 24 Jul 06 06:56:50 PM PDT 24 488273778 ps
T1626 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3486247705 Jul 06 06:57:05 PM PDT 24 Jul 06 06:57:12 PM PDT 24 48593945 ps
T1627 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.285395164 Jul 06 06:56:08 PM PDT 24 Jul 06 06:56:54 PM PDT 24 296526353 ps
T1628 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.551417109 Jul 06 06:56:55 PM PDT 24 Jul 06 06:57:10 PM PDT 24 93596136 ps
T1629 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2215613617 Jul 06 06:55:43 PM PDT 24 Jul 06 06:56:32 PM PDT 24 33664800 ps
T1630 /workspace/coverage/cover_reg_top/23.i2c_intr_test.4134096748 Jul 06 06:57:26 PM PDT 24 Jul 06 06:57:28 PM PDT 24 151146024 ps
T1631 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2952606257 Jul 06 06:57:19 PM PDT 24 Jul 06 06:57:21 PM PDT 24 34334568 ps
T1632 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2387699389 Jul 06 06:56:12 PM PDT 24 Jul 06 06:56:57 PM PDT 24 36569984 ps

Test location /workspace/coverage/default/20.i2c_host_fifo_full.517477362
Short name T1
Test name
Test status
Simulation time 2462013234 ps
CPU time 176.59 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:45:08 PM PDT 24
Peak memory 750276 kb
Host smart-b5f0e42c-687f-4b10-9697-f58ae70ee82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517477362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.517477362
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3405388489
Short name T14
Test name
Test status
Simulation time 7092523187 ps
CPU time 10.2 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:19 PM PDT 24
Peak memory 213728 kb
Host smart-62370d97-4a04-4ea2-b0e4-c2856bbae25e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405388489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3405388489
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3062260748
Short name T29
Test name
Test status
Simulation time 5685961487 ps
CPU time 7.52 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:30 PM PDT 24
Peak memory 221284 kb
Host smart-71ff8023-5a24-4105-85cb-386a026cd586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062260748 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3062260748
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3939986413
Short name T42
Test name
Test status
Simulation time 153782508059 ps
CPU time 959.02 seconds
Started Jul 06 05:42:19 PM PDT 24
Finished Jul 06 05:58:18 PM PDT 24
Peak memory 1549556 kb
Host smart-23df0528-a28b-4dfb-995a-47728a039adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939986413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3939986413
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2945849928
Short name T155
Test name
Test status
Simulation time 35675720 ps
CPU time 1.59 seconds
Started Jul 06 06:55:56 PM PDT 24
Finished Jul 06 06:56:47 PM PDT 24
Peak memory 212724 kb
Host smart-30de6ecb-f07e-47ee-b512-889f2415d519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945849928 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2945849928
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.564333199
Short name T48
Test name
Test status
Simulation time 18321500545 ps
CPU time 1140.81 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 06:05:35 PM PDT 24
Peak memory 3380328 kb
Host smart-68b635cb-aeab-43b2-a351-330fa053e4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564333199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.564333199
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.356569939
Short name T12
Test name
Test status
Simulation time 521390071 ps
CPU time 1.21 seconds
Started Jul 06 05:38:42 PM PDT 24
Finished Jul 06 05:38:44 PM PDT 24
Peak memory 204988 kb
Host smart-6705883b-cf78-4ed4-b1ff-877c307caf6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356569939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.356569939
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2761080052
Short name T85
Test name
Test status
Simulation time 28526458 ps
CPU time 0.77 seconds
Started Jul 06 06:55:50 PM PDT 24
Finished Jul 06 06:56:41 PM PDT 24
Peak memory 204256 kb
Host smart-578b9a0a-802d-469e-8910-42a28e3709f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761080052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2761080052
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3305031700
Short name T158
Test name
Test status
Simulation time 67112170 ps
CPU time 0.97 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:38:30 PM PDT 24
Peak memory 223276 kb
Host smart-c4af0e4f-5c15-4d72-a717-88af237abf59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305031700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3305031700
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/27.i2c_host_override.3453665100
Short name T68
Test name
Test status
Simulation time 28009080 ps
CPU time 0.69 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:27 PM PDT 24
Peak memory 204716 kb
Host smart-04dc4b1c-2608-4e32-ba67-0c0e84e66330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453665100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3453665100
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1126576793
Short name T34
Test name
Test status
Simulation time 2516532757 ps
CPU time 3.02 seconds
Started Jul 06 05:44:09 PM PDT 24
Finished Jul 06 05:44:12 PM PDT 24
Peak memory 205132 kb
Host smart-40c76531-7964-424b-9d01-57778603b547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126576793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1126576793
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3795736613
Short name T74
Test name
Test status
Simulation time 46592441112 ps
CPU time 277.64 seconds
Started Jul 06 05:37:51 PM PDT 24
Finished Jul 06 05:42:29 PM PDT 24
Peak memory 822240 kb
Host smart-3bd0d590-4ee9-471c-8fd4-29de09ea5343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795736613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3795736613
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2212929718
Short name T6
Test name
Test status
Simulation time 21296293195 ps
CPU time 95.68 seconds
Started Jul 06 05:47:03 PM PDT 24
Finished Jul 06 05:48:39 PM PDT 24
Peak memory 1273944 kb
Host smart-83274fc0-66f8-425a-9239-bd74f8f22ed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212929718 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2212929718
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.1361795112
Short name T428
Test name
Test status
Simulation time 154814193 ps
CPU time 2.65 seconds
Started Jul 06 05:38:04 PM PDT 24
Finished Jul 06 05:38:07 PM PDT 24
Peak memory 205048 kb
Host smart-522b3335-30bb-4a92-8234-8e585cc52c67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361795112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.1361795112
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2145439219
Short name T88
Test name
Test status
Simulation time 300560895 ps
CPU time 1.51 seconds
Started Jul 06 06:57:22 PM PDT 24
Finished Jul 06 06:57:24 PM PDT 24
Peak memory 204588 kb
Host smart-c6a9f962-1757-413a-9964-4b7a54e93d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145439219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2145439219
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.373461502
Short name T267
Test name
Test status
Simulation time 6538447122 ps
CPU time 6.84 seconds
Started Jul 06 05:45:27 PM PDT 24
Finished Jul 06 05:45:34 PM PDT 24
Peak memory 213404 kb
Host smart-c647603e-5944-4944-9842-0319099274b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373461502 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.373461502
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2612375497
Short name T55
Test name
Test status
Simulation time 163684311 ps
CPU time 1.22 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:46:41 PM PDT 24
Peak memory 204776 kb
Host smart-9fd1804a-b1ab-4d15-b8f1-427da230d2a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612375497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2612375497
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1654671799
Short name T26
Test name
Test status
Simulation time 3505686742 ps
CPU time 4.12 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:57 PM PDT 24
Peak memory 213260 kb
Host smart-b9951842-061d-4752-96f0-1a08086d330e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654671799 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1654671799
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.553428571
Short name T260
Test name
Test status
Simulation time 11292395583 ps
CPU time 765.75 seconds
Started Jul 06 05:38:35 PM PDT 24
Finished Jul 06 05:51:21 PM PDT 24
Peak memory 1275280 kb
Host smart-d7319764-2ce3-41f2-99d1-3afc07c0841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553428571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.553428571
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.665272895
Short name T38
Test name
Test status
Simulation time 1297481087 ps
CPU time 28.4 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:38 PM PDT 24
Peak memory 360172 kb
Host smart-5afe8443-9679-49e3-9b1a-146dce083f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665272895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.665272895
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1377323834
Short name T370
Test name
Test status
Simulation time 36439041 ps
CPU time 0.62 seconds
Started Jul 06 05:40:31 PM PDT 24
Finished Jul 06 05:40:32 PM PDT 24
Peak memory 204636 kb
Host smart-443bf83a-3235-4e59-8f0a-7b7aef9a1095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377323834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1377323834
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3715012459
Short name T35
Test name
Test status
Simulation time 164356887 ps
CPU time 4.28 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:07 PM PDT 24
Peak memory 205020 kb
Host smart-bdb72ce4-ec4a-4857-a835-2865873f8e7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715012459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3715012459
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.415522541
Short name T561
Test name
Test status
Simulation time 23203228529 ps
CPU time 941.66 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:53:51 PM PDT 24
Peak memory 205072 kb
Host smart-1a638b67-3107-48f1-aa2c-de980efb2441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415522541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.415522541
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.554062445
Short name T168
Test name
Test status
Simulation time 95284121 ps
CPU time 2.13 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:27 PM PDT 24
Peak memory 204492 kb
Host smart-59c85e57-4590-4234-ac61-2b873cfba4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554062445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.554062445
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1548882475
Short name T43
Test name
Test status
Simulation time 19399868592 ps
CPU time 204.76 seconds
Started Jul 06 05:39:37 PM PDT 24
Finished Jul 06 05:43:02 PM PDT 24
Peak memory 1495636 kb
Host smart-d778248a-c9e1-4848-851f-9f1c294b9408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548882475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1548882475
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.335439152
Short name T109
Test name
Test status
Simulation time 25107225364 ps
CPU time 742.21 seconds
Started Jul 06 05:39:26 PM PDT 24
Finished Jul 06 05:51:48 PM PDT 24
Peak memory 1950344 kb
Host smart-bd2b7386-fdd1-4ce4-9692-9a767a4fb7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335439152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.335439152
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1792531607
Short name T170
Test name
Test status
Simulation time 578400283 ps
CPU time 2.48 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:28 PM PDT 24
Peak memory 204516 kb
Host smart-10a6b1e2-5675-4772-9a2b-c0beecd230f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792531607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1792531607
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3108114516
Short name T108
Test name
Test status
Simulation time 11708850641 ps
CPU time 160.43 seconds
Started Jul 06 05:40:08 PM PDT 24
Finished Jul 06 05:42:49 PM PDT 24
Peak memory 724820 kb
Host smart-fa9b67ef-8ae9-4c9c-ae61-c6a4be7c1c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108114516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3108114516
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.1817615964
Short name T191
Test name
Test status
Simulation time 1591309039 ps
CPU time 2.43 seconds
Started Jul 06 05:40:13 PM PDT 24
Finished Jul 06 05:40:16 PM PDT 24
Peak memory 205084 kb
Host smart-21e0f5d1-7ef8-4517-bd11-2c7e702ce6c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817615964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.1817615964
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.4248911975
Short name T243
Test name
Test status
Simulation time 370440802 ps
CPU time 1.29 seconds
Started Jul 06 05:44:50 PM PDT 24
Finished Jul 06 05:44:52 PM PDT 24
Peak memory 205028 kb
Host smart-0b16afc4-c2ad-474b-b48b-510ebdbb60a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248911975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.4248911975
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2125699936
Short name T140
Test name
Test status
Simulation time 209539499 ps
CPU time 1.26 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:42:49 PM PDT 24
Peak memory 204796 kb
Host smart-9864420c-14ab-4156-911d-a4d190df04cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125699936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2125699936
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3388175162
Short name T208
Test name
Test status
Simulation time 106068617 ps
CPU time 1.2 seconds
Started Jul 06 06:55:44 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204564 kb
Host smart-f22bbd61-5954-4a7c-940c-4acd4d086e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388175162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3388175162
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.447441522
Short name T57
Test name
Test status
Simulation time 176899045 ps
CPU time 0.91 seconds
Started Jul 06 05:37:48 PM PDT 24
Finished Jul 06 05:37:49 PM PDT 24
Peak memory 204768 kb
Host smart-bacb76a4-e7cb-4821-884e-d78ed122c777
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447441522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.447441522
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_override.3795832447
Short name T225
Test name
Test status
Simulation time 83306552 ps
CPU time 0.66 seconds
Started Jul 06 05:37:51 PM PDT 24
Finished Jul 06 05:37:52 PM PDT 24
Peak memory 204780 kb
Host smart-6fdb42d0-142e-4e9e-ab5e-26002daeb370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795832447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3795832447
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1175000952
Short name T661
Test name
Test status
Simulation time 1675586670 ps
CPU time 8.39 seconds
Started Jul 06 05:45:53 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 213436 kb
Host smart-a77daddb-614e-4039-b3c7-2a0797e37f09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175000952 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1175000952
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.1877857528
Short name T1226
Test name
Test status
Simulation time 10508007867 ps
CPU time 176.89 seconds
Started Jul 06 05:43:40 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 745060 kb
Host smart-1aee22bd-1ef0-4e8a-bf26-b21619a3a513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877857528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1877857528
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.4159778260
Short name T67
Test name
Test status
Simulation time 7653455206 ps
CPU time 100.45 seconds
Started Jul 06 05:41:29 PM PDT 24
Finished Jul 06 05:43:09 PM PDT 24
Peak memory 445572 kb
Host smart-6ee42d91-7cb0-4587-bd81-95ad9e9fb286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159778260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.4159778260
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_perf.693992780
Short name T58
Test name
Test status
Simulation time 12599531128 ps
CPU time 778.08 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:54:06 PM PDT 24
Peak memory 2092272 kb
Host smart-22c3d891-36a0-4d13-af11-80f92f10eccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693992780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.693992780
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1716544573
Short name T251
Test name
Test status
Simulation time 2189654021 ps
CPU time 25.88 seconds
Started Jul 06 05:37:51 PM PDT 24
Finished Jul 06 05:38:18 PM PDT 24
Peak memory 213204 kb
Host smart-0e23cc3a-8130-4526-80de-64698944f1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716544573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1716544573
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2127601599
Short name T30
Test name
Test status
Simulation time 148380323 ps
CPU time 1.11 seconds
Started Jul 06 05:37:59 PM PDT 24
Finished Jul 06 05:38:01 PM PDT 24
Peak memory 217168 kb
Host smart-298b6d9b-273e-41c5-b294-e14c4fd52d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127601599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2127601599
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.2049307067
Short name T296
Test name
Test status
Simulation time 208553035 ps
CPU time 1.34 seconds
Started Jul 06 05:38:13 PM PDT 24
Finished Jul 06 05:38:14 PM PDT 24
Peak memory 204788 kb
Host smart-95fd6835-1242-499a-b5d1-3129654e66d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049307067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.2049307067
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.794893371
Short name T235
Test name
Test status
Simulation time 2226642090 ps
CPU time 6.83 seconds
Started Jul 06 05:40:13 PM PDT 24
Finished Jul 06 05:40:20 PM PDT 24
Peak memory 205136 kb
Host smart-d40b253a-9c7f-409c-a22f-70cac5146e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794893371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.794893371
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.241312593
Short name T246
Test name
Test status
Simulation time 2405045209 ps
CPU time 13.67 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:41:37 PM PDT 24
Peak memory 213308 kb
Host smart-ee8d1390-f2e0-4062-983d-cde99a8b5c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241312593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.241312593
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2571271188
Short name T221
Test name
Test status
Simulation time 3778554768 ps
CPU time 95.69 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:43:35 PM PDT 24
Peak memory 445080 kb
Host smart-49de050d-7962-4563-b8f9-0bc6a2951dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571271188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2571271188
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.260329699
Short name T227
Test name
Test status
Simulation time 3691189735 ps
CPU time 36.49 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:45:59 PM PDT 24
Peak memory 205020 kb
Host smart-f94b9642-7b12-4f87-a699-9e733e0699e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260329699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.260329699
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1066479334
Short name T89
Test name
Test status
Simulation time 351173628 ps
CPU time 1.53 seconds
Started Jul 06 06:55:47 PM PDT 24
Finished Jul 06 06:56:38 PM PDT 24
Peak memory 204580 kb
Host smart-5ab4dcad-c806-4523-9640-5d4bb757aa2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066479334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1066479334
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1799054496
Short name T177
Test name
Test status
Simulation time 152770526 ps
CPU time 2.46 seconds
Started Jul 06 06:55:39 PM PDT 24
Finished Jul 06 06:56:29 PM PDT 24
Peak memory 204480 kb
Host smart-4cd3de8b-b8ce-4f4c-8380-0aeef17e9f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799054496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1799054496
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4287742378
Short name T174
Test name
Test status
Simulation time 632811489 ps
CPU time 1.46 seconds
Started Jul 06 06:56:24 PM PDT 24
Finished Jul 06 06:57:03 PM PDT 24
Peak memory 204584 kb
Host smart-9ba31a4e-f307-4c3e-9a07-6dd9d9cac96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287742378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4287742378
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1028531007
Short name T185
Test name
Test status
Simulation time 48536673 ps
CPU time 1.33 seconds
Started Jul 06 06:56:54 PM PDT 24
Finished Jul 06 06:57:11 PM PDT 24
Peak memory 204584 kb
Host smart-b2f29185-d340-43fb-85b2-78c2b0ab51fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028531007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1028531007
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1384452918
Short name T173
Test name
Test status
Simulation time 79875636 ps
CPU time 2.18 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:27 PM PDT 24
Peak memory 204556 kb
Host smart-97533ec6-3882-4d3b-b0ae-8158085f6bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384452918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1384452918
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.1676571123
Short name T46
Test name
Test status
Simulation time 12306004797 ps
CPU time 609.47 seconds
Started Jul 06 05:44:52 PM PDT 24
Finished Jul 06 05:55:01 PM PDT 24
Peak memory 2515268 kb
Host smart-0300b4d0-465c-4c01-8580-dc949335e8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676571123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1676571123
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2879353979
Short name T1582
Test name
Test status
Simulation time 168172463 ps
CPU time 1.22 seconds
Started Jul 06 06:55:46 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204492 kb
Host smart-721a6ba0-c386-4bd7-b43d-4581ff5a7913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879353979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2879353979
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2916162046
Short name T204
Test name
Test status
Simulation time 121532123 ps
CPU time 2.46 seconds
Started Jul 06 06:55:39 PM PDT 24
Finished Jul 06 06:56:29 PM PDT 24
Peak memory 204424 kb
Host smart-3b08c5e5-57bc-41db-86c5-aa8659d234ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916162046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2916162046
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2287898913
Short name T1540
Test name
Test status
Simulation time 39713700 ps
CPU time 0.76 seconds
Started Jul 06 06:55:39 PM PDT 24
Finished Jul 06 06:56:27 PM PDT 24
Peak memory 204224 kb
Host smart-10bc75e0-56df-4051-bb56-d29be7000652
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287898913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2287898913
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2449188490
Short name T92
Test name
Test status
Simulation time 29101459 ps
CPU time 0.81 seconds
Started Jul 06 06:55:45 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204428 kb
Host smart-1fad2f43-054a-4964-a2f4-f30e86c65f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449188490 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2449188490
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.688804176
Short name T200
Test name
Test status
Simulation time 63258653 ps
CPU time 0.79 seconds
Started Jul 06 06:55:37 PM PDT 24
Finished Jul 06 06:56:24 PM PDT 24
Peak memory 204228 kb
Host smart-56ae02b9-79df-4296-a15f-ea029be3e369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688804176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.688804176
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3255726485
Short name T1531
Test name
Test status
Simulation time 15456744 ps
CPU time 0.71 seconds
Started Jul 06 06:55:39 PM PDT 24
Finished Jul 06 06:56:27 PM PDT 24
Peak memory 203984 kb
Host smart-64eab8da-94d4-4245-9b6f-4e9eaeffb278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255726485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3255726485
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3777528185
Short name T1546
Test name
Test status
Simulation time 96644156 ps
CPU time 0.85 seconds
Started Jul 06 06:55:45 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204352 kb
Host smart-14de67de-59d4-448e-8f7e-faeb84bec7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777528185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3777528185
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.876043563
Short name T165
Test name
Test status
Simulation time 31777353 ps
CPU time 1.65 seconds
Started Jul 06 06:55:39 PM PDT 24
Finished Jul 06 06:56:28 PM PDT 24
Peak memory 204588 kb
Host smart-6644b170-9331-4171-98fb-121ce2d77fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876043563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.876043563
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3858446974
Short name T1585
Test name
Test status
Simulation time 187815304 ps
CPU time 1.88 seconds
Started Jul 06 06:55:44 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204516 kb
Host smart-5fc5f9e3-858b-4a4a-a1e1-7c5a7b5adff9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858446974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3858446974
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2948367021
Short name T91
Test name
Test status
Simulation time 474550482 ps
CPU time 3 seconds
Started Jul 06 06:55:44 PM PDT 24
Finished Jul 06 06:56:38 PM PDT 24
Peak memory 204528 kb
Host smart-50c25022-e161-45f4-853d-f14f22982bdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948367021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2948367021
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2299318858
Short name T131
Test name
Test status
Simulation time 16989376 ps
CPU time 0.74 seconds
Started Jul 06 06:55:46 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204324 kb
Host smart-2dc7a420-08b9-4a22-a72f-e069cf3a5593
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299318858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2299318858
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.263631629
Short name T1590
Test name
Test status
Simulation time 37236366 ps
CPU time 0.93 seconds
Started Jul 06 06:55:47 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204412 kb
Host smart-2d0f3200-f794-4008-846c-6b7ee495b9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263631629 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.263631629
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2215613617
Short name T1629
Test name
Test status
Simulation time 33664800 ps
CPU time 0.67 seconds
Started Jul 06 06:55:43 PM PDT 24
Finished Jul 06 06:56:32 PM PDT 24
Peak memory 204220 kb
Host smart-5dfc02b9-a64c-4c24-9168-b6007e287933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215613617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2215613617
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.774577423
Short name T1561
Test name
Test status
Simulation time 61274171 ps
CPU time 0.72 seconds
Started Jul 06 06:55:46 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204288 kb
Host smart-f255160a-acab-4182-8b92-17124775a8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774577423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.774577423
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2849006496
Short name T1622
Test name
Test status
Simulation time 389959911 ps
CPU time 2 seconds
Started Jul 06 06:55:45 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204568 kb
Host smart-62294296-5f34-44dd-9336-af5a7fd3aaee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849006496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2849006496
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2693139015
Short name T167
Test name
Test status
Simulation time 67816153 ps
CPU time 1.42 seconds
Started Jul 06 06:55:44 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204536 kb
Host smart-9cd9cb2b-bbda-4951-b16a-43a0a70ec776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693139015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2693139015
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.533299309
Short name T1621
Test name
Test status
Simulation time 145008483 ps
CPU time 1.01 seconds
Started Jul 06 06:56:12 PM PDT 24
Finished Jul 06 06:56:57 PM PDT 24
Peak memory 204416 kb
Host smart-4f5160ac-30a3-4986-b5f4-0840c6ea0809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533299309 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.533299309
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.516530548
Short name T202
Test name
Test status
Simulation time 147403900 ps
CPU time 0.77 seconds
Started Jul 06 06:56:13 PM PDT 24
Finished Jul 06 06:56:57 PM PDT 24
Peak memory 204284 kb
Host smart-98e2809d-83e3-4f99-bc2f-0c875a4057b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516530548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.516530548
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2387085151
Short name T1617
Test name
Test status
Simulation time 38237596 ps
CPU time 0.68 seconds
Started Jul 06 06:56:14 PM PDT 24
Finished Jul 06 06:56:58 PM PDT 24
Peak memory 204256 kb
Host smart-3b375bfc-eddd-41f2-a846-9b4a3ba9eb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387085151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2387085151
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1125702941
Short name T205
Test name
Test status
Simulation time 394777165 ps
CPU time 0.93 seconds
Started Jul 06 06:56:12 PM PDT 24
Finished Jul 06 06:56:57 PM PDT 24
Peak memory 204336 kb
Host smart-465651c2-8159-4ea8-85fa-330a7570e60e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125702941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1125702941
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2726972744
Short name T1602
Test name
Test status
Simulation time 49515282 ps
CPU time 2.57 seconds
Started Jul 06 06:56:13 PM PDT 24
Finished Jul 06 06:57:00 PM PDT 24
Peak memory 212788 kb
Host smart-d570dd71-f17a-4360-a35d-a5a6b1a7422e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726972744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2726972744
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1565492782
Short name T157
Test name
Test status
Simulation time 238818270 ps
CPU time 1.49 seconds
Started Jul 06 06:56:13 PM PDT 24
Finished Jul 06 06:56:58 PM PDT 24
Peak memory 204488 kb
Host smart-609fa9fc-7fb7-42fc-a3ac-5a4c62a1cd91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565492782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1565492782
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1373849965
Short name T166
Test name
Test status
Simulation time 23140645 ps
CPU time 1 seconds
Started Jul 06 06:56:19 PM PDT 24
Finished Jul 06 06:57:00 PM PDT 24
Peak memory 204384 kb
Host smart-ff62783a-20e2-4ef5-b49c-4c92c602255c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373849965 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1373849965
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1571296854
Short name T207
Test name
Test status
Simulation time 33523945 ps
CPU time 0.7 seconds
Started Jul 06 06:56:14 PM PDT 24
Finished Jul 06 06:56:58 PM PDT 24
Peak memory 204260 kb
Host smart-a9218c75-2304-4d50-8211-bc73f3d98dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571296854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1571296854
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3205290560
Short name T1616
Test name
Test status
Simulation time 56524539 ps
CPU time 0.67 seconds
Started Jul 06 06:56:12 PM PDT 24
Finished Jul 06 06:56:56 PM PDT 24
Peak memory 204232 kb
Host smart-aa04377c-89e6-463d-9532-051669dd4518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205290560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3205290560
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2203886823
Short name T209
Test name
Test status
Simulation time 52575112 ps
CPU time 1.11 seconds
Started Jul 06 06:56:17 PM PDT 24
Finished Jul 06 06:56:59 PM PDT 24
Peak memory 204564 kb
Host smart-4141c5e2-f1be-426d-b827-c8539f35ca55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203886823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2203886823
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3785641215
Short name T172
Test name
Test status
Simulation time 26292076 ps
CPU time 1.2 seconds
Started Jul 06 06:56:12 PM PDT 24
Finished Jul 06 06:56:57 PM PDT 24
Peak memory 204636 kb
Host smart-8935c3a7-b91c-47c1-8b53-1e6bab3bbcac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785641215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3785641215
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1019343191
Short name T87
Test name
Test status
Simulation time 80434651 ps
CPU time 1.42 seconds
Started Jul 06 06:56:11 PM PDT 24
Finished Jul 06 06:56:58 PM PDT 24
Peak memory 204524 kb
Host smart-a6658a76-df54-4d01-baf6-66755f1e34ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019343191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1019343191
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3724214878
Short name T1555
Test name
Test status
Simulation time 84543591 ps
CPU time 0.82 seconds
Started Jul 06 06:56:45 PM PDT 24
Finished Jul 06 06:57:09 PM PDT 24
Peak memory 204040 kb
Host smart-ba3d09be-df7f-431d-9571-30c573a00539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724214878 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3724214878
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.860805274
Short name T197
Test name
Test status
Simulation time 48154736 ps
CPU time 0.7 seconds
Started Jul 06 06:56:28 PM PDT 24
Finished Jul 06 06:57:03 PM PDT 24
Peak memory 204232 kb
Host smart-c1aae167-f35a-4fa0-8913-20e7a714d7a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860805274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.860805274
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.137209297
Short name T1547
Test name
Test status
Simulation time 14458570 ps
CPU time 0.69 seconds
Started Jul 06 06:56:29 PM PDT 24
Finished Jul 06 06:57:04 PM PDT 24
Peak memory 204284 kb
Host smart-246ac1e7-3964-4897-9db5-ba31035b70bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137209297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.137209297
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2816782564
Short name T1607
Test name
Test status
Simulation time 32273851 ps
CPU time 0.84 seconds
Started Jul 06 06:56:41 PM PDT 24
Finished Jul 06 06:57:08 PM PDT 24
Peak memory 204356 kb
Host smart-8b5dd8f1-70f5-4797-a117-65f9ae2baeb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816782564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2816782564
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4067031680
Short name T1608
Test name
Test status
Simulation time 62375886 ps
CPU time 2.2 seconds
Started Jul 06 06:56:25 PM PDT 24
Finished Jul 06 06:57:04 PM PDT 24
Peak memory 204520 kb
Host smart-823dd801-ee8e-4e04-a586-11d569106423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067031680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4067031680
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.551417109
Short name T1628
Test name
Test status
Simulation time 93596136 ps
CPU time 0.93 seconds
Started Jul 06 06:56:55 PM PDT 24
Finished Jul 06 06:57:10 PM PDT 24
Peak memory 204440 kb
Host smart-786d9d20-1a5d-41e0-9842-043306c8fb61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551417109 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.551417109
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1928709248
Short name T1578
Test name
Test status
Simulation time 40402611 ps
CPU time 0.77 seconds
Started Jul 06 06:56:56 PM PDT 24
Finished Jul 06 06:57:10 PM PDT 24
Peak memory 204304 kb
Host smart-13cbe251-a0a2-4365-bca3-3bc2ce44416c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928709248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1928709248
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.939328545
Short name T1615
Test name
Test status
Simulation time 38839686 ps
CPU time 0.67 seconds
Started Jul 06 06:56:50 PM PDT 24
Finished Jul 06 06:57:09 PM PDT 24
Peak memory 204284 kb
Host smart-d9df0806-2235-45cd-8290-2d2e7ca005ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939328545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.939328545
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1831627149
Short name T210
Test name
Test status
Simulation time 38042905 ps
CPU time 0.91 seconds
Started Jul 06 06:56:55 PM PDT 24
Finished Jul 06 06:57:10 PM PDT 24
Peak memory 204344 kb
Host smart-2f7f1463-3509-4ea6-b727-58f5e3587503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831627149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1831627149
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.399490441
Short name T1566
Test name
Test status
Simulation time 115298892 ps
CPU time 2.78 seconds
Started Jul 06 06:56:44 PM PDT 24
Finished Jul 06 06:57:11 PM PDT 24
Peak memory 204580 kb
Host smart-2908b13d-f1e3-4957-b293-8737ea2fe403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399490441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.399490441
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.50437383
Short name T179
Test name
Test status
Simulation time 88618098 ps
CPU time 2.06 seconds
Started Jul 06 06:56:44 PM PDT 24
Finished Jul 06 06:57:10 PM PDT 24
Peak memory 204348 kb
Host smart-ef03511d-7a6d-4a93-8b10-bda459486b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50437383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.50437383
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.585830466
Short name T171
Test name
Test status
Simulation time 35403202 ps
CPU time 1.65 seconds
Started Jul 06 06:57:06 PM PDT 24
Finished Jul 06 06:57:13 PM PDT 24
Peak memory 220100 kb
Host smart-a3044b3c-9d90-47be-a4b0-49ef4a35cc5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585830466 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.585830466
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.89514388
Short name T198
Test name
Test status
Simulation time 26475812 ps
CPU time 0.84 seconds
Started Jul 06 06:57:05 PM PDT 24
Finished Jul 06 06:57:12 PM PDT 24
Peak memory 204224 kb
Host smart-08ddd959-12a5-4160-bb14-2988b70f959a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89514388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.89514388
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3486247705
Short name T1626
Test name
Test status
Simulation time 48593945 ps
CPU time 0.69 seconds
Started Jul 06 06:57:05 PM PDT 24
Finished Jul 06 06:57:12 PM PDT 24
Peak memory 204276 kb
Host smart-3630b279-f9b9-47c7-afcd-780373ed24ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486247705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3486247705
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1409732953
Short name T1618
Test name
Test status
Simulation time 33099004 ps
CPU time 0.91 seconds
Started Jul 06 06:57:05 PM PDT 24
Finished Jul 06 06:57:12 PM PDT 24
Peak memory 204324 kb
Host smart-ba381f9a-b9ed-439e-8bb0-6b0e51352ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409732953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1409732953
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1235207006
Short name T1548
Test name
Test status
Simulation time 142323888 ps
CPU time 2.09 seconds
Started Jul 06 06:56:56 PM PDT 24
Finished Jul 06 06:57:12 PM PDT 24
Peak memory 204588 kb
Host smart-d6ccea3d-9c2d-4899-bb16-89a90aee1556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235207006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1235207006
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3997194136
Short name T1564
Test name
Test status
Simulation time 68707902 ps
CPU time 1.11 seconds
Started Jul 06 06:57:18 PM PDT 24
Finished Jul 06 06:57:20 PM PDT 24
Peak memory 204656 kb
Host smart-a5d3ffba-a1e1-47bf-8e15-bbca291a3658
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997194136 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3997194136
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3109324317
Short name T199
Test name
Test status
Simulation time 30750295 ps
CPU time 0.73 seconds
Started Jul 06 06:57:11 PM PDT 24
Finished Jul 06 06:57:13 PM PDT 24
Peak memory 204288 kb
Host smart-bc8d0b10-4ade-468b-bdb6-51844c767b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109324317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3109324317
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3033675351
Short name T1586
Test name
Test status
Simulation time 16243159 ps
CPU time 0.67 seconds
Started Jul 06 06:57:14 PM PDT 24
Finished Jul 06 06:57:15 PM PDT 24
Peak memory 204248 kb
Host smart-1ee96a64-fa97-48f3-8542-17e4bd01b200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033675351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3033675351
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.785320712
Short name T1565
Test name
Test status
Simulation time 97427182 ps
CPU time 1.19 seconds
Started Jul 06 06:57:23 PM PDT 24
Finished Jul 06 06:57:25 PM PDT 24
Peak memory 204492 kb
Host smart-d1855852-1a8e-440f-bf9a-09a55bb83a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785320712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.785320712
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1297566973
Short name T1611
Test name
Test status
Simulation time 93970899 ps
CPU time 2.53 seconds
Started Jul 06 06:57:11 PM PDT 24
Finished Jul 06 06:57:14 PM PDT 24
Peak memory 204612 kb
Host smart-55692263-503a-4595-b1b4-302d8c57ed39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297566973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1297566973
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.699583685
Short name T1614
Test name
Test status
Simulation time 429580575 ps
CPU time 1.47 seconds
Started Jul 06 06:57:13 PM PDT 24
Finished Jul 06 06:57:15 PM PDT 24
Peak memory 204612 kb
Host smart-15e5ddb2-5855-4794-aa27-b4c55d6cd5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699583685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.699583685
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1663554672
Short name T1596
Test name
Test status
Simulation time 82257656 ps
CPU time 1.25 seconds
Started Jul 06 06:57:20 PM PDT 24
Finished Jul 06 06:57:22 PM PDT 24
Peak memory 204548 kb
Host smart-e8fe431e-4777-46a2-a98c-9470f7551d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663554672 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1663554672
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.889810263
Short name T1549
Test name
Test status
Simulation time 20027612 ps
CPU time 0.7 seconds
Started Jul 06 06:57:22 PM PDT 24
Finished Jul 06 06:57:24 PM PDT 24
Peak memory 204252 kb
Host smart-0ae29db7-d661-4662-8059-fe4804f1b9f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889810263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.889810263
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1004775804
Short name T1557
Test name
Test status
Simulation time 67453476 ps
CPU time 0.68 seconds
Started Jul 06 06:57:19 PM PDT 24
Finished Jul 06 06:57:21 PM PDT 24
Peak memory 204304 kb
Host smart-f49f4932-7661-4d0c-948b-b6a3736fac6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004775804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1004775804
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4258798770
Short name T1594
Test name
Test status
Simulation time 44208904 ps
CPU time 0.82 seconds
Started Jul 06 06:57:20 PM PDT 24
Finished Jul 06 06:57:22 PM PDT 24
Peak memory 204400 kb
Host smart-c2b36c31-e81b-4c1b-bba3-dbd888e2f8c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258798770 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.4258798770
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2053342426
Short name T195
Test name
Test status
Simulation time 55824517 ps
CPU time 0.67 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204216 kb
Host smart-f83b46fb-9802-49dd-848f-d53a62b113d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053342426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2053342426
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2630375340
Short name T1570
Test name
Test status
Simulation time 42491747 ps
CPU time 0.64 seconds
Started Jul 06 06:57:18 PM PDT 24
Finished Jul 06 06:57:19 PM PDT 24
Peak memory 204336 kb
Host smart-ded688b4-075a-4bee-8eda-7734a69ccf37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630375340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2630375340
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2745741344
Short name T1625
Test name
Test status
Simulation time 205759202 ps
CPU time 0.89 seconds
Started Jul 06 06:57:20 PM PDT 24
Finished Jul 06 06:57:22 PM PDT 24
Peak memory 204328 kb
Host smart-d1d81356-5ca0-47d1-98a1-7c89b1c76a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745741344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2745741344
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1455756290
Short name T1587
Test name
Test status
Simulation time 410369002 ps
CPU time 2.21 seconds
Started Jul 06 06:57:20 PM PDT 24
Finished Jul 06 06:57:22 PM PDT 24
Peak memory 204592 kb
Host smart-2eb9b054-dd5b-4d3d-be20-b2557b114adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455756290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1455756290
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2952606257
Short name T1631
Test name
Test status
Simulation time 34334568 ps
CPU time 0.96 seconds
Started Jul 06 06:57:19 PM PDT 24
Finished Jul 06 06:57:21 PM PDT 24
Peak memory 204416 kb
Host smart-2d5f2c0c-f4c7-4d5e-9f82-26bb50ba0be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952606257 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2952606257
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2235471095
Short name T194
Test name
Test status
Simulation time 25998144 ps
CPU time 0.76 seconds
Started Jul 06 06:57:22 PM PDT 24
Finished Jul 06 06:57:24 PM PDT 24
Peak memory 204244 kb
Host smart-0cf93a45-c7d1-441d-9668-1ce20da4f628
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235471095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2235471095
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2769720340
Short name T1545
Test name
Test status
Simulation time 18260863 ps
CPU time 0.7 seconds
Started Jul 06 06:57:18 PM PDT 24
Finished Jul 06 06:57:20 PM PDT 24
Peak memory 204304 kb
Host smart-a05bfb26-bc0c-484a-90fb-60022d54cf92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769720340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2769720340
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1709299462
Short name T1612
Test name
Test status
Simulation time 94071322 ps
CPU time 0.89 seconds
Started Jul 06 06:57:17 PM PDT 24
Finished Jul 06 06:57:18 PM PDT 24
Peak memory 204376 kb
Host smart-cf2d3971-1d09-4140-baaf-dbf6d2401ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709299462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1709299462
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1961673273
Short name T1609
Test name
Test status
Simulation time 583021561 ps
CPU time 2.53 seconds
Started Jul 06 06:57:18 PM PDT 24
Finished Jul 06 06:57:21 PM PDT 24
Peak memory 204648 kb
Host smart-59a28d7c-4c33-428d-a4ee-b507cd4ee28e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961673273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1961673273
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.568977829
Short name T175
Test name
Test status
Simulation time 277506926 ps
CPU time 1.5 seconds
Started Jul 06 06:57:19 PM PDT 24
Finished Jul 06 06:57:21 PM PDT 24
Peak memory 204572 kb
Host smart-c642baf7-14dd-4803-8947-8adc4c4bcf45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568977829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.568977829
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3524985701
Short name T1595
Test name
Test status
Simulation time 51628418 ps
CPU time 0.85 seconds
Started Jul 06 06:57:25 PM PDT 24
Finished Jul 06 06:57:28 PM PDT 24
Peak memory 204276 kb
Host smart-47faaf8b-6c23-43a3-b6f3-ba922e1035bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524985701 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3524985701
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.337236551
Short name T1613
Test name
Test status
Simulation time 76282059 ps
CPU time 0.79 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204228 kb
Host smart-b71bffd0-21cc-403b-8bd9-7e246dafccbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337236551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.337236551
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.335522612
Short name T1579
Test name
Test status
Simulation time 17644769 ps
CPU time 0.7 seconds
Started Jul 06 06:57:27 PM PDT 24
Finished Jul 06 06:57:29 PM PDT 24
Peak memory 204216 kb
Host smart-0a37bbba-51e2-4e50-a194-6b2850698adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335522612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.335522612
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1445115154
Short name T94
Test name
Test status
Simulation time 74087075 ps
CPU time 0.85 seconds
Started Jul 06 06:57:27 PM PDT 24
Finished Jul 06 06:57:29 PM PDT 24
Peak memory 204368 kb
Host smart-76b179be-54f7-47b8-8eee-09cf128adf9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445115154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1445115154
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1352133883
Short name T182
Test name
Test status
Simulation time 289760163 ps
CPU time 1.54 seconds
Started Jul 06 06:57:23 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204628 kb
Host smart-fb1f56ae-c80f-4c98-be1f-0494239fb5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352133883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1352133883
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2624477778
Short name T201
Test name
Test status
Simulation time 42235093 ps
CPU time 1.79 seconds
Started Jul 06 06:55:48 PM PDT 24
Finished Jul 06 06:56:39 PM PDT 24
Peak memory 204384 kb
Host smart-c63b7a8d-1917-4a78-8b22-e6a1721b39b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624477778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2624477778
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2779869507
Short name T1535
Test name
Test status
Simulation time 311243737 ps
CPU time 2.61 seconds
Started Jul 06 06:55:49 PM PDT 24
Finished Jul 06 06:56:40 PM PDT 24
Peak memory 204480 kb
Host smart-fe5f6728-b91f-426a-9265-f85c342a2661
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779869507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2779869507
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1194223000
Short name T1559
Test name
Test status
Simulation time 47514933 ps
CPU time 0.76 seconds
Started Jul 06 06:55:44 PM PDT 24
Finished Jul 06 06:56:36 PM PDT 24
Peak memory 204308 kb
Host smart-dfc3e509-b022-4bb7-8d00-159fafbe56ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194223000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1194223000
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1566525459
Short name T93
Test name
Test status
Simulation time 31426336 ps
CPU time 0.93 seconds
Started Jul 06 06:55:49 PM PDT 24
Finished Jul 06 06:56:39 PM PDT 24
Peak memory 204428 kb
Host smart-e086c0d9-773c-4793-9aa4-20612b54d5e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566525459 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1566525459
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1137183633
Short name T1550
Test name
Test status
Simulation time 43998789 ps
CPU time 0.73 seconds
Started Jul 06 06:55:49 PM PDT 24
Finished Jul 06 06:56:38 PM PDT 24
Peak memory 204312 kb
Host smart-4da4f343-8827-4b93-90ef-82fb879741a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137183633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1137183633
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3474539610
Short name T1573
Test name
Test status
Simulation time 21541197 ps
CPU time 0.68 seconds
Started Jul 06 06:55:47 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204260 kb
Host smart-8ef86da5-3824-4a20-a1f0-7c4e64a3cdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474539610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3474539610
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3474939591
Short name T1599
Test name
Test status
Simulation time 238885648 ps
CPU time 2.24 seconds
Started Jul 06 06:55:45 PM PDT 24
Finished Jul 06 06:56:38 PM PDT 24
Peak memory 204584 kb
Host smart-1f7646bd-2a54-4efb-b3a1-28514bea9e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474939591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3474939591
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.4082911316
Short name T1530
Test name
Test status
Simulation time 26585508 ps
CPU time 0.68 seconds
Started Jul 06 06:57:27 PM PDT 24
Finished Jul 06 06:57:29 PM PDT 24
Peak memory 204216 kb
Host smart-a2e714ed-43b7-4112-8bf7-615a62ea9126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082911316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.4082911316
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2866989887
Short name T1544
Test name
Test status
Simulation time 24776486 ps
CPU time 0.66 seconds
Started Jul 06 06:57:23 PM PDT 24
Finished Jul 06 06:57:25 PM PDT 24
Peak memory 204304 kb
Host smart-de6161e1-cd77-471c-85f1-860d319869cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866989887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2866989887
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1065607944
Short name T1556
Test name
Test status
Simulation time 34586683 ps
CPU time 0.66 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204292 kb
Host smart-5a49f0f9-e3f8-4d05-b21b-6dcfd8de64d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065607944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1065607944
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.4134096748
Short name T1630
Test name
Test status
Simulation time 151146024 ps
CPU time 0.73 seconds
Started Jul 06 06:57:26 PM PDT 24
Finished Jul 06 06:57:28 PM PDT 24
Peak memory 204284 kb
Host smart-bf7e1452-f8d6-4423-8884-ca1821c458f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134096748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4134096748
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2593958070
Short name T1552
Test name
Test status
Simulation time 29728117 ps
CPU time 0.7 seconds
Started Jul 06 06:57:25 PM PDT 24
Finished Jul 06 06:57:27 PM PDT 24
Peak memory 204236 kb
Host smart-43f7ca39-ef5c-4c80-a992-136a5f58fd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593958070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2593958070
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1766058908
Short name T1539
Test name
Test status
Simulation time 32104588 ps
CPU time 0.74 seconds
Started Jul 06 06:57:26 PM PDT 24
Finished Jul 06 06:57:28 PM PDT 24
Peak memory 204272 kb
Host smart-d71f8f25-3a5c-4838-9e5b-ba0992b50717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766058908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1766058908
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2812697563
Short name T1536
Test name
Test status
Simulation time 171413797 ps
CPU time 0.65 seconds
Started Jul 06 06:57:26 PM PDT 24
Finished Jul 06 06:57:28 PM PDT 24
Peak memory 204268 kb
Host smart-51384eb7-7ab0-40b6-a3a2-ba244ce47102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812697563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2812697563
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1096541037
Short name T1533
Test name
Test status
Simulation time 49602522 ps
CPU time 0.69 seconds
Started Jul 06 06:58:13 PM PDT 24
Finished Jul 06 06:58:15 PM PDT 24
Peak memory 204300 kb
Host smart-356a15e5-0cdc-4e0f-8865-c04ee62f0466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096541037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1096541037
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.4065902944
Short name T1580
Test name
Test status
Simulation time 24649288 ps
CPU time 0.7 seconds
Started Jul 06 06:57:25 PM PDT 24
Finished Jul 06 06:57:27 PM PDT 24
Peak memory 204252 kb
Host smart-cf0e7f5a-8f8e-4aa9-a7dd-4ee41272b297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065902944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.4065902944
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.595298861
Short name T1583
Test name
Test status
Simulation time 25456347 ps
CPU time 0.74 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204248 kb
Host smart-324c17eb-35f0-4dbf-ac75-c320c0e16b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595298861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.595298861
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2008422468
Short name T1581
Test name
Test status
Simulation time 174478958 ps
CPU time 1.86 seconds
Started Jul 06 06:55:52 PM PDT 24
Finished Jul 06 06:56:43 PM PDT 24
Peak memory 204460 kb
Host smart-41c4c531-93bc-48cc-bb67-f3da2c8542a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008422468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2008422468
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1090425986
Short name T90
Test name
Test status
Simulation time 912789400 ps
CPU time 5.31 seconds
Started Jul 06 06:55:49 PM PDT 24
Finished Jul 06 06:56:43 PM PDT 24
Peak memory 204464 kb
Host smart-95fbe9df-eaf8-4905-8766-7186b86aa986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090425986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1090425986
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.870867223
Short name T1620
Test name
Test status
Simulation time 44138373 ps
CPU time 0.68 seconds
Started Jul 06 06:55:47 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 204280 kb
Host smart-98da3588-eae4-4154-ad1f-70bfcb1afa11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870867223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.870867223
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1900213359
Short name T1553
Test name
Test status
Simulation time 41134271 ps
CPU time 0.67 seconds
Started Jul 06 06:55:50 PM PDT 24
Finished Jul 06 06:56:41 PM PDT 24
Peak memory 204276 kb
Host smart-5ca2dd28-ffef-455c-ac77-fc5c9fc76356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900213359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1900213359
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3660322505
Short name T86
Test name
Test status
Simulation time 58384994 ps
CPU time 1.19 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204520 kb
Host smart-d0ccba83-2132-41e9-84b2-95b88ae4f20f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660322505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3660322505
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2865340199
Short name T1588
Test name
Test status
Simulation time 248943238 ps
CPU time 2.42 seconds
Started Jul 06 06:55:49 PM PDT 24
Finished Jul 06 06:56:40 PM PDT 24
Peak memory 204468 kb
Host smart-4232051c-eef9-4a1b-a60f-fbdce263c6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865340199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2865340199
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2695836924
Short name T156
Test name
Test status
Simulation time 73144304 ps
CPU time 1.42 seconds
Started Jul 06 06:55:52 PM PDT 24
Finished Jul 06 06:56:42 PM PDT 24
Peak memory 204600 kb
Host smart-8b424b8b-e128-4dbf-8bbe-f8efcfd6703d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695836924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2695836924
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1594364232
Short name T1569
Test name
Test status
Simulation time 51256382 ps
CPU time 0.72 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204284 kb
Host smart-8ff6a8ca-e8b9-4910-bf69-680048cb91ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594364232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1594364232
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3514548779
Short name T1571
Test name
Test status
Simulation time 69031986 ps
CPU time 0.68 seconds
Started Jul 06 06:57:27 PM PDT 24
Finished Jul 06 06:57:29 PM PDT 24
Peak memory 204312 kb
Host smart-d6e5f40d-3a0c-4c38-a619-558594c074ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514548779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3514548779
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.973230253
Short name T1542
Test name
Test status
Simulation time 18094636 ps
CPU time 0.62 seconds
Started Jul 06 06:57:25 PM PDT 24
Finished Jul 06 06:57:27 PM PDT 24
Peak memory 204252 kb
Host smart-94e4d8e0-a9d7-4537-aa4f-84bb8aca5cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973230253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.973230253
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2617157039
Short name T1575
Test name
Test status
Simulation time 44776839 ps
CPU time 0.66 seconds
Started Jul 06 06:57:24 PM PDT 24
Finished Jul 06 06:57:26 PM PDT 24
Peak memory 204284 kb
Host smart-05070e55-9dc5-4148-9c60-0cdc8e9d4ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617157039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2617157039
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3297930544
Short name T110
Test name
Test status
Simulation time 42351443 ps
CPU time 0.66 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204256 kb
Host smart-281ec07e-fb8c-47b6-b845-47a8f9c975af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297930544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3297930544
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3213926138
Short name T1597
Test name
Test status
Simulation time 17793950 ps
CPU time 0.67 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204196 kb
Host smart-23d7398e-ea33-444c-a044-0e431670dbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213926138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3213926138
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3723050904
Short name T1541
Test name
Test status
Simulation time 20768192 ps
CPU time 0.67 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:31 PM PDT 24
Peak memory 204272 kb
Host smart-2fc6d334-5fa6-4171-9c24-631458507a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723050904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3723050904
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1511511023
Short name T1551
Test name
Test status
Simulation time 27116429 ps
CPU time 0.69 seconds
Started Jul 06 06:57:29 PM PDT 24
Finished Jul 06 06:57:31 PM PDT 24
Peak memory 204228 kb
Host smart-484a4843-5358-4291-8540-7ec4f696f00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511511023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1511511023
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3259288024
Short name T1605
Test name
Test status
Simulation time 14953953 ps
CPU time 0.67 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204320 kb
Host smart-e782104b-ff15-44df-ba28-1b945d0f35bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259288024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3259288024
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1943388825
Short name T111
Test name
Test status
Simulation time 22084530 ps
CPU time 0.7 seconds
Started Jul 06 06:57:29 PM PDT 24
Finished Jul 06 06:57:31 PM PDT 24
Peak memory 204284 kb
Host smart-02e53df1-e242-45a2-9742-92cff35b20dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943388825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1943388825
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3961922959
Short name T1560
Test name
Test status
Simulation time 94001667 ps
CPU time 1.92 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204436 kb
Host smart-907d5b01-8518-4cb5-abb7-6482224a7709
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961922959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3961922959
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.586217884
Short name T106
Test name
Test status
Simulation time 348855139 ps
CPU time 2.94 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:48 PM PDT 24
Peak memory 204408 kb
Host smart-6c07fae0-5278-4761-8def-e0f88341f12d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586217884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.586217884
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.251484185
Short name T132
Test name
Test status
Simulation time 57645756 ps
CPU time 0.74 seconds
Started Jul 06 06:55:56 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204252 kb
Host smart-ca0678d3-21fc-448f-82d8-1c8c94a9607b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251484185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.251484185
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3664927984
Short name T1589
Test name
Test status
Simulation time 410886436 ps
CPU time 0.92 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:45 PM PDT 24
Peak memory 204360 kb
Host smart-f0d99bf8-4d75-4b73-a842-1a586ec89fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664927984 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3664927984
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1018574415
Short name T1591
Test name
Test status
Simulation time 18462452 ps
CPU time 0.73 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204232 kb
Host smart-dfe648ea-7a1b-40c3-ac09-2232795d2222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018574415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1018574415
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1092662699
Short name T1577
Test name
Test status
Simulation time 26057379 ps
CPU time 0.67 seconds
Started Jul 06 06:55:56 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204244 kb
Host smart-76d03ea4-fba6-496c-bee2-09e0cfea700f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092662699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1092662699
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.840524527
Short name T1576
Test name
Test status
Simulation time 50875808 ps
CPU time 1.14 seconds
Started Jul 06 06:55:55 PM PDT 24
Finished Jul 06 06:56:46 PM PDT 24
Peak memory 204464 kb
Host smart-5f038b03-8457-4806-826b-6442e91c801e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840524527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.840524527
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1528359495
Short name T181
Test name
Test status
Simulation time 117430416 ps
CPU time 1.6 seconds
Started Jul 06 06:55:56 PM PDT 24
Finished Jul 06 06:56:47 PM PDT 24
Peak memory 204616 kb
Host smart-8f8470b9-9b95-4159-a81b-47932e3454a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528359495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1528359495
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.270877438
Short name T169
Test name
Test status
Simulation time 235546949 ps
CPU time 2.09 seconds
Started Jul 06 06:55:58 PM PDT 24
Finished Jul 06 06:56:48 PM PDT 24
Peak memory 204528 kb
Host smart-47c5b9c8-7791-4a14-ab63-16fdbf8aca7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270877438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.270877438
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3479420098
Short name T1532
Test name
Test status
Simulation time 18061140 ps
CPU time 0.68 seconds
Started Jul 06 06:57:31 PM PDT 24
Finished Jul 06 06:57:33 PM PDT 24
Peak memory 204316 kb
Host smart-e970e184-ffb1-4963-bd67-aa7ccc0d3ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479420098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3479420098
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2977118969
Short name T1619
Test name
Test status
Simulation time 67815394 ps
CPU time 0.68 seconds
Started Jul 06 06:57:28 PM PDT 24
Finished Jul 06 06:57:30 PM PDT 24
Peak memory 204276 kb
Host smart-15f9a694-555f-40f2-a094-44e30f162f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977118969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2977118969
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1788962539
Short name T1606
Test name
Test status
Simulation time 18348488 ps
CPU time 0.69 seconds
Started Jul 06 06:57:29 PM PDT 24
Finished Jul 06 06:57:31 PM PDT 24
Peak memory 204280 kb
Host smart-d68d9b75-f4b8-4789-8139-bc6d4e429ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788962539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1788962539
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1016750721
Short name T1558
Test name
Test status
Simulation time 29169472 ps
CPU time 0.73 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204260 kb
Host smart-05639c23-e43b-4678-8a1e-85c2b13539a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016750721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1016750721
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2179378493
Short name T1537
Test name
Test status
Simulation time 54305371 ps
CPU time 0.68 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204276 kb
Host smart-6e3a281c-c927-461b-b504-433ca9d89580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179378493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2179378493
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1166490095
Short name T1543
Test name
Test status
Simulation time 19205768 ps
CPU time 0.7 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204304 kb
Host smart-ac02f0a5-b7ed-47d0-9404-ed105c1606a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166490095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1166490095
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.878848901
Short name T1529
Test name
Test status
Simulation time 31993011 ps
CPU time 0.68 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204284 kb
Host smart-41f53d11-8a5e-4abe-a4e8-7d195d5841b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878848901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.878848901
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3841028925
Short name T1593
Test name
Test status
Simulation time 41277168 ps
CPU time 0.68 seconds
Started Jul 06 06:57:30 PM PDT 24
Finished Jul 06 06:57:32 PM PDT 24
Peak memory 204228 kb
Host smart-95a81146-af0f-4f28-97c0-2ceddf088006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841028925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3841028925
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.143100641
Short name T1624
Test name
Test status
Simulation time 37849592 ps
CPU time 0.69 seconds
Started Jul 06 06:57:31 PM PDT 24
Finished Jul 06 06:57:33 PM PDT 24
Peak memory 204252 kb
Host smart-ca365d70-1883-4f1b-a07b-d947fa1fa777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143100641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.143100641
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1514458415
Short name T1534
Test name
Test status
Simulation time 47674540 ps
CPU time 0.7 seconds
Started Jul 06 06:57:28 PM PDT 24
Finished Jul 06 06:57:30 PM PDT 24
Peak memory 204308 kb
Host smart-b0763efa-c0ec-4cb2-9795-a26e67373c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514458415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1514458415
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3512209510
Short name T1603
Test name
Test status
Simulation time 63148734 ps
CPU time 1.05 seconds
Started Jul 06 06:56:00 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204432 kb
Host smart-1c859b89-7354-48a7-9caa-b68e0b7b1740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512209510 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3512209510
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2932400887
Short name T1563
Test name
Test status
Simulation time 74832110 ps
CPU time 0.7 seconds
Started Jul 06 06:56:02 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204232 kb
Host smart-aae83a3a-2750-4d75-b810-30e60a20903e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932400887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2932400887
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2856636420
Short name T1568
Test name
Test status
Simulation time 22396292 ps
CPU time 0.71 seconds
Started Jul 06 06:56:01 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204272 kb
Host smart-de8e0fb6-502d-477c-9b4b-728bb233fbe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856636420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2856636420
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2529305568
Short name T1567
Test name
Test status
Simulation time 334123500 ps
CPU time 1.2 seconds
Started Jul 06 06:56:04 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204556 kb
Host smart-fd3e746d-8c66-4d41-8490-614db2a8786f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529305568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2529305568
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3429459117
Short name T1574
Test name
Test status
Simulation time 58531614 ps
CPU time 1.46 seconds
Started Jul 06 06:55:56 PM PDT 24
Finished Jul 06 06:56:47 PM PDT 24
Peak memory 204584 kb
Host smart-764ce237-00d5-4096-8700-c0897c2778d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429459117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3429459117
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2124831629
Short name T176
Test name
Test status
Simulation time 488273778 ps
CPU time 1.35 seconds
Started Jul 06 06:56:01 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204600 kb
Host smart-b4b22859-8cf7-44dc-b6b1-690c536f191a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124831629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2124831629
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.699787660
Short name T193
Test name
Test status
Simulation time 176031795 ps
CPU time 0.81 seconds
Started Jul 06 06:55:59 PM PDT 24
Finished Jul 06 06:56:49 PM PDT 24
Peak memory 204380 kb
Host smart-865d8f42-000f-4af2-a0a4-6eb24cb1edf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699787660 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.699787660
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2858898924
Short name T196
Test name
Test status
Simulation time 19018398 ps
CPU time 0.71 seconds
Started Jul 06 06:56:01 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204228 kb
Host smart-d152078b-b678-499f-963b-fd057da589dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858898924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2858898924
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1697026437
Short name T1623
Test name
Test status
Simulation time 18085135 ps
CPU time 0.66 seconds
Started Jul 06 06:56:04 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204248 kb
Host smart-8bf05d6f-187f-417d-8c6c-f26546229f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697026437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1697026437
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4291989092
Short name T1572
Test name
Test status
Simulation time 59806040 ps
CPU time 0.92 seconds
Started Jul 06 06:56:02 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204084 kb
Host smart-0425b684-2f0a-4bc3-a0c1-c0669c6be802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291989092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4291989092
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1437153716
Short name T1600
Test name
Test status
Simulation time 45845522 ps
CPU time 1.27 seconds
Started Jul 06 06:56:01 PM PDT 24
Finished Jul 06 06:56:50 PM PDT 24
Peak memory 204612 kb
Host smart-3930af87-2780-4434-b813-f01680f1aeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437153716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1437153716
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.765576621
Short name T183
Test name
Test status
Simulation time 131232064 ps
CPU time 2.23 seconds
Started Jul 06 06:56:02 PM PDT 24
Finished Jul 06 06:56:51 PM PDT 24
Peak memory 204296 kb
Host smart-3b8a0016-f85c-4c57-96af-160599d7da1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765576621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.765576621
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2701995329
Short name T1604
Test name
Test status
Simulation time 168421211 ps
CPU time 0.92 seconds
Started Jul 06 06:56:07 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204336 kb
Host smart-9aed3960-a5c4-49b1-a45a-b0b1c74b5472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701995329 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2701995329
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.619690453
Short name T130
Test name
Test status
Simulation time 26214813 ps
CPU time 0.84 seconds
Started Jul 06 06:56:09 PM PDT 24
Finished Jul 06 06:56:54 PM PDT 24
Peak memory 204256 kb
Host smart-7dfc5644-3f7e-4229-93fb-653e0ead9d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619690453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.619690453
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.659758070
Short name T1554
Test name
Test status
Simulation time 54863512 ps
CPU time 0.66 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204280 kb
Host smart-77a38d80-4f7c-4275-ad4a-cd7735c89e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659758070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.659758070
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.896644516
Short name T1592
Test name
Test status
Simulation time 42102114 ps
CPU time 0.89 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204320 kb
Host smart-2d97e0d5-3d6f-41ae-abdc-db397b0b8948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896644516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.896644516
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2631291680
Short name T1610
Test name
Test status
Simulation time 40987595 ps
CPU time 1.73 seconds
Started Jul 06 06:56:08 PM PDT 24
Finished Jul 06 06:56:55 PM PDT 24
Peak memory 204536 kb
Host smart-fab20ad2-f396-4f74-aadc-058cc5d88211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631291680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2631291680
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3417048843
Short name T178
Test name
Test status
Simulation time 140783024 ps
CPU time 2.38 seconds
Started Jul 06 06:56:05 PM PDT 24
Finished Jul 06 06:56:54 PM PDT 24
Peak memory 204504 kb
Host smart-a6dd8861-e3bc-4e9e-9537-3159ff78de26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417048843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3417048843
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1116534139
Short name T192
Test name
Test status
Simulation time 45303574 ps
CPU time 1.17 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:53 PM PDT 24
Peak memory 204564 kb
Host smart-9bfec838-7af3-4b2d-bf38-b996d9559a24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116534139 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1116534139
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4128027153
Short name T1601
Test name
Test status
Simulation time 34880018 ps
CPU time 0.8 seconds
Started Jul 06 06:56:07 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204196 kb
Host smart-d3030232-2148-47ab-beda-c28b30c3ceb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128027153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.4128027153
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1088207487
Short name T1584
Test name
Test status
Simulation time 26371987 ps
CPU time 0.69 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204260 kb
Host smart-a94f71a7-a2ac-4ec5-bb93-131ea453e6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088207487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1088207487
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2686279811
Short name T1562
Test name
Test status
Simulation time 108257307 ps
CPU time 1.12 seconds
Started Jul 06 06:56:07 PM PDT 24
Finished Jul 06 06:56:53 PM PDT 24
Peak memory 204508 kb
Host smart-3d310000-5f96-4622-b4be-4ac8e4cbf0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686279811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2686279811
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3653281846
Short name T184
Test name
Test status
Simulation time 195251152 ps
CPU time 2.28 seconds
Started Jul 06 06:56:08 PM PDT 24
Finished Jul 06 06:56:55 PM PDT 24
Peak memory 204532 kb
Host smart-bb3ba4f5-9a73-473e-923a-95451da0a8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653281846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3653281846
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.285395164
Short name T1627
Test name
Test status
Simulation time 296526353 ps
CPU time 1.46 seconds
Started Jul 06 06:56:08 PM PDT 24
Finished Jul 06 06:56:54 PM PDT 24
Peak memory 204516 kb
Host smart-f9872961-7266-45d8-8191-cbb2af0e56c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285395164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.285395164
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2387699389
Short name T1632
Test name
Test status
Simulation time 36569984 ps
CPU time 0.77 seconds
Started Jul 06 06:56:12 PM PDT 24
Finished Jul 06 06:56:57 PM PDT 24
Peak memory 204356 kb
Host smart-0a4539a7-4d78-437d-9c6d-92439a897f2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387699389 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2387699389
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1446114903
Short name T203
Test name
Test status
Simulation time 25295628 ps
CPU time 0.78 seconds
Started Jul 06 06:56:08 PM PDT 24
Finished Jul 06 06:56:54 PM PDT 24
Peak memory 204252 kb
Host smart-3858ee5e-065b-4f70-86fa-2d6663698dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446114903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1446114903
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1409454413
Short name T1538
Test name
Test status
Simulation time 16957813 ps
CPU time 0.65 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:52 PM PDT 24
Peak memory 204300 kb
Host smart-e68bfda7-beb0-45ec-88a9-37b7e945cbec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409454413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1409454413
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3282307864
Short name T206
Test name
Test status
Simulation time 198065688 ps
CPU time 1.28 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:53 PM PDT 24
Peak memory 204540 kb
Host smart-c4dfd8c0-744f-49fa-ba17-7122bab470f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282307864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3282307864
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1648519845
Short name T1598
Test name
Test status
Simulation time 82184714 ps
CPU time 1.2 seconds
Started Jul 06 06:56:07 PM PDT 24
Finished Jul 06 06:56:53 PM PDT 24
Peak memory 204608 kb
Host smart-cb76c7c6-99ce-4362-91cc-ca9d02bb15ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648519845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1648519845
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1264355990
Short name T180
Test name
Test status
Simulation time 578435924 ps
CPU time 2.4 seconds
Started Jul 06 06:56:06 PM PDT 24
Finished Jul 06 06:56:54 PM PDT 24
Peak memory 204556 kb
Host smart-77bd9511-b381-4a0d-bfbc-fe96787a9469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264355990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1264355990
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2377926540
Short name T1469
Test name
Test status
Simulation time 27891551 ps
CPU time 0.62 seconds
Started Jul 06 05:38:04 PM PDT 24
Finished Jul 06 05:38:05 PM PDT 24
Peak memory 204592 kb
Host smart-f5a1071d-6054-456f-b339-d355424f948f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377926540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2377926540
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3796324422
Short name T1421
Test name
Test status
Simulation time 1080761409 ps
CPU time 4.04 seconds
Started Jul 06 05:37:52 PM PDT 24
Finished Jul 06 05:37:57 PM PDT 24
Peak memory 213204 kb
Host smart-f4dec836-3617-4be0-8880-136eaab53d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796324422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3796324422
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2713766826
Short name T667
Test name
Test status
Simulation time 1697651029 ps
CPU time 22.25 seconds
Started Jul 06 05:37:47 PM PDT 24
Finished Jul 06 05:38:10 PM PDT 24
Peak memory 286032 kb
Host smart-15562999-87f2-4431-89c6-0c4a8585947e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713766826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2713766826
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2831251872
Short name T1264
Test name
Test status
Simulation time 6579827992 ps
CPU time 116.48 seconds
Started Jul 06 05:37:53 PM PDT 24
Finished Jul 06 05:39:50 PM PDT 24
Peak memory 605556 kb
Host smart-104c64f3-79e5-4087-a56a-4b53080dd95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831251872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2831251872
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2358038360
Short name T1142
Test name
Test status
Simulation time 4854261128 ps
CPU time 187.32 seconds
Started Jul 06 05:37:50 PM PDT 24
Finished Jul 06 05:40:57 PM PDT 24
Peak memory 787212 kb
Host smart-4b96a238-baef-4cdc-bfa5-2aea2ecd3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358038360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2358038360
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1144129084
Short name T1304
Test name
Test status
Simulation time 988958862 ps
CPU time 4.49 seconds
Started Jul 06 05:37:48 PM PDT 24
Finished Jul 06 05:37:53 PM PDT 24
Peak memory 230160 kb
Host smart-ac4baa35-4bc2-480d-9642-554bc2e971bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144129084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1144129084
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.348710742
Short name T1213
Test name
Test status
Simulation time 23311621158 ps
CPU time 158.71 seconds
Started Jul 06 05:37:49 PM PDT 24
Finished Jul 06 05:40:28 PM PDT 24
Peak memory 1571476 kb
Host smart-04197a82-88f1-48f7-8f81-777cf431e569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348710742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.348710742
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3687253160
Short name T1134
Test name
Test status
Simulation time 1270348309 ps
CPU time 13.09 seconds
Started Jul 06 05:38:01 PM PDT 24
Finished Jul 06 05:38:14 PM PDT 24
Peak memory 205068 kb
Host smart-7fae5122-d763-4716-bf5f-33274f4e0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687253160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3687253160
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_perf.994134415
Short name T1209
Test name
Test status
Simulation time 48575391433 ps
CPU time 2568.28 seconds
Started Jul 06 05:37:52 PM PDT 24
Finished Jul 06 06:20:41 PM PDT 24
Peak memory 2510244 kb
Host smart-87c7116f-035e-48a7-982a-3f94f9b2f7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994134415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.994134415
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.2318143524
Short name T494
Test name
Test status
Simulation time 139359584 ps
CPU time 2.26 seconds
Started Jul 06 05:37:53 PM PDT 24
Finished Jul 06 05:37:56 PM PDT 24
Peak memory 229516 kb
Host smart-7e1d0607-8ac7-403a-83a3-d216b7fd4b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318143524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2318143524
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2012748064
Short name T367
Test name
Test status
Simulation time 4844682754 ps
CPU time 24.49 seconds
Started Jul 06 05:37:47 PM PDT 24
Finished Jul 06 05:38:12 PM PDT 24
Peak memory 349788 kb
Host smart-860da2f7-57b1-4f75-b1d4-a43b55d92aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012748064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2012748064
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.330100416
Short name T159
Test name
Test status
Simulation time 203180635 ps
CPU time 0.97 seconds
Started Jul 06 05:38:02 PM PDT 24
Finished Jul 06 05:38:03 PM PDT 24
Peak memory 223292 kb
Host smart-4d5eaa1b-11e8-412f-9272-2246355882dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330100416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.330100416
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3682874833
Short name T1278
Test name
Test status
Simulation time 762077436 ps
CPU time 3.7 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:07 PM PDT 24
Peak memory 204940 kb
Host smart-a88e2417-6d54-4cf0-8f7a-d4f8222e0f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682874833 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3682874833
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2385949004
Short name T626
Test name
Test status
Simulation time 145881887 ps
CPU time 0.87 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:10 PM PDT 24
Peak memory 204820 kb
Host smart-efdf55ad-688b-451d-8227-782415e45b7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385949004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2385949004
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1245120887
Short name T972
Test name
Test status
Simulation time 772069936 ps
CPU time 2.11 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:05 PM PDT 24
Peak memory 205024 kb
Host smart-4222ccaa-2a6c-4abe-8c00-32dca59af465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245120887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1245120887
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.2144793497
Short name T241
Test name
Test status
Simulation time 408953794 ps
CPU time 1.04 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:11 PM PDT 24
Peak memory 204612 kb
Host smart-63355399-11ef-4da7-9bb0-e8d618d4088c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144793497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2144793497
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3880266996
Short name T15
Test name
Test status
Simulation time 2459936315 ps
CPU time 12.36 seconds
Started Jul 06 05:37:54 PM PDT 24
Finished Jul 06 05:38:07 PM PDT 24
Peak memory 213824 kb
Host smart-94ed39a6-bd29-45a6-a6d7-a270beb4ac0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880266996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3880266996
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1315331206
Short name T708
Test name
Test status
Simulation time 285414456 ps
CPU time 4.24 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:08 PM PDT 24
Peak memory 205068 kb
Host smart-c07e6275-8e44-4883-8ff0-4154ceea2173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315331206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1315331206
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2364772907
Short name T509
Test name
Test status
Simulation time 4312845827 ps
CPU time 5.58 seconds
Started Jul 06 05:37:59 PM PDT 24
Finished Jul 06 05:38:05 PM PDT 24
Peak memory 205116 kb
Host smart-48fc27fc-8139-49db-a4f1-a3de79bf2cf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364772907 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2364772907
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3294058170
Short name T981
Test name
Test status
Simulation time 6583586406 ps
CPU time 4.77 seconds
Started Jul 06 05:37:57 PM PDT 24
Finished Jul 06 05:38:02 PM PDT 24
Peak memory 205064 kb
Host smart-87cd0a3b-0af5-4258-a172-c151dbd56b92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294058170 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3294058170
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1876720754
Short name T1362
Test name
Test status
Simulation time 5614208647 ps
CPU time 17.76 seconds
Started Jul 06 05:37:53 PM PDT 24
Finished Jul 06 05:38:11 PM PDT 24
Peak memory 205040 kb
Host smart-feb45876-8d95-491d-9cb9-c3549df14284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876720754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1876720754
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1585336246
Short name T613
Test name
Test status
Simulation time 935733229 ps
CPU time 38.29 seconds
Started Jul 06 05:38:01 PM PDT 24
Finished Jul 06 05:38:39 PM PDT 24
Peak memory 205032 kb
Host smart-e6815e69-797d-4ee0-869c-02b7c5adc6eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585336246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1585336246
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3696980729
Short name T1410
Test name
Test status
Simulation time 30565713222 ps
CPU time 213.13 seconds
Started Jul 06 05:37:58 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 2765104 kb
Host smart-7de862f0-9a5e-436f-9552-0f261bb9efe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696980729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3696980729
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.486456872
Short name T937
Test name
Test status
Simulation time 692588608 ps
CPU time 5.97 seconds
Started Jul 06 05:37:58 PM PDT 24
Finished Jul 06 05:38:04 PM PDT 24
Peak memory 221392 kb
Host smart-3321e5ae-9a3f-4f8a-91cd-54c3b7166230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486456872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.486456872
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3181468656
Short name T1301
Test name
Test status
Simulation time 1107501137 ps
CPU time 7.35 seconds
Started Jul 06 05:37:57 PM PDT 24
Finished Jul 06 05:38:05 PM PDT 24
Peak memory 213264 kb
Host smart-c2a1e9a5-9cfd-45be-a359-c63f69afc876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181468656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3181468656
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1432172164
Short name T1082
Test name
Test status
Simulation time 16434604 ps
CPU time 0.62 seconds
Started Jul 06 05:38:11 PM PDT 24
Finished Jul 06 05:38:12 PM PDT 24
Peak memory 204528 kb
Host smart-b34db192-4446-4ab2-952f-dc1693274970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432172164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1432172164
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1198804649
Short name T1270
Test name
Test status
Simulation time 510684558 ps
CPU time 1.69 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:11 PM PDT 24
Peak memory 213324 kb
Host smart-0c5048f6-a741-4b8a-a3f1-11f3372d7bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198804649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1198804649
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.180579687
Short name T823
Test name
Test status
Simulation time 1426638873 ps
CPU time 18.55 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:28 PM PDT 24
Peak memory 278720 kb
Host smart-7012308e-710e-4826-a71d-c8327ed74af6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180579687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.180579687
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.335541666
Short name T341
Test name
Test status
Simulation time 4137910188 ps
CPU time 113.84 seconds
Started Jul 06 05:38:02 PM PDT 24
Finished Jul 06 05:39:56 PM PDT 24
Peak memory 858260 kb
Host smart-c95b576d-8fab-46b8-8be5-e0f6fa7308c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335541666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.335541666
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2531281132
Short name T837
Test name
Test status
Simulation time 11678063700 ps
CPU time 92.8 seconds
Started Jul 06 05:38:04 PM PDT 24
Finished Jul 06 05:39:38 PM PDT 24
Peak memory 908112 kb
Host smart-6720de26-b416-4bb9-930b-8817545f46da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531281132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2531281132
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3713873081
Short name T992
Test name
Test status
Simulation time 156781699 ps
CPU time 1.35 seconds
Started Jul 06 05:38:04 PM PDT 24
Finished Jul 06 05:38:06 PM PDT 24
Peak memory 204900 kb
Host smart-a98cada1-bea3-4aaf-b067-e2ac10f20e98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713873081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3713873081
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1369891190
Short name T994
Test name
Test status
Simulation time 2865205676 ps
CPU time 73.2 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:39:17 PM PDT 24
Peak memory 835764 kb
Host smart-309145e0-6fb8-4802-a401-457da8d3d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369891190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1369891190
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2959581086
Short name T742
Test name
Test status
Simulation time 576935011 ps
CPU time 4.06 seconds
Started Jul 06 05:38:12 PM PDT 24
Finished Jul 06 05:38:17 PM PDT 24
Peak memory 205064 kb
Host smart-edcc61d1-0f14-4903-8a9b-bf5ddc104594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959581086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2959581086
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.811256428
Short name T654
Test name
Test status
Simulation time 2885884201 ps
CPU time 24.27 seconds
Started Jul 06 05:38:14 PM PDT 24
Finished Jul 06 05:38:38 PM PDT 24
Peak memory 297784 kb
Host smart-7086e100-814e-4f7b-8605-63295dc0411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811256428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.811256428
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.4267856068
Short name T1379
Test name
Test status
Simulation time 16642017 ps
CPU time 0.67 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:04 PM PDT 24
Peak memory 204752 kb
Host smart-30538b3a-5ed2-4f6b-ac49-d02a8e2fc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267856068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.4267856068
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.893531325
Short name T439
Test name
Test status
Simulation time 9386845332 ps
CPU time 374.26 seconds
Started Jul 06 05:38:10 PM PDT 24
Finished Jul 06 05:44:25 PM PDT 24
Peak memory 222648 kb
Host smart-98e384fb-6e18-4b0d-b336-385c19d6c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893531325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.893531325
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3959897084
Short name T1175
Test name
Test status
Simulation time 1558681951 ps
CPU time 24.59 seconds
Started Jul 06 05:38:03 PM PDT 24
Finished Jul 06 05:38:28 PM PDT 24
Peak memory 360748 kb
Host smart-15ae1443-25aa-4ec8-8ce1-2bef514a90f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959897084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3959897084
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1928440812
Short name T257
Test name
Test status
Simulation time 75558992433 ps
CPU time 2025.07 seconds
Started Jul 06 05:38:08 PM PDT 24
Finished Jul 06 06:11:54 PM PDT 24
Peak memory 3256284 kb
Host smart-5486770a-e654-411c-b035-237f80c865ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928440812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1928440812
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.388788972
Short name T1386
Test name
Test status
Simulation time 1034245778 ps
CPU time 18.78 seconds
Started Jul 06 05:38:08 PM PDT 24
Finished Jul 06 05:38:27 PM PDT 24
Peak memory 229488 kb
Host smart-05fbcb7b-7198-46d8-ab9b-00bc6af6eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388788972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.388788972
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.438093413
Short name T161
Test name
Test status
Simulation time 261782644 ps
CPU time 0.97 seconds
Started Jul 06 05:38:13 PM PDT 24
Finished Jul 06 05:38:14 PM PDT 24
Peak memory 223212 kb
Host smart-72664e28-66f5-44a0-8556-48adf4d743a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438093413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.438093413
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.461639613
Short name T707
Test name
Test status
Simulation time 4741318377 ps
CPU time 4.65 seconds
Started Jul 06 05:38:13 PM PDT 24
Finished Jul 06 05:38:18 PM PDT 24
Peak memory 213380 kb
Host smart-e9c5c8a3-7681-4280-a939-0f5fe87c0712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461639613 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.461639613
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3511705953
Short name T388
Test name
Test status
Simulation time 729236491 ps
CPU time 1.45 seconds
Started Jul 06 05:38:12 PM PDT 24
Finished Jul 06 05:38:14 PM PDT 24
Peak memory 204936 kb
Host smart-2fa9e9e2-e401-4d10-98e6-fbc50e16ee0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511705953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3511705953
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1278473196
Short name T1424
Test name
Test status
Simulation time 142608831 ps
CPU time 0.98 seconds
Started Jul 06 05:38:13 PM PDT 24
Finished Jul 06 05:38:14 PM PDT 24
Peak memory 204816 kb
Host smart-995beef9-5c4c-4c7d-bfd9-86ad8691a215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278473196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1278473196
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.717278600
Short name T1350
Test name
Test status
Simulation time 1242206169 ps
CPU time 0.99 seconds
Started Jul 06 05:38:15 PM PDT 24
Finished Jul 06 05:38:16 PM PDT 24
Peak memory 204836 kb
Host smart-8bffcb63-a318-4c1a-8acd-66af98739832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717278600 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.717278600
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1192673711
Short name T1076
Test name
Test status
Simulation time 753598448 ps
CPU time 3.35 seconds
Started Jul 06 05:38:14 PM PDT 24
Finished Jul 06 05:38:18 PM PDT 24
Peak memory 205152 kb
Host smart-9a667a59-7290-4bb5-a460-046e978f019b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192673711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1192673711
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.143585356
Short name T982
Test name
Test status
Simulation time 613635819 ps
CPU time 3.94 seconds
Started Jul 06 05:38:08 PM PDT 24
Finished Jul 06 05:38:13 PM PDT 24
Peak memory 205036 kb
Host smart-6e7dc981-108b-47f1-a79d-82e07596a6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143585356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.143585356
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.214590436
Short name T231
Test name
Test status
Simulation time 13866897666 ps
CPU time 189.64 seconds
Started Jul 06 05:38:08 PM PDT 24
Finished Jul 06 05:41:18 PM PDT 24
Peak memory 3004872 kb
Host smart-66818f97-3389-4634-ab9b-b8d52af93ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214590436 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.214590436
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2511537860
Short name T639
Test name
Test status
Simulation time 1197639442 ps
CPU time 46.19 seconds
Started Jul 06 05:38:07 PM PDT 24
Finished Jul 06 05:38:54 PM PDT 24
Peak memory 205056 kb
Host smart-0b52177f-6f56-4335-a3ec-fde565b9dfc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511537860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2511537860
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2577897785
Short name T792
Test name
Test status
Simulation time 1518971925 ps
CPU time 29.7 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:38:39 PM PDT 24
Peak memory 228572 kb
Host smart-96a263ef-92e0-4e60-ac03-e1d445b9d1de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577897785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2577897785
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2115719817
Short name T303
Test name
Test status
Simulation time 56409388426 ps
CPU time 196.85 seconds
Started Jul 06 05:38:09 PM PDT 24
Finished Jul 06 05:41:27 PM PDT 24
Peak memory 2166680 kb
Host smart-3465f7f3-8b60-4875-859b-4136e71284c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115719817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2115719817
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2667238840
Short name T646
Test name
Test status
Simulation time 4025747183 ps
CPU time 85.4 seconds
Started Jul 06 05:38:10 PM PDT 24
Finished Jul 06 05:39:35 PM PDT 24
Peak memory 1150328 kb
Host smart-f0db0a75-d50d-4238-8aad-8873c46f1e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667238840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2667238840
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.373138403
Short name T1384
Test name
Test status
Simulation time 1250272764 ps
CPU time 7.57 seconds
Started Jul 06 05:38:10 PM PDT 24
Finished Jul 06 05:38:18 PM PDT 24
Peak memory 221332 kb
Host smart-3e320f83-a6e3-446c-b303-df92d5866df5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373138403 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.373138403
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.1803245684
Short name T731
Test name
Test status
Simulation time 222768955 ps
CPU time 3.04 seconds
Started Jul 06 05:38:13 PM PDT 24
Finished Jul 06 05:38:16 PM PDT 24
Peak memory 205032 kb
Host smart-f4e28e66-9ccc-4bb7-a09f-9e98e2aadcc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803245684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1803245684
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.696701713
Short name T1447
Test name
Test status
Simulation time 40504664 ps
CPU time 0.66 seconds
Started Jul 06 05:40:12 PM PDT 24
Finished Jul 06 05:40:14 PM PDT 24
Peak memory 204648 kb
Host smart-fe26e3df-dd48-4cef-b06a-09c9c2116ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696701713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.696701713
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.452709432
Short name T1014
Test name
Test status
Simulation time 215476763 ps
CPU time 3.7 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:11 PM PDT 24
Peak memory 215144 kb
Host smart-8aeede9f-6bfc-44b0-98bc-d9343b25988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452709432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.452709432
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.803831766
Short name T496
Test name
Test status
Simulation time 311679695 ps
CPU time 16.28 seconds
Started Jul 06 05:40:04 PM PDT 24
Finished Jul 06 05:40:21 PM PDT 24
Peak memory 268324 kb
Host smart-2a4d813b-fc4c-4bbe-8653-f00173ba2715
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803831766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.803831766
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2098746133
Short name T1273
Test name
Test status
Simulation time 19662764966 ps
CPU time 91.65 seconds
Started Jul 06 05:40:04 PM PDT 24
Finished Jul 06 05:41:37 PM PDT 24
Peak memory 521304 kb
Host smart-9a28e940-8bbd-4259-9477-e5268d0f6848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098746133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2098746133
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.618933096
Short name T774
Test name
Test status
Simulation time 18153520753 ps
CPU time 179.47 seconds
Started Jul 06 05:40:05 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 704512 kb
Host smart-612c2cc4-4e06-4ccb-8d6e-8423f6064e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618933096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.618933096
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2257008495
Short name T1496
Test name
Test status
Simulation time 605768826 ps
CPU time 1.32 seconds
Started Jul 06 05:40:06 PM PDT 24
Finished Jul 06 05:40:08 PM PDT 24
Peak memory 204968 kb
Host smart-6a87694e-2881-4c5b-a61f-66fc37fd3a86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257008495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2257008495
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3128559508
Short name T3
Test name
Test status
Simulation time 383583566 ps
CPU time 4.56 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:11 PM PDT 24
Peak memory 205020 kb
Host smart-c11a91c1-c31e-48b8-a1ef-d892c6a99253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128559508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3128559508
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1360567356
Short name T929
Test name
Test status
Simulation time 11879830360 ps
CPU time 70.66 seconds
Started Jul 06 05:40:03 PM PDT 24
Finished Jul 06 05:41:14 PM PDT 24
Peak memory 974196 kb
Host smart-13946c9f-df19-4229-ac96-c3713d7417b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360567356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1360567356
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2920524685
Short name T499
Test name
Test status
Simulation time 2169953588 ps
CPU time 96.45 seconds
Started Jul 06 05:40:14 PM PDT 24
Finished Jul 06 05:41:50 PM PDT 24
Peak memory 309044 kb
Host smart-14f3db3a-13b8-4b2e-8faf-ab06d97b18ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920524685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2920524685
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1474900728
Short name T642
Test name
Test status
Simulation time 30168113 ps
CPU time 0.71 seconds
Started Jul 06 05:40:02 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 204728 kb
Host smart-13a894ca-6a89-4a57-b13d-6ca005858d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474900728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1474900728
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.738415259
Short name T674
Test name
Test status
Simulation time 2925428428 ps
CPU time 39.09 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:47 PM PDT 24
Peak memory 214292 kb
Host smart-c89eb81d-4067-4919-9eef-6b7765c0634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738415259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.738415259
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.3103340289
Short name T527
Test name
Test status
Simulation time 64209183 ps
CPU time 1.68 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:09 PM PDT 24
Peak memory 213144 kb
Host smart-3f0030ec-17ef-4d2c-af84-1b648a4075ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103340289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3103340289
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1193019929
Short name T1378
Test name
Test status
Simulation time 1319764916 ps
CPU time 28.69 seconds
Started Jul 06 05:40:05 PM PDT 24
Finished Jul 06 05:40:34 PM PDT 24
Peak memory 365980 kb
Host smart-6391140d-dc6d-4fb0-8cb0-364ea28fa8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193019929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1193019929
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1850826227
Short name T786
Test name
Test status
Simulation time 4589365076 ps
CPU time 20.16 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:28 PM PDT 24
Peak memory 217884 kb
Host smart-3fabf947-d203-49f0-9877-e50b70751fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850826227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1850826227
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2766433006
Short name T1268
Test name
Test status
Simulation time 2451056675 ps
CPU time 3.41 seconds
Started Jul 06 05:40:12 PM PDT 24
Finished Jul 06 05:40:16 PM PDT 24
Peak memory 205080 kb
Host smart-1b20629d-2b00-4642-8f89-196f576a0cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766433006 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2766433006
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.937823837
Short name T441
Test name
Test status
Simulation time 272696325 ps
CPU time 1.12 seconds
Started Jul 06 05:40:08 PM PDT 24
Finished Jul 06 05:40:09 PM PDT 24
Peak memory 205208 kb
Host smart-ff4fec33-8aa8-4e7a-a276-d8d703f3ab13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937823837 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.937823837
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2372587893
Short name T889
Test name
Test status
Simulation time 238061242 ps
CPU time 0.81 seconds
Started Jul 06 05:40:11 PM PDT 24
Finished Jul 06 05:40:12 PM PDT 24
Peak memory 204856 kb
Host smart-8b1527eb-ad59-4cd0-bb5a-822e04b1d838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372587893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2372587893
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.895991813
Short name T432
Test name
Test status
Simulation time 137216870 ps
CPU time 0.96 seconds
Started Jul 06 05:40:12 PM PDT 24
Finished Jul 06 05:40:13 PM PDT 24
Peak memory 204804 kb
Host smart-6b388a04-15ec-4a8f-9795-b4dadb2991e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895991813 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.895991813
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1680681920
Short name T1136
Test name
Test status
Simulation time 1009617704 ps
CPU time 5.99 seconds
Started Jul 06 05:40:08 PM PDT 24
Finished Jul 06 05:40:14 PM PDT 24
Peak memory 213264 kb
Host smart-8de5bf94-2069-4a6e-802b-30cd951499f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680681920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1680681920
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2966347072
Short name T190
Test name
Test status
Simulation time 2572724839 ps
CPU time 4.16 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:11 PM PDT 24
Peak memory 205032 kb
Host smart-35dbcc4f-9fb0-4ad4-ae3b-e9660c7563ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966347072 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2966347072
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3624917793
Short name T980
Test name
Test status
Simulation time 679254754 ps
CPU time 22.47 seconds
Started Jul 06 05:40:08 PM PDT 24
Finished Jul 06 05:40:30 PM PDT 24
Peak memory 205032 kb
Host smart-dc0b0961-6e25-446a-a08b-5c1c6dbc5d4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624917793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3624917793
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1346875930
Short name T383
Test name
Test status
Simulation time 5042855228 ps
CPU time 6.26 seconds
Started Jul 06 05:40:08 PM PDT 24
Finished Jul 06 05:40:15 PM PDT 24
Peak memory 205124 kb
Host smart-85b93b05-6c12-450f-944a-1de34cdd6cf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346875930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1346875930
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3261482643
Short name T1171
Test name
Test status
Simulation time 46773027225 ps
CPU time 114.13 seconds
Started Jul 06 05:40:06 PM PDT 24
Finished Jul 06 05:42:00 PM PDT 24
Peak memory 1662316 kb
Host smart-2e5437ef-244d-487f-b2c4-fa7cf2f59740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261482643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3261482643
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1599315035
Short name T519
Test name
Test status
Simulation time 131001812 ps
CPU time 1.1 seconds
Started Jul 06 05:40:11 PM PDT 24
Finished Jul 06 05:40:12 PM PDT 24
Peak memory 204828 kb
Host smart-610a7fe4-deff-4944-9827-1f740815ddad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599315035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1599315035
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1178575863
Short name T1359
Test name
Test status
Simulation time 1431834973 ps
CPU time 8.32 seconds
Started Jul 06 05:40:07 PM PDT 24
Finished Jul 06 05:40:15 PM PDT 24
Peak memory 220624 kb
Host smart-c52ff636-a61f-4202-a9dc-03fb601dad17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178575863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1178575863
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.205537932
Short name T648
Test name
Test status
Simulation time 358786317 ps
CPU time 4.37 seconds
Started Jul 06 05:40:14 PM PDT 24
Finished Jul 06 05:40:19 PM PDT 24
Peak memory 204992 kb
Host smart-9812aa2f-edc5-4092-bae7-b8349af27dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205537932 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.205537932
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2329416726
Short name T575
Test name
Test status
Simulation time 392271180 ps
CPU time 3.31 seconds
Started Jul 06 05:40:19 PM PDT 24
Finished Jul 06 05:40:23 PM PDT 24
Peak memory 214340 kb
Host smart-1789796e-e285-48ff-95ed-2f863975c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329416726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2329416726
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1776795310
Short name T346
Test name
Test status
Simulation time 4643420040 ps
CPU time 17.16 seconds
Started Jul 06 05:40:19 PM PDT 24
Finished Jul 06 05:40:36 PM PDT 24
Peak memory 258792 kb
Host smart-44f07dfd-b54b-45c1-9e5f-cbdb02f0ef1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776795310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1776795310
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1105959945
Short name T737
Test name
Test status
Simulation time 1735344992 ps
CPU time 80.93 seconds
Started Jul 06 05:40:19 PM PDT 24
Finished Jul 06 05:41:41 PM PDT 24
Peak memory 422312 kb
Host smart-6a3ae6b6-9caf-48f3-a5f5-376e4c34b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105959945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1105959945
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1198984308
Short name T744
Test name
Test status
Simulation time 4038292293 ps
CPU time 146.89 seconds
Started Jul 06 05:40:21 PM PDT 24
Finished Jul 06 05:42:48 PM PDT 24
Peak memory 696284 kb
Host smart-c3a11ab9-09b6-44b8-a545-d80847301056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198984308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1198984308
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3169359112
Short name T920
Test name
Test status
Simulation time 542895122 ps
CPU time 1.06 seconds
Started Jul 06 05:40:18 PM PDT 24
Finished Jul 06 05:40:20 PM PDT 24
Peak memory 204764 kb
Host smart-896a5632-346a-4ef4-8ac9-0f4015ffc5a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169359112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3169359112
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1450941538
Short name T113
Test name
Test status
Simulation time 151717045 ps
CPU time 3.53 seconds
Started Jul 06 05:40:20 PM PDT 24
Finished Jul 06 05:40:24 PM PDT 24
Peak memory 227700 kb
Host smart-d47b7dff-3a7d-473b-93fc-473c36ba0cb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450941538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1450941538
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3349794655
Short name T142
Test name
Test status
Simulation time 4164603766 ps
CPU time 120.47 seconds
Started Jul 06 05:40:15 PM PDT 24
Finished Jul 06 05:42:15 PM PDT 24
Peak memory 1211344 kb
Host smart-8966ae24-aac8-4c1e-ba61-36c3e1d620be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349794655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3349794655
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3686957644
Short name T1191
Test name
Test status
Simulation time 454299064 ps
CPU time 19.13 seconds
Started Jul 06 05:40:29 PM PDT 24
Finished Jul 06 05:40:49 PM PDT 24
Peak memory 205012 kb
Host smart-068c883b-9756-4dd0-847b-1b32db345f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686957644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3686957644
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.367262139
Short name T869
Test name
Test status
Simulation time 28009703043 ps
CPU time 32.35 seconds
Started Jul 06 05:40:26 PM PDT 24
Finished Jul 06 05:40:59 PM PDT 24
Peak memory 406996 kb
Host smart-81d3af75-3da8-4d51-bbc4-d553e71903da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367262139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.367262139
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.311837855
Short name T1490
Test name
Test status
Simulation time 36329266 ps
CPU time 0.65 seconds
Started Jul 06 05:40:20 PM PDT 24
Finished Jul 06 05:40:21 PM PDT 24
Peak memory 204668 kb
Host smart-fb3bdf45-be82-4e9e-b04b-150df13f4fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311837855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.311837855
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1049318635
Short name T457
Test name
Test status
Simulation time 3063332499 ps
CPU time 89.6 seconds
Started Jul 06 05:40:20 PM PDT 24
Finished Jul 06 05:41:50 PM PDT 24
Peak memory 928680 kb
Host smart-213a3e50-a369-46ae-bd62-ced5cbdee9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049318635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1049318635
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.830071047
Short name T1329
Test name
Test status
Simulation time 740565205 ps
CPU time 4.2 seconds
Started Jul 06 05:40:20 PM PDT 24
Finished Jul 06 05:40:25 PM PDT 24
Peak memory 204976 kb
Host smart-ac259120-fea8-4f0b-9b6e-d318fcf2a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830071047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.830071047
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1380628586
Short name T348
Test name
Test status
Simulation time 8976038594 ps
CPU time 34.08 seconds
Started Jul 06 05:40:12 PM PDT 24
Finished Jul 06 05:40:47 PM PDT 24
Peak memory 423344 kb
Host smart-258ed904-d551-4f83-8953-9903a0f6bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380628586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1380628586
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.621515730
Short name T102
Test name
Test status
Simulation time 68521241607 ps
CPU time 338.94 seconds
Started Jul 06 05:40:21 PM PDT 24
Finished Jul 06 05:46:00 PM PDT 24
Peak memory 1869768 kb
Host smart-580765d5-eddb-4da5-9107-bb82361ee727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621515730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.621515730
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3379528606
Short name T922
Test name
Test status
Simulation time 785592750 ps
CPU time 36.85 seconds
Started Jul 06 05:40:21 PM PDT 24
Finished Jul 06 05:40:58 PM PDT 24
Peak memory 213212 kb
Host smart-bc3e22ee-79de-43ab-ba99-244fc3a35e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379528606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3379528606
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.813466641
Short name T666
Test name
Test status
Simulation time 2017036445 ps
CPU time 4.42 seconds
Started Jul 06 05:40:29 PM PDT 24
Finished Jul 06 05:40:34 PM PDT 24
Peak memory 205048 kb
Host smart-0fbc1758-e320-4f1d-9b71-0abe4b2eda10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813466641 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.813466641
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1803078471
Short name T13
Test name
Test status
Simulation time 1434646307 ps
CPU time 1.24 seconds
Started Jul 06 05:40:26 PM PDT 24
Finished Jul 06 05:40:27 PM PDT 24
Peak memory 207732 kb
Host smart-c15186c1-3978-4a21-ae36-23270afcbcdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803078471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1803078471
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2940816601
Short name T579
Test name
Test status
Simulation time 209168267 ps
CPU time 1.36 seconds
Started Jul 06 05:40:30 PM PDT 24
Finished Jul 06 05:40:31 PM PDT 24
Peak memory 205020 kb
Host smart-c2559d0e-d52a-473b-a4bb-8da2bc99d8d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940816601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2940816601
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.123116539
Short name T1083
Test name
Test status
Simulation time 1001212245 ps
CPU time 2.52 seconds
Started Jul 06 05:40:29 PM PDT 24
Finished Jul 06 05:40:32 PM PDT 24
Peak memory 205024 kb
Host smart-e8b2239c-6536-4b6f-a92f-5797f4d2063c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123116539 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.123116539
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2790075235
Short name T615
Test name
Test status
Simulation time 170575715 ps
CPU time 1.37 seconds
Started Jul 06 05:40:30 PM PDT 24
Finished Jul 06 05:40:31 PM PDT 24
Peak memory 204808 kb
Host smart-0acbcaff-67a7-4543-a541-a0306887b971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790075235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2790075235
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1618680449
Short name T556
Test name
Test status
Simulation time 2648573240 ps
CPU time 5.48 seconds
Started Jul 06 05:40:21 PM PDT 24
Finished Jul 06 05:40:27 PM PDT 24
Peak memory 217812 kb
Host smart-ab96f989-4d83-4056-9ba6-33133a5f4e47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618680449 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1618680449
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1797123715
Short name T337
Test name
Test status
Simulation time 10485334279 ps
CPU time 47.93 seconds
Started Jul 06 05:40:25 PM PDT 24
Finished Jul 06 05:41:13 PM PDT 24
Peak memory 893980 kb
Host smart-1a20d2a7-8989-40d2-9c03-5d3a6ae35fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797123715 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1797123715
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1115982798
Short name T84
Test name
Test status
Simulation time 1122953632 ps
CPU time 44.89 seconds
Started Jul 06 05:40:22 PM PDT 24
Finished Jul 06 05:41:07 PM PDT 24
Peak memory 205008 kb
Host smart-ff5bff0d-283b-4282-9bb9-aa8dbb469056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115982798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1115982798
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.542477378
Short name T542
Test name
Test status
Simulation time 2673626792 ps
CPU time 10.76 seconds
Started Jul 06 05:40:25 PM PDT 24
Finished Jul 06 05:40:36 PM PDT 24
Peak memory 208904 kb
Host smart-a1632a6c-5d2c-48d9-9444-80be0e811479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542477378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.542477378
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2363618359
Short name T1479
Test name
Test status
Simulation time 41425986809 ps
CPU time 647.19 seconds
Started Jul 06 05:40:22 PM PDT 24
Finished Jul 06 05:51:09 PM PDT 24
Peak memory 5469608 kb
Host smart-906bc4b9-9641-4a40-a5de-3545d22608cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363618359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2363618359
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3895149577
Short name T1503
Test name
Test status
Simulation time 293986370 ps
CPU time 2.24 seconds
Started Jul 06 05:40:24 PM PDT 24
Finished Jul 06 05:40:26 PM PDT 24
Peak memory 214900 kb
Host smart-bf6f483b-7cb4-45e7-b25a-c8a497eafd37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895149577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3895149577
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3482270393
Short name T711
Test name
Test status
Simulation time 1199841370 ps
CPU time 6.94 seconds
Started Jul 06 05:40:29 PM PDT 24
Finished Jul 06 05:40:37 PM PDT 24
Peak memory 220884 kb
Host smart-9dbd5c26-0e9f-413b-be14-ac16a3bbdc85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482270393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3482270393
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.1957727394
Short name T988
Test name
Test status
Simulation time 138213674 ps
CPU time 2.94 seconds
Started Jul 06 05:40:30 PM PDT 24
Finished Jul 06 05:40:34 PM PDT 24
Peak memory 204960 kb
Host smart-d58dbbaa-e5c8-4262-a2ab-28c511b4602d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957727394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.1957727394
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3740175602
Short name T152
Test name
Test status
Simulation time 15717457 ps
CPU time 0.62 seconds
Started Jul 06 05:40:39 PM PDT 24
Finished Jul 06 05:40:40 PM PDT 24
Peak memory 204548 kb
Host smart-b7fdfb16-a4d3-48f0-aae4-d45923b751b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740175602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3740175602
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3326166597
Short name T359
Test name
Test status
Simulation time 1221370930 ps
CPU time 5.03 seconds
Started Jul 06 05:40:36 PM PDT 24
Finished Jul 06 05:40:41 PM PDT 24
Peak memory 233888 kb
Host smart-de3798d6-4787-4d0f-a818-3d5d1cfba543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326166597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3326166597
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3333111996
Short name T706
Test name
Test status
Simulation time 1974784708 ps
CPU time 19.9 seconds
Started Jul 06 05:40:31 PM PDT 24
Finished Jul 06 05:40:52 PM PDT 24
Peak memory 285544 kb
Host smart-5f20f095-2d75-430c-83c6-56deebe45293
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333111996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3333111996
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.866019677
Short name T531
Test name
Test status
Simulation time 17785483071 ps
CPU time 55.82 seconds
Started Jul 06 05:40:35 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 561092 kb
Host smart-44a52658-edb1-4780-8b9c-bd2a5676ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866019677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.866019677
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3203548604
Short name T1478
Test name
Test status
Simulation time 4104801325 ps
CPU time 61.96 seconds
Started Jul 06 05:40:30 PM PDT 24
Finished Jul 06 05:41:33 PM PDT 24
Peak memory 678124 kb
Host smart-8bd011e8-582a-4ee5-8777-06aa34bffcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203548604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3203548604
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2394537883
Short name T1249
Test name
Test status
Simulation time 817950630 ps
CPU time 0.91 seconds
Started Jul 06 05:40:29 PM PDT 24
Finished Jul 06 05:40:30 PM PDT 24
Peak memory 204752 kb
Host smart-2769710f-fa99-4e07-b129-ae7c20c1c56c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394537883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2394537883
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2030146249
Short name T1016
Test name
Test status
Simulation time 747475736 ps
CPU time 4.51 seconds
Started Jul 06 05:40:35 PM PDT 24
Finished Jul 06 05:40:40 PM PDT 24
Peak memory 204940 kb
Host smart-ebad36fc-efe5-4110-9f80-d9651366bbf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030146249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2030146249
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3921867217
Short name T95
Test name
Test status
Simulation time 4226612270 ps
CPU time 111.55 seconds
Started Jul 06 05:40:31 PM PDT 24
Finished Jul 06 05:42:23 PM PDT 24
Peak memory 1260032 kb
Host smart-b2015c75-903d-41c2-9f78-28dfb51b5815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921867217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3921867217
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.4244368754
Short name T719
Test name
Test status
Simulation time 326793496 ps
CPU time 4.16 seconds
Started Jul 06 05:40:40 PM PDT 24
Finished Jul 06 05:40:45 PM PDT 24
Peak memory 205092 kb
Host smart-8806adc5-2b0a-475a-8c22-68ef86fbfa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244368754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.4244368754
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2030463595
Short name T550
Test name
Test status
Simulation time 9805776640 ps
CPU time 38.41 seconds
Started Jul 06 05:40:40 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 408496 kb
Host smart-ee8617fb-49bf-43e6-9ce0-43b602abbf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030463595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2030463595
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.304585147
Short name T1102
Test name
Test status
Simulation time 55062349 ps
CPU time 0.64 seconds
Started Jul 06 05:40:31 PM PDT 24
Finished Jul 06 05:40:32 PM PDT 24
Peak memory 204736 kb
Host smart-194e30b2-f3b6-453a-9b66-df5a9dbb98ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304585147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.304585147
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3930281741
Short name T586
Test name
Test status
Simulation time 4929998488 ps
CPU time 162.4 seconds
Started Jul 06 05:40:38 PM PDT 24
Finished Jul 06 05:43:20 PM PDT 24
Peak memory 550060 kb
Host smart-c9c81245-634b-4056-98c6-2f38085cdcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930281741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3930281741
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.3717838967
Short name T312
Test name
Test status
Simulation time 5839906543 ps
CPU time 238.09 seconds
Started Jul 06 05:40:37 PM PDT 24
Finished Jul 06 05:44:35 PM PDT 24
Peak memory 213284 kb
Host smart-ce7e072b-bdef-43b6-a5a0-00f922d74c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717838967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.3717838967
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3755825907
Short name T1053
Test name
Test status
Simulation time 7511946798 ps
CPU time 94.01 seconds
Started Jul 06 05:40:31 PM PDT 24
Finished Jul 06 05:42:06 PM PDT 24
Peak memory 359980 kb
Host smart-945b1375-f1a8-4df0-a647-b9cd4054a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755825907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3755825907
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1079067597
Short name T948
Test name
Test status
Simulation time 494933649 ps
CPU time 8.35 seconds
Started Jul 06 05:40:35 PM PDT 24
Finished Jul 06 05:40:43 PM PDT 24
Peak memory 213232 kb
Host smart-9a91d6a3-80c3-48d6-bbb8-acc731e6c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079067597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1079067597
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2265209160
Short name T1129
Test name
Test status
Simulation time 3881813862 ps
CPU time 3.86 seconds
Started Jul 06 05:40:38 PM PDT 24
Finished Jul 06 05:40:42 PM PDT 24
Peak memory 205068 kb
Host smart-61cec956-b966-462d-ba28-9bec2425b34e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265209160 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2265209160
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1194609096
Short name T1163
Test name
Test status
Simulation time 263670762 ps
CPU time 1.65 seconds
Started Jul 06 05:40:38 PM PDT 24
Finished Jul 06 05:40:40 PM PDT 24
Peak memory 204904 kb
Host smart-f77f9e80-64fe-4a1d-a021-b64c77770726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194609096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1194609096
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2659313722
Short name T324
Test name
Test status
Simulation time 624135888 ps
CPU time 1.22 seconds
Started Jul 06 05:40:40 PM PDT 24
Finished Jul 06 05:40:41 PM PDT 24
Peak memory 213028 kb
Host smart-9cf80a14-28fe-49cf-9656-06bc56ff7885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659313722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2659313722
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.1936512826
Short name T1245
Test name
Test status
Simulation time 3256579540 ps
CPU time 3.06 seconds
Started Jul 06 05:40:40 PM PDT 24
Finished Jul 06 05:40:43 PM PDT 24
Peak memory 205024 kb
Host smart-2a84fe1f-db6c-4927-bcc3-87b2be30e2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936512826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.1936512826
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.868547632
Short name T1225
Test name
Test status
Simulation time 139090300 ps
CPU time 1.27 seconds
Started Jul 06 05:40:42 PM PDT 24
Finished Jul 06 05:40:44 PM PDT 24
Peak memory 204820 kb
Host smart-c6927389-019c-4461-8023-5fd74c276f74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868547632 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.868547632
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.58810981
Short name T1413
Test name
Test status
Simulation time 1480900032 ps
CPU time 7.36 seconds
Started Jul 06 05:40:38 PM PDT 24
Finished Jul 06 05:40:45 PM PDT 24
Peak memory 221244 kb
Host smart-ca5a3e18-7163-4e99-9a2b-19dec21e1138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58810981 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.58810981
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.852108560
Short name T1411
Test name
Test status
Simulation time 18274239156 ps
CPU time 39.29 seconds
Started Jul 06 05:40:40 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 1049836 kb
Host smart-977bf4f7-fd3b-4b00-a1d3-16e3b3df3864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852108560 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.852108560
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1731568200
Short name T1458
Test name
Test status
Simulation time 5539582094 ps
CPU time 53.54 seconds
Started Jul 06 05:40:34 PM PDT 24
Finished Jul 06 05:41:28 PM PDT 24
Peak memory 205140 kb
Host smart-b863dbeb-3026-41b8-ac70-5b447ea422cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731568200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1731568200
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.4187592168
Short name T543
Test name
Test status
Simulation time 4943400630 ps
CPU time 20.59 seconds
Started Jul 06 05:40:35 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 205152 kb
Host smart-6fa8ab1a-6bb6-40ed-a446-bdedf32db214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187592168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.4187592168
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1156475685
Short name T1063
Test name
Test status
Simulation time 41461114413 ps
CPU time 653.78 seconds
Started Jul 06 05:40:36 PM PDT 24
Finished Jul 06 05:51:30 PM PDT 24
Peak memory 5641060 kb
Host smart-2b50b279-0fa7-4455-b47e-2d998dd30697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156475685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1156475685
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1293706515
Short name T411
Test name
Test status
Simulation time 12794012107 ps
CPU time 6.99 seconds
Started Jul 06 05:40:39 PM PDT 24
Finished Jul 06 05:40:46 PM PDT 24
Peak memory 219164 kb
Host smart-b808af1f-90f5-479d-8e7b-64a2be463b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293706515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1293706515
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1178541103
Short name T630
Test name
Test status
Simulation time 224149962 ps
CPU time 3.1 seconds
Started Jul 06 05:40:43 PM PDT 24
Finished Jul 06 05:40:46 PM PDT 24
Peak memory 205020 kb
Host smart-6f03037c-aa42-474d-8288-2390077360a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178541103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1178541103
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1595028158
Short name T1336
Test name
Test status
Simulation time 39975367 ps
CPU time 0.64 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:40:55 PM PDT 24
Peak memory 204528 kb
Host smart-72effe9b-0eda-44cd-a07b-4ca8f9ffd6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595028158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1595028158
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.221744171
Short name T718
Test name
Test status
Simulation time 643434366 ps
CPU time 10.88 seconds
Started Jul 06 05:40:44 PM PDT 24
Finished Jul 06 05:40:55 PM PDT 24
Peak memory 221368 kb
Host smart-578ac607-2f42-40cd-a8eb-60fc3becbb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221744171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.221744171
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2373717249
Short name T539
Test name
Test status
Simulation time 601495953 ps
CPU time 15.03 seconds
Started Jul 06 05:40:43 PM PDT 24
Finished Jul 06 05:40:58 PM PDT 24
Peak memory 241908 kb
Host smart-83139d30-5bdd-4cb0-bb8c-4c7abd8f2ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373717249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2373717249
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1880958331
Short name T73
Test name
Test status
Simulation time 2605244037 ps
CPU time 83.91 seconds
Started Jul 06 05:40:44 PM PDT 24
Finished Jul 06 05:42:09 PM PDT 24
Peak memory 841212 kb
Host smart-176eac53-a98c-4cdf-9182-d89e12dfbec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880958331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1880958331
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3149611730
Short name T605
Test name
Test status
Simulation time 2388243911 ps
CPU time 173.76 seconds
Started Jul 06 05:40:43 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 751356 kb
Host smart-cdbe463a-8b4c-4d56-966d-c2e30a0edff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149611730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3149611730
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1167215427
Short name T817
Test name
Test status
Simulation time 106217723 ps
CPU time 1.11 seconds
Started Jul 06 05:40:43 PM PDT 24
Finished Jul 06 05:40:44 PM PDT 24
Peak memory 204756 kb
Host smart-fa42b5f8-8d36-41d9-a41c-7c98945b0227
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167215427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1167215427
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2850435773
Short name T1445
Test name
Test status
Simulation time 534785629 ps
CPU time 3.56 seconds
Started Jul 06 05:40:44 PM PDT 24
Finished Jul 06 05:40:48 PM PDT 24
Peak memory 204944 kb
Host smart-4fd7357d-f133-4483-99ea-f0e4c7dcb2b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850435773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2850435773
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3077269855
Short name T1065
Test name
Test status
Simulation time 5009673916 ps
CPU time 154.26 seconds
Started Jul 06 05:40:42 PM PDT 24
Finished Jul 06 05:43:17 PM PDT 24
Peak memory 1447476 kb
Host smart-231dabf1-4310-41f2-857b-89fd9fde44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077269855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3077269855
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.4132077961
Short name T720
Test name
Test status
Simulation time 505745380 ps
CPU time 7.75 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:41:02 PM PDT 24
Peak memory 205036 kb
Host smart-be0cb878-4581-420b-ad54-3242a4c8132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132077961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.4132077961
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2078637948
Short name T1434
Test name
Test status
Simulation time 1772063815 ps
CPU time 81.81 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:42:16 PM PDT 24
Peak memory 348344 kb
Host smart-2727e5ed-90b1-4126-ae10-403355949de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078637948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2078637948
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1598406477
Short name T338
Test name
Test status
Simulation time 20255022 ps
CPU time 0.69 seconds
Started Jul 06 05:40:47 PM PDT 24
Finished Jul 06 05:40:48 PM PDT 24
Peak memory 204740 kb
Host smart-0d6072ee-2a88-4d3b-983d-f52b7f2737f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598406477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1598406477
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.364232950
Short name T580
Test name
Test status
Simulation time 3561210087 ps
CPU time 20.71 seconds
Started Jul 06 05:40:45 PM PDT 24
Finished Jul 06 05:41:06 PM PDT 24
Peak memory 217304 kb
Host smart-e1a190dd-9d2d-469e-b8e9-1a3ee42c9b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364232950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.364232950
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.119784161
Short name T275
Test name
Test status
Simulation time 70958909 ps
CPU time 1.26 seconds
Started Jul 06 05:40:47 PM PDT 24
Finished Jul 06 05:40:48 PM PDT 24
Peak memory 214100 kb
Host smart-8fcdb10f-6e6b-4732-b9db-b6636c0a43f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119784161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.119784161
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.4042863630
Short name T1244
Test name
Test status
Simulation time 3914186375 ps
CPU time 103.75 seconds
Started Jul 06 05:40:45 PM PDT 24
Finished Jul 06 05:42:29 PM PDT 24
Peak memory 492556 kb
Host smart-75650b6a-750b-4704-bc78-da6908761250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042863630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.4042863630
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.4008097033
Short name T255
Test name
Test status
Simulation time 39539862760 ps
CPU time 342.62 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:46:32 PM PDT 24
Peak memory 1862672 kb
Host smart-a3ad69e5-61e0-4bf4-9dc1-cfabcb3afb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008097033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.4008097033
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.118652575
Short name T623
Test name
Test status
Simulation time 1314555326 ps
CPU time 35.69 seconds
Started Jul 06 05:40:45 PM PDT 24
Finished Jul 06 05:41:21 PM PDT 24
Peak memory 213220 kb
Host smart-4f8cffeb-15b6-4b44-b181-5cfad892a15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118652575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.118652575
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3621904984
Short name T532
Test name
Test status
Simulation time 1669107818 ps
CPU time 5.88 seconds
Started Jul 06 05:40:48 PM PDT 24
Finished Jul 06 05:40:54 PM PDT 24
Peak memory 213268 kb
Host smart-6f41f255-f025-4a72-b7e3-f2da21e09b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621904984 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3621904984
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2521399756
Short name T900
Test name
Test status
Simulation time 620944410 ps
CPU time 1.3 seconds
Started Jul 06 05:40:50 PM PDT 24
Finished Jul 06 05:40:52 PM PDT 24
Peak memory 204840 kb
Host smart-b71b4f34-ddbd-463c-a681-e592097a9d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521399756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2521399756
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2117087836
Short name T903
Test name
Test status
Simulation time 267931500 ps
CPU time 1.55 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:40:50 PM PDT 24
Peak memory 204836 kb
Host smart-a64fb02c-9eba-495d-b207-c6e1ff6776da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117087836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2117087836
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.1947192581
Short name T645
Test name
Test status
Simulation time 542885650 ps
CPU time 2.85 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:40:57 PM PDT 24
Peak memory 205020 kb
Host smart-972b282b-6dc2-4025-bc5d-3c211993c84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947192581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1947192581
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2292123649
Short name T924
Test name
Test status
Simulation time 355148095 ps
CPU time 1.36 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 204832 kb
Host smart-9c5d34d6-e0d0-42c3-b979-6f00213a2cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292123649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2292123649
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3457160893
Short name T1040
Test name
Test status
Simulation time 1269188538 ps
CPU time 3.49 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:40:58 PM PDT 24
Peak memory 205148 kb
Host smart-9e0d51eb-ecd6-499b-9fb2-84fa4e5c51ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457160893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3457160893
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.810681398
Short name T672
Test name
Test status
Simulation time 1588619297 ps
CPU time 5.09 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:40:54 PM PDT 24
Peak memory 213128 kb
Host smart-f5886fce-8325-48e9-a823-2a4c70e6382d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810681398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.810681398
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3770253016
Short name T675
Test name
Test status
Simulation time 17365489820 ps
CPU time 40.71 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:41:30 PM PDT 24
Peak memory 1017828 kb
Host smart-5f77b09a-7f6d-41c8-a1ea-5edddc378c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770253016 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3770253016
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.429521714
Short name T33
Test name
Test status
Simulation time 3544285567 ps
CPU time 8.71 seconds
Started Jul 06 05:43:48 PM PDT 24
Finished Jul 06 05:43:57 PM PDT 24
Peak memory 205036 kb
Host smart-c869240f-ab29-4f2a-9f64-9d5ef445dc59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429521714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.429521714
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.994459816
Short name T277
Test name
Test status
Simulation time 1848809407 ps
CPU time 43.63 seconds
Started Jul 06 05:40:47 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 204988 kb
Host smart-cad57ec9-04b8-4292-8724-dc9210455b3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994459816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.994459816
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.956688611
Short name T291
Test name
Test status
Simulation time 11332735227 ps
CPU time 6.58 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 205064 kb
Host smart-5f173a71-e3eb-49fd-a9ce-320f7cdae4ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956688611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.956688611
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2086280960
Short name T735
Test name
Test status
Simulation time 3799127180 ps
CPU time 31.49 seconds
Started Jul 06 05:40:47 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 338624 kb
Host smart-88f49a46-3ea0-48b2-a0cb-bdc93e815e6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086280960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2086280960
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.321403875
Short name T471
Test name
Test status
Simulation time 3037938918 ps
CPU time 7.12 seconds
Started Jul 06 05:40:49 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 213308 kb
Host smart-576a2b66-56ba-41ef-a7ed-af46f6acf883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321403875 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.321403875
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.1574974428
Short name T473
Test name
Test status
Simulation time 156017887 ps
CPU time 3.23 seconds
Started Jul 06 05:40:55 PM PDT 24
Finished Jul 06 05:40:59 PM PDT 24
Peak memory 205052 kb
Host smart-12af434d-923c-4c5b-a63d-429d4da6dca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574974428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1574974428
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2160093085
Short name T1228
Test name
Test status
Simulation time 24348036 ps
CPU time 0.64 seconds
Started Jul 06 05:41:11 PM PDT 24
Finished Jul 06 05:41:12 PM PDT 24
Peak memory 204520 kb
Host smart-bfce0e33-f771-4513-a5e0-8d88bf2315f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160093085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2160093085
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.577055747
Short name T421
Test name
Test status
Simulation time 506504329 ps
CPU time 4.28 seconds
Started Jul 06 05:40:59 PM PDT 24
Finished Jul 06 05:41:04 PM PDT 24
Peak memory 219296 kb
Host smart-40ba289a-4970-41ee-b1e6-c86ee9b05c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577055747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.577055747
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1016906402
Short name T1499
Test name
Test status
Simulation time 935834776 ps
CPU time 10.46 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 303672 kb
Host smart-7affeed6-f2f1-4035-9c30-8d64e18707f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016906402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1016906402
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3517929931
Short name T135
Test name
Test status
Simulation time 2625099951 ps
CPU time 92.21 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:42:26 PM PDT 24
Peak memory 835528 kb
Host smart-851e79d7-7082-4c19-a885-259ff2ae5fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517929931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3517929931
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2192449171
Short name T1157
Test name
Test status
Simulation time 4695761564 ps
CPU time 82.36 seconds
Started Jul 06 05:40:55 PM PDT 24
Finished Jul 06 05:42:18 PM PDT 24
Peak memory 498684 kb
Host smart-1471b912-e787-4747-ade3-6afa0bed258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192449171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2192449171
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2540489401
Short name T371
Test name
Test status
Simulation time 373794419 ps
CPU time 1.12 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 204708 kb
Host smart-9ce0f9a9-2411-46f7-b2a7-cfb143df209f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540489401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2540489401
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.440079217
Short name T347
Test name
Test status
Simulation time 591758053 ps
CPU time 2.79 seconds
Started Jul 06 05:40:56 PM PDT 24
Finished Jul 06 05:40:59 PM PDT 24
Peak memory 204988 kb
Host smart-234f04ff-db7e-4d92-b07c-6884157123f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440079217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
440079217
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.46691312
Short name T452
Test name
Test status
Simulation time 18006820088 ps
CPU time 287.71 seconds
Started Jul 06 05:40:56 PM PDT 24
Finished Jul 06 05:45:44 PM PDT 24
Peak memory 1194760 kb
Host smart-c567ceba-36ed-4ea4-ac92-14c32d6e187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46691312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.46691312
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2238180382
Short name T1483
Test name
Test status
Simulation time 443705896 ps
CPU time 18.97 seconds
Started Jul 06 05:41:04 PM PDT 24
Finished Jul 06 05:41:23 PM PDT 24
Peak memory 204976 kb
Host smart-2d11b57c-9f6e-49dd-ac9a-228ede179440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238180382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2238180382
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2234997304
Short name T1517
Test name
Test status
Simulation time 10789688621 ps
CPU time 116.59 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 441668 kb
Host smart-343bce46-7fec-489a-b038-05c8af64f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234997304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2234997304
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1637898212
Short name T1504
Test name
Test status
Simulation time 28132707 ps
CPU time 0.71 seconds
Started Jul 06 05:40:55 PM PDT 24
Finished Jul 06 05:40:56 PM PDT 24
Peak memory 204692 kb
Host smart-a1369bb8-d6c7-400e-abbf-120f22aab1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637898212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1637898212
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3494641026
Short name T1211
Test name
Test status
Simulation time 7551094912 ps
CPU time 242.14 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:45:00 PM PDT 24
Peak memory 1386040 kb
Host smart-24e6069a-7076-4d05-b1de-8902300b30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494641026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3494641026
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.2701870860
Short name T1486
Test name
Test status
Simulation time 265560963 ps
CPU time 5.81 seconds
Started Jul 06 05:40:59 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 221192 kb
Host smart-e9cb03a4-6239-411f-b116-752591058c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701870860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.2701870860
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1532157955
Short name T282
Test name
Test status
Simulation time 1808864406 ps
CPU time 88.85 seconds
Started Jul 06 05:40:54 PM PDT 24
Finished Jul 06 05:42:23 PM PDT 24
Peak memory 386104 kb
Host smart-15d34ddb-df44-4b41-a547-22b3a7d7a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532157955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1532157955
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3713961270
Short name T259
Test name
Test status
Simulation time 14456689329 ps
CPU time 685.88 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:52:25 PM PDT 24
Peak memory 2401588 kb
Host smart-5455c9b9-68be-46d7-bf3c-100d31837982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713961270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3713961270
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1504762925
Short name T2
Test name
Test status
Simulation time 5051606616 ps
CPU time 15.36 seconds
Started Jul 06 05:40:57 PM PDT 24
Finished Jul 06 05:41:13 PM PDT 24
Peak memory 215248 kb
Host smart-566bc0be-1a56-4881-8a3c-bc13824590dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504762925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1504762925
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2001290366
Short name T1345
Test name
Test status
Simulation time 4290070616 ps
CPU time 4 seconds
Started Jul 06 05:41:05 PM PDT 24
Finished Jul 06 05:41:09 PM PDT 24
Peak memory 213276 kb
Host smart-2ee1b686-ed78-4a0f-b4fe-4239a6ea11be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001290366 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2001290366
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2458693983
Short name T242
Test name
Test status
Simulation time 258592356 ps
CPU time 1.58 seconds
Started Jul 06 05:41:03 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 205028 kb
Host smart-d4ee87f9-dc40-4560-8805-c9209f4ca5b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458693983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2458693983
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.456159464
Short name T351
Test name
Test status
Simulation time 190185330 ps
CPU time 1.2 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:41:09 PM PDT 24
Peak memory 204840 kb
Host smart-9b25d56f-fd3d-4d71-b7b0-f3b882881230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456159464 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.456159464
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.3313911980
Short name T17
Test name
Test status
Simulation time 1902107899 ps
CPU time 2.55 seconds
Started Jul 06 05:41:02 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 204984 kb
Host smart-e80d0f50-b718-4922-9e62-6f83292a8db7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313911980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.3313911980
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.273701013
Short name T738
Test name
Test status
Simulation time 468986684 ps
CPU time 1.14 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:41:10 PM PDT 24
Peak memory 204788 kb
Host smart-e740965f-dce3-48b3-9eac-41f954b71cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273701013 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.273701013
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1451786880
Short name T1414
Test name
Test status
Simulation time 3580402835 ps
CPU time 6.15 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 205136 kb
Host smart-f356a8c1-e284-4c4a-b132-616c341e63f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451786880 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1451786880
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.640248077
Short name T663
Test name
Test status
Simulation time 15869534561 ps
CPU time 277.1 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:45:35 PM PDT 24
Peak memory 3808056 kb
Host smart-7964191a-8c39-40f9-a8e2-77b2875b8afb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640248077 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.640248077
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.4057060137
Short name T1355
Test name
Test status
Simulation time 736770048 ps
CPU time 12.29 seconds
Started Jul 06 05:40:59 PM PDT 24
Finished Jul 06 05:41:11 PM PDT 24
Peak memory 205044 kb
Host smart-59856d19-1994-4392-ab81-fe80569c4c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057060137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.4057060137
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3670009766
Short name T818
Test name
Test status
Simulation time 215106518 ps
CPU time 8.21 seconds
Started Jul 06 05:40:59 PM PDT 24
Finished Jul 06 05:41:08 PM PDT 24
Peak memory 204972 kb
Host smart-d4abd308-fbfd-49f0-a1f9-582d4a81a9d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670009766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3670009766
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2008551801
Short name T627
Test name
Test status
Simulation time 6816577010 ps
CPU time 7.31 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:41:06 PM PDT 24
Peak memory 204848 kb
Host smart-c4e856ee-e6db-4101-bb85-4b7e15beae9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008551801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2008551801
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.587118476
Short name T522
Test name
Test status
Simulation time 1409426545 ps
CPU time 9.54 seconds
Started Jul 06 05:40:58 PM PDT 24
Finished Jul 06 05:41:08 PM PDT 24
Peak memory 332404 kb
Host smart-f08ff23f-fbf3-4d23-94b7-90cc586429b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587118476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.587118476
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.547970709
Short name T435
Test name
Test status
Simulation time 5988378762 ps
CPU time 8 seconds
Started Jul 06 05:41:04 PM PDT 24
Finished Jul 06 05:41:12 PM PDT 24
Peak memory 219684 kb
Host smart-0446b8f4-dfc0-4d3c-b12c-4173fb4ae382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547970709 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.547970709
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.3197125201
Short name T1255
Test name
Test status
Simulation time 228061817 ps
CPU time 3.74 seconds
Started Jul 06 05:41:15 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 204944 kb
Host smart-2bd0c00b-90d6-4ede-b73b-55efd32bb070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197125201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.3197125201
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.550768464
Short name T1117
Test name
Test status
Simulation time 16156358 ps
CPU time 0.65 seconds
Started Jul 06 05:41:20 PM PDT 24
Finished Jul 06 05:41:21 PM PDT 24
Peak memory 204540 kb
Host smart-4d4d1bf9-b07e-45d7-a2f0-91f8cd729ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550768464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.550768464
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3661586213
Short name T517
Test name
Test status
Simulation time 2701142445 ps
CPU time 6.89 seconds
Started Jul 06 05:41:14 PM PDT 24
Finished Jul 06 05:41:21 PM PDT 24
Peak memory 232476 kb
Host smart-f4e62a21-aa1d-439f-8142-fdc64a23efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661586213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3661586213
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3319473846
Short name T644
Test name
Test status
Simulation time 550471978 ps
CPU time 12.27 seconds
Started Jul 06 05:41:11 PM PDT 24
Finished Jul 06 05:41:24 PM PDT 24
Peak memory 315568 kb
Host smart-8380880f-5c1a-446c-96d9-e108bebf61c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319473846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3319473846
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3236071675
Short name T1006
Test name
Test status
Simulation time 1568130078 ps
CPU time 91.56 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:42:40 PM PDT 24
Peak memory 498000 kb
Host smart-13ea20cf-e6f8-4c55-b333-d99df6d82956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236071675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3236071675
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1514284277
Short name T918
Test name
Test status
Simulation time 7448893142 ps
CPU time 36.37 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:41:45 PM PDT 24
Peak memory 540672 kb
Host smart-b6a39a31-80be-403e-8ba7-6ebeb5e4b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514284277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1514284277
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2163436148
Short name T1150
Test name
Test status
Simulation time 593669758 ps
CPU time 1.08 seconds
Started Jul 06 05:41:11 PM PDT 24
Finished Jul 06 05:41:12 PM PDT 24
Peak memory 204652 kb
Host smart-8100598b-b959-419e-8554-8780af9365cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163436148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2163436148
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3629121850
Short name T213
Test name
Test status
Simulation time 496903770 ps
CPU time 4.17 seconds
Started Jul 06 05:41:09 PM PDT 24
Finished Jul 06 05:41:13 PM PDT 24
Peak memory 227752 kb
Host smart-a978bcf1-a20e-487b-a4e6-e5093bca964b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629121850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3629121850
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4078370670
Short name T568
Test name
Test status
Simulation time 17789869247 ps
CPU time 152.04 seconds
Started Jul 06 05:41:07 PM PDT 24
Finished Jul 06 05:43:40 PM PDT 24
Peak memory 1405660 kb
Host smart-c7fb2c48-d71c-4d06-8897-dd58bf288541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078370670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4078370670
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2287642503
Short name T1468
Test name
Test status
Simulation time 722285421 ps
CPU time 9.93 seconds
Started Jul 06 05:41:21 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 204976 kb
Host smart-06d19692-b74d-4484-a68a-8a1a7f3c9e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287642503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2287642503
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3259276755
Short name T915
Test name
Test status
Simulation time 4116144071 ps
CPU time 39.14 seconds
Started Jul 06 05:41:22 PM PDT 24
Finished Jul 06 05:42:01 PM PDT 24
Peak memory 358800 kb
Host smart-dcc378ac-c9a4-4d38-8e55-4a10255f5bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259276755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3259276755
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2008241573
Short name T996
Test name
Test status
Simulation time 16925747 ps
CPU time 0.65 seconds
Started Jul 06 05:41:09 PM PDT 24
Finished Jul 06 05:41:10 PM PDT 24
Peak memory 204640 kb
Host smart-a28e9753-57ea-4ffb-820d-2850192bf4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008241573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2008241573
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3361914017
Short name T354
Test name
Test status
Simulation time 5825774590 ps
CPU time 80.63 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:42:29 PM PDT 24
Peak memory 205100 kb
Host smart-4626d8cf-6e5b-451b-9c0f-525530aad36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361914017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3361914017
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.4026788486
Short name T739
Test name
Test status
Simulation time 6314873379 ps
CPU time 25.29 seconds
Started Jul 06 05:41:08 PM PDT 24
Finished Jul 06 05:41:33 PM PDT 24
Peak memory 337792 kb
Host smart-509fabcd-7ea0-477d-b00b-f5c8a1881365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026788486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.4026788486
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1917791202
Short name T1289
Test name
Test status
Simulation time 303331710137 ps
CPU time 751.83 seconds
Started Jul 06 05:41:12 PM PDT 24
Finished Jul 06 05:53:45 PM PDT 24
Peak memory 2495808 kb
Host smart-efeb13cd-d20f-4567-99f0-df026aca1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917791202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1917791202
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2928919827
Short name T1231
Test name
Test status
Simulation time 837796536 ps
CPU time 14.92 seconds
Started Jul 06 05:41:14 PM PDT 24
Finished Jul 06 05:41:29 PM PDT 24
Peak memory 220780 kb
Host smart-1975b84b-cebe-49c3-97be-c1b8310d8d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928919827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2928919827
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1153161303
Short name T114
Test name
Test status
Simulation time 534449580 ps
CPU time 2.73 seconds
Started Jul 06 05:41:19 PM PDT 24
Finished Jul 06 05:41:22 PM PDT 24
Peak memory 205072 kb
Host smart-f9d18eb2-cd89-49d4-9fe5-f57d3aae47a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153161303 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1153161303
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.397288309
Short name T816
Test name
Test status
Simulation time 110189139 ps
CPU time 0.88 seconds
Started Jul 06 05:41:21 PM PDT 24
Finished Jul 06 05:41:22 PM PDT 24
Peak memory 204824 kb
Host smart-7e52adbb-ba18-45c0-991d-247132c7aa33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397288309 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.397288309
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3729607208
Short name T244
Test name
Test status
Simulation time 202977393 ps
CPU time 1.34 seconds
Started Jul 06 05:41:19 PM PDT 24
Finished Jul 06 05:41:21 PM PDT 24
Peak memory 213164 kb
Host smart-a1ac008e-2bea-4e91-90aa-6f45b8f437e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729607208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3729607208
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.2732527196
Short name T1233
Test name
Test status
Simulation time 970956368 ps
CPU time 2.8 seconds
Started Jul 06 05:41:19 PM PDT 24
Finished Jul 06 05:41:22 PM PDT 24
Peak memory 204988 kb
Host smart-d4777496-19b4-44da-9802-a52b982aeece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732527196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.2732527196
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3703223542
Short name T358
Test name
Test status
Simulation time 126069030 ps
CPU time 0.94 seconds
Started Jul 06 05:41:19 PM PDT 24
Finished Jul 06 05:41:20 PM PDT 24
Peak memory 204792 kb
Host smart-20a7686b-8072-4dc7-9e9f-127eff3dfeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703223542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3703223542
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2124712344
Short name T1397
Test name
Test status
Simulation time 327662909 ps
CPU time 2.49 seconds
Started Jul 06 05:41:20 PM PDT 24
Finished Jul 06 05:41:22 PM PDT 24
Peak memory 205036 kb
Host smart-c457efae-a9e7-4b66-b43c-d2ceae3a6007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124712344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2124712344
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3300680781
Short name T501
Test name
Test status
Simulation time 6585234636 ps
CPU time 5.79 seconds
Started Jul 06 05:41:13 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 213236 kb
Host smart-fe500a3f-cce6-4419-9ebb-76a4ffe36073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300680781 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3300680781
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.392109367
Short name T702
Test name
Test status
Simulation time 3534213609 ps
CPU time 4.31 seconds
Started Jul 06 05:41:13 PM PDT 24
Finished Jul 06 05:41:17 PM PDT 24
Peak memory 205048 kb
Host smart-9748be98-9cfa-42ff-a814-2597ca681d78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392109367 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.392109367
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2277409736
Short name T670
Test name
Test status
Simulation time 1008635676 ps
CPU time 15.55 seconds
Started Jul 06 05:41:14 PM PDT 24
Finished Jul 06 05:41:30 PM PDT 24
Peak memory 205012 kb
Host smart-6b9fbb10-2580-4329-924b-ae994417f81f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277409736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2277409736
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.905763619
Short name T162
Test name
Test status
Simulation time 7868648855 ps
CPU time 61.53 seconds
Started Jul 06 05:41:13 PM PDT 24
Finished Jul 06 05:42:15 PM PDT 24
Peak memory 208820 kb
Host smart-f54b8b7b-60e1-4b17-8954-a37f850fdb05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905763619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.905763619
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1011122734
Short name T364
Test name
Test status
Simulation time 40838690173 ps
CPU time 43.11 seconds
Started Jul 06 05:41:14 PM PDT 24
Finished Jul 06 05:41:57 PM PDT 24
Peak memory 841748 kb
Host smart-46ecb365-235f-46f3-bbbe-2005255d2bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011122734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1011122734
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.625595818
Short name T1064
Test name
Test status
Simulation time 2442441875 ps
CPU time 3.5 seconds
Started Jul 06 05:41:13 PM PDT 24
Finished Jul 06 05:41:17 PM PDT 24
Peak memory 227608 kb
Host smart-e1e7ebb1-fcb8-4a40-a76a-667d37efec98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625595818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.625595818
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3160692765
Short name T871
Test name
Test status
Simulation time 3128377978 ps
CPU time 8.22 seconds
Started Jul 06 05:41:19 PM PDT 24
Finished Jul 06 05:41:28 PM PDT 24
Peak memory 221324 kb
Host smart-8a645943-894b-46b7-be4f-3944dfba228e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160692765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3160692765
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.2451892045
Short name T968
Test name
Test status
Simulation time 248641818 ps
CPU time 3.93 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:41:27 PM PDT 24
Peak memory 205064 kb
Host smart-03f25517-4b67-488a-96da-98857b7f3929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451892045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2451892045
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3803667587
Short name T1450
Test name
Test status
Simulation time 15903685 ps
CPU time 0.62 seconds
Started Jul 06 05:41:33 PM PDT 24
Finished Jul 06 05:41:34 PM PDT 24
Peak memory 204628 kb
Host smart-5ccd01fd-62ca-4cac-b100-42b6e4af16f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803667587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3803667587
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2097035903
Short name T1441
Test name
Test status
Simulation time 1092394402 ps
CPU time 10.46 seconds
Started Jul 06 05:41:25 PM PDT 24
Finished Jul 06 05:41:35 PM PDT 24
Peak memory 250060 kb
Host smart-79599d24-573b-4d43-8292-b8eebc1bca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097035903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2097035903
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3390764237
Short name T1327
Test name
Test status
Simulation time 233944101 ps
CPU time 12.29 seconds
Started Jul 06 05:41:25 PM PDT 24
Finished Jul 06 05:41:37 PM PDT 24
Peak memory 251940 kb
Host smart-f1adcad5-6b9e-4de2-9a6a-e8b93b65ee92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390764237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3390764237
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3099795087
Short name T815
Test name
Test status
Simulation time 1303614563 ps
CPU time 81.84 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:42:46 PM PDT 24
Peak memory 516848 kb
Host smart-3973e4fe-8c61-4de4-b63d-278e90663f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099795087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3099795087
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3954662719
Short name T83
Test name
Test status
Simulation time 24356075279 ps
CPU time 101.74 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 843816 kb
Host smart-483c976e-9143-42c7-8a3b-0d92c7eea0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954662719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3954662719
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3535134628
Short name T1283
Test name
Test status
Simulation time 1303842829 ps
CPU time 1.33 seconds
Started Jul 06 05:41:25 PM PDT 24
Finished Jul 06 05:41:26 PM PDT 24
Peak memory 204932 kb
Host smart-d7034812-b8a7-4d12-bdee-ec9955aeb344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535134628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3535134628
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1340283556
Short name T1050
Test name
Test status
Simulation time 249369353 ps
CPU time 10.72 seconds
Started Jul 06 05:41:24 PM PDT 24
Finished Jul 06 05:41:35 PM PDT 24
Peak memory 205004 kb
Host smart-808dfa6b-6c69-470f-b921-01117144d36d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340283556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1340283556
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.426672469
Short name T664
Test name
Test status
Simulation time 13424294999 ps
CPU time 95.8 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:42:59 PM PDT 24
Peak memory 1010684 kb
Host smart-b41c72e8-81b1-4372-950b-fc04d04a4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426672469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.426672469
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3263206190
Short name T691
Test name
Test status
Simulation time 437432548 ps
CPU time 6.8 seconds
Started Jul 06 05:41:30 PM PDT 24
Finished Jul 06 05:41:38 PM PDT 24
Peak memory 205080 kb
Host smart-f05ba500-8a01-4a62-8fbc-905e150198d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263206190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3263206190
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.1660730337
Short name T560
Test name
Test status
Simulation time 44373576 ps
CPU time 0.68 seconds
Started Jul 06 05:41:26 PM PDT 24
Finished Jul 06 05:41:27 PM PDT 24
Peak memory 204728 kb
Host smart-f2ff0f8a-893c-4487-a40a-adb0c1d8e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660730337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1660730337
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.2466909384
Short name T758
Test name
Test status
Simulation time 802926452 ps
CPU time 7.65 seconds
Started Jul 06 05:41:27 PM PDT 24
Finished Jul 06 05:41:34 PM PDT 24
Peak memory 290736 kb
Host smart-d804e936-78fd-4cb5-8710-aa74cff96f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466909384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.2466909384
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2321084267
Short name T115
Test name
Test status
Simulation time 4622471275 ps
CPU time 17.3 seconds
Started Jul 06 05:41:22 PM PDT 24
Finished Jul 06 05:41:40 PM PDT 24
Peak memory 304316 kb
Host smart-e5ccccf0-a63f-49c9-a4e9-84193551f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321084267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2321084267
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.3065726743
Short name T98
Test name
Test status
Simulation time 43610135096 ps
CPU time 251.28 seconds
Started Jul 06 05:41:24 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 1645696 kb
Host smart-66e87101-0d8d-4f5d-a6be-b551facbdeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065726743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.3065726743
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1808557530
Short name T1351
Test name
Test status
Simulation time 750998107 ps
CPU time 3.64 seconds
Started Jul 06 05:41:29 PM PDT 24
Finished Jul 06 05:41:33 PM PDT 24
Peak memory 205008 kb
Host smart-303a0653-497b-4314-9293-92af9d1c7593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808557530 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1808557530
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.728072455
Short name T1284
Test name
Test status
Simulation time 321684953 ps
CPU time 0.9 seconds
Started Jul 06 05:41:30 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 204792 kb
Host smart-bd2fe58c-2aaf-450d-a8b9-1d37ea7bc53c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728072455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.728072455
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.351597134
Short name T403
Test name
Test status
Simulation time 187930219 ps
CPU time 0.96 seconds
Started Jul 06 05:41:29 PM PDT 24
Finished Jul 06 05:41:30 PM PDT 24
Peak memory 204816 kb
Host smart-4903510c-000b-4160-9a86-0af2fffaa2d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351597134 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.351597134
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3906906172
Short name T1161
Test name
Test status
Simulation time 815488384 ps
CPU time 1.8 seconds
Started Jul 06 05:41:36 PM PDT 24
Finished Jul 06 05:41:38 PM PDT 24
Peak memory 204708 kb
Host smart-3c0ff397-deeb-4d43-8da8-bb7e216747ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906906172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3906906172
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.1860765702
Short name T19
Test name
Test status
Simulation time 86920674 ps
CPU time 0.96 seconds
Started Jul 06 05:41:36 PM PDT 24
Finished Jul 06 05:41:37 PM PDT 24
Peak memory 204720 kb
Host smart-8a177910-7c93-4dac-a3ee-055b95b7dd79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860765702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.1860765702
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2712312326
Short name T715
Test name
Test status
Simulation time 513316785 ps
CPU time 2.83 seconds
Started Jul 06 05:41:29 PM PDT 24
Finished Jul 06 05:41:32 PM PDT 24
Peak memory 205084 kb
Host smart-e777357e-f05d-4b7e-aa6d-060a9aa332f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712312326 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2712312326
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1518741004
Short name T874
Test name
Test status
Simulation time 757668395 ps
CPU time 4.45 seconds
Started Jul 06 05:41:29 PM PDT 24
Finished Jul 06 05:41:33 PM PDT 24
Peak memory 205024 kb
Host smart-6561fb75-694c-408a-bc80-1bf72b83d1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518741004 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1518741004
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1384171442
Short name T408
Test name
Test status
Simulation time 15813433002 ps
CPU time 191.75 seconds
Started Jul 06 05:41:31 PM PDT 24
Finished Jul 06 05:44:43 PM PDT 24
Peak memory 2345676 kb
Host smart-dcdf467b-b4da-4f24-8d1f-52e4a4c38269
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384171442 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1384171442
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.341123406
Short name T1502
Test name
Test status
Simulation time 16680631619 ps
CPU time 12.28 seconds
Started Jul 06 05:41:26 PM PDT 24
Finished Jul 06 05:41:38 PM PDT 24
Peak memory 204932 kb
Host smart-d5ff031e-49cc-4019-91ca-b3198568ea8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341123406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.341123406
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.964241597
Short name T762
Test name
Test status
Simulation time 325982998 ps
CPU time 5.17 seconds
Started Jul 06 05:41:23 PM PDT 24
Finished Jul 06 05:41:28 PM PDT 24
Peak memory 205024 kb
Host smart-0b088cdd-6f8e-4af6-9d6c-5814c7eec45b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964241597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.964241597
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2506468498
Short name T831
Test name
Test status
Simulation time 55614644961 ps
CPU time 123.37 seconds
Started Jul 06 05:41:25 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 1589456 kb
Host smart-e13c717b-a053-48d1-bdb3-d4ec1fd7f1dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506468498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2506468498
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2986214045
Short name T1080
Test name
Test status
Simulation time 4673760836 ps
CPU time 6.17 seconds
Started Jul 06 05:41:30 PM PDT 24
Finished Jul 06 05:41:36 PM PDT 24
Peak memory 211220 kb
Host smart-b55d8827-7103-4928-aad3-87d31f475d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986214045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2986214045
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3185170215
Short name T71
Test name
Test status
Simulation time 1595081063 ps
CPU time 7.99 seconds
Started Jul 06 05:41:31 PM PDT 24
Finished Jul 06 05:41:39 PM PDT 24
Peak memory 213272 kb
Host smart-e9d049b1-36ca-4a97-83a6-42821f0222f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185170215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3185170215
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.463086476
Short name T290
Test name
Test status
Simulation time 356582123 ps
CPU time 4.98 seconds
Started Jul 06 05:41:33 PM PDT 24
Finished Jul 06 05:41:38 PM PDT 24
Peak memory 205032 kb
Host smart-ad99cd3c-4af3-48f1-ae77-9ce669faf2f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463086476 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.463086476
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2591016538
Short name T1373
Test name
Test status
Simulation time 16598613 ps
CPU time 0.63 seconds
Started Jul 06 05:41:43 PM PDT 24
Finished Jul 06 05:41:44 PM PDT 24
Peak memory 204616 kb
Host smart-31424907-abb9-4e77-bdbe-521241f35b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591016538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2591016538
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2709634241
Short name T1271
Test name
Test status
Simulation time 118610729 ps
CPU time 3.39 seconds
Started Jul 06 05:41:35 PM PDT 24
Finished Jul 06 05:41:39 PM PDT 24
Peak memory 215940 kb
Host smart-8c1a641b-414b-4369-9e46-845159682ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709634241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2709634241
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.780276698
Short name T1332
Test name
Test status
Simulation time 3152267623 ps
CPU time 5.4 seconds
Started Jul 06 05:41:36 PM PDT 24
Finished Jul 06 05:41:41 PM PDT 24
Peak memory 263368 kb
Host smart-95c33770-8795-4bfd-93f5-99f97f284870
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780276698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.780276698
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.808055769
Short name T800
Test name
Test status
Simulation time 1423955135 ps
CPU time 40.2 seconds
Started Jul 06 05:41:35 PM PDT 24
Finished Jul 06 05:42:15 PM PDT 24
Peak memory 519636 kb
Host smart-303ce8b5-691b-49aa-a63c-29561d9dbca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808055769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.808055769
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3929083892
Short name T508
Test name
Test status
Simulation time 1936454227 ps
CPU time 60.75 seconds
Started Jul 06 05:41:34 PM PDT 24
Finished Jul 06 05:42:35 PM PDT 24
Peak memory 623108 kb
Host smart-28cc5852-2122-47de-bcf6-b2090d1f2084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929083892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3929083892
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3915209695
Short name T686
Test name
Test status
Simulation time 213510184 ps
CPU time 0.98 seconds
Started Jul 06 05:41:35 PM PDT 24
Finished Jul 06 05:41:36 PM PDT 24
Peak memory 204764 kb
Host smart-ebfe8b70-a154-4bb1-ba2e-701238793f3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915209695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3915209695
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2585952780
Short name T396
Test name
Test status
Simulation time 1216916097 ps
CPU time 6.35 seconds
Started Jul 06 05:41:36 PM PDT 24
Finished Jul 06 05:41:42 PM PDT 24
Peak memory 205048 kb
Host smart-ce537316-773a-4c75-9310-b32e2a9ce7d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585952780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2585952780
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3171515019
Short name T781
Test name
Test status
Simulation time 26822755924 ps
CPU time 120.19 seconds
Started Jul 06 05:41:33 PM PDT 24
Finished Jul 06 05:43:33 PM PDT 24
Peak memory 1144208 kb
Host smart-5e8df734-8a8f-4b79-8370-59f4f7bfa609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171515019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3171515019
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.4189621183
Short name T1131
Test name
Test status
Simulation time 1807989024 ps
CPU time 7.62 seconds
Started Jul 06 05:41:44 PM PDT 24
Finished Jul 06 05:41:52 PM PDT 24
Peak memory 205052 kb
Host smart-4881c4bc-91fc-42cf-b879-66e36bb8937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189621183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.4189621183
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1830506961
Short name T66
Test name
Test status
Simulation time 5922449721 ps
CPU time 65.17 seconds
Started Jul 06 05:41:44 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 302120 kb
Host smart-e42e8fac-aaa6-47e6-9290-5f41bf4c3e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830506961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1830506961
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3141099760
Short name T1442
Test name
Test status
Simulation time 25733817 ps
CPU time 0.68 seconds
Started Jul 06 05:41:33 PM PDT 24
Finished Jul 06 05:41:34 PM PDT 24
Peak memory 204760 kb
Host smart-c9876644-0723-40f2-8692-23a513bd7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141099760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3141099760
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3756548374
Short name T1341
Test name
Test status
Simulation time 815963033 ps
CPU time 7 seconds
Started Jul 06 05:41:32 PM PDT 24
Finished Jul 06 05:41:40 PM PDT 24
Peak memory 219376 kb
Host smart-ab5fb13a-7359-4705-b348-4584ff9e9a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756548374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3756548374
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.541705354
Short name T376
Test name
Test status
Simulation time 302397031 ps
CPU time 2.71 seconds
Started Jul 06 05:41:34 PM PDT 24
Finished Jul 06 05:41:37 PM PDT 24
Peak memory 204916 kb
Host smart-b00d928c-59e1-4492-a5f6-7f643e89f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541705354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.541705354
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1690347893
Short name T1376
Test name
Test status
Simulation time 4219382123 ps
CPU time 15.22 seconds
Started Jul 06 05:41:33 PM PDT 24
Finished Jul 06 05:41:48 PM PDT 24
Peak memory 300472 kb
Host smart-07bd7cf9-ccfe-4021-8399-6993c66a2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690347893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1690347893
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1534547058
Short name T103
Test name
Test status
Simulation time 6322884394 ps
CPU time 187.44 seconds
Started Jul 06 05:41:34 PM PDT 24
Finished Jul 06 05:44:41 PM PDT 24
Peak memory 1404140 kb
Host smart-f5264632-63a2-45f2-b7fd-a17c9642e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534547058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1534547058
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.977600241
Short name T1347
Test name
Test status
Simulation time 2942104639 ps
CPU time 32.98 seconds
Started Jul 06 05:41:34 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 213272 kb
Host smart-545baa2b-724e-4642-9801-90e17c02f90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977600241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.977600241
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1621602616
Short name T449
Test name
Test status
Simulation time 2543987531 ps
CPU time 2.85 seconds
Started Jul 06 05:41:46 PM PDT 24
Finished Jul 06 05:41:49 PM PDT 24
Peak memory 205080 kb
Host smart-ad9cd6ae-a3a0-42aa-a32a-7e0ce928bd33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621602616 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1621602616
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.811993883
Short name T1164
Test name
Test status
Simulation time 218581948 ps
CPU time 1.4 seconds
Started Jul 06 05:41:42 PM PDT 24
Finished Jul 06 05:41:44 PM PDT 24
Peak memory 205016 kb
Host smart-e7f3e9b1-1393-4499-a4bd-efb0c60b3281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811993883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.811993883
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2118782954
Short name T1415
Test name
Test status
Simulation time 266456788 ps
CPU time 0.82 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:41:46 PM PDT 24
Peak memory 204832 kb
Host smart-0a662250-638b-4036-a76b-ff4d95cca63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118782954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2118782954
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.2038443076
Short name T1446
Test name
Test status
Simulation time 1957195326 ps
CPU time 2.76 seconds
Started Jul 06 05:41:47 PM PDT 24
Finished Jul 06 05:41:50 PM PDT 24
Peak memory 205040 kb
Host smart-9c4107ad-9440-479a-85b8-18a380625ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038443076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.2038443076
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2917415556
Short name T1300
Test name
Test status
Simulation time 140174070 ps
CPU time 1.31 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:41:47 PM PDT 24
Peak memory 204824 kb
Host smart-187e8271-5e21-44b5-80ac-33286333a977
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917415556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2917415556
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.697140927
Short name T1054
Test name
Test status
Simulation time 3707905452 ps
CPU time 5.86 seconds
Started Jul 06 05:41:42 PM PDT 24
Finished Jul 06 05:41:48 PM PDT 24
Peak memory 216956 kb
Host smart-005b60ea-0158-4950-a756-a2dce95b1df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697140927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.697140927
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4177864214
Short name T547
Test name
Test status
Simulation time 17911417983 ps
CPU time 50.89 seconds
Started Jul 06 05:41:40 PM PDT 24
Finished Jul 06 05:42:31 PM PDT 24
Peak memory 1189140 kb
Host smart-31afcdc8-0fa9-42e9-9bdf-a0ec37db4295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177864214 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4177864214
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1535346900
Short name T609
Test name
Test status
Simulation time 2782784300 ps
CPU time 9.9 seconds
Started Jul 06 05:41:40 PM PDT 24
Finished Jul 06 05:41:50 PM PDT 24
Peak memory 205064 kb
Host smart-7af6a3db-c3b2-4c99-b4e3-cff51235c4a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535346900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1535346900
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.582367137
Short name T486
Test name
Test status
Simulation time 706837215 ps
CPU time 13.52 seconds
Started Jul 06 05:41:42 PM PDT 24
Finished Jul 06 05:41:56 PM PDT 24
Peak memory 206932 kb
Host smart-c9471709-c432-45e5-923c-5c494cc1d178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582367137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.582367137
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3969724272
Short name T118
Test name
Test status
Simulation time 39463303690 ps
CPU time 93.98 seconds
Started Jul 06 05:41:42 PM PDT 24
Finished Jul 06 05:43:16 PM PDT 24
Peak memory 1403632 kb
Host smart-ca7edf1d-34ba-4c42-8339-a3125362b28f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969724272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3969724272
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3674850766
Short name T1107
Test name
Test status
Simulation time 162460001 ps
CPU time 1.05 seconds
Started Jul 06 05:41:41 PM PDT 24
Finished Jul 06 05:41:42 PM PDT 24
Peak memory 204832 kb
Host smart-414ccfec-b729-4775-91e8-29f82ac355bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674850766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3674850766
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.832145994
Short name T525
Test name
Test status
Simulation time 1686563367 ps
CPU time 8.04 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:41:53 PM PDT 24
Peak memory 221264 kb
Host smart-c5daea84-698e-4503-b355-66c64f3c28fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832145994 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.832145994
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2606519938
Short name T1002
Test name
Test status
Simulation time 55631105 ps
CPU time 1.44 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:41:47 PM PDT 24
Peak memory 205060 kb
Host smart-42a22c64-a05b-42a8-9a9f-910531746796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606519938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2606519938
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.459117143
Short name T1256
Test name
Test status
Simulation time 47276620 ps
CPU time 0.63 seconds
Started Jul 06 05:41:54 PM PDT 24
Finished Jul 06 05:41:54 PM PDT 24
Peak memory 204632 kb
Host smart-d9243941-1da8-4012-b05b-afe50cdbf454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459117143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.459117143
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1052386709
Short name T1046
Test name
Test status
Simulation time 128615095 ps
CPU time 3.3 seconds
Started Jul 06 05:41:56 PM PDT 24
Finished Jul 06 05:42:00 PM PDT 24
Peak memory 213256 kb
Host smart-01581859-b41f-4948-96db-cdecb8dc62a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052386709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1052386709
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.105205761
Short name T1179
Test name
Test status
Simulation time 392874192 ps
CPU time 7.19 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:41:57 PM PDT 24
Peak memory 287228 kb
Host smart-70f6a58f-2992-46ae-8473-d773b452d825
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105205761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.105205761
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1331228469
Short name T1091
Test name
Test status
Simulation time 9127622208 ps
CPU time 87.33 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:43:17 PM PDT 24
Peak memory 777544 kb
Host smart-d6abe2d4-fa82-4617-ae81-e1cc6017ba9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331228469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1331228469
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.346538196
Short name T1247
Test name
Test status
Simulation time 2127023767 ps
CPU time 63.74 seconds
Started Jul 06 05:41:48 PM PDT 24
Finished Jul 06 05:42:52 PM PDT 24
Peak memory 682844 kb
Host smart-ebfc02f6-1bfb-4de2-becd-1a255b93232d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346538196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.346538196
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2134898340
Short name T323
Test name
Test status
Simulation time 165667989 ps
CPU time 0.97 seconds
Started Jul 06 05:41:44 PM PDT 24
Finished Jul 06 05:41:45 PM PDT 24
Peak memory 204724 kb
Host smart-adb822c8-92e3-4b70-9ab3-7fdac87798ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134898340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2134898340
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3723601184
Short name T752
Test name
Test status
Simulation time 494644801 ps
CPU time 3.06 seconds
Started Jul 06 05:41:48 PM PDT 24
Finished Jul 06 05:41:51 PM PDT 24
Peak memory 205036 kb
Host smart-af37cdfb-3c6a-4c31-97f6-eb2fd29dfcc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723601184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3723601184
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.728513719
Short name T963
Test name
Test status
Simulation time 4079116080 ps
CPU time 273.09 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:46:18 PM PDT 24
Peak memory 1142332 kb
Host smart-9d4a864e-9a1f-454e-a8a7-08084dd8fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728513719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.728513719
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3382223694
Short name T1197
Test name
Test status
Simulation time 4074978189 ps
CPU time 7.21 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:42:06 PM PDT 24
Peak memory 205052 kb
Host smart-1b8697d2-138f-4f3d-90a4-f05766c897ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382223694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3382223694
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.3337988427
Short name T554
Test name
Test status
Simulation time 28249220 ps
CPU time 0.65 seconds
Started Jul 06 05:41:44 PM PDT 24
Finished Jul 06 05:41:45 PM PDT 24
Peak memory 204728 kb
Host smart-379aad47-4331-4c4e-aee6-51d18fd832a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337988427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3337988427
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1159249734
Short name T1456
Test name
Test status
Simulation time 3412105027 ps
CPU time 15.62 seconds
Started Jul 06 05:41:50 PM PDT 24
Finished Jul 06 05:42:06 PM PDT 24
Peak memory 379376 kb
Host smart-fdb94e30-ec4a-430d-ab5c-0562fab4997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159249734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1159249734
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.2945878018
Short name T381
Test name
Test status
Simulation time 6122447865 ps
CPU time 58.48 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:42:47 PM PDT 24
Peak memory 205032 kb
Host smart-519afc40-5e5e-4ef5-9081-3682c1582127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945878018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2945878018
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.105649728
Short name T1036
Test name
Test status
Simulation time 6399275689 ps
CPU time 53.79 seconds
Started Jul 06 05:41:45 PM PDT 24
Finished Jul 06 05:42:39 PM PDT 24
Peak memory 289416 kb
Host smart-d2cd4f30-61dc-426d-8fb7-476242a01c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105649728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.105649728
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3624424076
Short name T357
Test name
Test status
Simulation time 74228108874 ps
CPU time 482.33 seconds
Started Jul 06 05:41:48 PM PDT 24
Finished Jul 06 05:49:51 PM PDT 24
Peak memory 1103984 kb
Host smart-1ffaf914-7cad-4929-bdbc-401892c37b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624424076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3624424076
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.541649390
Short name T1419
Test name
Test status
Simulation time 1724214250 ps
CPU time 13.69 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:42:03 PM PDT 24
Peak memory 221376 kb
Host smart-31a34ea2-99a6-4dda-b3dd-7f08b2e253c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541649390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.541649390
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2457847812
Short name T848
Test name
Test status
Simulation time 675911786 ps
CPU time 4.02 seconds
Started Jul 06 05:41:56 PM PDT 24
Finished Jul 06 05:42:00 PM PDT 24
Peak memory 205044 kb
Host smart-ef870221-2ffb-4072-b700-614093946788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457847812 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2457847812
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2756906601
Short name T1238
Test name
Test status
Simulation time 186526032 ps
CPU time 1.16 seconds
Started Jul 06 05:41:54 PM PDT 24
Finished Jul 06 05:41:55 PM PDT 24
Peak memory 205004 kb
Host smart-89019b18-6802-4c82-8912-876440bddcd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756906601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2756906601
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1482839303
Short name T263
Test name
Test status
Simulation time 565499421 ps
CPU time 1.1 seconds
Started Jul 06 05:41:54 PM PDT 24
Finished Jul 06 05:41:56 PM PDT 24
Peak memory 205016 kb
Host smart-37b87976-60e3-4b7f-8b09-4af326f8e8db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482839303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1482839303
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.3013249046
Short name T1429
Test name
Test status
Simulation time 433303134 ps
CPU time 2.37 seconds
Started Jul 06 05:41:55 PM PDT 24
Finished Jul 06 05:41:57 PM PDT 24
Peak memory 205020 kb
Host smart-2e2fb847-416d-4b93-86e0-9520fdba469a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013249046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.3013249046
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.222954949
Short name T153
Test name
Test status
Simulation time 667313946 ps
CPU time 1.31 seconds
Started Jul 06 05:41:52 PM PDT 24
Finished Jul 06 05:41:54 PM PDT 24
Peak memory 204820 kb
Host smart-572da69e-a576-4d1b-940c-058643764265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222954949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.222954949
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.447075850
Short name T1147
Test name
Test status
Simulation time 1545092928 ps
CPU time 3.37 seconds
Started Jul 06 05:41:54 PM PDT 24
Finished Jul 06 05:41:58 PM PDT 24
Peak memory 205048 kb
Host smart-a0ef81cd-b8b8-4c77-928d-54ba396adb50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447075850 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.447075850
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2248752261
Short name T859
Test name
Test status
Simulation time 7264188352 ps
CPU time 3.7 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:41:53 PM PDT 24
Peak memory 205080 kb
Host smart-85a71214-5102-4709-b39f-6930b8a8161f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248752261 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2248752261
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3338470355
Short name T274
Test name
Test status
Simulation time 3610693764 ps
CPU time 26.7 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:42:16 PM PDT 24
Peak memory 964736 kb
Host smart-fd2807b0-7356-4fd0-8ebb-c224d8ce5b2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338470355 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3338470355
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.4025926727
Short name T899
Test name
Test status
Simulation time 5559304302 ps
CPU time 49.54 seconds
Started Jul 06 05:41:47 PM PDT 24
Finished Jul 06 05:42:37 PM PDT 24
Peak memory 205076 kb
Host smart-ac7a9dca-eab9-4ea6-b432-63157cefeca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025926727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.4025926727
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3325861386
Short name T1019
Test name
Test status
Simulation time 1295043567 ps
CPU time 10.11 seconds
Started Jul 06 05:41:50 PM PDT 24
Finished Jul 06 05:42:00 PM PDT 24
Peak memory 207528 kb
Host smart-58505697-a799-4600-97df-0b51443cb9f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325861386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3325861386
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.56898300
Short name T940
Test name
Test status
Simulation time 53001616515 ps
CPU time 451.31 seconds
Started Jul 06 05:41:50 PM PDT 24
Finished Jul 06 05:49:22 PM PDT 24
Peak memory 4217392 kb
Host smart-811e8b10-aece-4698-afc5-17041def6eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56898300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_wr.56898300
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3728797223
Short name T513
Test name
Test status
Simulation time 4550783916 ps
CPU time 111.16 seconds
Started Jul 06 05:41:49 PM PDT 24
Finished Jul 06 05:43:40 PM PDT 24
Peak memory 1234980 kb
Host smart-845538a9-27ec-4d08-b0aa-25ab01f5aeff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728797223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3728797223
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.668262098
Short name T1257
Test name
Test status
Simulation time 1380991919 ps
CPU time 7.8 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 213244 kb
Host smart-4acf1acd-ef56-4ed0-a422-b1f641904f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668262098 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.668262098
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3127289398
Short name T935
Test name
Test status
Simulation time 59328771 ps
CPU time 1.46 seconds
Started Jul 06 05:41:53 PM PDT 24
Finished Jul 06 05:41:55 PM PDT 24
Peak memory 205016 kb
Host smart-ac23af50-b97d-4708-970e-16ababbf8cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127289398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3127289398
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1696790495
Short name T443
Test name
Test status
Simulation time 28473328 ps
CPU time 0.61 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:42:12 PM PDT 24
Peak memory 204620 kb
Host smart-4370c2f8-bdd8-4ebf-aed4-ba69879b26b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696790495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1696790495
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.537145105
Short name T895
Test name
Test status
Simulation time 128685435 ps
CPU time 2.19 seconds
Started Jul 06 05:42:01 PM PDT 24
Finished Jul 06 05:42:03 PM PDT 24
Peak memory 222264 kb
Host smart-669a44db-ea0e-46ad-abd2-b3f069bf2bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537145105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.537145105
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3666771472
Short name T299
Test name
Test status
Simulation time 1669715230 ps
CPU time 9.54 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:09 PM PDT 24
Peak memory 296296 kb
Host smart-0603ee00-3551-41f0-adf8-b969d598fafa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666771472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3666771472
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.416377492
Short name T77
Test name
Test status
Simulation time 22366362959 ps
CPU time 39.09 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:40 PM PDT 24
Peak memory 418608 kb
Host smart-10f29635-c02e-4b05-b2cd-aaaf7de2f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416377492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.416377492
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2855344113
Short name T577
Test name
Test status
Simulation time 5338307051 ps
CPU time 83.04 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:43:23 PM PDT 24
Peak memory 844564 kb
Host smart-b9b96747-0b16-4a2f-aafd-f0249d7332e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855344113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2855344113
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1203059866
Short name T1494
Test name
Test status
Simulation time 1360317089 ps
CPU time 1.03 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:42:01 PM PDT 24
Peak memory 204724 kb
Host smart-bbeafb80-bd8e-4f34-8567-d8b86c72990d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203059866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1203059866
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3020180974
Short name T569
Test name
Test status
Simulation time 581042831 ps
CPU time 3.6 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:42:02 PM PDT 24
Peak memory 205100 kb
Host smart-01dc3a91-bac1-461e-b01b-591df00aa64a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020180974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3020180974
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.83359619
Short name T544
Test name
Test status
Simulation time 2666937167 ps
CPU time 168.24 seconds
Started Jul 06 05:41:58 PM PDT 24
Finished Jul 06 05:44:47 PM PDT 24
Peak memory 867400 kb
Host smart-082bd4f2-b116-42dc-87a8-4983603c0508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83359619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.83359619
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3613449050
Short name T854
Test name
Test status
Simulation time 2914552734 ps
CPU time 27.5 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:42:39 PM PDT 24
Peak memory 205108 kb
Host smart-d6f340c1-c20a-4f70-9ff8-f30f525e7f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613449050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3613449050
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1127659138
Short name T593
Test name
Test status
Simulation time 7746340409 ps
CPU time 84.38 seconds
Started Jul 06 05:42:04 PM PDT 24
Finished Jul 06 05:43:29 PM PDT 24
Peak memory 300556 kb
Host smart-2b369042-a311-44d6-979c-b10306ad16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127659138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1127659138
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2558785336
Short name T127
Test name
Test status
Simulation time 22168117 ps
CPU time 0.69 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:01 PM PDT 24
Peak memory 204748 kb
Host smart-4447855d-18e5-4d9b-9680-68df2959dd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558785336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2558785336
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.894481593
Short name T1103
Test name
Test status
Simulation time 5038778165 ps
CPU time 55.77 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:56 PM PDT 24
Peak memory 237772 kb
Host smart-95f93566-1ad1-46d9-90af-846da60ec7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894481593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.894481593
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2163774977
Short name T945
Test name
Test status
Simulation time 143006146 ps
CPU time 2.18 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:03 PM PDT 24
Peak memory 204956 kb
Host smart-00f3c631-696f-4717-b90e-f1c5e764a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163774977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2163774977
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3373312105
Short name T1112
Test name
Test status
Simulation time 7959994377 ps
CPU time 25.76 seconds
Started Jul 06 05:41:54 PM PDT 24
Finished Jul 06 05:42:20 PM PDT 24
Peak memory 310660 kb
Host smart-698daa5d-6f52-4657-b5ba-150247248552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373312105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3373312105
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2326082968
Short name T247
Test name
Test status
Simulation time 51711415744 ps
CPU time 1194.77 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 06:01:55 PM PDT 24
Peak memory 2747272 kb
Host smart-e5da19c6-bd05-48cc-9419-2355263d4399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326082968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2326082968
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3552004258
Short name T252
Test name
Test status
Simulation time 3861787494 ps
CPU time 29.7 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:42:29 PM PDT 24
Peak memory 213324 kb
Host smart-58f57168-7937-4d5c-9da9-c025586534fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552004258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3552004258
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.373417281
Short name T997
Test name
Test status
Simulation time 1608003170 ps
CPU time 3.33 seconds
Started Jul 06 05:42:03 PM PDT 24
Finished Jul 06 05:42:06 PM PDT 24
Peak memory 205000 kb
Host smart-66db5e8b-fa05-4d2f-83f7-ba119f4de52c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373417281 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.373417281
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3779283878
Short name T873
Test name
Test status
Simulation time 287788325 ps
CPU time 1.18 seconds
Started Jul 06 05:42:05 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 204788 kb
Host smart-8849672e-be02-4490-85f0-5a912b85dc10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779283878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3779283878
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3752053705
Short name T1508
Test name
Test status
Simulation time 385915792 ps
CPU time 0.99 seconds
Started Jul 06 05:42:06 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 204792 kb
Host smart-14357ea9-4c1e-46fe-bab7-8d3828a11092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752053705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3752053705
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1889162418
Short name T1334
Test name
Test status
Simulation time 2174791882 ps
CPU time 2.31 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:13 PM PDT 24
Peak memory 205144 kb
Host smart-c442eadd-3fc1-40d5-be8b-0841eceab604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889162418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1889162418
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.2269267390
Short name T1020
Test name
Test status
Simulation time 176566130 ps
CPU time 1.32 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:11 PM PDT 24
Peak memory 204816 kb
Host smart-e74e1e51-a6b6-4d03-95ee-1cd8ef30440c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269267390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.2269267390
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2710264057
Short name T1182
Test name
Test status
Simulation time 353702354 ps
CPU time 2.55 seconds
Started Jul 06 05:42:04 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 205100 kb
Host smart-cf1fc7ef-a4f9-4eb2-bf0f-ce47084ea90b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710264057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2710264057
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.549262049
Short name T840
Test name
Test status
Simulation time 10390406626 ps
CPU time 6.33 seconds
Started Jul 06 05:42:04 PM PDT 24
Finished Jul 06 05:42:10 PM PDT 24
Peak memory 219456 kb
Host smart-dbde31f4-bccc-4a2e-8fad-c32b5d95619c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549262049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.549262049
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1640720624
Short name T1110
Test name
Test status
Simulation time 18940541959 ps
CPU time 299.73 seconds
Started Jul 06 05:42:03 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 3069072 kb
Host smart-51245f4f-69d7-4cc0-a215-3bbe55f10d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640720624 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1640720624
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.4127617200
Short name T464
Test name
Test status
Simulation time 892450058 ps
CPU time 31.55 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:32 PM PDT 24
Peak memory 204980 kb
Host smart-56e118f1-a004-4fde-98e0-efacdb3a3a24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127617200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.4127617200
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2215007292
Short name T1029
Test name
Test status
Simulation time 2726590222 ps
CPU time 10.56 seconds
Started Jul 06 05:42:00 PM PDT 24
Finished Jul 06 05:42:11 PM PDT 24
Peak memory 214108 kb
Host smart-b82652d5-c2fb-41fa-b53e-4d07aca4361b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215007292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2215007292
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2999054146
Short name T1081
Test name
Test status
Simulation time 47786166943 ps
CPU time 372.78 seconds
Started Jul 06 05:41:59 PM PDT 24
Finished Jul 06 05:48:12 PM PDT 24
Peak memory 3603616 kb
Host smart-4fb591da-910d-4deb-82b5-f52a707bb9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999054146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2999054146
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3779382210
Short name T1025
Test name
Test status
Simulation time 4021448768 ps
CPU time 190.76 seconds
Started Jul 06 05:42:05 PM PDT 24
Finished Jul 06 05:45:17 PM PDT 24
Peak memory 1020744 kb
Host smart-109e4f9a-9f0b-4258-b5f7-32243ada5ed4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779382210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3779382210
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1423457291
Short name T447
Test name
Test status
Simulation time 6021857421 ps
CPU time 7.97 seconds
Started Jul 06 05:42:05 PM PDT 24
Finished Jul 06 05:42:13 PM PDT 24
Peak memory 221320 kb
Host smart-1674593f-2c02-4652-b7da-36d0509fdb32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423457291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1423457291
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.2299131645
Short name T1159
Test name
Test status
Simulation time 212288936 ps
CPU time 2.82 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:14 PM PDT 24
Peak memory 205040 kb
Host smart-b7317a94-fdd8-443a-aade-d380692cc5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299131645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2299131645
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3557711514
Short name T638
Test name
Test status
Simulation time 96093958 ps
CPU time 0.63 seconds
Started Jul 06 05:38:32 PM PDT 24
Finished Jul 06 05:38:33 PM PDT 24
Peak memory 204620 kb
Host smart-03b16898-f5d0-4431-82b3-d68361ecf20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557711514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3557711514
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1062186338
Short name T1120
Test name
Test status
Simulation time 372588632 ps
CPU time 3.59 seconds
Started Jul 06 05:38:21 PM PDT 24
Finished Jul 06 05:38:25 PM PDT 24
Peak memory 239028 kb
Host smart-4e019672-14c2-4527-8093-5dcc36eaae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062186338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1062186338
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3473102204
Short name T602
Test name
Test status
Simulation time 240927841 ps
CPU time 4.5 seconds
Started Jul 06 05:38:17 PM PDT 24
Finished Jul 06 05:38:22 PM PDT 24
Peak memory 248212 kb
Host smart-05bba440-b815-441d-be40-8a12d40d5b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473102204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3473102204
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2396765886
Short name T716
Test name
Test status
Simulation time 5255026451 ps
CPU time 26.79 seconds
Started Jul 06 05:38:19 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 343016 kb
Host smart-cc8a8e1d-e331-4b31-af13-59cfd371c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396765886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2396765886
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1682178775
Short name T949
Test name
Test status
Simulation time 8795393405 ps
CPU time 64.03 seconds
Started Jul 06 05:38:18 PM PDT 24
Finished Jul 06 05:39:22 PM PDT 24
Peak memory 731016 kb
Host smart-ddc6e25f-e8b2-47dc-8f63-867728c035c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682178775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1682178775
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2831422843
Short name T1306
Test name
Test status
Simulation time 128120643 ps
CPU time 1.22 seconds
Started Jul 06 05:38:16 PM PDT 24
Finished Jul 06 05:38:17 PM PDT 24
Peak memory 204720 kb
Host smart-b91e9b69-b39d-4d67-8b48-889d643996ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831422843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2831422843
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2851296468
Short name T597
Test name
Test status
Simulation time 191292217 ps
CPU time 10.67 seconds
Started Jul 06 05:38:17 PM PDT 24
Finished Jul 06 05:38:28 PM PDT 24
Peak memory 241012 kb
Host smart-47bc8a29-6c74-4ecd-9acf-6d84b716d06b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851296468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2851296468
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.396416835
Short name T1430
Test name
Test status
Simulation time 21352383936 ps
CPU time 414.36 seconds
Started Jul 06 05:38:16 PM PDT 24
Finished Jul 06 05:45:11 PM PDT 24
Peak memory 1512404 kb
Host smart-c0e5656f-b35c-41ef-99e1-9c095b88d30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396416835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.396416835
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1958310638
Short name T45
Test name
Test status
Simulation time 311524005 ps
CPU time 4.96 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:38:34 PM PDT 24
Peak memory 205028 kb
Host smart-28b0fb5f-3953-40c4-b660-09eb99aa94cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958310638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1958310638
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1322333848
Short name T612
Test name
Test status
Simulation time 1260077110 ps
CPU time 22.05 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:38:52 PM PDT 24
Peak memory 323264 kb
Host smart-37df8ba4-5268-4cf5-b352-bd114b98d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322333848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1322333848
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1268934373
Short name T1240
Test name
Test status
Simulation time 16928368 ps
CPU time 0.67 seconds
Started Jul 06 05:38:18 PM PDT 24
Finished Jul 06 05:38:19 PM PDT 24
Peak memory 204696 kb
Host smart-d35d6e16-0477-47b1-ae51-09064bca1cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268934373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1268934373
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3196765111
Short name T549
Test name
Test status
Simulation time 7530702905 ps
CPU time 18.28 seconds
Started Jul 06 05:38:19 PM PDT 24
Finished Jul 06 05:38:38 PM PDT 24
Peak memory 218148 kb
Host smart-cd469d08-352b-419d-b9b4-3f9471dd0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196765111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3196765111
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2462601660
Short name T779
Test name
Test status
Simulation time 2409133495 ps
CPU time 36.23 seconds
Started Jul 06 05:38:17 PM PDT 24
Finished Jul 06 05:38:53 PM PDT 24
Peak memory 222928 kb
Host smart-542e2a9b-b84c-47ae-9ee1-0283567b961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462601660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2462601660
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3105300130
Short name T954
Test name
Test status
Simulation time 3351859826 ps
CPU time 22.05 seconds
Started Jul 06 05:38:14 PM PDT 24
Finished Jul 06 05:38:37 PM PDT 24
Peak memory 333216 kb
Host smart-1052daa2-f1e6-4d97-abe5-5365aa17fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105300130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3105300130
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3501821426
Short name T1250
Test name
Test status
Simulation time 15357440991 ps
CPU time 474.48 seconds
Started Jul 06 05:38:23 PM PDT 24
Finished Jul 06 05:46:18 PM PDT 24
Peak memory 1980608 kb
Host smart-ae2ca779-c6ac-4a6a-93d5-f9ee012b64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501821426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3501821426
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2170836556
Short name T565
Test name
Test status
Simulation time 2890077478 ps
CPU time 10.96 seconds
Started Jul 06 05:38:16 PM PDT 24
Finished Jul 06 05:38:27 PM PDT 24
Peak memory 221484 kb
Host smart-0f4627db-b539-4f34-8602-ac1fcb443de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170836556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2170836556
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.338177519
Short name T1309
Test name
Test status
Simulation time 666530930 ps
CPU time 3.52 seconds
Started Jul 06 05:38:27 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 205100 kb
Host smart-0386dbfe-1678-478f-92ce-bd2b24a2ec23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338177519 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.338177519
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3363388890
Short name T139
Test name
Test status
Simulation time 1039382237 ps
CPU time 1.33 seconds
Started Jul 06 05:38:30 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 204772 kb
Host smart-cb28b313-e22a-4ece-9dbd-5fce2f155c5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363388890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3363388890
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3530449457
Short name T813
Test name
Test status
Simulation time 431005483 ps
CPU time 0.96 seconds
Started Jul 06 05:38:30 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 204824 kb
Host smart-16cbfde5-4606-4fbf-ac71-e8543328c1aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530449457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3530449457
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.195631261
Short name T983
Test name
Test status
Simulation time 1402014541 ps
CPU time 2.85 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:38:32 PM PDT 24
Peak memory 205036 kb
Host smart-22cf9ad4-2ae2-45e2-8137-6bf8c6b4ae2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195631261 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.195631261
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3780677519
Short name T32
Test name
Test status
Simulation time 175863786 ps
CPU time 0.98 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 204836 kb
Host smart-9fc84bf2-4740-41b3-b7fc-3ddfb9edc735
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780677519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3780677519
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1659778799
Short name T1008
Test name
Test status
Simulation time 2244207341 ps
CPU time 3.37 seconds
Started Jul 06 05:38:23 PM PDT 24
Finished Jul 06 05:38:27 PM PDT 24
Peak memory 205104 kb
Host smart-a12a528e-5c5b-401c-8f32-dfe92b0025bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659778799 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1659778799
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1910693700
Short name T567
Test name
Test status
Simulation time 4768875553 ps
CPU time 16.85 seconds
Started Jul 06 05:38:24 PM PDT 24
Finished Jul 06 05:38:41 PM PDT 24
Peak memory 687356 kb
Host smart-65ec4fab-c228-45e0-929b-a55d27294998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910693700 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1910693700
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2798657077
Short name T189
Test name
Test status
Simulation time 2554685615 ps
CPU time 47.05 seconds
Started Jul 06 05:38:23 PM PDT 24
Finished Jul 06 05:39:10 PM PDT 24
Peak memory 205088 kb
Host smart-22cab181-dbf4-4e5d-8699-8f9ca0e72ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798657077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2798657077
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1613442769
Short name T163
Test name
Test status
Simulation time 1142075607 ps
CPU time 21.57 seconds
Started Jul 06 05:38:25 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 217356 kb
Host smart-51a9058b-1a01-4258-bba8-af2eaa8fd1d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613442769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1613442769
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.197277850
Short name T1492
Test name
Test status
Simulation time 7593325868 ps
CPU time 7.88 seconds
Started Jul 06 05:38:23 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 205072 kb
Host smart-727ac47a-723c-4c21-bab5-02d7a47c3529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197277850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.197277850
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3090857822
Short name T1156
Test name
Test status
Simulation time 5132895405 ps
CPU time 42.38 seconds
Started Jul 06 05:38:24 PM PDT 24
Finished Jul 06 05:39:07 PM PDT 24
Peak memory 385468 kb
Host smart-0add286c-1357-4dc9-b4f5-1b4fa27615f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090857822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3090857822
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.4202955786
Short name T466
Test name
Test status
Simulation time 1451855271 ps
CPU time 7.56 seconds
Started Jul 06 05:38:24 PM PDT 24
Finished Jul 06 05:38:31 PM PDT 24
Peak memory 214980 kb
Host smart-30e49036-1fcd-448c-b00e-0ec7861ab487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202955786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.4202955786
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.1112681225
Short name T751
Test name
Test status
Simulation time 406484927 ps
CPU time 6.12 seconds
Started Jul 06 05:38:30 PM PDT 24
Finished Jul 06 05:38:36 PM PDT 24
Peak memory 205060 kb
Host smart-fa91901e-a073-43cf-86d0-9d4672673df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112681225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.1112681225
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.476026937
Short name T515
Test name
Test status
Simulation time 16317767 ps
CPU time 0.64 seconds
Started Jul 06 05:42:14 PM PDT 24
Finished Jul 06 05:42:15 PM PDT 24
Peak memory 204624 kb
Host smart-517ce6bd-af94-43f3-a7db-5f2f86527787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476026937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.476026937
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1457802724
Short name T1148
Test name
Test status
Simulation time 104092084 ps
CPU time 1.73 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:12 PM PDT 24
Peak memory 221432 kb
Host smart-07636961-4fdf-4a49-8f63-53b6d4b3be70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457802724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1457802724
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3826016727
Short name T1412
Test name
Test status
Simulation time 408076376 ps
CPU time 21.54 seconds
Started Jul 06 05:42:13 PM PDT 24
Finished Jul 06 05:42:35 PM PDT 24
Peak memory 296388 kb
Host smart-4c9bc63f-1063-4983-9776-812ad49c8983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826016727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3826016727
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2296960465
Short name T1135
Test name
Test status
Simulation time 4194676065 ps
CPU time 131.45 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:44:23 PM PDT 24
Peak memory 611128 kb
Host smart-10d5fe92-6a5b-4664-ba27-dff923e63925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296960465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2296960465
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3575840675
Short name T56
Test name
Test status
Simulation time 108901566 ps
CPU time 1.04 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:42:13 PM PDT 24
Peak memory 204768 kb
Host smart-e5353966-2857-417b-9874-85c2512e8337
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575840675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3575840675
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.4135754108
Short name T791
Test name
Test status
Simulation time 2908262785 ps
CPU time 5.53 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:42:17 PM PDT 24
Peak memory 237948 kb
Host smart-810b7ecf-b93d-4af8-b43a-9059931319eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135754108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.4135754108
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3371605623
Short name T570
Test name
Test status
Simulation time 21437682609 ps
CPU time 319.38 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:47:30 PM PDT 24
Peak memory 1276852 kb
Host smart-79372cc0-2d0f-4edb-960f-b09fcb36428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371605623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3371605623
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.133456122
Short name T1162
Test name
Test status
Simulation time 616268125 ps
CPU time 10.1 seconds
Started Jul 06 05:42:19 PM PDT 24
Finished Jul 06 05:42:29 PM PDT 24
Peak memory 205072 kb
Host smart-42a21fde-61fe-40db-8b4b-b715cbd601ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133456122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.133456122
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.864639667
Short name T503
Test name
Test status
Simulation time 4409234476 ps
CPU time 97.67 seconds
Started Jul 06 05:42:19 PM PDT 24
Finished Jul 06 05:43:57 PM PDT 24
Peak memory 366728 kb
Host smart-55f6b901-cb5a-445a-a3b4-9a00f11ec813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864639667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.864639667
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.877350976
Short name T533
Test name
Test status
Simulation time 26966030 ps
CPU time 0.66 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:11 PM PDT 24
Peak memory 204700 kb
Host smart-2396c70e-fdfa-418e-a542-0bee9354e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877350976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.877350976
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.624092778
Short name T406
Test name
Test status
Simulation time 12784173034 ps
CPU time 282.98 seconds
Started Jul 06 05:42:09 PM PDT 24
Finished Jul 06 05:46:52 PM PDT 24
Peak memory 1729388 kb
Host smart-3ef183c4-fdca-4f7a-98da-4feb8c60215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624092778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.624092778
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.1871338174
Short name T287
Test name
Test status
Simulation time 75683363 ps
CPU time 1.86 seconds
Started Jul 06 05:42:09 PM PDT 24
Finished Jul 06 05:42:11 PM PDT 24
Peak memory 217356 kb
Host smart-6ce7ed1c-9201-424d-9878-e71159d0b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871338174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.1871338174
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.412208215
Short name T536
Test name
Test status
Simulation time 9006717229 ps
CPU time 34.5 seconds
Started Jul 06 05:42:10 PM PDT 24
Finished Jul 06 05:42:45 PM PDT 24
Peak memory 382376 kb
Host smart-d4f76491-820f-4bcf-8f40-bdc4cada9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412208215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.412208215
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3707626367
Short name T740
Test name
Test status
Simulation time 7139316641 ps
CPU time 108.06 seconds
Started Jul 06 05:42:13 PM PDT 24
Finished Jul 06 05:44:01 PM PDT 24
Peak memory 262200 kb
Host smart-c42c4f9f-3e7d-4928-ba90-779651fcb51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707626367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3707626367
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3287963578
Short name T1237
Test name
Test status
Simulation time 3023089156 ps
CPU time 15.11 seconds
Started Jul 06 05:42:11 PM PDT 24
Finished Jul 06 05:42:27 PM PDT 24
Peak memory 221420 kb
Host smart-8bd22023-293a-4697-8478-d0f9125b1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287963578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3287963578
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3699115303
Short name T1308
Test name
Test status
Simulation time 3259290454 ps
CPU time 4.46 seconds
Started Jul 06 05:42:15 PM PDT 24
Finished Jul 06 05:42:20 PM PDT 24
Peak memory 213352 kb
Host smart-08f96d22-6f23-46e9-bee0-25c80bd95576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699115303 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3699115303
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.816059629
Short name T845
Test name
Test status
Simulation time 232616109 ps
CPU time 1.48 seconds
Started Jul 06 05:42:16 PM PDT 24
Finished Jul 06 05:42:18 PM PDT 24
Peak memory 205020 kb
Host smart-2cf1b64b-61ae-4f08-8db7-b61e48cfad6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816059629 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.816059629
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3042699821
Short name T492
Test name
Test status
Simulation time 215487674 ps
CPU time 1.45 seconds
Started Jul 06 05:42:14 PM PDT 24
Finished Jul 06 05:42:16 PM PDT 24
Peak memory 204908 kb
Host smart-e73d19b4-a587-4916-9247-cc5e917567b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042699821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3042699821
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.4226639682
Short name T232
Test name
Test status
Simulation time 254926013 ps
CPU time 1.58 seconds
Started Jul 06 05:42:15 PM PDT 24
Finished Jul 06 05:42:17 PM PDT 24
Peak memory 204760 kb
Host smart-d7bc5cf7-ff02-4f37-96e0-a0379179ac88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226639682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.4226639682
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1950099206
Short name T491
Test name
Test status
Simulation time 441462095 ps
CPU time 1.14 seconds
Started Jul 06 05:42:14 PM PDT 24
Finished Jul 06 05:42:16 PM PDT 24
Peak memory 204812 kb
Host smart-41b0c92f-5f7c-4d97-9c8d-86a1134666ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950099206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1950099206
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1785532153
Short name T1127
Test name
Test status
Simulation time 908438744 ps
CPU time 3.1 seconds
Started Jul 06 05:42:14 PM PDT 24
Finished Jul 06 05:42:17 PM PDT 24
Peak memory 205052 kb
Host smart-d177ce21-a45f-4d68-89e7-01500b55ca49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785532153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1785532153
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.737874583
Short name T765
Test name
Test status
Simulation time 3007989936 ps
CPU time 7.39 seconds
Started Jul 06 05:42:19 PM PDT 24
Finished Jul 06 05:42:27 PM PDT 24
Peak memory 214016 kb
Host smart-1c318e04-9afb-4938-b41a-f28adcef0a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737874583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.737874583
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3981704314
Short name T1084
Test name
Test status
Simulation time 11211099353 ps
CPU time 4.03 seconds
Started Jul 06 05:42:16 PM PDT 24
Finished Jul 06 05:42:20 PM PDT 24
Peak memory 205024 kb
Host smart-da1d0c57-eb14-460b-ad7e-fe487e2dd7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981704314 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3981704314
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3201616134
Short name T1126
Test name
Test status
Simulation time 930560734 ps
CPU time 16.22 seconds
Started Jul 06 05:42:16 PM PDT 24
Finished Jul 06 05:42:33 PM PDT 24
Peak memory 204996 kb
Host smart-be1e0deb-9e07-40ea-8e1e-3940865f275c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201616134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3201616134
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2507204753
Short name T430
Test name
Test status
Simulation time 4013609129 ps
CPU time 18.46 seconds
Started Jul 06 05:42:15 PM PDT 24
Finished Jul 06 05:42:34 PM PDT 24
Peak memory 221692 kb
Host smart-e148905b-998c-416a-8c26-634720cc2a12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507204753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2507204753
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3419941415
Short name T756
Test name
Test status
Simulation time 36898918394 ps
CPU time 38.24 seconds
Started Jul 06 05:42:14 PM PDT 24
Finished Jul 06 05:42:53 PM PDT 24
Peak memory 841752 kb
Host smart-56c1c863-592e-471a-bae2-6e34a1f5c614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419941415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3419941415
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3923868484
Short name T1220
Test name
Test status
Simulation time 2366384057 ps
CPU time 7.17 seconds
Started Jul 06 05:42:18 PM PDT 24
Finished Jul 06 05:42:26 PM PDT 24
Peak memory 223804 kb
Host smart-f0fcbdc4-7f67-4378-96dc-231d8026269b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923868484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3923868484
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1534387691
Short name T1007
Test name
Test status
Simulation time 1379421908 ps
CPU time 7.86 seconds
Started Jul 06 05:42:15 PM PDT 24
Finished Jul 06 05:42:23 PM PDT 24
Peak memory 219904 kb
Host smart-eba00d4f-edea-4a7f-8dec-85f2f1124027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534387691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1534387691
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1298003751
Short name T833
Test name
Test status
Simulation time 50765733 ps
CPU time 1.11 seconds
Started Jul 06 05:42:16 PM PDT 24
Finished Jul 06 05:42:17 PM PDT 24
Peak memory 205064 kb
Host smart-b4a22d1c-ed9f-4bc7-b4bc-785d35e399f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298003751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1298003751
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1603931814
Short name T772
Test name
Test status
Simulation time 18373367 ps
CPU time 0.64 seconds
Started Jul 06 05:42:32 PM PDT 24
Finished Jul 06 05:42:33 PM PDT 24
Peak memory 204524 kb
Host smart-86f553da-728e-4c82-a39e-0c12601a9aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603931814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1603931814
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.4015833777
Short name T9
Test name
Test status
Simulation time 193263194 ps
CPU time 3.37 seconds
Started Jul 06 05:42:21 PM PDT 24
Finished Jul 06 05:42:24 PM PDT 24
Peak memory 219692 kb
Host smart-a940c68a-d796-44bc-9b13-4f385d5372b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015833777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.4015833777
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1907961507
Short name T1375
Test name
Test status
Simulation time 176284858 ps
CPU time 2.96 seconds
Started Jul 06 05:42:20 PM PDT 24
Finished Jul 06 05:42:23 PM PDT 24
Peak memory 218560 kb
Host smart-26000eb1-b219-493f-8e3e-479ff9958f2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907961507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1907961507
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2377337993
Short name T402
Test name
Test status
Simulation time 7022371316 ps
CPU time 53.1 seconds
Started Jul 06 05:42:21 PM PDT 24
Finished Jul 06 05:43:15 PM PDT 24
Peak memory 643008 kb
Host smart-966587d9-62e3-46ef-97bd-3e7fcccf004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377337993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2377337993
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1753569576
Short name T1180
Test name
Test status
Simulation time 2488080391 ps
CPU time 92.75 seconds
Started Jul 06 05:42:20 PM PDT 24
Finished Jul 06 05:43:54 PM PDT 24
Peak memory 827568 kb
Host smart-a823fa85-fcc5-4f17-9d5d-4a418eeb9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753569576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1753569576
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3697292422
Short name T754
Test name
Test status
Simulation time 124669167 ps
CPU time 0.94 seconds
Started Jul 06 05:42:21 PM PDT 24
Finished Jul 06 05:42:22 PM PDT 24
Peak memory 204752 kb
Host smart-70d11cd5-8618-4381-805e-c65d7eee4152
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697292422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3697292422
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1320436955
Short name T429
Test name
Test status
Simulation time 262258627 ps
CPU time 7.63 seconds
Started Jul 06 05:42:20 PM PDT 24
Finished Jul 06 05:42:28 PM PDT 24
Peak memory 257416 kb
Host smart-30e0deb3-e1d2-45aa-8402-fd37ba671d85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320436955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1320436955
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.244092931
Short name T1371
Test name
Test status
Simulation time 5280482253 ps
CPU time 417.81 seconds
Started Jul 06 05:42:21 PM PDT 24
Finished Jul 06 05:49:19 PM PDT 24
Peak memory 1522980 kb
Host smart-4ecff4d1-5b66-48eb-b639-f9feb004cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244092931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.244092931
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2678307197
Short name T682
Test name
Test status
Simulation time 960655997 ps
CPU time 5.78 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:42:36 PM PDT 24
Peak memory 205068 kb
Host smart-a24223b4-e8d9-4d06-9fef-4dce00ea0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678307197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2678307197
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3275826919
Short name T912
Test name
Test status
Simulation time 1716250165 ps
CPU time 64.3 seconds
Started Jul 06 05:42:31 PM PDT 24
Finished Jul 06 05:43:35 PM PDT 24
Peak memory 297996 kb
Host smart-f37a5d8b-6549-4f98-a9ec-149af2c258b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275826919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3275826919
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1172453637
Short name T448
Test name
Test status
Simulation time 17609475 ps
CPU time 0.64 seconds
Started Jul 06 05:42:22 PM PDT 24
Finished Jul 06 05:42:23 PM PDT 24
Peak memory 204732 kb
Host smart-e48b10be-3491-4e3e-818f-10ba3e667be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172453637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1172453637
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2714003610
Short name T59
Test name
Test status
Simulation time 2268461353 ps
CPU time 4.82 seconds
Started Jul 06 05:42:20 PM PDT 24
Finished Jul 06 05:42:26 PM PDT 24
Peak memory 213288 kb
Host smart-b4814771-4b01-4e4e-a974-c9a4dd331698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714003610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2714003610
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3662995247
Short name T1272
Test name
Test status
Simulation time 3087645315 ps
CPU time 17.17 seconds
Started Jul 06 05:42:22 PM PDT 24
Finished Jul 06 05:42:39 PM PDT 24
Peak memory 277804 kb
Host smart-acfcf546-bd9c-4c15-8630-08b792b066f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662995247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3662995247
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.4111763147
Short name T1497
Test name
Test status
Simulation time 3566099524 ps
CPU time 28.35 seconds
Started Jul 06 05:42:19 PM PDT 24
Finished Jul 06 05:42:48 PM PDT 24
Peak memory 352912 kb
Host smart-13e7dc37-636a-483d-a6f7-29469dc2f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111763147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.4111763147
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2378687173
Short name T805
Test name
Test status
Simulation time 791779592 ps
CPU time 12.02 seconds
Started Jul 06 05:42:20 PM PDT 24
Finished Jul 06 05:42:32 PM PDT 24
Peak memory 229320 kb
Host smart-3d165fe7-1a0b-4670-b226-bd31e3df0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378687173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2378687173
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2351747395
Short name T1193
Test name
Test status
Simulation time 8755238503 ps
CPU time 4.13 seconds
Started Jul 06 05:42:26 PM PDT 24
Finished Jul 06 05:42:30 PM PDT 24
Peak memory 213172 kb
Host smart-ae61b3be-5732-4d92-9751-22cdaceeee6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351747395 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2351747395
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.629277216
Short name T839
Test name
Test status
Simulation time 455549981 ps
CPU time 0.92 seconds
Started Jul 06 05:42:25 PM PDT 24
Finished Jul 06 05:42:27 PM PDT 24
Peak memory 204824 kb
Host smart-a5f90b83-0d7f-402b-a13c-c3a2e4c9a6c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629277216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.629277216
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3503688494
Short name T330
Test name
Test status
Simulation time 177647042 ps
CPU time 1.18 seconds
Started Jul 06 05:42:26 PM PDT 24
Finished Jul 06 05:42:28 PM PDT 24
Peak memory 204832 kb
Host smart-1eeb5a12-0bb1-40c2-9d69-a1c3f8a16465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503688494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3503688494
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.536712489
Short name T1512
Test name
Test status
Simulation time 373935550 ps
CPU time 2.28 seconds
Started Jul 06 05:42:32 PM PDT 24
Finished Jul 06 05:42:34 PM PDT 24
Peak memory 205032 kb
Host smart-6caf836d-ea82-4c5b-8da5-96355edc3b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536712489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.536712489
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.2812473368
Short name T807
Test name
Test status
Simulation time 162632419 ps
CPU time 1.26 seconds
Started Jul 06 05:42:29 PM PDT 24
Finished Jul 06 05:42:31 PM PDT 24
Peak memory 204824 kb
Host smart-00cbe7fe-eb53-473f-947f-e77f47d7c64b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812473368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.2812473368
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2630420126
Short name T349
Test name
Test status
Simulation time 373349793 ps
CPU time 4.05 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:42:35 PM PDT 24
Peak memory 205120 kb
Host smart-fb9ebf34-3055-432c-ad2b-312d6b992c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630420126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2630420126
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1829672331
Short name T1032
Test name
Test status
Simulation time 1133133330 ps
CPU time 5.99 seconds
Started Jul 06 05:42:24 PM PDT 24
Finished Jul 06 05:42:30 PM PDT 24
Peak memory 210624 kb
Host smart-158c62ed-b8bd-4dfd-b056-71cf996fc5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829672331 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1829672331
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2678184643
Short name T1448
Test name
Test status
Simulation time 8278212765 ps
CPU time 14.7 seconds
Started Jul 06 05:42:26 PM PDT 24
Finished Jul 06 05:42:41 PM PDT 24
Peak memory 319716 kb
Host smart-989c4eb6-c37a-4520-89d5-5f643b6914fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678184643 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2678184643
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1664900205
Short name T1281
Test name
Test status
Simulation time 860157187 ps
CPU time 15.34 seconds
Started Jul 06 05:42:25 PM PDT 24
Finished Jul 06 05:42:41 PM PDT 24
Peak memory 205060 kb
Host smart-3381102e-c734-4b4a-89b6-f2ca064a9507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664900205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1664900205
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3264786758
Short name T240
Test name
Test status
Simulation time 762426348 ps
CPU time 7.34 seconds
Started Jul 06 05:42:26 PM PDT 24
Finished Jul 06 05:42:33 PM PDT 24
Peak memory 205068 kb
Host smart-26de8ab9-646e-4136-8632-8ecd533b90c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264786758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3264786758
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4060032577
Short name T629
Test name
Test status
Simulation time 52821552174 ps
CPU time 164.91 seconds
Started Jul 06 05:42:27 PM PDT 24
Finished Jul 06 05:45:12 PM PDT 24
Peak memory 2144824 kb
Host smart-5de98fc0-f3bd-4138-9c29-8ce486c2a83c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060032577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4060032577
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1543678173
Short name T1248
Test name
Test status
Simulation time 4980312181 ps
CPU time 8.25 seconds
Started Jul 06 05:42:28 PM PDT 24
Finished Jul 06 05:42:37 PM PDT 24
Peak memory 322676 kb
Host smart-e95e4e6e-ec8c-4940-8e94-38ea065f1259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543678173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1543678173
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.854637204
Short name T622
Test name
Test status
Simulation time 1273488325 ps
CPU time 7.26 seconds
Started Jul 06 05:42:26 PM PDT 24
Finished Jul 06 05:42:34 PM PDT 24
Peak memory 210828 kb
Host smart-115b8f71-5086-46b2-b755-b09d945b444e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854637204 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.854637204
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.231893567
Short name T20
Test name
Test status
Simulation time 127528048 ps
CPU time 2.29 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:42:32 PM PDT 24
Peak memory 204992 kb
Host smart-bc0e1cae-ae00-4eef-8132-2a39f72a5ad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231893567 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.231893567
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1302059837
Short name T4
Test name
Test status
Simulation time 15511082 ps
CPU time 0.65 seconds
Started Jul 06 05:42:44 PM PDT 24
Finished Jul 06 05:42:45 PM PDT 24
Peak memory 204592 kb
Host smart-6dde2dce-1e07-49d6-a7e4-28c7a02ea02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302059837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1302059837
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2983428987
Short name T936
Test name
Test status
Simulation time 3339764926 ps
CPU time 4.79 seconds
Started Jul 06 05:42:39 PM PDT 24
Finished Jul 06 05:42:44 PM PDT 24
Peak memory 264748 kb
Host smart-7b2ce4d2-eaa0-4985-a719-ec9131a7d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983428987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2983428987
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1151327711
Short name T844
Test name
Test status
Simulation time 1022723876 ps
CPU time 6.77 seconds
Started Jul 06 05:42:31 PM PDT 24
Finished Jul 06 05:42:38 PM PDT 24
Peak memory 268356 kb
Host smart-a6cebed3-ab74-4cb6-a5f1-376e3851fc8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151327711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1151327711
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2108112586
Short name T374
Test name
Test status
Simulation time 11208287633 ps
CPU time 84.73 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:44:03 PM PDT 24
Peak memory 768576 kb
Host smart-d52507c5-1c8a-48f8-8d1d-898a20305dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108112586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2108112586
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.394697901
Short name T390
Test name
Test status
Simulation time 2296428323 ps
CPU time 68.84 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:43:39 PM PDT 24
Peak memory 683480 kb
Host smart-a21fdf1a-6cb8-453e-8f4d-f501975d888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394697901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.394697901
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3200918281
Short name T1165
Test name
Test status
Simulation time 262530444 ps
CPU time 0.93 seconds
Started Jul 06 05:42:31 PM PDT 24
Finished Jul 06 05:42:33 PM PDT 24
Peak memory 204752 kb
Host smart-d822ca93-4ffa-418e-a65a-302012a1d7dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200918281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3200918281
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3393157327
Short name T733
Test name
Test status
Simulation time 257600474 ps
CPU time 7.31 seconds
Started Jul 06 05:42:39 PM PDT 24
Finished Jul 06 05:42:47 PM PDT 24
Peak memory 205040 kb
Host smart-48b5143e-4565-458b-9669-d582bfff83a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393157327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3393157327
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1708192025
Short name T250
Test name
Test status
Simulation time 11909786268 ps
CPU time 172.36 seconds
Started Jul 06 05:42:32 PM PDT 24
Finished Jul 06 05:45:24 PM PDT 24
Peak memory 856328 kb
Host smart-bb40d010-d223-478a-b71a-b846b48454e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708192025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1708192025
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3444219299
Short name T1408
Test name
Test status
Simulation time 426976507 ps
CPU time 7.32 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 205052 kb
Host smart-2d41f384-06ae-4429-8abc-be0a9fa503d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444219299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3444219299
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2977517894
Short name T955
Test name
Test status
Simulation time 9313103140 ps
CPU time 76.27 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:44:04 PM PDT 24
Peak memory 351772 kb
Host smart-2d3d0ddb-693a-47ab-bde4-769009fae9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977517894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2977517894
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1122567180
Short name T356
Test name
Test status
Simulation time 133377886 ps
CPU time 0.67 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:42:31 PM PDT 24
Peak memory 204748 kb
Host smart-7b678026-8988-4555-ac07-bd1d5a6c72d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122567180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1122567180
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.322128641
Short name T1505
Test name
Test status
Simulation time 7402301993 ps
CPU time 372.24 seconds
Started Jul 06 05:42:37 PM PDT 24
Finished Jul 06 05:48:49 PM PDT 24
Peak memory 535880 kb
Host smart-a6814de5-4fe4-486d-b9e1-4c6b40d984c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322128641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.322128641
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.4270466221
Short name T289
Test name
Test status
Simulation time 87680714 ps
CPU time 1.66 seconds
Started Jul 06 05:42:39 PM PDT 24
Finished Jul 06 05:42:41 PM PDT 24
Peak memory 217816 kb
Host smart-79256e09-d44a-4074-b305-e3a38ba4ec57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270466221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.4270466221
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3930264646
Short name T278
Test name
Test status
Simulation time 4912836476 ps
CPU time 54.02 seconds
Started Jul 06 05:42:30 PM PDT 24
Finished Jul 06 05:43:25 PM PDT 24
Peak memory 310228 kb
Host smart-495c5cdc-2646-4434-8772-82cc30f4f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930264646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3930264646
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1855117562
Short name T1242
Test name
Test status
Simulation time 79224060353 ps
CPU time 2843.65 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 3163000 kb
Host smart-fab5d203-a682-461d-a11a-4fea1133b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855117562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1855117562
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2349634566
Short name T373
Test name
Test status
Simulation time 1727883084 ps
CPU time 14.73 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:53 PM PDT 24
Peak memory 213196 kb
Host smart-431c42e5-a102-40ce-8b80-8947581b4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349634566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2349634566
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2181029623
Short name T1476
Test name
Test status
Simulation time 810815135 ps
CPU time 4.39 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 213408 kb
Host smart-964d8d44-f8c1-47ee-871f-b3cc69b7054d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181029623 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2181029623
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2870506997
Short name T1090
Test name
Test status
Simulation time 747048648 ps
CPU time 1.32 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:40 PM PDT 24
Peak memory 204984 kb
Host smart-6f3d01d7-7955-4f4b-81f8-2a9b0adc16d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870506997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2870506997
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2127520939
Short name T1269
Test name
Test status
Simulation time 177705273 ps
CPU time 1.14 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:40 PM PDT 24
Peak memory 213016 kb
Host smart-b10498df-4695-4da5-9ef6-db9aa2ff33ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127520939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2127520939
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.260572225
Short name T1132
Test name
Test status
Simulation time 2700802376 ps
CPU time 2.49 seconds
Started Jul 06 05:42:48 PM PDT 24
Finished Jul 06 05:42:51 PM PDT 24
Peak memory 205064 kb
Host smart-8c828f25-6f8c-409b-950e-0353e31325ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260572225 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.260572225
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.177126356
Short name T1021
Test name
Test status
Simulation time 601483400 ps
CPU time 1.31 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:42:49 PM PDT 24
Peak memory 204768 kb
Host smart-575499d7-0de5-48af-a661-2dd5f85e1790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177126356 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.177126356
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1874457041
Short name T789
Test name
Test status
Simulation time 4393110466 ps
CPU time 6.89 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:45 PM PDT 24
Peak memory 221384 kb
Host smart-bc8ea152-d491-4801-8176-883f8d5eeae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874457041 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1874457041
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2667878544
Short name T858
Test name
Test status
Simulation time 28292608569 ps
CPU time 24.78 seconds
Started Jul 06 05:42:37 PM PDT 24
Finished Jul 06 05:43:02 PM PDT 24
Peak memory 691224 kb
Host smart-eaab5afc-d9fc-40c6-8360-d4c021c481c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667878544 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2667878544
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.526960124
Short name T614
Test name
Test status
Simulation time 1210725325 ps
CPU time 16.15 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:55 PM PDT 24
Peak memory 205000 kb
Host smart-d96f0922-4adf-41e6-8ad5-f473affe6108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526960124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.526960124
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3165121701
Short name T1523
Test name
Test status
Simulation time 2558191838 ps
CPU time 53.76 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:43:32 PM PDT 24
Peak memory 206416 kb
Host smart-a9ed14fb-345a-49de-bb3e-2d2a7f5d3f4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165121701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3165121701
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1119170638
Short name T1224
Test name
Test status
Simulation time 52175140854 ps
CPU time 1322.53 seconds
Started Jul 06 05:42:37 PM PDT 24
Finished Jul 06 06:04:40 PM PDT 24
Peak memory 8242828 kb
Host smart-a1b0f5dc-c99a-4d4e-8216-858fc29601e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119170638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1119170638
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3977175941
Short name T1005
Test name
Test status
Simulation time 4305635631 ps
CPU time 46.41 seconds
Started Jul 06 05:42:36 PM PDT 24
Finished Jul 06 05:43:23 PM PDT 24
Peak memory 413244 kb
Host smart-290e76a9-4bf6-4a0e-a53b-01ba530148ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977175941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3977175941
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2822079537
Short name T1059
Test name
Test status
Simulation time 4758708805 ps
CPU time 6.75 seconds
Started Jul 06 05:42:38 PM PDT 24
Finished Jul 06 05:42:45 PM PDT 24
Peak memory 213300 kb
Host smart-cda0e29f-98a9-46b6-86c9-e65b325edb27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822079537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2822079537
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.144391066
Short name T687
Test name
Test status
Simulation time 308551505 ps
CPU time 3.13 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 213164 kb
Host smart-5e7ed25e-d480-4a35-b407-b4aee1f7742c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144391066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.144391066
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.744673855
Short name T313
Test name
Test status
Simulation time 16573596 ps
CPU time 0.63 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 204608 kb
Host smart-f6fe08b0-b08d-468e-9e43-e1fa0b33c4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744673855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.744673855
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.44490729
Short name T129
Test name
Test status
Simulation time 104442596 ps
CPU time 1.56 seconds
Started Jul 06 05:42:48 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 205132 kb
Host smart-f9e64b95-7608-440c-834b-b36f0ee3fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44490729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.44490729
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.946285153
Short name T1172
Test name
Test status
Simulation time 1151121201 ps
CPU time 15.43 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:43:02 PM PDT 24
Peak memory 268432 kb
Host smart-5cac3476-4e60-465b-a385-37cf74728260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946285153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.946285153
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2793453203
Short name T643
Test name
Test status
Simulation time 5401296974 ps
CPU time 35.31 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:43:23 PM PDT 24
Peak memory 494748 kb
Host smart-0d237339-0be6-4ea6-bf08-0c18044b9a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793453203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2793453203
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.381047578
Short name T914
Test name
Test status
Simulation time 1994551056 ps
CPU time 55.67 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:43:42 PM PDT 24
Peak memory 658960 kb
Host smart-af2cb108-7340-4dd1-b205-68a313ebb3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381047578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.381047578
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1694937950
Short name T680
Test name
Test status
Simulation time 354247926 ps
CPU time 1.06 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:42:47 PM PDT 24
Peak memory 204776 kb
Host smart-e331f2f0-0108-4b6a-a8f1-c898dbd37bf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694937950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1694937950
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2750056839
Short name T822
Test name
Test status
Simulation time 161051027 ps
CPU time 5.99 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 204960 kb
Host smart-0ed71bc4-fc27-4d9e-9f02-98ab75f2d575
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750056839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2750056839
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.370102850
Short name T801
Test name
Test status
Simulation time 4314937856 ps
CPU time 128.84 seconds
Started Jul 06 05:42:46 PM PDT 24
Finished Jul 06 05:44:55 PM PDT 24
Peak memory 1206804 kb
Host smart-6bb80b59-3127-4496-a595-bebca314e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370102850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.370102850
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1978735096
Short name T910
Test name
Test status
Simulation time 1527988618 ps
CPU time 6.16 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:59 PM PDT 24
Peak memory 205016 kb
Host smart-6d0f57ee-e5e9-4259-a112-83db0cbc87ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978735096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1978735096
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.564676341
Short name T1218
Test name
Test status
Simulation time 2378151629 ps
CPU time 34.27 seconds
Started Jul 06 05:42:52 PM PDT 24
Finished Jul 06 05:43:27 PM PDT 24
Peak memory 324576 kb
Host smart-001c650b-d65e-404b-9eb8-ab140d5fa61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564676341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.564676341
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.4265088153
Short name T946
Test name
Test status
Simulation time 42616247 ps
CPU time 0.65 seconds
Started Jul 06 05:42:49 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 204756 kb
Host smart-8c15b05f-e260-4f18-b1b3-242cdc3801f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265088153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4265088153
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2310678779
Short name T1251
Test name
Test status
Simulation time 8264138090 ps
CPU time 106.49 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:44:34 PM PDT 24
Peak memory 426288 kb
Host smart-c745669e-6fc8-4d70-b22e-83ab3ff734a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310678779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2310678779
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1422759551
Short name T310
Test name
Test status
Simulation time 75849940 ps
CPU time 1.45 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:42:48 PM PDT 24
Peak memory 205004 kb
Host smart-194e4420-193e-4522-b417-581a8152b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422759551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1422759551
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2816678646
Short name T1390
Test name
Test status
Simulation time 2469387414 ps
CPU time 24.67 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:43:12 PM PDT 24
Peak memory 324516 kb
Host smart-6687a01a-55d3-4754-b833-da61321fab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816678646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2816678646
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2527221630
Short name T853
Test name
Test status
Simulation time 36347226729 ps
CPU time 2246.53 seconds
Started Jul 06 05:42:48 PM PDT 24
Finished Jul 06 06:20:15 PM PDT 24
Peak memory 3516184 kb
Host smart-d798a969-202e-4fe8-bb86-1b2709937dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527221630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2527221630
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.582385248
Short name T578
Test name
Test status
Simulation time 1733433200 ps
CPU time 7.59 seconds
Started Jul 06 05:42:47 PM PDT 24
Finished Jul 06 05:42:55 PM PDT 24
Peak memory 213248 kb
Host smart-eb63fd56-2db9-49bd-9b42-0a8883327732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582385248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.582385248
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.693599322
Short name T1431
Test name
Test status
Simulation time 217719045 ps
CPU time 1.29 seconds
Started Jul 06 05:42:48 PM PDT 24
Finished Jul 06 05:42:49 PM PDT 24
Peak memory 213296 kb
Host smart-7e5c42d2-c52a-4a57-a6ff-f92269f4359e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693599322 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.693599322
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.4273752185
Short name T322
Test name
Test status
Simulation time 339776706 ps
CPU time 1.97 seconds
Started Jul 06 05:42:55 PM PDT 24
Finished Jul 06 05:42:57 PM PDT 24
Peak memory 204988 kb
Host smart-8e594598-cd4c-46cc-ab32-515e6855ea75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273752185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.4273752185
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.3107284968
Short name T1470
Test name
Test status
Simulation time 299556061 ps
CPU time 0.95 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 204744 kb
Host smart-e5b60de5-6300-4694-afa2-fd95231bd1c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107284968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.3107284968
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2267421588
Short name T855
Test name
Test status
Simulation time 1050818867 ps
CPU time 2.47 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:56 PM PDT 24
Peak memory 205076 kb
Host smart-83bcf3cb-2184-4d19-bd0a-4dd7f9b3faf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267421588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2267421588
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.50948018
Short name T932
Test name
Test status
Simulation time 911408477 ps
CPU time 5.53 seconds
Started Jul 06 05:42:51 PM PDT 24
Finished Jul 06 05:42:56 PM PDT 24
Peak memory 218816 kb
Host smart-d2fcf358-ce57-49f9-8c3b-b185fa97bd5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50948018 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.50948018
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.22371264
Short name T724
Test name
Test status
Simulation time 8896546481 ps
CPU time 6.51 seconds
Started Jul 06 05:42:48 PM PDT 24
Finished Jul 06 05:42:55 PM PDT 24
Peak memory 334452 kb
Host smart-414e891a-aded-43c7-8acd-e675c0da91cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371264 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.22371264
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3959029502
Short name T1440
Test name
Test status
Simulation time 1142607952 ps
CPU time 12.43 seconds
Started Jul 06 05:42:50 PM PDT 24
Finished Jul 06 05:43:02 PM PDT 24
Peak memory 204996 kb
Host smart-364ccb24-10f4-4efb-b8fe-e6cafc0a12d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959029502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3959029502
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1536540440
Short name T514
Test name
Test status
Simulation time 1231074328 ps
CPU time 4.84 seconds
Started Jul 06 05:42:49 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 205032 kb
Host smart-071e4a0e-069e-43d7-8872-84f0f784c7e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536540440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1536540440
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1450505438
Short name T573
Test name
Test status
Simulation time 49740225184 ps
CPU time 177.54 seconds
Started Jul 06 05:42:49 PM PDT 24
Finished Jul 06 05:45:47 PM PDT 24
Peak memory 2182828 kb
Host smart-72301dd3-955d-451d-a694-9302743dd114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450505438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1450505438
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2003270330
Short name T1027
Test name
Test status
Simulation time 11835943008 ps
CPU time 6.81 seconds
Started Jul 06 05:42:49 PM PDT 24
Finished Jul 06 05:42:57 PM PDT 24
Peak memory 205360 kb
Host smart-c0ad6803-2cc2-4246-835f-a62d2456fe89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003270330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2003270330
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.1717708494
Short name T703
Test name
Test status
Simulation time 41414267 ps
CPU time 1.09 seconds
Started Jul 06 05:42:52 PM PDT 24
Finished Jul 06 05:42:53 PM PDT 24
Peak memory 205000 kb
Host smart-d4cf4f06-4184-4e70-8a5d-ff3a1e4a030e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717708494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1717708494
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.558432561
Short name T788
Test name
Test status
Simulation time 18196384 ps
CPU time 0.64 seconds
Started Jul 06 05:43:04 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 204532 kb
Host smart-afbe5b36-6dcb-4e87-b724-ce88a823a1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558432561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.558432561
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2350102507
Short name T1181
Test name
Test status
Simulation time 149481202 ps
CPU time 3.07 seconds
Started Jul 06 05:42:57 PM PDT 24
Finished Jul 06 05:43:01 PM PDT 24
Peak memory 233844 kb
Host smart-2a095df4-0606-4bed-b9bc-de59ad39dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350102507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2350102507
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2153070779
Short name T990
Test name
Test status
Simulation time 952237327 ps
CPU time 4.71 seconds
Started Jul 06 05:42:56 PM PDT 24
Finished Jul 06 05:43:01 PM PDT 24
Peak memory 252796 kb
Host smart-abf7c128-4642-4d81-8ee4-2c3b315c5954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153070779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2153070779
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2400677446
Short name T360
Test name
Test status
Simulation time 2283713365 ps
CPU time 80.36 seconds
Started Jul 06 05:42:52 PM PDT 24
Finished Jul 06 05:44:13 PM PDT 24
Peak memory 750556 kb
Host smart-66d5c48e-e710-40bd-9484-40d0fa197273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400677446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2400677446
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2069051730
Short name T906
Test name
Test status
Simulation time 22259386606 ps
CPU time 70.67 seconds
Started Jul 06 05:42:55 PM PDT 24
Finished Jul 06 05:44:06 PM PDT 24
Peak memory 707860 kb
Host smart-d13fec4a-6660-4d41-ba31-368ed26bb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069051730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2069051730
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2975118382
Short name T216
Test name
Test status
Simulation time 103353081 ps
CPU time 0.98 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:54 PM PDT 24
Peak memory 204684 kb
Host smart-393b1cf5-ea37-422f-bf16-1bf0e3c93d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975118382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2975118382
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1658705772
Short name T843
Test name
Test status
Simulation time 406569058 ps
CPU time 5.61 seconds
Started Jul 06 05:42:52 PM PDT 24
Finished Jul 06 05:42:58 PM PDT 24
Peak memory 241132 kb
Host smart-a5a80403-82da-49ca-8432-3110bc1d7196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658705772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1658705772
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1346183933
Short name T1085
Test name
Test status
Simulation time 53450028003 ps
CPU time 170.21 seconds
Started Jul 06 05:42:51 PM PDT 24
Finished Jul 06 05:45:41 PM PDT 24
Peak memory 836740 kb
Host smart-4e3b7f69-64d0-41df-abae-6c6aa91b0d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346183933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1346183933
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.330935195
Short name T722
Test name
Test status
Simulation time 3201139924 ps
CPU time 4.21 seconds
Started Jul 06 05:43:01 PM PDT 24
Finished Jul 06 05:43:06 PM PDT 24
Peak memory 205088 kb
Host smart-38c26c83-19ef-4bbc-bd59-0b74d06895be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330935195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.330935195
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1500137104
Short name T1296
Test name
Test status
Simulation time 17644691838 ps
CPU time 70.73 seconds
Started Jul 06 05:43:02 PM PDT 24
Finished Jul 06 05:44:13 PM PDT 24
Peak memory 431720 kb
Host smart-0e00d2c5-cb28-4d9e-af3f-03f0ef35dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500137104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1500137104
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.4131357049
Short name T112
Test name
Test status
Simulation time 84458166 ps
CPU time 0.67 seconds
Started Jul 06 05:42:54 PM PDT 24
Finished Jul 06 05:42:55 PM PDT 24
Peak memory 204752 kb
Host smart-9f44e628-6cd1-4293-9239-1e24a90f3139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131357049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.4131357049
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1275369344
Short name T60
Test name
Test status
Simulation time 7595890251 ps
CPU time 285.46 seconds
Started Jul 06 05:42:52 PM PDT 24
Finished Jul 06 05:47:37 PM PDT 24
Peak memory 205148 kb
Host smart-aa8d367f-0912-4ee8-9654-906237f61d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275369344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1275369344
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.2582464050
Short name T723
Test name
Test status
Simulation time 298056869 ps
CPU time 1.6 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:42:55 PM PDT 24
Peak memory 204936 kb
Host smart-44637521-1a66-4c02-bf13-1f61ae915a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582464050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.2582464050
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2331434918
Short name T399
Test name
Test status
Simulation time 7960391287 ps
CPU time 36.57 seconds
Started Jul 06 05:42:53 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 311712 kb
Host smart-b7adf413-7f52-4bcf-8c5c-5ef9b7be10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331434918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2331434918
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2348642824
Short name T1507
Test name
Test status
Simulation time 5503399328 ps
CPU time 447.61 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:50:26 PM PDT 24
Peak memory 942116 kb
Host smart-5263313e-d230-493f-86e0-303511cb5f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348642824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2348642824
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3343955835
Short name T500
Test name
Test status
Simulation time 2732086471 ps
CPU time 33.61 seconds
Started Jul 06 05:42:56 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 213312 kb
Host smart-02e04b71-fbc7-47ea-a4d0-d9689b29e772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343955835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3343955835
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4062340045
Short name T27
Test name
Test status
Simulation time 1373356777 ps
CPU time 2.26 seconds
Started Jul 06 05:43:02 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 205032 kb
Host smart-f53edee9-eac3-4897-9c81-43bb1d0e45b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062340045 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4062340045
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1901642602
Short name T1010
Test name
Test status
Simulation time 383680937 ps
CPU time 1.01 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:42:59 PM PDT 24
Peak memory 204836 kb
Host smart-61f09a7c-bf8d-4e95-a905-c223f62f80c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901642602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1901642602
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.884520689
Short name T1466
Test name
Test status
Simulation time 1879577505 ps
CPU time 1.17 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:42:59 PM PDT 24
Peak memory 205024 kb
Host smart-c49c6811-4023-4631-bc1c-d52364f4f8c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884520689 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.884520689
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3187647713
Short name T1513
Test name
Test status
Simulation time 948170100 ps
CPU time 2.18 seconds
Started Jul 06 05:43:02 PM PDT 24
Finished Jul 06 05:43:04 PM PDT 24
Peak memory 205016 kb
Host smart-7af3825d-9ad4-4cea-a2ff-6cbcf55b78b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187647713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3187647713
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.2959814281
Short name T1383
Test name
Test status
Simulation time 234212206 ps
CPU time 1.2 seconds
Started Jul 06 05:43:02 PM PDT 24
Finished Jul 06 05:43:03 PM PDT 24
Peak memory 204832 kb
Host smart-9db05090-5713-40d7-86b8-d7039f5d33de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959814281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.2959814281
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3498231037
Short name T398
Test name
Test status
Simulation time 1100408886 ps
CPU time 6.1 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:43:04 PM PDT 24
Peak memory 213228 kb
Host smart-5016d559-763f-44e6-b95c-c08c685ab545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498231037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3498231037
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.668494672
Short name T761
Test name
Test status
Simulation time 18370316413 ps
CPU time 261.32 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:47:19 PM PDT 24
Peak memory 2907696 kb
Host smart-1ba169f0-ef28-4250-8d61-51c724725743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668494672 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.668494672
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.4062269521
Short name T1178
Test name
Test status
Simulation time 2981812827 ps
CPU time 21.02 seconds
Started Jul 06 05:42:59 PM PDT 24
Finished Jul 06 05:43:20 PM PDT 24
Peak memory 205064 kb
Host smart-e07a0cd9-6cdc-47fc-a5b8-7ef9b462d844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062269521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.4062269521
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.852285303
Short name T650
Test name
Test status
Simulation time 1656754482 ps
CPU time 15.98 seconds
Started Jul 06 05:42:57 PM PDT 24
Finished Jul 06 05:43:13 PM PDT 24
Peak memory 205032 kb
Host smart-b6c66101-5b88-4c6c-b5bb-326827f3d847
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852285303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.852285303
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3621129957
Short name T571
Test name
Test status
Simulation time 57173488227 ps
CPU time 232.75 seconds
Started Jul 06 05:42:59 PM PDT 24
Finished Jul 06 05:46:52 PM PDT 24
Peak memory 2625696 kb
Host smart-8a4dbfca-c0d6-4cac-8583-3bbcd34701ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621129957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3621129957
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.522366922
Short name T308
Test name
Test status
Simulation time 1945813116 ps
CPU time 6.5 seconds
Started Jul 06 05:42:58 PM PDT 24
Finished Jul 06 05:43:05 PM PDT 24
Peak memory 255948 kb
Host smart-a767f778-bdba-4604-aa44-a628a4eb95ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522366922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.522366922
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1262666381
Short name T1145
Test name
Test status
Simulation time 11039302490 ps
CPU time 6.92 seconds
Started Jul 06 05:42:56 PM PDT 24
Finished Jul 06 05:43:03 PM PDT 24
Peak memory 221328 kb
Host smart-fb299ed8-0969-4ee1-aa6e-8bf5ecff1567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262666381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1262666381
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.233417141
Short name T1463
Test name
Test status
Simulation time 169674706 ps
CPU time 2.92 seconds
Started Jul 06 05:43:04 PM PDT 24
Finished Jul 06 05:43:07 PM PDT 24
Peak memory 214012 kb
Host smart-00bc2b79-6ab1-407f-ae3b-60062b71775d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233417141 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.233417141
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2805679300
Short name T957
Test name
Test status
Simulation time 23921398 ps
CPU time 0.62 seconds
Started Jul 06 05:43:17 PM PDT 24
Finished Jul 06 05:43:18 PM PDT 24
Peak memory 204604 kb
Host smart-5c51edac-7c9f-4c66-a2cc-91aa1cca2946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805679300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2805679300
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3442524992
Short name T1260
Test name
Test status
Simulation time 346292258 ps
CPU time 6.96 seconds
Started Jul 06 05:43:12 PM PDT 24
Finished Jul 06 05:43:19 PM PDT 24
Peak memory 268060 kb
Host smart-06212f20-75ba-487b-8979-4612fa9b086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442524992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3442524992
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.4155968086
Short name T1354
Test name
Test status
Simulation time 1083670601 ps
CPU time 8.94 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:43:21 PM PDT 24
Peak memory 294060 kb
Host smart-743320d2-0bb7-4156-adbf-ee97889de673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155968086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.4155968086
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3468427114
Short name T919
Test name
Test status
Simulation time 11382201744 ps
CPU time 211.94 seconds
Started Jul 06 05:43:13 PM PDT 24
Finished Jul 06 05:46:45 PM PDT 24
Peak memory 889200 kb
Host smart-2f7c3635-6a5a-4234-96fe-608de5da89dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468427114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3468427114
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1101808891
Short name T1073
Test name
Test status
Simulation time 4661009856 ps
CPU time 78.61 seconds
Started Jul 06 05:43:13 PM PDT 24
Finished Jul 06 05:44:32 PM PDT 24
Peak memory 808996 kb
Host smart-33c591f8-3178-414b-8813-d9a7806226cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101808891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1101808891
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2179519740
Short name T217
Test name
Test status
Simulation time 212594537 ps
CPU time 1.1 seconds
Started Jul 06 05:43:16 PM PDT 24
Finished Jul 06 05:43:18 PM PDT 24
Peak memory 204736 kb
Host smart-78a7725e-104c-448f-b34d-de06cd8f2302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179519740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2179519740
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.63448989
Short name T896
Test name
Test status
Simulation time 663966076 ps
CPU time 4.14 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:43:15 PM PDT 24
Peak memory 204916 kb
Host smart-dfae0e4d-8919-47fe-a455-20bebf8e976b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63448989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.63448989
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2934580378
Short name T1348
Test name
Test status
Simulation time 17244165292 ps
CPU time 113.52 seconds
Started Jul 06 05:43:12 PM PDT 24
Finished Jul 06 05:45:06 PM PDT 24
Peak memory 1237156 kb
Host smart-5c7cf147-b70a-411d-8766-1309bdac2c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934580378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2934580378
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2993046989
Short name T1370
Test name
Test status
Simulation time 662952810 ps
CPU time 9.33 seconds
Started Jul 06 05:43:18 PM PDT 24
Finished Jul 06 05:43:27 PM PDT 24
Peak memory 205104 kb
Host smart-52147d72-5dbc-431b-82cb-4fcb2b53852e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993046989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2993046989
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2378018669
Short name T713
Test name
Test status
Simulation time 1096819971 ps
CPU time 15.01 seconds
Started Jul 06 05:43:16 PM PDT 24
Finished Jul 06 05:43:31 PM PDT 24
Peak memory 267820 kb
Host smart-edf992a3-781b-4008-bd87-40287900870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378018669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2378018669
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1836173341
Short name T456
Test name
Test status
Simulation time 84797542 ps
CPU time 0.67 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:43:12 PM PDT 24
Peak memory 204760 kb
Host smart-78d759e0-8b2d-4753-aae5-81dd2aaa6d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836173341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1836173341
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1296109156
Short name T1325
Test name
Test status
Simulation time 49496595440 ps
CPU time 1856.56 seconds
Started Jul 06 05:43:10 PM PDT 24
Finished Jul 06 06:14:07 PM PDT 24
Peak memory 205112 kb
Host smart-2314f972-789b-4e20-adc0-ed52838ea39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296109156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1296109156
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.293786124
Short name T681
Test name
Test status
Simulation time 23302978075 ps
CPU time 597.3 seconds
Started Jul 06 05:43:16 PM PDT 24
Finished Jul 06 05:53:13 PM PDT 24
Peak memory 2431400 kb
Host smart-9744484c-e4eb-4e81-add5-016e8e63999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293786124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.293786124
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1870359640
Short name T280
Test name
Test status
Simulation time 9377303094 ps
CPU time 39.28 seconds
Started Jul 06 05:43:04 PM PDT 24
Finished Jul 06 05:43:44 PM PDT 24
Peak memory 253936 kb
Host smart-391ac16e-e045-4de4-9da4-0b82afdc496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870359640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1870359640
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.777167135
Short name T133
Test name
Test status
Simulation time 40388423503 ps
CPU time 818.75 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:56:50 PM PDT 24
Peak memory 1891216 kb
Host smart-34fbb99a-8c73-4c3a-aa5c-0fbda4890f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777167135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.777167135
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3363021477
Short name T295
Test name
Test status
Simulation time 3829735103 ps
CPU time 36.5 seconds
Started Jul 06 05:43:13 PM PDT 24
Finished Jul 06 05:43:50 PM PDT 24
Peak memory 213264 kb
Host smart-ed5eb7fd-eb5a-4ac7-b588-d5f17afba904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363021477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3363021477
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.636485427
Short name T1105
Test name
Test status
Simulation time 5287495517 ps
CPU time 3.37 seconds
Started Jul 06 05:43:15 PM PDT 24
Finished Jul 06 05:43:18 PM PDT 24
Peak memory 205148 kb
Host smart-5532c518-8a70-4d19-b724-28b1a5ddc64d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636485427 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.636485427
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3625787754
Short name T1153
Test name
Test status
Simulation time 240438032 ps
CPU time 1.35 seconds
Started Jul 06 05:43:12 PM PDT 24
Finished Jul 06 05:43:14 PM PDT 24
Peak memory 204808 kb
Host smart-81b30a4d-196f-4337-bd85-8793611cd6eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625787754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3625787754
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3900359798
Short name T292
Test name
Test status
Simulation time 335960481 ps
CPU time 1.19 seconds
Started Jul 06 05:43:15 PM PDT 24
Finished Jul 06 05:43:17 PM PDT 24
Peak memory 213288 kb
Host smart-442ca239-7d59-4cc5-993e-fe7c9d5ebaa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900359798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3900359798
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3298757595
Short name T1133
Test name
Test status
Simulation time 156323106 ps
CPU time 1.22 seconds
Started Jul 06 05:43:18 PM PDT 24
Finished Jul 06 05:43:19 PM PDT 24
Peak memory 204784 kb
Host smart-1d19df06-a42d-4bec-b8d4-f7eb022b4236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298757595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3298757595
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.1927878270
Short name T385
Test name
Test status
Simulation time 247623464 ps
CPU time 1.22 seconds
Started Jul 06 05:43:17 PM PDT 24
Finished Jul 06 05:43:19 PM PDT 24
Peak memory 204808 kb
Host smart-b22ffec7-94e7-465e-92a9-8ed07f7c439a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927878270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.1927878270
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1929832471
Short name T953
Test name
Test status
Simulation time 1030548711 ps
CPU time 5.24 seconds
Started Jul 06 05:43:13 PM PDT 24
Finished Jul 06 05:43:19 PM PDT 24
Peak memory 213252 kb
Host smart-3a6485d8-4775-4b1e-a0c4-1b5104a34f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929832471 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1929832471
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3964005507
Short name T624
Test name
Test status
Simulation time 5398115611 ps
CPU time 59.26 seconds
Started Jul 06 05:43:16 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 1462416 kb
Host smart-ed83f3bf-3d3d-48f4-a656-3bdf44dc2566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964005507 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3964005507
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2974064274
Short name T1436
Test name
Test status
Simulation time 1049944018 ps
CPU time 12.73 seconds
Started Jul 06 05:43:12 PM PDT 24
Finished Jul 06 05:43:25 PM PDT 24
Peak memory 205036 kb
Host smart-391a7817-625e-4b90-a0d9-e05ae86d0531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974064274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2974064274
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1255985252
Short name T856
Test name
Test status
Simulation time 2592608550 ps
CPU time 18.95 seconds
Started Jul 06 05:43:09 PM PDT 24
Finished Jul 06 05:43:29 PM PDT 24
Peak memory 224560 kb
Host smart-65f18f56-a29e-490d-95d7-f9a914c6ce9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255985252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1255985252
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2465793464
Short name T897
Test name
Test status
Simulation time 37431803942 ps
CPU time 166.75 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:45:58 PM PDT 24
Peak memory 2249568 kb
Host smart-95032373-a734-4af0-98e5-9db434f2c8ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465793464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2465793464
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.102532048
Short name T1139
Test name
Test status
Simulation time 897778943 ps
CPU time 16.98 seconds
Started Jul 06 05:43:11 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 282420 kb
Host smart-3ee1dd3b-5feb-4af6-91c2-e43910d43d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102532048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.102532048
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3261209669
Short name T1426
Test name
Test status
Simulation time 6743418299 ps
CPU time 7.46 seconds
Started Jul 06 05:43:12 PM PDT 24
Finished Jul 06 05:43:20 PM PDT 24
Peak memory 213848 kb
Host smart-ede662ae-bb79-4a60-a61b-e814d97548f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261209669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3261209669
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.1041866236
Short name T969
Test name
Test status
Simulation time 118548902 ps
CPU time 2.5 seconds
Started Jul 06 05:43:16 PM PDT 24
Finished Jul 06 05:43:18 PM PDT 24
Peak memory 204952 kb
Host smart-39ad05ad-5111-4339-bccf-5cb52f572977
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041866236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.1041866236
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2215862990
Short name T1199
Test name
Test status
Simulation time 45948537 ps
CPU time 0.68 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:43:29 PM PDT 24
Peak memory 204616 kb
Host smart-2f0364da-f711-40d7-88ea-2a1e65ba7fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215862990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2215862990
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4049172581
Short name T1074
Test name
Test status
Simulation time 179799033 ps
CPU time 2.14 seconds
Started Jul 06 05:43:26 PM PDT 24
Finished Jul 06 05:43:29 PM PDT 24
Peak memory 213304 kb
Host smart-ec1d4be7-a7ed-4ad5-9ecf-0c6363d837ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049172581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4049172581
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1392231117
Short name T386
Test name
Test status
Simulation time 4757464401 ps
CPU time 7.4 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:43:33 PM PDT 24
Peak memory 278016 kb
Host smart-5f6c5792-3e35-49a9-9011-fc74e7b2ca66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392231117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1392231117
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2363318157
Short name T933
Test name
Test status
Simulation time 2304161363 ps
CPU time 76.45 seconds
Started Jul 06 05:43:22 PM PDT 24
Finished Jul 06 05:44:39 PM PDT 24
Peak memory 780868 kb
Host smart-45b87ecb-2a4e-49ec-9860-a7980ecb67ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363318157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2363318157
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3568927903
Short name T698
Test name
Test status
Simulation time 12625904114 ps
CPU time 171.67 seconds
Started Jul 06 05:43:23 PM PDT 24
Finished Jul 06 05:46:15 PM PDT 24
Peak memory 730148 kb
Host smart-57bfa086-fdf1-4f6b-93fc-4d6f5f0cca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568927903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3568927903
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2372291005
Short name T362
Test name
Test status
Simulation time 284084258 ps
CPU time 0.89 seconds
Started Jul 06 05:43:24 PM PDT 24
Finished Jul 06 05:43:25 PM PDT 24
Peak memory 204720 kb
Host smart-71791a01-2588-499d-a25d-1f4bde384ba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372291005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2372291005
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3489600813
Short name T143
Test name
Test status
Simulation time 417983908 ps
CPU time 11.35 seconds
Started Jul 06 05:43:23 PM PDT 24
Finished Jul 06 05:43:35 PM PDT 24
Peak memory 205036 kb
Host smart-df78c994-fd8c-46dd-b12f-86b853fe14b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489600813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3489600813
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.4249741739
Short name T340
Test name
Test status
Simulation time 58465289594 ps
CPU time 139.51 seconds
Started Jul 06 05:43:15 PM PDT 24
Finished Jul 06 05:45:35 PM PDT 24
Peak memory 1300292 kb
Host smart-78756956-55b1-482d-858e-0d0097c7ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249741739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.4249741739
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.142045821
Short name T673
Test name
Test status
Simulation time 1294321884 ps
CPU time 13.9 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:43:42 PM PDT 24
Peak memory 205048 kb
Host smart-abf8005f-0956-4bdb-8cb4-82be6d478711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142045821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.142045821
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.245566308
Short name T669
Test name
Test status
Simulation time 1303672392 ps
CPU time 24.34 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:51 PM PDT 24
Peak memory 308840 kb
Host smart-5616e48f-78f1-4081-9a4b-e1d707bdfc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245566308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.245566308
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3660962474
Short name T584
Test name
Test status
Simulation time 18771842 ps
CPU time 0.76 seconds
Started Jul 06 05:43:19 PM PDT 24
Finished Jul 06 05:43:20 PM PDT 24
Peak memory 204728 kb
Host smart-696deaec-3a6c-4bd3-844a-de74c7e8e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660962474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3660962474
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3302830600
Short name T1116
Test name
Test status
Simulation time 5191760577 ps
CPU time 56.12 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:44:21 PM PDT 24
Peak memory 221320 kb
Host smart-d07bc529-344c-4a70-acf9-91ed1cc86863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302830600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3302830600
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3165464140
Short name T809
Test name
Test status
Simulation time 2332701033 ps
CPU time 144.76 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:45:50 PM PDT 24
Peak memory 760984 kb
Host smart-65c0d17b-ee8e-4c5e-874c-419f00f17c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165464140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3165464140
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.388724551
Short name T1100
Test name
Test status
Simulation time 1030820353 ps
CPU time 18.72 seconds
Started Jul 06 05:43:19 PM PDT 24
Finished Jul 06 05:43:38 PM PDT 24
Peak memory 277804 kb
Host smart-a71242a0-ce1e-4d8c-b6de-17a9e6994081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388724551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.388724551
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1734293015
Short name T589
Test name
Test status
Simulation time 5977740477 ps
CPU time 47.91 seconds
Started Jul 06 05:43:22 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 215660 kb
Host smart-a76af97a-2a91-43ae-b8ea-775833cfd8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734293015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1734293015
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3469491031
Short name T511
Test name
Test status
Simulation time 4468850548 ps
CPU time 6.07 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:43:31 PM PDT 24
Peak memory 214992 kb
Host smart-868f6572-f3e8-4ecb-adc7-6d6b7e0f5bc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469491031 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3469491031
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1268535529
Short name T864
Test name
Test status
Simulation time 255148055 ps
CPU time 1.5 seconds
Started Jul 06 05:43:26 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 213244 kb
Host smart-f765ca2e-00a2-4236-898d-d5ef4c5369b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268535529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1268535529
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1029648380
Short name T1307
Test name
Test status
Simulation time 839404982 ps
CPU time 1.46 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 205016 kb
Host smart-c2fc5f4c-ef45-47ec-8f24-36e38eda8920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029648380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1029648380
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.3311892938
Short name T1319
Test name
Test status
Simulation time 430768679 ps
CPU time 2.46 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 204992 kb
Host smart-1557fe60-21ed-43eb-a8e7-87f67d37d6c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311892938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.3311892938
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.3398810966
Short name T587
Test name
Test status
Simulation time 183856842 ps
CPU time 1.1 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 204824 kb
Host smart-530e3c54-b71f-443d-85e4-b4d3040a3640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398810966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3398810966
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2005134281
Short name T925
Test name
Test status
Simulation time 474512950 ps
CPU time 4.62 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:43:33 PM PDT 24
Peak memory 205080 kb
Host smart-cfb036ba-9caf-4082-8e1a-6f1744449943
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005134281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2005134281
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.201933136
Short name T850
Test name
Test status
Simulation time 776060296 ps
CPU time 4.01 seconds
Started Jul 06 05:43:26 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 205024 kb
Host smart-15eb3e66-690e-4606-84ed-f3c486670545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201933136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.201933136
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4023192667
Short name T685
Test name
Test status
Simulation time 13481625622 ps
CPU time 115.42 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:45:24 PM PDT 24
Peak memory 1737804 kb
Host smart-757fccc2-ba02-409c-8b2c-f5bda86cab14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023192667 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4023192667
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1611898030
Short name T146
Test name
Test status
Simulation time 4608710301 ps
CPU time 14.17 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:43:39 PM PDT 24
Peak memory 205068 kb
Host smart-a1ac46c5-06fd-4ade-9d34-0b41ff4293d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611898030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1611898030
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3154487374
Short name T767
Test name
Test status
Simulation time 7709636222 ps
CPU time 24.23 seconds
Started Jul 06 05:43:22 PM PDT 24
Finished Jul 06 05:43:47 PM PDT 24
Peak memory 205036 kb
Host smart-d80190af-bc88-4281-a911-ce995cd97673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154487374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3154487374
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.958436283
Short name T1104
Test name
Test status
Simulation time 25158535924 ps
CPU time 16.96 seconds
Started Jul 06 05:43:24 PM PDT 24
Finished Jul 06 05:43:41 PM PDT 24
Peak memory 375156 kb
Host smart-4d9420ca-d7e9-4b1d-b0b2-b3e69d93d6fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958436283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.958436283
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3948820100
Short name T620
Test name
Test status
Simulation time 2596117084 ps
CPU time 4.69 seconds
Started Jul 06 05:43:25 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 229400 kb
Host smart-10ecf995-b50c-4b2c-87ae-874aa57205b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948820100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3948820100
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1061199864
Short name T1154
Test name
Test status
Simulation time 2799855214 ps
CPU time 7.6 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:43:35 PM PDT 24
Peak memory 213332 kb
Host smart-6ce2e328-96ae-4345-9bc8-cadac07125c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061199864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1061199864
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.2351024566
Short name T599
Test name
Test status
Simulation time 496053683 ps
CPU time 6.68 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:34 PM PDT 24
Peak memory 205036 kb
Host smart-2ecceb03-9109-4708-a7da-aef070931749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351024566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.2351024566
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3688361803
Short name T585
Test name
Test status
Simulation time 40174593 ps
CPU time 0.6 seconds
Started Jul 06 05:43:39 PM PDT 24
Finished Jul 06 05:43:40 PM PDT 24
Peak memory 204548 kb
Host smart-4ca95681-5a49-4fed-a8b3-32ab2240ac00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688361803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3688361803
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.4284794729
Short name T619
Test name
Test status
Simulation time 248602889 ps
CPU time 3.87 seconds
Started Jul 06 05:43:31 PM PDT 24
Finished Jul 06 05:43:35 PM PDT 24
Peak memory 243204 kb
Host smart-e42d0d80-5be0-4dc9-9209-ad035b1a6d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284794729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.4284794729
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1643701169
Short name T795
Test name
Test status
Simulation time 1480783647 ps
CPU time 3.31 seconds
Started Jul 06 05:43:24 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 229624 kb
Host smart-e85559f0-d082-45f8-bf48-f852c690fdf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643701169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1643701169
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.77925230
Short name T1287
Test name
Test status
Simulation time 2100883689 ps
CPU time 118.56 seconds
Started Jul 06 05:43:33 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 454628 kb
Host smart-5d52959f-50ef-4f51-ac8b-1ac2f4cc1c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77925230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.77925230
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.741413528
Short name T1305
Test name
Test status
Simulation time 8468466817 ps
CPU time 146.86 seconds
Started Jul 06 05:43:26 PM PDT 24
Finished Jul 06 05:45:53 PM PDT 24
Peak memory 654816 kb
Host smart-abc0d901-fe7f-4ad6-bae9-d9b07c704a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741413528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.741413528
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2233710240
Short name T1299
Test name
Test status
Simulation time 88347983 ps
CPU time 0.83 seconds
Started Jul 06 05:43:27 PM PDT 24
Finished Jul 06 05:43:28 PM PDT 24
Peak memory 204756 kb
Host smart-16ac33b6-4532-4010-9aed-1ae9b87a2450
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233710240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2233710240
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3560706429
Short name T469
Test name
Test status
Simulation time 565175182 ps
CPU time 4.03 seconds
Started Jul 06 05:43:33 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 230632 kb
Host smart-f85b33b0-d169-44d0-b4a5-f024ed754e29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560706429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3560706429
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2652290988
Short name T1315
Test name
Test status
Simulation time 4401821381 ps
CPU time 136.63 seconds
Started Jul 06 05:43:26 PM PDT 24
Finished Jul 06 05:45:43 PM PDT 24
Peak memory 1270548 kb
Host smart-d81ac6c0-0711-4e50-a0ef-f7578ba7cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652290988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2652290988
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2808934011
Short name T226
Test name
Test status
Simulation time 647276045 ps
CPU time 9.68 seconds
Started Jul 06 05:43:39 PM PDT 24
Finished Jul 06 05:43:49 PM PDT 24
Peak memory 205096 kb
Host smart-07cb15cc-21f8-4775-bb37-363a8d2d19a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808934011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2808934011
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2599883779
Short name T63
Test name
Test status
Simulation time 6584424066 ps
CPU time 77.47 seconds
Started Jul 06 05:43:38 PM PDT 24
Finished Jul 06 05:44:56 PM PDT 24
Peak memory 278380 kb
Host smart-b7b75096-27e3-4257-9232-a0e027bf2938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599883779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2599883779
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2301137035
Short name T777
Test name
Test status
Simulation time 7440573586 ps
CPU time 100.37 seconds
Started Jul 06 05:43:32 PM PDT 24
Finished Jul 06 05:45:13 PM PDT 24
Peak memory 205084 kb
Host smart-cd0710f1-a129-4810-8675-3d64e13f055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301137035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2301137035
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.1382746023
Short name T315
Test name
Test status
Simulation time 1288272859 ps
CPU time 7.72 seconds
Started Jul 06 05:43:31 PM PDT 24
Finished Jul 06 05:43:39 PM PDT 24
Peak memory 234096 kb
Host smart-98ce4e64-ce12-4a60-b613-f20063f40aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382746023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1382746023
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4147325573
Short name T333
Test name
Test status
Simulation time 11828767992 ps
CPU time 39.28 seconds
Started Jul 06 05:43:28 PM PDT 24
Finished Jul 06 05:44:08 PM PDT 24
Peak memory 375136 kb
Host smart-a567f46e-df87-465f-bd80-20a89ab25377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147325573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4147325573
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3365320190
Short name T1437
Test name
Test status
Simulation time 39013448027 ps
CPU time 1357 seconds
Started Jul 06 05:43:33 PM PDT 24
Finished Jul 06 06:06:11 PM PDT 24
Peak memory 4095344 kb
Host smart-fc765d46-bdc4-4940-8efd-029011b95b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365320190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3365320190
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1232789082
Short name T904
Test name
Test status
Simulation time 2509620792 ps
CPU time 11.31 seconds
Started Jul 06 05:43:31 PM PDT 24
Finished Jul 06 05:43:43 PM PDT 24
Peak memory 217628 kb
Host smart-62ea7495-46ba-4f49-a806-40902ffa8fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232789082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1232789082
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2402081970
Short name T621
Test name
Test status
Simulation time 2153670376 ps
CPU time 5.01 seconds
Started Jul 06 05:43:39 PM PDT 24
Finished Jul 06 05:43:45 PM PDT 24
Peak memory 213256 kb
Host smart-aa85bc5e-d158-4653-a914-9e78dac6170c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402081970 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2402081970
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3855617363
Short name T510
Test name
Test status
Simulation time 485342202 ps
CPU time 1.47 seconds
Started Jul 06 05:43:31 PM PDT 24
Finished Jul 06 05:43:33 PM PDT 24
Peak memory 205028 kb
Host smart-5853d6db-03a4-48ff-b63e-8803f1303b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855617363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3855617363
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1305974499
Short name T1286
Test name
Test status
Simulation time 205095158 ps
CPU time 0.96 seconds
Started Jul 06 05:43:33 PM PDT 24
Finished Jul 06 05:43:34 PM PDT 24
Peak memory 204728 kb
Host smart-08372f53-ca07-4c1e-af59-7d0c74ea5b8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305974499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1305974499
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.1357822725
Short name T237
Test name
Test status
Simulation time 2126891995 ps
CPU time 2.72 seconds
Started Jul 06 05:43:37 PM PDT 24
Finished Jul 06 05:43:40 PM PDT 24
Peak memory 204980 kb
Host smart-1d7ddb11-6b78-4081-b050-4eba15c3151d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357822725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.1357822725
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.3657201461
Short name T1493
Test name
Test status
Simulation time 775946429 ps
CPU time 1.41 seconds
Started Jul 06 05:43:39 PM PDT 24
Finished Jul 06 05:43:41 PM PDT 24
Peak memory 204836 kb
Host smart-1f538ddc-b921-4426-b3bf-616e23d79791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657201461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.3657201461
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.4037796636
Short name T233
Test name
Test status
Simulation time 768337778 ps
CPU time 3.13 seconds
Started Jul 06 05:43:37 PM PDT 24
Finished Jul 06 05:43:40 PM PDT 24
Peak memory 205076 kb
Host smart-5fc56807-86ab-4221-b97e-81cb7291fae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037796636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.4037796636
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4153179007
Short name T950
Test name
Test status
Simulation time 3356305410 ps
CPU time 4.42 seconds
Started Jul 06 05:43:32 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 213208 kb
Host smart-84ba1423-46be-498c-96da-ba20a32f00ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153179007 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4153179007
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.223133930
Short name T1066
Test name
Test status
Simulation time 9169826057 ps
CPU time 6.29 seconds
Started Jul 06 05:43:34 PM PDT 24
Finished Jul 06 05:43:41 PM PDT 24
Peak memory 205128 kb
Host smart-dc47cbe5-1557-4b29-94bd-bad60502dc1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223133930 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.223133930
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3369647293
Short name T147
Test name
Test status
Simulation time 5265551619 ps
CPU time 11.13 seconds
Started Jul 06 05:43:34 PM PDT 24
Finished Jul 06 05:43:46 PM PDT 24
Peak memory 205140 kb
Host smart-af38c68b-6ffc-4fff-9e37-8bd409f33531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369647293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3369647293
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.992136475
Short name T1279
Test name
Test status
Simulation time 2084941568 ps
CPU time 16.47 seconds
Started Jul 06 05:43:32 PM PDT 24
Finished Jul 06 05:43:49 PM PDT 24
Peak memory 223540 kb
Host smart-6306ccc7-2ffd-422c-ac2d-6b1a623044fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992136475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.992136475
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3881226110
Short name T1252
Test name
Test status
Simulation time 19963014861 ps
CPU time 35.39 seconds
Started Jul 06 05:43:31 PM PDT 24
Finished Jul 06 05:44:07 PM PDT 24
Peak memory 205072 kb
Host smart-c78391d2-9e47-48d1-8ceb-58a8d7858257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881226110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3881226110
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2090218634
Short name T962
Test name
Test status
Simulation time 5057940422 ps
CPU time 231.84 seconds
Started Jul 06 05:43:30 PM PDT 24
Finished Jul 06 05:47:22 PM PDT 24
Peak memory 1145316 kb
Host smart-3bc83ceb-0488-4bc4-bf97-b532ce69220c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090218634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2090218634
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2269502355
Short name T832
Test name
Test status
Simulation time 1564867666 ps
CPU time 8.32 seconds
Started Jul 06 05:43:30 PM PDT 24
Finished Jul 06 05:43:39 PM PDT 24
Peak memory 218428 kb
Host smart-7abff3d5-6bb9-4240-b1bf-a62034603cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269502355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2269502355
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.951287875
Short name T22
Test name
Test status
Simulation time 67854867 ps
CPU time 1.49 seconds
Started Jul 06 05:43:35 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 205052 kb
Host smart-211d6c58-f21b-42b3-8a3c-b786a83ad983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951287875 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.951287875
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2382887103
Short name T271
Test name
Test status
Simulation time 19257703 ps
CPU time 0.6 seconds
Started Jul 06 05:43:47 PM PDT 24
Finished Jul 06 05:43:47 PM PDT 24
Peak memory 204628 kb
Host smart-52c4c0ea-e65b-4524-bea7-ae0ea264a7c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382887103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2382887103
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3447106147
Short name T879
Test name
Test status
Simulation time 383194214 ps
CPU time 2.65 seconds
Started Jul 06 05:43:40 PM PDT 24
Finished Jul 06 05:43:44 PM PDT 24
Peak memory 213332 kb
Host smart-4d191e85-82d4-4236-ae8f-3657047739b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447106147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3447106147
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.4293596497
Short name T1522
Test name
Test status
Simulation time 2548209996 ps
CPU time 16.19 seconds
Started Jul 06 05:43:37 PM PDT 24
Finished Jul 06 05:43:53 PM PDT 24
Peak memory 271184 kb
Host smart-7c40a7b9-7beb-4e3f-99e2-b16fde42e316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293596497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.4293596497
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3179231348
Short name T518
Test name
Test status
Simulation time 15981879762 ps
CPU time 182.57 seconds
Started Jul 06 05:43:35 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 735376 kb
Host smart-c75ebd9f-2086-4b55-b8c5-72531faeb135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179231348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3179231348
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.4238955396
Short name T342
Test name
Test status
Simulation time 98591689 ps
CPU time 1.15 seconds
Started Jul 06 05:43:36 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 204964 kb
Host smart-36c07591-0148-4dd3-be13-3adecd63f8bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238955396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.4238955396
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2381127644
Short name T64
Test name
Test status
Simulation time 763768902 ps
CPU time 3.96 seconds
Started Jul 06 05:43:40 PM PDT 24
Finished Jul 06 05:43:45 PM PDT 24
Peak memory 205044 kb
Host smart-03461c23-c72e-4ca2-b4fd-06d35d807063
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381127644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2381127644
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1269666936
Short name T728
Test name
Test status
Simulation time 6434576718 ps
CPU time 279.15 seconds
Started Jul 06 05:43:34 PM PDT 24
Finished Jul 06 05:48:14 PM PDT 24
Peak memory 1161524 kb
Host smart-65b423df-9cda-4c08-a7cc-80298cb9ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269666936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1269666936
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3763408016
Short name T438
Test name
Test status
Simulation time 2031564805 ps
CPU time 3.29 seconds
Started Jul 06 05:43:45 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 205036 kb
Host smart-b641e777-c66d-4626-aaff-b6d8eef607d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763408016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3763408016
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3378026964
Short name T1282
Test name
Test status
Simulation time 1698612013 ps
CPU time 79.16 seconds
Started Jul 06 05:43:43 PM PDT 24
Finished Jul 06 05:45:02 PM PDT 24
Peak memory 359248 kb
Host smart-230bc6c8-bd02-4f4f-bb54-fd5d60934920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378026964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3378026964
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.4040521496
Short name T926
Test name
Test status
Simulation time 94718323 ps
CPU time 0.69 seconds
Started Jul 06 05:43:36 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 204732 kb
Host smart-046155ca-4a0a-412f-8578-c8797bcff143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040521496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.4040521496
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4132391181
Short name T1204
Test name
Test status
Simulation time 782597795 ps
CPU time 3.56 seconds
Started Jul 06 05:43:43 PM PDT 24
Finished Jul 06 05:43:47 PM PDT 24
Peak memory 233000 kb
Host smart-9056f1d2-eb81-42c4-b4fb-2fe69589aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132391181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4132391181
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3012724065
Short name T437
Test name
Test status
Simulation time 669072262 ps
CPU time 25.53 seconds
Started Jul 06 05:43:41 PM PDT 24
Finished Jul 06 05:44:07 PM PDT 24
Peak memory 204976 kb
Host smart-f371f824-5537-4ef0-a9d4-18f1332ded85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012724065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3012724065
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.4281237058
Short name T1294
Test name
Test status
Simulation time 1521986773 ps
CPU time 73.7 seconds
Started Jul 06 05:43:37 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 296912 kb
Host smart-c6197719-90c4-4767-9f00-9028181bc4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281237058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4281237058
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1899687762
Short name T985
Test name
Test status
Simulation time 16961270486 ps
CPU time 2293.07 seconds
Started Jul 06 05:43:42 PM PDT 24
Finished Jul 06 06:21:56 PM PDT 24
Peak memory 3167016 kb
Host smart-408bb069-ba54-474b-afeb-151ae5d1f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899687762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1899687762
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3028573789
Short name T472
Test name
Test status
Simulation time 569148167 ps
CPU time 25.67 seconds
Started Jul 06 05:43:45 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 213220 kb
Host smart-efc970bc-aa44-4a49-a3f9-e1f46215ddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028573789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3028573789
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1954460021
Short name T409
Test name
Test status
Simulation time 448367003 ps
CPU time 2.54 seconds
Started Jul 06 05:43:45 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 205012 kb
Host smart-e80c6961-1282-4523-ba24-d7faa6f71527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954460021 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1954460021
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1985561833
Short name T436
Test name
Test status
Simulation time 234484698 ps
CPU time 1.29 seconds
Started Jul 06 05:43:45 PM PDT 24
Finished Jul 06 05:43:46 PM PDT 24
Peak memory 204804 kb
Host smart-fdae3ad8-d985-4c90-a6a4-f8cf2f582ab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985561833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1985561833
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.4211414349
Short name T846
Test name
Test status
Simulation time 155529038 ps
CPU time 1.12 seconds
Started Jul 06 05:43:46 PM PDT 24
Finished Jul 06 05:43:47 PM PDT 24
Peak memory 213268 kb
Host smart-c2326d0e-76b5-46ad-80fa-424ee84a1691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211414349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.4211414349
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.4158118212
Short name T812
Test name
Test status
Simulation time 421272246 ps
CPU time 2.36 seconds
Started Jul 06 05:43:46 PM PDT 24
Finished Jul 06 05:43:49 PM PDT 24
Peak memory 204984 kb
Host smart-b8f8bb8a-41df-4fdf-98fc-3d8913c45328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158118212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.4158118212
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.2663356597
Short name T951
Test name
Test status
Simulation time 306152114 ps
CPU time 1 seconds
Started Jul 06 05:43:46 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 204836 kb
Host smart-981e9fed-4aa5-489e-a4f0-3d77ef5ded8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663356597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.2663356597
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1395295253
Short name T1118
Test name
Test status
Simulation time 2781413538 ps
CPU time 3.45 seconds
Started Jul 06 05:43:40 PM PDT 24
Finished Jul 06 05:43:44 PM PDT 24
Peak memory 205204 kb
Host smart-26ea7c38-5583-4954-84ef-352b45c16101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395295253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1395295253
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.993977862
Short name T1340
Test name
Test status
Simulation time 6410145018 ps
CPU time 6.03 seconds
Started Jul 06 05:43:41 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 220428 kb
Host smart-b2ce91ab-e2dc-48ce-8023-2722c85620cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993977862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.993977862
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2065106036
Short name T326
Test name
Test status
Simulation time 14418399244 ps
CPU time 81 seconds
Started Jul 06 05:43:40 PM PDT 24
Finished Jul 06 05:45:02 PM PDT 24
Peak memory 1755376 kb
Host smart-0c32f141-b000-4ebf-830c-96bb1e517658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065106036 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2065106036
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1034370000
Short name T1276
Test name
Test status
Simulation time 1716882464 ps
CPU time 31.6 seconds
Started Jul 06 05:43:42 PM PDT 24
Finished Jul 06 05:44:14 PM PDT 24
Peak memory 205060 kb
Host smart-6767f929-63b5-4516-9fb8-e66460042b2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034370000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1034370000
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3063975171
Short name T1285
Test name
Test status
Simulation time 9719145344 ps
CPU time 71.39 seconds
Started Jul 06 05:43:41 PM PDT 24
Finished Jul 06 05:44:53 PM PDT 24
Peak memory 211832 kb
Host smart-d2a0e31d-2ab5-4db0-a3d4-03ebc4f7f514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063975171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3063975171
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3302592542
Short name T138
Test name
Test status
Simulation time 23295517686 ps
CPU time 68.89 seconds
Started Jul 06 05:43:43 PM PDT 24
Finished Jul 06 05:44:52 PM PDT 24
Peak memory 1007428 kb
Host smart-ba2cacf3-c9b5-4137-8045-b2ec5385a7ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302592542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3302592542
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2761187414
Short name T336
Test name
Test status
Simulation time 4049827211 ps
CPU time 32.69 seconds
Started Jul 06 05:43:41 PM PDT 24
Finished Jul 06 05:44:15 PM PDT 24
Peak memory 638688 kb
Host smart-2646e253-7f2f-472f-9b1e-380ee37c2b90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761187414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2761187414
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3581995846
Short name T977
Test name
Test status
Simulation time 1567870992 ps
CPU time 8.32 seconds
Started Jul 06 05:43:41 PM PDT 24
Finished Jul 06 05:43:50 PM PDT 24
Peak memory 220116 kb
Host smart-c8502f3e-26e1-4b89-a737-03b83ae199da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581995846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3581995846
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1960515267
Short name T350
Test name
Test status
Simulation time 586661125 ps
CPU time 7.95 seconds
Started Jul 06 05:43:47 PM PDT 24
Finished Jul 06 05:43:55 PM PDT 24
Peak memory 205028 kb
Host smart-9245e055-0578-4c90-a0da-6a814be8f10f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960515267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1960515267
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3749493064
Short name T1055
Test name
Test status
Simulation time 20232250 ps
CPU time 0.68 seconds
Started Jul 06 05:44:05 PM PDT 24
Finished Jul 06 05:44:06 PM PDT 24
Peak memory 204632 kb
Host smart-999ba232-bac5-459c-9621-0d2b88e6f3dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749493064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3749493064
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.61843280
Short name T1482
Test name
Test status
Simulation time 150717785 ps
CPU time 1.49 seconds
Started Jul 06 05:43:52 PM PDT 24
Finished Jul 06 05:43:54 PM PDT 24
Peak memory 213328 kb
Host smart-5e33e433-ae6b-4e8e-837c-c72b4b0bbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61843280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.61843280
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.100261567
Short name T497
Test name
Test status
Simulation time 1194777397 ps
CPU time 15.01 seconds
Started Jul 06 05:43:54 PM PDT 24
Finished Jul 06 05:44:10 PM PDT 24
Peak memory 265584 kb
Host smart-91269a27-69e3-42e7-9830-ab16b7525b76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100261567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.100261567
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1353994788
Short name T1184
Test name
Test status
Simulation time 8353610604 ps
CPU time 79.42 seconds
Started Jul 06 05:43:53 PM PDT 24
Finished Jul 06 05:45:12 PM PDT 24
Peak memory 726228 kb
Host smart-3367feb0-9446-45cd-a314-eee0df4f394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353994788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1353994788
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3461138679
Short name T1160
Test name
Test status
Simulation time 6798176895 ps
CPU time 45.67 seconds
Started Jul 06 05:43:55 PM PDT 24
Finished Jul 06 05:44:41 PM PDT 24
Peak memory 611824 kb
Host smart-f61789c9-dc82-4beb-873c-1f1a755fca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461138679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3461138679
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.4081165124
Short name T455
Test name
Test status
Simulation time 147326393 ps
CPU time 1.08 seconds
Started Jul 06 05:43:52 PM PDT 24
Finished Jul 06 05:43:54 PM PDT 24
Peak memory 204772 kb
Host smart-6e0334ac-0453-480f-8571-4f037d3340d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081165124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.4081165124
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.194625962
Short name T1034
Test name
Test status
Simulation time 295403950 ps
CPU time 11.92 seconds
Started Jul 06 05:43:54 PM PDT 24
Finished Jul 06 05:44:07 PM PDT 24
Peak memory 245308 kb
Host smart-56c65b5f-1700-4b91-8fa6-13507ff5fa96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194625962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
194625962
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.316958045
Short name T54
Test name
Test status
Simulation time 4344075101 ps
CPU time 123.74 seconds
Started Jul 06 05:43:54 PM PDT 24
Finished Jul 06 05:45:58 PM PDT 24
Peak memory 1218964 kb
Host smart-c6a3c0a2-737c-48db-ab94-6f0204299b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316958045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.316958045
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3205342064
Short name T293
Test name
Test status
Simulation time 286394825 ps
CPU time 11.39 seconds
Started Jul 06 05:43:59 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 205032 kb
Host smart-28390709-837b-4e00-a7ec-cc12f776639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205342064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3205342064
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.4129418423
Short name T1303
Test name
Test status
Simulation time 1797965284 ps
CPU time 86.93 seconds
Started Jul 06 05:43:57 PM PDT 24
Finished Jul 06 05:45:24 PM PDT 24
Peak memory 461232 kb
Host smart-cfc26497-287f-49e7-96a0-6ef57f3a6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129418423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4129418423
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.4117573065
Short name T1321
Test name
Test status
Simulation time 27846584 ps
CPU time 0.69 seconds
Started Jul 06 05:43:45 PM PDT 24
Finished Jul 06 05:43:46 PM PDT 24
Peak memory 204688 kb
Host smart-6f9dc41c-ba25-4b24-aa07-ea6145bc3753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117573065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4117573065
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3154329659
Short name T212
Test name
Test status
Simulation time 52535767206 ps
CPU time 1224.21 seconds
Started Jul 06 05:43:53 PM PDT 24
Finished Jul 06 06:04:18 PM PDT 24
Peak memory 442712 kb
Host smart-ab9cc7bd-22be-431a-9340-6b44ec021fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154329659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3154329659
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.542852603
Short name T1275
Test name
Test status
Simulation time 23278310267 ps
CPU time 867.85 seconds
Started Jul 06 05:43:55 PM PDT 24
Finished Jul 06 05:58:23 PM PDT 24
Peak memory 205064 kb
Host smart-d34583d8-85f9-4e74-b9af-cef599582ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542852603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.542852603
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.603030971
Short name T1221
Test name
Test status
Simulation time 1338260787 ps
CPU time 22.04 seconds
Started Jul 06 05:43:48 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 328296 kb
Host smart-89246f24-28fc-49fb-945e-c38ddce739f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603030971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.603030971
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.4134502426
Short name T79
Test name
Test status
Simulation time 27150399217 ps
CPU time 300.29 seconds
Started Jul 06 05:43:51 PM PDT 24
Finished Jul 06 05:48:52 PM PDT 24
Peak memory 1534792 kb
Host smart-14c7e7b9-4d4b-4886-8e56-dc09dfb84161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134502426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.4134502426
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3092353067
Short name T254
Test name
Test status
Simulation time 2934263710 ps
CPU time 16.97 seconds
Started Jul 06 05:43:54 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 221436 kb
Host smart-bd47d4d4-2d63-47ba-bb6d-ef3ddfc4c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092353067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3092353067
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.960611867
Short name T545
Test name
Test status
Simulation time 736180532 ps
CPU time 3.82 seconds
Started Jul 06 05:43:56 PM PDT 24
Finished Jul 06 05:44:00 PM PDT 24
Peak memory 213240 kb
Host smart-17cdf46f-bb6e-4a41-89b4-2a216ec17960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960611867 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.960611867
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3600489347
Short name T1316
Test name
Test status
Simulation time 142997744 ps
CPU time 0.95 seconds
Started Jul 06 05:44:02 PM PDT 24
Finished Jul 06 05:44:03 PM PDT 24
Peak memory 204804 kb
Host smart-816aec38-47c2-4b82-b308-7ee356c33a02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600489347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3600489347
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1820534327
Short name T1047
Test name
Test status
Simulation time 221470706 ps
CPU time 1.28 seconds
Started Jul 06 05:43:57 PM PDT 24
Finished Jul 06 05:43:59 PM PDT 24
Peak memory 205080 kb
Host smart-b618441f-45d7-4dd0-a0f1-ab55bb1dead2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820534327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1820534327
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.243670238
Short name T395
Test name
Test status
Simulation time 2206435580 ps
CPU time 2.78 seconds
Started Jul 06 05:44:00 PM PDT 24
Finished Jul 06 05:44:03 PM PDT 24
Peak memory 205064 kb
Host smart-23267aec-9ac0-4037-911e-6f098e27ee4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243670238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.243670238
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2857189292
Short name T798
Test name
Test status
Simulation time 609025580 ps
CPU time 1.22 seconds
Started Jul 06 05:43:57 PM PDT 24
Finished Jul 06 05:43:59 PM PDT 24
Peak memory 204792 kb
Host smart-03175010-f01a-4f42-a688-bc2f47ffcc7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857189292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2857189292
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1833888911
Short name T709
Test name
Test status
Simulation time 455792989 ps
CPU time 3.56 seconds
Started Jul 06 05:43:58 PM PDT 24
Finished Jul 06 05:44:02 PM PDT 24
Peak memory 205132 kb
Host smart-63112266-cca0-4e3b-9a16-a41195bbe000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833888911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1833888911
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3407358366
Short name T987
Test name
Test status
Simulation time 4446332937 ps
CPU time 6.13 seconds
Started Jul 06 05:44:00 PM PDT 24
Finished Jul 06 05:44:06 PM PDT 24
Peak memory 213312 kb
Host smart-712942f9-b3db-4310-b3c0-03f2edaa17b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407358366 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3407358366
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3481258403
Short name T1017
Test name
Test status
Simulation time 25936416692 ps
CPU time 645.74 seconds
Started Jul 06 05:43:58 PM PDT 24
Finished Jul 06 05:54:44 PM PDT 24
Peak memory 6449960 kb
Host smart-97c4b618-905c-4656-b5b3-7ab25f553da1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481258403 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3481258403
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2021680168
Short name T1422
Test name
Test status
Simulation time 1137068907 ps
CPU time 16.35 seconds
Started Jul 06 05:43:54 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 205040 kb
Host smart-2e053d8f-1a8d-4a0d-8581-b23737b8c1d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021680168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2021680168
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3244467660
Short name T745
Test name
Test status
Simulation time 2107815752 ps
CPU time 19.71 seconds
Started Jul 06 05:44:00 PM PDT 24
Finished Jul 06 05:44:20 PM PDT 24
Peak memory 213536 kb
Host smart-afa94b60-73fe-4bec-95af-c20bb4a5981b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244467660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3244467660
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.1810482881
Short name T1035
Test name
Test status
Simulation time 76432232661 ps
CPU time 181.35 seconds
Started Jul 06 05:43:52 PM PDT 24
Finished Jul 06 05:46:53 PM PDT 24
Peak memory 1895708 kb
Host smart-0759ec37-21e0-41d9-80a4-39a93c5b5a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810482881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.1810482881
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3567938479
Short name T1498
Test name
Test status
Simulation time 1199506442 ps
CPU time 6.21 seconds
Started Jul 06 05:44:00 PM PDT 24
Finished Jul 06 05:44:06 PM PDT 24
Peak memory 219504 kb
Host smart-a33222f1-45d8-49d6-8efd-03a2aca851e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567938479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3567938479
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.982534181
Short name T851
Test name
Test status
Simulation time 690383986 ps
CPU time 8.56 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:17 PM PDT 24
Peak memory 204992 kb
Host smart-b95fcda7-4b0a-42ad-9c9e-2da631bc9310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982534181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.982534181
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2135626764
Short name T1357
Test name
Test status
Simulation time 54772812 ps
CPU time 0.64 seconds
Started Jul 06 05:38:38 PM PDT 24
Finished Jul 06 05:38:39 PM PDT 24
Peak memory 204616 kb
Host smart-a7f08cc5-b5e1-435f-9818-25fb7fddd9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135626764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2135626764
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.765690365
Short name T298
Test name
Test status
Simulation time 478121130 ps
CPU time 1.47 seconds
Started Jul 06 05:38:33 PM PDT 24
Finished Jul 06 05:38:35 PM PDT 24
Peak memory 213336 kb
Host smart-3df13128-e557-492c-9354-7b4ce72b3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765690365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.765690365
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2290975838
Short name T450
Test name
Test status
Simulation time 451434476 ps
CPU time 23.93 seconds
Started Jul 06 05:38:37 PM PDT 24
Finished Jul 06 05:39:01 PM PDT 24
Peak memory 304564 kb
Host smart-8c3a1d95-cd30-45ed-b405-5a8a43888e00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290975838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2290975838
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2607048804
Short name T749
Test name
Test status
Simulation time 1497830380 ps
CPU time 83.39 seconds
Started Jul 06 05:38:36 PM PDT 24
Finished Jul 06 05:39:59 PM PDT 24
Peak memory 335492 kb
Host smart-10ff2f90-895d-41fb-9e44-d5aad3a434a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607048804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2607048804
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.414494915
Short name T1396
Test name
Test status
Simulation time 38666164091 ps
CPU time 159.97 seconds
Started Jul 06 05:38:34 PM PDT 24
Finished Jul 06 05:41:15 PM PDT 24
Peak memory 697960 kb
Host smart-ecc50b71-258c-438f-ad90-a2007a353153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414494915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.414494915
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1163949197
Short name T705
Test name
Test status
Simulation time 518915630 ps
CPU time 1.08 seconds
Started Jul 06 05:38:34 PM PDT 24
Finished Jul 06 05:38:35 PM PDT 24
Peak memory 204764 kb
Host smart-fc173b9e-7bd5-4cbd-a708-fe841b77af57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163949197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1163949197
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1685620447
Short name T1519
Test name
Test status
Simulation time 2031421774 ps
CPU time 6.47 seconds
Started Jul 06 05:38:33 PM PDT 24
Finished Jul 06 05:38:40 PM PDT 24
Peak memory 205040 kb
Host smart-caa5a2fd-af63-4fbe-8841-7dd468549ccb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685620447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1685620447
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2302668904
Short name T696
Test name
Test status
Simulation time 74563158993 ps
CPU time 395.34 seconds
Started Jul 06 05:38:29 PM PDT 24
Finished Jul 06 05:45:05 PM PDT 24
Peak memory 1500728 kb
Host smart-33c64953-b1cf-4933-8271-7bdc7611975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302668904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2302668904
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2996920767
Short name T1214
Test name
Test status
Simulation time 398717403 ps
CPU time 4.92 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:49 PM PDT 24
Peak memory 205088 kb
Host smart-47450c43-03d6-43d1-8ffb-1c93fad5c5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996920767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2996920767
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.4118018563
Short name T234
Test name
Test status
Simulation time 2702817933 ps
CPU time 17.13 seconds
Started Jul 06 05:38:40 PM PDT 24
Finished Jul 06 05:38:58 PM PDT 24
Peak memory 267892 kb
Host smart-c035c350-c573-4d9c-a98a-8651d036340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118018563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.4118018563
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2267638814
Short name T363
Test name
Test status
Simulation time 15221708 ps
CPU time 0.68 seconds
Started Jul 06 05:38:31 PM PDT 24
Finished Jul 06 05:38:32 PM PDT 24
Peak memory 204760 kb
Host smart-43e2a1b0-b468-4a71-a11a-cc9ea1c41c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267638814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2267638814
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1893419724
Short name T1052
Test name
Test status
Simulation time 2766071860 ps
CPU time 29.15 seconds
Started Jul 06 05:38:37 PM PDT 24
Finished Jul 06 05:39:06 PM PDT 24
Peak memory 213572 kb
Host smart-8159e986-3fa3-4f63-b721-a87d29dead40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893419724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1893419724
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.3242491058
Short name T995
Test name
Test status
Simulation time 379997211 ps
CPU time 4.26 seconds
Started Jul 06 05:38:33 PM PDT 24
Finished Jul 06 05:38:38 PM PDT 24
Peak memory 213356 kb
Host smart-050d55d5-f141-4bca-8038-5c876723fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242491058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3242491058
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3452745301
Short name T534
Test name
Test status
Simulation time 1728943064 ps
CPU time 29.22 seconds
Started Jul 06 05:38:32 PM PDT 24
Finished Jul 06 05:39:02 PM PDT 24
Peak memory 357972 kb
Host smart-a8410aad-90db-4861-bbe1-047889505bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452745301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3452745301
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3038995155
Short name T477
Test name
Test status
Simulation time 9374099501 ps
CPU time 38.89 seconds
Started Jul 06 05:38:35 PM PDT 24
Finished Jul 06 05:39:14 PM PDT 24
Peak memory 213328 kb
Host smart-0a7bc32c-f6bd-424e-bc46-5b4f56526cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038995155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3038995155
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2194939183
Short name T160
Test name
Test status
Simulation time 65528820 ps
CPU time 1.02 seconds
Started Jul 06 05:38:45 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 223268 kb
Host smart-fc3ba048-362d-4c25-a6fe-baf439a319cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194939183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2194939183
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1064098336
Short name T717
Test name
Test status
Simulation time 764315427 ps
CPU time 4.07 seconds
Started Jul 06 05:38:37 PM PDT 24
Finished Jul 06 05:38:41 PM PDT 24
Peak memory 204968 kb
Host smart-cbe3c84c-9a82-4073-a127-02f3b5f02f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064098336 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1064098336
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1036149170
Short name T1460
Test name
Test status
Simulation time 341344600 ps
CPU time 0.84 seconds
Started Jul 06 05:38:35 PM PDT 24
Finished Jul 06 05:38:36 PM PDT 24
Peak memory 204796 kb
Host smart-4b20abb9-678e-418a-a3e2-4bc34f367c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036149170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1036149170
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.1631962484
Short name T343
Test name
Test status
Simulation time 1007490963 ps
CPU time 1.68 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:47 PM PDT 24
Peak memory 204936 kb
Host smart-20a9505a-1011-425b-a2eb-6428c6bb0ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631962484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.1631962484
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1649619891
Short name T410
Test name
Test status
Simulation time 1795553272 ps
CPU time 1.19 seconds
Started Jul 06 05:38:41 PM PDT 24
Finished Jul 06 05:38:43 PM PDT 24
Peak memory 204836 kb
Host smart-6f1ee3ca-d4e8-4ea3-bbca-336bfb49d925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649619891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1649619891
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3063960629
Short name T695
Test name
Test status
Simulation time 1212711280 ps
CPU time 5.95 seconds
Started Jul 06 05:38:34 PM PDT 24
Finished Jul 06 05:38:40 PM PDT 24
Peak memory 212512 kb
Host smart-a75ac5bd-09ea-45d7-9a60-3363f493c08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063960629 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3063960629
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.37151614
Short name T1318
Test name
Test status
Simulation time 13658547241 ps
CPU time 18.18 seconds
Started Jul 06 05:38:33 PM PDT 24
Finished Jul 06 05:38:52 PM PDT 24
Peak memory 427512 kb
Host smart-1c7a3ff3-f6ea-4188-8671-f00959940cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37151614 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.37151614
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1747632539
Short name T590
Test name
Test status
Simulation time 12129526330 ps
CPU time 31.69 seconds
Started Jul 06 05:38:35 PM PDT 24
Finished Jul 06 05:39:07 PM PDT 24
Peak memory 204960 kb
Host smart-ca25aaeb-4ee2-44c8-be8b-d020419ecdab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747632539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1747632539
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1011427545
Short name T1026
Test name
Test status
Simulation time 2620404715 ps
CPU time 22.07 seconds
Started Jul 06 05:38:36 PM PDT 24
Finished Jul 06 05:38:58 PM PDT 24
Peak memory 227792 kb
Host smart-ec4a852f-98ab-494e-a30e-5aea0d7c48a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011427545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1011427545
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3622690058
Short name T334
Test name
Test status
Simulation time 14623087787 ps
CPU time 25.18 seconds
Started Jul 06 05:38:34 PM PDT 24
Finished Jul 06 05:39:00 PM PDT 24
Peak memory 205088 kb
Host smart-c77a9dd8-4c71-4e44-89af-ed80c27deb78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622690058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3622690058
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.4049931321
Short name T776
Test name
Test status
Simulation time 2277555781 ps
CPU time 3.61 seconds
Started Jul 06 05:38:34 PM PDT 24
Finished Jul 06 05:38:38 PM PDT 24
Peak memory 205060 kb
Host smart-4f275556-ae65-45c7-8b2c-314cf1e23c0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049931321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.4049931321
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.930388626
Short name T657
Test name
Test status
Simulation time 1071118022 ps
CPU time 6.62 seconds
Started Jul 06 05:38:33 PM PDT 24
Finished Jul 06 05:38:40 PM PDT 24
Peak memory 220624 kb
Host smart-55607fe7-18dd-469d-8b08-ccab5cb60ce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930388626 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.930388626
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.2024816260
Short name T693
Test name
Test status
Simulation time 101394658 ps
CPU time 1.82 seconds
Started Jul 06 05:38:40 PM PDT 24
Finished Jul 06 05:38:42 PM PDT 24
Peak memory 205016 kb
Host smart-70e26eb5-2c33-4651-9868-63d92988bb78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024816260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2024816260
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1152302803
Short name T1330
Test name
Test status
Simulation time 17953900 ps
CPU time 0.72 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:09 PM PDT 24
Peak memory 204636 kb
Host smart-9d4054f7-5f5d-4cc7-8ed1-067c0a1dcdf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152302803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1152302803
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3751700640
Short name T407
Test name
Test status
Simulation time 7360035546 ps
CPU time 7.45 seconds
Started Jul 06 05:44:05 PM PDT 24
Finished Jul 06 05:44:13 PM PDT 24
Peak memory 269168 kb
Host smart-830b5fcd-cbdb-43c0-bd6a-7b12fe24331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751700640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3751700640
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1924659468
Short name T1404
Test name
Test status
Simulation time 651488750 ps
CPU time 17.44 seconds
Started Jul 06 05:44:04 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 273720 kb
Host smart-a78492ba-ad3b-44e0-b46a-44ffc3fd0153
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924659468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1924659468
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1424315514
Short name T592
Test name
Test status
Simulation time 8734156705 ps
CPU time 167.76 seconds
Started Jul 06 05:44:06 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 793484 kb
Host smart-9223b7b8-921c-4c2e-a77f-eaab5bdefc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424315514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1424315514
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2300155519
Short name T1012
Test name
Test status
Simulation time 1693134928 ps
CPU time 44.22 seconds
Started Jul 06 05:44:03 PM PDT 24
Finished Jul 06 05:44:47 PM PDT 24
Peak memory 575056 kb
Host smart-a8d47246-b46d-4e27-9327-8cb118bc1d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300155519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2300155519
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1197036994
Short name T535
Test name
Test status
Simulation time 209042564 ps
CPU time 1.08 seconds
Started Jul 06 05:44:09 PM PDT 24
Finished Jul 06 05:44:10 PM PDT 24
Peak memory 204728 kb
Host smart-0563cf89-59f5-4bd9-bf99-2bda7e476970
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197036994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1197036994
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1051697152
Short name T847
Test name
Test status
Simulation time 147640857 ps
CPU time 3.04 seconds
Started Jul 06 05:44:06 PM PDT 24
Finished Jul 06 05:44:09 PM PDT 24
Peak memory 204932 kb
Host smart-13508d33-7bc3-4aaf-b4c2-7ff20acbc774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051697152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1051697152
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1613397837
Short name T144
Test name
Test status
Simulation time 14183392852 ps
CPU time 239.18 seconds
Started Jul 06 05:44:07 PM PDT 24
Finished Jul 06 05:48:06 PM PDT 24
Peak memory 1021048 kb
Host smart-8382e8e0-8414-434f-bd0f-a02b501b64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613397837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1613397837
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3406648649
Short name T1043
Test name
Test status
Simulation time 1847847502 ps
CPU time 82.52 seconds
Started Jul 06 05:44:11 PM PDT 24
Finished Jul 06 05:45:33 PM PDT 24
Peak memory 320780 kb
Host smart-8a86e7cf-5d1b-41a8-b183-9d78beaa654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406648649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3406648649
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1419117026
Short name T537
Test name
Test status
Simulation time 98820162 ps
CPU time 0.68 seconds
Started Jul 06 05:44:05 PM PDT 24
Finished Jul 06 05:44:06 PM PDT 24
Peak memory 204728 kb
Host smart-d0acb951-8800-4515-a0e8-b1f567c257f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419117026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1419117026
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1762207765
Short name T1480
Test name
Test status
Simulation time 377733783 ps
CPU time 5.04 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:14 PM PDT 24
Peak memory 222680 kb
Host smart-1898dafe-1039-485e-81f2-60e02d41095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762207765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1762207765
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.3506385983
Short name T520
Test name
Test status
Simulation time 2735666516 ps
CPU time 14.83 seconds
Started Jul 06 05:44:04 PM PDT 24
Finished Jul 06 05:44:19 PM PDT 24
Peak memory 347792 kb
Host smart-d3a40ac8-e3d5-4031-8b71-d54ec6525bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506385983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3506385983
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1546625054
Short name T1398
Test name
Test status
Simulation time 1184269262 ps
CPU time 16.98 seconds
Started Jul 06 05:44:05 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 278236 kb
Host smart-f5302013-7cbb-43a1-96d2-8d71367b8078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546625054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1546625054
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.331544212
Short name T1389
Test name
Test status
Simulation time 46288904771 ps
CPU time 1342.26 seconds
Started Jul 06 05:44:04 PM PDT 24
Finished Jul 06 06:06:27 PM PDT 24
Peak memory 2377220 kb
Host smart-78ed05d5-9d43-4128-a4fa-c652162b72b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331544212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.331544212
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3249224018
Short name T470
Test name
Test status
Simulation time 3941598144 ps
CPU time 33.41 seconds
Started Jul 06 05:44:04 PM PDT 24
Finished Jul 06 05:44:38 PM PDT 24
Peak memory 213268 kb
Host smart-b6086b06-72ec-4f37-b39f-10ac26971002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249224018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3249224018
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3939433704
Short name T863
Test name
Test status
Simulation time 4721318741 ps
CPU time 5.41 seconds
Started Jul 06 05:44:10 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 205120 kb
Host smart-d372834b-eb04-4c47-b7b3-c4acdf94413b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939433704 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3939433704
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2780157568
Short name T1195
Test name
Test status
Simulation time 866484367 ps
CPU time 1.22 seconds
Started Jul 06 05:44:09 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 213200 kb
Host smart-9b06874c-bbf3-4241-a284-870ef2753c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780157568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2780157568
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3064512581
Short name T827
Test name
Test status
Simulation time 245958820 ps
CPU time 1.45 seconds
Started Jul 06 05:44:07 PM PDT 24
Finished Jul 06 05:44:09 PM PDT 24
Peak memory 208008 kb
Host smart-4a07560b-f9d1-4bd4-8d26-b29c50e279c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064512581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3064512581
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.3454901
Short name T802
Test name
Test status
Simulation time 306043399 ps
CPU time 1.2 seconds
Started Jul 06 05:44:09 PM PDT 24
Finished Jul 06 05:44:11 PM PDT 24
Peak memory 204796 kb
Host smart-dac20b38-36e4-423c-bdad-b4fdda8677f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454901 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.3454901
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3700266630
Short name T838
Test name
Test status
Simulation time 332287761 ps
CPU time 1.25 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:09 PM PDT 24
Peak memory 204808 kb
Host smart-ac42d339-cbed-4155-a42e-34432514e5cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700266630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3700266630
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1706012647
Short name T311
Test name
Test status
Simulation time 391708733 ps
CPU time 2.77 seconds
Started Jul 06 05:44:11 PM PDT 24
Finished Jul 06 05:44:14 PM PDT 24
Peak memory 205084 kb
Host smart-3c554c98-a124-4521-baa6-53a2158e3cd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706012647 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1706012647
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.874822240
Short name T1324
Test name
Test status
Simulation time 4689231290 ps
CPU time 6.89 seconds
Started Jul 06 05:44:09 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 221324 kb
Host smart-754c9fa8-62c9-434d-a154-7e6e9057498e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874822240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.874822240
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1764204588
Short name T704
Test name
Test status
Simulation time 20885282390 ps
CPU time 42.47 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 1070472 kb
Host smart-91575de7-66aa-465a-8e22-e30b01038293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764204588 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1764204588
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.242780339
Short name T137
Test name
Test status
Simulation time 2679638355 ps
CPU time 21.31 seconds
Started Jul 06 05:44:04 PM PDT 24
Finished Jul 06 05:44:25 PM PDT 24
Peak memory 205092 kb
Host smart-e7749c92-ec7c-4da7-912c-3d95e4c3b182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242780339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.242780339
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3494363665
Short name T826
Test name
Test status
Simulation time 4459408998 ps
CPU time 34.55 seconds
Started Jul 06 05:44:10 PM PDT 24
Finished Jul 06 05:44:45 PM PDT 24
Peak memory 205092 kb
Host smart-94f1a8be-fe03-4ded-a18d-a6e4a4eb0912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494363665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3494363665
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3068187446
Short name T24
Test name
Test status
Simulation time 30202298584 ps
CPU time 29.45 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:38 PM PDT 24
Peak memory 656392 kb
Host smart-9dcdabae-6771-4a31-b220-aab2c2ba8f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068187446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3068187446
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2704207527
Short name T877
Test name
Test status
Simulation time 1762122971 ps
CPU time 13.15 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 354932 kb
Host smart-29f9d7ea-a0fa-47ce-9327-a0d329c2df3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704207527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2704207527
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3429239276
Short name T460
Test name
Test status
Simulation time 1174212060 ps
CPU time 6.43 seconds
Started Jul 06 05:44:08 PM PDT 24
Finished Jul 06 05:44:14 PM PDT 24
Peak memory 213344 kb
Host smart-3509ed22-d3ba-4d1d-ac95-0b99b4599834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429239276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3429239276
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.2319497454
Short name T548
Test name
Test status
Simulation time 80016983 ps
CPU time 1.85 seconds
Started Jul 06 05:44:11 PM PDT 24
Finished Jul 06 05:44:13 PM PDT 24
Peak memory 205056 kb
Host smart-d6ae6e4c-c50f-45fc-aa52-18105a156efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319497454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.2319497454
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.390814209
Short name T1510
Test name
Test status
Simulation time 18143415 ps
CPU time 0.62 seconds
Started Jul 06 05:44:18 PM PDT 24
Finished Jul 06 05:44:18 PM PDT 24
Peak memory 204880 kb
Host smart-fb44360e-956b-4730-82b6-fe03411a4aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390814209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.390814209
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3381455919
Short name T1023
Test name
Test status
Simulation time 180120638 ps
CPU time 5.91 seconds
Started Jul 06 05:44:20 PM PDT 24
Finished Jul 06 05:44:26 PM PDT 24
Peak memory 234812 kb
Host smart-72fbb561-5c08-4143-ad37-885622d10e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381455919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3381455919
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3058837017
Short name T606
Test name
Test status
Simulation time 406622495 ps
CPU time 9.11 seconds
Started Jul 06 05:44:14 PM PDT 24
Finished Jul 06 05:44:24 PM PDT 24
Peak memory 291200 kb
Host smart-c7b47a43-b815-438d-a5a8-de4ef78fdc97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058837017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3058837017
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.699866871
Short name T134
Test name
Test status
Simulation time 8436850779 ps
CPU time 122.64 seconds
Started Jul 06 05:44:16 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 526388 kb
Host smart-77053a77-c513-4a5b-88fc-bb21e7b9267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699866871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.699866871
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3180793405
Short name T725
Test name
Test status
Simulation time 29312107794 ps
CPU time 155.21 seconds
Started Jul 06 05:44:20 PM PDT 24
Finished Jul 06 05:46:55 PM PDT 24
Peak memory 718028 kb
Host smart-dd8d1f1c-5ad6-4639-86c8-0b81241bb019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180793405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3180793405
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1753959621
Short name T369
Test name
Test status
Simulation time 62745900 ps
CPU time 1.09 seconds
Started Jul 06 05:44:15 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 204708 kb
Host smart-be822e19-840c-4aa3-a104-def49b6a3eee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753959621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1753959621
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1778505694
Short name T998
Test name
Test status
Simulation time 1653878823 ps
CPU time 2.89 seconds
Started Jul 06 05:44:13 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 221208 kb
Host smart-6054c825-c0f4-48b8-9090-c508c7f84a21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778505694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1778505694
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4187550243
Short name T1070
Test name
Test status
Simulation time 14318104905 ps
CPU time 333.16 seconds
Started Jul 06 05:44:13 PM PDT 24
Finished Jul 06 05:49:47 PM PDT 24
Peak memory 1311572 kb
Host smart-d9a26f16-4d1d-4ad0-a29e-b472eefad0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187550243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4187550243
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.90405872
Short name T372
Test name
Test status
Simulation time 820953029 ps
CPU time 5.64 seconds
Started Jul 06 05:44:27 PM PDT 24
Finished Jul 06 05:44:33 PM PDT 24
Peak memory 204912 kb
Host smart-75dc51ed-87dd-4565-ad45-edcc7fe760b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90405872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.90405872
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1713017989
Short name T1331
Test name
Test status
Simulation time 1475603861 ps
CPU time 53.63 seconds
Started Jul 06 05:44:17 PM PDT 24
Finished Jul 06 05:45:11 PM PDT 24
Peak memory 332832 kb
Host smart-dae44e1f-5b1a-431a-871c-f0868d22bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713017989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1713017989
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1700039311
Short name T120
Test name
Test status
Simulation time 83714279 ps
CPU time 0.65 seconds
Started Jul 06 05:44:11 PM PDT 24
Finished Jul 06 05:44:12 PM PDT 24
Peak memory 204652 kb
Host smart-8a4f78e0-ccb0-49de-8469-92e72d0e4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700039311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1700039311
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3371120289
Short name T1234
Test name
Test status
Simulation time 7352931633 ps
CPU time 8.51 seconds
Started Jul 06 05:44:18 PM PDT 24
Finished Jul 06 05:44:26 PM PDT 24
Peak memory 213296 kb
Host smart-e0d5a76b-2cb5-438c-bcbf-0f2d7b6a1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371120289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3371120289
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.786656298
Short name T488
Test name
Test status
Simulation time 380139950 ps
CPU time 2.63 seconds
Started Jul 06 05:44:16 PM PDT 24
Finished Jul 06 05:44:19 PM PDT 24
Peak memory 222684 kb
Host smart-a35191ac-a0bb-42ff-b6aa-d51351cdc715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786656298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.786656298
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2457210591
Short name T422
Test name
Test status
Simulation time 1980635204 ps
CPU time 103.84 seconds
Started Jul 06 05:44:12 PM PDT 24
Finished Jul 06 05:45:56 PM PDT 24
Peak memory 428040 kb
Host smart-5a27b509-3657-41bb-a07a-fc4b4d8d930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457210591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2457210591
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3838747485
Short name T52
Test name
Test status
Simulation time 15383314550 ps
CPU time 1975.67 seconds
Started Jul 06 05:44:17 PM PDT 24
Finished Jul 06 06:17:14 PM PDT 24
Peak memory 3004136 kb
Host smart-6bd238f3-68e7-47d9-90a3-f8658f5f4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838747485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3838747485
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.664711078
Short name T1409
Test name
Test status
Simulation time 1730945604 ps
CPU time 14.53 seconds
Started Jul 06 05:44:15 PM PDT 24
Finished Jul 06 05:44:29 PM PDT 24
Peak memory 213300 kb
Host smart-d1c7f2eb-9d59-4ebe-8f30-c72c1a60b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664711078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.664711078
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.991094571
Short name T1453
Test name
Test status
Simulation time 987169532 ps
CPU time 2.7 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:44:33 PM PDT 24
Peak memory 204988 kb
Host smart-6501c559-1f8b-4557-9697-966de822ca81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991094571 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.991094571
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3254915862
Short name T1041
Test name
Test status
Simulation time 278640074 ps
CPU time 1.52 seconds
Started Jul 06 05:44:15 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 213200 kb
Host smart-27de6d09-f10b-45a0-8daa-d86b9a1f3a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254915862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3254915862
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3088279066
Short name T1092
Test name
Test status
Simulation time 312745415 ps
CPU time 1.31 seconds
Started Jul 06 05:44:20 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 206156 kb
Host smart-719a7420-d0cd-46a3-b52f-cded31dc6b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088279066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3088279066
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2064059632
Short name T1501
Test name
Test status
Simulation time 1212695114 ps
CPU time 1.27 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:44:20 PM PDT 24
Peak memory 204708 kb
Host smart-3454faea-0eba-4f65-927e-8864d67b7dad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064059632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2064059632
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.4077743496
Short name T1095
Test name
Test status
Simulation time 469938087 ps
CPU time 1.16 seconds
Started Jul 06 05:44:31 PM PDT 24
Finished Jul 06 05:44:33 PM PDT 24
Peak memory 204696 kb
Host smart-265bb5fc-91f3-42c7-84ab-9cf30acb659b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077743496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.4077743496
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3282949110
Short name T1298
Test name
Test status
Simulation time 754079384 ps
CPU time 4.99 seconds
Started Jul 06 05:44:16 PM PDT 24
Finished Jul 06 05:44:21 PM PDT 24
Peak memory 217844 kb
Host smart-0444eda3-c85d-48db-98bb-bd2c46bb345f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282949110 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3282949110
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1081516689
Short name T378
Test name
Test status
Simulation time 2857774787 ps
CPU time 5.66 seconds
Started Jul 06 05:44:16 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 205112 kb
Host smart-7018b25f-af49-4fed-8736-838b722beae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081516689 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1081516689
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.158658612
Short name T814
Test name
Test status
Simulation time 712685337 ps
CPU time 11.01 seconds
Started Jul 06 05:44:18 PM PDT 24
Finished Jul 06 05:44:29 PM PDT 24
Peak memory 205064 kb
Host smart-1c5ebd76-50e5-447f-9340-2989e2917b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158658612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.158658612
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1974259407
Short name T600
Test name
Test status
Simulation time 694278118 ps
CPU time 26.96 seconds
Started Jul 06 05:44:18 PM PDT 24
Finished Jul 06 05:44:45 PM PDT 24
Peak memory 205004 kb
Host smart-96ec3c33-3038-41bb-a8ab-417716660fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974259407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1974259407
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.4207565041
Short name T1444
Test name
Test status
Simulation time 40284943689 ps
CPU time 72.11 seconds
Started Jul 06 05:44:14 PM PDT 24
Finished Jul 06 05:45:26 PM PDT 24
Peak memory 1232652 kb
Host smart-38af9832-073e-4aad-b4da-86b9eac0cfb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207565041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.4207565041
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1526449569
Short name T1200
Test name
Test status
Simulation time 188169066 ps
CPU time 1.4 seconds
Started Jul 06 05:44:20 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 205052 kb
Host smart-1f0d1de8-673a-4922-9403-a59ef0414fad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526449569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1526449569
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.312713772
Short name T763
Test name
Test status
Simulation time 10292335279 ps
CPU time 7.37 seconds
Started Jul 06 05:44:14 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 213728 kb
Host smart-24610682-e2fd-445f-abba-938aad13614f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312713772 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.312713772
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.2069395186
Short name T1143
Test name
Test status
Simulation time 265586554 ps
CPU time 3.59 seconds
Started Jul 06 05:44:17 PM PDT 24
Finished Jul 06 05:44:21 PM PDT 24
Peak memory 204988 kb
Host smart-8ee4342e-5f71-451e-8d7a-f9941917590a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069395186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2069395186
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.440472493
Short name T418
Test name
Test status
Simulation time 38881776 ps
CPU time 0.64 seconds
Started Jul 06 05:44:31 PM PDT 24
Finished Jul 06 05:44:32 PM PDT 24
Peak memory 204652 kb
Host smart-71dcbd93-093b-48fd-876c-c2ccf6f9cb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440472493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.440472493
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3298995697
Short name T804
Test name
Test status
Simulation time 87782566 ps
CPU time 1.64 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:44:32 PM PDT 24
Peak memory 213200 kb
Host smart-915a538e-e388-4e30-a8b1-e0e6e2ea8f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298995697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3298995697
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2128634362
Short name T1056
Test name
Test status
Simulation time 194569907 ps
CPU time 3.52 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:44:23 PM PDT 24
Peak memory 239572 kb
Host smart-832264ec-5439-4808-b24a-b8127ca7af91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128634362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2128634362
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2228978681
Short name T961
Test name
Test status
Simulation time 1611565118 ps
CPU time 104.29 seconds
Started Jul 06 05:44:20 PM PDT 24
Finished Jul 06 05:46:04 PM PDT 24
Peak memory 544096 kb
Host smart-2b576084-aee0-489e-b6fd-67bd7b2b94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228978681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2228978681
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2571266676
Short name T335
Test name
Test status
Simulation time 3084749207 ps
CPU time 99.21 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:45:58 PM PDT 24
Peak memory 510936 kb
Host smart-a8d78dc4-2c68-453e-a2bd-3e15395add18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571266676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2571266676
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1289754742
Short name T1401
Test name
Test status
Simulation time 578801549 ps
CPU time 1.17 seconds
Started Jul 06 05:44:17 PM PDT 24
Finished Jul 06 05:44:19 PM PDT 24
Peak memory 205048 kb
Host smart-9c795f43-dc9f-4e24-bd7d-8759ded720af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289754742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1289754742
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1835977369
Short name T632
Test name
Test status
Simulation time 141254068 ps
CPU time 3.98 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:44:23 PM PDT 24
Peak memory 228540 kb
Host smart-bccb2625-58d8-44ff-963b-7b3289570b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835977369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1835977369
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.35872362
Short name T1057
Test name
Test status
Simulation time 5565135916 ps
CPU time 126.6 seconds
Started Jul 06 05:44:21 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 1387664 kb
Host smart-15cc79f5-6c8e-43bb-b4d4-ba0938e4f26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35872362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.35872362
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2907929200
Short name T61
Test name
Test status
Simulation time 3405121815 ps
CPU time 7.24 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:30 PM PDT 24
Peak memory 205076 kb
Host smart-09af50a9-c330-4cac-a7c3-a264642c4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907929200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2907929200
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2042014685
Short name T928
Test name
Test status
Simulation time 2097497560 ps
CPU time 35.45 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:45:06 PM PDT 24
Peak memory 365432 kb
Host smart-06013675-e5fe-45dc-b73d-a7166b2e348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042014685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2042014685
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1463254465
Short name T123
Test name
Test status
Simulation time 21964014 ps
CPU time 0.73 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:44:20 PM PDT 24
Peak memory 204768 kb
Host smart-2f657b6f-44a0-404c-8a5e-3870887e5e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463254465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1463254465
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3229976242
Short name T1506
Test name
Test status
Simulation time 52160458373 ps
CPU time 1439.67 seconds
Started Jul 06 05:44:18 PM PDT 24
Finished Jul 06 06:08:18 PM PDT 24
Peak memory 2764332 kb
Host smart-bddd5962-3424-411f-9128-2e2223c35f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229976242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3229976242
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.3895427429
Short name T309
Test name
Test status
Simulation time 247048081 ps
CPU time 3.35 seconds
Started Jul 06 05:44:25 PM PDT 24
Finished Jul 06 05:44:28 PM PDT 24
Peak memory 225180 kb
Host smart-722eabc0-5c62-40cb-ab74-006b93ade774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895427429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3895427429
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1112296566
Short name T1374
Test name
Test status
Simulation time 2177550808 ps
CPU time 34.24 seconds
Started Jul 06 05:44:19 PM PDT 24
Finished Jul 06 05:44:53 PM PDT 24
Peak memory 365100 kb
Host smart-2f714be5-7bb6-4b16-b959-965c4898d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112296566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1112296566
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1453908093
Short name T53
Test name
Test status
Simulation time 7825856562 ps
CPU time 627.36 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:54:57 PM PDT 24
Peak memory 1481216 kb
Host smart-f052fb1c-5cd4-4783-bca6-1e479c4757e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453908093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1453908093
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2723547592
Short name T279
Test name
Test status
Simulation time 1861278722 ps
CPU time 11.68 seconds
Started Jul 06 05:44:24 PM PDT 24
Finished Jul 06 05:44:36 PM PDT 24
Peak memory 217392 kb
Host smart-a236a367-3e1a-489c-8380-7f106a0f34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723547592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2723547592
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.94870309
Short name T414
Test name
Test status
Simulation time 856438223 ps
CPU time 2.46 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:26 PM PDT 24
Peak memory 204960 kb
Host smart-d3adc2b9-2897-4a7e-9ee7-2d0c35c6c58c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94870309 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_bad_addr.94870309
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2897019757
Short name T1205
Test name
Test status
Simulation time 157450329 ps
CPU time 0.75 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:44:31 PM PDT 24
Peak memory 204696 kb
Host smart-0b95296d-4e63-4747-8c1e-8910ff8f4475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897019757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2897019757
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3191486343
Short name T710
Test name
Test status
Simulation time 232132767 ps
CPU time 1.39 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:25 PM PDT 24
Peak memory 205016 kb
Host smart-012b0765-2269-409c-8978-025fc571f6c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191486343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3191486343
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.797842319
Short name T256
Test name
Test status
Simulation time 5367022492 ps
CPU time 2.52 seconds
Started Jul 06 05:44:31 PM PDT 24
Finished Jul 06 05:44:34 PM PDT 24
Peak memory 204968 kb
Host smart-b2900144-1dd8-4418-ad8a-f851c8f48a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797842319 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.797842319
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.4098625098
Short name T319
Test name
Test status
Simulation time 502479818 ps
CPU time 1.11 seconds
Started Jul 06 05:44:31 PM PDT 24
Finished Jul 06 05:44:32 PM PDT 24
Peak memory 204828 kb
Host smart-548ec6aa-382a-4533-81fa-e57a9a510d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098625098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.4098625098
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3607396357
Short name T1207
Test name
Test status
Simulation time 9094904542 ps
CPU time 14.13 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:38 PM PDT 24
Peak memory 327664 kb
Host smart-07a4a5f8-7590-4483-ae71-f21eabc95dad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607396357 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3607396357
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1352953682
Short name T572
Test name
Test status
Simulation time 903382993 ps
CPU time 17.21 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:41 PM PDT 24
Peak memory 204996 kb
Host smart-a777c444-b1e4-4d94-a9c7-1cd802d9d8c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352953682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1352953682
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3864654697
Short name T302
Test name
Test status
Simulation time 3570924264 ps
CPU time 11.04 seconds
Started Jul 06 05:44:24 PM PDT 24
Finished Jul 06 05:44:35 PM PDT 24
Peak memory 209704 kb
Host smart-c0120e7d-0d9d-4e18-9887-72186785eff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864654697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3864654697
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.459224967
Short name T1485
Test name
Test status
Simulation time 52034432987 ps
CPU time 150.32 seconds
Started Jul 06 05:44:24 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 2061016 kb
Host smart-d12bf388-dc53-438a-bddf-e5b12112b7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459224967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.459224967
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1263777772
Short name T1288
Test name
Test status
Simulation time 1848737564 ps
CPU time 4.48 seconds
Started Jul 06 05:44:23 PM PDT 24
Finished Jul 06 05:44:28 PM PDT 24
Peak memory 239364 kb
Host smart-2348d834-8b75-4a74-ad0f-7a372fddc1e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263777772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1263777772
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1023319368
Short name T714
Test name
Test status
Simulation time 2421635928 ps
CPU time 6.62 seconds
Started Jul 06 05:44:24 PM PDT 24
Finished Jul 06 05:44:31 PM PDT 24
Peak memory 205152 kb
Host smart-679b1536-0c46-41e7-963d-99646df689b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023319368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1023319368
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.1340156919
Short name T656
Test name
Test status
Simulation time 551035319 ps
CPU time 6.88 seconds
Started Jul 06 05:44:29 PM PDT 24
Finished Jul 06 05:44:36 PM PDT 24
Peak memory 204964 kb
Host smart-c23a6c8a-63c6-4c62-a383-058312752fc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340156919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1340156919
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1710202453
Short name T375
Test name
Test status
Simulation time 17571736 ps
CPU time 0.65 seconds
Started Jul 06 05:44:47 PM PDT 24
Finished Jul 06 05:44:48 PM PDT 24
Peak memory 204612 kb
Host smart-05c8f663-20f6-482e-b733-612a2cb274ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710202453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1710202453
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2880894452
Short name T628
Test name
Test status
Simulation time 5263714565 ps
CPU time 15.48 seconds
Started Jul 06 05:44:38 PM PDT 24
Finished Jul 06 05:44:54 PM PDT 24
Peak memory 272956 kb
Host smart-fd2476b7-5987-4497-aeb7-f3167a8b1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880894452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2880894452
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.325249369
Short name T1344
Test name
Test status
Simulation time 4106570194 ps
CPU time 17.07 seconds
Started Jul 06 05:44:34 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 274852 kb
Host smart-11356953-df92-4daa-abbb-d05919f973a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325249369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.325249369
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.361870191
Short name T1166
Test name
Test status
Simulation time 1727489759 ps
CPU time 114.07 seconds
Started Jul 06 05:44:34 PM PDT 24
Finished Jul 06 05:46:28 PM PDT 24
Peak memory 624388 kb
Host smart-e55ce98a-bfcf-4c0f-8430-44fa823cca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361870191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.361870191
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2519234283
Short name T1093
Test name
Test status
Simulation time 1826666415 ps
CPU time 48.02 seconds
Started Jul 06 05:44:31 PM PDT 24
Finished Jul 06 05:45:19 PM PDT 24
Peak memory 614168 kb
Host smart-0eb9ba96-5a7b-4649-9a1c-5f6e0dcabf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519234283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2519234283
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.890126790
Short name T516
Test name
Test status
Simulation time 393498072 ps
CPU time 1.19 seconds
Started Jul 06 05:44:29 PM PDT 24
Finished Jul 06 05:44:30 PM PDT 24
Peak memory 204756 kb
Host smart-23d5f03c-6561-4fdb-a086-8a51a6e03081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890126790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.890126790
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3926541833
Short name T1435
Test name
Test status
Simulation time 591601008 ps
CPU time 3.31 seconds
Started Jul 06 05:44:34 PM PDT 24
Finished Jul 06 05:44:37 PM PDT 24
Peak memory 205040 kb
Host smart-59496386-1fd5-4c35-8bfd-b2027ef98cba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926541833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3926541833
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.551095597
Short name T96
Test name
Test status
Simulation time 13437810774 ps
CPU time 70.87 seconds
Started Jul 06 05:44:30 PM PDT 24
Finished Jul 06 05:45:41 PM PDT 24
Peak memory 941244 kb
Host smart-1e9732ce-735b-4360-9f8b-959fc1f3485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551095597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.551095597
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1020367035
Short name T1433
Test name
Test status
Simulation time 848042523 ps
CPU time 2.92 seconds
Started Jul 06 05:44:45 PM PDT 24
Finished Jul 06 05:44:48 PM PDT 24
Peak memory 205016 kb
Host smart-9410aa72-706d-4f27-9795-87c820af6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020367035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1020367035
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.551089693
Short name T505
Test name
Test status
Simulation time 28788292511 ps
CPU time 100.46 seconds
Started Jul 06 05:44:44 PM PDT 24
Finished Jul 06 05:46:25 PM PDT 24
Peak memory 399068 kb
Host smart-46629ef2-7275-49d9-85f7-34c752f9539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551089693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.551089693
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2756688034
Short name T1232
Test name
Test status
Simulation time 24706638 ps
CPU time 0.66 seconds
Started Jul 06 05:44:29 PM PDT 24
Finished Jul 06 05:44:30 PM PDT 24
Peak memory 204712 kb
Host smart-a8fa55eb-316a-42c4-b372-63bc65a1c55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756688034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2756688034
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.153976292
Short name T1170
Test name
Test status
Simulation time 97768025122 ps
CPU time 900.48 seconds
Started Jul 06 05:44:34 PM PDT 24
Finished Jul 06 05:59:34 PM PDT 24
Peak memory 1940472 kb
Host smart-6aa41668-222c-45f3-8ac4-30950285c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153976292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.153976292
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.1304107259
Short name T732
Test name
Test status
Simulation time 330330880 ps
CPU time 5.39 seconds
Started Jul 06 05:44:32 PM PDT 24
Finished Jul 06 05:44:38 PM PDT 24
Peak memory 228700 kb
Host smart-0b99ad27-a7b3-45b9-8ae9-f822a28481ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304107259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1304107259
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2930481764
Short name T164
Test name
Test status
Simulation time 1908688709 ps
CPU time 28.98 seconds
Started Jul 06 05:44:29 PM PDT 24
Finished Jul 06 05:44:58 PM PDT 24
Peak memory 281584 kb
Host smart-612a03cc-9ce2-4bcb-bc64-75fbee8c2f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930481764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2930481764
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.533954587
Short name T991
Test name
Test status
Simulation time 80791154982 ps
CPU time 3110 seconds
Started Jul 06 05:44:38 PM PDT 24
Finished Jul 06 06:36:29 PM PDT 24
Peak memory 4198804 kb
Host smart-a821c71a-13ae-45cb-b4a9-76c1a8c24c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533954587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.533954587
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1562405561
Short name T635
Test name
Test status
Simulation time 2414996984 ps
CPU time 10.61 seconds
Started Jul 06 05:44:33 PM PDT 24
Finished Jul 06 05:44:44 PM PDT 24
Peak memory 213236 kb
Host smart-0b04b9de-e9a9-464b-b5dc-0e38810431b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562405561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1562405561
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3436035406
Short name T25
Test name
Test status
Simulation time 5521617900 ps
CPU time 3.8 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:44:50 PM PDT 24
Peak memory 205056 kb
Host smart-0a076907-ca40-418f-ad6a-405da9565005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436035406 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3436035406
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3739175261
Short name T665
Test name
Test status
Simulation time 206099343 ps
CPU time 1.31 seconds
Started Jul 06 05:44:44 PM PDT 24
Finished Jul 06 05:44:45 PM PDT 24
Peak memory 205000 kb
Host smart-3cba4677-014f-4714-b03f-2cb48c65c246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739175261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3739175261
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2489837335
Short name T1128
Test name
Test status
Simulation time 209539815 ps
CPU time 1.18 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:44:47 PM PDT 24
Peak memory 204820 kb
Host smart-996bcb0c-761a-4803-b815-b587035697ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489837335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2489837335
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3770768274
Short name T640
Test name
Test status
Simulation time 861510047 ps
CPU time 2.06 seconds
Started Jul 06 05:44:47 PM PDT 24
Finished Jul 06 05:44:49 PM PDT 24
Peak memory 205064 kb
Host smart-508fc681-9118-4c2a-84d2-de9bba7622b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770768274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3770768274
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2263667826
Short name T1472
Test name
Test status
Simulation time 546670113 ps
CPU time 1.32 seconds
Started Jul 06 05:44:44 PM PDT 24
Finished Jul 06 05:44:46 PM PDT 24
Peak memory 204832 kb
Host smart-abb217bf-c4f4-474e-8857-af8c94a8376a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263667826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2263667826
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.402028542
Short name T1475
Test name
Test status
Simulation time 2727809338 ps
CPU time 4.02 seconds
Started Jul 06 05:44:42 PM PDT 24
Finished Jul 06 05:44:46 PM PDT 24
Peak memory 205560 kb
Host smart-a67d3726-fbb4-40d2-bc5a-94561ea2fdd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402028542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.402028542
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3917553670
Short name T426
Test name
Test status
Simulation time 6792036230 ps
CPU time 8.46 seconds
Started Jul 06 05:44:39 PM PDT 24
Finished Jul 06 05:44:48 PM PDT 24
Peak memory 205060 kb
Host smart-c3cfb7ae-b639-4aa1-80c2-d74120133715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917553670 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3917553670
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.4049141117
Short name T149
Test name
Test status
Simulation time 2973532101 ps
CPU time 12.03 seconds
Started Jul 06 05:44:40 PM PDT 24
Finished Jul 06 05:44:52 PM PDT 24
Peak memory 205028 kb
Host smart-0328f7cb-e02c-4973-a753-dac20bfadafa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049141117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.4049141117
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1523133300
Short name T467
Test name
Test status
Simulation time 686621166 ps
CPU time 11.84 seconds
Started Jul 06 05:44:40 PM PDT 24
Finished Jul 06 05:44:52 PM PDT 24
Peak memory 208920 kb
Host smart-f1a6f0ed-3c59-46f1-b4c1-bd5114dd93bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523133300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1523133300
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2785729663
Short name T902
Test name
Test status
Simulation time 68423594920 ps
CPU time 847.74 seconds
Started Jul 06 05:44:41 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 6094232 kb
Host smart-e1aab414-b042-4feb-825d-193b11293289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785729663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2785729663
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.996191100
Short name T401
Test name
Test status
Simulation time 2236837080 ps
CPU time 91.23 seconds
Started Jul 06 05:44:40 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 629916 kb
Host smart-201364a6-48b0-4ff5-8572-98be5e67fec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996191100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.996191100
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2102458751
Short name T967
Test name
Test status
Simulation time 2271840239 ps
CPU time 7.56 seconds
Started Jul 06 05:44:40 PM PDT 24
Finished Jul 06 05:44:48 PM PDT 24
Peak memory 213316 kb
Host smart-0483dec8-ffa0-4992-b504-5af3d005a514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102458751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2102458751
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.2571135008
Short name T747
Test name
Test status
Simulation time 141501247 ps
CPU time 2.87 seconds
Started Jul 06 05:44:44 PM PDT 24
Finished Jul 06 05:44:47 PM PDT 24
Peak memory 205012 kb
Host smart-064fc4bb-0e23-47cc-8232-01dd38200b4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571135008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2571135008
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1764116113
Short name T766
Test name
Test status
Simulation time 26233184 ps
CPU time 0.6 seconds
Started Jul 06 05:44:56 PM PDT 24
Finished Jul 06 05:44:57 PM PDT 24
Peak memory 204624 kb
Host smart-05d81c60-ef3e-4c69-8796-a25b9204c0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764116113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1764116113
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2426473522
Short name T721
Test name
Test status
Simulation time 163283285 ps
CPU time 3.81 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:44:53 PM PDT 24
Peak memory 217328 kb
Host smart-6066e672-d536-4a98-a220-01327888e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426473522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2426473522
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.963152467
Short name T394
Test name
Test status
Simulation time 920192322 ps
CPU time 9.17 seconds
Started Jul 06 05:44:44 PM PDT 24
Finished Jul 06 05:44:54 PM PDT 24
Peak memory 281832 kb
Host smart-c89e7d68-643a-431f-a103-1e9c984e0c40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963152467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.963152467
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.818092809
Short name T883
Test name
Test status
Simulation time 9860543907 ps
CPU time 153.51 seconds
Started Jul 06 05:44:45 PM PDT 24
Finished Jul 06 05:47:19 PM PDT 24
Peak memory 724180 kb
Host smart-01b908db-3323-4583-a0b4-f80910ef5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818092809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.818092809
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1184021295
Short name T1365
Test name
Test status
Simulation time 3077016042 ps
CPU time 90.85 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:46:17 PM PDT 24
Peak memory 903620 kb
Host smart-8ac32fd0-f589-4386-8c6d-5ff464476788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184021295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1184021295
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3713958348
Short name T214
Test name
Test status
Simulation time 343612430 ps
CPU time 1.2 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:44:48 PM PDT 24
Peak memory 204772 kb
Host smart-294d3d67-1c12-4033-b3ab-5920d83a9ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713958348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3713958348
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2299052041
Short name T1392
Test name
Test status
Simulation time 169315536 ps
CPU time 10.02 seconds
Started Jul 06 05:44:45 PM PDT 24
Finished Jul 06 05:44:55 PM PDT 24
Peak memory 236812 kb
Host smart-94d86f31-2437-4fed-9384-da9dab79b537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299052041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2299052041
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2586972434
Short name T97
Test name
Test status
Simulation time 13504945008 ps
CPU time 81.56 seconds
Started Jul 06 05:44:45 PM PDT 24
Finished Jul 06 05:46:06 PM PDT 24
Peak memory 1049004 kb
Host smart-c1c6cc06-c407-4972-bd14-46c059534aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586972434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2586972434
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2483175969
Short name T819
Test name
Test status
Simulation time 2069496959 ps
CPU time 6.05 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:45:01 PM PDT 24
Peak memory 205024 kb
Host smart-10e8197e-f48e-4318-8472-e418b6af816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483175969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2483175969
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4193873914
Short name T220
Test name
Test status
Simulation time 2790336061 ps
CPU time 62.69 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:45:58 PM PDT 24
Peak memory 262828 kb
Host smart-b16f17a5-1cde-45af-852a-b78ee2463e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193873914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4193873914
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1306241188
Short name T269
Test name
Test status
Simulation time 57463655 ps
CPU time 0.67 seconds
Started Jul 06 05:44:45 PM PDT 24
Finished Jul 06 05:44:46 PM PDT 24
Peak memory 204756 kb
Host smart-6b41a1a9-074e-4a0b-9a4a-9b5d9874b4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306241188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1306241188
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.462016624
Short name T875
Test name
Test status
Simulation time 6378365136 ps
CPU time 95.66 seconds
Started Jul 06 05:44:48 PM PDT 24
Finished Jul 06 05:46:24 PM PDT 24
Peak memory 285892 kb
Host smart-324002e8-ac04-4ba7-8e33-3eb414afb44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462016624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.462016624
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.547976244
Short name T314
Test name
Test status
Simulation time 1168930379 ps
CPU time 4.45 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:44:50 PM PDT 24
Peak memory 224916 kb
Host smart-1746d543-5184-4ba1-ac0c-0e9014c669bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547976244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.547976244
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.440812297
Short name T540
Test name
Test status
Simulation time 1356747013 ps
CPU time 62.59 seconds
Started Jul 06 05:44:46 PM PDT 24
Finished Jul 06 05:45:49 PM PDT 24
Peak memory 332168 kb
Host smart-c3d17e8e-46c4-4d70-9368-5b6c25b76e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440812297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.440812297
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1190169875
Short name T842
Test name
Test status
Simulation time 694839017 ps
CPU time 11.03 seconds
Started Jul 06 05:44:50 PM PDT 24
Finished Jul 06 05:45:01 PM PDT 24
Peak memory 220852 kb
Host smart-7cd17b57-93b9-4417-b323-2a715d3b3d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190169875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1190169875
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4254842194
Short name T790
Test name
Test status
Simulation time 6205988443 ps
CPU time 4.53 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:45:00 PM PDT 24
Peak memory 205080 kb
Host smart-564e264a-52a8-4a11-8c6d-88386f330742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254842194 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4254842194
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.584944048
Short name T141
Test name
Test status
Simulation time 761732691 ps
CPU time 1.36 seconds
Started Jul 06 05:44:50 PM PDT 24
Finished Jul 06 05:44:52 PM PDT 24
Peak memory 205048 kb
Host smart-7c3725d1-becb-4554-8fe6-c6c91892bbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584944048 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.584944048
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3501378111
Short name T1352
Test name
Test status
Simulation time 203937440 ps
CPU time 1.36 seconds
Started Jul 06 05:44:56 PM PDT 24
Finished Jul 06 05:44:57 PM PDT 24
Peak memory 204792 kb
Host smart-3fda6522-0ded-48ce-908e-b523c26e043f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501378111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3501378111
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1012369676
Short name T415
Test name
Test status
Simulation time 174059413 ps
CPU time 1.36 seconds
Started Jul 06 05:44:56 PM PDT 24
Finished Jul 06 05:44:58 PM PDT 24
Peak memory 204824 kb
Host smart-2868f523-08ce-4a47-bcef-2af99ecb88ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012369676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1012369676
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1602479780
Short name T1277
Test name
Test status
Simulation time 824418713 ps
CPU time 5.01 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:44:55 PM PDT 24
Peak memory 213692 kb
Host smart-8cd23972-c7de-4577-992f-223f149b2e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602479780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1602479780
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.4272405550
Short name T23
Test name
Test status
Simulation time 18668953003 ps
CPU time 116.63 seconds
Started Jul 06 05:44:51 PM PDT 24
Finished Jul 06 05:46:47 PM PDT 24
Peak memory 1571416 kb
Host smart-18115e29-fbec-4423-bfda-252576ff5763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272405550 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.4272405550
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1496340234
Short name T1001
Test name
Test status
Simulation time 726319228 ps
CPU time 24.24 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:45:14 PM PDT 24
Peak memory 205056 kb
Host smart-ec8c6273-7933-49cc-8d8b-a2c15f6a3501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496340234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1496340234
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2687409396
Short name T442
Test name
Test status
Simulation time 1550095836 ps
CPU time 26.45 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:45:16 PM PDT 24
Peak memory 224256 kb
Host smart-dab6b6c0-e30b-4e27-ac0b-e5a6cee8e7b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687409396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2687409396
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.375459160
Short name T566
Test name
Test status
Simulation time 37373078165 ps
CPU time 30.56 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:45:20 PM PDT 24
Peak memory 709420 kb
Host smart-32ed18a0-16d1-4f36-8bda-d61ced788b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375459160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.375459160
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3681623890
Short name T400
Test name
Test status
Simulation time 491114675 ps
CPU time 1.92 seconds
Started Jul 06 05:44:49 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 207608 kb
Host smart-d87f3873-ffda-4b50-bee7-d1c08d2cc8ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681623890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3681623890
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1196790525
Short name T652
Test name
Test status
Simulation time 1582515822 ps
CPU time 7.68 seconds
Started Jul 06 05:44:50 PM PDT 24
Finished Jul 06 05:44:58 PM PDT 24
Peak memory 213252 kb
Host smart-ad6754f0-4d87-462c-b7ce-0a23e46ab821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196790525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1196790525
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.983125432
Short name T1452
Test name
Test status
Simulation time 234779490 ps
CPU time 3.08 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:44:58 PM PDT 24
Peak memory 205020 kb
Host smart-77992f57-b300-4cf5-86d8-6493161beda9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983125432 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.983125432
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2838456027
Short name T1406
Test name
Test status
Simulation time 27313731 ps
CPU time 0.64 seconds
Started Jul 06 05:45:07 PM PDT 24
Finished Jul 06 05:45:08 PM PDT 24
Peak memory 204588 kb
Host smart-1eccb5c0-19fc-4ec4-8e5f-f521171e19e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838456027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2838456027
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4281823044
Short name T344
Test name
Test status
Simulation time 101033614 ps
CPU time 1.68 seconds
Started Jul 06 05:44:58 PM PDT 24
Finished Jul 06 05:45:00 PM PDT 24
Peak memory 213320 kb
Host smart-4468b873-a81e-4517-acb4-ba526eeb6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281823044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4281823044
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1351168844
Short name T1230
Test name
Test status
Simulation time 1171178412 ps
CPU time 15.63 seconds
Started Jul 06 05:44:56 PM PDT 24
Finished Jul 06 05:45:12 PM PDT 24
Peak memory 266784 kb
Host smart-b4c9b76a-57ab-4095-8de9-0cf7407dfd6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351168844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1351168844
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.402670489
Short name T136
Test name
Test status
Simulation time 12964122249 ps
CPU time 82.18 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:46:17 PM PDT 24
Peak memory 505336 kb
Host smart-0122b9da-8700-4d29-baa4-b307a7aa353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402670489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.402670489
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1157443029
Short name T1097
Test name
Test status
Simulation time 1514332859 ps
CPU time 99.82 seconds
Started Jul 06 05:44:57 PM PDT 24
Finished Jul 06 05:46:37 PM PDT 24
Peak memory 569552 kb
Host smart-be88af1e-0b41-43c9-84f5-a243a6214c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157443029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1157443029
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3856822945
Short name T215
Test name
Test status
Simulation time 107411932 ps
CPU time 1.05 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:44:56 PM PDT 24
Peak memory 204756 kb
Host smart-f8c65857-8810-4419-a9bd-a44921d96255
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856822945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3856822945
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1823328238
Short name T636
Test name
Test status
Simulation time 575565260 ps
CPU time 8.87 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:45:04 PM PDT 24
Peak memory 229608 kb
Host smart-18652abd-f54d-4ef8-a993-7f8d29e1a4c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823328238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1823328238
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.431866539
Short name T958
Test name
Test status
Simulation time 19647189998 ps
CPU time 72.62 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:46:08 PM PDT 24
Peak memory 871952 kb
Host smart-89ebca4c-5922-4f6a-937e-84ce1bd43773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431866539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.431866539
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.556491867
Short name T730
Test name
Test status
Simulation time 407708392 ps
CPU time 5.25 seconds
Started Jul 06 05:45:01 PM PDT 24
Finished Jul 06 05:45:07 PM PDT 24
Peak memory 205072 kb
Host smart-8db31984-7ecd-4962-9da8-f2ff48e3b4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556491867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.556491867
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.830056326
Short name T37
Test name
Test status
Simulation time 23104467703 ps
CPU time 33.71 seconds
Started Jul 06 05:45:01 PM PDT 24
Finished Jul 06 05:45:35 PM PDT 24
Peak memory 447212 kb
Host smart-9208ca55-641d-4c31-b075-1ca6adcfb620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830056326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.830056326
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1835053219
Short name T125
Test name
Test status
Simulation time 83733362 ps
CPU time 0.68 seconds
Started Jul 06 05:44:54 PM PDT 24
Finished Jul 06 05:44:55 PM PDT 24
Peak memory 204752 kb
Host smart-0e8542e4-00a2-4dc5-8a2d-e43d0eabb476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835053219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1835053219
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1328285831
Short name T451
Test name
Test status
Simulation time 72770853503 ps
CPU time 691.37 seconds
Started Jul 06 05:44:55 PM PDT 24
Finished Jul 06 05:56:26 PM PDT 24
Peak memory 213340 kb
Host smart-39db4c21-0075-487f-aa67-5df9d64e80a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328285831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1328285831
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.12390137
Short name T1113
Test name
Test status
Simulation time 6187801055 ps
CPU time 32.08 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:33 PM PDT 24
Peak memory 205028 kb
Host smart-4f30fb63-5edf-40f8-8732-dca392f79a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12390137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.12390137
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1338114432
Short name T1265
Test name
Test status
Simulation time 6542376905 ps
CPU time 25.46 seconds
Started Jul 06 05:44:54 PM PDT 24
Finished Jul 06 05:45:19 PM PDT 24
Peak memory 354752 kb
Host smart-84a29e7f-c125-494b-899a-96ecbbd5f6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338114432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1338114432
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.500355324
Short name T105
Test name
Test status
Simulation time 1519596316 ps
CPU time 17.7 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:18 PM PDT 24
Peak memory 213112 kb
Host smart-7c7ed57a-c5fb-4beb-80cf-8f6999cc231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500355324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.500355324
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3711138233
Short name T908
Test name
Test status
Simulation time 732811246 ps
CPU time 3.48 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:03 PM PDT 24
Peak memory 205036 kb
Host smart-bd889db0-6412-466e-8a7b-a411c4f25bd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711138233 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3711138233
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3072417536
Short name T876
Test name
Test status
Simulation time 408888679 ps
CPU time 0.84 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:01 PM PDT 24
Peak memory 215204 kb
Host smart-08e8eb38-e116-46e0-9878-4bac5b4bad38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072417536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3072417536
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1032751499
Short name T684
Test name
Test status
Simulation time 151100331 ps
CPU time 1.08 seconds
Started Jul 06 05:44:59 PM PDT 24
Finished Jul 06 05:45:01 PM PDT 24
Peak memory 212940 kb
Host smart-c1221455-5c01-454f-a463-2935d09641fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032751499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1032751499
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1944473071
Short name T1394
Test name
Test status
Simulation time 980372884 ps
CPU time 2.09 seconds
Started Jul 06 05:45:03 PM PDT 24
Finished Jul 06 05:45:05 PM PDT 24
Peak memory 204988 kb
Host smart-0ad0ca86-2f7f-4d10-889e-35395ff15899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944473071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1944473071
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2681081635
Short name T1509
Test name
Test status
Simulation time 176288824 ps
CPU time 1.45 seconds
Started Jul 06 05:45:01 PM PDT 24
Finished Jul 06 05:45:03 PM PDT 24
Peak memory 204840 kb
Host smart-39a21313-7cfb-4fbe-b59b-42606e2fff11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681081635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2681081635
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3643070698
Short name T1262
Test name
Test status
Simulation time 1554319424 ps
CPU time 3.46 seconds
Started Jul 06 05:44:58 PM PDT 24
Finished Jul 06 05:45:02 PM PDT 24
Peak memory 205028 kb
Host smart-207c74dd-9fa4-4364-8c1a-5de602af5e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643070698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3643070698
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2258441344
Short name T1068
Test name
Test status
Simulation time 1980904228 ps
CPU time 5.73 seconds
Started Jul 06 05:44:58 PM PDT 24
Finished Jul 06 05:45:04 PM PDT 24
Peak memory 205020 kb
Host smart-020cc3eb-4bea-403c-b84f-277b7705541a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258441344 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2258441344
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.4203097454
Short name T783
Test name
Test status
Simulation time 22501692406 ps
CPU time 58.74 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:59 PM PDT 24
Peak memory 1245824 kb
Host smart-e6778d39-754b-4617-bcf0-5a7b5fccbea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203097454 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4203097454
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2566897163
Short name T148
Test name
Test status
Simulation time 1158814169 ps
CPU time 42.21 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:42 PM PDT 24
Peak memory 204948 kb
Host smart-b795b8a6-c4e9-4a94-b8b7-ca0838f418d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566897163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2566897163
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1972516093
Short name T1451
Test name
Test status
Simulation time 1732386895 ps
CPU time 6.73 seconds
Started Jul 06 05:45:00 PM PDT 24
Finished Jul 06 05:45:07 PM PDT 24
Peak memory 205340 kb
Host smart-8c9b9396-971c-4521-b648-cbf594d18ce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972516093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1972516093
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3290865090
Short name T808
Test name
Test status
Simulation time 14099569679 ps
CPU time 24.37 seconds
Started Jul 06 05:45:01 PM PDT 24
Finished Jul 06 05:45:26 PM PDT 24
Peak memory 205056 kb
Host smart-701abf2b-8981-4c89-91f6-c6c52b39e4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290865090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3290865090
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.207330638
Short name T607
Test name
Test status
Simulation time 3641374869 ps
CPU time 13.04 seconds
Started Jul 06 05:44:59 PM PDT 24
Finished Jul 06 05:45:12 PM PDT 24
Peak memory 372556 kb
Host smart-9ff800d7-63b7-4b93-a556-84b604e9672c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207330638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.207330638
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1326712538
Short name T784
Test name
Test status
Simulation time 5488738511 ps
CPU time 7.46 seconds
Started Jul 06 05:44:59 PM PDT 24
Finished Jul 06 05:45:07 PM PDT 24
Peak memory 214760 kb
Host smart-3a3702e8-e6e8-456a-937d-7a367489084a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326712538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1326712538
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2700092438
Short name T1338
Test name
Test status
Simulation time 103623125 ps
CPU time 1.94 seconds
Started Jul 06 05:45:01 PM PDT 24
Finished Jul 06 05:45:03 PM PDT 24
Peak memory 205036 kb
Host smart-c55d053b-2028-4e04-9489-30772827e002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700092438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2700092438
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2847322210
Short name T128
Test name
Test status
Simulation time 44384984 ps
CPU time 0.62 seconds
Started Jul 06 05:45:17 PM PDT 24
Finished Jul 06 05:45:18 PM PDT 24
Peak memory 204640 kb
Host smart-89e73882-2d10-42ac-97b2-1682f6f0ad54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847322210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2847322210
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2922603115
Short name T317
Test name
Test status
Simulation time 336725181 ps
CPU time 1.5 seconds
Started Jul 06 05:45:10 PM PDT 24
Finished Jul 06 05:45:12 PM PDT 24
Peak memory 213368 kb
Host smart-4b232680-0df7-4f50-9c2e-d8ccced03046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922603115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2922603115
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.305350359
Short name T1011
Test name
Test status
Simulation time 1014535760 ps
CPU time 5.97 seconds
Started Jul 06 05:45:06 PM PDT 24
Finished Jul 06 05:45:13 PM PDT 24
Peak memory 258160 kb
Host smart-b42e08eb-2cf4-4f68-9aee-eac296d1c1fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305350359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.305350359
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3097686923
Short name T1500
Test name
Test status
Simulation time 1779498507 ps
CPU time 126.86 seconds
Started Jul 06 05:45:07 PM PDT 24
Finished Jul 06 05:47:14 PM PDT 24
Peak memory 642728 kb
Host smart-7fb6e68e-0dd6-4dd1-a367-57d599038ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097686923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3097686923
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3414130852
Short name T867
Test name
Test status
Simulation time 132700405 ps
CPU time 1.2 seconds
Started Jul 06 05:45:05 PM PDT 24
Finished Jul 06 05:45:06 PM PDT 24
Peak memory 204980 kb
Host smart-5382889b-c682-4c25-818c-cee97fcddead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414130852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3414130852
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2611944647
Short name T507
Test name
Test status
Simulation time 176476158 ps
CPU time 9.79 seconds
Started Jul 06 05:45:03 PM PDT 24
Finished Jul 06 05:45:13 PM PDT 24
Peak memory 235548 kb
Host smart-d6bc3a5a-997b-4529-b441-43e3bda312ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611944647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2611944647
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2768018454
Short name T1274
Test name
Test status
Simulation time 14125085342 ps
CPU time 230.59 seconds
Started Jul 06 05:45:06 PM PDT 24
Finished Jul 06 05:48:57 PM PDT 24
Peak memory 1050280 kb
Host smart-10457841-8d37-4325-8b91-344c3b14afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768018454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2768018454
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.646073024
Short name T305
Test name
Test status
Simulation time 429446148 ps
CPU time 6.89 seconds
Started Jul 06 05:45:16 PM PDT 24
Finished Jul 06 05:45:23 PM PDT 24
Peak memory 205044 kb
Host smart-30bb238f-0388-4b2b-9bcc-36137a642764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646073024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.646073024
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2951713167
Short name T625
Test name
Test status
Simulation time 6188637617 ps
CPU time 72.38 seconds
Started Jul 06 05:45:17 PM PDT 24
Finished Jul 06 05:46:29 PM PDT 24
Peak memory 389168 kb
Host smart-0eb997f9-9509-4e7c-8dc7-39b5fcdadaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951713167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2951713167
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1192781950
Short name T1481
Test name
Test status
Simulation time 43845097 ps
CPU time 0.68 seconds
Started Jul 06 05:45:06 PM PDT 24
Finished Jul 06 05:45:06 PM PDT 24
Peak memory 204728 kb
Host smart-acea499b-bd8f-4ce4-aeef-d287ff3d713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192781950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1192781950
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2967255650
Short name T803
Test name
Test status
Simulation time 6905364010 ps
CPU time 20.09 seconds
Started Jul 06 05:45:03 PM PDT 24
Finished Jul 06 05:45:24 PM PDT 24
Peak memory 241536 kb
Host smart-9c6689d4-ce33-49c7-8cdd-986c4d177f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967255650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2967255650
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.439080666
Short name T581
Test name
Test status
Simulation time 219428052 ps
CPU time 2.26 seconds
Started Jul 06 05:45:08 PM PDT 24
Finished Jul 06 05:45:11 PM PDT 24
Peak memory 205000 kb
Host smart-8a058571-9114-4bd6-82c1-96ac7989b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439080666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.439080666
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.762927735
Short name T1467
Test name
Test status
Simulation time 5380080074 ps
CPU time 76.18 seconds
Started Jul 06 05:45:04 PM PDT 24
Finished Jul 06 05:46:21 PM PDT 24
Peak memory 354044 kb
Host smart-89e055db-9d4a-43f7-bb57-2c62960ad289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762927735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.762927735
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1429877573
Short name T258
Test name
Test status
Simulation time 8216613172 ps
CPU time 684.01 seconds
Started Jul 06 05:45:09 PM PDT 24
Finished Jul 06 05:56:33 PM PDT 24
Peak memory 1865508 kb
Host smart-6f6b7ec4-677d-418e-9e1f-5ba89ec1a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429877573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1429877573
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.180005230
Short name T424
Test name
Test status
Simulation time 994421112 ps
CPU time 43.4 seconds
Started Jul 06 05:45:10 PM PDT 24
Finished Jul 06 05:45:54 PM PDT 24
Peak memory 221176 kb
Host smart-99033667-3936-426e-b7ab-5bf2d827b7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180005230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.180005230
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1474822742
Short name T538
Test name
Test status
Simulation time 1984863643 ps
CPU time 2.81 seconds
Started Jul 06 05:45:11 PM PDT 24
Finished Jul 06 05:45:14 PM PDT 24
Peak memory 205024 kb
Host smart-ea8263d3-891a-4dd7-81b0-b24112b25029
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474822742 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1474822742
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1552519942
Short name T743
Test name
Test status
Simulation time 729837849 ps
CPU time 1.27 seconds
Started Jul 06 05:45:13 PM PDT 24
Finished Jul 06 05:45:15 PM PDT 24
Peak memory 204836 kb
Host smart-0bd16a6f-48b0-41f5-8620-d3d35e6ba71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552519942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1552519942
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1848251125
Short name T1280
Test name
Test status
Simulation time 239065711 ps
CPU time 0.84 seconds
Started Jul 06 05:45:08 PM PDT 24
Finished Jul 06 05:45:09 PM PDT 24
Peak memory 204832 kb
Host smart-46411d48-1e50-4915-8133-d066c4d255f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848251125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1848251125
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.1472283592
Short name T688
Test name
Test status
Simulation time 274317197 ps
CPU time 1.54 seconds
Started Jul 06 05:45:16 PM PDT 24
Finished Jul 06 05:45:18 PM PDT 24
Peak memory 204784 kb
Host smart-cb347895-0121-4fc8-9cbb-2140682e13fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472283592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.1472283592
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.4070382392
Short name T1293
Test name
Test status
Simulation time 131540300 ps
CPU time 1.26 seconds
Started Jul 06 05:45:15 PM PDT 24
Finished Jul 06 05:45:17 PM PDT 24
Peak memory 204828 kb
Host smart-d71a2e71-8f10-46d1-94f6-bc8a471dc8a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070382392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.4070382392
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.404950130
Short name T425
Test name
Test status
Simulation time 1635850686 ps
CPU time 3.31 seconds
Started Jul 06 05:45:16 PM PDT 24
Finished Jul 06 05:45:20 PM PDT 24
Peak memory 205132 kb
Host smart-b6d023f1-1a9e-4824-a6bc-1f84c2e9bda1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404950130 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.404950130
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2253231968
Short name T1313
Test name
Test status
Simulation time 3376530186 ps
CPU time 4.99 seconds
Started Jul 06 05:45:10 PM PDT 24
Finished Jul 06 05:45:16 PM PDT 24
Peak memory 213436 kb
Host smart-4320d670-2e2a-4110-88c5-4dd8f7656719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253231968 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2253231968
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3856178058
Short name T1263
Test name
Test status
Simulation time 5726169616 ps
CPU time 25.36 seconds
Started Jul 06 05:45:08 PM PDT 24
Finished Jul 06 05:45:34 PM PDT 24
Peak memory 819228 kb
Host smart-11179b1d-d3e1-42f3-a603-5b6032d15a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856178058 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3856178058
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2486852370
Short name T504
Test name
Test status
Simulation time 2186392259 ps
CPU time 44.35 seconds
Started Jul 06 05:45:09 PM PDT 24
Finished Jul 06 05:45:54 PM PDT 24
Peak memory 205076 kb
Host smart-f855ca50-80b1-41f0-ad04-54b7bfda6e6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486852370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2486852370
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.994798066
Short name T1229
Test name
Test status
Simulation time 2389482583 ps
CPU time 22.03 seconds
Started Jul 06 05:45:10 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 217676 kb
Host smart-c81eee72-151c-4d17-b31b-3aad1d594157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994798066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.994798066
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.55527899
Short name T304
Test name
Test status
Simulation time 61663936409 ps
CPU time 1664.56 seconds
Started Jul 06 05:45:09 PM PDT 24
Finished Jul 06 06:12:54 PM PDT 24
Peak memory 10279916 kb
Host smart-dc866eb3-e178-478b-84af-06b93089f40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55527899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_wr.55527899
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2435796759
Short name T502
Test name
Test status
Simulation time 3085886196 ps
CPU time 145.89 seconds
Started Jul 06 05:45:12 PM PDT 24
Finished Jul 06 05:47:38 PM PDT 24
Peak memory 858164 kb
Host smart-6ef7d2ce-6c29-4b98-ab85-00fbf9a9d76c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435796759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2435796759
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2670220657
Short name T1388
Test name
Test status
Simulation time 981883106 ps
CPU time 6.45 seconds
Started Jul 06 05:45:09 PM PDT 24
Finished Jul 06 05:45:16 PM PDT 24
Peak memory 211520 kb
Host smart-cabffd28-57f0-4c4c-b3bb-09dbfef03d39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670220657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2670220657
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.2323742437
Short name T930
Test name
Test status
Simulation time 917650079 ps
CPU time 11.32 seconds
Started Jul 06 05:45:15 PM PDT 24
Finished Jul 06 05:45:26 PM PDT 24
Peak memory 214296 kb
Host smart-6231c03d-7bff-407a-bfb4-1ffa785a98b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323742437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2323742437
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2250484877
Short name T591
Test name
Test status
Simulation time 57005760 ps
CPU time 0.61 seconds
Started Jul 06 05:45:26 PM PDT 24
Finished Jul 06 05:45:27 PM PDT 24
Peak memory 204572 kb
Host smart-fee5c5ac-7e14-4be9-9df2-eec47cc5844f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250484877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2250484877
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4215947020
Short name T1254
Test name
Test status
Simulation time 167769561 ps
CPU time 1.19 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:45:23 PM PDT 24
Peak memory 205108 kb
Host smart-c3dd1d46-7c03-4aeb-a80e-1cb1a8b1f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215947020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4215947020
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.866810776
Short name T321
Test name
Test status
Simulation time 1312200228 ps
CPU time 7.72 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:45:28 PM PDT 24
Peak memory 277400 kb
Host smart-fd247120-46eb-40c4-b7f3-c3db28da7b22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866810776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.866810776
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3407240550
Short name T631
Test name
Test status
Simulation time 9222809605 ps
CPU time 66.15 seconds
Started Jul 06 05:45:20 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 697540 kb
Host smart-9f783c9c-bef5-4991-b5f8-70c81f30836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407240550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3407240550
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1008627492
Short name T355
Test name
Test status
Simulation time 3932231301 ps
CPU time 57.74 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:46:20 PM PDT 24
Peak memory 593248 kb
Host smart-988c4687-f59f-4c8c-9f5b-de6a47b2d75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008627492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1008627492
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.906768479
Short name T878
Test name
Test status
Simulation time 213538657 ps
CPU time 0.92 seconds
Started Jul 06 05:45:20 PM PDT 24
Finished Jul 06 05:45:22 PM PDT 24
Peak memory 204772 kb
Host smart-870b39d7-a2f1-491d-91d2-350bee751cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906768479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.906768479
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2839393311
Short name T726
Test name
Test status
Simulation time 203470067 ps
CPU time 11.75 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:45:34 PM PDT 24
Peak memory 244100 kb
Host smart-4c44a120-ef49-443c-8112-7a3a03d51510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839393311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2839393311
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1427560164
Short name T1124
Test name
Test status
Simulation time 11273985097 ps
CPU time 64.83 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 929080 kb
Host smart-23ef3a21-af4d-458d-9f60-f4535a3c7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427560164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1427560164
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.666052122
Short name T1491
Test name
Test status
Simulation time 495737904 ps
CPU time 7.87 seconds
Started Jul 06 05:45:28 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 205092 kb
Host smart-47201f96-868a-4436-9ed1-0fc23ffdf1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666052122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.666052122
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2717701974
Short name T1024
Test name
Test status
Simulation time 1989907155 ps
CPU time 18.57 seconds
Started Jul 06 05:45:26 PM PDT 24
Finished Jul 06 05:45:45 PM PDT 24
Peak memory 315488 kb
Host smart-0989737e-977a-4061-a572-f30fc86bcb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717701974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2717701974
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3131700678
Short name T943
Test name
Test status
Simulation time 17140325 ps
CPU time 0.67 seconds
Started Jul 06 05:45:15 PM PDT 24
Finished Jul 06 05:45:16 PM PDT 24
Peak memory 204676 kb
Host smart-fc804394-bd43-409a-a013-aeb6586a8d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131700678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3131700678
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3075179413
Short name T1152
Test name
Test status
Simulation time 7080520411 ps
CPU time 66.18 seconds
Started Jul 06 05:45:20 PM PDT 24
Finished Jul 06 05:46:26 PM PDT 24
Peak memory 213320 kb
Host smart-da85d961-ae30-475c-8f97-b11042889c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075179413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3075179413
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.732100321
Short name T1106
Test name
Test status
Simulation time 730232817 ps
CPU time 15.65 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:45:38 PM PDT 24
Peak memory 256196 kb
Host smart-4ab30647-540d-4f90-8b08-2906062ce4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732100321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.732100321
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3998335490
Short name T461
Test name
Test status
Simulation time 2295608737 ps
CPU time 80.34 seconds
Started Jul 06 05:45:17 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 354456 kb
Host smart-444d57b6-fda6-4d30-bafe-c28e6f59095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998335490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3998335490
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.121781283
Short name T676
Test name
Test status
Simulation time 31564661385 ps
CPU time 496.16 seconds
Started Jul 06 05:45:20 PM PDT 24
Finished Jul 06 05:53:36 PM PDT 24
Peak memory 1019396 kb
Host smart-77fa3c8e-18ca-417e-8f15-061b97d24118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121781283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.121781283
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2379910515
Short name T281
Test name
Test status
Simulation time 860443318 ps
CPU time 14.68 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 218200 kb
Host smart-a4f82be0-9d06-43a1-a82e-4a3e2a3921de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379910515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2379910515
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2771870205
Short name T1141
Test name
Test status
Simulation time 2487353809 ps
CPU time 3.05 seconds
Started Jul 06 05:45:28 PM PDT 24
Finished Jul 06 05:45:31 PM PDT 24
Peak memory 205104 kb
Host smart-7fd5075a-5481-4f93-9b13-5119a21280c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771870205 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2771870205
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.445099860
Short name T16
Test name
Test status
Simulation time 245335191 ps
CPU time 1.44 seconds
Started Jul 06 05:45:26 PM PDT 24
Finished Jul 06 05:45:28 PM PDT 24
Peak memory 204836 kb
Host smart-7f9a4c7f-22d8-4def-bda4-94868172639c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445099860 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.445099860
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1109656295
Short name T1524
Test name
Test status
Simulation time 744672378 ps
CPU time 1.46 seconds
Started Jul 06 05:45:25 PM PDT 24
Finished Jul 06 05:45:27 PM PDT 24
Peak memory 204996 kb
Host smart-03d52c16-6402-4e13-a7b7-ed25efe81d45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109656295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1109656295
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.2751923714
Short name T7
Test name
Test status
Simulation time 511502522 ps
CPU time 2.49 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 205080 kb
Host smart-2f881b5c-0e62-4b66-8577-a96d765f85f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751923714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.2751923714
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.3351795930
Short name T1489
Test name
Test status
Simulation time 487681590 ps
CPU time 1.19 seconds
Started Jul 06 05:45:27 PM PDT 24
Finished Jul 06 05:45:28 PM PDT 24
Peak memory 204848 kb
Host smart-ef6f4cd2-51a7-45b3-b6d2-61b19d211533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351795930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.3351795930
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.2085715996
Short name T294
Test name
Test status
Simulation time 2803504591 ps
CPU time 2.58 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 205132 kb
Host smart-84c46bcc-558d-4179-b885-85ccb13dece5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085715996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.2085715996
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3635219431
Short name T405
Test name
Test status
Simulation time 12164637648 ps
CPU time 5.6 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:45:27 PM PDT 24
Peak memory 211268 kb
Host smart-f58cadaf-2d3d-4927-9b02-7cecbf0821de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635219431 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3635219431
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.4110196337
Short name T1051
Test name
Test status
Simulation time 14690453010 ps
CPU time 155.77 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:47:57 PM PDT 24
Peak memory 2035396 kb
Host smart-f1650ae5-3598-4d59-9333-08dd4fdc59be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110196337 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.4110196337
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.792938717
Short name T1190
Test name
Test status
Simulation time 1534790839 ps
CPU time 58.71 seconds
Started Jul 06 05:45:21 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 205060 kb
Host smart-991a653c-9fde-4389-9c67-1625c983c918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792938717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.792938717
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3181272635
Short name T230
Test name
Test status
Simulation time 47539866766 ps
CPU time 127.38 seconds
Started Jul 06 05:45:22 PM PDT 24
Finished Jul 06 05:47:30 PM PDT 24
Peak memory 1807932 kb
Host smart-42c181f9-acc9-4e45-94e0-4877b3c6fbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181272635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3181272635
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.2374284706
Short name T1261
Test name
Test status
Simulation time 57361402 ps
CPU time 1.46 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:45:31 PM PDT 24
Peak memory 205044 kb
Host smart-e0c960be-d779-4f27-8358-46ec5c9bffd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374284706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2374284706
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.784905866
Short name T521
Test name
Test status
Simulation time 33530029 ps
CPU time 0.67 seconds
Started Jul 06 05:45:40 PM PDT 24
Finished Jul 06 05:45:41 PM PDT 24
Peak memory 204624 kb
Host smart-75e7768d-c976-428f-adc3-501928b98366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784905866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.784905866
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1794076460
Short name T1037
Test name
Test status
Simulation time 203204219 ps
CPU time 2.08 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:45:33 PM PDT 24
Peak memory 213312 kb
Host smart-136c5876-9228-469e-b3ae-fd6c2cfc2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794076460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1794076460
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1915115113
Short name T1438
Test name
Test status
Simulation time 447858812 ps
CPU time 7.94 seconds
Started Jul 06 05:45:25 PM PDT 24
Finished Jul 06 05:45:33 PM PDT 24
Peak memory 302240 kb
Host smart-8d85d4a5-90e7-463c-acb1-7e8ffe951da2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915115113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1915115113
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2332050854
Short name T482
Test name
Test status
Simulation time 2537998155 ps
CPU time 78.78 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:46:48 PM PDT 24
Peak memory 661340 kb
Host smart-d2966d45-895a-4a94-b0fa-922c018c75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332050854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2332050854
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1801612585
Short name T810
Test name
Test status
Simulation time 10424306548 ps
CPU time 85.37 seconds
Started Jul 06 05:45:28 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 855668 kb
Host smart-b1d1a067-9e91-4ddc-8b87-c5938b2ffcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801612585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1801612585
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3724107473
Short name T1087
Test name
Test status
Simulation time 260835867 ps
CPU time 1.02 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:45:30 PM PDT 24
Peak memory 204772 kb
Host smart-b92f624d-69d8-4b21-a0d6-778263cf1976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724107473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3724107473
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2236955848
Short name T306
Test name
Test status
Simulation time 804122378 ps
CPU time 10.91 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:45:40 PM PDT 24
Peak memory 205068 kb
Host smart-07f0a481-5184-4317-b47d-3d6b2dc854c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236955848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2236955848
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.243693419
Short name T1062
Test name
Test status
Simulation time 4071033588 ps
CPU time 96.44 seconds
Started Jul 06 05:45:25 PM PDT 24
Finished Jul 06 05:47:02 PM PDT 24
Peak memory 1183312 kb
Host smart-efcd951a-0f86-4ba3-b829-613d806c1311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243693419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.243693419
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2222519931
Short name T1013
Test name
Test status
Simulation time 746588902 ps
CPU time 8.77 seconds
Started Jul 06 05:45:35 PM PDT 24
Finished Jul 06 05:45:44 PM PDT 24
Peak memory 204948 kb
Host smart-510231d4-9ce3-425a-8805-e046b25ea464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222519931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2222519931
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2897813505
Short name T1335
Test name
Test status
Simulation time 39354089933 ps
CPU time 31.58 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:46:03 PM PDT 24
Peak memory 362324 kb
Host smart-4f1a10fd-20f4-4267-a31f-3d5f28f9b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897813505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2897813505
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3207670308
Short name T956
Test name
Test status
Simulation time 46874521 ps
CPU time 0.64 seconds
Started Jul 06 05:45:26 PM PDT 24
Finished Jul 06 05:45:27 PM PDT 24
Peak memory 204716 kb
Host smart-a1367cfa-529e-4df4-82ba-7ad0a5c1e91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207670308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3207670308
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1428206922
Short name T677
Test name
Test status
Simulation time 218056836 ps
CPU time 2.45 seconds
Started Jul 06 05:45:27 PM PDT 24
Finished Jul 06 05:45:30 PM PDT 24
Peak memory 229604 kb
Host smart-aaf52dbf-cf34-454d-97c2-af465d326621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428206922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1428206922
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.4266602867
Short name T404
Test name
Test status
Simulation time 1398367828 ps
CPU time 58.23 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 299864 kb
Host smart-acae40bd-a566-4f3d-921d-caa5bda2fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266602867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.4266602867
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4061116397
Short name T412
Test name
Test status
Simulation time 1614505357 ps
CPU time 26.39 seconds
Started Jul 06 05:45:30 PM PDT 24
Finished Jul 06 05:45:56 PM PDT 24
Peak memory 327848 kb
Host smart-946815e0-1cfc-43dc-9ea1-40543e10ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061116397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4061116397
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2212098794
Short name T249
Test name
Test status
Simulation time 43729281792 ps
CPU time 1154.18 seconds
Started Jul 06 05:45:30 PM PDT 24
Finished Jul 06 06:04:45 PM PDT 24
Peak memory 2000340 kb
Host smart-755fd797-19da-47ab-a57e-002e1a57ed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212098794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2212098794
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.736375068
Short name T1069
Test name
Test status
Simulation time 1469536759 ps
CPU time 35.65 seconds
Started Jul 06 05:45:26 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 213184 kb
Host smart-a33a32ff-bd2c-49ec-b287-3e8cf57d1f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736375068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.736375068
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1817332989
Short name T1130
Test name
Test status
Simulation time 798725275 ps
CPU time 4.11 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 205036 kb
Host smart-6c32580e-23da-4915-aaac-2467d02ac1f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817332989 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1817332989
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2280797364
Short name T339
Test name
Test status
Simulation time 206002452 ps
CPU time 1.31 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:45:33 PM PDT 24
Peak memory 205032 kb
Host smart-976c75be-a55a-4b65-a50d-13e180716ef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280797364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2280797364
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3212160466
Short name T1098
Test name
Test status
Simulation time 713267699 ps
CPU time 1.41 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 205028 kb
Host smart-a54229c9-5109-4972-b28e-7b1f01e1f6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212160466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3212160466
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.402709695
Short name T668
Test name
Test status
Simulation time 2109564953 ps
CPU time 2.94 seconds
Started Jul 06 05:45:37 PM PDT 24
Finished Jul 06 05:45:41 PM PDT 24
Peak memory 205080 kb
Host smart-07adaa35-22dc-436e-be6b-0d8b5e4d64d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402709695 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.402709695
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.375854868
Short name T528
Test name
Test status
Simulation time 95961382 ps
CPU time 0.97 seconds
Started Jul 06 05:45:35 PM PDT 24
Finished Jul 06 05:45:37 PM PDT 24
Peak memory 204808 kb
Host smart-a62f51b7-2592-4bd9-84cd-1b63390b1f53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375854868 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.375854868
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1184600060
Short name T1417
Test name
Test status
Simulation time 1988769903 ps
CPU time 2.77 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:45:35 PM PDT 24
Peak memory 205100 kb
Host smart-e029e211-5cdf-483d-8178-8dc0ff7e810d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184600060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1184600060
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1100526083
Short name T1210
Test name
Test status
Simulation time 1250396837 ps
CPU time 3.71 seconds
Started Jul 06 05:45:32 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 205020 kb
Host smart-bc0ced6b-729b-4fc8-9a1c-da719e97b71b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100526083 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1100526083
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2013120138
Short name T857
Test name
Test status
Simulation time 17624860475 ps
CPU time 208.77 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:49:00 PM PDT 24
Peak memory 3130556 kb
Host smart-f50f1462-6c9f-461a-abe2-183750df2486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013120138 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2013120138
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3550978328
Short name T806
Test name
Test status
Simulation time 1093628653 ps
CPU time 46.43 seconds
Started Jul 06 05:45:29 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 205016 kb
Host smart-d17f4b30-6932-4051-a69c-77ef17a381f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550978328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3550978328
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.4074304795
Short name T594
Test name
Test status
Simulation time 10337985154 ps
CPU time 65.91 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 210440 kb
Host smart-f72de263-d329-455b-a685-bec76c821579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074304795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.4074304795
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1431938386
Short name T785
Test name
Test status
Simulation time 47968327840 ps
CPU time 329.55 seconds
Started Jul 06 05:45:31 PM PDT 24
Finished Jul 06 05:51:01 PM PDT 24
Peak memory 3403028 kb
Host smart-0538ed92-227c-4402-85a2-a20334a709d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431938386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1431938386
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.12506763
Short name T1382
Test name
Test status
Simulation time 1494838247 ps
CPU time 4.11 seconds
Started Jul 06 05:45:32 PM PDT 24
Finished Jul 06 05:45:37 PM PDT 24
Peak memory 253916 kb
Host smart-f6142417-baf2-4999-b5bb-d4805de0208b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_stretch.12506763
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1396651749
Short name T1405
Test name
Test status
Simulation time 1226071532 ps
CPU time 7.59 seconds
Started Jul 06 05:45:30 PM PDT 24
Finished Jul 06 05:45:37 PM PDT 24
Peak memory 221308 kb
Host smart-cfd76d6c-a53e-4aa6-81ed-9e11f5f4aacc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396651749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1396651749
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.3128325771
Short name T921
Test name
Test status
Simulation time 135807788 ps
CPU time 2.44 seconds
Started Jul 06 05:45:37 PM PDT 24
Finished Jul 06 05:45:40 PM PDT 24
Peak memory 205028 kb
Host smart-e48c97a3-c657-4735-a867-4adb7bae6d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128325771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3128325771
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1561454124
Short name T1464
Test name
Test status
Simulation time 27344920 ps
CPU time 0.62 seconds
Started Jul 06 05:45:48 PM PDT 24
Finished Jul 06 05:45:48 PM PDT 24
Peak memory 204660 kb
Host smart-6279a4e2-3e9b-49bb-b3aa-087b57e47144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561454124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1561454124
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2737548467
Short name T345
Test name
Test status
Simulation time 548194750 ps
CPU time 2.27 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:45:44 PM PDT 24
Peak memory 213320 kb
Host smart-ea88fc3b-32ac-4dd5-944c-444a2d3615e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737548467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2737548467
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2937718471
Short name T397
Test name
Test status
Simulation time 4930048426 ps
CPU time 7.41 seconds
Started Jul 06 05:45:35 PM PDT 24
Finished Jul 06 05:45:43 PM PDT 24
Peak memory 272180 kb
Host smart-8b607269-1f47-49c1-868f-0a1fe78cc9d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937718471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2937718471
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.587405210
Short name T1449
Test name
Test status
Simulation time 2904535950 ps
CPU time 110.02 seconds
Started Jul 06 05:45:35 PM PDT 24
Finished Jul 06 05:47:26 PM PDT 24
Peak memory 899724 kb
Host smart-4476d968-5947-4750-853b-41ee1edc488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587405210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.587405210
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1742706127
Short name T770
Test name
Test status
Simulation time 6612720950 ps
CPU time 118.46 seconds
Started Jul 06 05:45:38 PM PDT 24
Finished Jul 06 05:47:37 PM PDT 24
Peak memory 617640 kb
Host smart-a54fc272-6077-439c-aeb1-0baa23fc3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742706127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1742706127
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2631213662
Short name T634
Test name
Test status
Simulation time 62150039 ps
CPU time 0.9 seconds
Started Jul 06 05:45:36 PM PDT 24
Finished Jul 06 05:45:38 PM PDT 24
Peak memory 204768 kb
Host smart-6b4c24a9-6738-4207-b258-1fa3d584e882
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631213662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2631213662
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2225771756
Short name T481
Test name
Test status
Simulation time 191579500 ps
CPU time 10.08 seconds
Started Jul 06 05:45:36 PM PDT 24
Finished Jul 06 05:45:46 PM PDT 24
Peak memory 236104 kb
Host smart-2e5712e5-aa0f-4882-a62b-3dccf15c165e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225771756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2225771756
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3661721523
Short name T690
Test name
Test status
Simulation time 5247273440 ps
CPU time 159.19 seconds
Started Jul 06 05:45:36 PM PDT 24
Finished Jul 06 05:48:16 PM PDT 24
Peak memory 1388200 kb
Host smart-ce5e2d09-6887-41db-a810-7b5af4e552f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661721523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3661721523
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2314483357
Short name T1339
Test name
Test status
Simulation time 365601688 ps
CPU time 5.95 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:45:55 PM PDT 24
Peak memory 205116 kb
Host smart-cee0b470-666d-47c5-beb2-e2187843024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314483357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2314483357
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.4247788034
Short name T329
Test name
Test status
Simulation time 10125377346 ps
CPU time 76.23 seconds
Started Jul 06 05:45:46 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 338848 kb
Host smart-41872d23-53e0-4d75-8ff3-e3216f6157d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247788034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.4247788034
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.498584217
Short name T830
Test name
Test status
Simulation time 67634575 ps
CPU time 0.65 seconds
Started Jul 06 05:45:37 PM PDT 24
Finished Jul 06 05:45:38 PM PDT 24
Peak memory 204752 kb
Host smart-55486310-3133-4902-bdce-ad2ac3d531da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498584217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.498584217
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2584824628
Short name T1253
Test name
Test status
Simulation time 4609871071 ps
CPU time 19.06 seconds
Started Jul 06 05:45:37 PM PDT 24
Finished Jul 06 05:45:57 PM PDT 24
Peak memory 266004 kb
Host smart-da0bd3c5-aab7-4dc3-bbdf-d713b4441468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584824628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2584824628
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.1631439401
Short name T966
Test name
Test status
Simulation time 2503947532 ps
CPU time 34.08 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 205588 kb
Host smart-1090eab8-0678-41e0-8ee5-95841ca71022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631439401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1631439401
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3328389614
Short name T1123
Test name
Test status
Simulation time 6484425879 ps
CPU time 24.95 seconds
Started Jul 06 05:45:38 PM PDT 24
Finished Jul 06 05:46:03 PM PDT 24
Peak memory 375172 kb
Host smart-59ae5cf5-dcf8-4ed1-b924-f1d28753c8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328389614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3328389614
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.801997474
Short name T36
Test name
Test status
Simulation time 726702852 ps
CPU time 33.69 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 213188 kb
Host smart-489d6795-dfc5-4629-b6a2-b3f33ed8a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801997474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.801997474
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.623269375
Short name T1443
Test name
Test status
Simulation time 1431262831 ps
CPU time 4.29 seconds
Started Jul 06 05:45:50 PM PDT 24
Finished Jul 06 05:45:55 PM PDT 24
Peak memory 213228 kb
Host smart-65677eac-b9ef-4953-85cb-fa2bd650f353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623269375 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.623269375
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1221465810
Short name T1487
Test name
Test status
Simulation time 126404284 ps
CPU time 0.95 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:45:43 PM PDT 24
Peak memory 204828 kb
Host smart-3fc843b9-cf50-4604-bf77-f9d82b8746f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221465810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1221465810
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1321340036
Short name T562
Test name
Test status
Simulation time 198314202 ps
CPU time 1.09 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:45:43 PM PDT 24
Peak memory 204820 kb
Host smart-27654b32-4b8e-4d96-814b-7be556844f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321340036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1321340036
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.541203208
Short name T239
Test name
Test status
Simulation time 544699276 ps
CPU time 2.88 seconds
Started Jul 06 05:45:47 PM PDT 24
Finished Jul 06 05:45:50 PM PDT 24
Peak memory 213216 kb
Host smart-175530d5-48c1-4fee-a905-632a284d5ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541203208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.541203208
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1537857211
Short name T307
Test name
Test status
Simulation time 306496791 ps
CPU time 1.38 seconds
Started Jul 06 05:45:50 PM PDT 24
Finished Jul 06 05:45:52 PM PDT 24
Peak memory 204836 kb
Host smart-482a9799-c871-47fd-ac71-d12aaf77fb20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537857211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1537857211
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1394035958
Short name T887
Test name
Test status
Simulation time 623002133 ps
CPU time 3.65 seconds
Started Jul 06 05:45:41 PM PDT 24
Finished Jul 06 05:45:45 PM PDT 24
Peak memory 205032 kb
Host smart-4b5e84f8-9df2-4747-aecf-f66fe19316c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394035958 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1394035958
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2080199705
Short name T1194
Test name
Test status
Simulation time 32865054503 ps
CPU time 18.81 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:46:01 PM PDT 24
Peak memory 515756 kb
Host smart-80ae27e0-aa2c-40ab-934d-c53feb3b824b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080199705 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2080199705
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4192780855
Short name T150
Test name
Test status
Simulation time 11488893115 ps
CPU time 13.58 seconds
Started Jul 06 05:45:40 PM PDT 24
Finished Jul 06 05:45:54 PM PDT 24
Peak memory 205048 kb
Host smart-e4d47364-aa63-41fe-8ea8-48ca8076cd1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192780855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4192780855
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3444995298
Short name T603
Test name
Test status
Simulation time 1931029634 ps
CPU time 30.55 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:46:13 PM PDT 24
Peak memory 204980 kb
Host smart-f26f259e-fcc3-4a06-8b20-ba1ea0caaee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444995298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3444995298
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3845657121
Short name T797
Test name
Test status
Simulation time 64896550169 ps
CPU time 629.86 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:56:12 PM PDT 24
Peak memory 5712240 kb
Host smart-21474196-da4b-457a-b9f4-475db91d7dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845657121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3845657121
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.2566711610
Short name T559
Test name
Test status
Simulation time 1061796714 ps
CPU time 33.76 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 347500 kb
Host smart-9a59ea68-a076-4ad3-858d-22388fcb689f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566711610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.2566711610
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.4020793389
Short name T965
Test name
Test status
Simulation time 10075595702 ps
CPU time 7.42 seconds
Started Jul 06 05:45:42 PM PDT 24
Finished Jul 06 05:45:50 PM PDT 24
Peak memory 213400 kb
Host smart-274e25df-52fc-48ce-bdf4-834aae86d1e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020793389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.4020793389
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.3525067276
Short name T782
Test name
Test status
Simulation time 144936738 ps
CPU time 2.08 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:45:51 PM PDT 24
Peak memory 205008 kb
Host smart-58c47817-990d-4b63-b985-79f1552b8fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525067276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3525067276
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1071195278
Short name T759
Test name
Test status
Simulation time 56490586 ps
CPU time 0.63 seconds
Started Jul 06 05:38:52 PM PDT 24
Finished Jul 06 05:38:53 PM PDT 24
Peak memory 204540 kb
Host smart-ec1fe059-674c-4f9f-b0ea-cfff9d7b00d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071195278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1071195278
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4028766575
Short name T1465
Test name
Test status
Simulation time 199080567 ps
CPU time 6.01 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:51 PM PDT 24
Peak memory 234316 kb
Host smart-002a548b-4c15-4cba-aa64-8e026b6f4c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028766575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4028766575
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2438211157
Short name T431
Test name
Test status
Simulation time 968551580 ps
CPU time 4.35 seconds
Started Jul 06 05:38:37 PM PDT 24
Finished Jul 06 05:38:41 PM PDT 24
Peak memory 246916 kb
Host smart-e8ff0f07-b74d-4c70-8fe9-c601664bfaa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438211157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2438211157
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3069933142
Short name T1514
Test name
Test status
Simulation time 32734478968 ps
CPU time 49.44 seconds
Started Jul 06 05:38:42 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 471364 kb
Host smart-0054f9fb-ef7a-4de2-bc6e-54c9d4bd5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069933142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3069933142
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.344075447
Short name T1526
Test name
Test status
Simulation time 7013771317 ps
CPU time 48.89 seconds
Started Jul 06 05:38:38 PM PDT 24
Finished Jul 06 05:39:27 PM PDT 24
Peak memory 590688 kb
Host smart-7f80abdf-01b3-4924-b081-639badfb6306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344075447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.344075447
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1563411729
Short name T218
Test name
Test status
Simulation time 587640570 ps
CPU time 1.32 seconds
Started Jul 06 05:38:37 PM PDT 24
Finished Jul 06 05:38:39 PM PDT 24
Peak memory 204996 kb
Host smart-a996fa69-c376-4c8f-96e8-41ccd4e6c740
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563411729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1563411729
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2478924620
Short name T420
Test name
Test status
Simulation time 1787595494 ps
CPU time 3.57 seconds
Started Jul 06 05:38:42 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 205016 kb
Host smart-bd1d3b40-62cd-4e8d-9e6a-bb2ce9f1f7ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478924620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2478924620
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1298068627
Short name T101
Test name
Test status
Simulation time 43263350795 ps
CPU time 96.31 seconds
Started Jul 06 05:38:39 PM PDT 24
Finished Jul 06 05:40:16 PM PDT 24
Peak memory 1175836 kb
Host smart-5c5bfc72-3666-4b28-a2e9-b5b37d0ae8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298068627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1298068627
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3958035398
Short name T964
Test name
Test status
Simulation time 903361842 ps
CPU time 19.02 seconds
Started Jul 06 05:38:52 PM PDT 24
Finished Jul 06 05:39:11 PM PDT 24
Peak memory 205076 kb
Host smart-7de2eeca-93fe-4581-8f61-f6cb3a3e414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958035398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3958035398
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3982286681
Short name T465
Test name
Test status
Simulation time 1658309918 ps
CPU time 71.16 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:40:06 PM PDT 24
Peak memory 302052 kb
Host smart-f2a5e657-de84-4db7-b35d-d8cd63335507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982286681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3982286681
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.871269440
Short name T1511
Test name
Test status
Simulation time 82892660 ps
CPU time 0.69 seconds
Started Jul 06 05:38:41 PM PDT 24
Finished Jul 06 05:38:42 PM PDT 24
Peak memory 204760 kb
Host smart-1acb3572-6424-49c1-b231-c0204f04760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871269440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.871269440
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2212790907
Short name T734
Test name
Test status
Simulation time 5337644185 ps
CPU time 42.64 seconds
Started Jul 06 05:38:38 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 461780 kb
Host smart-66b50d8f-8cdb-4038-b6f8-4d4c4aea89c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212790907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2212790907
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.910996520
Short name T211
Test name
Test status
Simulation time 232792597 ps
CPU time 4.53 seconds
Started Jul 06 05:38:42 PM PDT 24
Finished Jul 06 05:38:47 PM PDT 24
Peak memory 234648 kb
Host smart-7f8cbd15-ec61-4fbc-8431-c5bec6dad3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910996520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.910996520
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1373296306
Short name T898
Test name
Test status
Simulation time 3343888988 ps
CPU time 27.97 seconds
Started Jul 06 05:38:39 PM PDT 24
Finished Jul 06 05:39:07 PM PDT 24
Peak memory 382024 kb
Host smart-6fe82f6f-5eb4-428b-83e5-55264801ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373296306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1373296306
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.912310717
Short name T939
Test name
Test status
Simulation time 745837003 ps
CPU time 11.9 seconds
Started Jul 06 05:38:40 PM PDT 24
Finished Jul 06 05:38:52 PM PDT 24
Peak memory 220380 kb
Host smart-ab25e759-7e41-422d-9ed8-9412decc4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912310717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.912310717
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3590467024
Short name T151
Test name
Test status
Simulation time 59921419 ps
CPU time 0.94 seconds
Started Jul 06 05:38:51 PM PDT 24
Finished Jul 06 05:38:52 PM PDT 24
Peak memory 223232 kb
Host smart-38f3042a-a42e-49d8-87ab-75c0b8057b39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590467024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3590467024
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.4273643205
Short name T794
Test name
Test status
Simulation time 718853110 ps
CPU time 3.91 seconds
Started Jul 06 05:38:45 PM PDT 24
Finished Jul 06 05:38:49 PM PDT 24
Peak memory 205012 kb
Host smart-74ecac26-6132-47de-8260-92015587107e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273643205 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.4273643205
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1810983072
Short name T454
Test name
Test status
Simulation time 146006539 ps
CPU time 0.8 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 204776 kb
Host smart-1efef295-cdb1-4c45-acfa-c3866c44685f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810983072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1810983072
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.117157579
Short name T1258
Test name
Test status
Simulation time 191154167 ps
CPU time 1.09 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:46 PM PDT 24
Peak memory 204812 kb
Host smart-ab3503b2-1d25-4c22-a55f-0d442328d7f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117157579 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.117157579
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.4171825187
Short name T1516
Test name
Test status
Simulation time 2413488750 ps
CPU time 2.81 seconds
Started Jul 06 05:38:50 PM PDT 24
Finished Jul 06 05:38:53 PM PDT 24
Peak memory 205072 kb
Host smart-b72f01bf-2846-4a04-974e-87b6acd1ff52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171825187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.4171825187
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.35949683
Short name T1333
Test name
Test status
Simulation time 138080168 ps
CPU time 1.17 seconds
Started Jul 06 05:38:50 PM PDT 24
Finished Jul 06 05:38:51 PM PDT 24
Peak memory 204828 kb
Host smart-81f3bce4-1d71-4c2b-a4d9-4987146b7599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949683 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.35949683
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.738513788
Short name T927
Test name
Test status
Simulation time 2084520099 ps
CPU time 2.98 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:48 PM PDT 24
Peak memory 205076 kb
Host smart-a091c5db-c9b1-48f6-bb6e-e95af518f720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738513788 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.738513788
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.475285393
Short name T1380
Test name
Test status
Simulation time 1597283794 ps
CPU time 7.61 seconds
Started Jul 06 05:38:46 PM PDT 24
Finished Jul 06 05:38:53 PM PDT 24
Peak memory 213296 kb
Host smart-39ba0141-d339-44fd-aa43-01affe979e98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475285393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.475285393
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.670545964
Short name T1031
Test name
Test status
Simulation time 8996709758 ps
CPU time 8.82 seconds
Started Jul 06 05:38:47 PM PDT 24
Finished Jul 06 05:38:56 PM PDT 24
Peak memory 399696 kb
Host smart-ba1ac073-35bb-472b-ba0f-01859bb63409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670545964 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.670545964
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.491082570
Short name T699
Test name
Test status
Simulation time 744065037 ps
CPU time 24.83 seconds
Started Jul 06 05:38:45 PM PDT 24
Finished Jul 06 05:39:11 PM PDT 24
Peak memory 205064 kb
Host smart-0a89b9d8-c4ef-4373-b683-61115ed38791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491082570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.491082570
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.185569660
Short name T228
Test name
Test status
Simulation time 4534910236 ps
CPU time 5.91 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:38:51 PM PDT 24
Peak memory 205060 kb
Host smart-52d9af46-512e-4e8f-ac82-e129e6633c3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185569660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.185569660
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.4024434482
Short name T601
Test name
Test status
Simulation time 38359653756 ps
CPU time 489.41 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 4532136 kb
Host smart-42ea5669-48e6-423a-88b8-74bf8becf4ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024434482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.4024434482
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3044959101
Short name T975
Test name
Test status
Simulation time 2391371986 ps
CPU time 55.12 seconds
Started Jul 06 05:38:44 PM PDT 24
Finished Jul 06 05:39:40 PM PDT 24
Peak memory 461032 kb
Host smart-a2fc7f51-bc1f-4cfa-b2ae-8e86b379e23c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044959101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3044959101
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1295036628
Short name T1474
Test name
Test status
Simulation time 1332910029 ps
CPU time 6.96 seconds
Started Jul 06 05:38:46 PM PDT 24
Finished Jul 06 05:38:53 PM PDT 24
Peak memory 219632 kb
Host smart-ef9e47d9-7f83-4c5f-8da1-bf7fcac18e8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295036628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1295036628
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.550202580
Short name T880
Test name
Test status
Simulation time 313393691 ps
CPU time 4.92 seconds
Started Jul 06 05:38:49 PM PDT 24
Finished Jul 06 05:38:54 PM PDT 24
Peak memory 205048 kb
Host smart-1ff7ce06-0662-4d38-964e-bc5f4be29ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550202580 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.550202580
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3850947644
Short name T637
Test name
Test status
Simulation time 15606989 ps
CPU time 0.65 seconds
Started Jul 06 05:46:00 PM PDT 24
Finished Jul 06 05:46:00 PM PDT 24
Peak memory 204636 kb
Host smart-8e93c574-5d7f-4bd4-a948-9783e74d24bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850947644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3850947644
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3680760422
Short name T971
Test name
Test status
Simulation time 366806578 ps
CPU time 6.42 seconds
Started Jul 06 05:45:56 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 222468 kb
Host smart-b90d0993-e976-46a1-9f8b-466ac8437a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680760422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3680760422
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1244090742
Short name T970
Test name
Test status
Simulation time 394878524 ps
CPU time 7.92 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:45:57 PM PDT 24
Peak memory 287320 kb
Host smart-7284e27f-3ef2-404d-a7cc-145015b3623a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244090742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1244090742
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1342964984
Short name T1317
Test name
Test status
Simulation time 11324032651 ps
CPU time 129.07 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:47:58 PM PDT 24
Peak memory 659480 kb
Host smart-c7fc6062-8aee-43f6-9614-ee3a08fd14b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342964984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1342964984
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1640260021
Short name T327
Test name
Test status
Simulation time 2039218730 ps
CPU time 125.94 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:47:55 PM PDT 24
Peak memory 498656 kb
Host smart-e194835f-0a64-4ef3-a5ae-f588e4acf241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640260021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1640260021
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.548043364
Short name T727
Test name
Test status
Simulation time 88376277 ps
CPU time 0.96 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:45:50 PM PDT 24
Peak memory 204772 kb
Host smart-9f000e68-4e74-4bdb-aa2d-6b1327159927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548043364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.548043364
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.730484493
Short name T485
Test name
Test status
Simulation time 225862291 ps
CPU time 6.15 seconds
Started Jul 06 05:45:48 PM PDT 24
Finished Jul 06 05:45:54 PM PDT 24
Peak memory 221136 kb
Host smart-14e45563-ac04-4401-9c3e-dc49f763f1a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730484493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
730484493
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3887305800
Short name T99
Test name
Test status
Simulation time 5055041122 ps
CPU time 123.84 seconds
Started Jul 06 05:45:49 PM PDT 24
Finished Jul 06 05:47:53 PM PDT 24
Peak memory 1407612 kb
Host smart-ca4ceaa8-8c5b-4385-922e-64230b1fef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887305800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3887305800
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.225096691
Short name T1402
Test name
Test status
Simulation time 634170407 ps
CPU time 4.59 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 205076 kb
Host smart-bde71593-c158-4391-8ea6-0049c7ff0b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225096691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.225096691
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3053622073
Short name T62
Test name
Test status
Simulation time 5232572623 ps
CPU time 28.98 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:46:26 PM PDT 24
Peak memory 361296 kb
Host smart-de7f0fbf-3e7e-4429-9136-78b9dfe1b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053622073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3053622073
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2991796504
Short name T121
Test name
Test status
Simulation time 27394461 ps
CPU time 0.71 seconds
Started Jul 06 05:45:48 PM PDT 24
Finished Jul 06 05:45:49 PM PDT 24
Peak memory 204688 kb
Host smart-5be48732-580e-4320-aca9-c67e36ff0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991796504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2991796504
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2514405979
Short name T557
Test name
Test status
Simulation time 3343710020 ps
CPU time 34.54 seconds
Started Jul 06 05:45:47 PM PDT 24
Finished Jul 06 05:46:22 PM PDT 24
Peak memory 564196 kb
Host smart-a2302152-8e16-462e-86f6-9c11bfceb1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514405979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2514405979
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.3719340338
Short name T288
Test name
Test status
Simulation time 444434995 ps
CPU time 19.87 seconds
Started Jul 06 05:45:52 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 285536 kb
Host smart-9236afe2-f42d-422f-83e2-66ecaca4c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719340338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3719340338
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3605149828
Short name T775
Test name
Test status
Simulation time 1411326115 ps
CPU time 21.68 seconds
Started Jul 06 05:45:47 PM PDT 24
Finished Jul 06 05:46:09 PM PDT 24
Peak memory 268836 kb
Host smart-b63e40df-20a6-4acc-b267-5792f881c234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605149828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3605149828
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3313459697
Short name T1407
Test name
Test status
Simulation time 17435476756 ps
CPU time 376.39 seconds
Started Jul 06 05:45:53 PM PDT 24
Finished Jul 06 05:52:10 PM PDT 24
Peak memory 583184 kb
Host smart-80ec84c5-aa31-4524-a41d-a70c1896e6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313459697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3313459697
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1301920394
Short name T886
Test name
Test status
Simulation time 1073698812 ps
CPU time 18.89 seconds
Started Jul 06 05:45:52 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 219328 kb
Host smart-2e918850-7b5c-4b3d-bdd9-03facd37774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301920394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1301920394
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2724458615
Short name T1364
Test name
Test status
Simulation time 2987254183 ps
CPU time 4.01 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:45:59 PM PDT 24
Peak memory 213336 kb
Host smart-4e48063a-d684-4d51-a205-67cbbd019ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724458615 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2724458615
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3444686787
Short name T268
Test name
Test status
Simulation time 1287281176 ps
CPU time 1.51 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:45:56 PM PDT 24
Peak memory 205016 kb
Host smart-4a8feb91-b8d1-40ca-9aa3-b892ecafa178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444686787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3444686787
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.818747578
Short name T1471
Test name
Test status
Simulation time 214273515 ps
CPU time 1.35 seconds
Started Jul 06 05:45:53 PM PDT 24
Finished Jul 06 05:45:55 PM PDT 24
Peak memory 204972 kb
Host smart-23ac4ee6-6bfd-4008-9318-69265fd9801c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818747578 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.818747578
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.1784142804
Short name T1192
Test name
Test status
Simulation time 421169410 ps
CPU time 2.55 seconds
Started Jul 06 05:45:59 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 205032 kb
Host smart-de1b10a8-e15d-48d7-85db-04a2ce9e32c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784142804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.1784142804
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.997988374
Short name T1039
Test name
Test status
Simulation time 143226489 ps
CPU time 1.19 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:45:58 PM PDT 24
Peak memory 204748 kb
Host smart-4cd045b1-71c2-4b0c-ac46-7f17016ec24a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997988374 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.997988374
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3574199712
Short name T616
Test name
Test status
Simulation time 290543955 ps
CPU time 2.69 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:45:57 PM PDT 24
Peak memory 205068 kb
Host smart-e811f908-eff8-44cd-93d0-17a140aea77d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574199712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3574199712
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2419274204
Short name T868
Test name
Test status
Simulation time 14136229238 ps
CPU time 40.14 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:46:34 PM PDT 24
Peak memory 903576 kb
Host smart-5641c52c-43de-4a76-8d9e-16ce8e68c05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419274204 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2419274204
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.913382162
Short name T1243
Test name
Test status
Simulation time 3218103767 ps
CPU time 34.25 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:46:28 PM PDT 24
Peak memory 205104 kb
Host smart-229f92b6-c42d-465d-bbda-3049f3e2887b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913382162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.913382162
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3914349585
Short name T493
Test name
Test status
Simulation time 1102095888 ps
CPU time 44.71 seconds
Started Jul 06 05:45:55 PM PDT 24
Finished Jul 06 05:46:40 PM PDT 24
Peak memory 204916 kb
Host smart-8bf7d891-b44d-4693-bd64-9b18e237442a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914349585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3914349585
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3812974386
Short name T1393
Test name
Test status
Simulation time 16643299084 ps
CPU time 11.57 seconds
Started Jul 06 05:45:54 PM PDT 24
Finished Jul 06 05:46:06 PM PDT 24
Peak memory 205080 kb
Host smart-4f893dc4-de11-481a-a9e7-3af5b73c9f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812974386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3812974386
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.680420055
Short name T564
Test name
Test status
Simulation time 1370092857 ps
CPU time 13.96 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:46:11 PM PDT 24
Peak memory 423300 kb
Host smart-8d4a06f9-9ef7-4890-88f8-1564f283fa98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680420055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.680420055
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2909436236
Short name T546
Test name
Test status
Simulation time 5779581012 ps
CPU time 7.65 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:46:05 PM PDT 24
Peak memory 217580 kb
Host smart-cbcf44d8-0eab-4f00-9126-48bce6d3ccd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909436236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2909436236
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.1613756146
Short name T978
Test name
Test status
Simulation time 68445540 ps
CPU time 1.54 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:45:59 PM PDT 24
Peak memory 205020 kb
Host smart-7d8887a0-b92a-45cb-b955-5874705440f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613756146 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.1613756146
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2514312335
Short name T659
Test name
Test status
Simulation time 17924172 ps
CPU time 0.66 seconds
Started Jul 06 05:46:08 PM PDT 24
Finished Jul 06 05:46:09 PM PDT 24
Peak memory 204624 kb
Host smart-f23128b4-74eb-4a1d-8df7-fb6cfda38d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514312335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2514312335
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.4228935253
Short name T51
Test name
Test status
Simulation time 90862000 ps
CPU time 2.46 seconds
Started Jul 06 05:46:05 PM PDT 24
Finished Jul 06 05:46:08 PM PDT 24
Peak memory 213264 kb
Host smart-46c1e6d5-fae0-4f20-bfdb-5647983a51fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228935253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.4228935253
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3422445130
Short name T1368
Test name
Test status
Simulation time 948738139 ps
CPU time 8.73 seconds
Started Jul 06 05:45:59 PM PDT 24
Finished Jul 06 05:46:08 PM PDT 24
Peak memory 306252 kb
Host smart-15811edf-14ca-4e76-bc1b-c1d275ecfcb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422445130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3422445130
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3824517541
Short name T384
Test name
Test status
Simulation time 2993584327 ps
CPU time 120.14 seconds
Started Jul 06 05:45:58 PM PDT 24
Finished Jul 06 05:47:59 PM PDT 24
Peak memory 951096 kb
Host smart-456944bd-9a11-4457-ad74-322aee4371fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824517541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3824517541
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3689975492
Short name T446
Test name
Test status
Simulation time 9525805035 ps
CPU time 35.13 seconds
Started Jul 06 05:45:58 PM PDT 24
Finished Jul 06 05:46:33 PM PDT 24
Peak memory 487536 kb
Host smart-23d5509d-a644-40fc-8be9-853d12a52f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689975492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3689975492
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.4253380103
Short name T1119
Test name
Test status
Simulation time 326796672 ps
CPU time 0.96 seconds
Started Jul 06 05:45:59 PM PDT 24
Finished Jul 06 05:46:00 PM PDT 24
Peak memory 204764 kb
Host smart-49a67197-0755-4acb-92b3-7944d99923a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253380103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.4253380103
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3931187027
Short name T445
Test name
Test status
Simulation time 291217227 ps
CPU time 3.9 seconds
Started Jul 06 05:46:00 PM PDT 24
Finished Jul 06 05:46:04 PM PDT 24
Peak memory 224576 kb
Host smart-13f0f0bb-2b97-499e-8489-2592b829b9db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931187027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3931187027
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.406524923
Short name T773
Test name
Test status
Simulation time 2930819953 ps
CPU time 81.45 seconds
Started Jul 06 05:46:00 PM PDT 24
Finished Jul 06 05:47:21 PM PDT 24
Peak memory 935668 kb
Host smart-0fb3c3ec-a72d-40a4-992c-f65ed0187800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406524923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.406524923
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2366529658
Short name T1366
Test name
Test status
Simulation time 434535766 ps
CPU time 17.76 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:46:25 PM PDT 24
Peak memory 205084 kb
Host smart-20f18975-4038-4b1d-a07d-7449c1befba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366529658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2366529658
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2748541538
Short name T1311
Test name
Test status
Simulation time 8909073092 ps
CPU time 112.66 seconds
Started Jul 06 05:46:10 PM PDT 24
Finished Jul 06 05:48:03 PM PDT 24
Peak memory 503080 kb
Host smart-fe2d67db-e1bc-405b-a7d5-49155d54cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748541538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2748541538
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.499357843
Short name T862
Test name
Test status
Simulation time 92089499 ps
CPU time 0.7 seconds
Started Jul 06 05:45:58 PM PDT 24
Finished Jul 06 05:45:59 PM PDT 24
Peak memory 204740 kb
Host smart-90fdcde0-4951-4001-96ea-94a11d22ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499357843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.499357843
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.241862875
Short name T552
Test name
Test status
Simulation time 519335924 ps
CPU time 5.63 seconds
Started Jul 06 05:45:57 PM PDT 24
Finished Jul 06 05:46:03 PM PDT 24
Peak memory 227592 kb
Host smart-dd76c1f6-51a9-4e14-8ee0-bdae357adc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241862875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.241862875
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.5384279
Short name T1310
Test name
Test status
Simulation time 1700784346 ps
CPU time 2.33 seconds
Started Jul 06 05:46:04 PM PDT 24
Finished Jul 06 05:46:07 PM PDT 24
Peak memory 204952 kb
Host smart-ce4346a6-1191-47f7-89be-437d948588ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5384279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.5384279
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.691765630
Short name T297
Test name
Test status
Simulation time 2655628852 ps
CPU time 24.74 seconds
Started Jul 06 05:46:00 PM PDT 24
Finished Jul 06 05:46:25 PM PDT 24
Peak memory 361352 kb
Host smart-e7efd6f4-7ddf-4239-b1af-0af5da0bbb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691765630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.691765630
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2597821138
Short name T186
Test name
Test status
Simulation time 33417252822 ps
CPU time 1208.89 seconds
Started Jul 06 05:46:04 PM PDT 24
Finished Jul 06 06:06:13 PM PDT 24
Peak memory 3210508 kb
Host smart-4b264ab0-c473-4d04-a50c-06e73fefff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597821138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2597821138
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.220918597
Short name T712
Test name
Test status
Simulation time 826747314 ps
CPU time 38.19 seconds
Started Jul 06 05:46:04 PM PDT 24
Finished Jul 06 05:46:42 PM PDT 24
Peak memory 213224 kb
Host smart-71f940f3-6a33-4e4a-9003-5207dcbbb866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220918597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.220918597
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1282301929
Short name T1241
Test name
Test status
Simulation time 479150075 ps
CPU time 2.81 seconds
Started Jul 06 05:46:08 PM PDT 24
Finished Jul 06 05:46:11 PM PDT 24
Peak memory 204960 kb
Host smart-4faa5668-5883-4701-821d-75f283a06e0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282301929 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1282301929
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.770921000
Short name T530
Test name
Test status
Simulation time 708858387 ps
CPU time 1.4 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:46:08 PM PDT 24
Peak memory 205000 kb
Host smart-99041ba5-3a55-4c61-b1a3-16a538455e7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770921000 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.770921000
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2528067925
Short name T368
Test name
Test status
Simulation time 171542153 ps
CPU time 1.12 seconds
Started Jul 06 05:46:08 PM PDT 24
Finished Jul 06 05:46:09 PM PDT 24
Peak memory 204776 kb
Host smart-80c3db56-cbcc-45b5-aefb-5830d5fa1f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528067925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2528067925
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1543226274
Short name T558
Test name
Test status
Simulation time 578110590 ps
CPU time 1.67 seconds
Started Jul 06 05:46:10 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 204784 kb
Host smart-15a77f5d-7c01-4a7c-93c1-f8d9e2ae1564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543226274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1543226274
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3914796853
Short name T604
Test name
Test status
Simulation time 89647041 ps
CPU time 0.9 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:46:09 PM PDT 24
Peak memory 204828 kb
Host smart-2492207a-50f7-4819-8750-d96aecce43f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914796853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3914796853
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.4151678886
Short name T1428
Test name
Test status
Simulation time 4011608269 ps
CPU time 3.91 seconds
Started Jul 06 05:46:10 PM PDT 24
Finished Jul 06 05:46:14 PM PDT 24
Peak memory 205140 kb
Host smart-36189e7d-8194-4a18-90c6-07d55a3e3a88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151678886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.4151678886
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3594159837
Short name T1372
Test name
Test status
Simulation time 1124435737 ps
CPU time 6.29 seconds
Started Jul 06 05:46:04 PM PDT 24
Finished Jul 06 05:46:11 PM PDT 24
Peak memory 218664 kb
Host smart-ea231e18-9f18-42d6-b605-a0175dd0042c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594159837 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3594159837
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.523351318
Short name T780
Test name
Test status
Simulation time 4632661083 ps
CPU time 46.96 seconds
Started Jul 06 05:46:16 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 1235340 kb
Host smart-0c86516b-46c6-4625-a565-9efa4b9f13d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523351318 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.523351318
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.4201727579
Short name T1259
Test name
Test status
Simulation time 5523030415 ps
CPU time 19.78 seconds
Started Jul 06 05:46:06 PM PDT 24
Finished Jul 06 05:46:26 PM PDT 24
Peak memory 205076 kb
Host smart-3ce1a71e-f8cd-4832-91e7-9396a652e71b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201727579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.4201727579
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.4271660186
Short name T463
Test name
Test status
Simulation time 925384847 ps
CPU time 19.22 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:46:26 PM PDT 24
Peak memory 205040 kb
Host smart-95727952-d6ff-4117-97af-e8985f6c89b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271660186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.4271660186
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1356090544
Short name T1108
Test name
Test status
Simulation time 50476667312 ps
CPU time 1145.16 seconds
Started Jul 06 05:46:05 PM PDT 24
Finished Jul 06 06:05:11 PM PDT 24
Peak memory 7755492 kb
Host smart-a0e27b51-1e29-4223-8c77-67d2e55e6c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356090544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1356090544
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2130852295
Short name T10
Test name
Test status
Simulation time 3609204535 ps
CPU time 204 seconds
Started Jul 06 05:46:03 PM PDT 24
Finished Jul 06 05:49:27 PM PDT 24
Peak memory 1032768 kb
Host smart-cdbac7bd-5274-47f4-9f32-aaf039ae0abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130852295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2130852295
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1038683157
Short name T70
Test name
Test status
Simulation time 1456015465 ps
CPU time 7.07 seconds
Started Jul 06 05:46:04 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 213288 kb
Host smart-6b10d8b2-9e1d-4f4f-b3f4-190153ae5db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038683157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1038683157
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.445337050
Short name T512
Test name
Test status
Simulation time 500174469 ps
CPU time 6.55 seconds
Started Jul 06 05:46:11 PM PDT 24
Finished Jul 06 05:46:18 PM PDT 24
Peak memory 205032 kb
Host smart-f8ed4251-3b9a-41ff-84fa-3ed2614d193c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445337050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.445337050
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.973880590
Short name T1525
Test name
Test status
Simulation time 40243335 ps
CPU time 0.61 seconds
Started Jul 06 05:46:20 PM PDT 24
Finished Jul 06 05:46:21 PM PDT 24
Peak memory 204496 kb
Host smart-d68f6ded-8ca7-4855-8ce4-bca26614dd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973880590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.973880590
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3961975691
Short name T1201
Test name
Test status
Simulation time 225474365 ps
CPU time 1.49 seconds
Started Jul 06 05:46:08 PM PDT 24
Finished Jul 06 05:46:10 PM PDT 24
Peak memory 213272 kb
Host smart-c21dd3f3-bcea-45b4-a71f-97e85f7adbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961975691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3961975691
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3436113756
Short name T1044
Test name
Test status
Simulation time 2092491198 ps
CPU time 10.18 seconds
Started Jul 06 05:46:14 PM PDT 24
Finished Jul 06 05:46:24 PM PDT 24
Peak memory 308348 kb
Host smart-7f450962-98ac-46a2-be71-f2a37c34f555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436113756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3436113756
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1232235427
Short name T1346
Test name
Test status
Simulation time 17540757279 ps
CPU time 50.41 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 586800 kb
Host smart-1fc04c30-833d-4be4-b503-20e5201f88a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232235427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1232235427
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3889355235
Short name T1000
Test name
Test status
Simulation time 9726818951 ps
CPU time 68.92 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:47:16 PM PDT 24
Peak memory 701656 kb
Host smart-2b984db2-73aa-4c08-bf0a-454cc1bf35d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889355235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3889355235
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3978968951
Short name T1137
Test name
Test status
Simulation time 108350400 ps
CPU time 1.08 seconds
Started Jul 06 05:46:08 PM PDT 24
Finished Jul 06 05:46:09 PM PDT 24
Peak memory 204772 kb
Host smart-12e2baa1-29fb-4a1e-93ca-9a16b1c1c2a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978968951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3978968951
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3936414152
Short name T498
Test name
Test status
Simulation time 199958701 ps
CPU time 3.88 seconds
Started Jul 06 05:46:11 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 231852 kb
Host smart-b2d7b8b6-d1ce-40bf-9730-3ca35a2642d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936414152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3936414152
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3809345712
Short name T882
Test name
Test status
Simulation time 21270232004 ps
CPU time 404.45 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:52:54 PM PDT 24
Peak memory 1509996 kb
Host smart-f187981d-18de-4927-8932-62514048db4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809345712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3809345712
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.700665
Short name T1227
Test name
Test status
Simulation time 4486555729 ps
CPU time 13.36 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:29 PM PDT 24
Peak memory 205088 kb
Host smart-c3d67b21-7339-4caf-8a47-b39b424e1c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.700665
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3997849456
Short name T284
Test name
Test status
Simulation time 9032674355 ps
CPU time 22.59 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 310692 kb
Host smart-e165fe6b-da37-4b4e-876c-a945c4aca187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997849456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3997849456
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2097852023
Short name T224
Test name
Test status
Simulation time 18504452 ps
CPU time 0.66 seconds
Started Jul 06 05:46:14 PM PDT 24
Finished Jul 06 05:46:15 PM PDT 24
Peak memory 204692 kb
Host smart-ee2194a6-854c-4fc1-86e3-1c98d0b413ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097852023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2097852023
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.4098676716
Short name T1391
Test name
Test status
Simulation time 6946073458 ps
CPU time 14.2 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:46:24 PM PDT 24
Peak memory 354512 kb
Host smart-84f31c3f-0e90-4201-a5b9-f958ea6dcbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098676716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.4098676716
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1781334513
Short name T595
Test name
Test status
Simulation time 4289878340 ps
CPU time 50.93 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:47:01 PM PDT 24
Peak memory 326644 kb
Host smart-79d1a36b-1625-494a-b8a4-9b6d3f793d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781334513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1781334513
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3902467256
Short name T50
Test name
Test status
Simulation time 11686165005 ps
CPU time 473.29 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:54:03 PM PDT 24
Peak memory 1588512 kb
Host smart-146af01a-2341-4575-b35c-de54ebbce27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902467256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3902467256
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2259484903
Short name T413
Test name
Test status
Simulation time 877909039 ps
CPU time 19.94 seconds
Started Jul 06 05:46:09 PM PDT 24
Finished Jul 06 05:46:29 PM PDT 24
Peak memory 213212 kb
Host smart-70b96cd2-902a-4ac2-b7bc-e1339d19b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259484903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2259484903
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1865863043
Short name T736
Test name
Test status
Simulation time 1067977387 ps
CPU time 3.23 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 205020 kb
Host smart-a3ae92a2-2c2e-43d5-98d7-8877b5238972
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865863043 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1865863043
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1364949097
Short name T1423
Test name
Test status
Simulation time 211570078 ps
CPU time 0.73 seconds
Started Jul 06 05:46:14 PM PDT 24
Finished Jul 06 05:46:15 PM PDT 24
Peak memory 204724 kb
Host smart-3c12eab6-b76c-4cac-9c71-0f6c531c0494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364949097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1364949097
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3029528584
Short name T952
Test name
Test status
Simulation time 249505909 ps
CPU time 1.52 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:16 PM PDT 24
Peak memory 205020 kb
Host smart-85e2de70-91fd-402f-82f8-7055da1b1e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029528584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3029528584
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1208701274
Short name T1266
Test name
Test status
Simulation time 874804829 ps
CPU time 2.47 seconds
Started Jul 06 05:46:16 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 205060 kb
Host smart-cf93bc66-e55e-4fa0-909e-73e9745e9ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208701274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1208701274
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3533869492
Short name T352
Test name
Test status
Simulation time 842801048 ps
CPU time 1.01 seconds
Started Jul 06 05:46:14 PM PDT 24
Finished Jul 06 05:46:15 PM PDT 24
Peak memory 204836 kb
Host smart-142536f4-fce2-4f8c-94d1-beee95ac33cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533869492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3533869492
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1369231829
Short name T741
Test name
Test status
Simulation time 881307371 ps
CPU time 5.51 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:21 PM PDT 24
Peak memory 216832 kb
Host smart-b0a4339f-6471-414f-9e7f-4473b9163841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369231829 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1369231829
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3166628322
Short name T692
Test name
Test status
Simulation time 4670345166 ps
CPU time 3.57 seconds
Started Jul 06 05:46:14 PM PDT 24
Finished Jul 06 05:46:17 PM PDT 24
Peak memory 205080 kb
Host smart-9b837778-9420-40fb-8959-8e7394a5c6cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166628322 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3166628322
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1690729399
Short name T145
Test name
Test status
Simulation time 2357453854 ps
CPU time 15.47 seconds
Started Jul 06 05:46:07 PM PDT 24
Finished Jul 06 05:46:22 PM PDT 24
Peak memory 205060 kb
Host smart-5bf982d0-e6e5-4b9f-9f12-d23e34086c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690729399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1690729399
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.1120210793
Short name T8
Test name
Test status
Simulation time 7466509388 ps
CPU time 34.13 seconds
Started Jul 06 05:46:15 PM PDT 24
Finished Jul 06 05:46:49 PM PDT 24
Peak memory 227448 kb
Host smart-3f0911c6-fee7-42e4-862b-f4252b3213c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120210793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.1120210793
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2045404603
Short name T484
Test name
Test status
Simulation time 9428217233 ps
CPU time 12.18 seconds
Started Jul 06 05:46:13 PM PDT 24
Finished Jul 06 05:46:25 PM PDT 24
Peak memory 205056 kb
Host smart-385605dd-611e-40d1-bfc1-1861e5883a0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045404603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2045404603
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1581581782
Short name T1088
Test name
Test status
Simulation time 9162530094 ps
CPU time 6.8 seconds
Started Jul 06 05:46:13 PM PDT 24
Finished Jul 06 05:46:20 PM PDT 24
Peak memory 221412 kb
Host smart-271bd9c6-be55-46c5-baa6-85f0810fd9d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581581782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1581581782
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.3075789258
Short name T778
Test name
Test status
Simulation time 225586138 ps
CPU time 3.77 seconds
Started Jul 06 05:46:16 PM PDT 24
Finished Jul 06 05:46:20 PM PDT 24
Peak memory 205084 kb
Host smart-121b7c70-5495-4fc6-a34a-f60bd8154e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075789258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3075789258
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.901591290
Short name T555
Test name
Test status
Simulation time 42882967 ps
CPU time 0.62 seconds
Started Jul 06 05:46:26 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 204552 kb
Host smart-34df44f6-e4a3-45d9-8a68-737e6ce4ccdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901591290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.901591290
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2701360823
Short name T49
Test name
Test status
Simulation time 132669594 ps
CPU time 1.18 seconds
Started Jul 06 05:46:16 PM PDT 24
Finished Jul 06 05:46:17 PM PDT 24
Peak memory 213264 kb
Host smart-1f41bbf0-9cb9-4f15-aed9-fb1a46a37a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701360823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2701360823
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1680899282
Short name T653
Test name
Test status
Simulation time 3336072322 ps
CPU time 24.14 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:46:42 PM PDT 24
Peak memory 298796 kb
Host smart-ef5572fe-0dee-44e2-8c94-a64c26ac8321
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680899282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1680899282
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.725120048
Short name T462
Test name
Test status
Simulation time 9395666590 ps
CPU time 66.62 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 525312 kb
Host smart-22942f3d-c992-4347-812a-883ed826bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725120048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.725120048
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.4164021449
Short name T154
Test name
Test status
Simulation time 10158776354 ps
CPU time 94.98 seconds
Started Jul 06 05:46:20 PM PDT 24
Finished Jul 06 05:47:55 PM PDT 24
Peak memory 816524 kb
Host smart-cab49456-7695-42b7-9e5a-f5f35014a61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164021449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4164021449
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1528936958
Short name T1385
Test name
Test status
Simulation time 160684224 ps
CPU time 1.23 seconds
Started Jul 06 05:46:17 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 205028 kb
Host smart-8e3da79c-9e03-4adc-bf04-ebe51cf6acd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528936958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1528936958
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3258616674
Short name T894
Test name
Test status
Simulation time 691192159 ps
CPU time 8.21 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 229340 kb
Host smart-54905cbf-f5f8-4431-89b9-f6b1d000b369
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258616674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3258616674
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2457708469
Short name T793
Test name
Test status
Simulation time 3570120846 ps
CPU time 68.04 seconds
Started Jul 06 05:46:17 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 986040 kb
Host smart-97ece482-20d9-4fe2-ae05-e8446aaa978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457708469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2457708469
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.473920972
Short name T1239
Test name
Test status
Simulation time 539913218 ps
CPU time 11.84 seconds
Started Jul 06 05:46:23 PM PDT 24
Finished Jul 06 05:46:35 PM PDT 24
Peak memory 205044 kb
Host smart-1647bf94-386b-4de1-bc37-3bbb9c892e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473920972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.473920972
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.4022293951
Short name T1420
Test name
Test status
Simulation time 2172822832 ps
CPU time 113.55 seconds
Started Jul 06 05:46:23 PM PDT 24
Finished Jul 06 05:48:17 PM PDT 24
Peak memory 496444 kb
Host smart-3165b0b2-9a1c-494f-b3fa-04216ca5f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022293951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4022293951
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3328457722
Short name T1219
Test name
Test status
Simulation time 33483172 ps
CPU time 0.71 seconds
Started Jul 06 05:46:19 PM PDT 24
Finished Jul 06 05:46:20 PM PDT 24
Peak memory 204708 kb
Host smart-2a08b3ac-81a0-47a2-bb51-942f5122cc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328457722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3328457722
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3724552356
Short name T651
Test name
Test status
Simulation time 2171547958 ps
CPU time 22.22 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:46:41 PM PDT 24
Peak memory 205128 kb
Host smart-6324bcb6-cec0-4992-a9e1-e43affe6150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724552356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3724552356
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1116666213
Short name T885
Test name
Test status
Simulation time 25103624495 ps
CPU time 67 seconds
Started Jul 06 05:46:19 PM PDT 24
Finished Jul 06 05:47:26 PM PDT 24
Peak memory 629936 kb
Host smart-fb2c3937-40fc-40df-b707-03e23eb88583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116666213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1116666213
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.86273055
Short name T934
Test name
Test status
Simulation time 1198185975 ps
CPU time 58.13 seconds
Started Jul 06 05:46:19 PM PDT 24
Finished Jul 06 05:47:17 PM PDT 24
Peak memory 292312 kb
Host smart-ae6bcd32-335c-48ee-8a27-f9cd2c265a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86273055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.86273055
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3762169153
Short name T1246
Test name
Test status
Simulation time 772561236 ps
CPU time 12.59 seconds
Started Jul 06 05:46:17 PM PDT 24
Finished Jul 06 05:46:30 PM PDT 24
Peak memory 213204 kb
Host smart-1719f3ad-86d4-414b-a8a5-4274f187946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762169153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3762169153
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1828875922
Short name T1202
Test name
Test status
Simulation time 682760861 ps
CPU time 3.8 seconds
Started Jul 06 05:46:24 PM PDT 24
Finished Jul 06 05:46:28 PM PDT 24
Peak memory 213236 kb
Host smart-e2497cfc-cca1-4b1f-8203-693ec46917b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828875922 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1828875922
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.376461897
Short name T931
Test name
Test status
Simulation time 302342328 ps
CPU time 0.84 seconds
Started Jul 06 05:46:24 PM PDT 24
Finished Jul 06 05:46:25 PM PDT 24
Peak memory 204824 kb
Host smart-2528ccf0-a68b-4139-8e29-3735a45477fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376461897 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.376461897
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3579970495
Short name T841
Test name
Test status
Simulation time 408047678 ps
CPU time 1.43 seconds
Started Jul 06 05:46:22 PM PDT 24
Finished Jul 06 05:46:24 PM PDT 24
Peak memory 205520 kb
Host smart-030540a4-654a-4ff4-b1ca-17693521110b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579970495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3579970495
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.3608298280
Short name T1189
Test name
Test status
Simulation time 4223055681 ps
CPU time 2.21 seconds
Started Jul 06 05:46:27 PM PDT 24
Finished Jul 06 05:46:30 PM PDT 24
Peak memory 205128 kb
Host smart-60e2fb3f-d789-4efc-88e6-a4f73204ca9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608298280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.3608298280
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.413038056
Short name T389
Test name
Test status
Simulation time 79316014 ps
CPU time 0.95 seconds
Started Jul 06 05:46:27 PM PDT 24
Finished Jul 06 05:46:28 PM PDT 24
Peak memory 204780 kb
Host smart-c57288ab-da00-4f55-a9d9-cfbb91727c57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413038056 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.413038056
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1117687689
Short name T1403
Test name
Test status
Simulation time 664793499 ps
CPU time 2.34 seconds
Started Jul 06 05:46:21 PM PDT 24
Finished Jul 06 05:46:24 PM PDT 24
Peak memory 205056 kb
Host smart-19a97583-d716-431b-bd8d-0902a567ffd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117687689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1117687689
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3426720385
Short name T1361
Test name
Test status
Simulation time 1412673233 ps
CPU time 7.29 seconds
Started Jul 06 05:46:24 PM PDT 24
Finished Jul 06 05:46:31 PM PDT 24
Peak memory 204996 kb
Host smart-bad5f5c3-34d3-4549-84d4-e71c0a691230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426720385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3426720385
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.503728991
Short name T1416
Test name
Test status
Simulation time 19851672081 ps
CPU time 384.54 seconds
Started Jul 06 05:46:22 PM PDT 24
Finished Jul 06 05:52:47 PM PDT 24
Peak memory 4641672 kb
Host smart-eb176f32-ca75-4160-a5d1-be8021f00f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503728991 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.503728991
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3334686406
Short name T821
Test name
Test status
Simulation time 1446283237 ps
CPU time 57.71 seconds
Started Jul 06 05:46:19 PM PDT 24
Finished Jul 06 05:47:17 PM PDT 24
Peak memory 205048 kb
Host smart-4b64fed3-0947-4890-a9a2-f65aa0ec64b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334686406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3334686406
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3520802061
Short name T331
Test name
Test status
Simulation time 3230577033 ps
CPU time 13.01 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:46:32 PM PDT 24
Peak memory 214532 kb
Host smart-974cc050-03ba-4d45-bb38-75ba650111d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520802061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3520802061
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1912319056
Short name T1075
Test name
Test status
Simulation time 7646526910 ps
CPU time 14.14 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:46:32 PM PDT 24
Peak memory 205096 kb
Host smart-423f08d9-3013-4750-a7df-3d82ad6f4da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912319056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1912319056
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2346076374
Short name T475
Test name
Test status
Simulation time 3596909288 ps
CPU time 60.03 seconds
Started Jul 06 05:46:18 PM PDT 24
Finished Jul 06 05:47:19 PM PDT 24
Peak memory 827628 kb
Host smart-28bab0f1-f81e-4f27-b5f2-ae873534865c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346076374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2346076374
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2166308284
Short name T655
Test name
Test status
Simulation time 5441923872 ps
CPU time 7.01 seconds
Started Jul 06 05:46:23 PM PDT 24
Finished Jul 06 05:46:31 PM PDT 24
Peak memory 213300 kb
Host smart-5c0773e8-74a9-4bda-a1a6-6337afa27f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166308284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2166308284
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.825155972
Short name T423
Test name
Test status
Simulation time 286259179 ps
CPU time 4.76 seconds
Started Jul 06 05:46:26 PM PDT 24
Finished Jul 06 05:46:31 PM PDT 24
Peak memory 205092 kb
Host smart-0573610c-bb39-49ed-ac6b-b29c86ba95b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825155972 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.825155972
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2319521503
Short name T884
Test name
Test status
Simulation time 15142528 ps
CPU time 0.67 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:46:39 PM PDT 24
Peak memory 204612 kb
Host smart-8effceed-7f7a-4adf-839b-931af9bc8cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319521503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2319521503
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1289850565
Short name T523
Test name
Test status
Simulation time 147209131 ps
CPU time 2.83 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:46:37 PM PDT 24
Peak memory 232996 kb
Host smart-4e7a290a-e078-473e-985a-5e3e6281368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289850565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1289850565
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.828432945
Short name T325
Test name
Test status
Simulation time 3752372723 ps
CPU time 4.79 seconds
Started Jul 06 05:46:28 PM PDT 24
Finished Jul 06 05:46:34 PM PDT 24
Peak memory 247060 kb
Host smart-57595a6a-41a7-4064-8003-ddc0e5fb5cbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828432945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.828432945
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.893649251
Short name T1459
Test name
Test status
Simulation time 7178123397 ps
CPU time 34.88 seconds
Started Jul 06 05:46:28 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 270224 kb
Host smart-35f68591-08ff-43c5-80bb-fc77027c677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893649251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.893649251
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1777044226
Short name T574
Test name
Test status
Simulation time 2390428881 ps
CPU time 65.96 seconds
Started Jul 06 05:46:27 PM PDT 24
Finished Jul 06 05:47:33 PM PDT 24
Peak memory 732552 kb
Host smart-48dd6955-9d9b-4957-a150-83042a2fe923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777044226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1777044226
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1700915875
Short name T771
Test name
Test status
Simulation time 194355386 ps
CPU time 0.97 seconds
Started Jul 06 05:46:26 PM PDT 24
Finished Jul 06 05:46:28 PM PDT 24
Peak memory 204772 kb
Host smart-615d7e6e-cd71-4cf6-86f6-5a1186a82b76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700915875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1700915875
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3339033471
Short name T1235
Test name
Test status
Simulation time 1066119875 ps
CPU time 5.25 seconds
Started Jul 06 05:46:29 PM PDT 24
Finished Jul 06 05:46:35 PM PDT 24
Peak memory 204892 kb
Host smart-e73113e2-bd67-4b91-8355-e4c8fb4b322f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339033471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3339033471
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3336842778
Short name T1101
Test name
Test status
Simulation time 8629491425 ps
CPU time 315.36 seconds
Started Jul 06 05:46:26 PM PDT 24
Finished Jul 06 05:51:41 PM PDT 24
Peak memory 1261760 kb
Host smart-5ee0b661-b136-4b9e-a8b0-23cd5e0f093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336842778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3336842778
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.774324585
Short name T1003
Test name
Test status
Simulation time 1622759628 ps
CPU time 16.73 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 205064 kb
Host smart-165c2353-a588-4d04-8ac4-1e21d5fa7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774324585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.774324585
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2239716941
Short name T576
Test name
Test status
Simulation time 6424131227 ps
CPU time 31.35 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:47:10 PM PDT 24
Peak memory 367300 kb
Host smart-ce5a0138-1e11-4236-9785-a8bd09b0351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239716941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2239716941
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.482409193
Short name T81
Test name
Test status
Simulation time 108422140 ps
CPU time 0.68 seconds
Started Jul 06 05:46:28 PM PDT 24
Finished Jul 06 05:46:29 PM PDT 24
Peak memory 204752 kb
Host smart-1ed7f43f-f97e-4a8a-9978-de9e3b40a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482409193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.482409193
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2845397680
Short name T1206
Test name
Test status
Simulation time 12394849030 ps
CPU time 108.62 seconds
Started Jul 06 05:46:34 PM PDT 24
Finished Jul 06 05:48:23 PM PDT 24
Peak memory 205080 kb
Host smart-b2c3790a-be91-402b-98ea-15907be93998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845397680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2845397680
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.3854226121
Short name T382
Test name
Test status
Simulation time 71085884 ps
CPU time 1.96 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:46:36 PM PDT 24
Peak memory 204924 kb
Host smart-9f8c9051-beee-4b52-819b-0f763fcd2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854226121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.3854226121
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1429113136
Short name T1099
Test name
Test status
Simulation time 1373553275 ps
CPU time 23.47 seconds
Started Jul 06 05:46:27 PM PDT 24
Finished Jul 06 05:46:51 PM PDT 24
Peak memory 363900 kb
Host smart-a8a1f353-4c31-44ce-b5fa-fccceb56b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429113136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1429113136
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1931993519
Short name T1528
Test name
Test status
Simulation time 1802565910 ps
CPU time 42.47 seconds
Started Jul 06 05:46:34 PM PDT 24
Finished Jul 06 05:47:17 PM PDT 24
Peak memory 213204 kb
Host smart-582d42e1-4360-4862-ad90-caedf4f40c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931993519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1931993519
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3301624731
Short name T746
Test name
Test status
Simulation time 1088957699 ps
CPU time 4.98 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:46:43 PM PDT 24
Peak memory 213272 kb
Host smart-e068c4b0-38f5-44b9-84e4-9a10785241e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301624731 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3301624731
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3954401650
Short name T866
Test name
Test status
Simulation time 217733496 ps
CPU time 0.95 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:46:34 PM PDT 24
Peak memory 204824 kb
Host smart-3d9e0354-392d-4b4d-bfa3-5b353802dc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954401650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3954401650
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3309902209
Short name T377
Test name
Test status
Simulation time 1346909285 ps
CPU time 1.62 seconds
Started Jul 06 05:46:32 PM PDT 24
Finished Jul 06 05:46:34 PM PDT 24
Peak memory 206048 kb
Host smart-ad2ee374-66c4-4130-85d6-76003dcaa7c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309902209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3309902209
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.4151343138
Short name T1473
Test name
Test status
Simulation time 482012116 ps
CPU time 1.28 seconds
Started Jul 06 05:46:36 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 204664 kb
Host smart-0eeb9533-7c13-464d-8712-f548997232da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151343138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.4151343138
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.179331045
Short name T474
Test name
Test status
Simulation time 219182972 ps
CPU time 1.05 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:46:38 PM PDT 24
Peak memory 204832 kb
Host smart-7349c95a-577c-42f1-902f-7f8cf34e92ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179331045 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.179331045
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.961334737
Short name T598
Test name
Test status
Simulation time 1309425425 ps
CPU time 3.65 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:46:41 PM PDT 24
Peak memory 205128 kb
Host smart-7adead41-1b0b-4c00-bcd1-5027d895e264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961334737 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.961334737
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2511518007
Short name T1322
Test name
Test status
Simulation time 2190078211 ps
CPU time 3.77 seconds
Started Jul 06 05:46:32 PM PDT 24
Finished Jul 06 05:46:36 PM PDT 24
Peak memory 205348 kb
Host smart-26b9e865-d378-4d8b-8028-c5f6bc0de08f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511518007 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2511518007
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2923684597
Short name T1399
Test name
Test status
Simulation time 21768697635 ps
CPU time 9.23 seconds
Started Jul 06 05:46:34 PM PDT 24
Finished Jul 06 05:46:44 PM PDT 24
Peak memory 244148 kb
Host smart-d09c1cb5-4099-49ff-b039-1a00f9734312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923684597 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2923684597
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2440175043
Short name T1515
Test name
Test status
Simulation time 3212361484 ps
CPU time 13.03 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:46:47 PM PDT 24
Peak memory 205116 kb
Host smart-8fc914ab-533e-4de2-a13b-12c3fb319741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440175043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2440175043
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.219335310
Short name T229
Test name
Test status
Simulation time 978743101 ps
CPU time 15.62 seconds
Started Jul 06 05:46:32 PM PDT 24
Finished Jul 06 05:46:48 PM PDT 24
Peak memory 218048 kb
Host smart-b2942103-4e58-49e3-9257-0613595d3765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219335310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.219335310
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.631290782
Short name T860
Test name
Test status
Simulation time 23273513914 ps
CPU time 66.32 seconds
Started Jul 06 05:46:34 PM PDT 24
Finished Jul 06 05:47:41 PM PDT 24
Peak memory 963388 kb
Host smart-f5587b39-937d-413f-ba5b-8e50d5435045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631290782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.631290782
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2451970224
Short name T1168
Test name
Test status
Simulation time 3864455201 ps
CPU time 44.67 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:47:18 PM PDT 24
Peak memory 767924 kb
Host smart-d63f4ae4-8f0f-4ffe-8f9f-c3d4c1a038c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451970224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2451970224
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3394402820
Short name T679
Test name
Test status
Simulation time 5619754133 ps
CPU time 7.79 seconds
Started Jul 06 05:46:33 PM PDT 24
Finished Jul 06 05:46:41 PM PDT 24
Peak memory 220780 kb
Host smart-042e124c-cead-466d-b7a2-d634d942cd54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394402820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3394402820
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.4069217625
Short name T1183
Test name
Test status
Simulation time 121494114 ps
CPU time 2.49 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:46:39 PM PDT 24
Peak memory 205056 kb
Host smart-8b336988-e88e-4679-99a3-32f2a08bc331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069217625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.4069217625
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.666327792
Short name T881
Test name
Test status
Simulation time 33666094 ps
CPU time 0.72 seconds
Started Jul 06 05:46:46 PM PDT 24
Finished Jul 06 05:46:47 PM PDT 24
Peak memory 204632 kb
Host smart-266094c9-b71c-468c-bac5-23fe1431763c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666327792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.666327792
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3196291531
Short name T787
Test name
Test status
Simulation time 476246472 ps
CPU time 3.93 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:46:44 PM PDT 24
Peak memory 246540 kb
Host smart-7844d355-295c-40df-8703-1955ea4334e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196291531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3196291531
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3032094013
Short name T1477
Test name
Test status
Simulation time 2281828831 ps
CPU time 31.32 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:47:10 PM PDT 24
Peak memory 319480 kb
Host smart-04aea6b6-8e9c-42cc-babd-46c7e44bd25f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032094013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3032094013
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.680130973
Short name T76
Test name
Test status
Simulation time 5576314951 ps
CPU time 100.51 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:48:19 PM PDT 24
Peak memory 568276 kb
Host smart-1313f6ea-f117-4899-acfd-371613be742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680130973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.680130973
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2660510050
Short name T1177
Test name
Test status
Simulation time 2126782547 ps
CPU time 161.72 seconds
Started Jul 06 05:46:39 PM PDT 24
Finished Jul 06 05:49:21 PM PDT 24
Peak memory 707384 kb
Host smart-63b98394-1724-40e6-ae14-690bd04adf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660510050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2660510050
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1472143097
Short name T1185
Test name
Test status
Simulation time 884484503 ps
CPU time 6.1 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:46:44 PM PDT 24
Peak memory 246160 kb
Host smart-f35bcd2a-30c1-426f-aa08-6d4ecb8c8c4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472143097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1472143097
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1462157117
Short name T353
Test name
Test status
Simulation time 6329166372 ps
CPU time 178.83 seconds
Started Jul 06 05:46:37 PM PDT 24
Finished Jul 06 05:49:37 PM PDT 24
Peak memory 857444 kb
Host smart-780e017d-ceaf-43ca-b597-4ae474d13dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462157117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1462157117
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3266671758
Short name T236
Test name
Test status
Simulation time 1570827833 ps
CPU time 5.05 seconds
Started Jul 06 05:46:46 PM PDT 24
Finished Jul 06 05:46:51 PM PDT 24
Peak memory 205000 kb
Host smart-c81a29b6-57be-4a95-84cb-c7f31bc7bd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266671758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3266671758
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3219418886
Short name T694
Test name
Test status
Simulation time 2026363271 ps
CPU time 84.32 seconds
Started Jul 06 05:46:46 PM PDT 24
Finished Jul 06 05:48:11 PM PDT 24
Peak memory 357628 kb
Host smart-6f28b6a4-27b1-45b9-acaf-d0837f50bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219418886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3219418886
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2061606845
Short name T82
Test name
Test status
Simulation time 98702650 ps
CPU time 0.71 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:46:39 PM PDT 24
Peak memory 204676 kb
Host smart-165e1d5f-8975-4cfa-b9b2-9f0c50ff2054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061606845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2061606845
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3367582579
Short name T1042
Test name
Test status
Simulation time 2774402842 ps
CPU time 38.24 seconds
Started Jul 06 05:46:39 PM PDT 24
Finished Jul 06 05:47:18 PM PDT 24
Peak memory 364096 kb
Host smart-9d44f1c4-eba7-49ff-a37f-1fcc4e05e040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367582579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3367582579
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1693673659
Short name T993
Test name
Test status
Simulation time 225394952 ps
CPU time 10.62 seconds
Started Jul 06 05:46:39 PM PDT 24
Finished Jul 06 05:46:50 PM PDT 24
Peak memory 238264 kb
Host smart-86d6ba30-58f5-4c20-9c7d-44e2c3fa0078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693673659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1693673659
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3354193006
Short name T1096
Test name
Test status
Simulation time 2097258250 ps
CPU time 113.28 seconds
Started Jul 06 05:46:38 PM PDT 24
Finished Jul 06 05:48:32 PM PDT 24
Peak memory 499208 kb
Host smart-e1561473-1a66-4671-a8e8-3f7732b53b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354193006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3354193006
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3006679647
Short name T219
Test name
Test status
Simulation time 8910081943 ps
CPU time 914.88 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 06:01:56 PM PDT 24
Peak memory 1884220 kb
Host smart-a96e5945-9ba1-45d0-85dd-51a990bfb45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006679647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3006679647
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4034077824
Short name T1223
Test name
Test status
Simulation time 654120963 ps
CPU time 30.28 seconds
Started Jul 06 05:46:42 PM PDT 24
Finished Jul 06 05:47:13 PM PDT 24
Peak memory 213184 kb
Host smart-d5bfd6b3-128c-416b-988f-6a11283be016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034077824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4034077824
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2321564668
Short name T796
Test name
Test status
Simulation time 3587093919 ps
CPU time 4.91 seconds
Started Jul 06 05:46:48 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 213328 kb
Host smart-cffe28b4-8d1a-4aa6-9466-5c8be9056faa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321564668 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2321564668
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1721567303
Short name T529
Test name
Test status
Simulation time 339734982 ps
CPU time 1.31 seconds
Started Jul 06 05:46:41 PM PDT 24
Finished Jul 06 05:46:43 PM PDT 24
Peak memory 204984 kb
Host smart-21e2f3d7-f708-45e3-b4f9-28e13d597874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721567303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1721567303
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.222097337
Short name T365
Test name
Test status
Simulation time 238896807 ps
CPU time 0.97 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:46:42 PM PDT 24
Peak memory 204832 kb
Host smart-f544ac0b-8a80-4c2b-ae20-27b31564a470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222097337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.222097337
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.156878073
Short name T238
Test name
Test status
Simulation time 721149935 ps
CPU time 3.6 seconds
Started Jul 06 05:46:46 PM PDT 24
Finished Jul 06 05:46:50 PM PDT 24
Peak memory 213176 kb
Host smart-3fcf1ebe-1cc3-470f-9e6c-64fac5c2cceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156878073 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.156878073
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.1900380837
Short name T1151
Test name
Test status
Simulation time 377087079 ps
CPU time 1.08 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:48 PM PDT 24
Peak memory 204812 kb
Host smart-522f045c-168c-44d8-88be-9a288a7bbc21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900380837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1900380837
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2994652307
Short name T1488
Test name
Test status
Simulation time 1294092535 ps
CPU time 2.98 seconds
Started Jul 06 05:46:46 PM PDT 24
Finished Jul 06 05:46:49 PM PDT 24
Peak memory 205100 kb
Host smart-df43f28a-b7cf-4f41-b2ca-309497781af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994652307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2994652307
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.4265834203
Short name T870
Test name
Test status
Simulation time 828436208 ps
CPU time 4.28 seconds
Started Jul 06 05:46:41 PM PDT 24
Finished Jul 06 05:46:45 PM PDT 24
Peak memory 213252 kb
Host smart-4ea74f48-ce47-442b-9a99-9e08e6e83840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265834203 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.4265834203
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1531043429
Short name T286
Test name
Test status
Simulation time 20258893439 ps
CPU time 52.61 seconds
Started Jul 06 05:46:43 PM PDT 24
Finished Jul 06 05:47:36 PM PDT 24
Peak memory 1223040 kb
Host smart-b09a982d-876f-4edd-96cc-7e7b7093bf14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531043429 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1531043429
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1740238642
Short name T1174
Test name
Test status
Simulation time 1306173682 ps
CPU time 21.47 seconds
Started Jul 06 05:46:41 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 205060 kb
Host smart-bb08f421-d146-4596-8324-f757ec2f447a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740238642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1740238642
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.448608804
Short name T417
Test name
Test status
Simulation time 3388653471 ps
CPU time 12.21 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:46:53 PM PDT 24
Peak memory 218660 kb
Host smart-c6bcbf42-92a5-4428-bebc-d40cb592011c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448608804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.448608804
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2904707562
Short name T1071
Test name
Test status
Simulation time 25938949382 ps
CPU time 106.75 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:48:28 PM PDT 24
Peak memory 1581740 kb
Host smart-a67bb2a2-a1bb-4f74-9e33-8e98be59abb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904707562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2904707562
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3775762276
Short name T119
Test name
Test status
Simulation time 2994478954 ps
CPU time 2.69 seconds
Started Jul 06 05:46:40 PM PDT 24
Finished Jul 06 05:46:43 PM PDT 24
Peak memory 204944 kb
Host smart-a2f15c0a-eb78-43bb-adfb-9286d41b842c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775762276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3775762276
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3314751702
Short name T468
Test name
Test status
Simulation time 1319525535 ps
CPU time 6.95 seconds
Started Jul 06 05:46:41 PM PDT 24
Finished Jul 06 05:46:48 PM PDT 24
Peak memory 213252 kb
Host smart-5c16b0e1-4f8f-477c-a1e9-ff07cc18600c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314751702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3314751702
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2577197175
Short name T1049
Test name
Test status
Simulation time 740819661 ps
CPU time 9.57 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:57 PM PDT 24
Peak memory 204968 kb
Host smart-89aacda8-b1dd-469a-aab4-806697d36f6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577197175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2577197175
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3970613852
Short name T1208
Test name
Test status
Simulation time 44690042 ps
CPU time 0.62 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 05:46:56 PM PDT 24
Peak memory 204572 kb
Host smart-27920f2f-0d21-4ad3-8e8f-1ac8d956d62b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970613852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3970613852
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1432505795
Short name T689
Test name
Test status
Simulation time 544249297 ps
CPU time 6.29 seconds
Started Jul 06 05:46:51 PM PDT 24
Finished Jul 06 05:46:57 PM PDT 24
Peak memory 237672 kb
Host smart-54e77fba-67e9-40ba-99e3-10eabde11dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432505795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1432505795
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1796989321
Short name T478
Test name
Test status
Simulation time 788283096 ps
CPU time 3.59 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:51 PM PDT 24
Peak memory 231708 kb
Host smart-dd48ee49-aa51-4521-bec0-3370d8d98961
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796989321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1796989321
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.850080533
Short name T1377
Test name
Test status
Simulation time 1571075707 ps
CPU time 44.03 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:47:32 PM PDT 24
Peak memory 580808 kb
Host smart-460b2ac2-3d5a-4f8d-b943-d670544ea652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850080533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.850080533
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1736454565
Short name T1267
Test name
Test status
Simulation time 11508918524 ps
CPU time 211.27 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:50:18 PM PDT 24
Peak memory 838760 kb
Host smart-9948ea79-2c8b-4476-a35e-58ff64100a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736454565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1736454565
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1171238261
Short name T820
Test name
Test status
Simulation time 121847999 ps
CPU time 1.11 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:49 PM PDT 24
Peak memory 204660 kb
Host smart-d401c801-0766-4e78-8eed-d2cf3f45a2b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171238261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1171238261
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1815553095
Short name T387
Test name
Test status
Simulation time 118859716 ps
CPU time 3.46 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:51 PM PDT 24
Peak memory 222496 kb
Host smart-50673196-5a66-4cbf-af7c-9c5216acfb3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815553095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1815553095
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1489675459
Short name T1212
Test name
Test status
Simulation time 18504017237 ps
CPU time 294 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:51:41 PM PDT 24
Peak memory 1220072 kb
Host smart-b6d07632-d3dd-435e-bd55-ed8287949810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489675459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1489675459
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2185374626
Short name T391
Test name
Test status
Simulation time 404426611 ps
CPU time 2.81 seconds
Started Jul 06 05:46:56 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 205096 kb
Host smart-ead5a4b2-a596-4afb-ba35-67e4fc000687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185374626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2185374626
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.239229471
Short name T1094
Test name
Test status
Simulation time 4247098008 ps
CPU time 45.48 seconds
Started Jul 06 05:46:52 PM PDT 24
Finished Jul 06 05:47:37 PM PDT 24
Peak memory 263748 kb
Host smart-ae785cc6-cbe3-4f3e-add8-2bfe53bf4dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239229471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.239229471
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3789245180
Short name T1038
Test name
Test status
Simulation time 51264468 ps
CPU time 0.68 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:46:48 PM PDT 24
Peak memory 204752 kb
Host smart-694246ea-6a7a-4dd1-90ab-b3405a556bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789245180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3789245180
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1513649918
Short name T999
Test name
Test status
Simulation time 14352908105 ps
CPU time 27.19 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:47:15 PM PDT 24
Peak memory 404732 kb
Host smart-c2fcd008-63a0-4bc8-829a-39ad020579c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513649918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1513649918
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3818982364
Short name T1048
Test name
Test status
Simulation time 98782621 ps
CPU time 1.89 seconds
Started Jul 06 05:46:52 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 222892 kb
Host smart-760a55d8-2f12-4c51-bf0e-0b42d2e0e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818982364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3818982364
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2765465959
Short name T649
Test name
Test status
Simulation time 7972891527 ps
CPU time 21.96 seconds
Started Jul 06 05:46:47 PM PDT 24
Finished Jul 06 05:47:09 PM PDT 24
Peak memory 302928 kb
Host smart-ec02d3ad-4648-47eb-abe6-61e05ef58e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765465959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2765465959
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2606976685
Short name T253
Test name
Test status
Simulation time 12950854488 ps
CPU time 1532.15 seconds
Started Jul 06 05:46:51 PM PDT 24
Finished Jul 06 06:12:23 PM PDT 24
Peak memory 2497864 kb
Host smart-6fcb1454-3c5b-4611-8e41-b6c8c62829a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606976685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2606976685
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.660096248
Short name T1203
Test name
Test status
Simulation time 630844527 ps
CPU time 11.17 seconds
Started Jul 06 05:46:52 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 221104 kb
Host smart-6d7716fc-11f2-4ec7-8f83-81101ca77ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660096248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.660096248
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1239976553
Short name T683
Test name
Test status
Simulation time 2733352582 ps
CPU time 3.95 seconds
Started Jul 06 05:46:50 PM PDT 24
Finished Jul 06 05:46:55 PM PDT 24
Peak memory 213236 kb
Host smart-fd31af04-d682-4532-a570-af5b984276d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239976553 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1239976553
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2428110961
Short name T1078
Test name
Test status
Simulation time 243530617 ps
CPU time 1.28 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 204820 kb
Host smart-30f2ff5a-dd29-46fc-bbcc-9917299a9bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428110961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2428110961
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2220814969
Short name T1312
Test name
Test status
Simulation time 475828443 ps
CPU time 1.1 seconds
Started Jul 06 05:46:53 PM PDT 24
Finished Jul 06 05:46:55 PM PDT 24
Peak memory 204836 kb
Host smart-80c7f725-6b69-4b38-a96c-58493d1b98e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220814969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2220814969
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1829601804
Short name T1520
Test name
Test status
Simulation time 1262484158 ps
CPU time 1.89 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 204920 kb
Host smart-0ffc111d-dc35-448c-856e-f3f6612736d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829601804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1829601804
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.3040214397
Short name T18
Test name
Test status
Simulation time 148615263 ps
CPU time 0.77 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:46:58 PM PDT 24
Peak memory 204840 kb
Host smart-81206327-006d-42a3-a34e-b88a79d1f7cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040214397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.3040214397
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2458690790
Short name T1067
Test name
Test status
Simulation time 391259158 ps
CPU time 3.55 seconds
Started Jul 06 05:46:50 PM PDT 24
Finished Jul 06 05:46:54 PM PDT 24
Peak memory 205116 kb
Host smart-6999583e-dbfb-405d-bd8b-f98fce4d89ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458690790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2458690790
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3733313906
Short name T1114
Test name
Test status
Simulation time 4968505380 ps
CPU time 6.12 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:47:05 PM PDT 24
Peak memory 213332 kb
Host smart-c7eed84f-0f50-4f43-ad75-a2fac155741f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733313906 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3733313906
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1994390557
Short name T974
Test name
Test status
Simulation time 23339166636 ps
CPU time 471.57 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:54:50 PM PDT 24
Peak memory 5393468 kb
Host smart-ebc0250b-55ce-4cac-ae78-1aad9a0e14d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994390557 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1994390557
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.4160056022
Short name T1196
Test name
Test status
Simulation time 475920579 ps
CPU time 16.78 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:47:14 PM PDT 24
Peak memory 205036 kb
Host smart-96f131be-25b3-409e-9fd5-33a305d42a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160056022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.4160056022
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.456258224
Short name T662
Test name
Test status
Simulation time 1315985555 ps
CPU time 20.8 seconds
Started Jul 06 05:46:52 PM PDT 24
Finished Jul 06 05:47:13 PM PDT 24
Peak memory 229564 kb
Host smart-84a7e6c2-535e-47b1-80cc-3792f214ddb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456258224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.456258224
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3909220459
Short name T1115
Test name
Test status
Simulation time 25422651863 ps
CPU time 89.16 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:48:27 PM PDT 24
Peak memory 1294004 kb
Host smart-2b8da5ed-b703-4e3c-9948-30488b7ef5d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909220459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3909220459
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3764923364
Short name T917
Test name
Test status
Simulation time 4900650149 ps
CPU time 7.07 seconds
Started Jul 06 05:46:49 PM PDT 24
Finished Jul 06 05:46:57 PM PDT 24
Peak memory 221208 kb
Host smart-110c8ae8-36a8-46af-9998-d4b42121a321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764923364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3764923364
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.3504091123
Short name T1521
Test name
Test status
Simulation time 116901032 ps
CPU time 2.46 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 205056 kb
Host smart-fefa39ed-6073-4874-8dd8-d314d4471c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504091123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3504091123
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2678128553
Short name T272
Test name
Test status
Simulation time 51476451 ps
CPU time 0.61 seconds
Started Jul 06 05:47:04 PM PDT 24
Finished Jul 06 05:47:05 PM PDT 24
Peak memory 204516 kb
Host smart-fffef1ab-4998-402e-9ae4-3992f7f69a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678128553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2678128553
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3735124537
Short name T273
Test name
Test status
Simulation time 196307115 ps
CPU time 3.91 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:47:01 PM PDT 24
Peak memory 236956 kb
Host smart-17afa455-1e51-4ae6-b6e8-4c88ee5f4ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735124537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3735124537
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3147701396
Short name T427
Test name
Test status
Simulation time 6428905220 ps
CPU time 10.79 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 05:47:06 PM PDT 24
Peak memory 304352 kb
Host smart-e6b666b4-3ae3-451c-93be-2e4d44d361b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147701396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3147701396
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1536119948
Short name T78
Test name
Test status
Simulation time 1810248628 ps
CPU time 58.35 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 05:47:53 PM PDT 24
Peak memory 644312 kb
Host smart-8506380c-c9fb-473d-a86f-8df61bcab7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536119948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1536119948
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.262592535
Short name T1349
Test name
Test status
Simulation time 10756926884 ps
CPU time 211.39 seconds
Started Jul 06 05:46:56 PM PDT 24
Finished Jul 06 05:50:28 PM PDT 24
Peak memory 847924 kb
Host smart-e8c0fc5c-1b98-4151-b060-131729c05425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262592535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.262592535
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3934314226
Short name T1028
Test name
Test status
Simulation time 708010770 ps
CPU time 1.31 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 05:46:57 PM PDT 24
Peak memory 204936 kb
Host smart-3b5b5c12-02ee-408d-86f2-9da97624bff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934314226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3934314226
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.277768272
Short name T828
Test name
Test status
Simulation time 123763875 ps
CPU time 7.43 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:47:05 PM PDT 24
Peak memory 225092 kb
Host smart-ffd11f49-03c7-444c-b9c4-4550844fe62a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277768272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
277768272
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2139235174
Short name T905
Test name
Test status
Simulation time 40219385115 ps
CPU time 138.72 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 05:49:14 PM PDT 24
Peak memory 1279244 kb
Host smart-07aa663b-86d2-41e3-8315-e42711a858f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139235174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2139235174
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2308154894
Short name T490
Test name
Test status
Simulation time 1686296930 ps
CPU time 8.07 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:10 PM PDT 24
Peak memory 204940 kb
Host smart-7777303b-5c9d-48cb-a246-ec00a75433fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308154894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2308154894
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2763954092
Short name T923
Test name
Test status
Simulation time 2216352995 ps
CPU time 104.23 seconds
Started Jul 06 05:47:00 PM PDT 24
Finished Jul 06 05:48:44 PM PDT 24
Peak memory 456276 kb
Host smart-4148edc7-e191-43f2-93ba-ee82c271b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763954092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2763954092
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2811496164
Short name T124
Test name
Test status
Simulation time 33636402 ps
CPU time 0.67 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:46:58 PM PDT 24
Peak memory 204644 kb
Host smart-390c7c0b-b4e9-4108-bc90-b00279955754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811496164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2811496164
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3522676861
Short name T524
Test name
Test status
Simulation time 7114076253 ps
CPU time 32.24 seconds
Started Jul 06 05:46:56 PM PDT 24
Finished Jul 06 05:47:28 PM PDT 24
Peak memory 213584 kb
Host smart-48ef5be6-9a82-4756-86eb-aebd7e00be20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522676861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3522676861
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3600151866
Short name T1121
Test name
Test status
Simulation time 546528495 ps
CPU time 2.2 seconds
Started Jul 06 05:46:58 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 204976 kb
Host smart-dfaf1ec5-bd39-4b23-923e-1a21e52ed920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600151866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3600151866
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.423536281
Short name T1358
Test name
Test status
Simulation time 6177311202 ps
CPU time 31.93 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:47:29 PM PDT 24
Peak memory 332840 kb
Host smart-fb990e1c-ecbd-483a-b07f-edecb2d6addb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423536281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.423536281
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1435505537
Short name T332
Test name
Test status
Simulation time 152347224363 ps
CPU time 2586.38 seconds
Started Jul 06 05:46:55 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 5086280 kb
Host smart-61b17fe5-dcf5-4d97-835d-bc508bef8207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435505537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1435505537
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.828702315
Short name T458
Test name
Test status
Simulation time 12032511789 ps
CPU time 37.99 seconds
Started Jul 06 05:46:57 PM PDT 24
Finished Jul 06 05:47:35 PM PDT 24
Peak memory 213296 kb
Host smart-2df8815a-6653-4268-b42f-1f7d784d8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828702315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.828702315
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.366608990
Short name T697
Test name
Test status
Simulation time 13870802113 ps
CPU time 5.06 seconds
Started Jul 06 05:47:04 PM PDT 24
Finished Jul 06 05:47:10 PM PDT 24
Peak memory 213228 kb
Host smart-29a92a07-bcd8-4757-a36c-ff82d13c615b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366608990 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.366608990
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1938664399
Short name T187
Test name
Test status
Simulation time 1196652513 ps
CPU time 1.26 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 204732 kb
Host smart-3adfed56-492e-43fc-bb01-9a174cc599cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938664399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1938664399
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.351009208
Short name T729
Test name
Test status
Simulation time 294108100 ps
CPU time 0.96 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 204804 kb
Host smart-c16b1e0f-2696-415b-a5cb-a808e18ba8cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351009208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.351009208
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.4001214242
Short name T892
Test name
Test status
Simulation time 1367973134 ps
CPU time 2.08 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 204976 kb
Host smart-c7b88709-8bc6-4d5b-9de1-414b49a81919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001214242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.4001214242
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.3058153700
Short name T1527
Test name
Test status
Simulation time 180425853 ps
CPU time 1.32 seconds
Started Jul 06 05:47:02 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 204828 kb
Host smart-684654b5-68c6-4b8c-bfc6-6e98d4ef6565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058153700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.3058153700
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.512476359
Short name T264
Test name
Test status
Simulation time 355120945 ps
CPU time 3.44 seconds
Started Jul 06 05:47:00 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 205076 kb
Host smart-0cd3851c-370b-44fa-86e1-a3071f62848c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512476359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.512476359
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1530186547
Short name T1060
Test name
Test status
Simulation time 1465697360 ps
CPU time 4.78 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:07 PM PDT 24
Peak memory 205072 kb
Host smart-eacccd87-ed4c-41e4-8f63-e4b86988b1e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530186547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1530186547
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2819294279
Short name T1149
Test name
Test status
Simulation time 1013439077 ps
CPU time 7.04 seconds
Started Jul 06 05:47:00 PM PDT 24
Finished Jul 06 05:47:07 PM PDT 24
Peak memory 205056 kb
Host smart-4b47f314-4d5b-475d-b9dd-1d6efbbb4b83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819294279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2819294279
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.121713260
Short name T1198
Test name
Test status
Simulation time 1300308145 ps
CPU time 20.22 seconds
Started Jul 06 05:47:03 PM PDT 24
Finished Jul 06 05:47:23 PM PDT 24
Peak memory 215572 kb
Host smart-11e28c51-93b2-4ebc-be10-68a654d50fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121713260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.121713260
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1195809311
Short name T824
Test name
Test status
Simulation time 42472943092 ps
CPU time 642.32 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:57:44 PM PDT 24
Peak memory 5505064 kb
Host smart-cbb75243-338b-4977-92d5-b46c87d65475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195809311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1195809311
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.528632013
Short name T947
Test name
Test status
Simulation time 1307587475 ps
CPU time 4.39 seconds
Started Jul 06 05:47:00 PM PDT 24
Finished Jul 06 05:47:05 PM PDT 24
Peak memory 246132 kb
Host smart-d1486714-edb6-4594-9076-4f866699f270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528632013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_t
arget_stretch.528632013
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1036473433
Short name T984
Test name
Test status
Simulation time 9547263819 ps
CPU time 8.55 seconds
Started Jul 06 05:47:01 PM PDT 24
Finished Jul 06 05:47:10 PM PDT 24
Peak memory 221288 kb
Host smart-df158069-e514-4cca-be1e-c7a61899dc6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036473433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1036473433
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.2799344316
Short name T1342
Test name
Test status
Simulation time 173811992 ps
CPU time 2.93 seconds
Started Jul 06 05:47:03 PM PDT 24
Finished Jul 06 05:47:06 PM PDT 24
Peak memory 205056 kb
Host smart-0ffc9bf6-57b2-4df2-ae87-f93bd65644b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799344316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2799344316
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3157259971
Short name T1343
Test name
Test status
Simulation time 22754210 ps
CPU time 0.58 seconds
Started Jul 06 05:47:11 PM PDT 24
Finished Jul 06 05:47:12 PM PDT 24
Peak memory 204600 kb
Host smart-74916a0a-1a22-45e1-aa30-e794c26e4092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157259971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3157259971
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3383076738
Short name T1400
Test name
Test status
Simulation time 418387702 ps
CPU time 1.9 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:09 PM PDT 24
Peak memory 213292 kb
Host smart-caa5ac5b-4430-455e-99aa-e37314444fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383076738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3383076738
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1731098621
Short name T270
Test name
Test status
Simulation time 320599474 ps
CPU time 16.48 seconds
Started Jul 06 05:47:08 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 272780 kb
Host smart-00219fdb-6234-46b6-8c30-8b574f6ac6bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731098621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1731098621
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.870873943
Short name T72
Test name
Test status
Simulation time 9235495283 ps
CPU time 129.11 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:49:16 PM PDT 24
Peak memory 665992 kb
Host smart-da04ff93-e921-4cc0-92f8-e311630c33c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870873943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.870873943
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1654743304
Short name T444
Test name
Test status
Simulation time 2210371025 ps
CPU time 164.33 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:49:51 PM PDT 24
Peak memory 697768 kb
Host smart-7cfe994c-4866-425f-b37c-7f7d9df96d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654743304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1654743304
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3125229877
Short name T1018
Test name
Test status
Simulation time 219185461 ps
CPU time 1.01 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:07 PM PDT 24
Peak memory 204708 kb
Host smart-4e990990-7520-41b6-a4d9-54d25de33aad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125229877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3125229877
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3842354027
Short name T459
Test name
Test status
Simulation time 167046914 ps
CPU time 3.75 seconds
Started Jul 06 05:47:07 PM PDT 24
Finished Jul 06 05:47:11 PM PDT 24
Peak memory 205020 kb
Host smart-ca13edb2-fa5e-4dd0-b810-89c2fcc6db26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842354027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3842354027
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2760962524
Short name T1188
Test name
Test status
Simulation time 7951124109 ps
CPU time 118.41 seconds
Started Jul 06 05:47:11 PM PDT 24
Finished Jul 06 05:49:10 PM PDT 24
Peak memory 1167572 kb
Host smart-a00811cf-1c0f-4161-8075-625e1c9787ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760962524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2760962524
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.4083876372
Short name T944
Test name
Test status
Simulation time 531238187 ps
CPU time 8.33 seconds
Started Jul 06 05:47:12 PM PDT 24
Finished Jul 06 05:47:20 PM PDT 24
Peak memory 205040 kb
Host smart-16cfbbbb-5145-413e-b33b-ad19829d760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083876372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.4083876372
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.113003868
Short name T39
Test name
Test status
Simulation time 6625257507 ps
CPU time 36.33 seconds
Started Jul 06 05:47:10 PM PDT 24
Finished Jul 06 05:47:47 PM PDT 24
Peak memory 417996 kb
Host smart-0484e8f2-929d-4005-9c16-0f0df8aedca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113003868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.113003868
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.4276211252
Short name T1140
Test name
Test status
Simulation time 84022126 ps
CPU time 0.7 seconds
Started Jul 06 05:47:03 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 204748 kb
Host smart-d16a1fb4-1365-4608-924e-9e125109e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276211252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4276211252
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.574289188
Short name T1367
Test name
Test status
Simulation time 18315596234 ps
CPU time 240.02 seconds
Started Jul 06 05:47:07 PM PDT 24
Finished Jul 06 05:51:07 PM PDT 24
Peak memory 213328 kb
Host smart-075fb791-0cf6-4968-b750-bdb4828a7550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574289188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.574289188
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.885288124
Short name T989
Test name
Test status
Simulation time 261233608 ps
CPU time 2.25 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:09 PM PDT 24
Peak memory 205924 kb
Host smart-eccfb3a8-a5d8-43a9-b8dc-72e89f49f997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885288124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.885288124
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2453026229
Short name T986
Test name
Test status
Simulation time 4012705571 ps
CPU time 36.4 seconds
Started Jul 06 05:47:02 PM PDT 24
Finished Jul 06 05:47:38 PM PDT 24
Peak memory 431024 kb
Host smart-76a602f8-5c5d-4132-96a5-2f7ac353005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453026229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2453026229
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.447610586
Short name T75
Test name
Test status
Simulation time 30727632669 ps
CPU time 735.53 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:59:22 PM PDT 24
Peak memory 2034408 kb
Host smart-fd29eda8-d907-48f0-8baf-6d207ad450bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447610586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.447610586
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1781993710
Short name T245
Test name
Test status
Simulation time 6528808850 ps
CPU time 14.14 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:21 PM PDT 24
Peak memory 216832 kb
Host smart-89710bef-d31e-4774-a4e3-e497c5402d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781993710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1781993710
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.4097421432
Short name T764
Test name
Test status
Simulation time 1721494577 ps
CPU time 4.73 seconds
Started Jul 06 05:47:10 PM PDT 24
Finished Jul 06 05:47:15 PM PDT 24
Peak memory 213236 kb
Host smart-95c1c260-8758-4314-b99c-09f849b93095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097421432 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.4097421432
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3725159697
Short name T433
Test name
Test status
Simulation time 118334997 ps
CPU time 0.92 seconds
Started Jul 06 05:47:13 PM PDT 24
Finished Jul 06 05:47:15 PM PDT 24
Peak memory 204816 kb
Host smart-52ea1ca8-5961-47c6-b427-ec089d96403d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725159697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3725159697
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.946322231
Short name T1292
Test name
Test status
Simulation time 697796188 ps
CPU time 1.37 seconds
Started Jul 06 05:47:10 PM PDT 24
Finished Jul 06 05:47:11 PM PDT 24
Peak memory 205712 kb
Host smart-93326f60-cd4c-4360-a825-ea4cba9954ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946322231 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.946322231
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.664174188
Short name T1455
Test name
Test status
Simulation time 149444395 ps
CPU time 1.2 seconds
Started Jul 06 05:47:09 PM PDT 24
Finished Jul 06 05:47:11 PM PDT 24
Peak memory 204752 kb
Host smart-0abdbdcc-c070-41af-a49c-bead942fff6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664174188 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.664174188
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3244742225
Short name T1457
Test name
Test status
Simulation time 165993558 ps
CPU time 0.73 seconds
Started Jul 06 05:47:13 PM PDT 24
Finished Jul 06 05:47:15 PM PDT 24
Peak memory 204852 kb
Host smart-162c7e17-68c1-4e33-a477-fe8897d6e7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244742225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3244742225
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1772506916
Short name T1320
Test name
Test status
Simulation time 1167904130 ps
CPU time 6.53 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:13 PM PDT 24
Peak memory 213196 kb
Host smart-901bee9b-ccdc-4f9f-aab8-4269f4b17fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772506916 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1772506916
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1513440340
Short name T647
Test name
Test status
Simulation time 12735033960 ps
CPU time 17.19 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:23 PM PDT 24
Peak memory 441944 kb
Host smart-31708244-fb08-4963-afa6-585952bb3485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513440340 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1513440340
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.566820765
Short name T799
Test name
Test status
Simulation time 5790178314 ps
CPU time 16.27 seconds
Started Jul 06 05:47:07 PM PDT 24
Finished Jul 06 05:47:24 PM PDT 24
Peak memory 205092 kb
Host smart-8c3e22d0-8406-4732-8c67-ec0d862e3780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566820765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.566820765
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.175805764
Short name T1427
Test name
Test status
Simulation time 805235823 ps
CPU time 33.08 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 05:47:39 PM PDT 24
Peak memory 204968 kb
Host smart-9c8ce58d-00ef-4be8-aa80-19639a29bef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175805764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.175805764
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3305477649
Short name T487
Test name
Test status
Simulation time 52155278320 ps
CPU time 1228.78 seconds
Started Jul 06 05:47:06 PM PDT 24
Finished Jul 06 06:07:36 PM PDT 24
Peak memory 7958000 kb
Host smart-beae2c51-2722-4a12-823c-6547223b6563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305477649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3305477649
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1797455740
Short name T641
Test name
Test status
Simulation time 703136091 ps
CPU time 6.63 seconds
Started Jul 06 05:47:08 PM PDT 24
Finished Jul 06 05:47:15 PM PDT 24
Peak memory 267024 kb
Host smart-0395dcd4-ea55-4bd7-a20d-e3fba9ca9314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797455740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1797455740
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.885734514
Short name T380
Test name
Test status
Simulation time 2525300462 ps
CPU time 6.58 seconds
Started Jul 06 05:47:11 PM PDT 24
Finished Jul 06 05:47:18 PM PDT 24
Peak memory 205116 kb
Host smart-2ff25fcf-dd67-4c2b-9029-b37cd2ed5716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885734514 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.885734514
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.3988599808
Short name T276
Test name
Test status
Simulation time 63712212 ps
CPU time 1.47 seconds
Started Jul 06 05:47:10 PM PDT 24
Finished Jul 06 05:47:12 PM PDT 24
Peak memory 205028 kb
Host smart-cf2d9e1b-1ee6-4027-b9c5-4507427a4489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988599808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.3988599808
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2439225375
Short name T1079
Test name
Test status
Simulation time 27349236 ps
CPU time 0.61 seconds
Started Jul 06 05:47:23 PM PDT 24
Finished Jul 06 05:47:24 PM PDT 24
Peak memory 204548 kb
Host smart-96b6d7e8-f928-4016-81c6-ace60af058d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439225375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2439225375
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1496652129
Short name T1314
Test name
Test status
Simulation time 264670711 ps
CPU time 2.11 seconds
Started Jul 06 05:47:19 PM PDT 24
Finished Jul 06 05:47:22 PM PDT 24
Peak memory 213356 kb
Host smart-135f74d7-e567-48b6-a8ca-ce6e297fbcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496652129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1496652129
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.662562527
Short name T748
Test name
Test status
Simulation time 1754207839 ps
CPU time 8.31 seconds
Started Jul 06 05:48:11 PM PDT 24
Finished Jul 06 05:48:20 PM PDT 24
Peak memory 280424 kb
Host smart-e6199f66-c190-4ba7-ba7c-903e8a336e20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662562527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.662562527
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1980149721
Short name T1072
Test name
Test status
Simulation time 2515441187 ps
CPU time 167.4 seconds
Started Jul 06 05:47:18 PM PDT 24
Finished Jul 06 05:50:06 PM PDT 24
Peak memory 714068 kb
Host smart-6c636202-57ca-45c1-9e27-324aab88f82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980149721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1980149721
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.983989762
Short name T671
Test name
Test status
Simulation time 1267722664 ps
CPU time 85.76 seconds
Started Jul 06 05:47:19 PM PDT 24
Finished Jul 06 05:48:45 PM PDT 24
Peak memory 491280 kb
Host smart-a5bd8fed-3641-44ef-9f2d-83985c0a41df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983989762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.983989762
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2901817204
Short name T1356
Test name
Test status
Simulation time 256442700 ps
CPU time 1.19 seconds
Started Jul 06 05:47:16 PM PDT 24
Finished Jul 06 05:47:17 PM PDT 24
Peak memory 204724 kb
Host smart-03d45cee-7d67-483e-9c11-3158f9b71fc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901817204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2901817204
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3591890165
Short name T301
Test name
Test status
Simulation time 142312430 ps
CPU time 8.12 seconds
Started Jul 06 05:47:19 PM PDT 24
Finished Jul 06 05:47:28 PM PDT 24
Peak memory 227440 kb
Host smart-26be75ea-9395-455c-bde8-9856f26f4e9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591890165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3591890165
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.515925213
Short name T582
Test name
Test status
Simulation time 51178914280 ps
CPU time 169.29 seconds
Started Jul 06 05:47:17 PM PDT 24
Finished Jul 06 05:50:06 PM PDT 24
Peak memory 1513636 kb
Host smart-1436eb63-d803-402f-b289-f91ee469c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515925213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.515925213
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.61026194
Short name T811
Test name
Test status
Simulation time 958177570 ps
CPU time 7.85 seconds
Started Jul 06 05:47:21 PM PDT 24
Finished Jul 06 05:47:29 PM PDT 24
Peak memory 205056 kb
Host smart-723d4ee7-7c27-4636-bc4f-6f20af74b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61026194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.61026194
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.197862121
Short name T1236
Test name
Test status
Simulation time 6903956649 ps
CPU time 24.3 seconds
Started Jul 06 05:47:24 PM PDT 24
Finished Jul 06 05:47:48 PM PDT 24
Peak memory 321060 kb
Host smart-4aecf7c8-90f8-4134-95b8-fefda2033825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197862121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.197862121
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3382271716
Short name T223
Test name
Test status
Simulation time 26895962 ps
CPU time 0.7 seconds
Started Jul 06 05:47:15 PM PDT 24
Finished Jul 06 05:47:16 PM PDT 24
Peak memory 204736 kb
Host smart-b2c4335d-8c10-40ae-82e7-f52ea4ba5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382271716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3382271716
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3090422203
Short name T1109
Test name
Test status
Simulation time 8194641318 ps
CPU time 85.7 seconds
Started Jul 06 05:47:18 PM PDT 24
Finished Jul 06 05:48:44 PM PDT 24
Peak memory 226624 kb
Host smart-373267ae-64bc-4b94-95ac-65b108e35573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090422203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3090422203
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.3533140309
Short name T849
Test name
Test status
Simulation time 3234559692 ps
CPU time 28.91 seconds
Started Jul 06 05:47:18 PM PDT 24
Finished Jul 06 05:47:48 PM PDT 24
Peak memory 265328 kb
Host smart-a0d9f84b-b0ac-4bd5-9472-a259797dbdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533140309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3533140309
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.985838980
Short name T835
Test name
Test status
Simulation time 6142102656 ps
CPU time 27.77 seconds
Started Jul 06 05:47:13 PM PDT 24
Finished Jul 06 05:47:41 PM PDT 24
Peak memory 299432 kb
Host smart-986e2371-f03f-4855-a020-ab6d23442787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985838980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.985838980
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.4038153046
Short name T261
Test name
Test status
Simulation time 11766412802 ps
CPU time 594.87 seconds
Started Jul 06 05:47:16 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 769544 kb
Host smart-f89fb4b5-297e-4ded-8e06-16e1909054f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038153046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.4038153046
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3396389810
Short name T617
Test name
Test status
Simulation time 7681201658 ps
CPU time 11.53 seconds
Started Jul 06 05:47:15 PM PDT 24
Finished Jul 06 05:47:27 PM PDT 24
Peak memory 221320 kb
Host smart-65e07912-af60-4fda-8934-62c460146f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396389810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3396389810
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3777679041
Short name T909
Test name
Test status
Simulation time 1045953233 ps
CPU time 3.89 seconds
Started Jul 06 05:47:21 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 213220 kb
Host smart-de2335c9-52e7-4303-ad79-1e76a5a6e205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777679041 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3777679041
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.71866250
Short name T1328
Test name
Test status
Simulation time 157645109 ps
CPU time 0.97 seconds
Started Jul 06 05:47:15 PM PDT 24
Finished Jul 06 05:47:16 PM PDT 24
Peak memory 204780 kb
Host smart-841c559b-f68e-4936-9fb8-458b11f1cba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71866250 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_acq.71866250
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.323197796
Short name T768
Test name
Test status
Simulation time 457239207 ps
CPU time 1.13 seconds
Started Jul 06 05:47:18 PM PDT 24
Finished Jul 06 05:47:19 PM PDT 24
Peak memory 204840 kb
Host smart-242ad571-d1e1-4882-97c2-e1cedf113260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323197796 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.323197796
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2549429404
Short name T1125
Test name
Test status
Simulation time 278606376 ps
CPU time 1.65 seconds
Started Jul 06 05:47:20 PM PDT 24
Finished Jul 06 05:47:22 PM PDT 24
Peak memory 204784 kb
Host smart-532e7199-816b-448c-be7a-ca7c45691fd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549429404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2549429404
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2924244580
Short name T300
Test name
Test status
Simulation time 220251934 ps
CPU time 1.16 seconds
Started Jul 06 05:47:21 PM PDT 24
Finished Jul 06 05:47:22 PM PDT 24
Peak memory 204828 kb
Host smart-99c01623-1751-44b1-9329-2e65de755813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924244580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2924244580
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1197314493
Short name T976
Test name
Test status
Simulation time 14179598652 ps
CPU time 7.72 seconds
Started Jul 06 05:47:17 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 213532 kb
Host smart-7134ba3c-cc4e-438a-a181-79b5d7ea590b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197314493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1197314493
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.248825110
Short name T901
Test name
Test status
Simulation time 15741928129 ps
CPU time 166.9 seconds
Started Jul 06 05:47:19 PM PDT 24
Finished Jul 06 05:50:06 PM PDT 24
Peak memory 2201620 kb
Host smart-0e52763c-c198-47ae-9e30-560bfba19023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248825110 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.248825110
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3736813147
Short name T865
Test name
Test status
Simulation time 5481704532 ps
CPU time 47.05 seconds
Started Jul 06 05:47:17 PM PDT 24
Finished Jul 06 05:48:04 PM PDT 24
Peak memory 205092 kb
Host smart-a4771dd1-e063-4d11-84a9-ad53824eb3df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736813147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3736813147
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2896414373
Short name T31
Test name
Test status
Simulation time 1533947140 ps
CPU time 66.7 seconds
Started Jul 06 05:47:14 PM PDT 24
Finished Jul 06 05:48:21 PM PDT 24
Peak memory 208744 kb
Host smart-51248d14-6dae-4356-8e02-7efaa21e2d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896414373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2896414373
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2288300831
Short name T760
Test name
Test status
Simulation time 23365601940 ps
CPU time 13.46 seconds
Started Jul 06 05:47:17 PM PDT 24
Finished Jul 06 05:47:31 PM PDT 24
Peak memory 264740 kb
Host smart-17eb5531-e534-4f26-b0f3-cb1ce193a56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288300831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2288300831
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.4034513203
Short name T852
Test name
Test status
Simulation time 1902116745 ps
CPU time 3.23 seconds
Started Jul 06 05:47:19 PM PDT 24
Finished Jul 06 05:47:23 PM PDT 24
Peak memory 224936 kb
Host smart-5b710d7b-25de-4f4d-9aa1-6060eaabdd80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034513203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.4034513203
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.642878835
Short name T440
Test name
Test status
Simulation time 1370627491 ps
CPU time 7.85 seconds
Started Jul 06 05:47:15 PM PDT 24
Finished Jul 06 05:47:23 PM PDT 24
Peak memory 213332 kb
Host smart-55bf01ec-600e-4b84-9eac-8897fa1a6e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642878835 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.642878835
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.3824859640
Short name T907
Test name
Test status
Simulation time 333040066 ps
CPU time 5.52 seconds
Started Jul 06 05:47:23 PM PDT 24
Finished Jul 06 05:47:28 PM PDT 24
Peak memory 205016 kb
Host smart-a4a5d574-07c0-488d-85b0-6bfb5c299df7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824859640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.3824859640
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2933489833
Short name T960
Test name
Test status
Simulation time 17670169 ps
CPU time 0.65 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:39:10 PM PDT 24
Peak memory 204616 kb
Host smart-010d7007-ab12-48ea-b005-91e4e09aa127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933489833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2933489833
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3345050808
Short name T836
Test name
Test status
Simulation time 229496622 ps
CPU time 1.76 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:38:57 PM PDT 24
Peak memory 213340 kb
Host smart-5977db83-a825-4aad-b49c-b2217d76302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345050808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3345050808
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.4119952083
Short name T890
Test name
Test status
Simulation time 1068741692 ps
CPU time 4.24 seconds
Started Jul 06 05:38:53 PM PDT 24
Finished Jul 06 05:38:58 PM PDT 24
Peak memory 241332 kb
Host smart-31ae1196-7317-403b-9365-7018f28d5b7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119952083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.4119952083
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2890905633
Short name T1111
Test name
Test status
Simulation time 13764565019 ps
CPU time 45.15 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:39:40 PM PDT 24
Peak memory 543596 kb
Host smart-4233348b-4924-4352-9fe4-387e49dff5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890905633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2890905633
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3596174774
Short name T750
Test name
Test status
Simulation time 2035966623 ps
CPU time 79.86 seconds
Started Jul 06 05:38:49 PM PDT 24
Finished Jul 06 05:40:09 PM PDT 24
Peak memory 454596 kb
Host smart-4bfe7e79-7db7-4ddc-af2e-abbb77172289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596174774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3596174774
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3839435892
Short name T1297
Test name
Test status
Simulation time 136638069 ps
CPU time 1.04 seconds
Started Jul 06 05:38:49 PM PDT 24
Finished Jul 06 05:38:51 PM PDT 24
Peak memory 204756 kb
Host smart-897af936-aff4-4c9b-9617-0bd3400548e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839435892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3839435892
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3360554133
Short name T526
Test name
Test status
Simulation time 757997102 ps
CPU time 4.72 seconds
Started Jul 06 05:38:54 PM PDT 24
Finished Jul 06 05:38:59 PM PDT 24
Peak memory 205004 kb
Host smart-3d1871d8-d3ab-4b00-acdd-6f35af0ef536
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360554133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3360554133
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3413869800
Short name T1323
Test name
Test status
Simulation time 11803470195 ps
CPU time 66.27 seconds
Started Jul 06 05:38:50 PM PDT 24
Finished Jul 06 05:39:57 PM PDT 24
Peak memory 878996 kb
Host smart-131d6ae7-4cd7-465a-8c90-785f9d7476d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413869800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3413869800
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.179081101
Short name T633
Test name
Test status
Simulation time 253012509 ps
CPU time 10.23 seconds
Started Jul 06 05:39:06 PM PDT 24
Finished Jul 06 05:39:17 PM PDT 24
Peak memory 205056 kb
Host smart-99494e91-a3a8-4cbf-aff3-9588d51e573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179081101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.179081101
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.47323740
Short name T701
Test name
Test status
Simulation time 1485037666 ps
CPU time 25.11 seconds
Started Jul 06 05:39:03 PM PDT 24
Finished Jul 06 05:39:29 PM PDT 24
Peak memory 365160 kb
Host smart-ea52202c-b95f-45a2-b0aa-b197b5821549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47323740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.47323740
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3780784413
Short name T979
Test name
Test status
Simulation time 30467020 ps
CPU time 0.74 seconds
Started Jul 06 05:38:54 PM PDT 24
Finished Jul 06 05:38:55 PM PDT 24
Peak memory 204760 kb
Host smart-3995a1b2-c48a-4afd-910f-04450ee7b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780784413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3780784413
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3538424604
Short name T942
Test name
Test status
Simulation time 23475219641 ps
CPU time 353.84 seconds
Started Jul 06 05:38:57 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 746372 kb
Host smart-efc44d0d-2e4b-4c67-85d0-ee8119625ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538424604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3538424604
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2523360631
Short name T834
Test name
Test status
Simulation time 2485737300 ps
CPU time 33.9 seconds
Started Jul 06 05:38:54 PM PDT 24
Finished Jul 06 05:39:28 PM PDT 24
Peak memory 205576 kb
Host smart-cbde68f1-971e-42a7-8ea4-1133c52bd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523360631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2523360631
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3147865896
Short name T1418
Test name
Test status
Simulation time 3304390329 ps
CPU time 32 seconds
Started Jul 06 05:38:49 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 431100 kb
Host smart-ad1b8d62-1643-473b-b4d8-461fa8320b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147865896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3147865896
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.4126721123
Short name T489
Test name
Test status
Simulation time 13424179905 ps
CPU time 1786.79 seconds
Started Jul 06 05:38:57 PM PDT 24
Finished Jul 06 06:08:44 PM PDT 24
Peak memory 3033156 kb
Host smart-ade1187e-ba0a-496f-9664-cb085168cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126721123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.4126721123
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1766421211
Short name T1167
Test name
Test status
Simulation time 3916589619 ps
CPU time 44.35 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:39:39 PM PDT 24
Peak memory 213328 kb
Host smart-44576fe6-e835-4bda-bd13-7e0748b455b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766421211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1766421211
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1006992691
Short name T1439
Test name
Test status
Simulation time 971283116 ps
CPU time 5.42 seconds
Started Jul 06 05:39:07 PM PDT 24
Finished Jul 06 05:39:12 PM PDT 24
Peak memory 209300 kb
Host smart-a79eddce-6482-48f0-9a02-8d36623c18a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006992691 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1006992691
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.99764258
Short name T861
Test name
Test status
Simulation time 953042799 ps
CPU time 1.01 seconds
Started Jul 06 05:39:00 PM PDT 24
Finished Jul 06 05:39:01 PM PDT 24
Peak memory 212976 kb
Host smart-e1a41639-cb41-43a9-9a39-5b4f09095915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99764258 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_acq.99764258
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1830839777
Short name T483
Test name
Test status
Simulation time 1007526705 ps
CPU time 1.17 seconds
Started Jul 06 05:39:04 PM PDT 24
Finished Jul 06 05:39:05 PM PDT 24
Peak memory 204752 kb
Host smart-318f8fc9-51c4-42a1-ac92-724aad4917d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830839777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1830839777
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3350656346
Short name T283
Test name
Test status
Simulation time 266692876 ps
CPU time 1.65 seconds
Started Jul 06 05:39:04 PM PDT 24
Finished Jul 06 05:39:06 PM PDT 24
Peak memory 204824 kb
Host smart-0cc57ebf-945e-49d4-b0cd-d99b8bf2d3a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350656346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3350656346
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.980806677
Short name T1360
Test name
Test status
Simulation time 281109534 ps
CPU time 1.18 seconds
Started Jul 06 05:39:03 PM PDT 24
Finished Jul 06 05:39:05 PM PDT 24
Peak memory 204836 kb
Host smart-62915b41-94b8-48b4-81de-4a182781295f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980806677 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.980806677
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3942031660
Short name T1387
Test name
Test status
Simulation time 352140121 ps
CPU time 2.61 seconds
Started Jul 06 05:39:05 PM PDT 24
Finished Jul 06 05:39:08 PM PDT 24
Peak memory 205068 kb
Host smart-c191a8e0-3e99-4a45-bb54-728d90062864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942031660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3942031660
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.847733162
Short name T888
Test name
Test status
Simulation time 917364690 ps
CPU time 5.41 seconds
Started Jul 06 05:38:57 PM PDT 24
Finished Jul 06 05:39:03 PM PDT 24
Peak memory 213360 kb
Host smart-cb3afe95-a77d-4bef-9710-446ddb59fa4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847733162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.847733162
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3155545913
Short name T1395
Test name
Test status
Simulation time 6417414955 ps
CPU time 74.77 seconds
Started Jul 06 05:38:59 PM PDT 24
Finished Jul 06 05:40:14 PM PDT 24
Peak memory 1633240 kb
Host smart-7241facc-5b60-4515-946a-da3f63a1877d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155545913 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3155545913
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.86270709
Short name T608
Test name
Test status
Simulation time 2812439709 ps
CPU time 13.76 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:39:09 PM PDT 24
Peak memory 205096 kb
Host smart-a6117843-35e3-40bc-9d53-44515e1bb89b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86270709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targe
t_smoke.86270709
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1008364774
Short name T1302
Test name
Test status
Simulation time 349169821 ps
CPU time 6.08 seconds
Started Jul 06 05:38:54 PM PDT 24
Finished Jul 06 05:39:00 PM PDT 24
Peak memory 204992 kb
Host smart-8e47a5ed-97e9-4e0c-97c3-647227be2bcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008364774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1008364774
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1406304263
Short name T28
Test name
Test status
Simulation time 28451093600 ps
CPU time 185.66 seconds
Started Jul 06 05:38:55 PM PDT 24
Finished Jul 06 05:42:01 PM PDT 24
Peak memory 2322536 kb
Host smart-598849e5-a25f-4de9-9ffc-1ff672e1d32e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406304263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1406304263
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3402872831
Short name T938
Test name
Test status
Simulation time 1801067512 ps
CPU time 8.03 seconds
Started Jul 06 05:39:01 PM PDT 24
Finished Jul 06 05:39:09 PM PDT 24
Peak memory 220648 kb
Host smart-e47765c9-f500-40e8-9d87-502f06cc59bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402872831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3402872831
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.421085553
Short name T1045
Test name
Test status
Simulation time 139673213 ps
CPU time 1.81 seconds
Started Jul 06 05:39:07 PM PDT 24
Finished Jul 06 05:39:09 PM PDT 24
Peak memory 205020 kb
Host smart-cdc76493-3177-4bcd-acfa-f49a8072b833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421085553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.421085553
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1698393029
Short name T913
Test name
Test status
Simulation time 30635083 ps
CPU time 0.68 seconds
Started Jul 06 05:39:19 PM PDT 24
Finished Jul 06 05:39:20 PM PDT 24
Peak memory 204616 kb
Host smart-f234d0e2-5ca7-4f23-b3be-66e5f63a1749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698393029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1698393029
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1252848940
Short name T1004
Test name
Test status
Simulation time 95215552 ps
CPU time 1.52 seconds
Started Jul 06 05:39:13 PM PDT 24
Finished Jul 06 05:39:14 PM PDT 24
Peak memory 213304 kb
Host smart-8f30e942-ffd0-4a90-aa4f-d2390ab527a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252848940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1252848940
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1702630188
Short name T1173
Test name
Test status
Simulation time 345945813 ps
CPU time 5.49 seconds
Started Jul 06 05:39:10 PM PDT 24
Finished Jul 06 05:39:16 PM PDT 24
Peak memory 240928 kb
Host smart-90f003a1-064d-4aff-b39a-8eca4fca4040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702630188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1702630188
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.683765823
Short name T973
Test name
Test status
Simulation time 2466375600 ps
CPU time 93.01 seconds
Started Jul 06 05:39:08 PM PDT 24
Finished Jul 06 05:40:42 PM PDT 24
Peak memory 814904 kb
Host smart-9ff042e9-bbf8-4cc6-afd9-2764af5fb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683765823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.683765823
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.18298643
Short name T361
Test name
Test status
Simulation time 18318382664 ps
CPU time 71.45 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:40:21 PM PDT 24
Peak memory 675152 kb
Host smart-3a6c3166-3e1d-485c-87f1-a3e3eca56750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18298643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.18298643
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3050408772
Short name T551
Test name
Test status
Simulation time 121023415 ps
CPU time 1.11 seconds
Started Jul 06 05:39:10 PM PDT 24
Finished Jul 06 05:39:11 PM PDT 24
Peak memory 204772 kb
Host smart-f267abe7-6bbf-4cec-a315-bb14f05e7e55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050408772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3050408772
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.369986016
Short name T392
Test name
Test status
Simulation time 266616648 ps
CPU time 4.98 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:39:14 PM PDT 24
Peak memory 204968 kb
Host smart-15d80b57-95bd-4976-bf5f-e0a6569bce3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369986016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.369986016
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1658761497
Short name T1009
Test name
Test status
Simulation time 4582483012 ps
CPU time 323.55 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:44:32 PM PDT 24
Peak memory 1312028 kb
Host smart-ee314068-3062-4e03-b823-6500032b5732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658761497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1658761497
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2291853519
Short name T44
Test name
Test status
Simulation time 1168941578 ps
CPU time 13.76 seconds
Started Jul 06 05:39:17 PM PDT 24
Finished Jul 06 05:39:31 PM PDT 24
Peak memory 204984 kb
Host smart-cf068e70-48b3-41c8-b7f1-0c83b86ca388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291853519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2291853519
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1781422364
Short name T285
Test name
Test status
Simulation time 3461880367 ps
CPU time 31.37 seconds
Started Jul 06 05:39:19 PM PDT 24
Finished Jul 06 05:39:50 PM PDT 24
Peak memory 310932 kb
Host smart-9ca63536-04b3-4763-b6e8-8d7fac93f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781422364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1781422364
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.4113866908
Short name T1158
Test name
Test status
Simulation time 86311288 ps
CPU time 0.71 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:39:10 PM PDT 24
Peak memory 204760 kb
Host smart-d0d03ec4-b799-4b67-96a5-044d9eff5bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113866908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.4113866908
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.586229837
Short name T328
Test name
Test status
Simulation time 12338419177 ps
CPU time 46.6 seconds
Started Jul 06 05:39:07 PM PDT 24
Finished Jul 06 05:39:54 PM PDT 24
Peak memory 221408 kb
Host smart-5f15245a-44d2-43a7-b12e-fe175bfa56a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586229837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.586229837
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.2261484024
Short name T1291
Test name
Test status
Simulation time 53371187 ps
CPU time 1.22 seconds
Started Jul 06 05:39:14 PM PDT 24
Finished Jul 06 05:39:16 PM PDT 24
Peak memory 205172 kb
Host smart-3111226b-c387-4278-8358-f7c0259af6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261484024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.2261484024
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1034475602
Short name T318
Test name
Test status
Simulation time 5836952800 ps
CPU time 68.03 seconds
Started Jul 06 05:39:09 PM PDT 24
Finished Jul 06 05:40:17 PM PDT 24
Peak memory 299932 kb
Host smart-b24d073a-859c-4ff8-ace8-fd353290261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034475602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1034475602
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2077487986
Short name T262
Test name
Test status
Simulation time 1878585104 ps
CPU time 16.55 seconds
Started Jul 06 05:39:12 PM PDT 24
Finished Jul 06 05:39:28 PM PDT 24
Peak memory 233772 kb
Host smart-5019c938-a36d-4545-98ea-4684182f486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077487986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2077487986
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3888387666
Short name T872
Test name
Test status
Simulation time 2667404051 ps
CPU time 10.54 seconds
Started Jul 06 05:39:17 PM PDT 24
Finished Jul 06 05:39:28 PM PDT 24
Peak memory 219104 kb
Host smart-82f731b9-a8b3-4a32-ab1c-c0b269c1b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888387666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3888387666
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3197584050
Short name T941
Test name
Test status
Simulation time 826753750 ps
CPU time 4.34 seconds
Started Jul 06 05:39:13 PM PDT 24
Finished Jul 06 05:39:18 PM PDT 24
Peak memory 214052 kb
Host smart-e468bd1a-2ce2-4ef4-b9ee-8e285e9b90c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197584050 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3197584050
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3775247795
Short name T1353
Test name
Test status
Simulation time 339870453 ps
CPU time 1.3 seconds
Started Jul 06 05:39:14 PM PDT 24
Finished Jul 06 05:39:16 PM PDT 24
Peak memory 213176 kb
Host smart-ec32e119-d037-47f1-8785-f9ffaeb9041d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775247795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3775247795
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.999553760
Short name T506
Test name
Test status
Simulation time 882365322 ps
CPU time 1.59 seconds
Started Jul 06 05:39:14 PM PDT 24
Finished Jul 06 05:39:16 PM PDT 24
Peak memory 205020 kb
Host smart-21beddbe-913c-42e4-b915-e5c64d848ad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999553760 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.999553760
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.107590031
Short name T1290
Test name
Test status
Simulation time 544333350 ps
CPU time 2.68 seconds
Started Jul 06 05:39:19 PM PDT 24
Finished Jul 06 05:39:22 PM PDT 24
Peak memory 204952 kb
Host smart-cef33a35-91f2-4282-825d-59eb201d350d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107590031 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.107590031
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.3244895483
Short name T1187
Test name
Test status
Simulation time 587139449 ps
CPU time 1.22 seconds
Started Jul 06 05:39:20 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 204804 kb
Host smart-1ac15cfc-91ad-45e8-9b0b-52c634652c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244895483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.3244895483
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3489417735
Short name T1222
Test name
Test status
Simulation time 1191776545 ps
CPU time 6.7 seconds
Started Jul 06 05:39:14 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 217256 kb
Host smart-a66fd78c-e1f5-4e9d-bcfc-3e06418a8e91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489417735 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3489417735
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1610379426
Short name T453
Test name
Test status
Simulation time 3809126997 ps
CPU time 8.67 seconds
Started Jul 06 05:39:12 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 205112 kb
Host smart-d6e248c3-3a25-49d1-a6b0-f3fbd4995a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610379426 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1610379426
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.334451266
Short name T583
Test name
Test status
Simulation time 909102739 ps
CPU time 36.71 seconds
Started Jul 06 05:39:17 PM PDT 24
Finished Jul 06 05:39:54 PM PDT 24
Peak memory 204468 kb
Host smart-f704e77d-908b-4b73-a868-b545fb4b686f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334451266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.334451266
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1380334142
Short name T1186
Test name
Test status
Simulation time 4237088193 ps
CPU time 77.16 seconds
Started Jul 06 05:39:15 PM PDT 24
Finished Jul 06 05:40:33 PM PDT 24
Peak memory 207772 kb
Host smart-40872832-af9c-40f2-a1c0-e0f5debbb7c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380334142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1380334142
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.4164620054
Short name T116
Test name
Test status
Simulation time 74017909018 ps
CPU time 2921.07 seconds
Started Jul 06 05:39:13 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 13241708 kb
Host smart-88a6f214-8b5c-4902-a9d2-23cda91b86f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164620054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.4164620054
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.323773222
Short name T1077
Test name
Test status
Simulation time 5410604575 ps
CPU time 68.38 seconds
Started Jul 06 05:39:13 PM PDT 24
Finished Jul 06 05:40:22 PM PDT 24
Peak memory 1225648 kb
Host smart-ac29df85-18cb-4555-9c9e-f342b1f90d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323773222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.323773222
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1209742910
Short name T1030
Test name
Test status
Simulation time 4529304089 ps
CPU time 6.34 seconds
Started Jul 06 05:39:14 PM PDT 24
Finished Jul 06 05:39:20 PM PDT 24
Peak memory 213356 kb
Host smart-ddf10ada-2d65-4c69-a144-537e7d4bfbbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209742910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1209742910
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.244351169
Short name T21
Test name
Test status
Simulation time 293723706 ps
CPU time 4.22 seconds
Started Jul 06 05:39:19 PM PDT 24
Finished Jul 06 05:39:23 PM PDT 24
Peak memory 204996 kb
Host smart-96a685c2-8244-4c7d-a7d2-97940f1f794a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244351169 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.244351169
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3568203714
Short name T104
Test name
Test status
Simulation time 36651808 ps
CPU time 0.6 seconds
Started Jul 06 05:39:29 PM PDT 24
Finished Jul 06 05:39:30 PM PDT 24
Peak memory 204608 kb
Host smart-5185b510-3982-4f66-aa61-f0f8a4704b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568203714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3568203714
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.848640575
Short name T366
Test name
Test status
Simulation time 72843902 ps
CPU time 1.29 seconds
Started Jul 06 05:39:24 PM PDT 24
Finished Jul 06 05:39:25 PM PDT 24
Peak memory 213328 kb
Host smart-94cd96cb-664f-41be-a02d-692b5064ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848640575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.848640575
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1026944322
Short name T1432
Test name
Test status
Simulation time 353624970 ps
CPU time 8.03 seconds
Started Jul 06 05:39:19 PM PDT 24
Finished Jul 06 05:39:28 PM PDT 24
Peak memory 275384 kb
Host smart-83a7ac73-4ec3-4c28-863e-18d700e30ffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026944322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1026944322
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2573064751
Short name T1022
Test name
Test status
Simulation time 2597125200 ps
CPU time 199.27 seconds
Started Jul 06 05:39:23 PM PDT 24
Finished Jul 06 05:42:43 PM PDT 24
Peak memory 754828 kb
Host smart-8f0f4b4d-4d19-485b-a86b-2c1c83300486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573064751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2573064751
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1643425209
Short name T320
Test name
Test status
Simulation time 24964365442 ps
CPU time 41.83 seconds
Started Jul 06 05:39:20 PM PDT 24
Finished Jul 06 05:40:02 PM PDT 24
Peak memory 581312 kb
Host smart-bf615f78-24b7-4e43-8598-e9b744bf587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643425209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1643425209
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3596420256
Short name T1155
Test name
Test status
Simulation time 326290596 ps
CPU time 1.12 seconds
Started Jul 06 05:39:20 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 204764 kb
Host smart-6c5125ec-4fad-407f-93cf-96e38892eb7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596420256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3596420256
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1058054610
Short name T660
Test name
Test status
Simulation time 161017351 ps
CPU time 4.12 seconds
Started Jul 06 05:39:27 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 232988 kb
Host smart-431f7619-a298-456b-b3ff-a8cc8d60e897
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058054610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1058054610
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2816445522
Short name T757
Test name
Test status
Simulation time 22522988266 ps
CPU time 136.57 seconds
Started Jul 06 05:39:22 PM PDT 24
Finished Jul 06 05:41:39 PM PDT 24
Peak memory 1470216 kb
Host smart-b121feaa-f262-4623-9305-18c22a913e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816445522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2816445522
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3948979937
Short name T1484
Test name
Test status
Simulation time 1752512395 ps
CPU time 7.72 seconds
Started Jul 06 05:39:27 PM PDT 24
Finished Jul 06 05:39:35 PM PDT 24
Peak memory 205008 kb
Host smart-c8f675c1-a77a-4956-b33c-07bb5ce8b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948979937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3948979937
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.939902709
Short name T222
Test name
Test status
Simulation time 11233832947 ps
CPU time 26.52 seconds
Started Jul 06 05:39:30 PM PDT 24
Finished Jul 06 05:39:57 PM PDT 24
Peak memory 376520 kb
Host smart-1a0da0a0-a37d-44b0-9884-d021119a9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939902709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.939902709
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.2297147166
Short name T480
Test name
Test status
Simulation time 27353083 ps
CPU time 0.64 seconds
Started Jul 06 05:39:20 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 204696 kb
Host smart-a951e170-b5c6-404d-a391-a0c33919e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297147166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2297147166
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1368391680
Short name T40
Test name
Test status
Simulation time 25586153311 ps
CPU time 348.94 seconds
Started Jul 06 05:39:26 PM PDT 24
Finished Jul 06 05:45:15 PM PDT 24
Peak memory 205076 kb
Host smart-5ddd9cba-d725-4a3b-8421-8a645ad15859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368391680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1368391680
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.1545064953
Short name T610
Test name
Test status
Simulation time 24649202500 ps
CPU time 326.71 seconds
Started Jul 06 05:39:24 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 751232 kb
Host smart-7a1ebdee-c24e-4766-a9d6-a40fab167f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545064953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.1545064953
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.328732189
Short name T434
Test name
Test status
Simulation time 4140164458 ps
CPU time 30.5 seconds
Started Jul 06 05:39:23 PM PDT 24
Finished Jul 06 05:39:53 PM PDT 24
Peak memory 355624 kb
Host smart-226bdb9d-ad59-4c55-a91a-d606eb66b1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328732189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.328732189
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2819571704
Short name T1381
Test name
Test status
Simulation time 788263356 ps
CPU time 35.19 seconds
Started Jul 06 05:39:25 PM PDT 24
Finished Jul 06 05:40:00 PM PDT 24
Peak memory 213140 kb
Host smart-e6546dd8-2b58-44cb-9e7b-c58f29e45363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819571704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2819571704
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.871603901
Short name T700
Test name
Test status
Simulation time 3389335266 ps
CPU time 4.42 seconds
Started Jul 06 05:39:27 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 213344 kb
Host smart-0e858b75-75b3-4549-9497-2f12518bdd00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871603901 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.871603901
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.497509770
Short name T1089
Test name
Test status
Simulation time 159525201 ps
CPU time 0.96 seconds
Started Jul 06 05:39:31 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 204840 kb
Host smart-71ad51d5-f696-415c-9420-4f0bdfc25ba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497509770 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.497509770
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3975351653
Short name T911
Test name
Test status
Simulation time 636810151 ps
CPU time 1.23 seconds
Started Jul 06 05:39:30 PM PDT 24
Finished Jul 06 05:39:31 PM PDT 24
Peak memory 204808 kb
Host smart-1bfc0fc0-bf7f-44c5-957e-1c13ec0fd4f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975351653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3975351653
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2517624627
Short name T1058
Test name
Test status
Simulation time 523430658 ps
CPU time 3.06 seconds
Started Jul 06 05:39:30 PM PDT 24
Finished Jul 06 05:39:33 PM PDT 24
Peak memory 205036 kb
Host smart-1be23ce8-fc33-45e5-8f27-cc06824f2b4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517624627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2517624627
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.2602772842
Short name T916
Test name
Test status
Simulation time 2018793692 ps
CPU time 1.34 seconds
Started Jul 06 05:39:31 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 204836 kb
Host smart-31c89e57-84a0-4510-9624-03dfb6170664
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602772842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2602772842
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3015697263
Short name T1461
Test name
Test status
Simulation time 897206806 ps
CPU time 4.67 seconds
Started Jul 06 05:39:25 PM PDT 24
Finished Jul 06 05:39:30 PM PDT 24
Peak memory 213212 kb
Host smart-06b91381-e70f-43fd-8e39-d7486b5d4d02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015697263 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3015697263
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.256850170
Short name T11
Test name
Test status
Simulation time 20220724129 ps
CPU time 414.64 seconds
Started Jul 06 05:39:32 PM PDT 24
Finished Jul 06 05:46:27 PM PDT 24
Peak memory 4784384 kb
Host smart-315ed3fd-1767-4fe1-8b1d-1a00eeb12aa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256850170 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.256850170
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3537712045
Short name T1061
Test name
Test status
Simulation time 5979194999 ps
CPU time 60.11 seconds
Started Jul 06 05:39:27 PM PDT 24
Finished Jul 06 05:40:27 PM PDT 24
Peak memory 205096 kb
Host smart-811fbe2a-014c-49d2-9386-875e3890f4bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537712045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3537712045
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2448969000
Short name T1216
Test name
Test status
Simulation time 949378548 ps
CPU time 13.12 seconds
Started Jul 06 05:39:24 PM PDT 24
Finished Jul 06 05:39:37 PM PDT 24
Peak memory 208596 kb
Host smart-911862e6-ee11-4bb4-bb19-fd59532dbc2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448969000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2448969000
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1069049787
Short name T893
Test name
Test status
Simulation time 35189872546 ps
CPU time 139.66 seconds
Started Jul 06 05:39:25 PM PDT 24
Finished Jul 06 05:41:45 PM PDT 24
Peak memory 2051476 kb
Host smart-b1b24d0c-a218-4248-95d2-8450349b1440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069049787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1069049787
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1700415759
Short name T479
Test name
Test status
Simulation time 5003837053 ps
CPU time 100.91 seconds
Started Jul 06 05:39:26 PM PDT 24
Finished Jul 06 05:41:07 PM PDT 24
Peak memory 1356732 kb
Host smart-efdade78-a2b5-4280-a581-8e1825e65f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700415759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1700415759
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1171714846
Short name T69
Test name
Test status
Simulation time 2784617188 ps
CPU time 7.53 seconds
Started Jul 06 05:39:30 PM PDT 24
Finished Jul 06 05:39:38 PM PDT 24
Peak memory 213316 kb
Host smart-64c2744f-61e5-4c25-b500-30de477f9c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171714846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1171714846
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2704917259
Short name T541
Test name
Test status
Simulation time 96141927 ps
CPU time 1.55 seconds
Started Jul 06 05:39:29 PM PDT 24
Finished Jul 06 05:39:31 PM PDT 24
Peak memory 205016 kb
Host smart-b74db1c2-7a12-423d-ba7d-5b81760b9c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704917259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2704917259
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1542978784
Short name T316
Test name
Test status
Simulation time 19230358 ps
CPU time 0.63 seconds
Started Jul 06 05:39:47 PM PDT 24
Finished Jul 06 05:39:48 PM PDT 24
Peak memory 204620 kb
Host smart-24aecbf0-1584-4939-ae5a-e1be0f942d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542978784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1542978784
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3402354373
Short name T611
Test name
Test status
Simulation time 135131003 ps
CPU time 1.99 seconds
Started Jul 06 05:39:38 PM PDT 24
Finished Jul 06 05:39:40 PM PDT 24
Peak memory 213324 kb
Host smart-2bd00e0f-6b5d-4bd4-9e76-49c4240c5fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402354373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3402354373
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3385510209
Short name T1495
Test name
Test status
Simulation time 298221853 ps
CPU time 6.44 seconds
Started Jul 06 05:39:35 PM PDT 24
Finished Jul 06 05:39:42 PM PDT 24
Peak memory 260612 kb
Host smart-a8db20b6-e93c-47f5-9649-be4bca4c08ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385510209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3385510209
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2319666483
Short name T769
Test name
Test status
Simulation time 25601969210 ps
CPU time 85.83 seconds
Started Jul 06 05:39:34 PM PDT 24
Finished Jul 06 05:41:00 PM PDT 24
Peak memory 743112 kb
Host smart-c029e194-8034-420d-92b0-7d3069047885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319666483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2319666483
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3179120299
Short name T825
Test name
Test status
Simulation time 2756250129 ps
CPU time 104.31 seconds
Started Jul 06 05:39:34 PM PDT 24
Finished Jul 06 05:41:18 PM PDT 24
Peak memory 847956 kb
Host smart-6a5e5d61-9e9c-4570-abf4-eb38306a954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179120299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3179120299
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2257130695
Short name T1217
Test name
Test status
Simulation time 291434021 ps
CPU time 0.89 seconds
Started Jul 06 05:39:36 PM PDT 24
Finished Jul 06 05:39:37 PM PDT 24
Peak memory 204752 kb
Host smart-c60a1487-443e-4d6c-af5c-a12172e86d0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257130695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2257130695
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2953594198
Short name T1015
Test name
Test status
Simulation time 1449170394 ps
CPU time 3.46 seconds
Started Jul 06 05:39:34 PM PDT 24
Finished Jul 06 05:39:37 PM PDT 24
Peak memory 225372 kb
Host smart-ab76ff91-537a-4bdf-903b-a36512b04b5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953594198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2953594198
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.972461304
Short name T1169
Test name
Test status
Simulation time 24197518924 ps
CPU time 308.17 seconds
Started Jul 06 05:39:34 PM PDT 24
Finished Jul 06 05:44:42 PM PDT 24
Peak memory 1231260 kb
Host smart-f8facd58-d051-412a-92ca-da512cc71f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972461304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.972461304
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1237635659
Short name T1215
Test name
Test status
Simulation time 1079370190 ps
CPU time 15.88 seconds
Started Jul 06 05:39:47 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 205048 kb
Host smart-22db0b2c-fbd3-495a-8204-5309fd2e54dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237635659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1237635659
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1494022725
Short name T65
Test name
Test status
Simulation time 2498855316 ps
CPU time 58.98 seconds
Started Jul 06 05:39:49 PM PDT 24
Finished Jul 06 05:40:48 PM PDT 24
Peak memory 341128 kb
Host smart-d023cd29-8f8f-46a1-87b5-6ec2caf8ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494022725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1494022725
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1770825286
Short name T126
Test name
Test status
Simulation time 100821610 ps
CPU time 0.7 seconds
Started Jul 06 05:39:33 PM PDT 24
Finished Jul 06 05:39:34 PM PDT 24
Peak memory 204688 kb
Host smart-60625849-f77b-4bfe-8592-f030228d8bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770825286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1770825286
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1238345947
Short name T393
Test name
Test status
Simulation time 681394612 ps
CPU time 3.45 seconds
Started Jul 06 05:39:32 PM PDT 24
Finished Jul 06 05:39:36 PM PDT 24
Peak memory 219564 kb
Host smart-e084d039-d87e-4a16-bc94-2fde08ef2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238345947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1238345947
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2037075358
Short name T753
Test name
Test status
Simulation time 41258905 ps
CPU time 1.83 seconds
Started Jul 06 05:39:35 PM PDT 24
Finished Jul 06 05:39:37 PM PDT 24
Peak memory 205524 kb
Host smart-7b3deab5-8538-447e-a07e-8bc65c6bc658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037075358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2037075358
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.4067477977
Short name T1518
Test name
Test status
Simulation time 1901552758 ps
CPU time 34.61 seconds
Started Jul 06 05:39:32 PM PDT 24
Finished Jul 06 05:40:07 PM PDT 24
Peak memory 334308 kb
Host smart-3a08dc51-48ff-4acb-8cbf-d3a47ced0cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067477977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.4067477977
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3480237263
Short name T248
Test name
Test status
Simulation time 12083329854 ps
CPU time 11.62 seconds
Started Jul 06 05:39:37 PM PDT 24
Finished Jul 06 05:39:48 PM PDT 24
Peak memory 220656 kb
Host smart-cc3b3ba7-877a-4c95-8fde-a1b26e4664ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480237263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3480237263
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.510828378
Short name T1146
Test name
Test status
Simulation time 637793603 ps
CPU time 3.84 seconds
Started Jul 06 05:39:45 PM PDT 24
Finished Jul 06 05:39:49 PM PDT 24
Peak memory 212964 kb
Host smart-081a10de-1e08-4333-9607-0f09ddf19f54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510828378 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.510828378
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3083422294
Short name T658
Test name
Test status
Simulation time 254104613 ps
CPU time 1.04 seconds
Started Jul 06 05:39:43 PM PDT 24
Finished Jul 06 05:39:44 PM PDT 24
Peak memory 204836 kb
Host smart-c310f881-e744-48d6-9050-248b844ac0e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083422294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3083422294
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1784777864
Short name T188
Test name
Test status
Simulation time 145796074 ps
CPU time 1.04 seconds
Started Jul 06 05:39:41 PM PDT 24
Finished Jul 06 05:39:42 PM PDT 24
Peak memory 204836 kb
Host smart-f50749b2-2f20-409d-b47b-910134fc2c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784777864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1784777864
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.415193634
Short name T588
Test name
Test status
Simulation time 881616422 ps
CPU time 2.15 seconds
Started Jul 06 05:39:48 PM PDT 24
Finished Jul 06 05:39:51 PM PDT 24
Peak memory 204984 kb
Host smart-9181cf33-2a1f-4755-8e0b-c92bbab33613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415193634 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.415193634
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.2372420601
Short name T416
Test name
Test status
Simulation time 909495421 ps
CPU time 1.15 seconds
Started Jul 06 05:39:49 PM PDT 24
Finished Jul 06 05:39:51 PM PDT 24
Peak memory 204828 kb
Host smart-f9e7b574-3501-4972-beef-aad88be4d650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372420601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.2372420601
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.415014845
Short name T1326
Test name
Test status
Simulation time 10586587156 ps
CPU time 8.15 seconds
Started Jul 06 05:39:45 PM PDT 24
Finished Jul 06 05:39:53 PM PDT 24
Peak memory 213908 kb
Host smart-3c5846d4-6c2c-4fc2-a370-c25f79206e0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415014845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.415014845
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1813755008
Short name T1176
Test name
Test status
Simulation time 16610494003 ps
CPU time 21.87 seconds
Started Jul 06 05:39:41 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 519676 kb
Host smart-97ad4624-49b5-480c-aa82-b6aad3e6fedb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813755008 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1813755008
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1478459714
Short name T1033
Test name
Test status
Simulation time 1818581263 ps
CPU time 36.69 seconds
Started Jul 06 05:39:38 PM PDT 24
Finished Jul 06 05:40:15 PM PDT 24
Peak memory 204992 kb
Host smart-d5a740f2-007c-4165-8846-e5cfd55c5860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478459714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1478459714
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.689916084
Short name T1122
Test name
Test status
Simulation time 2619187913 ps
CPU time 24.05 seconds
Started Jul 06 05:39:39 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 219652 kb
Host smart-73d3cbc0-f6dd-41ce-a3ad-6ec962d99b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689916084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.689916084
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.141222931
Short name T419
Test name
Test status
Simulation time 13937026862 ps
CPU time 13.01 seconds
Started Jul 06 05:39:40 PM PDT 24
Finished Jul 06 05:39:53 PM PDT 24
Peak memory 205068 kb
Host smart-eca906e9-1a33-4846-bfc1-14fb63992cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141222931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.141222931
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.876218874
Short name T266
Test name
Test status
Simulation time 2602374400 ps
CPU time 10.14 seconds
Started Jul 06 05:39:37 PM PDT 24
Finished Jul 06 05:39:48 PM PDT 24
Peak memory 311736 kb
Host smart-df6fec55-6da6-4940-b7e4-701aa06f0969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876218874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ta
rget_stretch.876218874
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1102572823
Short name T596
Test name
Test status
Simulation time 5557731141 ps
CPU time 8.46 seconds
Started Jul 06 05:39:42 PM PDT 24
Finished Jul 06 05:39:51 PM PDT 24
Peak memory 221404 kb
Host smart-83d2b386-ac12-4b49-b4d4-0c58e2c60887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102572823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1102572823
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.771846177
Short name T563
Test name
Test status
Simulation time 564523392 ps
CPU time 7.15 seconds
Started Jul 06 05:39:49 PM PDT 24
Finished Jul 06 05:39:56 PM PDT 24
Peak memory 205048 kb
Host smart-d80ffe56-db5c-4d7c-83e0-d3a99979f398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771846177 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.771846177
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.4274693338
Short name T80
Test name
Test status
Simulation time 41115724 ps
CPU time 0.65 seconds
Started Jul 06 05:40:04 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 204628 kb
Host smart-f5b9ee68-91c6-4b2f-bee1-d467c02e1da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274693338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.4274693338
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1281796387
Short name T5
Test name
Test status
Simulation time 71471462 ps
CPU time 1.36 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:39:54 PM PDT 24
Peak memory 213312 kb
Host smart-a026e68d-c80d-4f5b-9d17-100bd8e24d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281796387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1281796387
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3976515160
Short name T1337
Test name
Test status
Simulation time 4991945947 ps
CPU time 11.04 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 323944 kb
Host smart-e04095d9-c70a-4fca-acc7-9d0df4a30b38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976515160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3976515160
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1954287960
Short name T47
Test name
Test status
Simulation time 2412609122 ps
CPU time 134.49 seconds
Started Jul 06 05:39:52 PM PDT 24
Finished Jul 06 05:42:07 PM PDT 24
Peak memory 480368 kb
Host smart-b20a5415-a87e-4846-8aad-142392e5fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954287960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1954287960
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1581545079
Short name T755
Test name
Test status
Simulation time 6151663207 ps
CPU time 43.71 seconds
Started Jul 06 05:39:48 PM PDT 24
Finished Jul 06 05:40:32 PM PDT 24
Peak memory 572676 kb
Host smart-e5172e0c-5018-474f-873e-2c58ad3c5920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581545079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1581545079
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3813316631
Short name T1454
Test name
Test status
Simulation time 424917923 ps
CPU time 1.03 seconds
Started Jul 06 05:39:48 PM PDT 24
Finished Jul 06 05:39:49 PM PDT 24
Peak memory 204764 kb
Host smart-0f0cd5df-d2f2-499f-845e-9b349f6d0031
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813316631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3813316631
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3281309969
Short name T1425
Test name
Test status
Simulation time 295010732 ps
CPU time 3.49 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:39:57 PM PDT 24
Peak memory 205016 kb
Host smart-fc111545-e4f4-42f2-8500-03da38b6acbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281309969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3281309969
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.702987217
Short name T100
Test name
Test status
Simulation time 14479113585 ps
CPU time 79.52 seconds
Started Jul 06 05:39:48 PM PDT 24
Finished Jul 06 05:41:08 PM PDT 24
Peak memory 972196 kb
Host smart-32777eaf-06a5-4740-ab59-12167bad4403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702987217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.702987217
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2939426655
Short name T495
Test name
Test status
Simulation time 286514230 ps
CPU time 12.72 seconds
Started Jul 06 05:40:00 PM PDT 24
Finished Jul 06 05:40:13 PM PDT 24
Peak memory 205044 kb
Host smart-21a1e54c-4ebc-40b2-b189-e67697e154c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939426655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2939426655
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3163736497
Short name T476
Test name
Test status
Simulation time 5373464586 ps
CPU time 58.84 seconds
Started Jul 06 05:39:57 PM PDT 24
Finished Jul 06 05:40:57 PM PDT 24
Peak memory 308720 kb
Host smart-a513a374-3ce4-4b6f-9f1a-2078200ae766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163736497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3163736497
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.580703894
Short name T122
Test name
Test status
Simulation time 154876644 ps
CPU time 0.7 seconds
Started Jul 06 05:39:51 PM PDT 24
Finished Jul 06 05:39:52 PM PDT 24
Peak memory 204740 kb
Host smart-6dae2514-8626-4b89-96c2-d5780777a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580703894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.580703894
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3209721425
Short name T41
Test name
Test status
Simulation time 13535326709 ps
CPU time 23.7 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:40:17 PM PDT 24
Peak memory 436476 kb
Host smart-ae423fde-26f6-443e-a74f-4d3e6c5eb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209721425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3209721425
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.659185394
Short name T959
Test name
Test status
Simulation time 6043015205 ps
CPU time 74.51 seconds
Started Jul 06 05:39:54 PM PDT 24
Finished Jul 06 05:41:09 PM PDT 24
Peak memory 205028 kb
Host smart-78b21dfe-51cd-4d80-8acb-599b4766d68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659185394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.659185394
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2293373342
Short name T829
Test name
Test status
Simulation time 7719346821 ps
CPU time 36.98 seconds
Started Jul 06 05:39:50 PM PDT 24
Finished Jul 06 05:40:27 PM PDT 24
Peak memory 348320 kb
Host smart-65beb057-6664-4482-bb67-f7123a6725c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293373342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2293373342
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.4198369604
Short name T107
Test name
Test status
Simulation time 154294284986 ps
CPU time 442.76 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:47:17 PM PDT 24
Peak memory 1670796 kb
Host smart-4980eac1-a0e6-4b63-b5c5-0a4d53ef8915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198369604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.4198369604
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1162128329
Short name T1462
Test name
Test status
Simulation time 2164594241 ps
CPU time 25.58 seconds
Started Jul 06 05:39:54 PM PDT 24
Finished Jul 06 05:40:20 PM PDT 24
Peak memory 213284 kb
Host smart-ae7a32d4-4ed8-4c8e-b256-83e72f664d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162128329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1162128329
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.4191597556
Short name T1144
Test name
Test status
Simulation time 1354345149 ps
CPU time 4.07 seconds
Started Jul 06 05:40:00 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 213264 kb
Host smart-804cde98-685f-40eb-aaad-9c48b74bf541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191597556 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.4191597556
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2435236561
Short name T265
Test name
Test status
Simulation time 575522300 ps
CPU time 1.6 seconds
Started Jul 06 05:39:58 PM PDT 24
Finished Jul 06 05:40:00 PM PDT 24
Peak memory 209348 kb
Host smart-cb4e40ec-d1cc-486f-92b5-4db74ef6a409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435236561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2435236561
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.4231161420
Short name T379
Test name
Test status
Simulation time 206485821 ps
CPU time 1.29 seconds
Started Jul 06 05:40:00 PM PDT 24
Finished Jul 06 05:40:02 PM PDT 24
Peak memory 204780 kb
Host smart-51f9126a-04a0-4e8b-87f8-6034e96a71af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231161420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.4231161420
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1270338668
Short name T1086
Test name
Test status
Simulation time 2652403477 ps
CPU time 2.68 seconds
Started Jul 06 05:40:05 PM PDT 24
Finished Jul 06 05:40:08 PM PDT 24
Peak memory 205068 kb
Host smart-3b3d1bd6-0cba-436e-8e8a-f9459c25d3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270338668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1270338668
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3439689615
Short name T553
Test name
Test status
Simulation time 246970381 ps
CPU time 1.19 seconds
Started Jul 06 05:40:03 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 204800 kb
Host smart-438fc943-14b8-48f4-9bff-8306d9f06dec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439689615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3439689615
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2789908524
Short name T1369
Test name
Test status
Simulation time 737113690 ps
CPU time 4.6 seconds
Started Jul 06 05:39:57 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 208236 kb
Host smart-dd580905-ac7a-4bba-80d5-b2aacda03f03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789908524 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2789908524
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2183111836
Short name T618
Test name
Test status
Simulation time 5388448946 ps
CPU time 9.78 seconds
Started Jul 06 05:40:00 PM PDT 24
Finished Jul 06 05:40:10 PM PDT 24
Peak memory 205084 kb
Host smart-3b6d7ff7-54b1-4d0d-bf46-79fcadd4aa04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183111836 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2183111836
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.406556929
Short name T1138
Test name
Test status
Simulation time 943721426 ps
CPU time 32.62 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:40:26 PM PDT 24
Peak memory 204944 kb
Host smart-f17e052d-53a7-40d1-98e1-403ac8189cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406556929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.406556929
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2617371322
Short name T891
Test name
Test status
Simulation time 1913985560 ps
CPU time 78.02 seconds
Started Jul 06 05:39:54 PM PDT 24
Finished Jul 06 05:41:12 PM PDT 24
Peak memory 208320 kb
Host smart-1d77eeba-7857-4f0b-97c2-bf33bd248e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617371322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2617371322
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2120994574
Short name T1295
Test name
Test status
Simulation time 70729751283 ps
CPU time 335.93 seconds
Started Jul 06 05:39:53 PM PDT 24
Finished Jul 06 05:45:29 PM PDT 24
Peak memory 3271864 kb
Host smart-1c57ca4c-878f-49fe-9b0b-8c10d6ef9b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120994574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2120994574
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3664988441
Short name T117
Test name
Test status
Simulation time 2258310775 ps
CPU time 5.6 seconds
Started Jul 06 05:39:59 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 237132 kb
Host smart-bed8ab42-a184-447c-9019-e781c6f70eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664988441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3664988441
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3471382673
Short name T1363
Test name
Test status
Simulation time 5908773371 ps
CPU time 7.9 seconds
Started Jul 06 05:39:57 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 221288 kb
Host smart-19610dab-2c79-4240-b129-94efb2ccf0d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471382673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3471382673
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.705278510
Short name T678
Test name
Test status
Simulation time 107488034 ps
CPU time 2.12 seconds
Started Jul 06 05:40:04 PM PDT 24
Finished Jul 06 05:40:06 PM PDT 24
Peak memory 205020 kb
Host smart-7c161014-56a1-4bae-9175-3e0a5fa7655c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705278510 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.705278510
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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