Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.87	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	8	52	86.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	8	52	86.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	656911	1			T1	2		T2	2		T3	190
all_values[1]	656911	1			T1	2		T2	2		T3	190
all_values[2]	656911	1			T1	2		T2	2		T3	190
all_values[3]	656911	1			T1	2		T2	2		T3	190
all_values[4]	656911	1			T1	2		T2	2		T3	190
all_values[5]	656911	1			T1	2		T2	2		T3	190
all_values[6]	656911	1			T1	2		T2	2		T3	190
all_values[7]	656911	1			T1	2		T2	2		T3	190
all_values[8]	656911	1			T1	2		T2	2		T3	190
all_values[9]	656911	1			T1	2		T2	2		T3	190
all_values[10]	656911	1			T1	2		T2	2		T3	190
all_values[11]	656911	1			T1	2		T2	2		T3	190
all_values[12]	656911	1			T1	2		T2	2		T3	190
all_values[13]	656911	1			T1	2		T2	2		T3	190
all_values[14]	656911	1			T1	2		T2	2		T3	190

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8097269

1

T1

26

T2

26

T3

2424

auto[1]

1756396

1

T1

4

T2

4

T3

426

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9597011

1

T1

30

T2

30

T3

2850

auto[1]

256654

1

T20

252109

T157

460

T70

273

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	8	52	86.67	8

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3] , all_values[4] , all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	4
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	94653	1			T3	3		T4	1		T5	146
all_values[0]	auto[0]	auto[1]	184	1			T157	20		T70	8		T263	2
all_values[0]	auto[1]	auto[0]	561951	1			T1	2		T2	2		T3	187
all_values[0]	auto[1]	auto[1]	123	1			T157	11		T70	11		T263	1
all_values[1]	auto[0]	auto[0]	637081	1			T1	2		T2	2		T3	190
all_values[1]	auto[0]	auto[1]	19585	1			T20	19392		T157	26		T70	17
all_values[1]	auto[1]	auto[0]	131	1			T7	1		T40	1		T152	1
all_values[1]	auto[1]	auto[1]	114	1			T20	2		T157	6		T70	3
all_values[2]	auto[0]	auto[0]	637039	1			T1	2		T2	2		T3	190
all_values[2]	auto[0]	auto[1]	19558	1			T20	19392		T157	22		T70	6
all_values[2]	auto[1]	auto[0]	193	1			T9	1		T48	1		T173	1
all_values[2]	auto[1]	auto[1]	121	1			T20	1		T157	10		T70	6
all_values[3]	auto[0]	auto[0]	656592	1			T1	2		T2	2		T3	190
all_values[3]	auto[0]	auto[1]	188	1			T157	26		T70	9		T263	3
all_values[3]	auto[1]	auto[1]	131	1			T157	6		T70	2		T263	2
all_values[4]	auto[0]	auto[0]	637215	1			T1	2		T2	2		T3	190
all_values[4]	auto[0]	auto[1]	19582	1			T20	19391		T157	24		T70	16
all_values[4]	auto[1]	auto[1]	114	1			T20	1		T157	3		T70	4
all_values[5]	auto[0]	auto[0]	637203	1			T1	2		T2	2		T3	190
all_values[5]	auto[0]	auto[1]	19561	1			T20	19393		T157	26		T70	15
all_values[5]	auto[1]	auto[1]	147	1			T20	1		T157	6		T70	4
all_values[6]	auto[0]	auto[0]	637211	1			T1	2		T2	2		T3	190
all_values[6]	auto[0]	auto[1]	19566	1			T20	19390		T157	23		T70	14
all_values[6]	auto[1]	auto[1]	134	1			T20	2		T157	9		T70	5
all_values[7]	auto[0]	auto[0]	617676	1			T1	2		T2	2		T3	143
all_values[7]	auto[0]	auto[1]	19194	1			T20	19030		T157	23		T70	12
all_values[7]	auto[1]	auto[0]	19542	1			T3	47		T4	1		T5	139
all_values[7]	auto[1]	auto[1]	499	1			T20	362		T157	7		T70	7
all_values[8]	auto[0]	auto[0]	637216	1			T1	2		T2	2		T3	190
all_values[8]	auto[0]	auto[1]	19548	1			T20	19392		T157	18		T70	16
all_values[8]	auto[1]	auto[1]	147	1			T157	12		T70	3		T263	3
all_values[9]	auto[0]	auto[0]	137431	1			T1	2		T2	2		T3	185
all_values[9]	auto[0]	auto[1]	1867	1			T20	1713		T157	17		T70	8
all_values[9]	auto[1]	auto[0]	499783	1			T3	5		T4	1		T5	3266
all_values[9]	auto[1]	auto[1]	17830	1			T20	17681		T157	11		T70	10
all_values[10]	auto[0]	auto[0]	637222	1			T1	2		T2	2		T3	190
all_values[10]	auto[0]	auto[1]	19578	1			T20	19391		T157	24		T70	15
all_values[10]	auto[1]	auto[1]	111	1			T20	2		T157	8		T70	4
all_values[11]	auto[0]	auto[0]	1833	1			T3	3		T4	1		T5	9
all_values[11]	auto[0]	auto[1]	184	1			T20	11		T157	22		T70	6
all_values[11]	auto[1]	auto[0]	635378	1			T1	2		T2	2		T3	187
all_values[11]	auto[1]	auto[1]	19516	1			T20	19382		T157	10		T70	14
all_values[12]	auto[0]	auto[0]	637156	1			T1	2		T2	2		T3	190
all_values[12]	auto[0]	auto[1]	19585	1			T20	19392		T157	24		T70	14
all_values[12]	auto[1]	auto[0]	66	1			T48	1		T264	1		T265	1
all_values[12]	auto[1]	auto[1]	104	1			T20	2		T157	5		T70	4
all_values[13]	auto[0]	auto[0]	637220	1			T1	2		T2	2		T3	190
all_values[13]	auto[0]	auto[1]	19554	1			T20	19392		T157	19		T70	16
all_values[13]	auto[1]	auto[1]	137	1			T20	1		T157	10		T70	4
all_values[14]	auto[0]	auto[0]	637219	1			T1	2		T2	2		T3	190
all_values[14]	auto[0]	auto[1]	19568	1			T20	19392		T157	29		T70	15
all_values[14]	auto[1]	auto[1]	124	1			T20	1		T157	3		T70	5