Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	656911	1			T1	2		T2	2		T3	190
all_pins[1]	656911	1			T1	2		T2	2		T3	190
all_pins[2]	656911	1			T1	2		T2	2		T3	190
all_pins[3]	656911	1			T1	2		T2	2		T3	190
all_pins[4]	656911	1			T1	2		T2	2		T3	190
all_pins[5]	656911	1			T1	2		T2	2		T3	190
all_pins[6]	656911	1			T1	2		T2	2		T3	190
all_pins[7]	656911	1			T1	2		T2	2		T3	190
all_pins[8]	656911	1			T1	2		T2	2		T3	190
all_pins[9]	656911	1			T1	2		T2	2		T3	190
all_pins[10]	656911	1			T1	2		T2	2		T3	190
all_pins[11]	656911	1			T1	2		T2	2		T3	190
all_pins[12]	656911	1			T1	2		T2	2		T3	190
all_pins[13]	656911	1			T1	2		T2	2		T3	190
all_pins[14]	656911	1			T1	2		T2	2		T3	190

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8095911	1			T1	26		T2	26		T3	2417
values[0x1]	1757754	1			T1	4		T2	4		T3	433
transitions[0x0=>0x1]	1757362	1			T1	4		T2	4		T3	433
transitions[0x1=>0x0]	1756282	1			T1	3		T2	3		T3	432

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95020	1			T3	3		T4	1		T5	146
all_pins[0]	values[0x1]	561891	1			T1	2		T2	2		T3	187
all_pins[0]	transitions[0x0=>0x1]	561713	1			T1	2		T2	2		T3	187
all_pins[0]	transitions[0x1=>0x0]	45	1			T157	4		T70	1		T274	1
all_pins[1]	values[0x0]	656688	1			T1	2		T2	2		T3	190
all_pins[1]	values[0x1]	223	1			T7	1		T40	1		T152	1
all_pins[1]	transitions[0x0=>0x1]	207	1			T7	1		T40	1		T152	1
all_pins[1]	transitions[0x1=>0x0]	101	1			T9	1		T173	1		T264	1
all_pins[2]	values[0x0]	656794	1			T1	2		T2	2		T3	190
all_pins[2]	values[0x1]	117	1			T9	1		T173	1		T264	1
all_pins[2]	transitions[0x0=>0x1]	102	1			T9	1		T173	1		T264	1
all_pins[2]	transitions[0x1=>0x0]	49	1			T157	1		T263	1		T275	1
all_pins[3]	values[0x0]	656847	1			T1	2		T2	2		T3	190
all_pins[3]	values[0x1]	64	1			T157	1		T263	1		T275	1
all_pins[3]	transitions[0x0=>0x1]	52	1			T157	1		T263	1		T275	1
all_pins[3]	transitions[0x1=>0x0]	45	1			T20	1		T157	1		T70	3
all_pins[4]	values[0x0]	656854	1			T1	2		T2	2		T3	190
all_pins[4]	values[0x1]	57	1			T20	1		T157	1		T70	3
all_pins[4]	transitions[0x0=>0x1]	43	1			T20	1		T157	1		T70	3
all_pins[4]	transitions[0x1=>0x0]	62	1			T20	1		T157	3		T70	3
all_pins[5]	values[0x0]	656835	1			T1	2		T2	2		T3	190
all_pins[5]	values[0x1]	76	1			T20	1		T157	3		T70	3
all_pins[5]	transitions[0x0=>0x1]	65	1			T20	1		T157	2		T70	2
all_pins[5]	transitions[0x1=>0x0]	47	1			T157	3		T70	2		T275	1
all_pins[6]	values[0x0]	656853	1			T1	2		T2	2		T3	190
all_pins[6]	values[0x1]	58	1			T157	4		T70	3		T263	1
all_pins[6]	transitions[0x0=>0x1]	44	1			T157	2		T70	2		T263	1
all_pins[6]	transitions[0x1=>0x0]	22678	1			T3	54		T4	1		T5	152
all_pins[7]	values[0x0]	634219	1			T1	2		T2	2		T3	136
all_pins[7]	values[0x1]	22692	1			T3	54		T4	1		T5	152
all_pins[7]	transitions[0x0=>0x1]	22679	1			T3	54		T4	1		T5	152
all_pins[7]	transitions[0x1=>0x0]	63	1			T157	4		T70	1		T263	3
all_pins[8]	values[0x0]	656835	1			T1	2		T2	2		T3	190
all_pins[8]	values[0x1]	76	1			T157	6		T70	3		T263	3
all_pins[8]	transitions[0x0=>0x1]	59	1			T157	3		T70	3		T263	2
all_pins[8]	transitions[0x1=>0x0]	517548	1			T3	5		T4	1		T5	3266
all_pins[9]	values[0x0]	139346	1			T1	2		T2	2		T3	185
all_pins[9]	values[0x1]	517565	1			T3	5		T4	1		T5	3266
all_pins[9]	transitions[0x0=>0x1]	517552	1			T3	5		T4	1		T5	3266
all_pins[9]	transitions[0x1=>0x0]	40	1			T157	1		T263	1		T275	1
all_pins[10]	values[0x0]	656858	1			T1	2		T2	2		T3	190
all_pins[10]	values[0x1]	53	1			T157	1		T70	3		T263	1
all_pins[10]	transitions[0x0=>0x1]	40	1			T157	1		T70	3		T276	1
all_pins[10]	transitions[0x1=>0x0]	654616	1			T1	2		T2	2		T3	187
all_pins[11]	values[0x0]	2282	1			T3	3		T4	1		T5	9
all_pins[11]	values[0x1]	654629	1			T1	2		T2	2		T3	187
all_pins[11]	transitions[0x0=>0x1]	654602	1			T1	2		T2	2		T3	187
all_pins[11]	transitions[0x1=>0x0]	86	1			T48	1		T20	1		T55	1
all_pins[12]	values[0x0]	656798	1			T1	2		T2	2		T3	190
all_pins[12]	values[0x1]	113	1			T48	1		T264	1		T20	1
all_pins[12]	transitions[0x0=>0x1]	105	1			T48	1		T264	1		T20	1
all_pins[12]	transitions[0x1=>0x0]	61	1			T20	1		T157	5		T70	2
all_pins[13]	values[0x0]	656842	1			T1	2		T2	2		T3	190
all_pins[13]	values[0x1]	69	1			T20	1		T157	5		T70	2
all_pins[13]	transitions[0x0=>0x1]	52	1			T20	1		T157	5		T70	2
all_pins[13]	transitions[0x1=>0x0]	54	1			T157	3		T70	2		T275	3
all_pins[14]	values[0x0]	656840	1			T1	2		T2	2		T3	190
all_pins[14]	values[0x1]	71	1			T157	3		T70	2		T275	3
all_pins[14]	transitions[0x0=>0x1]	47	1			T157	2		T70	1		T275	1
all_pins[14]	transitions[0x1=>0x0]	560787	1			T1	1		T2	1		T3	186