Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293	1			T20	4		T157	18		T70	11
all_values[1]	293	1			T20	4		T157	18		T70	11
all_values[2]	293	1			T20	4		T157	18		T70	11
all_values[3]	293	1			T20	4		T157	18		T70	11
all_values[4]	293	1			T20	4		T157	18		T70	11
all_values[5]	293	1			T20	4		T157	18		T70	11
all_values[6]	293	1			T20	4		T157	18		T70	11
all_values[7]	293	1			T20	4		T157	18		T70	11
all_values[8]	293	1			T20	4		T157	18		T70	11
all_values[9]	293	1			T20	4		T157	18		T70	11
all_values[10]	293	1			T20	4		T157	18		T70	11
all_values[11]	293	1			T20	4		T157	18		T70	11
all_values[12]	293	1			T20	4		T157	18		T70	11
all_values[13]	293	1			T20	4		T157	18		T70	11
all_values[14]	293	1			T20	4		T157	18		T70	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2332

1

T20

16

T157

136

T70

89

auto[1]

2063

1

T20

44

T157

134

T70

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

832

1

T20

21

T157

20

T70

19

auto[1]

3563

1

T20

39

T157

250

T70

146

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2629

1

T20

41

T157

162

T70

101

auto[1]

1766

1

T20

19

T157

108

T70

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T70	1		T263	1		T277	4
all_values[0]	auto[0]	auto[0]	auto[1]	55	1			T157	1		T70	2		T263	1
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T20	4		T157	1		T263	1
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T157	8		T70	5		T275	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1			T157	4		T70	2		T275	3
all_values[0]	auto[1]	auto[1]	auto[1]	52	1			T157	4		T70	1		T263	1
all_values[1]	auto[0]	auto[0]	auto[0]	35	1			T275	1		T276	1		T277	1
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T157	9		T70	4		T263	1
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T275	1		T276	1		T126	1
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T20	2		T157	3		T70	4
all_values[1]	auto[1]	auto[0]	auto[1]	59	1			T157	1		T70	1		T263	1
all_values[1]	auto[1]	auto[1]	auto[1]	55	1			T20	2		T157	5		T70	2
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T20	1		T70	3		T263	4
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T157	2		T275	1		T276	1
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T70	1		T275	1		T278	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1			T20	2		T157	6		T70	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T20	1		T157	7		T70	3
all_values[2]	auto[1]	auto[1]	auto[1]	56	1			T157	3		T70	3		T275	1
all_values[3]	auto[0]	auto[0]	auto[0]	20	1			T70	3		T276	1		T277	1
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T157	10		T70	3		T263	2
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T20	4		T70	2		T275	3
all_values[3]	auto[0]	auto[1]	auto[1]	59	1			T157	2		T263	1		T275	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T157	3		T70	3		T263	1
all_values[3]	auto[1]	auto[1]	auto[1]	60	1			T157	3		T275	1		T277	1
all_values[4]	auto[0]	auto[0]	auto[0]	27	1			T263	2		T126	1		T279	1
all_values[4]	auto[0]	auto[0]	auto[1]	64	1			T157	9		T70	4		T263	1
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T20	2		T157	5		T280	1
all_values[4]	auto[0]	auto[1]	auto[1]	60	1			T20	1		T157	1		T70	3
all_values[4]	auto[1]	auto[0]	auto[1]	65	1			T157	2		T70	2		T263	1
all_values[4]	auto[1]	auto[1]	auto[1]	49	1			T20	1		T157	1		T70	2
all_values[5]	auto[0]	auto[0]	auto[0]	25	1			T277	1		T126	1		T281	2
all_values[5]	auto[0]	auto[0]	auto[1]	54	1			T157	5		T70	1		T127	1
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T70	1		T127	2		T281	1
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T20	3		T157	4		T70	4
all_values[5]	auto[1]	auto[0]	auto[1]	71	1			T157	3		T70	2		T263	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1			T20	1		T157	6		T70	3
all_values[6]	auto[0]	auto[0]	auto[0]	32	1			T70	1		T263	1		T126	3
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T20	1		T157	4		T70	3
all_values[6]	auto[0]	auto[1]	auto[0]	19	1			T20	2		T126	1		T282	1
all_values[6]	auto[0]	auto[1]	auto[1]	50	1			T157	4		T70	3		T263	1
all_values[6]	auto[1]	auto[0]	auto[1]	65	1			T20	1		T157	3		T70	2
all_values[6]	auto[1]	auto[1]	auto[1]	52	1			T157	7		T70	2		T263	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T157	1		T263	2		T277	1
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T20	1		T157	3		T70	4
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T20	2		T157	1		T70	1
all_values[7]	auto[0]	auto[1]	auto[1]	53	1			T157	5		T70	2		T276	1
all_values[7]	auto[1]	auto[0]	auto[1]	64	1			T20	1		T157	5		T70	3
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T157	3		T70	1		T275	2
all_values[8]	auto[0]	auto[0]	auto[0]	35	1			T263	1		T275	1		T277	1
all_values[8]	auto[0]	auto[0]	auto[1]	54	1			T157	6		T70	3		T275	1
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T20	2		T157	2		T70	1
all_values[8]	auto[0]	auto[1]	auto[1]	63	1			T20	1		T157	3		T70	3
all_values[8]	auto[1]	auto[0]	auto[1]	62	1			T157	3		T70	1		T275	2
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T20	1		T157	4		T70	3
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T157	3		T70	1		T279	1
all_values[9]	auto[0]	auto[0]	auto[1]	69	1			T20	1		T157	5		T70	2
all_values[9]	auto[0]	auto[1]	auto[0]	24	1			T157	1		T70	1		T281	1
all_values[9]	auto[0]	auto[1]	auto[1]	42	1			T157	2		T70	2		T263	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T20	1		T157	5		T70	3
all_values[9]	auto[1]	auto[1]	auto[1]	52	1			T20	2		T157	2		T70	2
all_values[10]	auto[0]	auto[0]	auto[0]	28	1			T20	1		T263	2		T275	1
all_values[10]	auto[0]	auto[0]	auto[1]	67	1			T20	1		T157	6		T70	5
all_values[10]	auto[0]	auto[1]	auto[0]	33	1			T70	1		T275	1		T127	1
all_values[10]	auto[0]	auto[1]	auto[1]	54	1			T157	4		T70	1		T263	1
all_values[10]	auto[1]	auto[0]	auto[1]	59	1			T20	2		T157	7		T70	1
all_values[10]	auto[1]	auto[1]	auto[1]	52	1			T157	1		T70	3		T275	1
all_values[11]	auto[0]	auto[0]	auto[0]	29	1			T20	1		T275	1		T126	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1			T157	5		T70	6		T277	2
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T275	1		T278	4		T280	1
all_values[11]	auto[0]	auto[1]	auto[1]	63	1			T20	2		T157	6		T263	1
all_values[11]	auto[1]	auto[0]	auto[1]	67	1			T20	1		T157	3		T70	4
all_values[11]	auto[1]	auto[1]	auto[1]	56	1			T157	4		T70	1		T275	3
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T70	1		T275	3		T276	3
all_values[12]	auto[0]	auto[0]	auto[1]	62	1			T20	2		T157	5		T277	1
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T157	3		T70	1		T275	4
all_values[12]	auto[0]	auto[1]	auto[1]	65	1			T157	5		T70	5		T263	3
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T157	1		T70	3		T263	1
all_values[12]	auto[1]	auto[1]	auto[1]	42	1			T20	2		T157	4		T70	1
all_values[13]	auto[0]	auto[0]	auto[0]	44	1			T263	2		T276	1		T279	1
all_values[13]	auto[0]	auto[0]	auto[1]	46	1			T157	4		T70	4		T275	1
all_values[13]	auto[0]	auto[1]	auto[0]	17	1			T20	1		T157	3		T283	2
all_values[13]	auto[0]	auto[1]	auto[1]	67	1			T20	1		T157	4		T70	2
all_values[13]	auto[1]	auto[0]	auto[1]	63	1			T157	3		T70	3		T263	1
all_values[13]	auto[1]	auto[1]	auto[1]	56	1			T20	2		T157	4		T70	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1			T263	1		T276	2		T282	1
all_values[14]	auto[0]	auto[0]	auto[1]	53	1			T157	6		T70	1		T277	1
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T20	1		T263	3		T276	2
all_values[14]	auto[0]	auto[1]	auto[1]	64	1			T20	2		T157	5		T70	5
all_values[14]	auto[1]	auto[0]	auto[1]	61	1			T157	2		T70	4		T275	2
all_values[14]	auto[1]	auto[1]	auto[1]	56	1			T20	1		T157	5		T70	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal