Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	639666	1			T1	4		T2	2		T3	2
all_values[1]	639666	1			T1	4		T2	2		T3	2
all_values[2]	639666	1			T1	4		T2	2		T3	2
all_values[3]	639666	1			T1	4		T2	2		T3	2
all_values[4]	639666	1			T1	4		T2	2		T3	2
all_values[5]	639666	1			T1	4		T2	2		T3	2
all_values[6]	639666	1			T1	4		T2	2		T3	2
all_values[7]	639666	1			T1	4		T2	2		T3	2
all_values[8]	639666	1			T1	4		T2	2		T3	2
all_values[9]	639666	1			T1	4		T2	2		T3	2
all_values[10]	639666	1			T1	4		T2	2		T3	2
all_values[11]	639666	1			T1	4		T2	2		T3	2
all_values[12]	639666	1			T1	4		T2	2		T3	2
all_values[13]	639666	1			T1	4		T2	2		T3	2
all_values[14]	639666	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7850610

1

T1

51

T2

26

T3

26

auto[1]

1744380

1

T1

9

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9313080

1

T1

60

T2

30

T3

30

auto[1]

281910

1

T25

508

T37

132087

T149

7373

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	72990	1			T6	2		T7	2		T11	2
all_values[0]	auto[0]	auto[1]	2200	1			T25	10		T37	783		T149	7
all_values[0]	auto[1]	auto[0]	542691	1			T1	4		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	21785	1			T25	26		T37	12426		T149	560
all_values[1]	auto[0]	auto[0]	628760	1			T1	4		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	10579	1			T25	26		T149	566		T148	13
all_values[1]	auto[1]	auto[0]	172	1			T30	1		T259	9		T37	9
all_values[1]	auto[1]	auto[1]	155	1			T25	8		T149	2		T148	3
all_values[2]	auto[0]	auto[0]	616066	1			T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	23261	1			T25	26		T37	13206		T149	567
all_values[2]	auto[1]	auto[0]	191	1			T9	1		T42	1		T113	1
all_values[2]	auto[1]	auto[1]	148	1			T25	10		T37	1		T149	1
all_values[3]	auto[0]	auto[0]	628917	1			T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	10580	1			T25	11		T149	564		T148	12
all_values[3]	auto[1]	auto[1]	169	1			T25	13		T149	3		T148	4
all_values[4]	auto[0]	auto[0]	624396	1			T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	15107	1			T25	28		T37	13206		T149	567
all_values[4]	auto[1]	auto[0]	17	1			T21	1		T254	1		T260	1
all_values[4]	auto[1]	auto[1]	146	1			T25	8		T37	3		T149	1
all_values[5]	auto[0]	auto[0]	616860	1			T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	22658	1			T25	27		T37	13206		T148	13
all_values[5]	auto[1]	auto[1]	148	1			T25	9		T37	3		T148	3
all_values[6]	auto[0]	auto[0]	628950	1			T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	10549	1			T25	28		T149	564		T148	10
all_values[6]	auto[1]	auto[1]	167	1			T25	7		T149	2		T148	2
all_values[7]	auto[0]	auto[0]	595968	1			T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	23262	1			T25	10		T37	13071		T149	565
all_values[7]	auto[1]	auto[0]	19732	1			T11	25		T12	377		T27	1
all_values[7]	auto[1]	auto[1]	704	1			T25	15		T37	138		T149	3
all_values[8]	auto[0]	auto[0]	615670	1			T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	23799	1			T25	27		T37	13208		T149	567
all_values[8]	auto[1]	auto[1]	197	1			T25	9		T37	1		T148	7
all_values[9]	auto[0]	auto[0]	117378	1			T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	2268	1			T25	21		T37	326		T149	563
all_values[9]	auto[1]	auto[0]	498305	1			T1	1		T5	1		T11	7
all_values[9]	auto[1]	auto[1]	21715	1			T25	15		T37	12883		T149	3
all_values[10]	auto[0]	auto[0]	616260	1			T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	23263	1			T25	28		T37	13206		T149	565
all_values[10]	auto[1]	auto[1]	143	1			T25	6		T37	3		T149	1
all_values[11]	auto[0]	auto[0]	2127	1			T6	2		T7	2		T11	2
all_values[11]	auto[0]	auto[1]	296	1			T25	7		T37	14		T149	7
all_values[11]	auto[1]	auto[0]	613560	1			T1	4		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	23683	1			T25	28		T37	13195		T149	561
all_values[12]	auto[0]	auto[0]	629415	1			T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	10053	1			T25	28		T148	15		T67	8730
all_values[12]	auto[1]	auto[0]	62	1			T9	1		T42	1		T63	1
all_values[12]	auto[1]	auto[1]	136	1			T25	7		T148	2		T67	2
all_values[13]	auto[0]	auto[0]	615691	1			T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	23797	1			T25	23		T37	13205		T149	564
all_values[13]	auto[1]	auto[1]	178	1			T25	12		T37	3		T149	2
all_values[14]	auto[0]	auto[0]	628902	1			T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	10588	1			T25	24		T149	565		T148	12
all_values[14]	auto[1]	auto[1]	176	1			T25	11		T149	3		T148	4