Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	639666	1			T1	4		T2	2		T3	2
all_pins[1]	639666	1			T1	4		T2	2		T3	2
all_pins[2]	639666	1			T1	4		T2	2		T3	2
all_pins[3]	639666	1			T1	4		T2	2		T3	2
all_pins[4]	639666	1			T1	4		T2	2		T3	2
all_pins[5]	639666	1			T1	4		T2	2		T3	2
all_pins[6]	639666	1			T1	4		T2	2		T3	2
all_pins[7]	639666	1			T1	4		T2	2		T3	2
all_pins[8]	639666	1			T1	4		T2	2		T3	2
all_pins[9]	639666	1			T1	4		T2	2		T3	2
all_pins[10]	639666	1			T1	4		T2	2		T3	2
all_pins[11]	639666	1			T1	4		T2	2		T3	2
all_pins[12]	639666	1			T1	4		T2	2		T3	2
all_pins[13]	639666	1			T1	4		T2	2		T3	2
all_pins[14]	639666	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7857354	1			T1	51		T2	26		T3	26
values[0x1]	1737636	1			T1	9		T2	4		T3	4
transitions[0x0=>0x1]	1737126	1			T1	9		T2	4		T3	4
transitions[0x1=>0x0]	1735994	1			T1	8		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78600	1			T6	2		T7	2		T9	1
all_pins[0]	values[0x1]	561066	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	560847	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	54	1			T25	2		T250	1		T67	1
all_pins[1]	values[0x0]	639393	1			T1	4		T2	2		T3	2
all_pins[1]	values[0x1]	273	1			T30	1		T259	15		T25	4
all_pins[1]	transitions[0x0=>0x1]	258	1			T30	1		T259	15		T25	4
all_pins[1]	transitions[0x1=>0x0]	103	1			T113	1		T114	1		T271	1
all_pins[2]	values[0x0]	639548	1			T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	118	1			T113	1		T114	1		T271	1
all_pins[2]	transitions[0x0=>0x1]	106	1			T113	1		T114	1		T271	1
all_pins[2]	transitions[0x1=>0x0]	67	1			T25	7		T149	1		T230	3
all_pins[3]	values[0x0]	639587	1			T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	79	1			T25	9		T149	1		T230	3
all_pins[3]	transitions[0x0=>0x1]	64	1			T25	7		T149	1		T230	1
all_pins[3]	transitions[0x1=>0x0]	79	1			T21	1		T25	3		T37	2
all_pins[4]	values[0x0]	639572	1			T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	94	1			T21	1		T25	5		T37	2
all_pins[4]	transitions[0x0=>0x1]	80	1			T21	1		T25	5		T37	2
all_pins[4]	transitions[0x1=>0x0]	67	1			T25	3		T148	2		T67	3
all_pins[5]	values[0x0]	639585	1			T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	81	1			T25	3		T148	3		T67	3
all_pins[5]	transitions[0x0=>0x1]	57	1			T25	3		T148	3		T230	2
all_pins[5]	transitions[0x1=>0x0]	55	1			T25	3		T149	2		T67	1
all_pins[6]	values[0x0]	639587	1			T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	79	1			T25	3		T149	2		T67	4
all_pins[6]	transitions[0x0=>0x1]	56	1			T25	1		T67	2		T230	2
all_pins[6]	transitions[0x1=>0x0]	22046	1			T12	427		T27	1		T40	1
all_pins[7]	values[0x0]	617597	1			T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	22069	1			T12	427		T27	1		T40	1
all_pins[7]	transitions[0x0=>0x1]	22040	1			T12	427		T27	1		T40	1
all_pins[7]	transitions[0x1=>0x0]	63	1			T25	1		T37	1		T148	2
all_pins[8]	values[0x0]	639574	1			T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	92	1			T25	3		T37	1		T148	3
all_pins[8]	transitions[0x0=>0x1]	71	1			T25	3		T37	1		T148	2
all_pins[8]	transitions[0x1=>0x0]	519921	1			T1	1		T5	1		T11	7
all_pins[9]	values[0x0]	119724	1			T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	519942	1			T1	1		T5	1		T11	7
all_pins[9]	transitions[0x0=>0x1]	519931	1			T1	1		T5	1		T11	7
all_pins[9]	transitions[0x1=>0x0]	63	1			T25	3		T37	2		T148	1
all_pins[10]	values[0x0]	639592	1			T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	74	1			T25	3		T37	2		T148	1
all_pins[10]	transitions[0x0=>0x1]	54	1			T25	2		T37	1		T148	1
all_pins[10]	transitions[0x1=>0x0]	633343	1			T1	4		T2	2		T3	2
all_pins[11]	values[0x0]	6303	1			T6	2		T7	2		T9	1
all_pins[11]	values[0x1]	633363	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	633331	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	92	1			T9	1		T42	1		T63	1
all_pins[12]	values[0x0]	639542	1			T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	124	1			T9	1		T42	1		T63	1
all_pins[12]	transitions[0x0=>0x1]	105	1			T9	1		T42	1		T63	1
all_pins[12]	transitions[0x1=>0x0]	66	1			T25	2		T37	1		T148	2
all_pins[13]	values[0x0]	639581	1			T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	85	1			T25	4		T37	1		T148	2
all_pins[13]	transitions[0x0=>0x1]	66	1			T25	3		T37	1		T148	1
all_pins[13]	transitions[0x1=>0x0]	78	1			T25	7		T149	2		T148	1
all_pins[14]	values[0x0]	639569	1			T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	97	1			T25	8		T149	2		T148	2
all_pins[14]	transitions[0x0=>0x1]	60	1			T25	2		T148	1		T67	2
all_pins[14]	transitions[0x1=>0x0]	559897	1			T1	3		T2	1		T3	1