Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	366	1			T25	22		T37	4		T149	4
all_values[1]	366	1			T25	22		T37	4		T149	4
all_values[2]	366	1			T25	22		T37	4		T149	4
all_values[3]	366	1			T25	22		T37	4		T149	4
all_values[4]	366	1			T25	22		T37	4		T149	4
all_values[5]	366	1			T25	22		T37	4		T149	4
all_values[6]	366	1			T25	22		T37	4		T149	4
all_values[7]	366	1			T25	22		T37	4		T149	4
all_values[8]	366	1			T25	22		T37	4		T149	4
all_values[9]	366	1			T25	22		T37	4		T149	4
all_values[10]	366	1			T25	22		T37	4		T149	4
all_values[11]	366	1			T25	22		T37	4		T149	4
all_values[12]	366	1			T25	22		T37	4		T149	4
all_values[13]	366	1			T25	22		T37	4		T149	4
all_values[14]	366	1			T25	22		T37	4		T149	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3015

1

T25

158

T37

37

T149

19

auto[1]

2475

1

T25

172

T37

23

T149

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

880

1

T25

18

T37

23

T149

19

auto[1]

4610

1

T25

312

T37

37

T149

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3254

1

T25

196

T37

42

T149

42

auto[1]

2236

1

T25

134

T37

18

T149

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T148	2		T67	1		T230	1
all_values[0]	auto[0]	auto[0]	auto[1]	91	1			T25	9		T230	8		T115	3
all_values[0]	auto[0]	auto[1]	auto[0]	14	1			T149	1		T230	1		T272	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T25	4		T37	3		T149	1
all_values[0]	auto[1]	auto[0]	auto[1]	93	1			T25	4		T37	1		T149	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1			T25	5		T149	1		T148	3
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T37	2		T148	1		T273	2
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T25	6		T149	2		T230	6
all_values[1]	auto[0]	auto[1]	auto[0]	16	1			T25	2		T37	2		T273	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T25	6		T148	3		T67	3
all_values[1]	auto[1]	auto[0]	auto[1]	91	1			T25	5		T149	1		T148	2
all_values[1]	auto[1]	auto[1]	auto[1]	64	1			T25	3		T149	1		T148	1
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T37	1		T148	2		T115	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T25	5		T148	2		T230	5
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T37	1		T148	1		T230	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T25	7		T37	1		T149	3
all_values[2]	auto[1]	auto[0]	auto[1]	89	1			T25	8		T148	1		T230	5
all_values[2]	auto[1]	auto[1]	auto[1]	59	1			T25	2		T37	1		T149	1
all_values[3]	auto[0]	auto[0]	auto[0]	41	1			T25	2		T37	4		T148	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T25	3		T149	2		T148	2
all_values[3]	auto[0]	auto[1]	auto[0]	28	1			T25	3		T149	1		T230	2
all_values[3]	auto[0]	auto[1]	auto[1]	60	1			T25	6		T148	1		T230	3
all_values[3]	auto[1]	auto[0]	auto[1]	78	1			T25	3		T148	2		T67	2
all_values[3]	auto[1]	auto[1]	auto[1]	77	1			T25	5		T149	1		T148	1
all_values[4]	auto[0]	auto[0]	auto[0]	30	1			T230	2		T273	1		T274	3
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T25	5		T149	1		T148	2
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T148	1		T67	4		T230	3
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T25	9		T37	1		T149	2
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T25	6		T37	2		T148	1
all_values[4]	auto[1]	auto[1]	auto[1]	56	1			T25	2		T37	1		T149	1
all_values[5]	auto[0]	auto[0]	auto[0]	47	1			T273	2		T115	4		T275	1
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T25	4		T37	1		T230	9
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T149	4		T148	1		T273	2
all_values[5]	auto[0]	auto[1]	auto[1]	89	1			T25	8		T148	2		T67	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1			T25	3		T37	3		T148	1
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T25	7		T148	3		T67	1
all_values[6]	auto[0]	auto[0]	auto[0]	50	1			T25	1		T37	3		T149	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T25	7		T148	1		T230	11
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T37	1		T149	1		T148	1
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T25	3		T149	1		T67	1
all_values[6]	auto[1]	auto[0]	auto[1]	88	1			T25	7		T148	1		T230	8
all_values[6]	auto[1]	auto[1]	auto[1]	61	1			T25	4		T149	1		T67	3
all_values[7]	auto[0]	auto[0]	auto[0]	34	1			T25	2		T273	1		T115	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T25	4		T37	3		T149	1
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T25	2		T230	2		T116	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T25	4		T149	1		T148	1
all_values[7]	auto[1]	auto[0]	auto[1]	79	1			T25	4		T37	1		T148	2
all_values[7]	auto[1]	auto[1]	auto[1]	63	1			T25	6		T149	2		T148	2
all_values[8]	auto[0]	auto[0]	auto[0]	21	1			T115	1		T275	2		T276	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T25	7		T37	2		T149	2
all_values[8]	auto[0]	auto[1]	auto[0]	15	1			T149	1		T272	1		T117	1
all_values[8]	auto[0]	auto[1]	auto[1]	90	1			T25	8		T37	1		T67	1
all_values[8]	auto[1]	auto[0]	auto[1]	88	1			T25	2		T37	1		T148	1
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T25	5		T149	1		T148	2
all_values[9]	auto[0]	auto[0]	auto[0]	30	1			T273	2		T116	3		T277	1
all_values[9]	auto[0]	auto[0]	auto[1]	76	1			T25	6		T149	1		T148	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T149	2		T148	1		T116	1
all_values[9]	auto[0]	auto[1]	auto[1]	85	1			T25	6		T37	2		T148	1
all_values[9]	auto[1]	auto[0]	auto[1]	91	1			T25	3		T37	2		T149	1
all_values[9]	auto[1]	auto[1]	auto[1]	65	1			T25	7		T148	4		T230	3
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T149	1		T148	1		T273	1
all_values[10]	auto[0]	auto[0]	auto[1]	70	1			T25	7		T149	1		T230	8
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T25	2		T149	1		T148	4
all_values[10]	auto[0]	auto[1]	auto[1]	85	1			T25	7		T37	1		T148	1
all_values[10]	auto[1]	auto[0]	auto[1]	73	1			T25	4		T37	1		T149	1
all_values[10]	auto[1]	auto[1]	auto[1]	70	1			T25	2		T37	2		T148	1
all_values[11]	auto[0]	auto[0]	auto[0]	32	1			T275	1		T278	1		T274	1
all_values[11]	auto[0]	auto[0]	auto[1]	74	1			T25	3		T37	1		T148	2
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T25	1		T148	1		T67	2
all_values[11]	auto[0]	auto[1]	auto[1]	74	1			T25	3		T37	1		T149	2
all_values[11]	auto[1]	auto[0]	auto[1]	81	1			T25	6		T37	1		T148	2
all_values[11]	auto[1]	auto[1]	auto[1]	85	1			T25	9		T37	1		T149	2
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T37	1		T115	1		T275	3
all_values[12]	auto[0]	auto[0]	auto[1]	85	1			T25	7		T148	2		T230	11
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T25	1		T37	3		T149	4
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T25	7		T148	3		T67	2
all_values[12]	auto[1]	auto[0]	auto[1]	76	1			T25	4		T148	1		T230	3
all_values[12]	auto[1]	auto[1]	auto[1]	60	1			T25	3		T148	1		T67	2
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T37	1		T148	1		T67	2
all_values[13]	auto[0]	auto[0]	auto[1]	77	1			T25	5		T37	2		T149	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1			T25	1		T149	2		T276	1
all_values[13]	auto[0]	auto[1]	auto[1]	86	1			T25	7		T67	1		T230	8
all_values[13]	auto[1]	auto[0]	auto[1]	83	1			T25	7		T149	1		T148	1
all_values[13]	auto[1]	auto[1]	auto[1]	62	1			T25	2		T37	1		T148	2
all_values[14]	auto[0]	auto[0]	auto[0]	38	1			T37	4		T148	1		T275	1
all_values[14]	auto[0]	auto[0]	auto[1]	75	1			T25	7		T149	1		T148	1
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T25	1		T67	1		T230	1
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T25	8		T149	1		T67	1
all_values[14]	auto[1]	auto[0]	auto[1]	79	1			T25	2		T148	3		T230	1
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T25	4		T149	2		T148	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal