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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.03 97.09 89.46 97.22 70.83 94.04 98.44 90.11


Total test records in report: 1674
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T1557 /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1842721444 Jul 11 07:33:10 PM PDT 24 Jul 11 07:33:14 PM PDT 24 127847994 ps
T1558 /workspace/coverage/default/31.i2c_target_stress_wr.908391219 Jul 11 07:31:07 PM PDT 24 Jul 11 07:35:13 PM PDT 24 46222972650 ps
T1559 /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3981848751 Jul 11 07:30:51 PM PDT 24 Jul 11 07:31:01 PM PDT 24 310847762 ps
T1560 /workspace/coverage/default/44.i2c_target_stress_wr.4076248054 Jul 11 07:33:39 PM PDT 24 Jul 11 07:33:45 PM PDT 24 8574943222 ps
T1561 /workspace/coverage/default/4.i2c_alert_test.498059081 Jul 11 07:23:31 PM PDT 24 Jul 11 07:23:32 PM PDT 24 20550976 ps
T1562 /workspace/coverage/default/37.i2c_host_smoke.3327090662 Jul 11 07:32:12 PM PDT 24 Jul 11 07:32:42 PM PDT 24 1577105724 ps
T1563 /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.4021679194 Jul 11 07:25:58 PM PDT 24 Jul 11 07:26:02 PM PDT 24 1750894849 ps
T1564 /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.843928109 Jul 11 07:24:54 PM PDT 24 Jul 11 07:24:59 PM PDT 24 183753873 ps
T1565 /workspace/coverage/default/9.i2c_target_timeout.292946720 Jul 11 07:25:11 PM PDT 24 Jul 11 07:25:19 PM PDT 24 4988002790 ps
T1566 /workspace/coverage/default/44.i2c_host_fifo_full.3623296771 Jul 11 07:33:47 PM PDT 24 Jul 11 07:37:24 PM PDT 24 2882957123 ps
T275 /workspace/coverage/cover_reg_top/24.i2c_intr_test.815675591 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 23059972 ps
T276 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2585197562 Jul 11 06:08:44 PM PDT 24 Jul 11 06:08:47 PM PDT 24 26919956 ps
T178 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2903553418 Jul 11 06:08:15 PM PDT 24 Jul 11 06:08:18 PM PDT 24 90551421 ps
T1567 /workspace/coverage/cover_reg_top/12.i2c_intr_test.12781836 Jul 11 06:08:32 PM PDT 24 Jul 11 06:08:34 PM PDT 24 18191849 ps
T207 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2322843260 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:44 PM PDT 24 64291337 ps
T1568 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1461461702 Jul 11 06:08:24 PM PDT 24 Jul 11 06:08:29 PM PDT 24 20172810 ps
T208 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2020552979 Jul 11 06:08:32 PM PDT 24 Jul 11 06:08:35 PM PDT 24 34243648 ps
T277 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2749033298 Jul 11 06:08:56 PM PDT 24 Jul 11 06:08:59 PM PDT 24 39724377 ps
T272 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2863638781 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:53 PM PDT 24 47281643 ps
T278 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3388213048 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:53 PM PDT 24 22340991 ps
T95 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1713063153 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:25 PM PDT 24 74614268 ps
T274 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3594054238 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:28 PM PDT 24 31571540 ps
T96 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1434298778 Jul 11 06:08:30 PM PDT 24 Jul 11 06:08:33 PM PDT 24 81856031 ps
T97 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1691893730 Jul 11 06:08:36 PM PDT 24 Jul 11 06:08:38 PM PDT 24 226382815 ps
T179 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.960597114 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:49 PM PDT 24 77138632 ps
T1569 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3150890769 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:55 PM PDT 24 19770055 ps
T195 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3377816472 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:52 PM PDT 24 375657538 ps
T117 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3640472710 Jul 11 06:08:53 PM PDT 24 Jul 11 06:08:55 PM PDT 24 91855159 ps
T221 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1066449498 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:27 PM PDT 24 425010934 ps
T228 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4074712864 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:43 PM PDT 24 65086954 ps
T215 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.32551845 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:26 PM PDT 24 17797395 ps
T98 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1603081427 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:41 PM PDT 24 41257791 ps
T1570 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2606265888 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 15816020 ps
T193 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1003081988 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:45 PM PDT 24 125087232 ps
T196 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.634986603 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:43 PM PDT 24 181044557 ps
T197 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1746588752 Jul 11 06:08:29 PM PDT 24 Jul 11 06:08:34 PM PDT 24 104266684 ps
T194 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.771418471 Jul 11 06:08:35 PM PDT 24 Jul 11 06:08:38 PM PDT 24 251418000 ps
T209 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.998294280 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:42 PM PDT 24 121880943 ps
T1571 /workspace/coverage/cover_reg_top/20.i2c_intr_test.4029909153 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 43916175 ps
T99 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3441216670 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:51 PM PDT 24 33624560 ps
T1572 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1786774512 Jul 11 06:08:53 PM PDT 24 Jul 11 06:08:56 PM PDT 24 26596701 ps
T100 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.588336227 Jul 11 06:08:26 PM PDT 24 Jul 11 06:08:31 PM PDT 24 100651351 ps
T1573 /workspace/coverage/cover_reg_top/26.i2c_intr_test.734675361 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 24563894 ps
T101 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1440694715 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:26 PM PDT 24 26837141 ps
T1574 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1145458578 Jul 11 06:08:44 PM PDT 24 Jul 11 06:08:46 PM PDT 24 25762942 ps
T229 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2553005866 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:23 PM PDT 24 28533877 ps
T1575 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3294860689 Jul 11 06:08:47 PM PDT 24 Jul 11 06:08:49 PM PDT 24 15912769 ps
T213 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2641844398 Jul 11 06:08:34 PM PDT 24 Jul 11 06:08:36 PM PDT 24 242189376 ps
T222 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3073728752 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:23 PM PDT 24 21592324 ps
T102 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1748417193 Jul 11 06:08:31 PM PDT 24 Jul 11 06:08:34 PM PDT 24 81111161 ps
T103 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3078286555 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:44 PM PDT 24 75776044 ps
T201 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4083414608 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:43 PM PDT 24 31578607 ps
T1576 /workspace/coverage/cover_reg_top/3.i2c_intr_test.483752783 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:24 PM PDT 24 47929440 ps
T1577 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1687241718 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:24 PM PDT 24 174803466 ps
T104 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1365537282 Jul 11 06:08:25 PM PDT 24 Jul 11 06:08:30 PM PDT 24 20132313 ps
T1578 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3902402493 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:40 PM PDT 24 19461297 ps
T216 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.328364619 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:28 PM PDT 24 51532346 ps
T1579 /workspace/coverage/cover_reg_top/33.i2c_intr_test.516708092 Jul 11 06:08:55 PM PDT 24 Jul 11 06:08:58 PM PDT 24 50849220 ps
T202 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3279428424 Jul 11 06:08:19 PM PDT 24 Jul 11 06:08:23 PM PDT 24 85152934 ps
T1580 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1083893338 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:41 PM PDT 24 27797383 ps
T1581 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2342284267 Jul 11 06:08:53 PM PDT 24 Jul 11 06:08:55 PM PDT 24 22152817 ps
T217 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1260217404 Jul 11 06:08:13 PM PDT 24 Jul 11 06:08:16 PM PDT 24 18782997 ps
T140 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2041476543 Jul 11 06:08:33 PM PDT 24 Jul 11 06:08:36 PM PDT 24 191246102 ps
T1582 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1127125369 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:43 PM PDT 24 63143410 ps
T1583 /workspace/coverage/cover_reg_top/27.i2c_intr_test.890092683 Jul 11 06:08:42 PM PDT 24 Jul 11 06:08:44 PM PDT 24 14850542 ps
T1584 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2108156258 Jul 11 06:08:30 PM PDT 24 Jul 11 06:08:33 PM PDT 24 35675193 ps
T1585 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2819722667 Jul 11 06:08:19 PM PDT 24 Jul 11 06:08:22 PM PDT 24 58989175 ps
T1586 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2469903439 Jul 11 06:08:54 PM PDT 24 Jul 11 06:08:57 PM PDT 24 18369127 ps
T1587 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2431678981 Jul 11 06:08:36 PM PDT 24 Jul 11 06:08:38 PM PDT 24 180431377 ps
T1588 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1989697236 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:26 PM PDT 24 74730323 ps
T1589 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3926434309 Jul 11 06:08:24 PM PDT 24 Jul 11 06:08:29 PM PDT 24 57351943 ps
T1590 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3042957119 Jul 11 06:08:54 PM PDT 24 Jul 11 06:08:56 PM PDT 24 23600459 ps
T1591 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3822727905 Jul 11 06:08:24 PM PDT 24 Jul 11 06:08:29 PM PDT 24 78757021 ps
T1592 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1415935718 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:43 PM PDT 24 41405257 ps
T1593 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3997778666 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 18275626 ps
T1594 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.461541116 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:42 PM PDT 24 26736438 ps
T261 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3726294351 Jul 11 06:08:42 PM PDT 24 Jul 11 06:08:45 PM PDT 24 53851543 ps
T1595 /workspace/coverage/cover_reg_top/6.i2c_intr_test.737156886 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:26 PM PDT 24 57423817 ps
T1596 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1976911893 Jul 11 06:08:16 PM PDT 24 Jul 11 06:08:20 PM PDT 24 125472965 ps
T198 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.990775692 Jul 11 06:08:13 PM PDT 24 Jul 11 06:08:17 PM PDT 24 304187013 ps
T1597 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1816953921 Jul 11 06:08:44 PM PDT 24 Jul 11 06:08:46 PM PDT 24 111894379 ps
T1598 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.225196430 Jul 11 06:08:37 PM PDT 24 Jul 11 06:08:39 PM PDT 24 88263127 ps
T1599 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3145221105 Jul 11 06:08:35 PM PDT 24 Jul 11 06:08:37 PM PDT 24 27988424 ps
T218 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2503994628 Jul 11 06:08:18 PM PDT 24 Jul 11 06:08:21 PM PDT 24 131602224 ps
T1600 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.185204022 Jul 11 06:08:46 PM PDT 24 Jul 11 06:08:49 PM PDT 24 23125782 ps
T223 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3096322803 Jul 11 06:08:16 PM PDT 24 Jul 11 06:08:21 PM PDT 24 1896325035 ps
T219 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2232778115 Jul 11 06:08:37 PM PDT 24 Jul 11 06:08:39 PM PDT 24 119548187 ps
T262 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.325664516 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:27 PM PDT 24 88178815 ps
T1601 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1195345521 Jul 11 06:08:11 PM PDT 24 Jul 11 06:08:14 PM PDT 24 17592548 ps
T220 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.982185388 Jul 11 06:08:15 PM PDT 24 Jul 11 06:08:18 PM PDT 24 23194682 ps
T1602 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.964488831 Jul 11 06:08:29 PM PDT 24 Jul 11 06:08:33 PM PDT 24 221259349 ps
T1603 /workspace/coverage/cover_reg_top/40.i2c_intr_test.1606668867 Jul 11 06:08:53 PM PDT 24 Jul 11 06:08:56 PM PDT 24 92426396 ps
T1604 /workspace/coverage/cover_reg_top/35.i2c_intr_test.4136808230 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:54 PM PDT 24 20511722 ps
T1605 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1162434208 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:41 PM PDT 24 21654841 ps
T1606 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2292609116 Jul 11 06:08:32 PM PDT 24 Jul 11 06:08:35 PM PDT 24 62589461 ps
T1607 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1603602002 Jul 11 06:08:46 PM PDT 24 Jul 11 06:08:49 PM PDT 24 41801548 ps
T1608 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1390157864 Jul 11 06:08:24 PM PDT 24 Jul 11 06:08:28 PM PDT 24 282992699 ps
T1609 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2291567418 Jul 11 06:08:19 PM PDT 24 Jul 11 06:08:22 PM PDT 24 69436894 ps
T1610 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2190877999 Jul 11 06:08:30 PM PDT 24 Jul 11 06:08:33 PM PDT 24 220022684 ps
T1611 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3233441528 Jul 11 06:08:34 PM PDT 24 Jul 11 06:08:36 PM PDT 24 33494001 ps
T1612 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1975848790 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:41 PM PDT 24 67348307 ps
T1613 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.705657305 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:27 PM PDT 24 119794194 ps
T1614 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3882083294 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:26 PM PDT 24 22553641 ps
T150 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.135812616 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 51525013 ps
T1615 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1182446359 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:52 PM PDT 24 63653309 ps
T1616 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3014087941 Jul 11 06:08:57 PM PDT 24 Jul 11 06:09:01 PM PDT 24 16422994 ps
T1617 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3860662522 Jul 11 06:08:25 PM PDT 24 Jul 11 06:08:30 PM PDT 24 20394691 ps
T1618 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3846003661 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:29 PM PDT 24 1073307011 ps
T1619 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.756955006 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:28 PM PDT 24 27131586 ps
T1620 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1637141157 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:23 PM PDT 24 208382218 ps
T1621 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3098511132 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:31 PM PDT 24 1832365911 ps
T1622 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.228651940 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:26 PM PDT 24 404325418 ps
T1623 /workspace/coverage/cover_reg_top/1.i2c_intr_test.821791303 Jul 11 06:08:18 PM PDT 24 Jul 11 06:08:20 PM PDT 24 14989289 ps
T1624 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1414706237 Jul 11 06:08:39 PM PDT 24 Jul 11 06:08:40 PM PDT 24 17698213 ps
T204 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3803822073 Jul 11 06:08:18 PM PDT 24 Jul 11 06:08:22 PM PDT 24 514322118 ps
T1625 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2369148560 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:28 PM PDT 24 140044507 ps
T203 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.659444024 Jul 11 06:08:30 PM PDT 24 Jul 11 06:08:35 PM PDT 24 152631428 ps
T1626 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1704063437 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:28 PM PDT 24 158269447 ps
T1627 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.579296837 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:28 PM PDT 24 28062870 ps
T199 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3113545642 Jul 11 06:08:33 PM PDT 24 Jul 11 06:08:36 PM PDT 24 265703799 ps
T1628 /workspace/coverage/cover_reg_top/32.i2c_intr_test.547960945 Jul 11 06:08:54 PM PDT 24 Jul 11 06:08:56 PM PDT 24 40128138 ps
T224 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2649783097 Jul 11 06:08:34 PM PDT 24 Jul 11 06:08:36 PM PDT 24 92930573 ps
T1629 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3348080059 Jul 11 06:08:16 PM PDT 24 Jul 11 06:08:19 PM PDT 24 513090324 ps
T200 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3806600030 Jul 11 06:08:27 PM PDT 24 Jul 11 06:08:32 PM PDT 24 73399551 ps
T225 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.380555148 Jul 11 06:08:16 PM PDT 24 Jul 11 06:08:20 PM PDT 24 132607224 ps
T1630 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.576250531 Jul 11 06:08:42 PM PDT 24 Jul 11 06:08:45 PM PDT 24 43163205 ps
T1631 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.966925804 Jul 11 06:08:25 PM PDT 24 Jul 11 06:08:31 PM PDT 24 726363727 ps
T1632 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3499488287 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:25 PM PDT 24 185001609 ps
T1633 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2281680113 Jul 11 06:08:36 PM PDT 24 Jul 11 06:08:38 PM PDT 24 19930597 ps
T1634 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2427643953 Jul 11 06:08:33 PM PDT 24 Jul 11 06:08:36 PM PDT 24 106573630 ps
T1635 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3564694725 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:43 PM PDT 24 49942761 ps
T1636 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.155550882 Jul 11 06:08:13 PM PDT 24 Jul 11 06:08:16 PM PDT 24 43956954 ps
T1637 /workspace/coverage/cover_reg_top/22.i2c_intr_test.875495061 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 52237169 ps
T1638 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3537771021 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:27 PM PDT 24 150679806 ps
T1639 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3091446864 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 33620943 ps
T1640 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.600042063 Jul 11 06:08:26 PM PDT 24 Jul 11 06:08:31 PM PDT 24 40571639 ps
T1641 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1050958285 Jul 11 06:08:29 PM PDT 24 Jul 11 06:08:32 PM PDT 24 29292278 ps
T1642 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3684336560 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:54 PM PDT 24 69820659 ps
T1643 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2581425188 Jul 11 06:08:23 PM PDT 24 Jul 11 06:08:29 PM PDT 24 284351065 ps
T1644 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1195319991 Jul 11 06:08:34 PM PDT 24 Jul 11 06:08:36 PM PDT 24 23849767 ps
T1645 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1743561061 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:23 PM PDT 24 67046142 ps
T1646 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.692970402 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:44 PM PDT 24 64398206 ps
T1647 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3510305919 Jul 11 06:08:25 PM PDT 24 Jul 11 06:08:30 PM PDT 24 30162135 ps
T1648 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1386396487 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:26 PM PDT 24 139039627 ps
T1649 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4060697350 Jul 11 06:08:31 PM PDT 24 Jul 11 06:08:33 PM PDT 24 36545168 ps
T226 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3577837522 Jul 11 06:08:10 PM PDT 24 Jul 11 06:08:13 PM PDT 24 20368267 ps
T1650 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2308764012 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:51 PM PDT 24 15486550 ps
T1651 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1369167009 Jul 11 06:08:28 PM PDT 24 Jul 11 06:08:31 PM PDT 24 60548602 ps
T1652 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3604859548 Jul 11 06:08:15 PM PDT 24 Jul 11 06:08:17 PM PDT 24 134812206 ps
T1653 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.385051604 Jul 11 06:08:17 PM PDT 24 Jul 11 06:08:24 PM PDT 24 351373604 ps
T1654 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4049317331 Jul 11 06:08:22 PM PDT 24 Jul 11 06:08:27 PM PDT 24 92276812 ps
T1655 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3628593696 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:25 PM PDT 24 332813866 ps
T1656 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.114450434 Jul 11 06:08:33 PM PDT 24 Jul 11 06:08:36 PM PDT 24 89260389 ps
T1657 /workspace/coverage/cover_reg_top/25.i2c_intr_test.4177698743 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:51 PM PDT 24 39809859 ps
T205 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1530699143 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:49 PM PDT 24 129118333 ps
T1658 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3788701932 Jul 11 06:08:34 PM PDT 24 Jul 11 06:08:37 PM PDT 24 276434478 ps
T1659 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2217398393 Jul 11 06:08:40 PM PDT 24 Jul 11 06:08:42 PM PDT 24 91121393 ps
T1660 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1141697179 Jul 11 06:08:19 PM PDT 24 Jul 11 06:08:21 PM PDT 24 16826073 ps
T1661 /workspace/coverage/cover_reg_top/8.i2c_intr_test.4123123451 Jul 11 06:08:25 PM PDT 24 Jul 11 06:08:30 PM PDT 24 19406129 ps
T1662 /workspace/coverage/cover_reg_top/10.i2c_intr_test.632451316 Jul 11 06:08:30 PM PDT 24 Jul 11 06:08:33 PM PDT 24 31317539 ps
T1663 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.357276658 Jul 11 06:08:49 PM PDT 24 Jul 11 06:08:51 PM PDT 24 347865741 ps
T1664 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3825304231 Jul 11 06:08:09 PM PDT 24 Jul 11 06:08:13 PM PDT 24 1808284995 ps
T1665 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2895100667 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:48 PM PDT 24 223844455 ps
T1666 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1938698535 Jul 11 06:08:43 PM PDT 24 Jul 11 06:08:46 PM PDT 24 21917899 ps
T1667 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1271748173 Jul 11 06:08:53 PM PDT 24 Jul 11 06:08:55 PM PDT 24 22833491 ps
T1668 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2127473977 Jul 11 06:08:17 PM PDT 24 Jul 11 06:08:19 PM PDT 24 25145828 ps
T1669 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2584049857 Jul 11 06:08:24 PM PDT 24 Jul 11 06:08:29 PM PDT 24 84139411 ps
T227 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2393936537 Jul 11 06:08:20 PM PDT 24 Jul 11 06:08:23 PM PDT 24 41499379 ps
T1670 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1559887307 Jul 11 06:08:52 PM PDT 24 Jul 11 06:08:54 PM PDT 24 60941290 ps
T1671 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1592801834 Jul 11 06:08:41 PM PDT 24 Jul 11 06:08:44 PM PDT 24 57952924 ps
T1672 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2868371689 Jul 11 06:08:21 PM PDT 24 Jul 11 06:08:24 PM PDT 24 63637417 ps
T1673 /workspace/coverage/cover_reg_top/43.i2c_intr_test.107071505 Jul 11 06:08:55 PM PDT 24 Jul 11 06:08:58 PM PDT 24 20477642 ps
T1674 /workspace/coverage/cover_reg_top/31.i2c_intr_test.4205386889 Jul 11 06:08:43 PM PDT 24 Jul 11 06:08:45 PM PDT 24 43698351 ps
T206 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1953815143 Jul 11 06:08:45 PM PDT 24 Jul 11 06:08:49 PM PDT 24 474613414 ps

Test location /workspace/coverage/default/16.i2c_target_stretch.1921141340
Short name T2
Test name
Test status
Simulation time 2070302217 ps
CPU time 8.56 seconds
Started Jul 11 07:27:15 PM PDT 24
Finished Jul 11 07:27:25 PM PDT 24
Peak memory 295144 kb
Host smart-1a77d6e6-3024-441d-afee-e5d7b985aef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921141340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1921141340
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2487018471
Short name T12
Test name
Test status
Simulation time 41293902437 ps
CPU time 1063.11 seconds
Started Jul 11 07:26:02 PM PDT 24
Finished Jul 11 07:43:48 PM PDT 24
Peak memory 3113620 kb
Host smart-e109495b-736d-4f51-a575-9a2a5b84b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487018471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2487018471
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1609307668
Short name T25
Test name
Test status
Simulation time 55853320986 ps
CPU time 379.4 seconds
Started Jul 11 07:30:39 PM PDT 24
Finished Jul 11 07:37:00 PM PDT 24
Peak memory 2433516 kb
Host smart-ddc6eb2a-63bc-401d-9cd3-b8c1ad9fdbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609307668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1609307668
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3069173593
Short name T46
Test name
Test status
Simulation time 2297475683 ps
CPU time 12.38 seconds
Started Jul 11 07:21:35 PM PDT 24
Finished Jul 11 07:21:48 PM PDT 24
Peak memory 213976 kb
Host smart-19ebc735-0f76-45bd-a465-375c6627b72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069173593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3069173593
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1603081427
Short name T98
Test name
Test status
Simulation time 41257791 ps
CPU time 0.98 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:41 PM PDT 24
Peak memory 204556 kb
Host smart-25c37e5e-df6f-4505-8af1-b85c73664b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603081427 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1603081427
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3246301381
Short name T44
Test name
Test status
Simulation time 4443271171 ps
CPU time 6.61 seconds
Started Jul 11 07:24:07 PM PDT 24
Finished Jul 11 07:24:15 PM PDT 24
Peak memory 221836 kb
Host smart-a478eab6-800c-40a0-b0d8-26b6568eef22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246301381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3246301381
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.1022368629
Short name T9
Test name
Test status
Simulation time 459906682 ps
CPU time 2.48 seconds
Started Jul 11 07:31:02 PM PDT 24
Finished Jul 11 07:31:06 PM PDT 24
Peak memory 205492 kb
Host smart-27a343d3-cf49-4af8-ad4d-c76ea6ae2dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022368629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.1022368629
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_host_override.3899599606
Short name T127
Test name
Test status
Simulation time 86203859 ps
CPU time 0.7 seconds
Started Jul 11 07:28:06 PM PDT 24
Finished Jul 11 07:28:11 PM PDT 24
Peak memory 205168 kb
Host smart-2feb7809-bcf7-44a8-a7a0-a84ee99fec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899599606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3899599606
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2502081489
Short name T24
Test name
Test status
Simulation time 1322274411 ps
CPU time 5.57 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 205464 kb
Host smart-fd5315e8-1d1d-4116-9aa8-31a11e6c473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502081489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2502081489
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3597786527
Short name T62
Test name
Test status
Simulation time 39504807322 ps
CPU time 747.1 seconds
Started Jul 11 07:23:15 PM PDT 24
Finished Jul 11 07:35:44 PM PDT 24
Peak memory 4933384 kb
Host smart-9afbd6ba-833c-4bc1-830e-2c6650776c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597786527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3597786527
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.771418471
Short name T194
Test name
Test status
Simulation time 251418000 ps
CPU time 2.35 seconds
Started Jul 11 06:08:35 PM PDT 24
Finished Jul 11 06:08:38 PM PDT 24
Peak memory 204800 kb
Host smart-6445d1cd-9ae0-4846-8fdd-03323c5d20c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771418471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.771418471
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_alert_test.791364922
Short name T176
Test name
Test status
Simulation time 29620181 ps
CPU time 0.64 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:25:41 PM PDT 24
Peak memory 204708 kb
Host smart-2b25f6f3-382d-40e9-aeb7-3b1bbf967852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791364922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.791364922
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.559188613
Short name T32
Test name
Test status
Simulation time 1361218971 ps
CPU time 1.13 seconds
Started Jul 11 07:28:03 PM PDT 24
Finished Jul 11 07:28:09 PM PDT 24
Peak memory 205184 kb
Host smart-5ae1f346-7b1c-40fe-8d03-d6d847b1290b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559188613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.559188613
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.2755425681
Short name T986
Test name
Test status
Simulation time 975728096 ps
CPU time 2.75 seconds
Started Jul 11 07:27:38 PM PDT 24
Finished Jul 11 07:27:41 PM PDT 24
Peak memory 205484 kb
Host smart-6e69a6ef-9c0c-4c81-8277-03789d618649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755425681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.2755425681
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.2661143352
Short name T48
Test name
Test status
Simulation time 270412787 ps
CPU time 4.42 seconds
Started Jul 11 07:28:35 PM PDT 24
Finished Jul 11 07:28:41 PM PDT 24
Peak memory 205436 kb
Host smart-df913476-386c-4e3c-96ee-00d5968abea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661143352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2661143352
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1713063153
Short name T95
Test name
Test status
Simulation time 74614268 ps
CPU time 0.74 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:25 PM PDT 24
Peak memory 204444 kb
Host smart-67177189-8002-4bf3-a641-4b9951f1e4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713063153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1713063153
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1929875953
Short name T148
Test name
Test status
Simulation time 8878740294 ps
CPU time 334.05 seconds
Started Jul 11 07:32:04 PM PDT 24
Finished Jul 11 07:37:40 PM PDT 24
Peak memory 1073128 kb
Host smart-85405c71-eb51-4529-9fb5-00ae824d4e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929875953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1929875953
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1045485349
Short name T56
Test name
Test status
Simulation time 6664033913 ps
CPU time 6.19 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:57 PM PDT 24
Peak memory 213772 kb
Host smart-fd577778-1278-447c-b6e0-11b14bd0f9ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045485349 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1045485349
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.3980157439
Short name T883
Test name
Test status
Simulation time 545591338 ps
CPU time 2.99 seconds
Started Jul 11 07:22:36 PM PDT 24
Finished Jul 11 07:22:40 PM PDT 24
Peak memory 213680 kb
Host smart-86c62c36-42f0-45b1-8c54-ca4560a845cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980157439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.3980157439
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1746588752
Short name T197
Test name
Test status
Simulation time 104266684 ps
CPU time 2.42 seconds
Started Jul 11 06:08:29 PM PDT 24
Finished Jul 11 06:08:34 PM PDT 24
Peak memory 204776 kb
Host smart-18e8f469-96e2-49ce-96d2-90c19682b2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746588752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1746588752
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1440975206
Short name T180
Test name
Test status
Simulation time 141486076 ps
CPU time 0.97 seconds
Started Jul 11 07:21:15 PM PDT 24
Finished Jul 11 07:21:16 PM PDT 24
Peak memory 223584 kb
Host smart-7071946f-79e8-408a-bebb-73b4a08e2eb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440975206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1440975206
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.734675361
Short name T1573
Test name
Test status
Simulation time 24563894 ps
CPU time 0.7 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204464 kb
Host smart-211bea19-5091-4913-94a3-616502fe0317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734675361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.734675361
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.85629900
Short name T41
Test name
Test status
Simulation time 493678619 ps
CPU time 7.93 seconds
Started Jul 11 07:27:47 PM PDT 24
Finished Jul 11 07:27:56 PM PDT 24
Peak memory 228444 kb
Host smart-f7a8e952-1570-41d0-be0d-41e4fac9ddd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85629900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.85629900
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2990796287
Short name T93
Test name
Test status
Simulation time 235958483 ps
CPU time 1.62 seconds
Started Jul 11 07:26:25 PM PDT 24
Finished Jul 11 07:26:28 PM PDT 24
Peak memory 205476 kb
Host smart-2da73f01-d67f-4643-91a4-3dadc87bb32b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990796287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2990796287
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2359050619
Short name T149
Test name
Test status
Simulation time 54558850890 ps
CPU time 2340.59 seconds
Started Jul 11 07:33:06 PM PDT 24
Finished Jul 11 08:12:10 PM PDT 24
Peak memory 4729360 kb
Host smart-24c70f3b-b323-4ec3-99f2-cbc699d7acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359050619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2359050619
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2572261889
Short name T21
Test name
Test status
Simulation time 496171686 ps
CPU time 6.38 seconds
Started Jul 11 07:32:03 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 205300 kb
Host smart-7d38849f-7abb-48c7-843c-280a868a2c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572261889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2572261889
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1194560711
Short name T73
Test name
Test status
Simulation time 2549949860 ps
CPU time 184.07 seconds
Started Jul 11 07:32:13 PM PDT 24
Finished Jul 11 07:35:18 PM PDT 24
Peak memory 814220 kb
Host smart-1605f32b-c1ac-460c-af02-f492cdda451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194560711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1194560711
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1697250808
Short name T8
Test name
Test status
Simulation time 1249155052 ps
CPU time 7.04 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 221868 kb
Host smart-9f9e4287-7dc4-470a-ac91-6915c709326a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697250808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1697250808
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2206920272
Short name T242
Test name
Test status
Simulation time 833426092 ps
CPU time 29.92 seconds
Started Jul 11 07:21:06 PM PDT 24
Finished Jul 11 07:21:37 PM PDT 24
Peak memory 205432 kb
Host smart-1f515702-def4-44ce-9827-5bd1968bf764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206920272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2206920272
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1944159862
Short name T78
Test name
Test status
Simulation time 2041537515 ps
CPU time 11.03 seconds
Started Jul 11 07:21:32 PM PDT 24
Finished Jul 11 07:21:44 PM PDT 24
Peak memory 213688 kb
Host smart-1ddffb33-3f51-4c0c-8877-018a34ab0912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944159862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1944159862
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3304753537
Short name T212
Test name
Test status
Simulation time 20151354677 ps
CPU time 50.65 seconds
Started Jul 11 07:29:12 PM PDT 24
Finished Jul 11 07:30:05 PM PDT 24
Peak memory 775696 kb
Host smart-e2b8b88c-5a67-4991-887f-2e5b631f29db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304753537 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3304753537
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2984043892
Short name T257
Test name
Test status
Simulation time 5671466682 ps
CPU time 28.76 seconds
Started Jul 11 07:25:30 PM PDT 24
Finished Jul 11 07:26:00 PM PDT 24
Peak memory 229992 kb
Host smart-af85a9b5-ed78-41b8-988f-8eaaec0ada05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984043892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2984043892
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3813171888
Short name T282
Test name
Test status
Simulation time 2158622288 ps
CPU time 20.02 seconds
Started Jul 11 07:22:17 PM PDT 24
Finished Jul 11 07:22:38 PM PDT 24
Peak memory 223736 kb
Host smart-a452405c-1a58-492a-8a20-e96e33f2ac2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813171888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3813171888
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1138427682
Short name T233
Test name
Test status
Simulation time 332499334 ps
CPU time 0.86 seconds
Started Jul 11 07:28:29 PM PDT 24
Finished Jul 11 07:28:32 PM PDT 24
Peak memory 205344 kb
Host smart-498d3d6f-7274-49e6-8803-8ccd3d6ae664
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138427682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1138427682
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.957664356
Short name T236
Test name
Test status
Simulation time 159958017 ps
CPU time 1.26 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:01 PM PDT 24
Peak memory 205252 kb
Host smart-0a3271f9-5a3d-4845-a993-e5a5e1334838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957664356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.957664356
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.4147503258
Short name T152
Test name
Test status
Simulation time 152665165 ps
CPU time 0.99 seconds
Started Jul 11 07:28:45 PM PDT 24
Finished Jul 11 07:28:48 PM PDT 24
Peak memory 205316 kb
Host smart-c22715df-f1ce-4405-a8eb-e8ceccec73c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147503258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.4147503258
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.226509870
Short name T116
Test name
Test status
Simulation time 5844330898 ps
CPU time 286.52 seconds
Started Jul 11 07:31:54 PM PDT 24
Finished Jul 11 07:36:41 PM PDT 24
Peak memory 1524604 kb
Host smart-6f3a83c6-1a6c-44db-b9f0-f74097142fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226509870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.226509870
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.578317797
Short name T238
Test name
Test status
Simulation time 81109261917 ps
CPU time 703.84 seconds
Started Jul 11 07:20:41 PM PDT 24
Finished Jul 11 07:32:26 PM PDT 24
Peak memory 2884920 kb
Host smart-89ed6937-6a7a-4fd3-88f4-1584f4120339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578317797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.578317797
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2553005866
Short name T229
Test name
Test status
Simulation time 28533877 ps
CPU time 1.08 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204780 kb
Host smart-a31262cd-eeb1-425c-a871-3938dbc4d9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553005866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2553005866
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2275237931
Short name T422
Test name
Test status
Simulation time 3107794798 ps
CPU time 30.85 seconds
Started Jul 11 07:21:34 PM PDT 24
Finished Jul 11 07:22:06 PM PDT 24
Peak memory 213600 kb
Host smart-08cc90ce-7cd0-4381-9c79-67e4c36a2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275237931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2275237931
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3676161831
Short name T409
Test name
Test status
Simulation time 4978673958 ps
CPU time 6.59 seconds
Started Jul 11 07:26:08 PM PDT 24
Finished Jul 11 07:26:16 PM PDT 24
Peak memory 221932 kb
Host smart-d6475fcb-1d7b-4031-8819-cedd1b103063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676161831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3676161831
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2309697016
Short name T263
Test name
Test status
Simulation time 883603890 ps
CPU time 5.42 seconds
Started Jul 11 07:28:01 PM PDT 24
Finished Jul 11 07:28:10 PM PDT 24
Peak memory 218428 kb
Host smart-9a36276c-0ef2-4e51-97cd-66deab01467b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309697016 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2309697016
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3912267145
Short name T247
Test name
Test status
Simulation time 614528838 ps
CPU time 24.13 seconds
Started Jul 11 07:28:54 PM PDT 24
Finished Jul 11 07:29:21 PM PDT 24
Peak memory 205364 kb
Host smart-7077f352-40d1-47e2-b1cf-ac801fe7c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912267145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3912267145
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2542244661
Short name T253
Test name
Test status
Simulation time 1624200991 ps
CPU time 7.65 seconds
Started Jul 11 07:29:46 PM PDT 24
Finished Jul 11 07:29:55 PM PDT 24
Peak memory 205332 kb
Host smart-6fa4152e-a668-4c0a-b5e6-ce287e31ad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542244661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2542244661
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.990775692
Short name T198
Test name
Test status
Simulation time 304187013 ps
CPU time 2.15 seconds
Started Jul 11 06:08:13 PM PDT 24
Finished Jul 11 06:08:17 PM PDT 24
Peak memory 204768 kb
Host smart-641a38bc-4022-421e-8ee3-f78aca71a83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990775692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.990775692
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.135812616
Short name T150
Test name
Test status
Simulation time 51525013 ps
CPU time 0.79 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204504 kb
Host smart-c20eda2d-abe5-4834-be57-df506de37cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135812616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.135812616
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1530699143
Short name T205
Test name
Test status
Simulation time 129118333 ps
CPU time 2.1 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204720 kb
Host smart-d4608cd6-d027-4bc6-b3a4-65291cc3dfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530699143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1530699143
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1953815143
Short name T206
Test name
Test status
Simulation time 474613414 ps
CPU time 2.38 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204748 kb
Host smart-8d7953e8-055d-4b6b-87a1-5287e0b5e4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953815143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1953815143
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3622737047
Short name T67
Test name
Test status
Simulation time 16517160602 ps
CPU time 113.93 seconds
Started Jul 11 07:34:15 PM PDT 24
Finished Jul 11 07:36:09 PM PDT 24
Peak memory 908272 kb
Host smart-a2449b74-4b7d-4f21-b3c6-072725932ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622737047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3622737047
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2369148560
Short name T1625
Test name
Test status
Simulation time 140044507 ps
CPU time 1.86 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204684 kb
Host smart-c34b59d0-bb19-4a01-99d1-6a09ec9bf70c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369148560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2369148560
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.385051604
Short name T1653
Test name
Test status
Simulation time 351373604 ps
CPU time 4.98 seconds
Started Jul 11 06:08:17 PM PDT 24
Finished Jul 11 06:08:24 PM PDT 24
Peak memory 204736 kb
Host smart-63a800c5-650b-4a5f-b99f-0c28bb34f1c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385051604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.385051604
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3577837522
Short name T226
Test name
Test status
Simulation time 20368267 ps
CPU time 0.74 seconds
Started Jul 11 06:08:10 PM PDT 24
Finished Jul 11 06:08:13 PM PDT 24
Peak memory 204388 kb
Host smart-e2d361c6-bcfe-4805-98d1-a8452cdd526a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577837522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3577837522
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2291567418
Short name T1609
Test name
Test status
Simulation time 69436894 ps
CPU time 0.81 seconds
Started Jul 11 06:08:19 PM PDT 24
Finished Jul 11 06:08:22 PM PDT 24
Peak memory 204564 kb
Host smart-6416f222-3ecf-4b36-9458-d0d3f8ae55fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291567418 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2291567418
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2127473977
Short name T1668
Test name
Test status
Simulation time 25145828 ps
CPU time 0.68 seconds
Started Jul 11 06:08:17 PM PDT 24
Finished Jul 11 06:08:19 PM PDT 24
Peak memory 204488 kb
Host smart-e109c14f-482a-4a97-a9b6-28d7c6b39ddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127473977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2127473977
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1195345521
Short name T1601
Test name
Test status
Simulation time 17592548 ps
CPU time 0.7 seconds
Started Jul 11 06:08:11 PM PDT 24
Finished Jul 11 06:08:14 PM PDT 24
Peak memory 204472 kb
Host smart-8eb44954-3621-49fe-9b55-2a7f53643ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195345521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1195345521
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3825304231
Short name T1664
Test name
Test status
Simulation time 1808284995 ps
CPU time 2.06 seconds
Started Jul 11 06:08:09 PM PDT 24
Finished Jul 11 06:08:13 PM PDT 24
Peak memory 204724 kb
Host smart-2b467b4b-29da-4e39-a166-8a5d63d112cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825304231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3825304231
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.380555148
Short name T225
Test name
Test status
Simulation time 132607224 ps
CPU time 1.84 seconds
Started Jul 11 06:08:16 PM PDT 24
Finished Jul 11 06:08:20 PM PDT 24
Peak memory 204748 kb
Host smart-94504250-ebb9-4dd0-85cb-537293614b10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380555148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.380555148
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3096322803
Short name T223
Test name
Test status
Simulation time 1896325035 ps
CPU time 2.82 seconds
Started Jul 11 06:08:16 PM PDT 24
Finished Jul 11 06:08:21 PM PDT 24
Peak memory 204668 kb
Host smart-50c22dfa-152c-4f1c-868e-9e3bdbdc50e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096322803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3096322803
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1260217404
Short name T217
Test name
Test status
Simulation time 18782997 ps
CPU time 0.76 seconds
Started Jul 11 06:08:13 PM PDT 24
Finished Jul 11 06:08:16 PM PDT 24
Peak memory 204488 kb
Host smart-83da9a66-fb9f-47ea-91c4-ff774e928b83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260217404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1260217404
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2903553418
Short name T178
Test name
Test status
Simulation time 90551421 ps
CPU time 1.41 seconds
Started Jul 11 06:08:15 PM PDT 24
Finished Jul 11 06:08:18 PM PDT 24
Peak memory 213072 kb
Host smart-3aab4a71-aaa3-4cb9-9ea7-d27e86e6586f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903553418 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2903553418
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.32551845
Short name T215
Test name
Test status
Simulation time 17797395 ps
CPU time 0.77 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204440 kb
Host smart-7ce7c255-9cad-453a-ad45-9d045b304af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32551845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.32551845
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.821791303
Short name T1623
Test name
Test status
Simulation time 14989289 ps
CPU time 0.67 seconds
Started Jul 11 06:08:18 PM PDT 24
Finished Jul 11 06:08:20 PM PDT 24
Peak memory 204452 kb
Host smart-3733d4ea-fb28-4466-af39-eebe767c4163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821791303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.821791303
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3604859548
Short name T1652
Test name
Test status
Simulation time 134812206 ps
CPU time 0.89 seconds
Started Jul 11 06:08:15 PM PDT 24
Finished Jul 11 06:08:17 PM PDT 24
Peak memory 204488 kb
Host smart-63cc12ab-7cd0-4102-a513-fe31c336ce13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604859548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3604859548
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1976911893
Short name T1596
Test name
Test status
Simulation time 125472965 ps
CPU time 2.36 seconds
Started Jul 11 06:08:16 PM PDT 24
Finished Jul 11 06:08:20 PM PDT 24
Peak memory 212960 kb
Host smart-d47e61b7-c393-47c8-81ee-b42a81893b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976911893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1976911893
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3348080059
Short name T1629
Test name
Test status
Simulation time 513090324 ps
CPU time 2.26 seconds
Started Jul 11 06:08:16 PM PDT 24
Finished Jul 11 06:08:19 PM PDT 24
Peak memory 204596 kb
Host smart-0fbe0c75-f102-4c31-9e90-8b51f68bd741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348080059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3348080059
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2108156258
Short name T1584
Test name
Test status
Simulation time 35675193 ps
CPU time 1.04 seconds
Started Jul 11 06:08:30 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204520 kb
Host smart-bdc52a3f-1ad6-4b95-a02e-6514d52c47c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108156258 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2108156258
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1748417193
Short name T102
Test name
Test status
Simulation time 81111161 ps
CPU time 0.82 seconds
Started Jul 11 06:08:31 PM PDT 24
Finished Jul 11 06:08:34 PM PDT 24
Peak memory 204488 kb
Host smart-cd5548c5-2413-4266-b8e4-03c5c6b8e07d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748417193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1748417193
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.632451316
Short name T1662
Test name
Test status
Simulation time 31317539 ps
CPU time 0.69 seconds
Started Jul 11 06:08:30 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204424 kb
Host smart-a533cefc-433f-4baf-b0cc-b09a24c44681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632451316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.632451316
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4060697350
Short name T1649
Test name
Test status
Simulation time 36545168 ps
CPU time 0.89 seconds
Started Jul 11 06:08:31 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204588 kb
Host smart-b95a4698-d344-483e-8f46-1d0c20bc13ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060697350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.4060697350
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.659444024
Short name T203
Test name
Test status
Simulation time 152631428 ps
CPU time 2.24 seconds
Started Jul 11 06:08:30 PM PDT 24
Finished Jul 11 06:08:35 PM PDT 24
Peak memory 204796 kb
Host smart-db354f54-d7a6-4477-bccd-88a670098993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659444024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.659444024
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2641844398
Short name T213
Test name
Test status
Simulation time 242189376 ps
CPU time 1 seconds
Started Jul 11 06:08:34 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204820 kb
Host smart-2d40e411-a6da-4f67-aafa-f85bfb24e75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641844398 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2641844398
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2649783097
Short name T224
Test name
Test status
Simulation time 92930573 ps
CPU time 0.78 seconds
Started Jul 11 06:08:34 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204496 kb
Host smart-719d698c-592d-47dc-8e88-c0aaf63fa235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649783097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2649783097
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3145221105
Short name T1599
Test name
Test status
Simulation time 27988424 ps
CPU time 0.7 seconds
Started Jul 11 06:08:35 PM PDT 24
Finished Jul 11 06:08:37 PM PDT 24
Peak memory 204480 kb
Host smart-1c98fba7-f27e-437f-a82e-21f00c1aec9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145221105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3145221105
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1691893730
Short name T97
Test name
Test status
Simulation time 226382815 ps
CPU time 1.19 seconds
Started Jul 11 06:08:36 PM PDT 24
Finished Jul 11 06:08:38 PM PDT 24
Peak memory 204824 kb
Host smart-50a83a84-b87a-4048-a89e-77b27476c79d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691893730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1691893730
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.998294280
Short name T209
Test name
Test status
Simulation time 121880943 ps
CPU time 1.66 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:42 PM PDT 24
Peak memory 204756 kb
Host smart-fb27cebd-654e-418a-832e-f855d1a9c92d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998294280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.998294280
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.964488831
Short name T1602
Test name
Test status
Simulation time 221259349 ps
CPU time 1.5 seconds
Started Jul 11 06:08:29 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204780 kb
Host smart-f757badd-160a-4957-a9db-145149156cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964488831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.964488831
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2427643953
Short name T1634
Test name
Test status
Simulation time 106573630 ps
CPU time 0.92 seconds
Started Jul 11 06:08:33 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204508 kb
Host smart-9bf9baee-b300-4f3a-9b99-ca9dd5b4e4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427643953 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2427643953
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1195319991
Short name T1644
Test name
Test status
Simulation time 23849767 ps
CPU time 0.82 seconds
Started Jul 11 06:08:34 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204392 kb
Host smart-bb078ef7-0f04-4bab-84c2-b0a09ca42011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195319991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1195319991
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.12781836
Short name T1567
Test name
Test status
Simulation time 18191849 ps
CPU time 0.77 seconds
Started Jul 11 06:08:32 PM PDT 24
Finished Jul 11 06:08:34 PM PDT 24
Peak memory 204472 kb
Host smart-c450a9a0-0332-4cd2-bb4d-006b8a47f4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.12781836
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1162434208
Short name T1605
Test name
Test status
Simulation time 21654841 ps
CPU time 0.84 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:41 PM PDT 24
Peak memory 204572 kb
Host smart-2b81b98e-b224-4aae-a183-17467f700b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162434208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1162434208
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2431678981
Short name T1587
Test name
Test status
Simulation time 180431377 ps
CPU time 1.21 seconds
Started Jul 11 06:08:36 PM PDT 24
Finished Jul 11 06:08:38 PM PDT 24
Peak memory 204792 kb
Host smart-3845aa04-9295-4a84-aea8-c65c5743b5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431678981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2431678981
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3113545642
Short name T199
Test name
Test status
Simulation time 265703799 ps
CPU time 1.69 seconds
Started Jul 11 06:08:33 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204740 kb
Host smart-e4df2467-da6c-4651-ad35-f9edca1aa525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113545642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3113545642
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.114450434
Short name T1656
Test name
Test status
Simulation time 89260389 ps
CPU time 0.85 seconds
Started Jul 11 06:08:33 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204572 kb
Host smart-7f029e13-ba19-441f-82c9-7b37f0a6b9ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114450434 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.114450434
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2281680113
Short name T1633
Test name
Test status
Simulation time 19930597 ps
CPU time 0.82 seconds
Started Jul 11 06:08:36 PM PDT 24
Finished Jul 11 06:08:38 PM PDT 24
Peak memory 204488 kb
Host smart-f9bee7a2-25d8-47af-87e0-5482945cdee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281680113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2281680113
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1414706237
Short name T1624
Test name
Test status
Simulation time 17698213 ps
CPU time 0.74 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:40 PM PDT 24
Peak memory 204480 kb
Host smart-6d2f9cef-88d7-429d-bc11-0dc28bb37515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414706237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1414706237
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3233441528
Short name T1611
Test name
Test status
Simulation time 33494001 ps
CPU time 0.86 seconds
Started Jul 11 06:08:34 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204536 kb
Host smart-15563de3-c316-4172-a423-dd6fb7452c4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233441528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3233441528
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2041476543
Short name T140
Test name
Test status
Simulation time 191246102 ps
CPU time 2.17 seconds
Started Jul 11 06:08:33 PM PDT 24
Finished Jul 11 06:08:36 PM PDT 24
Peak memory 204740 kb
Host smart-5141acc8-9251-4729-b69d-125e0ba9cd3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041476543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2041476543
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.225196430
Short name T1598
Test name
Test status
Simulation time 88263127 ps
CPU time 1.4 seconds
Started Jul 11 06:08:37 PM PDT 24
Finished Jul 11 06:08:39 PM PDT 24
Peak memory 204752 kb
Host smart-b9586986-1039-4459-9dff-c5a708318350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225196430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.225196430
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2232778115
Short name T219
Test name
Test status
Simulation time 119548187 ps
CPU time 0.78 seconds
Started Jul 11 06:08:37 PM PDT 24
Finished Jul 11 06:08:39 PM PDT 24
Peak memory 204492 kb
Host smart-fb0816b6-2566-404f-ad55-65fd0eab8831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232778115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2232778115
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3902402493
Short name T1578
Test name
Test status
Simulation time 19461297 ps
CPU time 0.7 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:40 PM PDT 24
Peak memory 204460 kb
Host smart-7717354b-0011-439e-908b-0b26a5bc435c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902402493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3902402493
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2217398393
Short name T1659
Test name
Test status
Simulation time 91121393 ps
CPU time 1.11 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:42 PM PDT 24
Peak memory 204832 kb
Host smart-31979fab-b54e-4c87-a9d5-7052c9c273ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217398393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2217398393
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3788701932
Short name T1658
Test name
Test status
Simulation time 276434478 ps
CPU time 1.63 seconds
Started Jul 11 06:08:34 PM PDT 24
Finished Jul 11 06:08:37 PM PDT 24
Peak memory 204772 kb
Host smart-a264a270-6927-4af4-a183-c376bee60e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788701932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3788701932
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1592801834
Short name T1671
Test name
Test status
Simulation time 57952924 ps
CPU time 1.43 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:44 PM PDT 24
Peak memory 204800 kb
Host smart-1800a4a3-b46a-4cbc-a4b0-f1947ad29a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592801834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1592801834
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.461541116
Short name T1594
Test name
Test status
Simulation time 26736438 ps
CPU time 0.87 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:42 PM PDT 24
Peak memory 204596 kb
Host smart-15bef90e-ffd8-49c3-bb28-d2187e592af9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461541116 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.461541116
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1415935718
Short name T1592
Test name
Test status
Simulation time 41405257 ps
CPU time 0.83 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204492 kb
Host smart-a2aba138-2861-4235-9247-d879a4687967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415935718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1415935718
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1127125369
Short name T1582
Test name
Test status
Simulation time 63143410 ps
CPU time 0.68 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204468 kb
Host smart-6d1e4255-b309-4427-a2be-266195cbf087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127125369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1127125369
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3091446864
Short name T1639
Test name
Test status
Simulation time 33620943 ps
CPU time 1.18 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204772 kb
Host smart-22d43511-4644-4a6a-9f8e-5ec5b749220a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091446864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3091446864
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.634986603
Short name T196
Test name
Test status
Simulation time 181044557 ps
CPU time 2.41 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204648 kb
Host smart-ad666262-deed-435e-9d67-156f647b8c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634986603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.634986603
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3726294351
Short name T261
Test name
Test status
Simulation time 53851543 ps
CPU time 1.45 seconds
Started Jul 11 06:08:42 PM PDT 24
Finished Jul 11 06:08:45 PM PDT 24
Peak memory 204796 kb
Host smart-0f8d6ebf-572c-4844-952a-3f6d0e533fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726294351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3726294351
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1975848790
Short name T1612
Test name
Test status
Simulation time 67348307 ps
CPU time 0.78 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:41 PM PDT 24
Peak memory 204524 kb
Host smart-374119ad-9ce0-48a9-a074-b5a99c967f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975848790 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1975848790
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1083893338
Short name T1580
Test name
Test status
Simulation time 27797383 ps
CPU time 0.67 seconds
Started Jul 11 06:08:39 PM PDT 24
Finished Jul 11 06:08:41 PM PDT 24
Peak memory 204460 kb
Host smart-ac6b3732-86aa-4fd3-b94a-ff2901eb3e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083893338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1083893338
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4074712864
Short name T228
Test name
Test status
Simulation time 65086954 ps
CPU time 0.87 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204536 kb
Host smart-093e0d7a-e3e6-4864-aa7c-4320b4feef5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074712864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.4074712864
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3564694725
Short name T1635
Test name
Test status
Simulation time 49942761 ps
CPU time 1.47 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204764 kb
Host smart-7086420c-282c-4b6c-b7af-988157a3a403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564694725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3564694725
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1003081988
Short name T193
Test name
Test status
Simulation time 125087232 ps
CPU time 2.36 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:45 PM PDT 24
Peak memory 204788 kb
Host smart-3f26f3f8-fa7c-49d0-ac3a-31a307460d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003081988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1003081988
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.357276658
Short name T1663
Test name
Test status
Simulation time 347865741 ps
CPU time 1.01 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:51 PM PDT 24
Peak memory 204476 kb
Host smart-dd859eb9-b308-40e7-88ec-91b4f8335aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357276658 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.357276658
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.692970402
Short name T1646
Test name
Test status
Simulation time 64398206 ps
CPU time 0.76 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:44 PM PDT 24
Peak memory 204468 kb
Host smart-2a0627d2-7ca1-41b2-9d6c-4d4051579a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692970402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.692970402
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1938698535
Short name T1666
Test name
Test status
Simulation time 21917899 ps
CPU time 0.65 seconds
Started Jul 11 06:08:43 PM PDT 24
Finished Jul 11 06:08:46 PM PDT 24
Peak memory 204476 kb
Host smart-37511710-e175-4590-a81c-150e1f4e2b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938698535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1938698535
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2322843260
Short name T207
Test name
Test status
Simulation time 64291337 ps
CPU time 0.85 seconds
Started Jul 11 06:08:41 PM PDT 24
Finished Jul 11 06:08:44 PM PDT 24
Peak memory 204508 kb
Host smart-37810903-218c-49cc-8767-be86426d8932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322843260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2322843260
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4083414608
Short name T201
Test name
Test status
Simulation time 31578607 ps
CPU time 1.5 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:43 PM PDT 24
Peak memory 204792 kb
Host smart-5ec554a1-1ec7-4994-89fd-8dd292ae50b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083414608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.4083414608
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3078286555
Short name T103
Test name
Test status
Simulation time 75776044 ps
CPU time 1.52 seconds
Started Jul 11 06:08:40 PM PDT 24
Finished Jul 11 06:08:44 PM PDT 24
Peak memory 204760 kb
Host smart-e13ffa6f-1382-46cb-9802-0a817469dd6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078286555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3078286555
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.185204022
Short name T1600
Test name
Test status
Simulation time 23125782 ps
CPU time 0.94 seconds
Started Jul 11 06:08:46 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204588 kb
Host smart-7cda7397-2e99-4bb3-962b-859c3f237e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185204022 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.185204022
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3997778666
Short name T1593
Test name
Test status
Simulation time 18275626 ps
CPU time 0.67 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204408 kb
Host smart-135f4cd5-96d9-4ca8-8049-7ada4a41a756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997778666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3997778666
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1145458578
Short name T1574
Test name
Test status
Simulation time 25762942 ps
CPU time 0.65 seconds
Started Jul 11 06:08:44 PM PDT 24
Finished Jul 11 06:08:46 PM PDT 24
Peak memory 204400 kb
Host smart-6df12794-339a-40ca-8887-16645e81d4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145458578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1145458578
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2895100667
Short name T1665
Test name
Test status
Simulation time 223844455 ps
CPU time 1.18 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204844 kb
Host smart-501ed477-0db3-4b71-9ae2-0d64ec9d23ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895100667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2895100667
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3377816472
Short name T195
Test name
Test status
Simulation time 375657538 ps
CPU time 1.87 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:52 PM PDT 24
Peak memory 204744 kb
Host smart-61b483b2-9038-4d10-96ce-b0ed9f4ffeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377816472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3377816472
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1603602002
Short name T1607
Test name
Test status
Simulation time 41801548 ps
CPU time 0.82 seconds
Started Jul 11 06:08:46 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204620 kb
Host smart-9169d7d0-58d4-4338-8652-b6915912490e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603602002 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1603602002
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3441216670
Short name T99
Test name
Test status
Simulation time 33624560 ps
CPU time 0.75 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:51 PM PDT 24
Peak memory 204460 kb
Host smart-5c68f1b7-a982-40ca-b95e-13aacce0fc07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441216670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3441216670
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2585197562
Short name T276
Test name
Test status
Simulation time 26919956 ps
CPU time 0.66 seconds
Started Jul 11 06:08:44 PM PDT 24
Finished Jul 11 06:08:47 PM PDT 24
Peak memory 204420 kb
Host smart-4e67ae2d-537e-4a7b-a9bd-03e5e1338d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585197562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2585197562
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.576250531
Short name T1630
Test name
Test status
Simulation time 43163205 ps
CPU time 0.86 seconds
Started Jul 11 06:08:42 PM PDT 24
Finished Jul 11 06:08:45 PM PDT 24
Peak memory 204492 kb
Host smart-97258e1b-a348-4715-bea2-0ecfbd4ffea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576250531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.576250531
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.960597114
Short name T179
Test name
Test status
Simulation time 77138632 ps
CPU time 2.2 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204724 kb
Host smart-a402ad31-b262-4add-b00a-0d07123b0256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960597114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.960597114
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1989697236
Short name T1588
Test name
Test status
Simulation time 74730323 ps
CPU time 1.25 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204644 kb
Host smart-a9412681-1d3a-4bb4-a6f6-e7b7544fd37b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989697236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1989697236
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3098511132
Short name T1621
Test name
Test status
Simulation time 1832365911 ps
CPU time 5.13 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 204684 kb
Host smart-8eb7cad0-cc5c-462b-b10b-e8217c848c06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098511132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3098511132
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.982185388
Short name T220
Test name
Test status
Simulation time 23194682 ps
CPU time 0.79 seconds
Started Jul 11 06:08:15 PM PDT 24
Finished Jul 11 06:08:18 PM PDT 24
Peak memory 204452 kb
Host smart-e5c644e3-857f-4b25-af1a-b0566dd6e6fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982185388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.982185388
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1637141157
Short name T1620
Test name
Test status
Simulation time 208382218 ps
CPU time 0.84 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204628 kb
Host smart-98d19d8b-ecd4-4890-8e49-cd31526bfca4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637141157 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1637141157
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3073728752
Short name T222
Test name
Test status
Simulation time 21592324 ps
CPU time 0.71 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204424 kb
Host smart-67c68e9c-ece7-47fb-9c88-5b569cfc7bf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073728752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3073728752
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1386396487
Short name T1648
Test name
Test status
Simulation time 139039627 ps
CPU time 0.69 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204416 kb
Host smart-62bd83e4-75b9-46f6-ae20-835227a2a57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386396487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1386396487
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1704063437
Short name T1626
Test name
Test status
Simulation time 158269447 ps
CPU time 1.1 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204796 kb
Host smart-35f92b71-9eba-4c6b-afc5-ecdeccb26d7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704063437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1704063437
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.155550882
Short name T1636
Test name
Test status
Simulation time 43956954 ps
CPU time 1.22 seconds
Started Jul 11 06:08:13 PM PDT 24
Finished Jul 11 06:08:16 PM PDT 24
Peak memory 204760 kb
Host smart-c8c229c8-24c3-461c-b30b-a1e7692b099d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155550882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.155550882
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.4029909153
Short name T1571
Test name
Test status
Simulation time 43916175 ps
CPU time 0.67 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204452 kb
Host smart-f0c2bbad-717e-45bb-ab9c-fe3668c5dac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029909153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.4029909153
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2606265888
Short name T1570
Test name
Test status
Simulation time 15816020 ps
CPU time 0.66 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204456 kb
Host smart-8301a430-b286-47c7-b684-d23d394f7a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606265888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2606265888
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.875495061
Short name T1637
Test name
Test status
Simulation time 52237169 ps
CPU time 0.66 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204452 kb
Host smart-c7585b32-0e3d-4f1b-b70c-c990345f32de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875495061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.875495061
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1182446359
Short name T1615
Test name
Test status
Simulation time 63653309 ps
CPU time 0.72 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:52 PM PDT 24
Peak memory 204468 kb
Host smart-6f7689dc-2959-4630-a408-386fd35dc68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182446359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1182446359
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.815675591
Short name T275
Test name
Test status
Simulation time 23059972 ps
CPU time 0.7 seconds
Started Jul 11 06:08:45 PM PDT 24
Finished Jul 11 06:08:48 PM PDT 24
Peak memory 204320 kb
Host smart-d13ff6e5-19f8-4fd3-8d0a-f6c6b37c28d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815675591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.815675591
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.4177698743
Short name T1657
Test name
Test status
Simulation time 39809859 ps
CPU time 0.63 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:51 PM PDT 24
Peak memory 204312 kb
Host smart-e7118e0c-5be0-4404-b189-e178f38b11a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177698743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.4177698743
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.890092683
Short name T1583
Test name
Test status
Simulation time 14850542 ps
CPU time 0.69 seconds
Started Jul 11 06:08:42 PM PDT 24
Finished Jul 11 06:08:44 PM PDT 24
Peak memory 204668 kb
Host smart-7cff5bf8-d2e1-42cf-80cf-5309d1eb3d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890092683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.890092683
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2308764012
Short name T1650
Test name
Test status
Simulation time 15486550 ps
CPU time 0.71 seconds
Started Jul 11 06:08:49 PM PDT 24
Finished Jul 11 06:08:51 PM PDT 24
Peak memory 204464 kb
Host smart-4d94be74-d49f-43a2-a869-facc96e4d228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308764012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2308764012
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3294860689
Short name T1575
Test name
Test status
Simulation time 15912769 ps
CPU time 0.67 seconds
Started Jul 11 06:08:47 PM PDT 24
Finished Jul 11 06:08:49 PM PDT 24
Peak memory 204456 kb
Host smart-9083944f-1504-4531-9831-0741fe2c06a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294860689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3294860689
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2503994628
Short name T218
Test name
Test status
Simulation time 131602224 ps
CPU time 1.86 seconds
Started Jul 11 06:08:18 PM PDT 24
Finished Jul 11 06:08:21 PM PDT 24
Peak memory 204660 kb
Host smart-f96b07ca-8951-41e2-b2c6-c41ef1ed9a1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503994628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2503994628
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1066449498
Short name T221
Test name
Test status
Simulation time 425010934 ps
CPU time 4.52 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:27 PM PDT 24
Peak memory 204744 kb
Host smart-a8d2cd9a-f3de-4735-9c0d-9a06b2320222
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066449498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1066449498
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1743561061
Short name T1645
Test name
Test status
Simulation time 67046142 ps
CPU time 0.7 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204456 kb
Host smart-336fe26b-0e67-4d78-b164-48f921655f7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743561061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1743561061
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1390157864
Short name T1608
Test name
Test status
Simulation time 282992699 ps
CPU time 0.85 seconds
Started Jul 11 06:08:24 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204524 kb
Host smart-1306ae67-5a25-464a-aad5-7960700f5137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390157864 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1390157864
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2868371689
Short name T1672
Test name
Test status
Simulation time 63637417 ps
CPU time 0.78 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:24 PM PDT 24
Peak memory 204408 kb
Host smart-0085e4cd-858a-4836-8720-e41195efa7b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868371689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2868371689
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.483752783
Short name T1576
Test name
Test status
Simulation time 47929440 ps
CPU time 0.72 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:24 PM PDT 24
Peak memory 204476 kb
Host smart-64861b6c-0d30-4b9e-9df4-339080c8e6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483752783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.483752783
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2819722667
Short name T1585
Test name
Test status
Simulation time 58989175 ps
CPU time 0.83 seconds
Started Jul 11 06:08:19 PM PDT 24
Finished Jul 11 06:08:22 PM PDT 24
Peak memory 204532 kb
Host smart-1082b4c9-96ea-4ed1-8ac7-4d035d13f06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819722667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2819722667
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2581425188
Short name T1643
Test name
Test status
Simulation time 284351065 ps
CPU time 2.74 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204728 kb
Host smart-b471cf3d-46fe-4b13-973f-98cea396f3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581425188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2581425188
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3279428424
Short name T202
Test name
Test status
Simulation time 85152934 ps
CPU time 1.57 seconds
Started Jul 11 06:08:19 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204788 kb
Host smart-d4987988-b3bb-45d7-84f9-a2d942ecfc9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279428424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3279428424
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1816953921
Short name T1597
Test name
Test status
Simulation time 111894379 ps
CPU time 0.7 seconds
Started Jul 11 06:08:44 PM PDT 24
Finished Jul 11 06:08:46 PM PDT 24
Peak memory 204672 kb
Host smart-a4a8b98b-50a6-4df0-9e0f-6314c9cbfa22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816953921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1816953921
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.4205386889
Short name T1674
Test name
Test status
Simulation time 43698351 ps
CPU time 0.62 seconds
Started Jul 11 06:08:43 PM PDT 24
Finished Jul 11 06:08:45 PM PDT 24
Peak memory 204436 kb
Host smart-06b16da2-21ae-4348-b96e-283e2f3f17f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205386889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4205386889
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.547960945
Short name T1628
Test name
Test status
Simulation time 40128138 ps
CPU time 0.67 seconds
Started Jul 11 06:08:54 PM PDT 24
Finished Jul 11 06:08:56 PM PDT 24
Peak memory 204416 kb
Host smart-9437edab-3e18-4e57-b62d-57d9054a9b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547960945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.547960945
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.516708092
Short name T1579
Test name
Test status
Simulation time 50849220 ps
CPU time 0.65 seconds
Started Jul 11 06:08:55 PM PDT 24
Finished Jul 11 06:08:58 PM PDT 24
Peak memory 204448 kb
Host smart-070019c4-1a69-43d5-a846-512914ce9c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516708092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.516708092
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3042957119
Short name T1590
Test name
Test status
Simulation time 23600459 ps
CPU time 0.67 seconds
Started Jul 11 06:08:54 PM PDT 24
Finished Jul 11 06:08:56 PM PDT 24
Peak memory 204460 kb
Host smart-979c2e80-9680-49b8-9315-4b4bbafa98da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042957119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3042957119
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.4136808230
Short name T1604
Test name
Test status
Simulation time 20511722 ps
CPU time 0.73 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:54 PM PDT 24
Peak memory 204440 kb
Host smart-67ce88f4-2b45-4e82-a4da-d397bf8c0369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136808230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4136808230
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2749033298
Short name T277
Test name
Test status
Simulation time 39724377 ps
CPU time 0.67 seconds
Started Jul 11 06:08:56 PM PDT 24
Finished Jul 11 06:08:59 PM PDT 24
Peak memory 204460 kb
Host smart-d749c750-d75c-43a1-8179-ba75186bb5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749033298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2749033298
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1786774512
Short name T1572
Test name
Test status
Simulation time 26596701 ps
CPU time 0.68 seconds
Started Jul 11 06:08:53 PM PDT 24
Finished Jul 11 06:08:56 PM PDT 24
Peak memory 204464 kb
Host smart-e723aa4d-ff5b-40a1-9f26-fdcb72972da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786774512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1786774512
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2863638781
Short name T272
Test name
Test status
Simulation time 47281643 ps
CPU time 0.7 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:53 PM PDT 24
Peak memory 204372 kb
Host smart-e4780866-9d44-4809-b6ae-4e14d91cd20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863638781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2863638781
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3150890769
Short name T1569
Test name
Test status
Simulation time 19770055 ps
CPU time 0.7 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:55 PM PDT 24
Peak memory 204436 kb
Host smart-e62de9bb-012c-4179-bae9-9707dc2baa31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150890769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3150890769
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1687241718
Short name T1577
Test name
Test status
Simulation time 174803466 ps
CPU time 1.25 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:24 PM PDT 24
Peak memory 204684 kb
Host smart-bd5de1d9-67a4-47f7-ad5d-ed649a80e1ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687241718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1687241718
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3499488287
Short name T1632
Test name
Test status
Simulation time 185001609 ps
CPU time 2.78 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:25 PM PDT 24
Peak memory 204720 kb
Host smart-ddebc22a-25dd-40e1-9e5c-a27b4c2d937e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499488287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3499488287
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2393936537
Short name T227
Test name
Test status
Simulation time 41499379 ps
CPU time 0.77 seconds
Started Jul 11 06:08:20 PM PDT 24
Finished Jul 11 06:08:23 PM PDT 24
Peak memory 204480 kb
Host smart-9805215d-f602-4dd2-b137-28e40b79da44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393936537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2393936537
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4049317331
Short name T1654
Test name
Test status
Simulation time 92276812 ps
CPU time 0.83 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:27 PM PDT 24
Peak memory 204548 kb
Host smart-41e6e6a5-9562-4b3b-b532-611de2e2bcd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049317331 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4049317331
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3882083294
Short name T1614
Test name
Test status
Simulation time 22553641 ps
CPU time 0.69 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204452 kb
Host smart-6851338d-5eab-4880-9461-cee0b3973298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882083294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3882083294
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.228651940
Short name T1622
Test name
Test status
Simulation time 404325418 ps
CPU time 2.39 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204672 kb
Host smart-513d56ee-54c0-4af3-aac6-b36126859800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228651940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.228651940
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3628593696
Short name T1655
Test name
Test status
Simulation time 332813866 ps
CPU time 1.43 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:25 PM PDT 24
Peak memory 204724 kb
Host smart-8e9ef7f4-b97b-43b4-8888-aeff6d57ec6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628593696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3628593696
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1606668867
Short name T1603
Test name
Test status
Simulation time 92426396 ps
CPU time 0.69 seconds
Started Jul 11 06:08:53 PM PDT 24
Finished Jul 11 06:08:56 PM PDT 24
Peak memory 204428 kb
Host smart-fa6be0ce-c928-4b6c-abf1-4a6bf3f564f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606668867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1606668867
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3684336560
Short name T1642
Test name
Test status
Simulation time 69820659 ps
CPU time 0.66 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:54 PM PDT 24
Peak memory 204460 kb
Host smart-01977f9b-0a48-45ee-b678-d38adbfb21e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684336560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3684336560
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3640472710
Short name T117
Test name
Test status
Simulation time 91855159 ps
CPU time 0.73 seconds
Started Jul 11 06:08:53 PM PDT 24
Finished Jul 11 06:08:55 PM PDT 24
Peak memory 204460 kb
Host smart-4e08a411-a92e-424e-8d3e-090aad252584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640472710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3640472710
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.107071505
Short name T1673
Test name
Test status
Simulation time 20477642 ps
CPU time 0.69 seconds
Started Jul 11 06:08:55 PM PDT 24
Finished Jul 11 06:08:58 PM PDT 24
Peak memory 204452 kb
Host smart-96c748c7-5483-453d-b1a6-953e83747b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107071505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.107071505
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1271748173
Short name T1667
Test name
Test status
Simulation time 22833491 ps
CPU time 0.71 seconds
Started Jul 11 06:08:53 PM PDT 24
Finished Jul 11 06:08:55 PM PDT 24
Peak memory 204472 kb
Host smart-5a5d9b27-626e-4503-9d6a-9548b7524ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271748173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1271748173
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1559887307
Short name T1670
Test name
Test status
Simulation time 60941290 ps
CPU time 0.69 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:54 PM PDT 24
Peak memory 204360 kb
Host smart-bb6ba229-3a76-4fa6-8d15-97a0ccb687f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559887307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1559887307
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2469903439
Short name T1586
Test name
Test status
Simulation time 18369127 ps
CPU time 0.7 seconds
Started Jul 11 06:08:54 PM PDT 24
Finished Jul 11 06:08:57 PM PDT 24
Peak memory 204420 kb
Host smart-8df4712d-b090-44c5-b50b-585205dca96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469903439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2469903439
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2342284267
Short name T1581
Test name
Test status
Simulation time 22152817 ps
CPU time 0.66 seconds
Started Jul 11 06:08:53 PM PDT 24
Finished Jul 11 06:08:55 PM PDT 24
Peak memory 204456 kb
Host smart-804f1d14-9928-4bb7-9e2f-dad75a5f4ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342284267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2342284267
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3388213048
Short name T278
Test name
Test status
Simulation time 22340991 ps
CPU time 0.66 seconds
Started Jul 11 06:08:52 PM PDT 24
Finished Jul 11 06:08:53 PM PDT 24
Peak memory 204476 kb
Host smart-d704ded5-e988-4651-9ae5-01b792fc9598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388213048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3388213048
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3014087941
Short name T1616
Test name
Test status
Simulation time 16422994 ps
CPU time 0.66 seconds
Started Jul 11 06:08:57 PM PDT 24
Finished Jul 11 06:09:01 PM PDT 24
Peak memory 204460 kb
Host smart-8d9924d7-40ab-406f-aef6-fbafb694ae21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014087941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3014087941
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1440694715
Short name T101
Test name
Test status
Simulation time 26837141 ps
CPU time 0.82 seconds
Started Jul 11 06:08:21 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204608 kb
Host smart-87d63afe-cac0-4774-84fa-06e6bbc69c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440694715 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1440694715
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1141697179
Short name T1660
Test name
Test status
Simulation time 16826073 ps
CPU time 0.69 seconds
Started Jul 11 06:08:19 PM PDT 24
Finished Jul 11 06:08:21 PM PDT 24
Peak memory 204488 kb
Host smart-1e0ce77f-2de9-49b7-8003-ee3a2d90a0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141697179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1141697179
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3594054238
Short name T274
Test name
Test status
Simulation time 31571540 ps
CPU time 0.7 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204448 kb
Host smart-1e0b79da-fe66-4381-bd74-fdab3c94191f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594054238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3594054238
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2292609116
Short name T1606
Test name
Test status
Simulation time 62589461 ps
CPU time 0.82 seconds
Started Jul 11 06:08:32 PM PDT 24
Finished Jul 11 06:08:35 PM PDT 24
Peak memory 204508 kb
Host smart-ed9aa7af-bdd7-45bb-a87e-1a886369b112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292609116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2292609116
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.756955006
Short name T1619
Test name
Test status
Simulation time 27131586 ps
CPU time 1.3 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204760 kb
Host smart-3074b4c8-4f55-4291-a107-8b2102e80910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756955006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.756955006
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3803822073
Short name T204
Test name
Test status
Simulation time 514322118 ps
CPU time 2.21 seconds
Started Jul 11 06:08:18 PM PDT 24
Finished Jul 11 06:08:22 PM PDT 24
Peak memory 204656 kb
Host smart-cb71117e-2f66-48ec-b62d-6cb1a887126c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803822073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3803822073
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3510305919
Short name T1647
Test name
Test status
Simulation time 30162135 ps
CPU time 0.88 seconds
Started Jul 11 06:08:25 PM PDT 24
Finished Jul 11 06:08:30 PM PDT 24
Peak memory 204588 kb
Host smart-fca35717-348d-4982-b404-a3afcbced5aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510305919 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3510305919
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1365537282
Short name T104
Test name
Test status
Simulation time 20132313 ps
CPU time 0.72 seconds
Started Jul 11 06:08:25 PM PDT 24
Finished Jul 11 06:08:30 PM PDT 24
Peak memory 204488 kb
Host smart-00dcbc56-891b-4bd6-9bc3-9ffff1a19cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365537282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1365537282
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.737156886
Short name T1595
Test name
Test status
Simulation time 57423817 ps
CPU time 0.67 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:26 PM PDT 24
Peak memory 204456 kb
Host smart-85e4fa0e-47aa-4f93-a23c-d5419025dfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737156886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.737156886
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3860662522
Short name T1617
Test name
Test status
Simulation time 20394691 ps
CPU time 0.84 seconds
Started Jul 11 06:08:25 PM PDT 24
Finished Jul 11 06:08:30 PM PDT 24
Peak memory 204464 kb
Host smart-7f5921c9-da38-4a5b-be63-308340f7adfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860662522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3860662522
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.705657305
Short name T1613
Test name
Test status
Simulation time 119794194 ps
CPU time 1.4 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:27 PM PDT 24
Peak memory 204848 kb
Host smart-453da8c8-c717-407a-adb0-e5ef3051f950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705657305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.705657305
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3822727905
Short name T1591
Test name
Test status
Simulation time 78757021 ps
CPU time 1.48 seconds
Started Jul 11 06:08:24 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204688 kb
Host smart-3d58769a-c783-483c-b127-6d1406996791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822727905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3822727905
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.588336227
Short name T100
Test name
Test status
Simulation time 100651351 ps
CPU time 1.02 seconds
Started Jul 11 06:08:26 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 204572 kb
Host smart-b902af4a-8009-4e89-bd38-f64bf8b6f9a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588336227 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.588336227
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1050958285
Short name T1641
Test name
Test status
Simulation time 29292278 ps
CPU time 0.84 seconds
Started Jul 11 06:08:29 PM PDT 24
Finished Jul 11 06:08:32 PM PDT 24
Peak memory 204488 kb
Host smart-c301e893-d7d7-4368-a9fe-610341cda427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050958285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1050958285
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1369167009
Short name T1651
Test name
Test status
Simulation time 60548602 ps
CPU time 0.71 seconds
Started Jul 11 06:08:28 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 204448 kb
Host smart-32873896-b4ed-4a97-9a68-76c8b5ab96dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369167009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1369167009
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3537771021
Short name T1638
Test name
Test status
Simulation time 150679806 ps
CPU time 0.96 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:27 PM PDT 24
Peak memory 204544 kb
Host smart-e5caaa06-ac74-4af0-82d4-7044ceabca5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537771021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3537771021
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3846003661
Short name T1618
Test name
Test status
Simulation time 1073307011 ps
CPU time 2.5 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204764 kb
Host smart-0a3cd181-d4c7-43c0-8b01-fa1ae98dad7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846003661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3846003661
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.966925804
Short name T1631
Test name
Test status
Simulation time 726363727 ps
CPU time 2.15 seconds
Started Jul 11 06:08:25 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 204784 kb
Host smart-d5d15313-6763-49d9-8356-1a98ce21de4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966925804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.966925804
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.579296837
Short name T1627
Test name
Test status
Simulation time 28062870 ps
CPU time 0.77 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204576 kb
Host smart-35e907dd-5541-4d11-ab44-aa30f2e41f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579296837 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.579296837
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.328364619
Short name T216
Test name
Test status
Simulation time 51532346 ps
CPU time 0.7 seconds
Started Jul 11 06:08:23 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 204440 kb
Host smart-e5580cdb-3188-48c3-bcfd-0cf7dba24636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328364619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.328364619
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.4123123451
Short name T1661
Test name
Test status
Simulation time 19406129 ps
CPU time 0.72 seconds
Started Jul 11 06:08:25 PM PDT 24
Finished Jul 11 06:08:30 PM PDT 24
Peak memory 204432 kb
Host smart-46d93679-17ba-4739-8ccb-fa090acf802a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123123451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4123123451
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2584049857
Short name T1669
Test name
Test status
Simulation time 84139411 ps
CPU time 1.07 seconds
Started Jul 11 06:08:24 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204780 kb
Host smart-afa12036-cfda-42b4-8fec-57b27550e9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584049857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2584049857
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3926434309
Short name T1589
Test name
Test status
Simulation time 57351943 ps
CPU time 1.25 seconds
Started Jul 11 06:08:24 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204772 kb
Host smart-810f39b6-bd3d-4ba3-a80f-f4104e00735b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926434309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3926434309
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3806600030
Short name T200
Test name
Test status
Simulation time 73399551 ps
CPU time 1.47 seconds
Started Jul 11 06:08:27 PM PDT 24
Finished Jul 11 06:08:32 PM PDT 24
Peak memory 204692 kb
Host smart-c82fa961-de4a-4d50-8dc7-fef0186f9fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806600030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3806600030
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1434298778
Short name T96
Test name
Test status
Simulation time 81856031 ps
CPU time 0.78 seconds
Started Jul 11 06:08:30 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204580 kb
Host smart-63d1ba75-adf2-4df8-b6b5-48fde0361777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434298778 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1434298778
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2020552979
Short name T208
Test name
Test status
Simulation time 34243648 ps
CPU time 0.7 seconds
Started Jul 11 06:08:32 PM PDT 24
Finished Jul 11 06:08:35 PM PDT 24
Peak memory 204484 kb
Host smart-7d1b7a42-6c0f-4154-a437-7ee29516ffe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020552979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2020552979
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1461461702
Short name T1568
Test name
Test status
Simulation time 20172810 ps
CPU time 0.69 seconds
Started Jul 11 06:08:24 PM PDT 24
Finished Jul 11 06:08:29 PM PDT 24
Peak memory 204472 kb
Host smart-706c9d9b-6e7b-44e7-88ca-ac4eb5e0b556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461461702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1461461702
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2190877999
Short name T1610
Test name
Test status
Simulation time 220022684 ps
CPU time 1.22 seconds
Started Jul 11 06:08:30 PM PDT 24
Finished Jul 11 06:08:33 PM PDT 24
Peak memory 204788 kb
Host smart-c0a1b8b1-4781-4c93-b375-96c7b192552d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190877999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2190877999
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.600042063
Short name T1640
Test name
Test status
Simulation time 40571639 ps
CPU time 2.03 seconds
Started Jul 11 06:08:26 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 212892 kb
Host smart-8c7b0ced-74c4-4845-93ea-f790011bed47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600042063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.600042063
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.325664516
Short name T262
Test name
Test status
Simulation time 88178815 ps
CPU time 1.48 seconds
Started Jul 11 06:08:22 PM PDT 24
Finished Jul 11 06:08:27 PM PDT 24
Peak memory 204792 kb
Host smart-4f3c097e-1034-4308-8c7a-aacfbb3939e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325664516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.325664516
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1781633668
Short name T1333
Test name
Test status
Simulation time 44596505 ps
CPU time 0.63 seconds
Started Jul 11 07:21:13 PM PDT 24
Finished Jul 11 07:21:14 PM PDT 24
Peak memory 204712 kb
Host smart-d4278d7e-15fe-4ce7-978e-76ff83ba5c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781633668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1781633668
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1992977259
Short name T1328
Test name
Test status
Simulation time 181544780 ps
CPU time 1.33 seconds
Started Jul 11 07:20:41 PM PDT 24
Finished Jul 11 07:20:43 PM PDT 24
Peak memory 216268 kb
Host smart-460865bd-4fd1-485d-ae5a-4d03cb51fb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992977259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1992977259
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2654471840
Short name T1396
Test name
Test status
Simulation time 4532127648 ps
CPU time 12.68 seconds
Started Jul 11 07:20:23 PM PDT 24
Finished Jul 11 07:20:37 PM PDT 24
Peak memory 253900 kb
Host smart-105e802c-f405-40f2-8c50-fcb23597c5da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654471840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2654471840
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2864770463
Short name T542
Test name
Test status
Simulation time 6554587981 ps
CPU time 105.93 seconds
Started Jul 11 07:20:27 PM PDT 24
Finished Jul 11 07:22:14 PM PDT 24
Peak memory 563676 kb
Host smart-2ace6f4e-93dd-4b6a-ace5-af31627331d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864770463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2864770463
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.25402775
Short name T814
Test name
Test status
Simulation time 1612604456 ps
CPU time 99.72 seconds
Started Jul 11 07:20:23 PM PDT 24
Finished Jul 11 07:22:04 PM PDT 24
Peak memory 549232 kb
Host smart-99117afe-f804-40ec-853c-71bbe2f6ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25402775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.25402775
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.526481809
Short name T1392
Test name
Test status
Simulation time 68350709 ps
CPU time 0.91 seconds
Started Jul 11 07:20:29 PM PDT 24
Finished Jul 11 07:20:31 PM PDT 24
Peak memory 205128 kb
Host smart-7f44b388-f6e2-43ad-8613-012bb38b2e00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526481809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.526481809
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3121636999
Short name T854
Test name
Test status
Simulation time 155360096 ps
CPU time 3.16 seconds
Started Jul 11 07:20:25 PM PDT 24
Finished Jul 11 07:20:30 PM PDT 24
Peak memory 205296 kb
Host smart-27acb140-29b4-454d-ae16-72c996696d81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121636999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3121636999
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2115646077
Short name T1423
Test name
Test status
Simulation time 5408298728 ps
CPU time 132.34 seconds
Started Jul 11 07:20:24 PM PDT 24
Finished Jul 11 07:22:38 PM PDT 24
Peak memory 1364560 kb
Host smart-b46c8ae6-082d-437c-8af2-525b86a309de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115646077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2115646077
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.3886825722
Short name T552
Test name
Test status
Simulation time 93164557 ps
CPU time 0.68 seconds
Started Jul 11 07:20:26 PM PDT 24
Finished Jul 11 07:20:28 PM PDT 24
Peak memory 205132 kb
Host smart-c7c1af62-4b23-46b3-ac9d-a917a4a71fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886825722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3886825722
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.4095148190
Short name T1522
Test name
Test status
Simulation time 2830885447 ps
CPU time 9.54 seconds
Started Jul 11 07:20:30 PM PDT 24
Finished Jul 11 07:20:41 PM PDT 24
Peak memory 227504 kb
Host smart-fd5630e2-9f5d-46b2-b815-59542820298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095148190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.4095148190
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.2671502796
Short name T830
Test name
Test status
Simulation time 200526905 ps
CPU time 3.22 seconds
Started Jul 11 07:20:37 PM PDT 24
Finished Jul 11 07:20:41 PM PDT 24
Peak memory 227292 kb
Host smart-4b91246a-e43f-438c-a9c1-9d22d3622a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671502796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2671502796
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1627217397
Short name T1132
Test name
Test status
Simulation time 1993838021 ps
CPU time 97.32 seconds
Started Jul 11 07:20:14 PM PDT 24
Finished Jul 11 07:21:53 PM PDT 24
Peak memory 327288 kb
Host smart-ad20c16f-de91-4191-b6c0-84b1ad5dfae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627217397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1627217397
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1495984458
Short name T376
Test name
Test status
Simulation time 1085988214 ps
CPU time 40.94 seconds
Started Jul 11 07:20:36 PM PDT 24
Finished Jul 11 07:21:18 PM PDT 24
Peak memory 213584 kb
Host smart-752cb1e3-be80-4d42-be5d-db21f2d4e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495984458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1495984458
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.972463675
Short name T1119
Test name
Test status
Simulation time 2335648943 ps
CPU time 4.12 seconds
Started Jul 11 07:20:57 PM PDT 24
Finished Jul 11 07:21:02 PM PDT 24
Peak memory 213916 kb
Host smart-3d8a1aca-366c-435b-8d6c-cd64702f14a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972463675 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.972463675
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.532696487
Short name T728
Test name
Test status
Simulation time 696718478 ps
CPU time 1.63 seconds
Started Jul 11 07:20:52 PM PDT 24
Finished Jul 11 07:20:54 PM PDT 24
Peak memory 205544 kb
Host smart-921fa476-f717-42e1-8666-14255fddb7e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532696487 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_acq.532696487
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2180507847
Short name T436
Test name
Test status
Simulation time 333189786 ps
CPU time 0.8 seconds
Started Jul 11 07:20:55 PM PDT 24
Finished Jul 11 07:20:56 PM PDT 24
Peak memory 205324 kb
Host smart-2cd6b649-8d91-4a6e-bcff-a2d7402a215b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180507847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2180507847
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.483334418
Short name T771
Test name
Test status
Simulation time 1369854718 ps
CPU time 2.25 seconds
Started Jul 11 07:21:07 PM PDT 24
Finished Jul 11 07:21:10 PM PDT 24
Peak memory 205336 kb
Host smart-a27c965c-aebb-4fb8-8f0c-0697e56915d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483334418 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.483334418
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.2009091347
Short name T386
Test name
Test status
Simulation time 473776723 ps
CPU time 1.2 seconds
Started Jul 11 07:21:02 PM PDT 24
Finished Jul 11 07:21:04 PM PDT 24
Peak memory 205388 kb
Host smart-67fee498-1550-45e8-a9db-8bb6e9c16d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009091347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2009091347
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2493744677
Short name T45
Test name
Test status
Simulation time 1904664270 ps
CPU time 9.56 seconds
Started Jul 11 07:20:44 PM PDT 24
Finished Jul 11 07:20:54 PM PDT 24
Peak memory 214012 kb
Host smart-2db2772e-1fe3-4c6f-b3bc-af322897dfcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493744677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2493744677
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1864572656
Short name T1467
Test name
Test status
Simulation time 2821128866 ps
CPU time 5.88 seconds
Started Jul 11 07:20:49 PM PDT 24
Finished Jul 11 07:20:56 PM PDT 24
Peak memory 221992 kb
Host smart-da2695b5-773b-4e92-87dd-a02462ea65b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864572656 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1864572656
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1237747188
Short name T89
Test name
Test status
Simulation time 11919224202 ps
CPU time 73.93 seconds
Started Jul 11 07:20:48 PM PDT 24
Finished Jul 11 07:22:03 PM PDT 24
Peak memory 1234700 kb
Host smart-814b9033-0cb3-4f16-999b-1fdac4954144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237747188 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1237747188
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.4230153530
Short name T1398
Test name
Test status
Simulation time 3102652190 ps
CPU time 3.01 seconds
Started Jul 11 07:21:09 PM PDT 24
Finished Jul 11 07:21:13 PM PDT 24
Peak memory 213836 kb
Host smart-c24b4ed1-542b-421b-ba7b-b33651900c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230153530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.4230153530
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.204751969
Short name T1012
Test name
Test status
Simulation time 528623955 ps
CPU time 2.86 seconds
Started Jul 11 07:21:08 PM PDT 24
Finished Jul 11 07:21:12 PM PDT 24
Peak memory 205520 kb
Host smart-01b9c131-42c5-42a6-a30b-969e09615dda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204751969 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.204751969
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.1884064875
Short name T961
Test name
Test status
Simulation time 365080636 ps
CPU time 2.09 seconds
Started Jul 11 07:21:04 PM PDT 24
Finished Jul 11 07:21:07 PM PDT 24
Peak memory 205344 kb
Host smart-151ed6b8-75c5-4c62-93d2-61a355062a94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884064875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_smbus_maxlen.1884064875
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.250183314
Short name T677
Test name
Test status
Simulation time 2964835990 ps
CPU time 8.82 seconds
Started Jul 11 07:20:48 PM PDT 24
Finished Jul 11 07:20:58 PM PDT 24
Peak memory 215608 kb
Host smart-7828d26f-eb94-4109-9a33-2edb381ac712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250183314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.250183314
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.533693837
Short name T603
Test name
Test status
Simulation time 1126934177 ps
CPU time 10.37 seconds
Started Jul 11 07:20:45 PM PDT 24
Finished Jul 11 07:20:56 PM PDT 24
Peak memory 217704 kb
Host smart-bb9027e8-b80d-46f3-bc65-903ccf82f422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533693837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.533693837
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1879094742
Short name T1063
Test name
Test status
Simulation time 39934515975 ps
CPU time 232.79 seconds
Started Jul 11 07:20:48 PM PDT 24
Finished Jul 11 07:24:42 PM PDT 24
Peak memory 2927516 kb
Host smart-a4a962e5-afb7-4f17-b888-c4b8820d5192
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879094742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1879094742
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2208966794
Short name T1530
Test name
Test status
Simulation time 5665452487 ps
CPU time 37.37 seconds
Started Jul 11 07:20:45 PM PDT 24
Finished Jul 11 07:21:23 PM PDT 24
Peak memory 601704 kb
Host smart-61f1ae78-3e53-4e2a-a942-4d3e2e6fcd0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208966794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2208966794
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2622958412
Short name T1096
Test name
Test status
Simulation time 1075522898 ps
CPU time 6.26 seconds
Started Jul 11 07:20:49 PM PDT 24
Finished Jul 11 07:20:56 PM PDT 24
Peak memory 217180 kb
Host smart-46932f4e-613f-472e-a57d-5af95e489047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622958412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2622958412
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.1634596097
Short name T50
Test name
Test status
Simulation time 136712256 ps
CPU time 2.82 seconds
Started Jul 11 07:21:04 PM PDT 24
Finished Jul 11 07:21:08 PM PDT 24
Peak memory 205476 kb
Host smart-2d347296-3811-4fb2-a360-3b5d360546d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634596097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.1634596097
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.376211921
Short name T1416
Test name
Test status
Simulation time 17177281 ps
CPU time 0.63 seconds
Started Jul 11 07:22:00 PM PDT 24
Finished Jul 11 07:22:01 PM PDT 24
Peak memory 204660 kb
Host smart-ba8b6863-3df2-46c0-86b0-181b0252e96a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376211921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.376211921
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.461111469
Short name T1158
Test name
Test status
Simulation time 723395002 ps
CPU time 2.53 seconds
Started Jul 11 07:21:31 PM PDT 24
Finished Jul 11 07:21:34 PM PDT 24
Peak memory 213676 kb
Host smart-37f49829-9446-4707-8a8b-afc4f200fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461111469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.461111469
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1516386522
Short name T518
Test name
Test status
Simulation time 6077473224 ps
CPU time 12.54 seconds
Started Jul 11 07:21:27 PM PDT 24
Finished Jul 11 07:21:40 PM PDT 24
Peak memory 329052 kb
Host smart-4a650690-4d44-4935-9a9a-db9bb9e5df87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516386522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1516386522
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2321815820
Short name T1110
Test name
Test status
Simulation time 11776106410 ps
CPU time 97.81 seconds
Started Jul 11 07:21:33 PM PDT 24
Finished Jul 11 07:23:11 PM PDT 24
Peak memory 763644 kb
Host smart-8e106308-5d2b-41d9-9be6-ed1dd33c36fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321815820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2321815820
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.4097543481
Short name T121
Test name
Test status
Simulation time 9647972034 ps
CPU time 62.08 seconds
Started Jul 11 07:21:17 PM PDT 24
Finished Jul 11 07:22:20 PM PDT 24
Peak memory 605268 kb
Host smart-3f597a3c-dc7d-4749-9406-5ca2ab49ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097543481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.4097543481
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2011318719
Short name T1126
Test name
Test status
Simulation time 110627210 ps
CPU time 1.14 seconds
Started Jul 11 07:21:22 PM PDT 24
Finished Jul 11 07:21:24 PM PDT 24
Peak memory 205128 kb
Host smart-b543b04d-3bfc-4bb6-94b7-c3cf1d0ebf17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011318719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2011318719
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.399091083
Short name T521
Test name
Test status
Simulation time 205506210 ps
CPU time 5.86 seconds
Started Jul 11 07:21:27 PM PDT 24
Finished Jul 11 07:21:33 PM PDT 24
Peak memory 241996 kb
Host smart-118d7150-6968-41cc-8cec-a39931a151e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399091083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.399091083
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3197506230
Short name T1379
Test name
Test status
Simulation time 3041926861 ps
CPU time 198.14 seconds
Started Jul 11 07:21:24 PM PDT 24
Finished Jul 11 07:24:43 PM PDT 24
Peak memory 923776 kb
Host smart-8aa05022-e86e-42ee-b018-43f7d06894eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197506230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3197506230
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1261391046
Short name T1443
Test name
Test status
Simulation time 282795085 ps
CPU time 11.98 seconds
Started Jul 11 07:21:53 PM PDT 24
Finished Jul 11 07:22:06 PM PDT 24
Peak memory 205336 kb
Host smart-f5ca4da3-3ce5-4024-8074-3ebe635c2fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261391046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1261391046
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.1897477374
Short name T1339
Test name
Test status
Simulation time 113421501 ps
CPU time 0.66 seconds
Started Jul 11 07:21:19 PM PDT 24
Finished Jul 11 07:21:20 PM PDT 24
Peak memory 205156 kb
Host smart-3191c7da-1409-43e3-9967-e912379dc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897477374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1897477374
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1300019454
Short name T647
Test name
Test status
Simulation time 2748322449 ps
CPU time 68.35 seconds
Started Jul 11 07:21:31 PM PDT 24
Finished Jul 11 07:22:40 PM PDT 24
Peak memory 853332 kb
Host smart-5e296e09-2e0f-4328-8886-52f8603a41f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300019454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1300019454
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.3126485653
Short name T389
Test name
Test status
Simulation time 228663833 ps
CPU time 1.34 seconds
Started Jul 11 07:21:33 PM PDT 24
Finished Jul 11 07:21:35 PM PDT 24
Peak memory 205192 kb
Host smart-680bcf77-f763-4856-a905-a31b20347339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126485653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3126485653
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1058205104
Short name T600
Test name
Test status
Simulation time 1155219877 ps
CPU time 39.25 seconds
Started Jul 11 07:21:18 PM PDT 24
Finished Jul 11 07:21:58 PM PDT 24
Peak memory 262076 kb
Host smart-2d1e1c0b-3c75-4523-9443-cc45288e7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058205104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1058205104
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1425653661
Short name T183
Test name
Test status
Simulation time 122800924 ps
CPU time 0.93 seconds
Started Jul 11 07:22:00 PM PDT 24
Finished Jul 11 07:22:02 PM PDT 24
Peak memory 223640 kb
Host smart-9ab1924d-1628-480a-9b60-14cb75fbe659
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425653661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1425653661
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1860361888
Short name T735
Test name
Test status
Simulation time 1330746328 ps
CPU time 7.27 seconds
Started Jul 11 07:21:46 PM PDT 24
Finished Jul 11 07:21:54 PM PDT 24
Peak memory 219684 kb
Host smart-3aa46700-2432-4538-a3f7-f4d8c906fc89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860361888 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1860361888
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1134091139
Short name T563
Test name
Test status
Simulation time 261089472 ps
CPU time 1.74 seconds
Started Jul 11 07:21:47 PM PDT 24
Finished Jul 11 07:21:50 PM PDT 24
Peak memory 205528 kb
Host smart-092beda1-479f-4fd3-b6d1-85416accef3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134091139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1134091139
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1998369126
Short name T1358
Test name
Test status
Simulation time 211208311 ps
CPU time 0.98 seconds
Started Jul 11 07:21:48 PM PDT 24
Finished Jul 11 07:21:50 PM PDT 24
Peak memory 205424 kb
Host smart-5a1c5f30-8ef3-450c-b091-718acb51931f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998369126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1998369126
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.2729421014
Short name T596
Test name
Test status
Simulation time 10505875897 ps
CPU time 2.92 seconds
Started Jul 11 07:21:51 PM PDT 24
Finished Jul 11 07:21:55 PM PDT 24
Peak memory 205588 kb
Host smart-576f9d6b-db1f-48c9-b570-d09ac8e5cee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729421014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.2729421014
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2532960060
Short name T598
Test name
Test status
Simulation time 547082065 ps
CPU time 1.4 seconds
Started Jul 11 07:21:51 PM PDT 24
Finished Jul 11 07:21:53 PM PDT 24
Peak memory 205360 kb
Host smart-d514de75-4bd3-4837-8026-52c044c68174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532960060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2532960060
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2815630875
Short name T1070
Test name
Test status
Simulation time 14332976291 ps
CPU time 6.64 seconds
Started Jul 11 07:21:40 PM PDT 24
Finished Jul 11 07:21:48 PM PDT 24
Peak memory 221928 kb
Host smart-2724c313-e817-4919-b640-bfd8b827a8ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815630875 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2815630875
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.626646213
Short name T371
Test name
Test status
Simulation time 9191437960 ps
CPU time 18.7 seconds
Started Jul 11 07:21:41 PM PDT 24
Finished Jul 11 07:22:01 PM PDT 24
Peak memory 630008 kb
Host smart-c12ace6f-5803-43b8-914f-1b9b033d43e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626646213 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.626646213
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.1154016774
Short name T1275
Test name
Test status
Simulation time 1384331512 ps
CPU time 2.74 seconds
Started Jul 11 07:21:59 PM PDT 24
Finished Jul 11 07:22:02 PM PDT 24
Peak memory 213632 kb
Host smart-0b0e2400-67c8-4435-9284-0be3a34a0502
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154016774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.1154016774
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.1871599440
Short name T801
Test name
Test status
Simulation time 590785875 ps
CPU time 2.79 seconds
Started Jul 11 07:22:01 PM PDT 24
Finished Jul 11 07:22:05 PM PDT 24
Peak memory 205488 kb
Host smart-b98d2b02-465c-4658-a84d-d9271d9b6621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871599440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1871599440
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.2258386195
Short name T347
Test name
Test status
Simulation time 1119330150 ps
CPU time 2.6 seconds
Started Jul 11 07:21:53 PM PDT 24
Finished Jul 11 07:21:56 PM PDT 24
Peak memory 205352 kb
Host smart-a8209664-5ebe-4e3a-b1e6-e9081ca0959c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258386195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.2258386195
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2189142466
Short name T488
Test name
Test status
Simulation time 3490462707 ps
CPU time 17.11 seconds
Started Jul 11 07:21:41 PM PDT 24
Finished Jul 11 07:21:59 PM PDT 24
Peak memory 221816 kb
Host smart-7f703930-ce11-4340-af6b-c41e30b7a9fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189142466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2189142466
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2755618216
Short name T461
Test name
Test status
Simulation time 31512685232 ps
CPU time 95.6 seconds
Started Jul 11 07:21:34 PM PDT 24
Finished Jul 11 07:23:10 PM PDT 24
Peak memory 1537548 kb
Host smart-522a07bc-1275-4660-8a58-b0b590001834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755618216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2755618216
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3292555920
Short name T1200
Test name
Test status
Simulation time 872666761 ps
CPU time 31.01 seconds
Started Jul 11 07:21:37 PM PDT 24
Finished Jul 11 07:22:09 PM PDT 24
Peak memory 329844 kb
Host smart-e6b1d058-c8e0-404c-963e-7f9423101fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292555920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3292555920
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.655183016
Short name T1014
Test name
Test status
Simulation time 15462249775 ps
CPU time 7.06 seconds
Started Jul 11 07:21:42 PM PDT 24
Finished Jul 11 07:21:50 PM PDT 24
Peak memory 221884 kb
Host smart-01d17212-86ad-4e17-9fdc-4f5858e076c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655183016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.655183016
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.3042190089
Short name T334
Test name
Test status
Simulation time 176807125 ps
CPU time 3.05 seconds
Started Jul 11 07:21:50 PM PDT 24
Finished Jul 11 07:21:54 PM PDT 24
Peak memory 205564 kb
Host smart-60ddd56f-5efe-4798-b8b6-5723a8e05db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042190089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.3042190089
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3181488494
Short name T1362
Test name
Test status
Simulation time 103575325 ps
CPU time 1.38 seconds
Started Jul 11 07:25:29 PM PDT 24
Finished Jul 11 07:25:32 PM PDT 24
Peak memory 213624 kb
Host smart-21adc100-c30d-49da-add0-cd24d9facddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181488494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3181488494
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.694494721
Short name T805
Test name
Test status
Simulation time 1361874734 ps
CPU time 18.36 seconds
Started Jul 11 07:25:19 PM PDT 24
Finished Jul 11 07:25:39 PM PDT 24
Peak memory 281692 kb
Host smart-0709c14d-14bf-47cb-997b-f70cf2d39614
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694494721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.694494721
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.4154622175
Short name T1510
Test name
Test status
Simulation time 4282319861 ps
CPU time 113.96 seconds
Started Jul 11 07:25:29 PM PDT 24
Finished Jul 11 07:27:24 PM PDT 24
Peak memory 860032 kb
Host smart-4a8b9f10-5391-4b69-a8be-628c3bec367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154622175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.4154622175
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3133900945
Short name T1198
Test name
Test status
Simulation time 5900208764 ps
CPU time 81.08 seconds
Started Jul 11 07:25:22 PM PDT 24
Finished Jul 11 07:26:45 PM PDT 24
Peak memory 472224 kb
Host smart-eb290ed4-3379-487b-92cc-dff189728b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133900945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3133900945
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.646144091
Short name T469
Test name
Test status
Simulation time 161091837 ps
CPU time 1.35 seconds
Started Jul 11 07:25:20 PM PDT 24
Finished Jul 11 07:25:23 PM PDT 24
Peak memory 205268 kb
Host smart-8b1253d1-9ad6-4eb7-9f01-8cb38ce31d0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646144091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.646144091
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.956332818
Short name T959
Test name
Test status
Simulation time 119744745 ps
CPU time 3.1 seconds
Started Jul 11 07:25:25 PM PDT 24
Finished Jul 11 07:25:29 PM PDT 24
Peak memory 205352 kb
Host smart-3206467e-8ed2-4302-9cb6-df41dcf02e20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956332818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
956332818
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2375272674
Short name T1525
Test name
Test status
Simulation time 8326015074 ps
CPU time 92.63 seconds
Started Jul 11 07:25:26 PM PDT 24
Finished Jul 11 07:26:59 PM PDT 24
Peak memory 1094348 kb
Host smart-8f9337a1-0840-49df-af03-0001f327f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375272674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2375272674
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.3003929766
Short name T1128
Test name
Test status
Simulation time 1190158842 ps
CPU time 11.58 seconds
Started Jul 11 07:25:39 PM PDT 24
Finished Jul 11 07:25:52 PM PDT 24
Peak memory 205356 kb
Host smart-5504e805-d561-4e6e-8f26-e33ff42b239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003929766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3003929766
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.4254059947
Short name T1473
Test name
Test status
Simulation time 23946829 ps
CPU time 0.65 seconds
Started Jul 11 07:25:20 PM PDT 24
Finished Jul 11 07:25:22 PM PDT 24
Peak memory 205108 kb
Host smart-6df33d54-a089-4f83-9df7-8b55add444c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254059947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.4254059947
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4064545456
Short name T895
Test name
Test status
Simulation time 6706355523 ps
CPU time 296.58 seconds
Started Jul 11 07:25:27 PM PDT 24
Finished Jul 11 07:30:24 PM PDT 24
Peak memory 1110836 kb
Host smart-bcf22f28-0bf8-47d7-8913-8262172bd006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064545456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4064545456
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1981340312
Short name T1465
Test name
Test status
Simulation time 40746842 ps
CPU time 1.36 seconds
Started Jul 11 07:25:28 PM PDT 24
Finished Jul 11 07:25:30 PM PDT 24
Peak memory 227536 kb
Host smart-58c6bbdf-f00f-4640-88d6-50d27ade74b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981340312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1981340312
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.680191037
Short name T239
Test name
Test status
Simulation time 3771507514 ps
CPU time 35.53 seconds
Started Jul 11 07:25:26 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 334784 kb
Host smart-8691be9e-9b2f-4812-b22a-0d4bf81afe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680191037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.680191037
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1746126009
Short name T37
Test name
Test status
Simulation time 25257542951 ps
CPU time 1412.23 seconds
Started Jul 11 07:25:28 PM PDT 24
Finished Jul 11 07:49:02 PM PDT 24
Peak memory 2334152 kb
Host smart-335c058f-ceba-45ef-8be8-fc4dcb9aa097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746126009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1746126009
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2175713090
Short name T381
Test name
Test status
Simulation time 686086814 ps
CPU time 30.31 seconds
Started Jul 11 07:25:30 PM PDT 24
Finished Jul 11 07:26:01 PM PDT 24
Peak memory 213652 kb
Host smart-9ba430aa-1703-4fcd-9226-3b5a5d4a31c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175713090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2175713090
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1107641317
Short name T879
Test name
Test status
Simulation time 2150337061 ps
CPU time 5.92 seconds
Started Jul 11 07:25:41 PM PDT 24
Finished Jul 11 07:25:49 PM PDT 24
Peak memory 210136 kb
Host smart-eee15a78-0281-4ea9-817f-1e5b700e5a0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107641317 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1107641317
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2348380861
Short name T472
Test name
Test status
Simulation time 190244725 ps
CPU time 0.95 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:25:41 PM PDT 24
Peak memory 205392 kb
Host smart-a8e291df-f3b5-47e0-8a72-40e7b3b6f4d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348380861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2348380861
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.448472251
Short name T1450
Test name
Test status
Simulation time 326547457 ps
CPU time 1.93 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:25:42 PM PDT 24
Peak memory 216860 kb
Host smart-0a1267b1-947b-47c3-a5fb-f6ff829dc0c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448472251 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.448472251
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.669046422
Short name T1153
Test name
Test status
Simulation time 225765357 ps
CPU time 1.47 seconds
Started Jul 11 07:25:42 PM PDT 24
Finished Jul 11 07:25:45 PM PDT 24
Peak memory 205332 kb
Host smart-4421793f-9604-4a75-9f2d-c1cc91cd9350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669046422 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.669046422
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.525250127
Short name T1137
Test name
Test status
Simulation time 403154690 ps
CPU time 1.05 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:25:42 PM PDT 24
Peak memory 205412 kb
Host smart-66ec5a2d-a7ae-41d8-bfb5-a8795eb60569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525250127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.525250127
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1426884977
Short name T721
Test name
Test status
Simulation time 2616537171 ps
CPU time 4.13 seconds
Started Jul 11 07:25:28 PM PDT 24
Finished Jul 11 07:25:33 PM PDT 24
Peak memory 218392 kb
Host smart-a5c2fdfa-88fd-4214-8b15-e70103cbba49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426884977 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1426884977
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1753646813
Short name T301
Test name
Test status
Simulation time 5529043038 ps
CPU time 9.81 seconds
Started Jul 11 07:25:29 PM PDT 24
Finished Jul 11 07:25:40 PM PDT 24
Peak memory 472196 kb
Host smart-fbde894c-4741-43f2-8d31-e3707cf6ccfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753646813 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1753646813
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.4240081852
Short name T695
Test name
Test status
Simulation time 1126663498 ps
CPU time 2.95 seconds
Started Jul 11 07:25:37 PM PDT 24
Finished Jul 11 07:25:42 PM PDT 24
Peak memory 213584 kb
Host smart-7fb674ce-764e-4550-83e1-1e76e908f2ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240081852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.4240081852
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.1706494349
Short name T779
Test name
Test status
Simulation time 2117379312 ps
CPU time 2.84 seconds
Started Jul 11 07:25:43 PM PDT 24
Finished Jul 11 07:25:47 PM PDT 24
Peak memory 205500 kb
Host smart-fe59a521-b625-4a97-8d5d-472a515d006e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706494349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.1706494349
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2833515497
Short name T1378
Test name
Test status
Simulation time 3285778105 ps
CPU time 2.62 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:25:43 PM PDT 24
Peak memory 205472 kb
Host smart-b5560e61-1b76-41cc-a0b2-9938c6f43240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833515497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2833515497
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.272406536
Short name T1226
Test name
Test status
Simulation time 2303926019 ps
CPU time 14.77 seconds
Started Jul 11 07:25:28 PM PDT 24
Finished Jul 11 07:25:44 PM PDT 24
Peak memory 213708 kb
Host smart-6bd0179e-46f9-4551-b2ff-9120acba0a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272406536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.272406536
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2522134977
Short name T1236
Test name
Test status
Simulation time 46687413388 ps
CPU time 967.83 seconds
Started Jul 11 07:25:30 PM PDT 24
Finished Jul 11 07:41:39 PM PDT 24
Peak memory 6563756 kb
Host smart-c12fb423-0f25-49c4-a088-641910034afc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522134977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2522134977
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2209065595
Short name T722
Test name
Test status
Simulation time 3567424407 ps
CPU time 7.44 seconds
Started Jul 11 07:25:29 PM PDT 24
Finished Jul 11 07:25:37 PM PDT 24
Peak memory 221764 kb
Host smart-5af8bfcf-9099-4460-ad9b-8d670c8e3750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209065595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2209065595
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3347667606
Short name T714
Test name
Test status
Simulation time 2348341495 ps
CPU time 6.9 seconds
Started Jul 11 07:25:29 PM PDT 24
Finished Jul 11 07:25:37 PM PDT 24
Peak memory 221900 kb
Host smart-c0a7b987-beea-4026-abf0-9e0a24e53c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347667606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3347667606
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.764930310
Short name T448
Test name
Test status
Simulation time 89374373 ps
CPU time 2.08 seconds
Started Jul 11 07:25:35 PM PDT 24
Finished Jul 11 07:25:38 PM PDT 24
Peak memory 205488 kb
Host smart-cfa630da-12ee-4668-98a3-0c0a40de0a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764930310 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.764930310
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1786961118
Short name T440
Test name
Test status
Simulation time 45700314 ps
CPU time 0.65 seconds
Started Jul 11 07:25:56 PM PDT 24
Finished Jul 11 07:25:59 PM PDT 24
Peak memory 204820 kb
Host smart-c4b2dc4f-4836-49ea-9e55-a7148bd8eb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786961118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1786961118
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2242546809
Short name T1088
Test name
Test status
Simulation time 507635179 ps
CPU time 1.48 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:25:49 PM PDT 24
Peak memory 213628 kb
Host smart-53ae3136-b626-4ce9-9f92-1962e81b2c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242546809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2242546809
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3522357452
Short name T909
Test name
Test status
Simulation time 815423172 ps
CPU time 20.96 seconds
Started Jul 11 07:25:39 PM PDT 24
Finished Jul 11 07:26:03 PM PDT 24
Peak memory 278348 kb
Host smart-ac15deab-7932-4bdf-a92b-369e5463ea77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522357452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3522357452
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.680887228
Short name T1415
Test name
Test status
Simulation time 4677187120 ps
CPU time 66.36 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:26:53 PM PDT 24
Peak memory 705524 kb
Host smart-5d0e22a9-2bf2-44b9-987a-f028de495f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680887228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.680887228
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2957831337
Short name T419
Test name
Test status
Simulation time 2221779966 ps
CPU time 174.45 seconds
Started Jul 11 07:25:42 PM PDT 24
Finished Jul 11 07:28:38 PM PDT 24
Peak memory 757124 kb
Host smart-8a77cde9-3de9-4f90-8f45-51e6a8c84c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957831337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2957831337
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1708994989
Short name T1046
Test name
Test status
Simulation time 336194340 ps
CPU time 0.93 seconds
Started Jul 11 07:25:39 PM PDT 24
Finished Jul 11 07:25:42 PM PDT 24
Peak memory 205144 kb
Host smart-e2f252c7-33ce-40fc-8f0e-c7fc6b2ee84c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708994989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1708994989
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1036236019
Short name T153
Test name
Test status
Simulation time 1868912548 ps
CPU time 11.36 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:25:58 PM PDT 24
Peak memory 205380 kb
Host smart-3fee6801-3b09-4c89-a219-990b0525fba8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036236019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1036236019
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3253403972
Short name T1552
Test name
Test status
Simulation time 8249689592 ps
CPU time 133.74 seconds
Started Jul 11 07:25:39 PM PDT 24
Finished Jul 11 07:27:55 PM PDT 24
Peak memory 1492212 kb
Host smart-3e50bd4a-2591-4149-94cb-ba53fb06d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253403972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3253403972
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2504424737
Short name T1225
Test name
Test status
Simulation time 444736834 ps
CPU time 17.28 seconds
Started Jul 11 07:25:52 PM PDT 24
Finished Jul 11 07:26:12 PM PDT 24
Peak memory 205444 kb
Host smart-962003c8-6d34-4447-9692-0a75a6bb8ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504424737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2504424737
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.194857246
Short name T1527
Test name
Test status
Simulation time 28707881 ps
CPU time 0.68 seconds
Started Jul 11 07:25:37 PM PDT 24
Finished Jul 11 07:25:40 PM PDT 24
Peak memory 205144 kb
Host smart-c442c580-ffe3-480f-9f28-b6b0b6c2981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194857246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.194857246
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1423139842
Short name T514
Test name
Test status
Simulation time 26140324937 ps
CPU time 238.48 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:29:46 PM PDT 24
Peak memory 223800 kb
Host smart-d142b78b-48f2-456e-83db-f8407b5b901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423139842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1423139842
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.3911365899
Short name T725
Test name
Test status
Simulation time 24313661655 ps
CPU time 314.84 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:31:02 PM PDT 24
Peak memory 205280 kb
Host smart-5e23fd92-2c7b-4d3a-9fbd-d9a7f5cedc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911365899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3911365899
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1512870652
Short name T995
Test name
Test status
Simulation time 1252226518 ps
CPU time 24.64 seconds
Started Jul 11 07:25:38 PM PDT 24
Finished Jul 11 07:26:05 PM PDT 24
Peak memory 357928 kb
Host smart-5c6c76bd-9d94-4cd7-87ee-8d9309bc51c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512870652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1512870652
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1544777165
Short name T1162
Test name
Test status
Simulation time 3616441751 ps
CPU time 17.79 seconds
Started Jul 11 07:25:47 PM PDT 24
Finished Jul 11 07:26:06 PM PDT 24
Peak memory 218292 kb
Host smart-269cf092-69a7-4203-9faa-aa1ec04bc8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544777165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1544777165
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1003126312
Short name T594
Test name
Test status
Simulation time 2307042999 ps
CPU time 6.28 seconds
Started Jul 11 07:25:52 PM PDT 24
Finished Jul 11 07:26:01 PM PDT 24
Peak memory 213816 kb
Host smart-b45be64c-30ca-4970-804f-909014862369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003126312 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1003126312
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3704200592
Short name T1004
Test name
Test status
Simulation time 1041351751 ps
CPU time 1.17 seconds
Started Jul 11 07:25:50 PM PDT 24
Finished Jul 11 07:25:52 PM PDT 24
Peak memory 205396 kb
Host smart-e87139c4-741a-4bfd-9eea-0382a81d2072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704200592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3704200592
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.418574197
Short name T1504
Test name
Test status
Simulation time 165574552 ps
CPU time 1.15 seconds
Started Jul 11 07:25:51 PM PDT 24
Finished Jul 11 07:25:53 PM PDT 24
Peak memory 205388 kb
Host smart-a995e097-5512-4fb4-b225-d2e660410932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418574197 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.418574197
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.2711271794
Short name T1029
Test name
Test status
Simulation time 1948039902 ps
CPU time 2.38 seconds
Started Jul 11 07:25:51 PM PDT 24
Finished Jul 11 07:25:54 PM PDT 24
Peak memory 205488 kb
Host smart-2d97affd-dd4b-4742-bf87-0f8f1b237199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711271794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2711271794
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.3185917174
Short name T587
Test name
Test status
Simulation time 320874444 ps
CPU time 1.46 seconds
Started Jul 11 07:25:54 PM PDT 24
Finished Jul 11 07:25:57 PM PDT 24
Peak memory 205348 kb
Host smart-4ace3f9a-998e-4750-85a1-800092fdf988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185917174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3185917174
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3731698068
Short name T653
Test name
Test status
Simulation time 4138813204 ps
CPU time 5.26 seconds
Started Jul 11 07:25:46 PM PDT 24
Finished Jul 11 07:25:53 PM PDT 24
Peak memory 213740 kb
Host smart-a0d47cef-5ced-4dba-99ba-a30bce310481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731698068 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3731698068
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.725808349
Short name T1456
Test name
Test status
Simulation time 27229208221 ps
CPU time 94.9 seconds
Started Jul 11 07:25:50 PM PDT 24
Finished Jul 11 07:27:26 PM PDT 24
Peak memory 1648196 kb
Host smart-c06654fd-32c3-47d1-bbf0-96a1982a49e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725808349 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.725808349
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.2132607657
Short name T945
Test name
Test status
Simulation time 560817619 ps
CPU time 3.14 seconds
Started Jul 11 07:25:57 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 213624 kb
Host smart-b360e18d-abbb-4833-b572-2d59d1e8c2d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132607657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.2132607657
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.4021679194
Short name T1563
Test name
Test status
Simulation time 1750894849 ps
CPU time 2.45 seconds
Started Jul 11 07:25:58 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 205496 kb
Host smart-99e050ed-4a90-4a38-9ed0-c377b29b8ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021679194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.4021679194
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.2977744889
Short name T312
Test name
Test status
Simulation time 353712706 ps
CPU time 1.94 seconds
Started Jul 11 07:25:55 PM PDT 24
Finished Jul 11 07:25:59 PM PDT 24
Peak memory 205344 kb
Host smart-328f8861-1127-483a-b034-7a06db7b2b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977744889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.2977744889
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1070419186
Short name T1411
Test name
Test status
Simulation time 707010983 ps
CPU time 9.33 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:25:57 PM PDT 24
Peak memory 213720 kb
Host smart-fc85cf11-6e4e-49aa-a514-38ed33644286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070419186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1070419186
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1740614664
Short name T915
Test name
Test status
Simulation time 1071251329 ps
CPU time 9.85 seconds
Started Jul 11 07:25:47 PM PDT 24
Finished Jul 11 07:25:58 PM PDT 24
Peak memory 205524 kb
Host smart-f525a810-d94d-4e78-973e-241e111d60d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740614664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1740614664
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2941886576
Short name T1075
Test name
Test status
Simulation time 29193410617 ps
CPU time 183.74 seconds
Started Jul 11 07:25:45 PM PDT 24
Finished Jul 11 07:28:50 PM PDT 24
Peak memory 2329660 kb
Host smart-fd89c341-ae42-434a-80d5-f6c194fe2941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941886576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2941886576
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.677736836
Short name T486
Test name
Test status
Simulation time 3448625537 ps
CPU time 74.91 seconds
Started Jul 11 07:26:21 PM PDT 24
Finished Jul 11 07:27:37 PM PDT 24
Peak memory 1003140 kb
Host smart-f35e0da4-8571-472b-96ba-69763aa3b917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677736836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.677736836
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.737358380
Short name T1434
Test name
Test status
Simulation time 5738134306 ps
CPU time 7.24 seconds
Started Jul 11 07:25:51 PM PDT 24
Finished Jul 11 07:25:59 PM PDT 24
Peak memory 219852 kb
Host smart-bd393e71-1e9b-4a43-86b0-5554b21ebb1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737358380 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.737358380
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.1993696204
Short name T1289
Test name
Test status
Simulation time 206722878 ps
CPU time 2.92 seconds
Started Jul 11 07:25:51 PM PDT 24
Finished Jul 11 07:25:57 PM PDT 24
Peak memory 205472 kb
Host smart-209b99b9-3980-4377-ba58-b609c69f33b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993696204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.1993696204
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3183088878
Short name T332
Test name
Test status
Simulation time 65720239 ps
CPU time 0.66 seconds
Started Jul 11 07:26:20 PM PDT 24
Finished Jul 11 07:26:22 PM PDT 24
Peak memory 204716 kb
Host smart-11702285-1ff6-432e-ad2a-e32371fec2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183088878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3183088878
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.656910370
Short name T700
Test name
Test status
Simulation time 231644500 ps
CPU time 1.75 seconds
Started Jul 11 07:26:01 PM PDT 24
Finished Jul 11 07:26:05 PM PDT 24
Peak memory 213640 kb
Host smart-02e75994-c95d-4c29-a29f-c2ef45ea6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656910370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.656910370
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2295147725
Short name T573
Test name
Test status
Simulation time 1163247831 ps
CPU time 5.69 seconds
Started Jul 11 07:25:58 PM PDT 24
Finished Jul 11 07:26:06 PM PDT 24
Peak memory 268572 kb
Host smart-6669a0a9-111a-4d31-a12d-2d42a41e11d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295147725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2295147725
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.4273831979
Short name T1541
Test name
Test status
Simulation time 6299596264 ps
CPU time 110.05 seconds
Started Jul 11 07:26:06 PM PDT 24
Finished Jul 11 07:27:58 PM PDT 24
Peak memory 600120 kb
Host smart-c0abb28e-57ae-48f9-ab46-216043afb2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273831979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.4273831979
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1591858117
Short name T904
Test name
Test status
Simulation time 2158061958 ps
CPU time 73.64 seconds
Started Jul 11 07:25:57 PM PDT 24
Finished Jul 11 07:27:13 PM PDT 24
Peak memory 702152 kb
Host smart-3ef41d5f-ee8f-475a-81e7-e3ae24552ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591858117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1591858117
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3930275357
Short name T342
Test name
Test status
Simulation time 586372925 ps
CPU time 1.19 seconds
Started Jul 11 07:25:57 PM PDT 24
Finished Jul 11 07:26:01 PM PDT 24
Peak memory 205144 kb
Host smart-68daed43-db6a-42a2-a576-7bdc19f96fde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930275357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3930275357
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2018183674
Short name T592
Test name
Test status
Simulation time 321810273 ps
CPU time 10.37 seconds
Started Jul 11 07:26:02 PM PDT 24
Finished Jul 11 07:26:14 PM PDT 24
Peak memory 236972 kb
Host smart-f12a4f06-26f1-40bb-bce2-7fbc885802f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018183674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2018183674
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3369856239
Short name T111
Test name
Test status
Simulation time 5132864264 ps
CPU time 130.7 seconds
Started Jul 11 07:26:02 PM PDT 24
Finished Jul 11 07:28:15 PM PDT 24
Peak memory 1487868 kb
Host smart-457efadf-f71c-418c-9dce-969b104bf75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369856239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3369856239
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.471813142
Short name T245
Test name
Test status
Simulation time 471177083 ps
CPU time 5.74 seconds
Started Jul 11 07:26:12 PM PDT 24
Finished Jul 11 07:26:21 PM PDT 24
Peak memory 205360 kb
Host smart-1d21a506-7f20-4888-8c65-15c7d7e3161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471813142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.471813142
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.4019368692
Short name T1165
Test name
Test status
Simulation time 39620820 ps
CPU time 0.66 seconds
Started Jul 11 07:25:59 PM PDT 24
Finished Jul 11 07:26:01 PM PDT 24
Peak memory 205160 kb
Host smart-d0cd2413-453a-4d94-b49a-a21fe2546466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019368692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4019368692
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.22559729
Short name T650
Test name
Test status
Simulation time 832202885 ps
CPU time 12.09 seconds
Started Jul 11 07:26:02 PM PDT 24
Finished Jul 11 07:26:16 PM PDT 24
Peak memory 302132 kb
Host smart-143ad0b0-7f3b-4ae2-8fe7-08af5ffbc48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22559729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.22559729
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.3973702678
Short name T154
Test name
Test status
Simulation time 6355628367 ps
CPU time 24 seconds
Started Jul 11 07:26:04 PM PDT 24
Finished Jul 11 07:26:30 PM PDT 24
Peak memory 205228 kb
Host smart-5f5abeb5-ef87-4122-9c27-e77995e314a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973702678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.3973702678
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.250801379
Short name T888
Test name
Test status
Simulation time 35538414073 ps
CPU time 85.96 seconds
Started Jul 11 07:26:01 PM PDT 24
Finished Jul 11 07:27:29 PM PDT 24
Peak memory 359744 kb
Host smart-28559994-9c67-43cc-a0cd-7cc8aaf0a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250801379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.250801379
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2104856753
Short name T1240
Test name
Test status
Simulation time 1729218196 ps
CPU time 14.89 seconds
Started Jul 11 07:26:04 PM PDT 24
Finished Jul 11 07:26:21 PM PDT 24
Peak memory 229912 kb
Host smart-0c44c319-3c7d-43ff-b79e-312fc0951267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104856753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2104856753
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1349017728
Short name T502
Test name
Test status
Simulation time 4553440213 ps
CPU time 5.28 seconds
Started Jul 11 07:26:11 PM PDT 24
Finished Jul 11 07:26:18 PM PDT 24
Peak memory 213792 kb
Host smart-4bb74a91-3dc3-4d1e-8455-7dfd3c5ceea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349017728 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1349017728
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.107385025
Short name T946
Test name
Test status
Simulation time 450629656 ps
CPU time 1.47 seconds
Started Jul 11 07:30:47 PM PDT 24
Finished Jul 11 07:30:50 PM PDT 24
Peak memory 205488 kb
Host smart-a91c951e-9ed3-4a8a-ae89-d0c80e469b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107385025 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.107385025
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.750211993
Short name T1404
Test name
Test status
Simulation time 203181435 ps
CPU time 1.36 seconds
Started Jul 11 07:26:08 PM PDT 24
Finished Jul 11 07:26:11 PM PDT 24
Peak memory 205472 kb
Host smart-34841403-0a24-4e12-a31f-794ad4c43698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750211993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.750211993
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.3568064858
Short name T1514
Test name
Test status
Simulation time 493207150 ps
CPU time 2.63 seconds
Started Jul 11 07:26:14 PM PDT 24
Finished Jul 11 07:26:19 PM PDT 24
Peak memory 205440 kb
Host smart-2dbfdea8-80d1-42c7-94e9-d5528336196f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568064858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.3568064858
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.1185425789
Short name T871
Test name
Test status
Simulation time 70603668 ps
CPU time 0.9 seconds
Started Jul 11 07:26:12 PM PDT 24
Finished Jul 11 07:26:16 PM PDT 24
Peak memory 205356 kb
Host smart-e3289c9e-0473-419d-ba7c-3e566be271e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185425789 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.1185425789
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4081443569
Short name T289
Test name
Test status
Simulation time 1149606784 ps
CPU time 3.73 seconds
Started Jul 11 07:26:09 PM PDT 24
Finished Jul 11 07:26:14 PM PDT 24
Peak memory 213940 kb
Host smart-0eb53e3f-965d-4c2c-b82e-fe707e59565f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081443569 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4081443569
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1135530391
Short name T1374
Test name
Test status
Simulation time 19782615459 ps
CPU time 471.6 seconds
Started Jul 11 07:26:29 PM PDT 24
Finished Jul 11 07:34:22 PM PDT 24
Peak memory 4648276 kb
Host smart-0470ae1d-68b7-42f5-b75b-3e81c8fc7f9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135530391 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1135530391
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.2199529773
Short name T1189
Test name
Test status
Simulation time 581549865 ps
CPU time 3.15 seconds
Started Jul 11 07:26:20 PM PDT 24
Finished Jul 11 07:26:25 PM PDT 24
Peak memory 213720 kb
Host smart-6ba21aeb-cecb-4419-a600-59d2ed2aca46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199529773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.2199529773
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.4153531361
Short name T415
Test name
Test status
Simulation time 2982211271 ps
CPU time 2.57 seconds
Started Jul 11 07:26:16 PM PDT 24
Finished Jul 11 07:26:21 PM PDT 24
Peak memory 205572 kb
Host smart-96afd702-8204-4c9b-b722-52bed3d995e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153531361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.4153531361
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.2409619795
Short name T321
Test name
Test status
Simulation time 1370482013 ps
CPU time 1.96 seconds
Started Jul 11 07:26:13 PM PDT 24
Finished Jul 11 07:26:18 PM PDT 24
Peak memory 205340 kb
Host smart-7a12138d-61ed-4361-a902-dca6904e596b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409619795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.2409619795
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.845793431
Short name T1324
Test name
Test status
Simulation time 1598921880 ps
CPU time 23.32 seconds
Started Jul 11 07:26:01 PM PDT 24
Finished Jul 11 07:26:27 PM PDT 24
Peak memory 213664 kb
Host smart-0f6cfb78-ee42-4dc8-9894-8ebb61c2ab12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845793431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.845793431
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.804787166
Short name T731
Test name
Test status
Simulation time 241175919 ps
CPU time 10.98 seconds
Started Jul 11 07:26:05 PM PDT 24
Finished Jul 11 07:26:18 PM PDT 24
Peak memory 205524 kb
Host smart-87f22137-1014-4df8-bb09-bf384086755b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804787166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.804787166
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1269710438
Short name T1453
Test name
Test status
Simulation time 51664101992 ps
CPU time 1224.34 seconds
Started Jul 11 07:26:02 PM PDT 24
Finished Jul 11 07:46:29 PM PDT 24
Peak memory 7327556 kb
Host smart-47a0bec4-c64e-4808-afc7-b80424aeabc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269710438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1269710438
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.4203190669
Short name T1513
Test name
Test status
Simulation time 3409245915 ps
CPU time 10.23 seconds
Started Jul 11 07:26:03 PM PDT 24
Finished Jul 11 07:26:16 PM PDT 24
Peak memory 346436 kb
Host smart-23cafc46-152a-41af-a4a4-1ce2d5531d87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203190669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.4203190669
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1754073112
Short name T124
Test name
Test status
Simulation time 37554532 ps
CPU time 0.98 seconds
Started Jul 11 07:26:15 PM PDT 24
Finished Jul 11 07:26:19 PM PDT 24
Peak memory 205496 kb
Host smart-99e8114e-6ae2-4fd0-8782-fad56ade22b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754073112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1754073112
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2946860130
Short name T1318
Test name
Test status
Simulation time 46614499 ps
CPU time 0.64 seconds
Started Jul 11 07:26:35 PM PDT 24
Finished Jul 11 07:26:39 PM PDT 24
Peak memory 204700 kb
Host smart-d49d1e73-168f-45d4-a4be-d0dd959a5e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946860130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2946860130
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2375178446
Short name T898
Test name
Test status
Simulation time 361298749 ps
CPU time 6.25 seconds
Started Jul 11 07:26:21 PM PDT 24
Finished Jul 11 07:26:29 PM PDT 24
Peak memory 250104 kb
Host smart-501df9d3-72f5-48a3-bd5c-86bed1bee10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375178446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2375178446
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.132952388
Short name T258
Test name
Test status
Simulation time 739748114 ps
CPU time 5.31 seconds
Started Jul 11 07:26:18 PM PDT 24
Finished Jul 11 07:26:25 PM PDT 24
Peak memory 249380 kb
Host smart-9bbb3ef7-8f9d-4378-8163-bc6771574a5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132952388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.132952388
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3107610163
Short name T71
Test name
Test status
Simulation time 12893562114 ps
CPU time 77.54 seconds
Started Jul 11 07:26:21 PM PDT 24
Finished Jul 11 07:27:40 PM PDT 24
Peak memory 433980 kb
Host smart-b51fa44f-e691-4ee0-baba-3d2a2c35ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107610163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3107610163
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2986397055
Short name T803
Test name
Test status
Simulation time 1588799917 ps
CPU time 103.84 seconds
Started Jul 11 07:26:19 PM PDT 24
Finished Jul 11 07:28:05 PM PDT 24
Peak memory 540956 kb
Host smart-6599213a-f435-4886-9842-62e07b1e6050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986397055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2986397055
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1202655501
Short name T578
Test name
Test status
Simulation time 101819480 ps
CPU time 0.96 seconds
Started Jul 11 07:26:20 PM PDT 24
Finished Jul 11 07:26:23 PM PDT 24
Peak memory 205160 kb
Host smart-2ea68038-9678-4b7a-a627-c8d38a5bc770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202655501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1202655501
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2434432764
Short name T368
Test name
Test status
Simulation time 181203383 ps
CPU time 8.1 seconds
Started Jul 11 07:26:19 PM PDT 24
Finished Jul 11 07:26:29 PM PDT 24
Peak memory 205376 kb
Host smart-7674783e-ec45-4101-982c-b19973997880
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434432764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2434432764
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.179214191
Short name T110
Test name
Test status
Simulation time 18853458517 ps
CPU time 139.45 seconds
Started Jul 11 07:26:19 PM PDT 24
Finished Jul 11 07:28:40 PM PDT 24
Peak memory 1381472 kb
Host smart-1e6f7c50-75b5-40c7-ba35-6a20fec52bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179214191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.179214191
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.4013715633
Short name T240
Test name
Test status
Simulation time 2743655016 ps
CPU time 30.17 seconds
Started Jul 11 07:26:34 PM PDT 24
Finished Jul 11 07:27:07 PM PDT 24
Peak memory 205492 kb
Host smart-9b17a53b-f098-4025-9f7f-ba63810e382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013715633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.4013715633
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.4197665188
Short name T477
Test name
Test status
Simulation time 25143675 ps
CPU time 0.68 seconds
Started Jul 11 07:26:18 PM PDT 24
Finished Jul 11 07:26:21 PM PDT 24
Peak memory 205164 kb
Host smart-3f306fe3-fcac-48fa-a5a3-b65f23e99fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197665188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.4197665188
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1038294384
Short name T923
Test name
Test status
Simulation time 13255206567 ps
CPU time 82.64 seconds
Started Jul 11 07:26:19 PM PDT 24
Finished Jul 11 07:27:43 PM PDT 24
Peak memory 205432 kb
Host smart-d9133395-3fbd-42f0-bb78-8517491d26de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038294384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1038294384
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.3942000433
Short name T613
Test name
Test status
Simulation time 242946757 ps
CPU time 1.15 seconds
Started Jul 11 07:26:18 PM PDT 24
Finished Jul 11 07:26:21 PM PDT 24
Peak memory 205192 kb
Host smart-87aa7ba9-adb4-4df3-a5cf-986e87214498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942000433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.3942000433
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3884671170
Short name T1251
Test name
Test status
Simulation time 1838534789 ps
CPU time 32.42 seconds
Started Jul 11 07:26:20 PM PDT 24
Finished Jul 11 07:26:54 PM PDT 24
Peak memory 323780 kb
Host smart-5e63d42a-4b5f-451e-be0b-a860e125cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884671170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3884671170
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2318436986
Short name T394
Test name
Test status
Simulation time 2497693185 ps
CPU time 19.92 seconds
Started Jul 11 07:26:19 PM PDT 24
Finished Jul 11 07:26:41 PM PDT 24
Peak memory 229868 kb
Host smart-e8df70af-477d-4f5a-ad9f-477055f7e35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318436986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2318436986
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1106260814
Short name T349
Test name
Test status
Simulation time 1149521840 ps
CPU time 5.67 seconds
Started Jul 11 07:26:30 PM PDT 24
Finished Jul 11 07:26:37 PM PDT 24
Peak memory 213796 kb
Host smart-40f0f8cc-ea64-43dc-8f82-0ed71cc5e292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106260814 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1106260814
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3902951867
Short name T699
Test name
Test status
Simulation time 442865974 ps
CPU time 1.19 seconds
Started Jul 11 07:26:28 PM PDT 24
Finished Jul 11 07:26:31 PM PDT 24
Peak memory 205364 kb
Host smart-b80c9dd9-4836-44ad-a0df-c12bd5917c4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902951867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3902951867
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.1379389041
Short name T515
Test name
Test status
Simulation time 1059890791 ps
CPU time 3.11 seconds
Started Jul 11 07:26:31 PM PDT 24
Finished Jul 11 07:26:36 PM PDT 24
Peak memory 205476 kb
Host smart-398cdb8c-e020-49dc-8d2d-26947cb29be7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379389041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1379389041
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2241272070
Short name T288
Test name
Test status
Simulation time 1043699907 ps
CPU time 1.36 seconds
Started Jul 11 07:26:32 PM PDT 24
Finished Jul 11 07:26:36 PM PDT 24
Peak memory 205388 kb
Host smart-bcfdb339-39c2-49ca-b7ea-18b052f97345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241272070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2241272070
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2106825779
Short name T1421
Test name
Test status
Simulation time 5440648908 ps
CPU time 7.7 seconds
Started Jul 11 07:26:25 PM PDT 24
Finished Jul 11 07:26:34 PM PDT 24
Peak memory 213752 kb
Host smart-464aebb2-7763-4bc0-aa11-96710c619f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106825779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2106825779
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3005924898
Short name T741
Test name
Test status
Simulation time 20671274688 ps
CPU time 413.4 seconds
Started Jul 11 07:26:26 PM PDT 24
Finished Jul 11 07:33:21 PM PDT 24
Peak memory 3526288 kb
Host smart-c500a774-973a-42fb-958e-366f4d30379e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005924898 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3005924898
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.713938177
Short name T192
Test name
Test status
Simulation time 2036654707 ps
CPU time 2.87 seconds
Started Jul 11 07:26:31 PM PDT 24
Finished Jul 11 07:26:37 PM PDT 24
Peak memory 213748 kb
Host smart-121352c8-eabc-46a2-870c-4eedcc063699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713938177 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_nack_acqfull.713938177
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.523698187
Short name T846
Test name
Test status
Simulation time 2372762950 ps
CPU time 2.89 seconds
Started Jul 11 07:26:37 PM PDT 24
Finished Jul 11 07:26:45 PM PDT 24
Peak memory 205552 kb
Host smart-588c14dd-4dfc-457d-8e4f-4e25b72a5e63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523698187 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.523698187
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.443229539
Short name T617
Test name
Test status
Simulation time 493413439 ps
CPU time 2.36 seconds
Started Jul 11 07:26:30 PM PDT 24
Finished Jul 11 07:26:34 PM PDT 24
Peak memory 205364 kb
Host smart-d9cd3827-8f9a-4353-bd5c-eb48f4783f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443229539 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_smbus_maxlen.443229539
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.412519985
Short name T323
Test name
Test status
Simulation time 2754750565 ps
CPU time 10.93 seconds
Started Jul 11 07:26:21 PM PDT 24
Finished Jul 11 07:26:33 PM PDT 24
Peak memory 213784 kb
Host smart-f184584b-b6c9-4cc3-9ff8-a50c0ed35d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412519985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.412519985
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3864067551
Short name T684
Test name
Test status
Simulation time 6845111136 ps
CPU time 18.84 seconds
Started Jul 11 07:26:25 PM PDT 24
Finished Jul 11 07:26:45 PM PDT 24
Peak memory 225352 kb
Host smart-946610c5-55b7-4810-b142-ceb457310f91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864067551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3864067551
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.645927765
Short name T403
Test name
Test status
Simulation time 15672046358 ps
CPU time 31.98 seconds
Started Jul 11 07:26:28 PM PDT 24
Finished Jul 11 07:27:01 PM PDT 24
Peak memory 205708 kb
Host smart-245437f2-fd77-499b-bf3b-1f5a703cf589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645927765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.645927765
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3775618735
Short name T626
Test name
Test status
Simulation time 2255920560 ps
CPU time 7.68 seconds
Started Jul 11 07:26:27 PM PDT 24
Finished Jul 11 07:26:36 PM PDT 24
Peak memory 308448 kb
Host smart-430bbb8c-f6d8-479e-b097-3515e350deb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775618735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3775618735
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2589654128
Short name T329
Test name
Test status
Simulation time 1193292947 ps
CPU time 6.82 seconds
Started Jul 11 07:26:25 PM PDT 24
Finished Jul 11 07:26:33 PM PDT 24
Peak memory 221848 kb
Host smart-86124d0e-ad18-43e8-be78-ceb3dac89fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589654128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2589654128
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.1594012417
Short name T1100
Test name
Test status
Simulation time 282496332 ps
CPU time 4.07 seconds
Started Jul 11 07:26:31 PM PDT 24
Finished Jul 11 07:26:37 PM PDT 24
Peak memory 205456 kb
Host smart-d3b42575-e565-4576-8664-b89607d54fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594012417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1594012417
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.871001995
Short name T1306
Test name
Test status
Simulation time 56352646 ps
CPU time 0.64 seconds
Started Jul 11 07:26:47 PM PDT 24
Finished Jul 11 07:26:52 PM PDT 24
Peak memory 204764 kb
Host smart-5c51ff95-1aa1-4d2b-8cb4-47cd630be381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871001995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.871001995
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3159651058
Short name T638
Test name
Test status
Simulation time 368594646 ps
CPU time 7.06 seconds
Started Jul 11 07:26:37 PM PDT 24
Finished Jul 11 07:26:48 PM PDT 24
Peak memory 235076 kb
Host smart-85c8f6f9-4a57-4fe4-9eec-599f1b47393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159651058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3159651058
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.955916505
Short name T90
Test name
Test status
Simulation time 1403437746 ps
CPU time 21.34 seconds
Started Jul 11 07:26:36 PM PDT 24
Finished Jul 11 07:27:01 PM PDT 24
Peak memory 291956 kb
Host smart-fd2c943d-e43a-489b-b2e2-147e7f1ac5a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955916505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.955916505
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.721587499
Short name T652
Test name
Test status
Simulation time 7208109994 ps
CPU time 59.46 seconds
Started Jul 11 07:26:36 PM PDT 24
Finished Jul 11 07:27:40 PM PDT 24
Peak memory 575880 kb
Host smart-74430727-3b42-4ede-919c-d7864496b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721587499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.721587499
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.451842484
Short name T1387
Test name
Test status
Simulation time 1776034870 ps
CPU time 122.17 seconds
Started Jul 11 07:26:40 PM PDT 24
Finished Jul 11 07:28:48 PM PDT 24
Peak memory 603116 kb
Host smart-b8492c05-e42c-4c11-aa2f-576cd36fd280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451842484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.451842484
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1957252181
Short name T88
Test name
Test status
Simulation time 190078200 ps
CPU time 0.91 seconds
Started Jul 11 07:26:38 PM PDT 24
Finished Jul 11 07:26:44 PM PDT 24
Peak memory 205180 kb
Host smart-aad98b74-15ce-46c8-adfd-b16800b59cdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957252181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1957252181
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4222391898
Short name T975
Test name
Test status
Simulation time 139193810 ps
CPU time 3.32 seconds
Started Jul 11 07:26:38 PM PDT 24
Finished Jul 11 07:26:46 PM PDT 24
Peak memory 205376 kb
Host smart-2a32f08c-6c79-420e-a49d-2e8e1dcfc174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222391898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4222391898
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1902564065
Short name T106
Test name
Test status
Simulation time 15340528247 ps
CPU time 80.7 seconds
Started Jul 11 07:26:37 PM PDT 24
Finished Jul 11 07:28:03 PM PDT 24
Peak memory 1016124 kb
Host smart-18e8df7c-7995-4561-9f9b-e22b8fb4e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902564065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1902564065
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.341279127
Short name T249
Test name
Test status
Simulation time 1027825189 ps
CPU time 8.36 seconds
Started Jul 11 07:26:44 PM PDT 24
Finished Jul 11 07:26:57 PM PDT 24
Peak memory 205324 kb
Host smart-367b8209-7539-42a8-811a-312043aa03e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341279127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.341279127
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.917211671
Short name T618
Test name
Test status
Simulation time 45816988 ps
CPU time 0.71 seconds
Started Jul 11 07:26:43 PM PDT 24
Finished Jul 11 07:26:48 PM PDT 24
Peak memory 205100 kb
Host smart-206f9ff7-7216-4230-a940-d14ac9d84642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917211671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.917211671
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1572179096
Short name T432
Test name
Test status
Simulation time 3007191931 ps
CPU time 36.95 seconds
Started Jul 11 07:26:36 PM PDT 24
Finished Jul 11 07:27:17 PM PDT 24
Peak memory 367580 kb
Host smart-532b6913-e427-495a-9a1b-190abcc071aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572179096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1572179096
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.746689996
Short name T1217
Test name
Test status
Simulation time 74598950 ps
CPU time 1.4 seconds
Started Jul 11 07:26:43 PM PDT 24
Finished Jul 11 07:26:49 PM PDT 24
Peak memory 213404 kb
Host smart-d37e2940-d7af-431b-a311-d44140ab85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746689996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.746689996
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2747289501
Short name T1204
Test name
Test status
Simulation time 4115429410 ps
CPU time 43.41 seconds
Started Jul 11 07:26:37 PM PDT 24
Finished Jul 11 07:27:25 PM PDT 24
Peak memory 461904 kb
Host smart-411af8fd-745f-4df1-9f42-530977abb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747289501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2747289501
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.4257013687
Short name T273
Test name
Test status
Simulation time 4983237400 ps
CPU time 441.46 seconds
Started Jul 11 07:26:36 PM PDT 24
Finished Jul 11 07:34:02 PM PDT 24
Peak memory 1321428 kb
Host smart-b59b8cc7-e5f2-49e2-bed4-78b9ac6b3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257013687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.4257013687
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.310064583
Short name T577
Test name
Test status
Simulation time 6126439490 ps
CPU time 12.3 seconds
Started Jul 11 07:26:38 PM PDT 24
Finished Jul 11 07:26:54 PM PDT 24
Peak memory 221464 kb
Host smart-4d0aa04a-aa6a-44df-9a45-a2761c5b7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310064583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.310064583
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2998637069
Short name T1354
Test name
Test status
Simulation time 525020876 ps
CPU time 3.51 seconds
Started Jul 11 07:26:41 PM PDT 24
Finished Jul 11 07:26:49 PM PDT 24
Peak memory 220660 kb
Host smart-bdf1d51b-8349-47b7-8789-142961f4aecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998637069 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2998637069
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3337898901
Short name T1097
Test name
Test status
Simulation time 228916288 ps
CPU time 1.49 seconds
Started Jul 11 07:26:43 PM PDT 24
Finished Jul 11 07:26:49 PM PDT 24
Peak memory 205740 kb
Host smart-3df094b1-18a1-4a3f-8266-c7aa5b3584ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337898901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3337898901
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3340701873
Short name T1343
Test name
Test status
Simulation time 896280458 ps
CPU time 1.27 seconds
Started Jul 11 07:26:41 PM PDT 24
Finished Jul 11 07:26:47 PM PDT 24
Peak memory 205492 kb
Host smart-adf09ab3-4299-4aa9-b4a9-cba79c4be82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340701873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3340701873
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.21581588
Short name T835
Test name
Test status
Simulation time 851012083 ps
CPU time 2.51 seconds
Started Jul 11 07:26:42 PM PDT 24
Finished Jul 11 07:26:50 PM PDT 24
Peak memory 205524 kb
Host smart-8ca208af-5b9c-48ed-bd4b-73f7c2bbd2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21581588 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.21581588
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.4283335981
Short name T1108
Test name
Test status
Simulation time 1229462567 ps
CPU time 1.45 seconds
Started Jul 11 07:26:44 PM PDT 24
Finished Jul 11 07:26:50 PM PDT 24
Peak memory 205388 kb
Host smart-14266fba-3b35-4eed-aa5f-d6cd24c3b563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283335981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.4283335981
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2185778335
Short name T43
Test name
Test status
Simulation time 1053911607 ps
CPU time 6.7 seconds
Started Jul 11 07:26:42 PM PDT 24
Finished Jul 11 07:26:54 PM PDT 24
Peak memory 232544 kb
Host smart-33bd4916-8f66-4f88-86b7-9972dc689c8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185778335 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2185778335
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2956156787
Short name T391
Test name
Test status
Simulation time 11586079785 ps
CPU time 58.39 seconds
Started Jul 11 07:26:41 PM PDT 24
Finished Jul 11 07:27:44 PM PDT 24
Peak memory 1134152 kb
Host smart-784ca834-9f5c-4b8a-8051-7263b77927bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956156787 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2956156787
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.1652157919
Short name T1025
Test name
Test status
Simulation time 6238712860 ps
CPU time 2.72 seconds
Started Jul 11 07:26:48 PM PDT 24
Finished Jul 11 07:26:54 PM PDT 24
Peak memory 213756 kb
Host smart-73674bd3-8af0-4d12-990f-fbd83132503d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652157919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.1652157919
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.1030288820
Short name T364
Test name
Test status
Simulation time 523843259 ps
CPU time 2.86 seconds
Started Jul 11 07:27:35 PM PDT 24
Finished Jul 11 07:27:39 PM PDT 24
Peak memory 205488 kb
Host smart-fbc64733-057a-40b5-a550-17316616ccdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030288820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.1030288820
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.2543499200
Short name T1115
Test name
Test status
Simulation time 528054589 ps
CPU time 2.32 seconds
Started Jul 11 07:26:47 PM PDT 24
Finished Jul 11 07:26:53 PM PDT 24
Peak memory 205368 kb
Host smart-271fd2cc-64aa-4a6c-98d3-54fc30d8a025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543499200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.2543499200
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.908803206
Short name T934
Test name
Test status
Simulation time 1209976420 ps
CPU time 14.5 seconds
Started Jul 11 07:26:38 PM PDT 24
Finished Jul 11 07:26:58 PM PDT 24
Peak memory 213700 kb
Host smart-934a0575-1957-4100-ae83-fd6b6e71e6dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908803206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.908803206
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3122061381
Short name T978
Test name
Test status
Simulation time 450423034 ps
CPU time 8.4 seconds
Started Jul 11 07:26:42 PM PDT 24
Finished Jul 11 07:26:55 PM PDT 24
Peak memory 205480 kb
Host smart-69068b96-9613-4c49-8652-b75d76d5c5d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122061381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3122061381
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2406617110
Short name T1116
Test name
Test status
Simulation time 14530056949 ps
CPU time 7.9 seconds
Started Jul 11 07:26:41 PM PDT 24
Finished Jul 11 07:26:54 PM PDT 24
Peak memory 205552 kb
Host smart-746750eb-bd78-46dd-8234-0f1130aef393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406617110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2406617110
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.224533778
Short name T1323
Test name
Test status
Simulation time 4786266186 ps
CPU time 117.12 seconds
Started Jul 11 07:26:43 PM PDT 24
Finished Jul 11 07:28:45 PM PDT 24
Peak memory 722764 kb
Host smart-6f0bc90a-8062-4f0d-ab31-ce077f65bd49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224533778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.224533778
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3600973082
Short name T546
Test name
Test status
Simulation time 2480824441 ps
CPU time 6.83 seconds
Started Jul 11 07:26:44 PM PDT 24
Finished Jul 11 07:26:55 PM PDT 24
Peak memory 221876 kb
Host smart-0724c433-e792-4236-a669-13b24a665d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600973082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3600973082
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.2935741887
Short name T49
Test name
Test status
Simulation time 300926330 ps
CPU time 4.94 seconds
Started Jul 11 07:26:53 PM PDT 24
Finished Jul 11 07:27:00 PM PDT 24
Peak memory 205984 kb
Host smart-29c01d95-f01f-48e8-b9d4-3a66879d06d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935741887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2935741887
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3032749360
Short name T1447
Test name
Test status
Simulation time 19409282 ps
CPU time 0.63 seconds
Started Jul 11 07:27:06 PM PDT 24
Finished Jul 11 07:27:08 PM PDT 24
Peak memory 204612 kb
Host smart-55919827-4202-4d4d-8dcb-ff6156331e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032749360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3032749360
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.769014371
Short name T1410
Test name
Test status
Simulation time 174581453 ps
CPU time 7.23 seconds
Started Jul 11 07:26:53 PM PDT 24
Finished Jul 11 07:27:02 PM PDT 24
Peak memory 235832 kb
Host smart-a1089bd1-2071-4dc9-8886-0e4cd11c4e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769014371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.769014371
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.55255602
Short name T1307
Test name
Test status
Simulation time 346809749 ps
CPU time 7.37 seconds
Started Jul 11 07:26:59 PM PDT 24
Finished Jul 11 07:27:09 PM PDT 24
Peak memory 273080 kb
Host smart-81b9e358-5abf-43e5-8c97-0ef0f617b9d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55255602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty
.55255602
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1476151985
Short name T793
Test name
Test status
Simulation time 1413267786 ps
CPU time 41.6 seconds
Started Jul 11 07:26:57 PM PDT 24
Finished Jul 11 07:27:42 PM PDT 24
Peak memory 446268 kb
Host smart-c9ed0248-e6d2-43d6-9a4a-f37df8b12cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476151985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1476151985
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1483473703
Short name T809
Test name
Test status
Simulation time 5490114353 ps
CPU time 95.01 seconds
Started Jul 11 07:26:49 PM PDT 24
Finished Jul 11 07:28:27 PM PDT 24
Peak memory 548488 kb
Host smart-717fba1b-b289-4b3d-987b-5fe01aea9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483473703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1483473703
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.454128669
Short name T1055
Test name
Test status
Simulation time 108567726 ps
CPU time 1.2 seconds
Started Jul 11 07:26:58 PM PDT 24
Finished Jul 11 07:27:02 PM PDT 24
Peak memory 205476 kb
Host smart-6358959e-9231-4662-90fa-3c38f5bdc35c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454128669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.454128669
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.238608790
Short name T1399
Test name
Test status
Simulation time 152148515 ps
CPU time 3.28 seconds
Started Jul 11 07:26:52 PM PDT 24
Finished Jul 11 07:26:58 PM PDT 24
Peak memory 205380 kb
Host smart-ece3437f-4e45-49ba-a67e-aa925eab673f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238608790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
238608790
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.937912896
Short name T1136
Test name
Test status
Simulation time 3218593465 ps
CPU time 73.59 seconds
Started Jul 11 07:26:46 PM PDT 24
Finished Jul 11 07:28:03 PM PDT 24
Peak memory 864872 kb
Host smart-88d73b9b-96a5-42c2-8076-aefaa90bd209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937912896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.937912896
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1965421256
Short name T1556
Test name
Test status
Simulation time 525859060 ps
CPU time 6.83 seconds
Started Jul 11 07:27:05 PM PDT 24
Finished Jul 11 07:27:14 PM PDT 24
Peak memory 205384 kb
Host smart-b22b9e6d-19e8-42af-9991-2b9ebc461d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965421256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1965421256
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.2049011901
Short name T639
Test name
Test status
Simulation time 17935027 ps
CPU time 0.64 seconds
Started Jul 11 07:26:47 PM PDT 24
Finished Jul 11 07:26:52 PM PDT 24
Peak memory 205136 kb
Host smart-db79c242-98bb-4a58-8ce8-a22fbca59cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049011901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2049011901
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1579759475
Short name T393
Test name
Test status
Simulation time 7345811266 ps
CPU time 25.13 seconds
Started Jul 11 07:26:58 PM PDT 24
Finished Jul 11 07:27:26 PM PDT 24
Peak memory 205572 kb
Host smart-d280c0cf-dcce-4332-b39b-bc03898896f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579759475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1579759475
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3781764500
Short name T827
Test name
Test status
Simulation time 23615257697 ps
CPU time 77.76 seconds
Started Jul 11 07:26:59 PM PDT 24
Finished Jul 11 07:28:20 PM PDT 24
Peak memory 205448 kb
Host smart-4269c6ad-47c1-4d90-9b73-04540cd5c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781764500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3781764500
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1927632814
Short name T1148
Test name
Test status
Simulation time 12382600376 ps
CPU time 93.8 seconds
Started Jul 11 07:26:54 PM PDT 24
Finished Jul 11 07:28:30 PM PDT 24
Peak memory 465684 kb
Host smart-ee6e6626-540e-45cf-8b7b-4fca3ed6a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927632814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1927632814
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.500449136
Short name T1368
Test name
Test status
Simulation time 2797060795 ps
CPU time 13.54 seconds
Started Jul 11 07:26:54 PM PDT 24
Finished Jul 11 07:27:09 PM PDT 24
Peak memory 218108 kb
Host smart-94cd2547-3283-46f3-8204-99cc5f4d9d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500449136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.500449136
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2655110627
Short name T567
Test name
Test status
Simulation time 3263164127 ps
CPU time 4.39 seconds
Started Jul 11 07:26:58 PM PDT 24
Finished Jul 11 07:27:06 PM PDT 24
Peak memory 213780 kb
Host smart-1977fe59-d8f7-49e4-a238-ee0119ffe6f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655110627 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2655110627
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3432294648
Short name T1509
Test name
Test status
Simulation time 418626630 ps
CPU time 1.68 seconds
Started Jul 11 07:26:59 PM PDT 24
Finished Jul 11 07:27:04 PM PDT 24
Peak memory 205472 kb
Host smart-1819c014-9cb2-4d48-bec8-f1b01633e30a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432294648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3432294648
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.1618298170
Short name T566
Test name
Test status
Simulation time 540200366 ps
CPU time 1.14 seconds
Started Jul 11 07:27:03 PM PDT 24
Finished Jul 11 07:27:06 PM PDT 24
Peak memory 205336 kb
Host smart-11b5e5f3-5165-4e1e-bcd7-f2e13923f36b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618298170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.1618298170
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.3743270988
Short name T1397
Test name
Test status
Simulation time 385708270 ps
CPU time 2.68 seconds
Started Jul 11 07:27:04 PM PDT 24
Finished Jul 11 07:27:09 PM PDT 24
Peak memory 205444 kb
Host smart-0c659fbc-ee57-4e6f-baab-68d1a34d8f45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743270988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.3743270988
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3191581230
Short name T775
Test name
Test status
Simulation time 417716971 ps
CPU time 1.45 seconds
Started Jul 11 07:27:03 PM PDT 24
Finished Jul 11 07:27:07 PM PDT 24
Peak memory 205336 kb
Host smart-8d3e4b7b-c6e5-4458-89b3-ecae61d28daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191581230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3191581230
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.161431013
Short name T804
Test name
Test status
Simulation time 1575849028 ps
CPU time 8.87 seconds
Started Jul 11 07:26:58 PM PDT 24
Finished Jul 11 07:27:10 PM PDT 24
Peak memory 230024 kb
Host smart-4544e1d7-c0d8-4434-af3d-f04f1afd0c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161431013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.161431013
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3418197021
Short name T296
Test name
Test status
Simulation time 8655230162 ps
CPU time 27.97 seconds
Started Jul 11 07:26:52 PM PDT 24
Finished Jul 11 07:27:22 PM PDT 24
Peak memory 559572 kb
Host smart-48580653-16f4-499d-bbe9-3960d7de3875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418197021 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3418197021
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.2010589607
Short name T1292
Test name
Test status
Simulation time 1866195741 ps
CPU time 2.85 seconds
Started Jul 11 07:27:04 PM PDT 24
Finished Jul 11 07:27:09 PM PDT 24
Peak memory 213664 kb
Host smart-31585757-b021-4f30-ba95-41d344c15212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010589607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.2010589607
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.2957906586
Short name T1469
Test name
Test status
Simulation time 5908891066 ps
CPU time 2.89 seconds
Started Jul 11 07:27:04 PM PDT 24
Finished Jul 11 07:27:09 PM PDT 24
Peak memory 205524 kb
Host smart-844bc72d-2f2d-49ca-8bad-0ed2ea7954af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957906586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.2957906586
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.2425288430
Short name T1356
Test name
Test status
Simulation time 456420810 ps
CPU time 2.21 seconds
Started Jul 11 07:27:05 PM PDT 24
Finished Jul 11 07:27:10 PM PDT 24
Peak memory 205364 kb
Host smart-0a6dfe1f-d1f3-409d-b2d0-ee05f7415069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425288430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.2425288430
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1329912833
Short name T125
Test name
Test status
Simulation time 4750590214 ps
CPU time 33.79 seconds
Started Jul 11 07:26:59 PM PDT 24
Finished Jul 11 07:27:36 PM PDT 24
Peak memory 209344 kb
Host smart-063e468d-9f49-4751-9610-859709751d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329912833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1329912833
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3338460158
Short name T545
Test name
Test status
Simulation time 5116985606 ps
CPU time 24.32 seconds
Started Jul 11 07:26:53 PM PDT 24
Finished Jul 11 07:27:20 PM PDT 24
Peak memory 230096 kb
Host smart-2de220cf-fc53-46e3-95ec-04a219d0a49b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338460158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3338460158
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3388890117
Short name T736
Test name
Test status
Simulation time 34641365242 ps
CPU time 127.36 seconds
Started Jul 11 07:26:58 PM PDT 24
Finished Jul 11 07:29:08 PM PDT 24
Peak memory 1848256 kb
Host smart-eb99b2e5-a205-469a-8ef1-5a5b10071095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388890117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3388890117
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3266871
Short name T322
Test name
Test status
Simulation time 2251349360 ps
CPU time 110.47 seconds
Started Jul 11 07:26:53 PM PDT 24
Finished Jul 11 07:28:46 PM PDT 24
Peak memory 705828 kb
Host smart-dd73071c-52bd-45b6-980a-82fc81786ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_stretch.3266871
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3220167403
Short name T929
Test name
Test status
Simulation time 19807518808 ps
CPU time 7.47 seconds
Started Jul 11 07:26:57 PM PDT 24
Finished Jul 11 07:27:08 PM PDT 24
Peak memory 213700 kb
Host smart-1b9d3362-9351-42ec-bcbd-47a020fef779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220167403 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3220167403
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.2697917433
Short name T1345
Test name
Test status
Simulation time 245831725 ps
CPU time 3.51 seconds
Started Jul 11 07:27:06 PM PDT 24
Finished Jul 11 07:27:12 PM PDT 24
Peak memory 205488 kb
Host smart-154c4747-48dd-4b7b-8091-faccba58b064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697917433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2697917433
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1594316559
Short name T841
Test name
Test status
Simulation time 15581735 ps
CPU time 0.64 seconds
Started Jul 11 07:27:28 PM PDT 24
Finished Jul 11 07:27:30 PM PDT 24
Peak memory 204804 kb
Host smart-3e56421d-470c-4d03-a436-dd69687e4096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594316559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1594316559
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.788408100
Short name T28
Test name
Test status
Simulation time 161019258 ps
CPU time 1.62 seconds
Started Jul 11 07:27:15 PM PDT 24
Finished Jul 11 07:27:19 PM PDT 24
Peak memory 213620 kb
Host smart-c8f5fd48-8b34-4071-a64a-036a0dbfbfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788408100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.788408100
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1666009690
Short name T1242
Test name
Test status
Simulation time 336082016 ps
CPU time 6.91 seconds
Started Jul 11 07:27:10 PM PDT 24
Finished Jul 11 07:27:20 PM PDT 24
Peak memory 276352 kb
Host smart-f5b4df5f-0ca9-43cc-9422-140b947d85ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666009690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1666009690
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3013969813
Short name T143
Test name
Test status
Simulation time 1954212044 ps
CPU time 130.93 seconds
Started Jul 11 07:27:11 PM PDT 24
Finished Jul 11 07:29:25 PM PDT 24
Peak memory 591328 kb
Host smart-a50d889c-6942-487b-888d-b5858cdcb552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013969813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3013969813
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.581326387
Short name T815
Test name
Test status
Simulation time 1818012057 ps
CPU time 123.84 seconds
Started Jul 11 07:27:11 PM PDT 24
Finished Jul 11 07:29:18 PM PDT 24
Peak memory 630520 kb
Host smart-7e5bf907-f9f8-43d7-bb15-6943975729a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581326387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.581326387
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1271057987
Short name T892
Test name
Test status
Simulation time 70929421 ps
CPU time 0.87 seconds
Started Jul 11 07:27:11 PM PDT 24
Finished Jul 11 07:27:14 PM PDT 24
Peak memory 205176 kb
Host smart-0ebb338f-9eaf-4a68-97f6-d2a711e159ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271057987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1271057987
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.85586460
Short name T1338
Test name
Test status
Simulation time 169913554 ps
CPU time 8.85 seconds
Started Jul 11 07:27:14 PM PDT 24
Finished Jul 11 07:27:25 PM PDT 24
Peak memory 205360 kb
Host smart-d781f0bc-3e10-4361-bc92-6d407c5dcd27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85586460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.85586460
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3638943832
Short name T1520
Test name
Test status
Simulation time 15342266150 ps
CPU time 249.16 seconds
Started Jul 11 07:27:10 PM PDT 24
Finished Jul 11 07:31:22 PM PDT 24
Peak memory 1058500 kb
Host smart-221eb36b-d996-41b3-ae48-70c16502c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638943832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3638943832
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3359769425
Short name T252
Test name
Test status
Simulation time 922932708 ps
CPU time 3.96 seconds
Started Jul 11 07:27:23 PM PDT 24
Finished Jul 11 07:27:29 PM PDT 24
Peak memory 205316 kb
Host smart-9a97b71d-c2be-4e5f-9f75-cf4b117475ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359769425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3359769425
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.2799681349
Short name T453
Test name
Test status
Simulation time 17210098 ps
CPU time 0.68 seconds
Started Jul 11 07:27:11 PM PDT 24
Finished Jul 11 07:27:14 PM PDT 24
Peak memory 205140 kb
Host smart-865f6a1c-8b18-457c-880a-3f24e9f990da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799681349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2799681349
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.985580525
Short name T324
Test name
Test status
Simulation time 12486868189 ps
CPU time 22.8 seconds
Started Jul 11 07:27:12 PM PDT 24
Finished Jul 11 07:27:37 PM PDT 24
Peak memory 237132 kb
Host smart-935a36e7-f459-4b4a-b584-49ec3e33a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985580525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.985580525
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.2944310854
Short name T734
Test name
Test status
Simulation time 44177985 ps
CPU time 1.2 seconds
Started Jul 11 07:27:14 PM PDT 24
Finished Jul 11 07:27:17 PM PDT 24
Peak memory 223856 kb
Host smart-b94e88aa-a766-4024-8998-24d84bf19045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944310854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.2944310854
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3731190032
Short name T484
Test name
Test status
Simulation time 18515394647 ps
CPU time 24.19 seconds
Started Jul 11 07:27:05 PM PDT 24
Finished Jul 11 07:27:32 PM PDT 24
Peak memory 359632 kb
Host smart-505dc101-b27d-4e91-bfab-8819ee57d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731190032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3731190032
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3955608634
Short name T259
Test name
Test status
Simulation time 3169659438 ps
CPU time 34.8 seconds
Started Jul 11 07:27:10 PM PDT 24
Finished Jul 11 07:27:48 PM PDT 24
Peak memory 213660 kb
Host smart-894cfbdf-b387-45a6-9332-3508d455211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955608634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3955608634
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.824487159
Short name T843
Test name
Test status
Simulation time 4309043286 ps
CPU time 5.18 seconds
Started Jul 11 07:27:24 PM PDT 24
Finished Jul 11 07:27:30 PM PDT 24
Peak memory 213792 kb
Host smart-dfe06cbc-4482-440f-84af-61ea268ea3a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824487159 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.824487159
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2675960226
Short name T1130
Test name
Test status
Simulation time 391072866 ps
CPU time 1.32 seconds
Started Jul 11 07:27:16 PM PDT 24
Finished Jul 11 07:27:20 PM PDT 24
Peak memory 207740 kb
Host smart-4c74ae92-fef3-497e-9d36-465a638dd279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675960226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2675960226
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3586273073
Short name T294
Test name
Test status
Simulation time 198706918 ps
CPU time 1.27 seconds
Started Jul 11 07:27:27 PM PDT 24
Finished Jul 11 07:27:30 PM PDT 24
Peak memory 205480 kb
Host smart-a2d61c71-dc2c-4386-8d9d-d7d747f82e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586273073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3586273073
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3886788453
Short name T458
Test name
Test status
Simulation time 1470859181 ps
CPU time 1.87 seconds
Started Jul 11 07:27:24 PM PDT 24
Finished Jul 11 07:27:28 PM PDT 24
Peak memory 205388 kb
Host smart-6615510a-b996-495d-bd99-6a8d69a035ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886788453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3886788453
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.2420191973
Short name T470
Test name
Test status
Simulation time 173138548 ps
CPU time 1.64 seconds
Started Jul 11 07:27:22 PM PDT 24
Finished Jul 11 07:27:25 PM PDT 24
Peak memory 205392 kb
Host smart-1fae5973-2bae-47eb-a821-3750d9865e92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420191973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.2420191973
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1288863566
Short name T1214
Test name
Test status
Simulation time 5061773704 ps
CPU time 7.13 seconds
Started Jul 11 07:27:18 PM PDT 24
Finished Jul 11 07:27:26 PM PDT 24
Peak memory 217340 kb
Host smart-cc8367ea-1ad8-4be5-b5d0-61f9021d7200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288863566 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1288863566
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.120334770
Short name T119
Test name
Test status
Simulation time 20494235731 ps
CPU time 528.62 seconds
Started Jul 11 07:27:17 PM PDT 24
Finished Jul 11 07:36:07 PM PDT 24
Peak memory 4991836 kb
Host smart-1c2416aa-9476-49da-b582-392b838e3625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120334770 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.120334770
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.1080876837
Short name T1438
Test name
Test status
Simulation time 1177511364 ps
CPU time 2.89 seconds
Started Jul 11 07:27:28 PM PDT 24
Finished Jul 11 07:27:32 PM PDT 24
Peak memory 213716 kb
Host smart-095d26a3-1168-49b3-b742-72f6870376bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080876837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_acqfull.1080876837
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.1817505810
Short name T1382
Test name
Test status
Simulation time 1744468298 ps
CPU time 2.57 seconds
Started Jul 11 07:27:26 PM PDT 24
Finished Jul 11 07:27:30 PM PDT 24
Peak memory 205480 kb
Host smart-eb4b2024-e83f-467b-925d-10bd6cc283fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817505810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.1817505810
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.3384138614
Short name T314
Test name
Test status
Simulation time 1928706156 ps
CPU time 2.2 seconds
Started Jul 11 07:27:28 PM PDT 24
Finished Jul 11 07:27:32 PM PDT 24
Peak memory 205328 kb
Host smart-3e3acb1d-c181-4139-afe1-64e19ac4df87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384138614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.3384138614
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2663065068
Short name T707
Test name
Test status
Simulation time 775709569 ps
CPU time 24.97 seconds
Started Jul 11 07:27:18 PM PDT 24
Finished Jul 11 07:27:44 PM PDT 24
Peak memory 213716 kb
Host smart-05350f99-1a79-41c2-a9fb-6c615610f9f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663065068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2663065068
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.749021547
Short name T354
Test name
Test status
Simulation time 2795536878 ps
CPU time 60.93 seconds
Started Jul 11 07:27:16 PM PDT 24
Finished Jul 11 07:28:19 PM PDT 24
Peak memory 216952 kb
Host smart-296c0501-d5c4-493e-abb3-23aea801287a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749021547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.749021547
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1414842502
Short name T1495
Test name
Test status
Simulation time 15423029144 ps
CPU time 28.41 seconds
Started Jul 11 07:27:20 PM PDT 24
Finished Jul 11 07:27:50 PM PDT 24
Peak memory 205596 kb
Host smart-aff813fb-d76a-44ff-98fd-45f5b96295bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414842502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1414842502
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2254389332
Short name T859
Test name
Test status
Simulation time 7598940599 ps
CPU time 7 seconds
Started Jul 11 07:27:16 PM PDT 24
Finished Jul 11 07:27:25 PM PDT 24
Peak memory 234664 kb
Host smart-d87933ee-f18c-4dd3-a57c-f78e7b15ca06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254389332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2254389332
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.2362889922
Short name T360
Test name
Test status
Simulation time 406092620 ps
CPU time 5.66 seconds
Started Jul 11 07:27:29 PM PDT 24
Finished Jul 11 07:27:36 PM PDT 24
Peak memory 205448 kb
Host smart-3b3d155f-75ea-42e4-8ad8-e248d59c25da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362889922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2362889922
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2422229894
Short name T781
Test name
Test status
Simulation time 17778714 ps
CPU time 0.64 seconds
Started Jul 11 07:27:45 PM PDT 24
Finished Jul 11 07:27:47 PM PDT 24
Peak memory 204688 kb
Host smart-7bc2fa35-4fa0-4e80-a036-0a7063eb7344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422229894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2422229894
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.669948091
Short name T1299
Test name
Test status
Simulation time 1018551220 ps
CPU time 8.81 seconds
Started Jul 11 07:27:34 PM PDT 24
Finished Jul 11 07:27:44 PM PDT 24
Peak memory 213600 kb
Host smart-7be9d089-e271-4b1c-8eb6-5f5f55f91837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669948091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.669948091
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1157081631
Short name T1123
Test name
Test status
Simulation time 553931057 ps
CPU time 14.75 seconds
Started Jul 11 07:27:31 PM PDT 24
Finished Jul 11 07:27:47 PM PDT 24
Peak memory 259984 kb
Host smart-fb3bf346-b9f9-47b6-96ae-4513f8ea4197
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157081631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1157081631
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3838357708
Short name T526
Test name
Test status
Simulation time 8339730978 ps
CPU time 55.94 seconds
Started Jul 11 07:27:28 PM PDT 24
Finished Jul 11 07:28:26 PM PDT 24
Peak memory 603296 kb
Host smart-25bdac0d-2bb2-4d20-adb9-80862423309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838357708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3838357708
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.675101766
Short name T330
Test name
Test status
Simulation time 3003922683 ps
CPU time 86.08 seconds
Started Jul 11 07:27:28 PM PDT 24
Finished Jul 11 07:28:55 PM PDT 24
Peak memory 832260 kb
Host smart-c61e597a-300c-4e05-99ac-e002877199b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675101766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.675101766
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1243586446
Short name T1135
Test name
Test status
Simulation time 1020373551 ps
CPU time 1.31 seconds
Started Jul 11 07:27:32 PM PDT 24
Finished Jul 11 07:27:34 PM PDT 24
Peak memory 205308 kb
Host smart-c77345e9-a765-4743-b090-f55c8389f831
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243586446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1243586446
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3539039910
Short name T141
Test name
Test status
Simulation time 210735870 ps
CPU time 5 seconds
Started Jul 11 07:27:30 PM PDT 24
Finished Jul 11 07:27:36 PM PDT 24
Peak memory 205384 kb
Host smart-684c842d-6e38-4bbd-a4b1-dd4bb84e7356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539039910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3539039910
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.344403941
Short name T430
Test name
Test status
Simulation time 13324374747 ps
CPU time 259.51 seconds
Started Jul 11 07:27:30 PM PDT 24
Finished Jul 11 07:31:51 PM PDT 24
Peak memory 1082724 kb
Host smart-ef0c3bb6-f0b4-4ed4-93de-1f5360604aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344403941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.344403941
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.2201087761
Short name T837
Test name
Test status
Simulation time 3164940908 ps
CPU time 26.33 seconds
Started Jul 11 07:27:40 PM PDT 24
Finished Jul 11 07:28:08 PM PDT 24
Peak memory 205384 kb
Host smart-ceb7007b-e494-486c-a676-0f8f4585d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201087761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.2201087761
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.3012378432
Short name T1008
Test name
Test status
Simulation time 16443250 ps
CPU time 0.64 seconds
Started Jul 11 07:27:31 PM PDT 24
Finished Jul 11 07:27:33 PM PDT 24
Peak memory 205140 kb
Host smart-05574577-23ee-47e9-9de7-d5c8e2602665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012378432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3012378432
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.113129612
Short name T13
Test name
Test status
Simulation time 33065560355 ps
CPU time 32.87 seconds
Started Jul 11 07:27:37 PM PDT 24
Finished Jul 11 07:28:11 PM PDT 24
Peak memory 290316 kb
Host smart-801f21df-40b6-42b1-b80a-e8c766facfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113129612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.113129612
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3318486225
Short name T39
Test name
Test status
Simulation time 24404653991 ps
CPU time 94.13 seconds
Started Jul 11 07:27:33 PM PDT 24
Finished Jul 11 07:29:08 PM PDT 24
Peak memory 753412 kb
Host smart-22441312-dc2b-450b-8276-e5fc47f84f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318486225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3318486225
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1210489049
Short name T410
Test name
Test status
Simulation time 2055091374 ps
CPU time 31.33 seconds
Started Jul 11 07:27:26 PM PDT 24
Finished Jul 11 07:27:58 PM PDT 24
Peak memory 256908 kb
Host smart-c10d772e-9f46-4c11-a35d-cc4d891d23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210489049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1210489049
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2028637046
Short name T525
Test name
Test status
Simulation time 443507952 ps
CPU time 20.12 seconds
Started Jul 11 07:27:34 PM PDT 24
Finished Jul 11 07:27:56 PM PDT 24
Peak memory 213608 kb
Host smart-fa3b9f42-a405-43b6-9d90-35d011c507c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028637046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2028637046
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2790146672
Short name T352
Test name
Test status
Simulation time 11640068722 ps
CPU time 5.35 seconds
Started Jul 11 07:27:39 PM PDT 24
Finished Jul 11 07:27:46 PM PDT 24
Peak memory 215080 kb
Host smart-c7d383ba-d12a-4c3d-85c8-6c6e865547c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790146672 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2790146672
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.4105999703
Short name T954
Test name
Test status
Simulation time 373795910 ps
CPU time 0.96 seconds
Started Jul 11 07:27:35 PM PDT 24
Finished Jul 11 07:27:37 PM PDT 24
Peak memory 205348 kb
Host smart-a07c3fd8-4fc4-4660-bba2-789efeb5a3c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105999703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.4105999703
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.629973433
Short name T877
Test name
Test status
Simulation time 179110842 ps
CPU time 1.15 seconds
Started Jul 11 07:27:39 PM PDT 24
Finished Jul 11 07:27:41 PM PDT 24
Peak memory 205352 kb
Host smart-3fabcbd0-f39b-4bc4-898c-315a570c4120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629973433 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.629973433
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.68583190
Short name T120
Test name
Test status
Simulation time 2139903806 ps
CPU time 2.08 seconds
Started Jul 11 07:27:40 PM PDT 24
Finished Jul 11 07:27:44 PM PDT 24
Peak memory 205332 kb
Host smart-a9434e8c-b07f-4ca8-91b3-f43e819bd48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68583190 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.68583190
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.800216925
Short name T1041
Test name
Test status
Simulation time 327063470 ps
CPU time 1.5 seconds
Started Jul 11 07:27:39 PM PDT 24
Finished Jul 11 07:27:41 PM PDT 24
Peak memory 205392 kb
Host smart-5b35fc4e-cc5b-4e02-99fa-3cf3d1f376bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800216925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.800216925
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1165768460
Short name T726
Test name
Test status
Simulation time 1598762329 ps
CPU time 4.95 seconds
Started Jul 11 07:27:34 PM PDT 24
Finished Jul 11 07:27:40 PM PDT 24
Peak memory 217488 kb
Host smart-23e016fd-357f-4057-b212-9d24d92b097a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165768460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1165768460
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4191720980
Short name T1360
Test name
Test status
Simulation time 18105235358 ps
CPU time 367.16 seconds
Started Jul 11 07:27:40 PM PDT 24
Finished Jul 11 07:33:49 PM PDT 24
Peak memory 4266600 kb
Host smart-61864f85-2739-43f7-ad53-27f757775a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191720980 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4191720980
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1050729517
Short name T738
Test name
Test status
Simulation time 2487056234 ps
CPU time 3.2 seconds
Started Jul 11 07:27:40 PM PDT 24
Finished Jul 11 07:27:45 PM PDT 24
Peak memory 213824 kb
Host smart-f0096f57-78fe-45a8-b0f3-afd904a750f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050729517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1050729517
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.1914191967
Short name T375
Test name
Test status
Simulation time 538765963 ps
CPU time 2.33 seconds
Started Jul 11 07:27:45 PM PDT 24
Finished Jul 11 07:27:48 PM PDT 24
Peak memory 205304 kb
Host smart-e318ac6d-f588-4193-8f0b-aafd5b7add77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914191967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.1914191967
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.4105833289
Short name T1045
Test name
Test status
Simulation time 4016600251 ps
CPU time 10.58 seconds
Started Jul 11 07:27:33 PM PDT 24
Finished Jul 11 07:27:45 PM PDT 24
Peak memory 213776 kb
Host smart-1c257315-27a6-40a0-a013-c1cd3deaf8ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105833289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.4105833289
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.979451198
Short name T162
Test name
Test status
Simulation time 1342442598 ps
CPU time 13.59 seconds
Started Jul 11 07:27:35 PM PDT 24
Finished Jul 11 07:27:50 PM PDT 24
Peak memory 205428 kb
Host smart-335ae20b-9f48-4eb8-9194-5d2d8cc3902e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979451198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.979451198
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3683726487
Short name T739
Test name
Test status
Simulation time 34011140600 ps
CPU time 6.3 seconds
Started Jul 11 07:27:33 PM PDT 24
Finished Jul 11 07:27:40 PM PDT 24
Peak memory 213744 kb
Host smart-f711f1e7-4362-4e5c-9abe-3d55895033ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683726487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3683726487
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.4227670116
Short name T601
Test name
Test status
Simulation time 2963851262 ps
CPU time 28.65 seconds
Started Jul 11 07:27:33 PM PDT 24
Finished Jul 11 07:28:03 PM PDT 24
Peak memory 604652 kb
Host smart-e299980c-4795-4b8e-aa08-9188fb750218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227670116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.4227670116
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.11909814
Short name T1487
Test name
Test status
Simulation time 1386066887 ps
CPU time 7.05 seconds
Started Jul 11 07:27:34 PM PDT 24
Finished Jul 11 07:27:42 PM PDT 24
Peak memory 230528 kb
Host smart-edfd98c6-95ec-48f4-b76c-d3d1867b2f15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909814 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_timeout.11909814
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.3069666037
Short name T608
Test name
Test status
Simulation time 670887328 ps
CPU time 8.88 seconds
Started Jul 11 07:27:39 PM PDT 24
Finished Jul 11 07:27:49 PM PDT 24
Peak memory 205456 kb
Host smart-4e17bf7a-8b94-4ae3-8306-5006d7af6fd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069666037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3069666037
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2577172575
Short name T755
Test name
Test status
Simulation time 26593574 ps
CPU time 0.64 seconds
Started Jul 11 07:28:08 PM PDT 24
Finished Jul 11 07:28:12 PM PDT 24
Peak memory 204692 kb
Host smart-59d06214-77d1-4179-bc72-a91f2b7db4c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577172575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2577172575
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3047441931
Short name T1523
Test name
Test status
Simulation time 125995858 ps
CPU time 4.62 seconds
Started Jul 11 07:27:49 PM PDT 24
Finished Jul 11 07:27:54 PM PDT 24
Peak memory 229796 kb
Host smart-923e0f8b-382c-47d9-9930-ba008c3385d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047441931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3047441931
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1498556512
Short name T799
Test name
Test status
Simulation time 307609144 ps
CPU time 14.57 seconds
Started Jul 11 07:27:51 PM PDT 24
Finished Jul 11 07:28:06 PM PDT 24
Peak memory 252448 kb
Host smart-fa47ce68-b13b-4d7a-bb0c-f8ec3c1be7b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498556512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1498556512
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2635762152
Short name T144
Test name
Test status
Simulation time 2370771286 ps
CPU time 181.39 seconds
Started Jul 11 07:27:50 PM PDT 24
Finished Jul 11 07:30:52 PM PDT 24
Peak memory 794904 kb
Host smart-0e1d91dd-c4d3-4859-a8f2-06917916c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635762152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2635762152
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.598711296
Short name T135
Test name
Test status
Simulation time 1310072399 ps
CPU time 83.66 seconds
Started Jul 11 07:27:46 PM PDT 24
Finished Jul 11 07:29:11 PM PDT 24
Peak memory 500284 kb
Host smart-b39fceef-5ab6-427e-8803-0666db6b4f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598711296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.598711296
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3508741830
Short name T1532
Test name
Test status
Simulation time 131788420 ps
CPU time 1.03 seconds
Started Jul 11 07:27:49 PM PDT 24
Finished Jul 11 07:27:51 PM PDT 24
Peak memory 205176 kb
Host smart-29993636-cc1a-4cd5-a0d2-6c278f92f200
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508741830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3508741830
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3052424233
Short name T1386
Test name
Test status
Simulation time 3463939461 ps
CPU time 73.64 seconds
Started Jul 11 07:27:49 PM PDT 24
Finished Jul 11 07:29:04 PM PDT 24
Peak memory 994188 kb
Host smart-ed00b158-180d-4ebf-bbe5-d3cff30c8df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052424233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3052424233
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1862548049
Short name T260
Test name
Test status
Simulation time 616625468 ps
CPU time 4.21 seconds
Started Jul 11 07:28:01 PM PDT 24
Finished Jul 11 07:28:10 PM PDT 24
Peak memory 205392 kb
Host smart-f15e3d82-8d2a-447e-b391-263863e69a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862548049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1862548049
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.1440639638
Short name T130
Test name
Test status
Simulation time 455855216 ps
CPU time 0.7 seconds
Started Jul 11 07:27:46 PM PDT 24
Finished Jul 11 07:27:47 PM PDT 24
Peak memory 205072 kb
Host smart-4c8e0e5f-e34e-4c94-8099-b6ec8f6f53d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440639638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1440639638
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2997015423
Short name T991
Test name
Test status
Simulation time 5173064913 ps
CPU time 184.66 seconds
Started Jul 11 07:27:47 PM PDT 24
Finished Jul 11 07:30:53 PM PDT 24
Peak memory 1315460 kb
Host smart-6525aba9-af0b-49ee-a1b7-ad96fcba016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997015423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2997015423
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.2016492641
Short name T940
Test name
Test status
Simulation time 853523386 ps
CPU time 36.03 seconds
Started Jul 11 07:27:45 PM PDT 24
Finished Jul 11 07:28:22 PM PDT 24
Peak memory 205260 kb
Host smart-8d9fe81f-9dc8-44b9-868e-2b041a18a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016492641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2016492641
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.844303172
Short name T744
Test name
Test status
Simulation time 6360405061 ps
CPU time 30.69 seconds
Started Jul 11 07:27:45 PM PDT 24
Finished Jul 11 07:28:17 PM PDT 24
Peak memory 374868 kb
Host smart-d8b39f94-8ffa-4abf-bff8-c6690fc07e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844303172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.844303172
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.807057590
Short name T424
Test name
Test status
Simulation time 2184106061 ps
CPU time 34.49 seconds
Started Jul 11 07:27:48 PM PDT 24
Finished Jul 11 07:28:24 PM PDT 24
Peak memory 213716 kb
Host smart-c6cd340e-3ca6-4dbd-ac4c-17bfd985940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807057590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.807057590
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1438520118
Short name T379
Test name
Test status
Simulation time 485144999 ps
CPU time 1.14 seconds
Started Jul 11 07:27:58 PM PDT 24
Finished Jul 11 07:28:00 PM PDT 24
Peak memory 205488 kb
Host smart-4766a3f0-2cf2-4874-8f1f-7d8f2424cb62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438520118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1438520118
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3459228189
Short name T1364
Test name
Test status
Simulation time 194143978 ps
CPU time 1.21 seconds
Started Jul 11 07:27:59 PM PDT 24
Finished Jul 11 07:28:03 PM PDT 24
Peak memory 205388 kb
Host smart-cd99c8ff-5122-481f-97e3-104575b24ae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459228189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3459228189
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.394745670
Short name T683
Test name
Test status
Simulation time 1301308766 ps
CPU time 3.37 seconds
Started Jul 11 07:27:59 PM PDT 24
Finished Jul 11 07:28:03 PM PDT 24
Peak memory 205476 kb
Host smart-f76dbaf0-e193-4b7d-ac75-a27ad8c2ce74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394745670 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.394745670
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.942744069
Short name T1181
Test name
Test status
Simulation time 1811305524 ps
CPU time 1.17 seconds
Started Jul 11 07:27:59 PM PDT 24
Finished Jul 11 07:28:01 PM PDT 24
Peak memory 205396 kb
Host smart-b607685d-e54c-4704-9a2f-9dcf657fc2d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942744069 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.942744069
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.552313012
Short name T1031
Test name
Test status
Simulation time 7918258303 ps
CPU time 5.66 seconds
Started Jul 11 07:27:54 PM PDT 24
Finished Jul 11 07:28:01 PM PDT 24
Peak memory 213780 kb
Host smart-a71afe62-608c-49e2-af12-51a539cafbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552313012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.552313012
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3107109718
Short name T1327
Test name
Test status
Simulation time 2907923787 ps
CPU time 3.01 seconds
Started Jul 11 07:27:55 PM PDT 24
Finished Jul 11 07:27:59 PM PDT 24
Peak memory 205476 kb
Host smart-6f040c4d-8d6c-43ab-9a96-e60b8a8a7b3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107109718 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3107109718
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.1312773998
Short name T160
Test name
Test status
Simulation time 2364809338 ps
CPU time 2.91 seconds
Started Jul 11 07:27:58 PM PDT 24
Finished Jul 11 07:28:02 PM PDT 24
Peak memory 213756 kb
Host smart-497c86c9-7797-4d10-8321-24eb4d80a68e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312773998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.1312773998
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.2650645936
Short name T1503
Test name
Test status
Simulation time 513102416 ps
CPU time 2.6 seconds
Started Jul 11 07:28:09 PM PDT 24
Finished Jul 11 07:28:15 PM PDT 24
Peak memory 206148 kb
Host smart-1c516ffb-412d-417f-965c-b3cedd1e9118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650645936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.2650645936
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.2214812280
Short name T534
Test name
Test status
Simulation time 457281656 ps
CPU time 2.15 seconds
Started Jul 11 07:27:58 PM PDT 24
Finished Jul 11 07:28:01 PM PDT 24
Peak memory 205356 kb
Host smart-e3926263-0ff7-4082-ad68-6e40c8f76198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214812280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.2214812280
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3977942771
Short name T717
Test name
Test status
Simulation time 3510505115 ps
CPU time 27.4 seconds
Started Jul 11 07:27:53 PM PDT 24
Finished Jul 11 07:28:22 PM PDT 24
Peak memory 213780 kb
Host smart-6eeb57ad-fd59-41ee-ad27-38b6ec9599a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977942771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3977942771
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.350557220
Short name T256
Test name
Test status
Simulation time 1611250617 ps
CPU time 24.54 seconds
Started Jul 11 07:27:53 PM PDT 24
Finished Jul 11 07:28:19 PM PDT 24
Peak memory 229976 kb
Host smart-56770253-a572-40ff-8ac8-5c29b1c1f444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350557220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.350557220
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1553381593
Short name T668
Test name
Test status
Simulation time 48335062444 ps
CPU time 135.75 seconds
Started Jul 11 07:27:52 PM PDT 24
Finished Jul 11 07:30:10 PM PDT 24
Peak memory 1859908 kb
Host smart-b9877972-1606-471d-99a0-b0c722c598b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553381593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1553381593
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3663673795
Short name T292
Test name
Test status
Simulation time 2947794389 ps
CPU time 54.96 seconds
Started Jul 11 07:27:51 PM PDT 24
Finished Jul 11 07:28:47 PM PDT 24
Peak memory 483804 kb
Host smart-93e5ca35-c626-47c8-a609-bd64dbc71513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663673795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3663673795
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2087178989
Short name T303
Test name
Test status
Simulation time 1142052258 ps
CPU time 6.89 seconds
Started Jul 11 07:27:53 PM PDT 24
Finished Jul 11 07:28:01 PM PDT 24
Peak memory 220452 kb
Host smart-23475e39-6fc3-45f3-af8a-6cc2073b7289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087178989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2087178989
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.572430031
Short name T800
Test name
Test status
Simulation time 128438335 ps
CPU time 2.46 seconds
Started Jul 11 07:27:59 PM PDT 24
Finished Jul 11 07:28:04 PM PDT 24
Peak memory 205464 kb
Host smart-acbfa105-02bb-4b4c-8894-21cfc0c8d950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572430031 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.572430031
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3556918344
Short name T1463
Test name
Test status
Simulation time 26793615 ps
CPU time 0.63 seconds
Started Jul 11 07:28:16 PM PDT 24
Finished Jul 11 07:28:18 PM PDT 24
Peak memory 204668 kb
Host smart-fb39b61f-dad5-42a0-92bd-6cb15dda9a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556918344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3556918344
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4140177520
Short name T772
Test name
Test status
Simulation time 591442673 ps
CPU time 4.95 seconds
Started Jul 11 07:28:04 PM PDT 24
Finished Jul 11 07:28:14 PM PDT 24
Peak memory 217272 kb
Host smart-7a6c81de-95fc-48a3-ba26-6dc9a809bdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140177520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4140177520
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.289185432
Short name T1494
Test name
Test status
Simulation time 807872810 ps
CPU time 22.64 seconds
Started Jul 11 07:28:04 PM PDT 24
Finished Jul 11 07:28:31 PM PDT 24
Peak memory 292456 kb
Host smart-89f7dd08-38f0-42c3-9121-28c7e3af696a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289185432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.289185432
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2879851067
Short name T938
Test name
Test status
Simulation time 6668073087 ps
CPU time 51.78 seconds
Started Jul 11 07:28:05 PM PDT 24
Finished Jul 11 07:29:01 PM PDT 24
Peak memory 623676 kb
Host smart-5821bafa-bc21-41e8-9ce0-82462f872751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879851067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2879851067
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1508373406
Short name T988
Test name
Test status
Simulation time 7122227315 ps
CPU time 126.48 seconds
Started Jul 11 07:28:03 PM PDT 24
Finished Jul 11 07:30:15 PM PDT 24
Peak memory 630340 kb
Host smart-8e57ece5-c3d0-438e-b166-a4383af3ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508373406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1508373406
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3614702432
Short name T161
Test name
Test status
Simulation time 486705701 ps
CPU time 3.39 seconds
Started Jul 11 07:28:10 PM PDT 24
Finished Jul 11 07:28:16 PM PDT 24
Peak memory 205360 kb
Host smart-4fc5a5e0-c90c-4b16-ae3f-95c64a611d94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614702432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3614702432
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1241474958
Short name T1543
Test name
Test status
Simulation time 7240776939 ps
CPU time 68.26 seconds
Started Jul 11 07:28:03 PM PDT 24
Finished Jul 11 07:29:16 PM PDT 24
Peak memory 824976 kb
Host smart-1f85dca1-dd8f-4ea8-87c0-d52ffd07839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241474958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1241474958
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2955385749
Short name T686
Test name
Test status
Simulation time 1811441884 ps
CPU time 5.5 seconds
Started Jul 11 07:28:15 PM PDT 24
Finished Jul 11 07:28:23 PM PDT 24
Peak memory 205352 kb
Host smart-7688bd0f-16c9-41bb-b60c-dea90b5a02a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955385749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2955385749
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_perf.800527026
Short name T372
Test name
Test status
Simulation time 7046561364 ps
CPU time 69.4 seconds
Started Jul 11 07:28:03 PM PDT 24
Finished Jul 11 07:29:18 PM PDT 24
Peak memory 205404 kb
Host smart-69aaf676-a7b9-43a4-8eb8-ffd22a0dba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800527026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.800527026
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.3375997193
Short name T1037
Test name
Test status
Simulation time 23228564636 ps
CPU time 925.46 seconds
Started Jul 11 07:28:04 PM PDT 24
Finished Jul 11 07:43:35 PM PDT 24
Peak memory 213576 kb
Host smart-e1a155ea-a83c-4a83-8307-bbebb6fc0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375997193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3375997193
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.525268721
Short name T435
Test name
Test status
Simulation time 4916931071 ps
CPU time 18.45 seconds
Started Jul 11 07:28:05 PM PDT 24
Finished Jul 11 07:28:28 PM PDT 24
Peak memory 284928 kb
Host smart-4fc869df-2d31-4c04-b0cf-faa6856e519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525268721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.525268721
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3705426535
Short name T1340
Test name
Test status
Simulation time 18050010295 ps
CPU time 3510.4 seconds
Started Jul 11 07:28:04 PM PDT 24
Finished Jul 11 08:26:40 PM PDT 24
Peak memory 4145300 kb
Host smart-627b897a-5a83-4f91-a00e-28ae1fa48a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705426535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3705426535
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3093669722
Short name T298
Test name
Test status
Simulation time 1043896403 ps
CPU time 16.84 seconds
Started Jul 11 07:28:06 PM PDT 24
Finished Jul 11 07:28:27 PM PDT 24
Peak memory 229440 kb
Host smart-3a34187b-215c-4cfe-a9c1-8c2fb70baaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093669722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3093669722
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3428342309
Short name T932
Test name
Test status
Simulation time 3082023014 ps
CPU time 3.54 seconds
Started Jul 11 07:28:17 PM PDT 24
Finished Jul 11 07:28:23 PM PDT 24
Peak memory 213816 kb
Host smart-19eef8bf-2e64-47c2-a6be-929b8def9b5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428342309 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3428342309
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1388276368
Short name T1390
Test name
Test status
Simulation time 135161037 ps
CPU time 0.98 seconds
Started Jul 11 07:28:10 PM PDT 24
Finished Jul 11 07:28:13 PM PDT 24
Peak memory 205404 kb
Host smart-fafc2822-8458-448c-be1e-3f37e7d3b4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388276368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1388276368
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2521624706
Short name T1066
Test name
Test status
Simulation time 324163786 ps
CPU time 1.95 seconds
Started Jul 11 07:28:13 PM PDT 24
Finished Jul 11 07:28:16 PM PDT 24
Peak memory 213656 kb
Host smart-bce00119-4386-401f-ae45-27b0159a3b6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521624706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2521624706
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1947261233
Short name T1095
Test name
Test status
Simulation time 3023667083 ps
CPU time 2.67 seconds
Started Jul 11 07:28:17 PM PDT 24
Finished Jul 11 07:28:22 PM PDT 24
Peak memory 205532 kb
Host smart-7eb16276-0b44-4c1b-92e4-0861e1a9dc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947261233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1947261233
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2733135391
Short name T715
Test name
Test status
Simulation time 289669193 ps
CPU time 2.87 seconds
Started Jul 11 07:28:12 PM PDT 24
Finished Jul 11 07:28:16 PM PDT 24
Peak memory 213720 kb
Host smart-c23ada7b-8fd6-4d46-9476-99269f6e5bf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733135391 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2733135391
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.387829391
Short name T972
Test name
Test status
Simulation time 16194585087 ps
CPU time 27.72 seconds
Started Jul 11 07:28:09 PM PDT 24
Finished Jul 11 07:28:40 PM PDT 24
Peak memory 590780 kb
Host smart-322d999c-8228-41b0-a222-513a05a05c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387829391 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.387829391
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.585625001
Short name T47
Test name
Test status
Simulation time 607586740 ps
CPU time 2.98 seconds
Started Jul 11 07:28:14 PM PDT 24
Finished Jul 11 07:28:19 PM PDT 24
Peak memory 213668 kb
Host smart-b6ecfb11-9194-484e-a3a8-b2e6636aaf04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585625001 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_nack_acqfull.585625001
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.844060143
Short name T1134
Test name
Test status
Simulation time 1992887421 ps
CPU time 3.01 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:28:28 PM PDT 24
Peak memory 205432 kb
Host smart-71830669-0ff4-4974-8b9c-6717158e6a1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844060143 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.844060143
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.902886857
Short name T1039
Test name
Test status
Simulation time 1171310864 ps
CPU time 2.48 seconds
Started Jul 11 07:28:15 PM PDT 24
Finished Jul 11 07:28:19 PM PDT 24
Peak memory 205328 kb
Host smart-14d303ee-3437-40d4-86cd-2d326274d22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902886857 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_smbus_maxlen.902886857
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2001944871
Short name T311
Test name
Test status
Simulation time 3045324258 ps
CPU time 19.46 seconds
Started Jul 11 07:28:06 PM PDT 24
Finished Jul 11 07:28:29 PM PDT 24
Peak memory 213728 kb
Host smart-088de38d-0fd4-4741-b8af-0f48465e3c73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001944871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2001944871
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3599854580
Short name T1448
Test name
Test status
Simulation time 1605851846 ps
CPU time 13.57 seconds
Started Jul 11 07:28:12 PM PDT 24
Finished Jul 11 07:28:27 PM PDT 24
Peak memory 205496 kb
Host smart-9aceb2bf-bbac-4970-9a78-6c8527877c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599854580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3599854580
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2527060509
Short name T758
Test name
Test status
Simulation time 28727291272 ps
CPU time 62.58 seconds
Started Jul 11 07:28:10 PM PDT 24
Finished Jul 11 07:29:15 PM PDT 24
Peak memory 1015700 kb
Host smart-34016300-825c-42de-bcc4-83b1376dcb15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527060509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2527060509
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1327104823
Short name T861
Test name
Test status
Simulation time 4648310403 ps
CPU time 18.75 seconds
Started Jul 11 07:28:10 PM PDT 24
Finished Jul 11 07:28:31 PM PDT 24
Peak memory 438944 kb
Host smart-4bc0a4c9-18e4-4fcb-8a2d-4476b0ab363b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327104823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1327104823
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.321614340
Short name T584
Test name
Test status
Simulation time 1195546286 ps
CPU time 6.45 seconds
Started Jul 11 07:28:10 PM PDT 24
Finished Jul 11 07:28:19 PM PDT 24
Peak memory 221428 kb
Host smart-b64faa98-4daf-4d55-8be6-761a1fa18ae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321614340 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.321614340
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.984159429
Short name T947
Test name
Test status
Simulation time 231825524 ps
CPU time 3.27 seconds
Started Jul 11 07:28:16 PM PDT 24
Finished Jul 11 07:28:21 PM PDT 24
Peak memory 205408 kb
Host smart-0c905ef8-aadc-4e42-9a26-e5625ba2233f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984159429 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.984159429
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4127475366
Short name T1168
Test name
Test status
Simulation time 39161667 ps
CPU time 0.64 seconds
Started Jul 11 07:22:35 PM PDT 24
Finished Jul 11 07:22:36 PM PDT 24
Peak memory 204684 kb
Host smart-c3d21a6f-4833-4464-a726-b1b724439a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127475366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4127475366
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.4025693544
Short name T761
Test name
Test status
Simulation time 297892926 ps
CPU time 7.21 seconds
Started Jul 11 07:22:16 PM PDT 24
Finished Jul 11 07:22:24 PM PDT 24
Peak memory 235820 kb
Host smart-a607586b-d88e-4679-b74a-da20beadd3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025693544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4025693544
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1045358564
Short name T967
Test name
Test status
Simulation time 1620066932 ps
CPU time 10.49 seconds
Started Jul 11 07:22:12 PM PDT 24
Finished Jul 11 07:22:23 PM PDT 24
Peak memory 296560 kb
Host smart-5e00e2fd-8dcf-48f2-a4a0-8a515170d8d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045358564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1045358564
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1908827033
Short name T318
Test name
Test status
Simulation time 7629925121 ps
CPU time 41.84 seconds
Started Jul 11 07:22:11 PM PDT 24
Finished Jul 11 07:22:54 PM PDT 24
Peak memory 507492 kb
Host smart-4b55b555-f349-49b0-a54f-84e3a719459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908827033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1908827033
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.783293366
Short name T569
Test name
Test status
Simulation time 2995278204 ps
CPU time 56.95 seconds
Started Jul 11 07:22:08 PM PDT 24
Finished Jul 11 07:23:06 PM PDT 24
Peak memory 588704 kb
Host smart-51195408-d1e9-456e-aaa9-bfb18dfe0a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783293366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.783293366
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1588302863
Short name T1086
Test name
Test status
Simulation time 77803895 ps
CPU time 0.85 seconds
Started Jul 11 07:22:09 PM PDT 24
Finished Jul 11 07:22:10 PM PDT 24
Peak memory 205200 kb
Host smart-3cd81035-e30b-4351-a28b-0103ad43336f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588302863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1588302863
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3855294086
Short name T847
Test name
Test status
Simulation time 479513703 ps
CPU time 3.45 seconds
Started Jul 11 07:22:07 PM PDT 24
Finished Jul 11 07:22:11 PM PDT 24
Peak memory 224036 kb
Host smart-f5cac916-b9a5-4bb6-8aaa-d96d03632f16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855294086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3855294086
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1627797692
Short name T1038
Test name
Test status
Simulation time 22193915795 ps
CPU time 149.1 seconds
Started Jul 11 07:22:09 PM PDT 24
Finished Jul 11 07:24:38 PM PDT 24
Peak memory 816388 kb
Host smart-8e3488f5-ca67-453b-a9c5-e56b46592de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627797692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1627797692
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3584999942
Short name T1544
Test name
Test status
Simulation time 341336190 ps
CPU time 14.66 seconds
Started Jul 11 07:22:30 PM PDT 24
Finished Jul 11 07:22:46 PM PDT 24
Peak memory 205428 kb
Host smart-0c71a65e-ab74-4d04-846f-391d077243fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584999942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3584999942
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.2856542575
Short name T723
Test name
Test status
Simulation time 30232387 ps
CPU time 0.67 seconds
Started Jul 11 07:22:03 PM PDT 24
Finished Jul 11 07:22:05 PM PDT 24
Peak memory 205184 kb
Host smart-e3f08c95-d438-4da7-9511-3d5e9ea18309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856542575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2856542575
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2190662906
Short name T1344
Test name
Test status
Simulation time 7009655489 ps
CPU time 38.63 seconds
Started Jul 11 07:22:13 PM PDT 24
Finished Jul 11 07:22:52 PM PDT 24
Peak memory 598676 kb
Host smart-d7c3f6ed-fb7b-4a57-8152-714d07f01670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190662906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2190662906
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.3513469754
Short name T836
Test name
Test status
Simulation time 120178863 ps
CPU time 2.07 seconds
Started Jul 11 07:22:12 PM PDT 24
Finished Jul 11 07:22:15 PM PDT 24
Peak memory 213400 kb
Host smart-09929f63-0a65-4115-9bac-c94b4abbc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513469754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.3513469754
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4205629645
Short name T1113
Test name
Test status
Simulation time 1340761635 ps
CPU time 59.47 seconds
Started Jul 11 07:22:02 PM PDT 24
Finished Jul 11 07:23:02 PM PDT 24
Peak memory 245640 kb
Host smart-a09c9b0f-bbb1-443c-aa6f-8ec901086517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205629645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4205629645
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2323843858
Short name T1018
Test name
Test status
Simulation time 672350247 ps
CPU time 30.54 seconds
Started Jul 11 07:22:12 PM PDT 24
Finished Jul 11 07:22:43 PM PDT 24
Peak memory 213512 kb
Host smart-8cf597e1-ee20-4ae5-a1fc-d1a7c3eb35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323843858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2323843858
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2529889549
Short name T184
Test name
Test status
Simulation time 65427952 ps
CPU time 1 seconds
Started Jul 11 07:22:37 PM PDT 24
Finished Jul 11 07:22:39 PM PDT 24
Peak memory 223548 kb
Host smart-c5b6a5c7-c433-4c74-bb63-6a30e9d8571f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529889549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2529889549
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2617270762
Short name T404
Test name
Test status
Simulation time 1213356401 ps
CPU time 6.42 seconds
Started Jul 11 07:22:29 PM PDT 24
Finished Jul 11 07:22:36 PM PDT 24
Peak memory 221820 kb
Host smart-e78e999c-8dcf-4134-bf12-5a4446fec645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617270762 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2617270762
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2007760602
Short name T1400
Test name
Test status
Simulation time 709312202 ps
CPU time 1.71 seconds
Started Jul 11 07:22:22 PM PDT 24
Finished Jul 11 07:22:25 PM PDT 24
Peak memory 205424 kb
Host smart-332aa1e1-3c86-4ee3-a26c-e62b2f030395
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007760602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2007760602
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3180553235
Short name T1461
Test name
Test status
Simulation time 369946007 ps
CPU time 1.66 seconds
Started Jul 11 07:22:21 PM PDT 24
Finished Jul 11 07:22:24 PM PDT 24
Peak memory 205484 kb
Host smart-bddf70e7-9dd8-4839-be0b-c9f302176cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180553235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3180553235
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2222850113
Short name T560
Test name
Test status
Simulation time 533174322 ps
CPU time 2.99 seconds
Started Jul 11 07:22:33 PM PDT 24
Finished Jul 11 07:22:37 PM PDT 24
Peak memory 205452 kb
Host smart-4a16768a-f13c-4d6c-b242-41eb00d960e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222850113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2222850113
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.4028142657
Short name T762
Test name
Test status
Simulation time 100360303 ps
CPU time 1.08 seconds
Started Jul 11 07:22:35 PM PDT 24
Finished Jul 11 07:22:37 PM PDT 24
Peak memory 205396 kb
Host smart-44f45787-9dda-4756-a9e1-7fc3e7d37c4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028142657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.4028142657
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.998185471
Short name T455
Test name
Test status
Simulation time 1397393368 ps
CPU time 4.06 seconds
Started Jul 11 07:22:22 PM PDT 24
Finished Jul 11 07:22:28 PM PDT 24
Peak memory 213724 kb
Host smart-d24eb0ee-e482-4f74-86f9-1af8bdabf416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998185471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.998185471
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.518805842
Short name T1184
Test name
Test status
Simulation time 19466162373 ps
CPU time 45.47 seconds
Started Jul 11 07:22:22 PM PDT 24
Finished Jul 11 07:23:08 PM PDT 24
Peak memory 813644 kb
Host smart-554a7068-6993-45df-a0b7-af24327d89ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518805842 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.518805842
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3021713678
Short name T1330
Test name
Test status
Simulation time 990149198 ps
CPU time 2.59 seconds
Started Jul 11 07:22:31 PM PDT 24
Finished Jul 11 07:22:35 PM PDT 24
Peak memory 205444 kb
Host smart-c3ca7d0c-35a4-48a8-9dc2-f1650814cdbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021713678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3021713678
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.3592609772
Short name T1384
Test name
Test status
Simulation time 1913368499 ps
CPU time 2.26 seconds
Started Jul 11 07:22:30 PM PDT 24
Finished Jul 11 07:22:34 PM PDT 24
Peak memory 205312 kb
Host smart-488a500b-4cfd-4949-83aa-1df5414eb6c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592609772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.3592609772
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2174257986
Short name T309
Test name
Test status
Simulation time 2365507663 ps
CPU time 19.23 seconds
Started Jul 11 07:22:17 PM PDT 24
Finished Jul 11 07:22:38 PM PDT 24
Peak memory 213764 kb
Host smart-73112054-1db1-4bae-9fe0-2e31af601512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174257986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2174257986
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.584746899
Short name T51
Test name
Test status
Simulation time 25492909877 ps
CPU time 18.8 seconds
Started Jul 11 07:22:16 PM PDT 24
Finished Jul 11 07:22:36 PM PDT 24
Peak memory 422556 kb
Host smart-db0d92db-7b09-43b2-a29a-0211d405c7f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584746899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.584746899
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2566993527
Short name T489
Test name
Test status
Simulation time 3815457313 ps
CPU time 55.8 seconds
Started Jul 11 07:22:18 PM PDT 24
Finished Jul 11 07:23:15 PM PDT 24
Peak memory 1030284 kb
Host smart-7749ecb3-9090-448f-b967-435eafd75780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566993527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2566993527
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3824707898
Short name T266
Test name
Test status
Simulation time 1152486517 ps
CPU time 6.5 seconds
Started Jul 11 07:22:23 PM PDT 24
Finished Jul 11 07:22:30 PM PDT 24
Peak memory 230092 kb
Host smart-9f0a1b84-e096-4454-9c4f-8218e353f480
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824707898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3824707898
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.1275970162
Short name T378
Test name
Test status
Simulation time 130350083 ps
CPU time 1.85 seconds
Started Jul 11 07:22:31 PM PDT 24
Finished Jul 11 07:22:34 PM PDT 24
Peak memory 221228 kb
Host smart-73a4ee95-e3d5-4201-9f81-cf6c127a27a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275970162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.1275970162
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3265125867
Short name T447
Test name
Test status
Simulation time 28713902 ps
CPU time 0.69 seconds
Started Jul 11 07:28:35 PM PDT 24
Finished Jul 11 07:28:37 PM PDT 24
Peak memory 204788 kb
Host smart-8139df23-8aa4-4f10-aadf-1b386c1cdaa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265125867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3265125867
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1074645272
Short name T18
Test name
Test status
Simulation time 156312496 ps
CPU time 1.42 seconds
Started Jul 11 07:28:20 PM PDT 24
Finished Jul 11 07:28:25 PM PDT 24
Peak memory 213648 kb
Host smart-128366d4-ad16-4578-83f8-dfa8146a33c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074645272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1074645272
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3282776298
Short name T664
Test name
Test status
Simulation time 497867805 ps
CPU time 12.03 seconds
Started Jul 11 07:28:20 PM PDT 24
Finished Jul 11 07:28:34 PM PDT 24
Peak memory 319660 kb
Host smart-c7ec4544-9d34-461b-ac89-611f9d6f0adc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282776298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3282776298
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2338141037
Short name T79
Test name
Test status
Simulation time 5449461174 ps
CPU time 181.17 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:31:25 PM PDT 24
Peak memory 632108 kb
Host smart-bca7bd31-c131-4756-8e39-fb4905587c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338141037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2338141037
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3628366004
Short name T970
Test name
Test status
Simulation time 2490302897 ps
CPU time 188.89 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:31:33 PM PDT 24
Peak memory 774160 kb
Host smart-7beaadd2-0e1e-41ea-9f96-cb45f617801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628366004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3628366004
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2717193083
Short name T1166
Test name
Test status
Simulation time 679899722 ps
CPU time 0.97 seconds
Started Jul 11 07:28:22 PM PDT 24
Finished Jul 11 07:28:26 PM PDT 24
Peak memory 205192 kb
Host smart-77c21438-6fbf-4181-ae4d-d81704381afb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717193083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2717193083
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2034978366
Short name T791
Test name
Test status
Simulation time 962225677 ps
CPU time 4.69 seconds
Started Jul 11 07:28:20 PM PDT 24
Finished Jul 11 07:28:28 PM PDT 24
Peak memory 237760 kb
Host smart-cd8673d7-cf04-4354-8f2b-5dc5702521c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034978366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2034978366
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1889936689
Short name T878
Test name
Test status
Simulation time 5180813923 ps
CPU time 181.03 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:31:25 PM PDT 24
Peak memory 869588 kb
Host smart-62b46e29-8bab-4827-be50-ae8f8ab65eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889936689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1889936689
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2586912854
Short name T241
Test name
Test status
Simulation time 3926126687 ps
CPU time 22.7 seconds
Started Jul 11 07:28:29 PM PDT 24
Finished Jul 11 07:28:54 PM PDT 24
Peak memory 205404 kb
Host smart-62839c1e-1080-4c33-9e3f-e232800d5cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586912854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2586912854
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_override.3008785874
Short name T128
Test name
Test status
Simulation time 81487231 ps
CPU time 0.66 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:28:24 PM PDT 24
Peak memory 205116 kb
Host smart-0ed2c2f3-6119-43cb-a35d-b46c40de50dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008785874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3008785874
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3223164568
Short name T35
Test name
Test status
Simulation time 2654921992 ps
CPU time 116.07 seconds
Started Jul 11 07:28:22 PM PDT 24
Finished Jul 11 07:30:21 PM PDT 24
Peak memory 283968 kb
Host smart-6133a4bb-c749-43d9-927e-63cbc6ad6e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223164568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3223164568
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2351810447
Short name T611
Test name
Test status
Simulation time 160937968 ps
CPU time 1.07 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:28:24 PM PDT 24
Peak memory 222676 kb
Host smart-5359c712-ec99-426b-b7af-900699dabcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351810447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2351810447
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.850384064
Short name T941
Test name
Test status
Simulation time 2503314457 ps
CPU time 94.72 seconds
Started Jul 11 07:28:19 PM PDT 24
Finished Jul 11 07:29:55 PM PDT 24
Peak memory 379456 kb
Host smart-01fbf677-d28c-4984-b655-0398e7a87e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850384064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.850384064
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1939915919
Short name T449
Test name
Test status
Simulation time 2716800455 ps
CPU time 31.7 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:28:55 PM PDT 24
Peak memory 213676 kb
Host smart-ec024f05-8ab0-4a80-939a-eecfa9ea9023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939915919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1939915919
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3386838582
Short name T356
Test name
Test status
Simulation time 3804532888 ps
CPU time 4.06 seconds
Started Jul 11 07:28:28 PM PDT 24
Finished Jul 11 07:28:34 PM PDT 24
Peak memory 213760 kb
Host smart-111ce462-daca-41c9-a976-72393cff194d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386838582 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3386838582
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1792796247
Short name T1103
Test name
Test status
Simulation time 170828965 ps
CPU time 1.2 seconds
Started Jul 11 07:28:30 PM PDT 24
Finished Jul 11 07:28:32 PM PDT 24
Peak memory 213680 kb
Host smart-5accf8b9-4fc9-4aae-ba7f-ae3c6953a303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792796247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1792796247
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3292846375
Short name T615
Test name
Test status
Simulation time 1183824216 ps
CPU time 3.21 seconds
Started Jul 11 07:28:28 PM PDT 24
Finished Jul 11 07:28:33 PM PDT 24
Peak memory 205524 kb
Host smart-50ed784a-10e1-4546-abfd-1cfb38028315
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292846375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3292846375
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.2545446217
Short name T1007
Test name
Test status
Simulation time 152006967 ps
CPU time 1.26 seconds
Started Jul 11 07:28:35 PM PDT 24
Finished Jul 11 07:28:38 PM PDT 24
Peak memory 205384 kb
Host smart-1736878d-8e52-4dc8-a428-65c9cb9864c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545446217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.2545446217
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2989481299
Short name T471
Test name
Test status
Simulation time 1464633455 ps
CPU time 5.21 seconds
Started Jul 11 07:28:20 PM PDT 24
Finished Jul 11 07:28:28 PM PDT 24
Peak memory 213924 kb
Host smart-489cf4e1-94cc-43db-b382-4a7e01ed8c0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989481299 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2989481299
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4278499663
Short name T267
Test name
Test status
Simulation time 18296702986 ps
CPU time 91.87 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:29:56 PM PDT 24
Peak memory 1493868 kb
Host smart-72643acc-bb90-41d4-9b61-dea404f593c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278499663 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4278499663
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.4046275110
Short name T1263
Test name
Test status
Simulation time 542355643 ps
CPU time 3.03 seconds
Started Jul 11 07:28:33 PM PDT 24
Finished Jul 11 07:28:37 PM PDT 24
Peak memory 213704 kb
Host smart-c0f946bf-541b-4da3-a0a9-c7fd8db879c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046275110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.4046275110
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.2435402410
Short name T698
Test name
Test status
Simulation time 484227665 ps
CPU time 2.6 seconds
Started Jul 11 07:28:36 PM PDT 24
Finished Jul 11 07:28:40 PM PDT 24
Peak memory 205496 kb
Host smart-2f6b0b8c-c1c1-4deb-9b7b-07e85e7c3e91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435402410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.2435402410
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.917437822
Short name T1490
Test name
Test status
Simulation time 1772172780 ps
CPU time 2.18 seconds
Started Jul 11 07:28:33 PM PDT 24
Finished Jul 11 07:28:36 PM PDT 24
Peak memory 205372 kb
Host smart-8f7eb98a-69f4-4d9c-89ed-21944e6fda80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917437822 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_smbus_maxlen.917437822
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3957044127
Short name T1407
Test name
Test status
Simulation time 1000801381 ps
CPU time 15.33 seconds
Started Jul 11 07:28:22 PM PDT 24
Finished Jul 11 07:28:40 PM PDT 24
Peak memory 213668 kb
Host smart-be04d4e6-693a-4947-9c26-a4ac84554fcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957044127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3957044127
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2898455461
Short name T1281
Test name
Test status
Simulation time 474384691 ps
CPU time 21.66 seconds
Started Jul 11 07:28:22 PM PDT 24
Finished Jul 11 07:28:47 PM PDT 24
Peak memory 205472 kb
Host smart-6ef447d8-60e4-49be-9f02-2913ed1f2230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898455461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2898455461
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3245341501
Short name T868
Test name
Test status
Simulation time 28818618739 ps
CPU time 182.06 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:31:27 PM PDT 24
Peak memory 2264120 kb
Host smart-827595fa-432d-49ca-9ad2-8a046308d158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245341501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3245341501
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3546453907
Short name T285
Test name
Test status
Simulation time 2435278321 ps
CPU time 27.6 seconds
Started Jul 11 07:28:21 PM PDT 24
Finished Jul 11 07:28:51 PM PDT 24
Peak memory 333912 kb
Host smart-bda63524-642b-4ef7-b9d2-be8573117d5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546453907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3546453907
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3186901308
Short name T876
Test name
Test status
Simulation time 1219427957 ps
CPU time 7.23 seconds
Started Jul 11 07:28:20 PM PDT 24
Finished Jul 11 07:28:29 PM PDT 24
Peak memory 213688 kb
Host smart-9e42fa46-ef90-496a-8000-b985184fc219
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186901308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3186901308
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3044171310
Short name T506
Test name
Test status
Simulation time 61082418 ps
CPU time 0.65 seconds
Started Jul 11 07:28:52 PM PDT 24
Finished Jul 11 07:28:55 PM PDT 24
Peak memory 204756 kb
Host smart-ec1b439b-4d22-4236-85ad-bc037e445182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044171310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3044171310
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.4098762500
Short name T1460
Test name
Test status
Simulation time 960781130 ps
CPU time 9.65 seconds
Started Jul 11 07:28:45 PM PDT 24
Finished Jul 11 07:28:56 PM PDT 24
Peak memory 246232 kb
Host smart-2867005a-1dbd-4578-bf11-ae2f881a7268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098762500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.4098762500
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2665932332
Short name T358
Test name
Test status
Simulation time 1392206801 ps
CPU time 8.54 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:28:49 PM PDT 24
Peak memory 291808 kb
Host smart-30e18c3c-7495-4305-9b57-6aa48c0ec748
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665932332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2665932332
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2117044738
Short name T81
Test name
Test status
Simulation time 1621111059 ps
CPU time 88.31 seconds
Started Jul 11 07:28:44 PM PDT 24
Finished Jul 11 07:30:13 PM PDT 24
Peak memory 510852 kb
Host smart-0730da06-ad02-4671-aa88-c02ffac5b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117044738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2117044738
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3433064822
Short name T688
Test name
Test status
Simulation time 1875238213 ps
CPU time 56.94 seconds
Started Jul 11 07:28:40 PM PDT 24
Finished Jul 11 07:29:38 PM PDT 24
Peak memory 651844 kb
Host smart-0bc4af6b-c511-406c-8b4e-d14ae6012037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433064822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3433064822
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.731090407
Short name T953
Test name
Test status
Simulation time 780817917 ps
CPU time 1.05 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:28:42 PM PDT 24
Peak memory 205196 kb
Host smart-ea3a247a-8c5e-4be6-b11f-1c5335659160
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731090407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.731090407
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1957572778
Short name T850
Test name
Test status
Simulation time 296551186 ps
CPU time 4.53 seconds
Started Jul 11 07:28:41 PM PDT 24
Finished Jul 11 07:28:47 PM PDT 24
Peak memory 229280 kb
Host smart-ababef79-3581-4513-9def-753b6e26f4ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957572778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1957572778
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.4079110753
Short name T1252
Test name
Test status
Simulation time 3734527381 ps
CPU time 234.36 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:32:35 PM PDT 24
Peak memory 1069492 kb
Host smart-992afe4e-7718-48c9-84d2-f90bca1192ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079110753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.4079110753
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_override.3974970481
Short name T568
Test name
Test status
Simulation time 82429286 ps
CPU time 0.68 seconds
Started Jul 11 07:28:35 PM PDT 24
Finished Jul 11 07:28:37 PM PDT 24
Peak memory 205168 kb
Host smart-2514dcc6-7ea4-4f6f-88c7-f2499bc04ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974970481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3974970481
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1414252917
Short name T421
Test name
Test status
Simulation time 25985765971 ps
CPU time 114.44 seconds
Started Jul 11 07:28:41 PM PDT 24
Finished Jul 11 07:30:36 PM PDT 24
Peak memory 751392 kb
Host smart-e026af71-91b3-4070-a520-6daccfee4e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414252917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1414252917
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.2318312574
Short name T1260
Test name
Test status
Simulation time 23502390416 ps
CPU time 460.84 seconds
Started Jul 11 07:28:40 PM PDT 24
Finished Jul 11 07:36:23 PM PDT 24
Peak memory 1495168 kb
Host smart-dfe9d742-66ed-4b3b-8e06-37796a73d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318312574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.2318312574
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2258760567
Short name T1282
Test name
Test status
Simulation time 4035865569 ps
CPU time 36.31 seconds
Started Jul 11 07:28:35 PM PDT 24
Finished Jul 11 07:29:13 PM PDT 24
Peak memory 406228 kb
Host smart-116ce1e6-a110-40be-9dc9-992285740635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258760567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2258760567
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.47702158
Short name T790
Test name
Test status
Simulation time 1046452780 ps
CPU time 10.76 seconds
Started Jul 11 07:28:40 PM PDT 24
Finished Jul 11 07:28:52 PM PDT 24
Peak memory 221236 kb
Host smart-b0d2eb8b-a4bb-48e0-926e-33c9b386cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47702158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.47702158
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2085280358
Short name T425
Test name
Test status
Simulation time 4213381312 ps
CPU time 7.02 seconds
Started Jul 11 07:28:45 PM PDT 24
Finished Jul 11 07:28:53 PM PDT 24
Peak memory 213816 kb
Host smart-5a2672b0-195f-4274-970c-01042282be86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085280358 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2085280358
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.858451787
Short name T1433
Test name
Test status
Simulation time 728491453 ps
CPU time 1.24 seconds
Started Jul 11 07:28:46 PM PDT 24
Finished Jul 11 07:28:48 PM PDT 24
Peak memory 205456 kb
Host smart-05c0c0cc-cf1c-411e-84de-c6e64b8a8151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858451787 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.858451787
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.2276425083
Short name T1255
Test name
Test status
Simulation time 966805549 ps
CPU time 1.55 seconds
Started Jul 11 07:28:52 PM PDT 24
Finished Jul 11 07:28:56 PM PDT 24
Peak memory 205392 kb
Host smart-43a9f8b1-b6c5-46b2-b508-f1acae87df16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276425083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.2276425083
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1867470353
Short name T338
Test name
Test status
Simulation time 604965907 ps
CPU time 1.41 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:28:54 PM PDT 24
Peak memory 205384 kb
Host smart-73cf686d-7c2b-498f-9e20-8aedb08bc08f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867470353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1867470353
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3311224025
Short name T748
Test name
Test status
Simulation time 1795295823 ps
CPU time 6.52 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:28:47 PM PDT 24
Peak memory 218576 kb
Host smart-f4f1c175-39c7-411b-b891-b9a0e8a9ee8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311224025 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3311224025
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1287961627
Short name T1371
Test name
Test status
Simulation time 8990192629 ps
CPU time 13.72 seconds
Started Jul 11 07:28:44 PM PDT 24
Finished Jul 11 07:28:59 PM PDT 24
Peak memory 317396 kb
Host smart-f2005363-4022-41ce-bf61-79bc060009fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287961627 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1287961627
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.3282015493
Short name T623
Test name
Test status
Simulation time 2261451729 ps
CPU time 2.62 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:28:54 PM PDT 24
Peak memory 213772 kb
Host smart-47fafcf8-9036-46fe-807e-4379bac928a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282015493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.3282015493
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.4131367096
Short name T382
Test name
Test status
Simulation time 472773522 ps
CPU time 2.51 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:28:55 PM PDT 24
Peak memory 205484 kb
Host smart-81217c4c-4cf0-461f-b45d-8cad0539f2d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131367096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.4131367096
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.542552120
Short name T914
Test name
Test status
Simulation time 957368892 ps
CPU time 2.19 seconds
Started Jul 11 07:28:54 PM PDT 24
Finished Jul 11 07:28:58 PM PDT 24
Peak memory 205340 kb
Host smart-933da62b-727a-4c7e-8d8c-29b1877ba030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542552120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_smbus_maxlen.542552120
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.22249607
Short name T1160
Test name
Test status
Simulation time 3198173657 ps
CPU time 12.51 seconds
Started Jul 11 07:28:45 PM PDT 24
Finished Jul 11 07:28:58 PM PDT 24
Peak memory 213740 kb
Host smart-fdd262cb-078f-4f34-bfba-e1824f269a54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22249607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_targ
et_smoke.22249607
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3916697271
Short name T1428
Test name
Test status
Simulation time 415850820 ps
CPU time 7.04 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:28:47 PM PDT 24
Peak memory 206032 kb
Host smart-f373e51c-b03b-4733-b06c-802754a32453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916697271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3916697271
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4082586874
Short name T363
Test name
Test status
Simulation time 56880230965 ps
CPU time 75.62 seconds
Started Jul 11 07:28:38 PM PDT 24
Finished Jul 11 07:29:54 PM PDT 24
Peak memory 1187668 kb
Host smart-878d5622-a984-482b-bd29-319817764da0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082586874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4082586874
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2576959282
Short name T1426
Test name
Test status
Simulation time 1727410751 ps
CPU time 1 seconds
Started Jul 11 07:28:39 PM PDT 24
Finished Jul 11 07:28:41 PM PDT 24
Peak memory 205388 kb
Host smart-4db86e55-0d7f-4122-a4ec-3049182a77f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576959282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2576959282
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2475277858
Short name T964
Test name
Test status
Simulation time 1123790524 ps
CPU time 6.72 seconds
Started Jul 11 07:28:44 PM PDT 24
Finished Jul 11 07:28:51 PM PDT 24
Peak memory 218408 kb
Host smart-3e1ee9e6-9649-4e6a-ae38-1a677d185780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475277858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2475277858
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.807439348
Short name T783
Test name
Test status
Simulation time 816320935 ps
CPU time 11.61 seconds
Started Jul 11 07:28:53 PM PDT 24
Finished Jul 11 07:29:06 PM PDT 24
Peak memory 206652 kb
Host smart-162a0d2d-3121-4d26-b916-9a7109b78400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807439348 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.807439348
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.4027614532
Short name T1122
Test name
Test status
Simulation time 52499079 ps
CPU time 0.66 seconds
Started Jul 11 07:29:04 PM PDT 24
Finished Jul 11 07:29:08 PM PDT 24
Peak memory 204644 kb
Host smart-7858c231-e982-437a-82da-fe5bc40c790b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027614532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.4027614532
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1768672773
Short name T1069
Test name
Test status
Simulation time 578725017 ps
CPU time 3.13 seconds
Started Jul 11 07:28:57 PM PDT 24
Finished Jul 11 07:29:03 PM PDT 24
Peak memory 229908 kb
Host smart-d70cf101-34ba-4421-b5ac-e3e2f72b26c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768672773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1768672773
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.658648370
Short name T718
Test name
Test status
Simulation time 191599470 ps
CPU time 3.71 seconds
Started Jul 11 07:28:51 PM PDT 24
Finished Jul 11 07:28:57 PM PDT 24
Peak memory 239984 kb
Host smart-fae91540-5132-4fed-8bb0-9c9e6aa45a1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658648370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.658648370
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2663413307
Short name T605
Test name
Test status
Simulation time 4337144377 ps
CPU time 73.53 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:30:06 PM PDT 24
Peak memory 680800 kb
Host smart-c2892c45-74f7-4800-aaf9-de755457e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663413307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2663413307
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2186088055
Short name T637
Test name
Test status
Simulation time 9514504095 ps
CPU time 139.47 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:31:11 PM PDT 24
Peak memory 557768 kb
Host smart-c23bdae5-0edf-4dd4-b29d-0f8ab085af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186088055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2186088055
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3895263380
Short name T1474
Test name
Test status
Simulation time 113539512 ps
CPU time 1.08 seconds
Started Jul 11 07:28:52 PM PDT 24
Finished Jul 11 07:28:56 PM PDT 24
Peak memory 205172 kb
Host smart-1353187e-0c32-4378-887c-ddf211bf2b14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895263380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3895263380
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1129376431
Short name T1320
Test name
Test status
Simulation time 158789571 ps
CPU time 3.14 seconds
Started Jul 11 07:28:52 PM PDT 24
Finished Jul 11 07:28:57 PM PDT 24
Peak memory 205396 kb
Host smart-585bd913-616e-4cf4-8549-96bbc2d52df4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129376431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1129376431
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4107754467
Short name T107
Test name
Test status
Simulation time 5119317839 ps
CPU time 117.97 seconds
Started Jul 11 07:28:51 PM PDT 24
Finished Jul 11 07:30:51 PM PDT 24
Peak memory 1336740 kb
Host smart-f8cf1523-3a1d-447c-a170-f28622458cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107754467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4107754467
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.4128647562
Short name T873
Test name
Test status
Simulation time 990014236 ps
CPU time 6.7 seconds
Started Jul 11 07:29:04 PM PDT 24
Finished Jul 11 07:29:15 PM PDT 24
Peak memory 205332 kb
Host smart-bbc5489e-72f6-4356-9e56-65c968f5e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128647562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.4128647562
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.3565451796
Short name T870
Test name
Test status
Simulation time 25879869 ps
CPU time 0.75 seconds
Started Jul 11 07:28:50 PM PDT 24
Finished Jul 11 07:28:52 PM PDT 24
Peak memory 205140 kb
Host smart-a70ad5d3-2687-474f-9873-eabb559dfe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565451796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3565451796
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.178046591
Short name T1284
Test name
Test status
Simulation time 5612369173 ps
CPU time 13.57 seconds
Started Jul 11 07:28:56 PM PDT 24
Finished Jul 11 07:29:13 PM PDT 24
Peak memory 336152 kb
Host smart-7acdffc0-638c-4114-85f1-292f0198cbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178046591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.178046591
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.2192582349
Short name T513
Test name
Test status
Simulation time 6105535100 ps
CPU time 230.38 seconds
Started Jul 11 07:28:56 PM PDT 24
Finished Jul 11 07:32:49 PM PDT 24
Peak memory 1544624 kb
Host smart-8f7e1d3f-5bbb-4356-9328-96f7f03a7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192582349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.2192582349
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2488533886
Short name T1455
Test name
Test status
Simulation time 1903596919 ps
CPU time 36.97 seconds
Started Jul 11 07:28:55 PM PDT 24
Finished Jul 11 07:29:34 PM PDT 24
Peak memory 346820 kb
Host smart-a182fafd-f09c-4dcf-b222-eca9c39eee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488533886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2488533886
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.4245091639
Short name T1348
Test name
Test status
Simulation time 598191912 ps
CPU time 26.43 seconds
Started Jul 11 07:28:58 PM PDT 24
Finished Jul 11 07:29:27 PM PDT 24
Peak memory 213592 kb
Host smart-29337adb-2cda-4d33-817e-e8e04f5f0c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245091639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.4245091639
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.4145386567
Short name T1167
Test name
Test status
Simulation time 1121834784 ps
CPU time 6.09 seconds
Started Jul 11 07:29:07 PM PDT 24
Finished Jul 11 07:29:16 PM PDT 24
Peak memory 218152 kb
Host smart-373eea29-6fda-4307-9ff2-3c5190e8faa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145386567 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.4145386567
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3839090481
Short name T965
Test name
Test status
Simulation time 225103712 ps
CPU time 1.51 seconds
Started Jul 11 07:28:56 PM PDT 24
Finished Jul 11 07:29:01 PM PDT 24
Peak memory 205432 kb
Host smart-7fec09b4-9dfa-4200-8ef7-8363fd13d937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839090481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3839090481
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3164997194
Short name T648
Test name
Test status
Simulation time 262196319 ps
CPU time 1.68 seconds
Started Jul 11 07:29:00 PM PDT 24
Finished Jul 11 07:29:04 PM PDT 24
Peak memory 205472 kb
Host smart-7af9d797-6860-4ebd-b7af-c1e518247c2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164997194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3164997194
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.3428968774
Short name T976
Test name
Test status
Simulation time 931331491 ps
CPU time 1.51 seconds
Started Jul 11 07:29:02 PM PDT 24
Finished Jul 11 07:29:06 PM PDT 24
Peak memory 205336 kb
Host smart-10bee149-5642-4385-8a82-e25d1c991ae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428968774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.3428968774
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2904831922
Short name T544
Test name
Test status
Simulation time 557807064 ps
CPU time 1.58 seconds
Started Jul 11 07:29:02 PM PDT 24
Finished Jul 11 07:29:06 PM PDT 24
Peak memory 205404 kb
Host smart-58f18ff1-e6da-45dd-9c70-d99d4e6f7272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904831922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2904831922
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.78958569
Short name T968
Test name
Test status
Simulation time 4129474975 ps
CPU time 6.26 seconds
Started Jul 11 07:29:02 PM PDT 24
Finished Jul 11 07:29:12 PM PDT 24
Peak memory 215576 kb
Host smart-2ae5653a-121d-46f3-b2dd-dde349a51f75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78958569 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.78958569
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3351208732
Short name T1485
Test name
Test status
Simulation time 17219482428 ps
CPU time 252.13 seconds
Started Jul 11 07:29:02 PM PDT 24
Finished Jul 11 07:33:19 PM PDT 24
Peak memory 2673684 kb
Host smart-7b41e559-30e4-439a-8a60-d73da4ad1c4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351208732 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3351208732
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.1035313476
Short name T59
Test name
Test status
Simulation time 1156666396 ps
CPU time 2.9 seconds
Started Jul 11 07:29:03 PM PDT 24
Finished Jul 11 07:29:10 PM PDT 24
Peak memory 213648 kb
Host smart-61caec32-f293-44ac-ad72-091b030787da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035313476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.1035313476
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.811333714
Short name T1353
Test name
Test status
Simulation time 982609343 ps
CPU time 2.4 seconds
Started Jul 11 07:29:04 PM PDT 24
Finished Jul 11 07:29:11 PM PDT 24
Peak memory 205460 kb
Host smart-ca68f107-6f25-4176-9106-506141c191c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811333714 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.811333714
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.539215156
Short name T1538
Test name
Test status
Simulation time 1680463971 ps
CPU time 2.09 seconds
Started Jul 11 07:29:04 PM PDT 24
Finished Jul 11 07:29:09 PM PDT 24
Peak memory 205380 kb
Host smart-70410486-0120-493d-92ea-f77e6e096050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539215156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_smbus_maxlen.539215156
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1728338039
Short name T406
Test name
Test status
Simulation time 2345604529 ps
CPU time 19.91 seconds
Started Jul 11 07:28:57 PM PDT 24
Finished Jul 11 07:29:20 PM PDT 24
Peak memory 213816 kb
Host smart-da980c7e-3fc8-4a36-9c34-55dd7ef362f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728338039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1728338039
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2123874922
Short name T1156
Test name
Test status
Simulation time 3138038228 ps
CPU time 28.86 seconds
Started Jul 11 07:28:56 PM PDT 24
Finished Jul 11 07:29:28 PM PDT 24
Peak memory 230656 kb
Host smart-fa163a3a-30ee-4cac-86c6-8470a5759ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123874922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2123874922
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.816501168
Short name T1244
Test name
Test status
Simulation time 62833810248 ps
CPU time 2714.97 seconds
Started Jul 11 07:28:57 PM PDT 24
Finished Jul 11 08:14:15 PM PDT 24
Peak memory 10567936 kb
Host smart-961606d2-ffd4-421f-9fdf-c60863ab85a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816501168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.816501168
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3057787452
Short name T1442
Test name
Test status
Simulation time 5485323654 ps
CPU time 14.4 seconds
Started Jul 11 07:28:57 PM PDT 24
Finished Jul 11 07:29:14 PM PDT 24
Peak memory 486296 kb
Host smart-1f3d2718-d5fa-4754-a2be-54fbae8fa882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057787452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3057787452
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2622819791
Short name T1109
Test name
Test status
Simulation time 3434418872 ps
CPU time 8.67 seconds
Started Jul 11 07:28:58 PM PDT 24
Finished Jul 11 07:29:10 PM PDT 24
Peak memory 230152 kb
Host smart-e761fc59-78b1-4585-8ea2-82fc8a7739c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622819791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2622819791
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.2564635132
Short name T1179
Test name
Test status
Simulation time 207323420 ps
CPU time 2.92 seconds
Started Jul 11 07:29:03 PM PDT 24
Finished Jul 11 07:29:10 PM PDT 24
Peak memory 205484 kb
Host smart-d7068d53-d33d-42b8-ab8a-9a277fb74b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564635132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.2564635132
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3963508860
Short name T672
Test name
Test status
Simulation time 18961661 ps
CPU time 0.67 seconds
Started Jul 11 07:29:19 PM PDT 24
Finished Jul 11 07:29:22 PM PDT 24
Peak memory 204816 kb
Host smart-65b55f3e-6815-463c-a0b7-f8c88b416f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963508860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3963508860
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2775492943
Short name T1129
Test name
Test status
Simulation time 56901488 ps
CPU time 1.19 seconds
Started Jul 11 07:29:10 PM PDT 24
Finished Jul 11 07:29:14 PM PDT 24
Peak memory 213612 kb
Host smart-06f76df9-70c8-4fa7-b0ea-e04a66412f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775492943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2775492943
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2637070943
Short name T1540
Test name
Test status
Simulation time 3398703738 ps
CPU time 25.57 seconds
Started Jul 11 07:29:10 PM PDT 24
Finished Jul 11 07:29:39 PM PDT 24
Peak memory 308068 kb
Host smart-21194528-8be7-43a1-bd6d-8f5ef539edca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637070943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2637070943
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2321597634
Short name T1417
Test name
Test status
Simulation time 2375286595 ps
CPU time 82.68 seconds
Started Jul 11 07:29:08 PM PDT 24
Finished Jul 11 07:30:34 PM PDT 24
Peak memory 793344 kb
Host smart-d6bf0861-ff94-475e-97f3-ef9ec064e5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321597634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2321597634
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3747830403
Short name T630
Test name
Test status
Simulation time 9414186928 ps
CPU time 64.6 seconds
Started Jul 11 07:29:10 PM PDT 24
Finished Jul 11 07:30:17 PM PDT 24
Peak memory 700828 kb
Host smart-64050890-6bc8-4269-83eb-fd3015db5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747830403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3747830403
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.192604726
Short name T492
Test name
Test status
Simulation time 85193313 ps
CPU time 0.95 seconds
Started Jul 11 07:29:09 PM PDT 24
Finished Jul 11 07:29:13 PM PDT 24
Peak memory 205172 kb
Host smart-beb25051-654e-4d9b-b4b6-d26efbc5f8b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192604726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.192604726
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3131611908
Short name T171
Test name
Test status
Simulation time 2278567932 ps
CPU time 3.7 seconds
Started Jul 11 07:29:09 PM PDT 24
Finished Jul 11 07:29:16 PM PDT 24
Peak memory 205456 kb
Host smart-33fc4b89-3b61-4a28-a808-6dbebe96377b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131611908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3131611908
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2725391522
Short name T1258
Test name
Test status
Simulation time 12483185175 ps
CPU time 209.72 seconds
Started Jul 11 07:29:04 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 954716 kb
Host smart-e3644d8b-4fc7-4657-818a-5da55673eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725391522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2725391522
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2384217788
Short name T1006
Test name
Test status
Simulation time 846441979 ps
CPU time 6.46 seconds
Started Jul 11 07:29:15 PM PDT 24
Finished Jul 11 07:29:24 PM PDT 24
Peak memory 205332 kb
Host smart-98515a68-694c-47a6-95c3-38316af3c50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384217788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2384217788
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.1514602939
Short name T129
Test name
Test status
Simulation time 65215664 ps
CPU time 0.68 seconds
Started Jul 11 07:29:02 PM PDT 24
Finished Jul 11 07:29:07 PM PDT 24
Peak memory 205128 kb
Host smart-4cb899a4-66f4-4cbc-88a5-0177ae7244f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514602939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1514602939
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.921006561
Short name T866
Test name
Test status
Simulation time 3478856899 ps
CPU time 19.92 seconds
Started Jul 11 07:29:16 PM PDT 24
Finished Jul 11 07:29:39 PM PDT 24
Peak memory 368332 kb
Host smart-f03c26de-55d6-4bd5-b571-40093db72572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921006561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.921006561
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1265057607
Short name T887
Test name
Test status
Simulation time 166747611 ps
CPU time 1.34 seconds
Started Jul 11 07:29:13 PM PDT 24
Finished Jul 11 07:29:17 PM PDT 24
Peak memory 222692 kb
Host smart-bf35e139-8d1b-4258-808a-1aeae8cc35b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265057607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1265057607
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2755319638
Short name T604
Test name
Test status
Simulation time 1882956669 ps
CPU time 32.57 seconds
Started Jul 11 07:29:03 PM PDT 24
Finished Jul 11 07:29:40 PM PDT 24
Peak memory 350288 kb
Host smart-af83a5d9-ad09-4863-a859-960530a0f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755319638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2755319638
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1244648317
Short name T350
Test name
Test status
Simulation time 1537939404 ps
CPU time 6.94 seconds
Started Jul 11 07:29:09 PM PDT 24
Finished Jul 11 07:29:20 PM PDT 24
Peak memory 213588 kb
Host smart-e1af13e7-cd4b-4716-8dfe-53b642234609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244648317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1244648317
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2746592916
Short name T556
Test name
Test status
Simulation time 5382515719 ps
CPU time 6.71 seconds
Started Jul 11 07:29:14 PM PDT 24
Finished Jul 11 07:29:23 PM PDT 24
Peak memory 221784 kb
Host smart-55471186-af93-49be-b096-5cd36c467ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746592916 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2746592916
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3854845447
Short name T1084
Test name
Test status
Simulation time 331087378 ps
CPU time 1.19 seconds
Started Jul 11 07:29:14 PM PDT 24
Finished Jul 11 07:29:18 PM PDT 24
Peak memory 205400 kb
Host smart-03a99305-c798-444b-846d-91334dab03e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854845447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3854845447
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3351918668
Short name T816
Test name
Test status
Simulation time 219601050 ps
CPU time 0.8 seconds
Started Jul 11 07:29:14 PM PDT 24
Finished Jul 11 07:29:17 PM PDT 24
Peak memory 205300 kb
Host smart-4d7043d9-9bb9-4628-ab84-a74f64718384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351918668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3351918668
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1288537713
Short name T694
Test name
Test status
Simulation time 2416773824 ps
CPU time 3.04 seconds
Started Jul 11 07:29:15 PM PDT 24
Finished Jul 11 07:29:21 PM PDT 24
Peak memory 205544 kb
Host smart-ec1d8285-3b5f-4f65-b6bd-b0fb22b93ad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288537713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1288537713
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1474455233
Short name T555
Test name
Test status
Simulation time 78499149 ps
CPU time 0.97 seconds
Started Jul 11 07:29:14 PM PDT 24
Finished Jul 11 07:29:17 PM PDT 24
Peak memory 205392 kb
Host smart-4a6138f2-8813-4ad3-a5b6-eb7e2e7f96e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474455233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1474455233
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2793714366
Short name T543
Test name
Test status
Simulation time 773245381 ps
CPU time 4.96 seconds
Started Jul 11 07:29:08 PM PDT 24
Finished Jul 11 07:29:16 PM PDT 24
Peak memory 216948 kb
Host smart-68cee01c-4314-49d1-8ae6-8c692542c1fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793714366 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2793714366
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.4219442608
Short name T1002
Test name
Test status
Simulation time 2358446816 ps
CPU time 3.02 seconds
Started Jul 11 07:29:19 PM PDT 24
Finished Jul 11 07:29:24 PM PDT 24
Peak memory 213784 kb
Host smart-fff30499-942e-4873-89ef-7da3b0be1b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219442608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.4219442608
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.794376157
Short name T957
Test name
Test status
Simulation time 417738143 ps
CPU time 2.4 seconds
Started Jul 11 07:29:19 PM PDT 24
Finished Jul 11 07:29:24 PM PDT 24
Peak memory 205460 kb
Host smart-ff5882c2-b6b4-49c7-bd5e-335217073f74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794376157 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.794376157
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1126348420
Short name T191
Test name
Test status
Simulation time 953044905 ps
CPU time 2.47 seconds
Started Jul 11 07:29:25 PM PDT 24
Finished Jul 11 07:29:28 PM PDT 24
Peak memory 205356 kb
Host smart-15f789aa-5933-4f3e-ab64-c72d041b8c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126348420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1126348420
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.23537888
Short name T1548
Test name
Test status
Simulation time 534400599 ps
CPU time 15.46 seconds
Started Jul 11 07:29:10 PM PDT 24
Finished Jul 11 07:29:29 PM PDT 24
Peak memory 213684 kb
Host smart-740ba169-d2eb-451a-b27c-d0d30f8ff010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23537888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_targ
et_smoke.23537888
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1008431809
Short name T553
Test name
Test status
Simulation time 3279306646 ps
CPU time 29.86 seconds
Started Jul 11 07:29:09 PM PDT 24
Finished Jul 11 07:29:42 PM PDT 24
Peak memory 238188 kb
Host smart-2ff96283-c0b7-4e2d-a470-bbd2b9472941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008431809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1008431809
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4275141571
Short name T896
Test name
Test status
Simulation time 51305921242 ps
CPU time 1461.06 seconds
Started Jul 11 07:29:11 PM PDT 24
Finished Jul 11 07:53:35 PM PDT 24
Peak memory 7965556 kb
Host smart-28574fed-2ce1-49a0-ab55-59d05739b5cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275141571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4275141571
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.4221857438
Short name T1092
Test name
Test status
Simulation time 4661205951 ps
CPU time 116.21 seconds
Started Jul 11 07:29:08 PM PDT 24
Finished Jul 11 07:31:07 PM PDT 24
Peak memory 1260768 kb
Host smart-6e1c5b2c-00bb-4bbd-a43a-9fbd6f9ab3a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221857438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.4221857438
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.335977711
Short name T949
Test name
Test status
Simulation time 24434415264 ps
CPU time 7.15 seconds
Started Jul 11 07:29:07 PM PDT 24
Finished Jul 11 07:29:17 PM PDT 24
Peak memory 221468 kb
Host smart-e44bebb1-1bac-42af-b57e-5107c6883e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335977711 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.335977711
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.845675291
Short name T918
Test name
Test status
Simulation time 264957405 ps
CPU time 3.48 seconds
Started Jul 11 07:29:21 PM PDT 24
Finished Jul 11 07:29:26 PM PDT 24
Peak memory 213644 kb
Host smart-82b4f20a-f340-463c-a1fc-daacd9921e0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845675291 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.845675291
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2993015223
Short name T1175
Test name
Test status
Simulation time 17580857 ps
CPU time 0.62 seconds
Started Jul 11 07:29:30 PM PDT 24
Finished Jul 11 07:29:32 PM PDT 24
Peak memory 204684 kb
Host smart-e16aea65-54f4-452a-a069-0f39e3719f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993015223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2993015223
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2747399043
Short name T703
Test name
Test status
Simulation time 308192333 ps
CPU time 3.14 seconds
Started Jul 11 07:29:26 PM PDT 24
Finished Jul 11 07:29:31 PM PDT 24
Peak memory 213540 kb
Host smart-a01644f2-400b-4ddb-ab08-b6ee52532e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747399043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2747399043
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.273340174
Short name T517
Test name
Test status
Simulation time 1294718635 ps
CPU time 17.3 seconds
Started Jul 11 07:29:27 PM PDT 24
Finished Jul 11 07:29:45 PM PDT 24
Peak memory 274352 kb
Host smart-b2c4cc4d-5a1f-4ec7-aa8f-75c4d331c671
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273340174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.273340174
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1159087481
Short name T1545
Test name
Test status
Simulation time 2944848946 ps
CPU time 213.98 seconds
Started Jul 11 07:29:27 PM PDT 24
Finished Jul 11 07:33:02 PM PDT 24
Peak memory 874476 kb
Host smart-430b0ea2-6f48-4a27-85c8-d9db73060f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159087481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1159087481
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1836125258
Short name T26
Test name
Test status
Simulation time 3162873514 ps
CPU time 44.4 seconds
Started Jul 11 07:29:29 PM PDT 24
Finished Jul 11 07:30:14 PM PDT 24
Peak memory 506824 kb
Host smart-1192d4cc-573f-495e-b192-db9ef7c0f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836125258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1836125258
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.208277894
Short name T875
Test name
Test status
Simulation time 584403274 ps
CPU time 1.06 seconds
Started Jul 11 07:29:27 PM PDT 24
Finished Jul 11 07:29:29 PM PDT 24
Peak memory 205140 kb
Host smart-833f7aba-6bb0-4581-8c2e-4517cf3c5901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208277894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.208277894
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1613677874
Short name T1133
Test name
Test status
Simulation time 489861068 ps
CPU time 3.14 seconds
Started Jul 11 07:29:25 PM PDT 24
Finished Jul 11 07:29:29 PM PDT 24
Peak memory 205360 kb
Host smart-1e7f953c-5cc5-44f8-a85b-887c5e1cb3c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613677874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1613677874
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2818713311
Short name T411
Test name
Test status
Simulation time 17814013636 ps
CPU time 319.81 seconds
Started Jul 11 07:29:20 PM PDT 24
Finished Jul 11 07:34:41 PM PDT 24
Peak memory 1274580 kb
Host smart-cf412989-be27-4d8a-b81d-34f8e1d13eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818713311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2818713311
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1183911400
Short name T1413
Test name
Test status
Simulation time 1941358276 ps
CPU time 18.16 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:52 PM PDT 24
Peak memory 205392 kb
Host smart-8b258528-3f7c-465a-88e7-226c2e87f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183911400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1183911400
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.3116332095
Short name T131
Test name
Test status
Simulation time 27601547 ps
CPU time 0.71 seconds
Started Jul 11 07:29:21 PM PDT 24
Finished Jul 11 07:29:23 PM PDT 24
Peak memory 205140 kb
Host smart-5849524a-f1f3-4c96-9ebf-96ff6696c66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116332095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3116332095
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.471351617
Short name T685
Test name
Test status
Simulation time 49079684823 ps
CPU time 1063.87 seconds
Started Jul 11 07:29:34 PM PDT 24
Finished Jul 11 07:47:19 PM PDT 24
Peak memory 279032 kb
Host smart-15e5cb5f-4db5-406b-a532-92ba1faccd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471351617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.471351617
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.1305950604
Short name T369
Test name
Test status
Simulation time 194122857 ps
CPU time 2.4 seconds
Started Jul 11 07:29:26 PM PDT 24
Finished Jul 11 07:29:30 PM PDT 24
Peak memory 205224 kb
Host smart-0bc251f1-2e14-49d5-ac4b-dc8162ca32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305950604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1305950604
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3195733574
Short name T1303
Test name
Test status
Simulation time 1870831617 ps
CPU time 38.33 seconds
Started Jul 11 07:29:19 PM PDT 24
Finished Jul 11 07:30:00 PM PDT 24
Peak memory 377888 kb
Host smart-2a7c6487-bf8c-43ae-9129-5078e9b453af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195733574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3195733574
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3345815888
Short name T431
Test name
Test status
Simulation time 398190766 ps
CPU time 18.17 seconds
Started Jul 11 07:29:26 PM PDT 24
Finished Jul 11 07:29:45 PM PDT 24
Peak memory 213592 kb
Host smart-9f8c9b56-79a7-4fd2-a2ad-5dc3992413c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345815888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3345815888
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4034114212
Short name T1112
Test name
Test status
Simulation time 5027422882 ps
CPU time 4.15 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:38 PM PDT 24
Peak memory 218064 kb
Host smart-b4901690-9e1c-4e80-b365-9182eb9a2fa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034114212 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4034114212
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3944582369
Short name T893
Test name
Test status
Simulation time 188708953 ps
CPU time 1.25 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:35 PM PDT 24
Peak memory 205396 kb
Host smart-fc8fe413-4945-4650-92da-73db29e7d085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944582369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3944582369
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1196194412
Short name T1114
Test name
Test status
Simulation time 162361046 ps
CPU time 1.13 seconds
Started Jul 11 07:29:36 PM PDT 24
Finished Jul 11 07:29:41 PM PDT 24
Peak memory 205400 kb
Host smart-e373a291-bbee-4bc0-be92-544bbd1e992e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196194412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1196194412
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.1504460491
Short name T271
Test name
Test status
Simulation time 454446358 ps
CPU time 2.78 seconds
Started Jul 11 07:29:31 PM PDT 24
Finished Jul 11 07:29:36 PM PDT 24
Peak memory 205468 kb
Host smart-cff35046-7013-4db6-bb6b-7a799f2c9785
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504460491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.1504460491
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1009142417
Short name T383
Test name
Test status
Simulation time 144197869 ps
CPU time 1.33 seconds
Started Jul 11 07:29:33 PM PDT 24
Finished Jul 11 07:29:36 PM PDT 24
Peak memory 205368 kb
Host smart-69131c2c-986a-480b-862d-8c7c1e0e89a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009142417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1009142417
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1927741149
Short name T905
Test name
Test status
Simulation time 1198620220 ps
CPU time 7.22 seconds
Started Jul 11 07:29:29 PM PDT 24
Finished Jul 11 07:29:37 PM PDT 24
Peak memory 219944 kb
Host smart-c8591be2-c9a6-41d2-a2e5-973b96f0efde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927741149 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1927741149
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.472928937
Short name T1535
Test name
Test status
Simulation time 8043753615 ps
CPU time 35.43 seconds
Started Jul 11 07:29:34 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 968732 kb
Host smart-c3f72964-65b0-4d27-9642-3166159d8b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472928937 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.472928937
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3114683266
Short name T156
Test name
Test status
Simulation time 516084692 ps
CPU time 2.73 seconds
Started Jul 11 07:29:39 PM PDT 24
Finished Jul 11 07:29:45 PM PDT 24
Peak memory 213684 kb
Host smart-e8194530-9204-465c-bd56-c283d5e61063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114683266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3114683266
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.716107387
Short name T606
Test name
Test status
Simulation time 1508061011 ps
CPU time 2.4 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:36 PM PDT 24
Peak memory 205480 kb
Host smart-5745f27c-5e0d-4d62-bff5-bbbf3521c38e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716107387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.716107387
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.436991445
Short name T413
Test name
Test status
Simulation time 1449368627 ps
CPU time 2.11 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:36 PM PDT 24
Peak memory 205368 kb
Host smart-5d02fa61-b36e-4a62-8f10-a3a4c2a4b365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436991445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.436991445
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.892902832
Short name T1052
Test name
Test status
Simulation time 1029094627 ps
CPU time 31.47 seconds
Started Jul 11 07:30:04 PM PDT 24
Finished Jul 11 07:30:39 PM PDT 24
Peak memory 213636 kb
Host smart-060b95b5-9162-431b-9675-e9793c0a9c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892902832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.892902832
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.849398559
Short name T1117
Test name
Test status
Simulation time 978467586 ps
CPU time 19.09 seconds
Started Jul 11 07:29:26 PM PDT 24
Finished Jul 11 07:29:46 PM PDT 24
Peak memory 221092 kb
Host smart-4d9eb17e-67ff-4de6-9266-75823158945b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849398559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.849398559
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3462864205
Short name T497
Test name
Test status
Simulation time 15739490580 ps
CPU time 6.39 seconds
Started Jul 11 07:29:27 PM PDT 24
Finished Jul 11 07:29:34 PM PDT 24
Peak memory 205572 kb
Host smart-59a15ace-9720-45bb-adb4-829fe8417b7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462864205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3462864205
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3001073387
Short name T405
Test name
Test status
Simulation time 582176254 ps
CPU time 1.1 seconds
Started Jul 11 07:29:25 PM PDT 24
Finished Jul 11 07:29:27 PM PDT 24
Peak memory 205448 kb
Host smart-d02c79ba-4543-4f81-b46a-7110fbbcd8e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001073387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3001073387
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.4179283835
Short name T126
Test name
Test status
Simulation time 1544543292 ps
CPU time 7.49 seconds
Started Jul 11 07:29:33 PM PDT 24
Finished Jul 11 07:29:42 PM PDT 24
Peak memory 219876 kb
Host smart-fd66236a-0f2d-4123-abcd-7a841b0d2a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179283835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.4179283835
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.337914875
Short name T1297
Test name
Test status
Simulation time 101305638 ps
CPU time 2.3 seconds
Started Jul 11 07:29:32 PM PDT 24
Finished Jul 11 07:29:37 PM PDT 24
Peak memory 205456 kb
Host smart-b9b6cc89-2bb9-43f8-8027-8ed9d5125e39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337914875 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.337914875
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2587274701
Short name T810
Test name
Test status
Simulation time 54101692 ps
CPU time 0.65 seconds
Started Jul 11 07:29:51 PM PDT 24
Finished Jul 11 07:29:53 PM PDT 24
Peak memory 204672 kb
Host smart-edd16bee-eee4-441b-a13c-bb7d45ed273e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587274701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2587274701
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3882602963
Short name T19
Test name
Test status
Simulation time 231098122 ps
CPU time 10.03 seconds
Started Jul 11 07:29:37 PM PDT 24
Finished Jul 11 07:29:51 PM PDT 24
Peak memory 250200 kb
Host smart-4de0bac3-9a8a-41ec-96d0-31b89949a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882602963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3882602963
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.210747882
Short name T1220
Test name
Test status
Simulation time 1895995795 ps
CPU time 9.32 seconds
Started Jul 11 07:29:37 PM PDT 24
Finished Jul 11 07:29:50 PM PDT 24
Peak memory 307448 kb
Host smart-c06d998f-7d3a-4c70-9b49-ce06bb0acda6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210747882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.210747882
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1129932629
Short name T82
Test name
Test status
Simulation time 6982369820 ps
CPU time 50.84 seconds
Started Jul 11 07:29:37 PM PDT 24
Finished Jul 11 07:30:32 PM PDT 24
Peak memory 536440 kb
Host smart-d6770b4f-6a4a-496e-a030-cc8988cb0f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129932629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1129932629
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3181239737
Short name T813
Test name
Test status
Simulation time 4703989411 ps
CPU time 52.03 seconds
Started Jul 11 07:29:38 PM PDT 24
Finished Jul 11 07:30:34 PM PDT 24
Peak memory 627196 kb
Host smart-83886478-4ebd-4976-99eb-83f3e9b4cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181239737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3181239737
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2608761908
Short name T943
Test name
Test status
Simulation time 138572312 ps
CPU time 1.36 seconds
Started Jul 11 07:29:37 PM PDT 24
Finished Jul 11 07:29:42 PM PDT 24
Peak memory 205248 kb
Host smart-dcb8ac2d-8d7b-409f-8c14-aa9a837db1a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608761908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2608761908
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.356663243
Short name T1047
Test name
Test status
Simulation time 171790892 ps
CPU time 4.18 seconds
Started Jul 11 07:29:38 PM PDT 24
Finished Jul 11 07:29:47 PM PDT 24
Peak memory 205392 kb
Host smart-402aa0f9-e97c-4c18-9a6d-8e0378474b76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356663243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
356663243
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3067916741
Short name T1023
Test name
Test status
Simulation time 5501720288 ps
CPU time 56.74 seconds
Started Jul 11 07:29:36 PM PDT 24
Finished Jul 11 07:30:35 PM PDT 24
Peak memory 804776 kb
Host smart-bd7b3279-5f3f-4dc9-8472-ae1872f047cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067916741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3067916741
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_override.1909968834
Short name T91
Test name
Test status
Simulation time 17315996 ps
CPU time 0.66 seconds
Started Jul 11 07:29:36 PM PDT 24
Finished Jul 11 07:29:40 PM PDT 24
Peak memory 205072 kb
Host smart-1985bda3-ce51-48c0-82f3-311d925b2470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909968834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1909968834
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.928854611
Short name T1065
Test name
Test status
Simulation time 371414047 ps
CPU time 14.96 seconds
Started Jul 11 07:29:38 PM PDT 24
Finished Jul 11 07:29:57 PM PDT 24
Peak memory 206016 kb
Host smart-a1fb8fc2-88f9-4b77-93f0-eadf2041c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928854611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.928854611
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1011884021
Short name T1232
Test name
Test status
Simulation time 50774659 ps
CPU time 1.99 seconds
Started Jul 11 07:29:37 PM PDT 24
Finished Jul 11 07:29:43 PM PDT 24
Peak memory 214200 kb
Host smart-c4833bd3-acb4-4512-a75c-9d8cbee84a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011884021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1011884021
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3548413543
Short name T501
Test name
Test status
Simulation time 1320261935 ps
CPU time 67.83 seconds
Started Jul 11 07:29:38 PM PDT 24
Finished Jul 11 07:30:50 PM PDT 24
Peak memory 366348 kb
Host smart-a3bb84f6-e851-4bbe-b9bb-d4209e8ff808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548413543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3548413543
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2471750795
Short name T777
Test name
Test status
Simulation time 500836516 ps
CPU time 22.17 seconds
Started Jul 11 07:29:38 PM PDT 24
Finished Jul 11 07:30:04 PM PDT 24
Peak memory 213600 kb
Host smart-93d4b18a-da2e-4897-bab8-76de58cb78a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471750795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2471750795
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.909039750
Short name T732
Test name
Test status
Simulation time 8244632996 ps
CPU time 4.65 seconds
Started Jul 11 07:29:45 PM PDT 24
Finished Jul 11 07:29:51 PM PDT 24
Peak memory 213988 kb
Host smart-c774292a-1ba1-4500-9281-98b0d75121d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909039750 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.909039750
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1260220420
Short name T1238
Test name
Test status
Simulation time 411461020 ps
CPU time 1.8 seconds
Started Jul 11 07:29:47 PM PDT 24
Finished Jul 11 07:29:50 PM PDT 24
Peak memory 205556 kb
Host smart-a6e6e332-ac7d-487f-b824-b244cae9653d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260220420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1260220420
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2807399621
Short name T1332
Test name
Test status
Simulation time 284857191 ps
CPU time 1.77 seconds
Started Jul 11 07:29:46 PM PDT 24
Finished Jul 11 07:29:49 PM PDT 24
Peak memory 213064 kb
Host smart-9035e17e-e3bb-4cc0-ab64-a8ca930f62e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807399621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2807399621
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.2402862103
Short name T1375
Test name
Test status
Simulation time 3234289907 ps
CPU time 2.98 seconds
Started Jul 11 07:29:55 PM PDT 24
Finished Jul 11 07:30:01 PM PDT 24
Peak memory 205588 kb
Host smart-2ee0f66f-cc89-484d-a297-af027b03bb2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402862103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.2402862103
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.1583375278
Short name T753
Test name
Test status
Simulation time 156870101 ps
CPU time 1.46 seconds
Started Jul 11 07:29:54 PM PDT 24
Finished Jul 11 07:29:58 PM PDT 24
Peak memory 205392 kb
Host smart-791b2e1e-3f9f-475a-a58c-e1802a3934ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583375278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.1583375278
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1278190148
Short name T633
Test name
Test status
Simulation time 3578941402 ps
CPU time 5.23 seconds
Started Jul 11 07:29:44 PM PDT 24
Finished Jul 11 07:29:51 PM PDT 24
Peak memory 213732 kb
Host smart-76193f4e-0aac-4e74-be02-48e07efcdd40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278190148 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1278190148
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2808458076
Short name T643
Test name
Test status
Simulation time 19833560604 ps
CPU time 55.1 seconds
Started Jul 11 07:29:45 PM PDT 24
Finished Jul 11 07:30:41 PM PDT 24
Peak memory 820956 kb
Host smart-2aa0bb3b-0d75-437f-9df6-3bc5dbe7401b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808458076 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2808458076
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.4004529347
Short name T1054
Test name
Test status
Simulation time 2354603661 ps
CPU time 3.2 seconds
Started Jul 11 07:29:55 PM PDT 24
Finished Jul 11 07:30:01 PM PDT 24
Peak memory 213748 kb
Host smart-c10fb522-64be-4057-9b24-beb98baf99dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004529347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.4004529347
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.3374032714
Short name T446
Test name
Test status
Simulation time 1089546715 ps
CPU time 2.62 seconds
Started Jul 11 07:29:51 PM PDT 24
Finished Jul 11 07:29:56 PM PDT 24
Peak memory 205428 kb
Host smart-d73d51c2-07e0-453e-95b8-cc83176b7a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374032714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3374032714
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.1858072083
Short name T1267
Test name
Test status
Simulation time 615224857 ps
CPU time 2.51 seconds
Started Jul 11 07:29:52 PM PDT 24
Finished Jul 11 07:29:57 PM PDT 24
Peak memory 205360 kb
Host smart-6c0c33e7-e3db-4e79-81a8-1b2c445b2475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858072083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.1858072083
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1067569557
Short name T969
Test name
Test status
Simulation time 4742944196 ps
CPU time 18.41 seconds
Started Jul 11 07:29:50 PM PDT 24
Finished Jul 11 07:30:09 PM PDT 24
Peak memory 213780 kb
Host smart-c2e48619-aa19-4864-b80c-81b413a0f91b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067569557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1067569557
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.501427226
Short name T1099
Test name
Test status
Simulation time 7920852890 ps
CPU time 82.64 seconds
Started Jul 11 07:29:45 PM PDT 24
Finished Jul 11 07:31:09 PM PDT 24
Peak memory 220252 kb
Host smart-ca75c2e3-f5d3-430f-aff9-36af66c41e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501427226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.501427226
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2072946162
Short name T820
Test name
Test status
Simulation time 46618543928 ps
CPU time 957.65 seconds
Started Jul 11 07:29:44 PM PDT 24
Finished Jul 11 07:45:43 PM PDT 24
Peak memory 6534944 kb
Host smart-f52d67cb-d1b7-46f2-a4e3-7944bf900a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072946162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2072946162
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.463140708
Short name T1342
Test name
Test status
Simulation time 3077117550 ps
CPU time 9.89 seconds
Started Jul 11 07:29:46 PM PDT 24
Finished Jul 11 07:29:58 PM PDT 24
Peak memory 326184 kb
Host smart-5479bdc1-3aac-43ed-9145-96dd0165000a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463140708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.463140708
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2749987185
Short name T745
Test name
Test status
Simulation time 1629288953 ps
CPU time 7.62 seconds
Started Jul 11 07:29:46 PM PDT 24
Finished Jul 11 07:29:55 PM PDT 24
Peak memory 218888 kb
Host smart-57d25940-ff40-4d9a-b821-2aa4364b2194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749987185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2749987185
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.475701335
Short name T1083
Test name
Test status
Simulation time 722253899 ps
CPU time 10.24 seconds
Started Jul 11 07:29:53 PM PDT 24
Finished Jul 11 07:30:05 PM PDT 24
Peak memory 221112 kb
Host smart-71a40a03-acb4-416e-9e62-35d94c27a18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475701335 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.475701335
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1812686376
Short name T1271
Test name
Test status
Simulation time 17543445 ps
CPU time 0.64 seconds
Started Jul 11 07:30:07 PM PDT 24
Finished Jul 11 07:30:09 PM PDT 24
Peak memory 204672 kb
Host smart-ec9f0ece-2eda-4869-8037-b8ee54f602ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812686376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1812686376
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.852693738
Short name T645
Test name
Test status
Simulation time 248013708 ps
CPU time 1.19 seconds
Started Jul 11 07:29:53 PM PDT 24
Finished Jul 11 07:29:56 PM PDT 24
Peak memory 213608 kb
Host smart-1340a576-9951-4e2a-8117-d3f19accdf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852693738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.852693738
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2046211769
Short name T1231
Test name
Test status
Simulation time 1252313330 ps
CPU time 5.56 seconds
Started Jul 11 07:29:53 PM PDT 24
Finished Jul 11 07:30:01 PM PDT 24
Peak memory 264480 kb
Host smart-84ba6dc1-5184-47de-9550-d66f575789e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046211769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2046211769
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2775844980
Short name T1451
Test name
Test status
Simulation time 7132833763 ps
CPU time 53.74 seconds
Started Jul 11 07:29:59 PM PDT 24
Finished Jul 11 07:30:57 PM PDT 24
Peak memory 632356 kb
Host smart-c8a4e71f-a240-4bdd-9713-f539b93f115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775844980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2775844980
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3409516714
Short name T701
Test name
Test status
Simulation time 5668866392 ps
CPU time 88.3 seconds
Started Jul 11 07:29:56 PM PDT 24
Finished Jul 11 07:31:28 PM PDT 24
Peak memory 447628 kb
Host smart-33571ba0-6538-4fd6-a061-0d54124c20b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409516714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3409516714
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1159603839
Short name T495
Test name
Test status
Simulation time 115106544 ps
CPU time 0.95 seconds
Started Jul 11 07:29:56 PM PDT 24
Finished Jul 11 07:30:01 PM PDT 24
Peak memory 205028 kb
Host smart-fd6e2b49-8e89-4890-8d7d-6a8e6de1af56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159603839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1159603839
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2455658466
Short name T1336
Test name
Test status
Simulation time 183910346 ps
CPU time 4.46 seconds
Started Jul 11 07:29:51 PM PDT 24
Finished Jul 11 07:29:57 PM PDT 24
Peak memory 238908 kb
Host smart-dba1184d-394b-4b41-a5b5-bc3112dbee8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455658466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2455658466
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.943845156
Short name T768
Test name
Test status
Simulation time 5293575158 ps
CPU time 165.47 seconds
Started Jul 11 07:29:52 PM PDT 24
Finished Jul 11 07:32:40 PM PDT 24
Peak memory 1477076 kb
Host smart-307bf72c-2559-4f3b-bc4a-4b8af2f2d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943845156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.943845156
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.1058441471
Short name T244
Test name
Test status
Simulation time 1974034566 ps
CPU time 7.39 seconds
Started Jul 11 07:29:58 PM PDT 24
Finished Jul 11 07:30:09 PM PDT 24
Peak memory 205432 kb
Host smart-9b999878-6214-4f12-8c5b-370a4f75a216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058441471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1058441471
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.965266973
Short name T134
Test name
Test status
Simulation time 26930666 ps
CPU time 0.69 seconds
Started Jul 11 07:29:55 PM PDT 24
Finished Jul 11 07:29:59 PM PDT 24
Peak memory 205140 kb
Host smart-046dd153-09bf-4cdc-a109-0088d751cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965266973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.965266973
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1634632169
Short name T33
Test name
Test status
Simulation time 7145834414 ps
CPU time 388.04 seconds
Started Jul 11 07:29:56 PM PDT 24
Finished Jul 11 07:36:28 PM PDT 24
Peak memory 777972 kb
Host smart-5578a126-fded-4135-9db4-5a43697b2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634632169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1634632169
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.2323548264
Short name T1352
Test name
Test status
Simulation time 132177044 ps
CPU time 2.41 seconds
Started Jul 11 07:29:53 PM PDT 24
Finished Jul 11 07:29:57 PM PDT 24
Peak memory 229740 kb
Host smart-51dca198-f71f-4bb5-bace-c56ee621f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323548264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.2323548264
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.4199974989
Short name T1499
Test name
Test status
Simulation time 20062790781 ps
CPU time 29.15 seconds
Started Jul 11 07:29:56 PM PDT 24
Finished Jul 11 07:30:30 PM PDT 24
Peak memory 367060 kb
Host smart-cdddda65-8bac-4b81-85c5-e71af6f3c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199974989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.4199974989
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.949873294
Short name T656
Test name
Test status
Simulation time 7469652316 ps
CPU time 36.61 seconds
Started Jul 11 07:29:52 PM PDT 24
Finished Jul 11 07:30:30 PM PDT 24
Peak memory 213720 kb
Host smart-05804106-c33a-40f3-a722-0f5c584fe9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949873294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.949873294
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2849255354
Short name T270
Test name
Test status
Simulation time 2285124279 ps
CPU time 3.87 seconds
Started Jul 11 07:29:57 PM PDT 24
Finished Jul 11 07:30:05 PM PDT 24
Peak memory 216756 kb
Host smart-7fb9d1a9-7010-4f2f-b75b-2e8d20982eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849255354 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2849255354
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2117369313
Short name T807
Test name
Test status
Simulation time 586950331 ps
CPU time 1.23 seconds
Started Jul 11 07:29:56 PM PDT 24
Finished Jul 11 07:30:01 PM PDT 24
Peak memory 205564 kb
Host smart-59603292-0055-4f35-83a5-ac4d26761bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117369313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2117369313
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4006857907
Short name T380
Test name
Test status
Simulation time 171153467 ps
CPU time 0.9 seconds
Started Jul 11 07:30:00 PM PDT 24
Finished Jul 11 07:30:04 PM PDT 24
Peak memory 205392 kb
Host smart-abe027fd-c627-4a53-96c8-cf099d929805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006857907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4006857907
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1105138746
Short name T524
Test name
Test status
Simulation time 695898424 ps
CPU time 2.39 seconds
Started Jul 11 07:30:00 PM PDT 24
Finished Jul 11 07:30:06 PM PDT 24
Peak memory 205472 kb
Host smart-5dda72ac-31c7-4656-bd37-c7597127403e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105138746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1105138746
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1630368949
Short name T1093
Test name
Test status
Simulation time 481868240 ps
CPU time 1.31 seconds
Started Jul 11 07:29:57 PM PDT 24
Finished Jul 11 07:30:02 PM PDT 24
Peak memory 205400 kb
Host smart-0ae3ead9-4938-43f4-a8ef-21066143f212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630368949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1630368949
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.954283556
Short name T939
Test name
Test status
Simulation time 3101798910 ps
CPU time 4.18 seconds
Started Jul 11 07:29:57 PM PDT 24
Finished Jul 11 07:30:05 PM PDT 24
Peak memory 218520 kb
Host smart-03711a49-14e2-468f-8f15-91dba710cd31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954283556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.954283556
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.655860609
Short name T210
Test name
Test status
Simulation time 20396446952 ps
CPU time 54.85 seconds
Started Jul 11 07:29:58 PM PDT 24
Finished Jul 11 07:30:57 PM PDT 24
Peak memory 822196 kb
Host smart-af7b4d5a-f6f2-4199-bc3e-cf34d96a3a8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655860609 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.655860609
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.2469692376
Short name T457
Test name
Test status
Simulation time 1591232920 ps
CPU time 2.59 seconds
Started Jul 11 07:30:03 PM PDT 24
Finished Jul 11 07:30:09 PM PDT 24
Peak memory 213728 kb
Host smart-61339f98-5611-4ff7-a73b-18d1bebc9bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469692376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_nack_acqfull.2469692376
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.3310864189
Short name T822
Test name
Test status
Simulation time 3228842553 ps
CPU time 3.04 seconds
Started Jul 11 07:30:06 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 205240 kb
Host smart-20ed14a9-a298-4b71-9456-1c7994ac1baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310864189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.3310864189
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.1159343588
Short name T439
Test name
Test status
Simulation time 3397837168 ps
CPU time 2.34 seconds
Started Jul 11 07:30:08 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 205412 kb
Host smart-8b30808a-104d-401b-898f-62379540057f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159343588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.1159343588
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1719000045
Short name T1502
Test name
Test status
Simulation time 936748932 ps
CPU time 27.72 seconds
Started Jul 11 07:29:52 PM PDT 24
Finished Jul 11 07:30:22 PM PDT 24
Peak memory 213676 kb
Host smart-fd55d2fc-2534-4d9c-80bd-14ff45b6f9b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719000045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1719000045
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2379299319
Short name T186
Test name
Test status
Simulation time 1337238594 ps
CPU time 9.82 seconds
Started Jul 11 07:30:01 PM PDT 24
Finished Jul 11 07:30:14 PM PDT 24
Peak memory 219456 kb
Host smart-75033bcb-05eb-4932-849e-511b08672b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379299319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2379299319
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.81087483
Short name T1138
Test name
Test status
Simulation time 8699357013 ps
CPU time 5.32 seconds
Started Jul 11 07:29:58 PM PDT 24
Finished Jul 11 07:30:07 PM PDT 24
Peak memory 205404 kb
Host smart-158f324d-474d-4e29-ac9b-427f7cd1ce46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81087483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stress_wr.81087483
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1640675089
Short name T511
Test name
Test status
Simulation time 239252936 ps
CPU time 1.11 seconds
Started Jul 11 07:29:58 PM PDT 24
Finished Jul 11 07:30:04 PM PDT 24
Peak memory 205392 kb
Host smart-d655cc41-c027-4b68-8c17-d9159aa41179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640675089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1640675089
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2298982886
Short name T925
Test name
Test status
Simulation time 17984123155 ps
CPU time 7.43 seconds
Started Jul 11 07:29:59 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 213736 kb
Host smart-49c7d1db-7d1a-4da4-b05c-35e69afa965b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298982886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2298982886
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.3027457237
Short name T1185
Test name
Test status
Simulation time 55750769 ps
CPU time 1.15 seconds
Started Jul 11 07:30:02 PM PDT 24
Finished Jul 11 07:30:06 PM PDT 24
Peak memory 205500 kb
Host smart-b8d2a470-04d2-486e-8484-b2afa57457f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027457237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3027457237
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2790668903
Short name T1314
Test name
Test status
Simulation time 34650916 ps
CPU time 0.61 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:19 PM PDT 24
Peak memory 204664 kb
Host smart-22f1b22d-518a-4d6c-9ac8-5210c534a5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790668903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2790668903
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3260122526
Short name T1247
Test name
Test status
Simulation time 86143290 ps
CPU time 1.78 seconds
Started Jul 11 07:30:04 PM PDT 24
Finished Jul 11 07:30:09 PM PDT 24
Peak memory 213600 kb
Host smart-89eec58f-07fa-479c-97f4-02cd9362ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260122526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3260122526
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3166729654
Short name T1286
Test name
Test status
Simulation time 112077283 ps
CPU time 6.02 seconds
Started Jul 11 07:30:02 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 223272 kb
Host smart-fc029c25-09ab-4399-80c9-bfe5225801cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166729654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3166729654
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1683507289
Short name T75
Test name
Test status
Simulation time 13041522595 ps
CPU time 121.77 seconds
Started Jul 11 07:30:04 PM PDT 24
Finished Jul 11 07:32:09 PM PDT 24
Peak memory 418136 kb
Host smart-4f8a8d7f-0ea1-42ab-8975-a2f9d014dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683507289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1683507289
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2237247974
Short name T924
Test name
Test status
Simulation time 6230344427 ps
CPU time 88.86 seconds
Started Jul 11 07:30:03 PM PDT 24
Finished Jul 11 07:31:35 PM PDT 24
Peak memory 427836 kb
Host smart-7a2afa8b-4558-45c2-bfe8-546f9d717813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237247974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2237247974
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.46704577
Short name T1331
Test name
Test status
Simulation time 388224725 ps
CPU time 0.98 seconds
Started Jul 11 07:30:01 PM PDT 24
Finished Jul 11 07:30:05 PM PDT 24
Peak memory 205092 kb
Host smart-7c9ca4e7-17c0-4dc2-b638-59f2e7e01719
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46704577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt
.46704577
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1993164818
Short name T155
Test name
Test status
Simulation time 244944928 ps
CPU time 6.46 seconds
Started Jul 11 07:30:04 PM PDT 24
Finished Jul 11 07:30:14 PM PDT 24
Peak memory 245948 kb
Host smart-f4ef1acb-a38f-40a0-a75d-fa06463a23b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993164818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1993164818
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3476918936
Short name T108
Test name
Test status
Simulation time 3413990091 ps
CPU time 78.02 seconds
Started Jul 11 07:30:06 PM PDT 24
Finished Jul 11 07:31:26 PM PDT 24
Peak memory 1056920 kb
Host smart-f409f1a1-09f2-4322-89b2-880a31ced5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476918936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3476918936
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1248641653
Short name T1125
Test name
Test status
Simulation time 1444723205 ps
CPU time 3.05 seconds
Started Jul 11 07:30:15 PM PDT 24
Finished Jul 11 07:30:18 PM PDT 24
Peak memory 205348 kb
Host smart-37ff1698-fb7d-466e-8517-0bc6252d6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248641653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1248641653
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.660523301
Short name T426
Test name
Test status
Simulation time 25184363 ps
CPU time 0.68 seconds
Started Jul 11 07:30:05 PM PDT 24
Finished Jul 11 07:30:08 PM PDT 24
Peak memory 205140 kb
Host smart-37fac560-cd08-4892-acbc-f9ef500782a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660523301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.660523301
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1435315623
Short name T823
Test name
Test status
Simulation time 1940698971 ps
CPU time 6.46 seconds
Started Jul 11 07:30:02 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 233868 kb
Host smart-bae94795-e2a7-494e-b95f-23ce15f55b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435315623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1435315623
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2499060295
Short name T590
Test name
Test status
Simulation time 1389201832 ps
CPU time 11.19 seconds
Started Jul 11 07:30:03 PM PDT 24
Finished Jul 11 07:30:17 PM PDT 24
Peak memory 205200 kb
Host smart-07f8839e-960b-4bdc-a88c-8c2f86b39a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499060295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2499060295
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2710499125
Short name T1381
Test name
Test status
Simulation time 4452249777 ps
CPU time 55.59 seconds
Started Jul 11 07:30:05 PM PDT 24
Finished Jul 11 07:31:03 PM PDT 24
Peak memory 298512 kb
Host smart-2ef4dbf2-85f9-4f3f-8770-078a22501d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710499125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2710499125
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3083058131
Short name T485
Test name
Test status
Simulation time 2324144692 ps
CPU time 34.97 seconds
Started Jul 11 07:30:03 PM PDT 24
Finished Jul 11 07:30:41 PM PDT 24
Peak memory 213616 kb
Host smart-0f9daa6f-2b83-42ba-86d7-4b709c374b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083058131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3083058131
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3646737165
Short name T826
Test name
Test status
Simulation time 1136139137 ps
CPU time 5.22 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:24 PM PDT 24
Peak memory 213676 kb
Host smart-7d2db0e4-9330-4baf-ac17-59dab42f429f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646737165 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3646737165
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2909598396
Short name T165
Test name
Test status
Simulation time 221537686 ps
CPU time 1.77 seconds
Started Jul 11 07:30:09 PM PDT 24
Finished Jul 11 07:30:13 PM PDT 24
Peak memory 213644 kb
Host smart-d1afff6a-dc79-4b68-a6b5-b8fa847164ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909598396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2909598396
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3188350791
Short name T1459
Test name
Test status
Simulation time 403412700 ps
CPU time 1.36 seconds
Started Jul 11 07:30:08 PM PDT 24
Finished Jul 11 07:30:11 PM PDT 24
Peak memory 205532 kb
Host smart-09657227-026f-4fff-a8cd-20ce6b07d07a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188350791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3188350791
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.3432504409
Short name T113
Test name
Test status
Simulation time 2362140746 ps
CPU time 2.29 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:20 PM PDT 24
Peak memory 205516 kb
Host smart-e7b94b58-14f3-4681-bd91-07a82e538e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432504409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.3432504409
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.1631083980
Short name T1492
Test name
Test status
Simulation time 117653635 ps
CPU time 1.19 seconds
Started Jul 11 07:30:15 PM PDT 24
Finished Jul 11 07:30:18 PM PDT 24
Peak memory 205348 kb
Host smart-c8facc94-cbe7-4e9f-8c11-46de0a4c6158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631083980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.1631083980
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4206798836
Short name T676
Test name
Test status
Simulation time 9424338199 ps
CPU time 5.2 seconds
Started Jul 11 07:30:08 PM PDT 24
Finished Jul 11 07:30:15 PM PDT 24
Peak memory 218188 kb
Host smart-afd64910-015f-484d-a002-bd824727b543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206798836 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4206798836
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1180737437
Short name T742
Test name
Test status
Simulation time 3350931083 ps
CPU time 5.99 seconds
Started Jul 11 07:30:08 PM PDT 24
Finished Jul 11 07:30:16 PM PDT 24
Peak memory 348688 kb
Host smart-27c0ae42-14f7-4a3c-ac80-79d01986d18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180737437 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1180737437
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.2094517017
Short name T1210
Test name
Test status
Simulation time 560526265 ps
CPU time 2.78 seconds
Started Jul 11 07:30:15 PM PDT 24
Finished Jul 11 07:30:19 PM PDT 24
Peak memory 213632 kb
Host smart-dcf5f601-58cc-472f-b133-5177a41c2d36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094517017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.2094517017
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.3783518996
Short name T1365
Test name
Test status
Simulation time 1395884502 ps
CPU time 2.56 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:19 PM PDT 24
Peak memory 205500 kb
Host smart-7db454fc-5b82-4159-84cd-208adbc1402d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783518996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.3783518996
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.3405504853
Short name T190
Test name
Test status
Simulation time 1051902705 ps
CPU time 2.59 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:21 PM PDT 24
Peak memory 205300 kb
Host smart-7c01265d-4356-4775-ac8e-a64882f81fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405504853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.3405504853
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2160889868
Short name T265
Test name
Test status
Simulation time 636464729 ps
CPU time 9.8 seconds
Started Jul 11 07:30:10 PM PDT 24
Finished Jul 11 07:30:21 PM PDT 24
Peak memory 221888 kb
Host smart-9e12c956-c973-4119-891b-b35ba3481f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160889868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2160889868
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1693201481
Short name T740
Test name
Test status
Simulation time 683007150 ps
CPU time 14.69 seconds
Started Jul 11 07:30:08 PM PDT 24
Finished Jul 11 07:30:24 PM PDT 24
Peak memory 221892 kb
Host smart-8ed92d34-9317-4027-8d47-fbe17420d361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693201481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1693201481
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1830402217
Short name T789
Test name
Test status
Simulation time 41385852262 ps
CPU time 280.81 seconds
Started Jul 11 07:30:12 PM PDT 24
Finished Jul 11 07:34:54 PM PDT 24
Peak memory 2855228 kb
Host smart-46d538d8-96d3-4ef7-816b-6f27efd49073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830402217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1830402217
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3898499791
Short name T1161
Test name
Test status
Simulation time 5538920327 ps
CPU time 5.03 seconds
Started Jul 11 07:30:10 PM PDT 24
Finished Jul 11 07:30:16 PM PDT 24
Peak memory 257500 kb
Host smart-7343916a-0c42-485d-809d-861580543fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898499791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3898499791
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3689634213
Short name T839
Test name
Test status
Simulation time 19489288416 ps
CPU time 7.02 seconds
Started Jul 11 07:30:10 PM PDT 24
Finished Jul 11 07:30:18 PM PDT 24
Peak memory 231864 kb
Host smart-29d4c3e8-e441-4b1c-b4ac-785e30eec602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689634213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3689634213
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1449681272
Short name T1202
Test name
Test status
Simulation time 116721918 ps
CPU time 2.57 seconds
Started Jul 11 07:30:16 PM PDT 24
Finished Jul 11 07:30:21 PM PDT 24
Peak memory 205476 kb
Host smart-fd13dde0-cea5-47ae-91eb-c0fd181941f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449681272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1449681272
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.998891274
Short name T397
Test name
Test status
Simulation time 37498053 ps
CPU time 0.63 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:30:42 PM PDT 24
Peak memory 204800 kb
Host smart-65cf210d-888b-476b-99af-266f69b93ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998891274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.998891274
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3830136597
Short name T1521
Test name
Test status
Simulation time 1693022710 ps
CPU time 2.54 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:30:25 PM PDT 24
Peak memory 220064 kb
Host smart-6a3968be-b870-4be0-b3ad-48592602fa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830136597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3830136597
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2197072879
Short name T1529
Test name
Test status
Simulation time 209571964 ps
CPU time 3.78 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:30:26 PM PDT 24
Peak memory 244160 kb
Host smart-5fca9a56-88b0-48da-838f-7c5e805151fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197072879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2197072879
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.195315008
Short name T509
Test name
Test status
Simulation time 21417202388 ps
CPU time 144.11 seconds
Started Jul 11 07:30:22 PM PDT 24
Finished Jul 11 07:32:48 PM PDT 24
Peak memory 648544 kb
Host smart-8eff7f36-850c-4f4e-aa2f-32ef9878bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195315008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.195315008
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.931028157
Short name T407
Test name
Test status
Simulation time 1820516385 ps
CPU time 53.64 seconds
Started Jul 11 07:30:20 PM PDT 24
Finished Jul 11 07:31:15 PM PDT 24
Peak memory 654792 kb
Host smart-f233bd0f-3669-4a98-9745-5aa2274ddaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931028157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.931028157
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3718895495
Short name T388
Test name
Test status
Simulation time 138573619 ps
CPU time 1.27 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:30:24 PM PDT 24
Peak memory 205300 kb
Host smart-1c36b1da-4b8f-4239-acba-f3c0ab189518
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718895495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3718895495
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4132042835
Short name T787
Test name
Test status
Simulation time 258469396 ps
CPU time 8.12 seconds
Started Jul 11 07:30:23 PM PDT 24
Finished Jul 11 07:30:33 PM PDT 24
Peak memory 228604 kb
Host smart-8c8b1b7a-0974-4e18-bf56-724f8f741eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132042835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4132042835
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3444424266
Short name T1391
Test name
Test status
Simulation time 3526117594 ps
CPU time 97.75 seconds
Started Jul 11 07:30:22 PM PDT 24
Finished Jul 11 07:32:01 PM PDT 24
Peak memory 1044392 kb
Host smart-654ed881-8926-41d3-b37c-2ae1f429ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444424266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3444424266
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2786314221
Short name T681
Test name
Test status
Simulation time 367663586 ps
CPU time 4.76 seconds
Started Jul 11 07:30:30 PM PDT 24
Finished Jul 11 07:30:36 PM PDT 24
Peak memory 205344 kb
Host smart-50c3476f-db3e-4b33-b8b3-9a587a9404d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786314221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2786314221
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.1006294832
Short name T1082
Test name
Test status
Simulation time 25612270 ps
CPU time 0.66 seconds
Started Jul 11 07:30:15 PM PDT 24
Finished Jul 11 07:30:17 PM PDT 24
Peak memory 205180 kb
Host smart-c0621b0b-3274-4250-b1dd-f91d08351922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006294832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1006294832
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3586250107
Short name T821
Test name
Test status
Simulation time 3256032387 ps
CPU time 118.23 seconds
Started Jul 11 07:30:25 PM PDT 24
Finished Jul 11 07:32:24 PM PDT 24
Peak memory 223764 kb
Host smart-09f7a922-61fe-4bea-bb61-49905aa06b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586250107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3586250107
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.1076169951
Short name T987
Test name
Test status
Simulation time 46277063 ps
CPU time 1.35 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:30:23 PM PDT 24
Peak memory 223096 kb
Host smart-01bff98d-86fd-4ce9-adc9-f982845145cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076169951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1076169951
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2717556054
Short name T1478
Test name
Test status
Simulation time 9981246980 ps
CPU time 25.26 seconds
Started Jul 11 07:30:17 PM PDT 24
Finished Jul 11 07:30:44 PM PDT 24
Peak memory 354316 kb
Host smart-12a644cf-fccc-4948-b3d3-48106c8e96b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717556054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2717556054
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3980519447
Short name T279
Test name
Test status
Simulation time 2049010426 ps
CPU time 16.84 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:30:39 PM PDT 24
Peak memory 229788 kb
Host smart-ce2ed62c-935e-43b7-94dd-7a773387400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980519447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3980519447
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3688546879
Short name T392
Test name
Test status
Simulation time 3665398913 ps
CPU time 5.19 seconds
Started Jul 11 07:30:30 PM PDT 24
Finished Jul 11 07:30:37 PM PDT 24
Peak memory 221952 kb
Host smart-fa39fa6c-7f0f-4ccb-aaa6-965070b218c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688546879 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3688546879
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1650316604
Short name T1209
Test name
Test status
Simulation time 174511503 ps
CPU time 0.91 seconds
Started Jul 11 07:30:30 PM PDT 24
Finished Jul 11 07:30:32 PM PDT 24
Peak memory 205372 kb
Host smart-453c8c56-bb86-4e96-b7a4-07dd7b23ef1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650316604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1650316604
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2370384285
Short name T1405
Test name
Test status
Simulation time 205033301 ps
CPU time 0.93 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:30:43 PM PDT 24
Peak memory 205340 kb
Host smart-c30b6db7-b3ac-4af8-b6e1-09dd78224b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370384285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2370384285
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.2183983226
Short name T532
Test name
Test status
Simulation time 743201187 ps
CPU time 2.28 seconds
Started Jul 11 07:30:33 PM PDT 24
Finished Jul 11 07:30:36 PM PDT 24
Peak memory 205396 kb
Host smart-fb6c2999-9c5e-48f3-ae01-59adbe0c8e7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183983226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.2183983226
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.2990914820
Short name T1
Test name
Test status
Simulation time 225145484 ps
CPU time 1.68 seconds
Started Jul 11 07:30:31 PM PDT 24
Finished Jul 11 07:30:35 PM PDT 24
Peak memory 205232 kb
Host smart-65a08247-c87c-4e48-87bd-c32dc84f7838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990914820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.2990914820
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2457488262
Short name T628
Test name
Test status
Simulation time 868392299 ps
CPU time 5.39 seconds
Started Jul 11 07:30:31 PM PDT 24
Finished Jul 11 07:30:38 PM PDT 24
Peak memory 214788 kb
Host smart-c7276d6c-0c19-4080-9cc2-67d740956d0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457488262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2457488262
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.50291928
Short name T1140
Test name
Test status
Simulation time 4998532371 ps
CPU time 43.81 seconds
Started Jul 11 07:30:31 PM PDT 24
Finished Jul 11 07:31:16 PM PDT 24
Peak memory 1254124 kb
Host smart-34bbfd6a-e03e-493a-bb0f-f7fc71371c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50291928 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.50291928
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.1383592781
Short name T1452
Test name
Test status
Simulation time 567047127 ps
CPU time 3.03 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:30:46 PM PDT 24
Peak memory 213708 kb
Host smart-04087e54-2973-4b03-86cc-e981e8864be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383592781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.1383592781
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.966724993
Short name T1436
Test name
Test status
Simulation time 997800519 ps
CPU time 2.31 seconds
Started Jul 11 07:30:39 PM PDT 24
Finished Jul 11 07:30:43 PM PDT 24
Peak memory 205468 kb
Host smart-9919ab1e-d493-4f6a-a4f3-8b71871f7f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966724993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.966724993
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.3785206966
Short name T1042
Test name
Test status
Simulation time 531102302 ps
CPU time 2.52 seconds
Started Jul 11 07:30:29 PM PDT 24
Finished Jul 11 07:30:33 PM PDT 24
Peak memory 205352 kb
Host smart-afc37cef-f81b-48c9-a13f-f5e7f76f0e21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785206966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.3785206966
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2728995818
Short name T1269
Test name
Test status
Simulation time 2767457986 ps
CPU time 8.88 seconds
Started Jul 11 07:30:25 PM PDT 24
Finished Jul 11 07:30:35 PM PDT 24
Peak memory 213976 kb
Host smart-9e672b5f-5e3b-4cf6-bfbe-4cb03cfb0d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728995818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2728995818
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2618402703
Short name T589
Test name
Test status
Simulation time 4514915081 ps
CPU time 30.26 seconds
Started Jul 11 07:30:23 PM PDT 24
Finished Jul 11 07:30:55 PM PDT 24
Peak memory 213832 kb
Host smart-a9c83c02-b4c8-41ee-b4d3-80534e2708a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618402703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2618402703
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3015098584
Short name T481
Test name
Test status
Simulation time 52889362104 ps
CPU time 781.52 seconds
Started Jul 11 07:30:21 PM PDT 24
Finished Jul 11 07:43:24 PM PDT 24
Peak memory 5330124 kb
Host smart-fbbea830-c8e9-4e85-ae52-c4011eeaed93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015098584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3015098584
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.665309244
Short name T1395
Test name
Test status
Simulation time 1105886096 ps
CPU time 10.39 seconds
Started Jul 11 07:30:22 PM PDT 24
Finished Jul 11 07:30:34 PM PDT 24
Peak memory 238212 kb
Host smart-6efc9c49-9e6c-42d4-9ff7-d9f59c147aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665309244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.665309244
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1089942778
Short name T1355
Test name
Test status
Simulation time 2868332931 ps
CPU time 6.67 seconds
Started Jul 11 07:30:34 PM PDT 24
Finished Jul 11 07:30:42 PM PDT 24
Peak memory 230156 kb
Host smart-e1e7ce98-ed61-4450-9429-5f381195ce10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089942778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1089942778
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1868753799
Short name T528
Test name
Test status
Simulation time 50930554 ps
CPU time 1.27 seconds
Started Jul 11 07:30:31 PM PDT 24
Finished Jul 11 07:30:33 PM PDT 24
Peak memory 205476 kb
Host smart-0743843c-0365-48cb-ac4d-767123802fbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868753799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1868753799
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1415927987
Short name T780
Test name
Test status
Simulation time 15286845 ps
CPU time 0.65 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:53 PM PDT 24
Peak memory 204720 kb
Host smart-36ca0094-2325-4910-82bf-b073e8c99591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415927987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1415927987
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.757990329
Short name T16
Test name
Test status
Simulation time 129009587 ps
CPU time 1.29 seconds
Started Jul 11 07:30:38 PM PDT 24
Finished Jul 11 07:30:41 PM PDT 24
Peak memory 213632 kb
Host smart-5764b0cb-aea4-44f0-88e8-c63e20383aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757990329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.757990329
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.660865034
Short name T920
Test name
Test status
Simulation time 228504534 ps
CPU time 11.67 seconds
Started Jul 11 07:30:39 PM PDT 24
Finished Jul 11 07:30:52 PM PDT 24
Peak memory 250160 kb
Host smart-95e83a2b-e873-4858-92b4-2fae79bbb1ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660865034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.660865034
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2996254574
Short name T992
Test name
Test status
Simulation time 6265613543 ps
CPU time 41.19 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:31:24 PM PDT 24
Peak memory 548228 kb
Host smart-82ae43db-7b29-428c-9e07-f2629546b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996254574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2996254574
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1116788600
Short name T1164
Test name
Test status
Simulation time 2135065997 ps
CPU time 147.73 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:33:09 PM PDT 24
Peak memory 708200 kb
Host smart-229ecf7b-6717-475b-9067-974052ce0502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116788600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1116788600
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1737311906
Short name T989
Test name
Test status
Simulation time 260289404 ps
CPU time 0.91 seconds
Started Jul 11 07:30:39 PM PDT 24
Finished Jul 11 07:30:42 PM PDT 24
Peak memory 205160 kb
Host smart-46cb3491-2368-4655-8d53-a19546e08185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737311906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1737311906
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.618869659
Short name T1430
Test name
Test status
Simulation time 661825862 ps
CPU time 5.21 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:30:46 PM PDT 24
Peak memory 236072 kb
Host smart-8e54712f-534a-4cd0-8f3e-9780218e5af6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618869659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
618869659
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1814567409
Short name T625
Test name
Test status
Simulation time 7526365087 ps
CPU time 193.66 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:33:56 PM PDT 24
Peak memory 938816 kb
Host smart-a9ffaace-9704-4e9f-8b24-b1d2188d6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814567409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1814567409
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.571483653
Short name T246
Test name
Test status
Simulation time 574460171 ps
CPU time 3.93 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:56 PM PDT 24
Peak memory 205348 kb
Host smart-1a1449ff-ab80-4278-8af1-dcfda0b3388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571483653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.571483653
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.2717924975
Short name T337
Test name
Test status
Simulation time 41345584 ps
CPU time 0.66 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:30:44 PM PDT 24
Peak memory 205164 kb
Host smart-ebb62b1a-38e2-4a89-a4c6-fd191c4c92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717924975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2717924975
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3813672523
Short name T632
Test name
Test status
Simulation time 6329806294 ps
CPU time 44.78 seconds
Started Jul 11 07:30:40 PM PDT 24
Finished Jul 11 07:31:27 PM PDT 24
Peak memory 213624 kb
Host smart-a178960e-8d7c-432a-9b04-6f8d6baecd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813672523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3813672523
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.445452890
Short name T1253
Test name
Test status
Simulation time 2553330971 ps
CPU time 51.1 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:31:34 PM PDT 24
Peak memory 600624 kb
Host smart-16f1ea98-2c13-4f46-9f46-d53e1abd62fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445452890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.445452890
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2069908079
Short name T1372
Test name
Test status
Simulation time 4697345830 ps
CPU time 21.97 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:31:05 PM PDT 24
Peak memory 345140 kb
Host smart-35ec012f-82dd-41e9-bc3a-afe0901d05df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069908079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2069908079
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.964573547
Short name T438
Test name
Test status
Simulation time 1055458590 ps
CPU time 17.12 seconds
Started Jul 11 07:30:38 PM PDT 24
Finished Jul 11 07:30:56 PM PDT 24
Peak memory 220928 kb
Host smart-18ac98e7-a24d-4689-b53c-642b0b8aa691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964573547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.964573547
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.302751657
Short name T786
Test name
Test status
Simulation time 216389314 ps
CPU time 1.31 seconds
Started Jul 11 07:30:50 PM PDT 24
Finished Jul 11 07:30:54 PM PDT 24
Peak memory 205388 kb
Host smart-ea1e6591-7bbb-49ee-b733-2a5eccb32f58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302751657 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.302751657
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2013588553
Short name T1458
Test name
Test status
Simulation time 214821545 ps
CPU time 1.31 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:52 PM PDT 24
Peak memory 205472 kb
Host smart-d075bb3e-a2be-4890-a928-91e646cec5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013588553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2013588553
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.2562611229
Short name T1480
Test name
Test status
Simulation time 841462640 ps
CPU time 1.86 seconds
Started Jul 11 07:30:47 PM PDT 24
Finished Jul 11 07:30:50 PM PDT 24
Peak memory 205348 kb
Host smart-062184dc-27ac-4749-81d5-d0e0b6dfe610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562611229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.2562611229
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2331380237
Short name T1477
Test name
Test status
Simulation time 204274847 ps
CPU time 1.53 seconds
Started Jul 11 07:30:50 PM PDT 24
Finished Jul 11 07:30:54 PM PDT 24
Peak memory 205364 kb
Host smart-18d7b46b-daa7-4a57-8fc3-edaeb24d4f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331380237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2331380237
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.4172264405
Short name T494
Test name
Test status
Simulation time 3705623255 ps
CPU time 4.61 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:55 PM PDT 24
Peak memory 210184 kb
Host smart-5c42bbde-ba59-40b5-abd0-b10bd8bd5d5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172264405 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.4172264405
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1789572731
Short name T853
Test name
Test status
Simulation time 20683334495 ps
CPU time 14.79 seconds
Started Jul 11 07:30:48 PM PDT 24
Finished Jul 11 07:31:04 PM PDT 24
Peak memory 493852 kb
Host smart-9dfc9a95-eec2-4f66-b3f1-74bdacae437f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789572731 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1789572731
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.2528139032
Short name T60
Test name
Test status
Simulation time 1158468037 ps
CPU time 2.92 seconds
Started Jul 11 07:30:47 PM PDT 24
Finished Jul 11 07:30:51 PM PDT 24
Peak memory 213628 kb
Host smart-c3a868e8-2a4f-4fd4-8e75-ac853b8697fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528139032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.2528139032
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.4195819495
Short name T158
Test name
Test status
Simulation time 437120084 ps
CPU time 2.43 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:31:00 PM PDT 24
Peak memory 205476 kb
Host smart-0e282710-a460-49c5-a1ba-c58a6d0a67a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195819495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.4195819495
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.2996200111
Short name T897
Test name
Test status
Simulation time 2055830910 ps
CPU time 2.4 seconds
Started Jul 11 07:31:03 PM PDT 24
Finished Jul 11 07:31:06 PM PDT 24
Peak memory 205340 kb
Host smart-abcd18c6-50e8-4b93-82ab-21b40f658c05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996200111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.2996200111
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3511775038
Short name T65
Test name
Test status
Simulation time 4037539168 ps
CPU time 12.71 seconds
Started Jul 11 07:30:43 PM PDT 24
Finished Jul 11 07:30:57 PM PDT 24
Peak memory 216572 kb
Host smart-87bc7dcd-f077-43f9-8a30-3f1aececae36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511775038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3511775038
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1383485211
Short name T264
Test name
Test status
Simulation time 7553283575 ps
CPU time 8.2 seconds
Started Jul 11 07:30:41 PM PDT 24
Finished Jul 11 07:30:51 PM PDT 24
Peak memory 220152 kb
Host smart-6b06e8c9-56ac-438d-a41c-5bc2db593915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383485211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1383485211
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2890572663
Short name T1277
Test name
Test status
Simulation time 49211090097 ps
CPU time 526.41 seconds
Started Jul 11 07:30:45 PM PDT 24
Finished Jul 11 07:39:32 PM PDT 24
Peak memory 4644880 kb
Host smart-17877543-7af1-4691-9b8a-d9a0b40ae6e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890572663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2890572663
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3761838737
Short name T1547
Test name
Test status
Simulation time 4108813200 ps
CPU time 39.41 seconds
Started Jul 11 07:30:39 PM PDT 24
Finished Jul 11 07:31:20 PM PDT 24
Peak memory 858936 kb
Host smart-d5b31ca7-3919-49f3-979a-fedc3a0f7196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761838737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3761838737
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4227747205
Short name T1186
Test name
Test status
Simulation time 1461169600 ps
CPU time 7.39 seconds
Started Jul 11 07:30:48 PM PDT 24
Finished Jul 11 07:30:56 PM PDT 24
Peak memory 213696 kb
Host smart-f04e54df-6a62-476b-b485-e86d60792711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227747205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4227747205
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.3396995600
Short name T1403
Test name
Test status
Simulation time 149379437 ps
CPU time 2.48 seconds
Started Jul 11 07:30:50 PM PDT 24
Finished Jul 11 07:30:55 PM PDT 24
Peak memory 205572 kb
Host smart-c5e19276-a2f0-47f0-b315-ea09488ed335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396995600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3396995600
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2208374488
Short name T666
Test name
Test status
Simulation time 22041361 ps
CPU time 0.63 seconds
Started Jul 11 07:23:07 PM PDT 24
Finished Jul 11 07:23:08 PM PDT 24
Peak memory 204724 kb
Host smart-c7c03b22-6a89-437e-b393-af8e9138f700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208374488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2208374488
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.759860780
Short name T733
Test name
Test status
Simulation time 952029584 ps
CPU time 3.64 seconds
Started Jul 11 07:22:43 PM PDT 24
Finished Jul 11 07:22:48 PM PDT 24
Peak memory 213616 kb
Host smart-d383e6d9-6867-4eac-846d-d055b05cb79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759860780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.759860780
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3708445906
Short name T346
Test name
Test status
Simulation time 413404836 ps
CPU time 9.32 seconds
Started Jul 11 07:22:39 PM PDT 24
Finished Jul 11 07:22:50 PM PDT 24
Peak memory 294016 kb
Host smart-960f8804-6fd2-4a41-9155-baea9d1d2024
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708445906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3708445906
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3785406738
Short name T374
Test name
Test status
Simulation time 6072628758 ps
CPU time 107.81 seconds
Started Jul 11 07:22:41 PM PDT 24
Finished Jul 11 07:24:29 PM PDT 24
Peak memory 583672 kb
Host smart-d6a26338-ef9b-4836-9f37-a5c68e8b4881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785406738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3785406738
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.989311540
Short name T1087
Test name
Test status
Simulation time 8236433005 ps
CPU time 149.07 seconds
Started Jul 11 07:22:36 PM PDT 24
Finished Jul 11 07:25:06 PM PDT 24
Peak memory 700316 kb
Host smart-438c4d18-6209-45ca-b108-502e41adaed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989311540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.989311540
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3535122733
Short name T1174
Test name
Test status
Simulation time 221957592 ps
CPU time 1.22 seconds
Started Jul 11 07:22:41 PM PDT 24
Finished Jul 11 07:22:43 PM PDT 24
Peak memory 205276 kb
Host smart-77a2cd49-8ac0-46c6-93e5-6fc31f46dd14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535122733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3535122733
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.992313361
Short name T674
Test name
Test status
Simulation time 148070541 ps
CPU time 8.65 seconds
Started Jul 11 07:22:39 PM PDT 24
Finished Jul 11 07:22:49 PM PDT 24
Peak memory 229792 kb
Host smart-ff625518-44f9-45d8-a705-db7a8d9f3ef9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992313361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.992313361
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4272175768
Short name T1533
Test name
Test status
Simulation time 2570424775 ps
CPU time 141.65 seconds
Started Jul 11 07:22:36 PM PDT 24
Finished Jul 11 07:24:59 PM PDT 24
Peak memory 738068 kb
Host smart-d8494d1c-db6f-4407-9415-9a918500edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272175768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4272175768
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1048008630
Short name T591
Test name
Test status
Simulation time 662113808 ps
CPU time 14.5 seconds
Started Jul 11 07:22:59 PM PDT 24
Finished Jul 11 07:23:14 PM PDT 24
Peak memory 205396 kb
Host smart-947bc6a2-be7d-466a-b29b-b165a8790490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048008630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1048008630
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.507667612
Short name T886
Test name
Test status
Simulation time 19005349 ps
CPU time 0.73 seconds
Started Jul 11 07:22:35 PM PDT 24
Finished Jul 11 07:22:37 PM PDT 24
Peak memory 205140 kb
Host smart-19f3e78d-d331-40a5-9ff1-5553748baf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507667612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.507667612
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2341923268
Short name T574
Test name
Test status
Simulation time 18108162585 ps
CPU time 700.61 seconds
Started Jul 11 07:22:49 PM PDT 24
Finished Jul 11 07:34:30 PM PDT 24
Peak memory 2675316 kb
Host smart-cdc8668f-726c-4aa6-aeac-ca55feec37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341923268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2341923268
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.1385837797
Short name T996
Test name
Test status
Simulation time 109041103 ps
CPU time 1.1 seconds
Started Jul 11 07:22:40 PM PDT 24
Finished Jul 11 07:22:42 PM PDT 24
Peak memory 222744 kb
Host smart-fe154be0-2c5f-44f7-a913-cd8be78cedf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385837797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.1385837797
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3577823485
Short name T689
Test name
Test status
Simulation time 15694354456 ps
CPU time 20.31 seconds
Started Jul 11 07:22:35 PM PDT 24
Finished Jul 11 07:22:56 PM PDT 24
Peak memory 286752 kb
Host smart-185d4e3a-f1ab-42e7-860b-0836af798e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577823485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3577823485
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3695645561
Short name T1549
Test name
Test status
Simulation time 1114162773 ps
CPU time 24.76 seconds
Started Jul 11 07:22:40 PM PDT 24
Finished Jul 11 07:23:05 PM PDT 24
Peak memory 213568 kb
Host smart-306e6956-2fe6-436e-9f06-131f1b66dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695645561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3695645561
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.4045404637
Short name T182
Test name
Test status
Simulation time 68774591 ps
CPU time 0.95 seconds
Started Jul 11 07:23:06 PM PDT 24
Finished Jul 11 07:23:08 PM PDT 24
Peak memory 223564 kb
Host smart-53685af0-92f5-49bd-9428-dd691a8a56cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045404637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.4045404637
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.706310069
Short name T621
Test name
Test status
Simulation time 2101016262 ps
CPU time 5.45 seconds
Started Jul 11 07:22:59 PM PDT 24
Finished Jul 11 07:23:05 PM PDT 24
Peak memory 218640 kb
Host smart-3e209518-46c8-46aa-a66d-c728e3d7c55e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706310069 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.706310069
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2817843738
Short name T1107
Test name
Test status
Simulation time 261419014 ps
CPU time 1.12 seconds
Started Jul 11 07:22:55 PM PDT 24
Finished Jul 11 07:22:56 PM PDT 24
Peak memory 205456 kb
Host smart-09f1d34b-36ea-490f-9629-e08f7d1f333c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817843738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2817843738
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.4236616171
Short name T937
Test name
Test status
Simulation time 317419189 ps
CPU time 0.9 seconds
Started Jul 11 07:22:56 PM PDT 24
Finished Jul 11 07:22:58 PM PDT 24
Peak memory 205348 kb
Host smart-3054783f-776e-4f09-b401-421114348755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236616171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.4236616171
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2358490573
Short name T840
Test name
Test status
Simulation time 250171945 ps
CPU time 1.58 seconds
Started Jul 11 07:23:01 PM PDT 24
Finished Jul 11 07:23:04 PM PDT 24
Peak memory 205348 kb
Host smart-85e57781-52bf-4fff-9211-77d4f14f5fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358490573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2358490573
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1480002640
Short name T1015
Test name
Test status
Simulation time 951414030 ps
CPU time 1.23 seconds
Started Jul 11 07:23:07 PM PDT 24
Finished Jul 11 07:23:09 PM PDT 24
Peak memory 205364 kb
Host smart-bdd57ea6-2ea0-4179-9da9-2ced45ce5bed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480002640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1480002640
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1145659743
Short name T955
Test name
Test status
Simulation time 796545843 ps
CPU time 5.01 seconds
Started Jul 11 07:22:52 PM PDT 24
Finished Jul 11 07:22:58 PM PDT 24
Peak memory 216092 kb
Host smart-86592a08-2e60-469c-b543-bff9fb4cdbcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145659743 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1145659743
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.500488311
Short name T785
Test name
Test status
Simulation time 25316160903 ps
CPU time 797.74 seconds
Started Jul 11 07:22:51 PM PDT 24
Finished Jul 11 07:36:09 PM PDT 24
Peak memory 6188072 kb
Host smart-1e77f5e8-c08c-40b4-b82b-8832fbc99f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500488311 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.500488311
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.3500892036
Short name T979
Test name
Test status
Simulation time 453938684 ps
CPU time 2.95 seconds
Started Jul 11 07:23:05 PM PDT 24
Finished Jul 11 07:23:09 PM PDT 24
Peak memory 213700 kb
Host smart-eef15c48-92a3-4c6a-ad7e-ea5b80f51acd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500892036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.3500892036
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.3458907809
Short name T157
Test name
Test status
Simulation time 7438767496 ps
CPU time 2.26 seconds
Started Jul 11 07:23:06 PM PDT 24
Finished Jul 11 07:23:09 PM PDT 24
Peak memory 205552 kb
Host smart-7161dbd3-9676-4a31-9ff6-4d068e02a9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458907809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.3458907809
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.839637951
Short name T1145
Test name
Test status
Simulation time 645143663 ps
CPU time 2.48 seconds
Started Jul 11 07:22:59 PM PDT 24
Finished Jul 11 07:23:03 PM PDT 24
Peak memory 205316 kb
Host smart-7d458254-d63d-4b58-8c84-197a13677266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839637951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_smbus_maxlen.839637951
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.4236829636
Short name T719
Test name
Test status
Simulation time 2589845492 ps
CPU time 9.96 seconds
Started Jul 11 07:22:47 PM PDT 24
Finished Jul 11 07:22:58 PM PDT 24
Peak memory 213788 kb
Host smart-dde507ed-4641-45d4-a099-b820fbf59db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236829636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.4236829636
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3858900813
Short name T927
Test name
Test status
Simulation time 4211873241 ps
CPU time 51.74 seconds
Started Jul 11 07:22:50 PM PDT 24
Finished Jul 11 07:23:42 PM PDT 24
Peak memory 215652 kb
Host smart-034deb59-98b3-43f1-90f5-3491f16b85b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858900813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3858900813
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2562629555
Short name T1406
Test name
Test status
Simulation time 9987998569 ps
CPU time 21.15 seconds
Started Jul 11 07:22:45 PM PDT 24
Finished Jul 11 07:23:07 PM PDT 24
Peak memory 205540 kb
Host smart-110283d7-b0ce-4717-a0d2-03ace97ede5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562629555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2562629555
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2069807527
Short name T451
Test name
Test status
Simulation time 1243206594 ps
CPU time 6.63 seconds
Started Jul 11 07:23:02 PM PDT 24
Finished Jul 11 07:23:10 PM PDT 24
Peak memory 219912 kb
Host smart-7cdfee14-9def-47d3-b85c-df32cabc2be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069807527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2069807527
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.1955846318
Short name T1256
Test name
Test status
Simulation time 309006876 ps
CPU time 4.53 seconds
Started Jul 11 07:22:59 PM PDT 24
Finished Jul 11 07:23:05 PM PDT 24
Peak memory 205448 kb
Host smart-cf276f66-2dce-4453-bd7a-9fd2d89952c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955846318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1955846318
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1527364623
Short name T1169
Test name
Test status
Simulation time 18265958 ps
CPU time 0.63 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:00 PM PDT 24
Peak memory 204672 kb
Host smart-ce0062a2-08aa-459e-9e73-d75359c6bb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527364623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1527364623
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2243933078
Short name T1131
Test name
Test status
Simulation time 143336484 ps
CPU time 3.37 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:55 PM PDT 24
Peak memory 213640 kb
Host smart-a2d7fb1d-8784-4836-aff9-feb3c6ee4609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243933078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2243933078
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.4085923312
Short name T1300
Test name
Test status
Simulation time 516738042 ps
CPU time 11.23 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:31:03 PM PDT 24
Peak memory 313844 kb
Host smart-8b2e1de9-4718-4b73-aaa6-d10a7c35ad71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085923312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.4085923312
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2989991109
Short name T36
Test name
Test status
Simulation time 26752715745 ps
CPU time 98.25 seconds
Started Jul 11 07:30:48 PM PDT 24
Finished Jul 11 07:32:27 PM PDT 24
Peak memory 771084 kb
Host smart-cb024530-e30e-4df5-bc0e-21f8620075da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989991109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2989991109
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1668518779
Short name T1127
Test name
Test status
Simulation time 12830410363 ps
CPU time 155.03 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:33:27 PM PDT 24
Peak memory 719580 kb
Host smart-856fe5ce-aa2a-4915-be34-406160f1c7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668518779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1668518779
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2002992007
Short name T533
Test name
Test status
Simulation time 290815097 ps
CPU time 1.1 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:52 PM PDT 24
Peak memory 205200 kb
Host smart-d2c45dea-ff79-4cac-9e4d-7286f253c136
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002992007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2002992007
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3981848751
Short name T1559
Test name
Test status
Simulation time 310847762 ps
CPU time 8.45 seconds
Started Jul 11 07:30:51 PM PDT 24
Finished Jul 11 07:31:01 PM PDT 24
Peak memory 205392 kb
Host smart-5ecdc697-acb6-40c2-b17c-d39a178a7ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981848751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3981848751
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3125777918
Short name T1078
Test name
Test status
Simulation time 5693083715 ps
CPU time 151.69 seconds
Started Jul 11 07:30:50 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 1457252 kb
Host smart-5fb0de90-059a-4381-a47a-49589b04bc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125777918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3125777918
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.720823926
Short name T1507
Test name
Test status
Simulation time 1380495912 ps
CPU time 4.35 seconds
Started Jul 11 07:30:54 PM PDT 24
Finished Jul 11 07:31:00 PM PDT 24
Peak memory 205288 kb
Host smart-217829ad-7b62-47d3-be88-3323c190aa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720823926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.720823926
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.3649178020
Short name T561
Test name
Test status
Simulation time 44172325 ps
CPU time 0.69 seconds
Started Jul 11 07:30:48 PM PDT 24
Finished Jul 11 07:30:51 PM PDT 24
Peak memory 205140 kb
Host smart-c719b014-f50c-4b1b-800d-edbefb076526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649178020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3649178020
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3669372853
Short name T1243
Test name
Test status
Simulation time 4846442275 ps
CPU time 27.31 seconds
Started Jul 11 07:30:51 PM PDT 24
Finished Jul 11 07:31:20 PM PDT 24
Peak memory 213632 kb
Host smart-042828c7-18b9-4526-9e79-9a9f2e504966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669372853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3669372853
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.3244027999
Short name T654
Test name
Test status
Simulation time 254973353 ps
CPU time 4.9 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:30:57 PM PDT 24
Peak memory 205228 kb
Host smart-ca984d0d-ce24-4296-a1c4-c691b6aa2310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244027999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3244027999
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2354940310
Short name T359
Test name
Test status
Simulation time 6036273345 ps
CPU time 73.72 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:32:06 PM PDT 24
Peak memory 345540 kb
Host smart-5a896cbc-87f9-403b-86d4-66df897ca2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354940310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2354940310
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.133489816
Short name T774
Test name
Test status
Simulation time 472369866 ps
CPU time 7.83 seconds
Started Jul 11 07:30:48 PM PDT 24
Finished Jul 11 07:30:56 PM PDT 24
Peak memory 221720 kb
Host smart-773a4143-2b68-445f-a09f-c6bdfaf9fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133489816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.133489816
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3064263764
Short name T1079
Test name
Test status
Simulation time 904423658 ps
CPU time 3.31 seconds
Started Jul 11 07:30:58 PM PDT 24
Finished Jul 11 07:31:03 PM PDT 24
Peak memory 220492 kb
Host smart-7947ce77-507c-424b-911c-07bdcbb205ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064263764 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3064263764
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.894743814
Short name T956
Test name
Test status
Simulation time 559477868 ps
CPU time 1.2 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:00 PM PDT 24
Peak memory 205488 kb
Host smart-2ba2351b-6048-45f6-8693-146846fe0b64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894743814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.894743814
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3024506976
Short name T234
Test name
Test status
Simulation time 178114906 ps
CPU time 1.26 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:30:59 PM PDT 24
Peak memory 205484 kb
Host smart-e8000b35-783d-46c8-ad38-e5f20ac51002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024506976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3024506976
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.2787730720
Short name T951
Test name
Test status
Simulation time 344291566 ps
CPU time 2.18 seconds
Started Jul 11 07:31:01 PM PDT 24
Finished Jul 11 07:31:04 PM PDT 24
Peak memory 205580 kb
Host smart-9b4b9a44-ee19-49ea-917f-f128cdeef787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787730720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.2787730720
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.2521818359
Short name T579
Test name
Test status
Simulation time 224146312 ps
CPU time 1.15 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:00 PM PDT 24
Peak memory 205332 kb
Host smart-e1aa7933-d61c-4d89-8617-ce58c3e43466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521818359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.2521818359
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2621576924
Short name T1325
Test name
Test status
Simulation time 3949819930 ps
CPU time 6.08 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:05 PM PDT 24
Peak memory 218536 kb
Host smart-074b1dc3-7c23-4e5a-bf9e-bc35dde28638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621576924 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2621576924
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.567789641
Short name T894
Test name
Test status
Simulation time 19658818551 ps
CPU time 7.96 seconds
Started Jul 11 07:30:54 PM PDT 24
Finished Jul 11 07:31:04 PM PDT 24
Peak memory 315404 kb
Host smart-5da0fbba-bb1c-4a27-a24e-1af7c828d488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567789641 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.567789641
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.563581542
Short name T902
Test name
Test status
Simulation time 545332168 ps
CPU time 3.04 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:03 PM PDT 24
Peak memory 213656 kb
Host smart-8781870a-ed40-4501-a50b-da47da7b28f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563581542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_nack_acqfull.563581542
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.2455659444
Short name T609
Test name
Test status
Simulation time 736923385 ps
CPU time 2.06 seconds
Started Jul 11 07:30:54 PM PDT 24
Finished Jul 11 07:30:58 PM PDT 24
Peak memory 205360 kb
Host smart-1f83111c-cbc0-49ee-9868-04e4a18fa452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455659444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_smbus_maxlen.2455659444
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2679246777
Short name T831
Test name
Test status
Simulation time 4097477362 ps
CPU time 33.25 seconds
Started Jul 11 07:30:49 PM PDT 24
Finished Jul 11 07:31:24 PM PDT 24
Peak memory 213780 kb
Host smart-06a5779b-04bd-4712-9fdd-831d29266cc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679246777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2679246777
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.505067149
Short name T1476
Test name
Test status
Simulation time 6992574156 ps
CPU time 30.37 seconds
Started Jul 11 07:30:56 PM PDT 24
Finished Jul 11 07:31:29 PM PDT 24
Peak memory 248132 kb
Host smart-7d2a2398-61b1-49dd-88f6-ea03caa33d91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505067149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.505067149
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3392299365
Short name T1550
Test name
Test status
Simulation time 37053522131 ps
CPU time 15.79 seconds
Started Jul 11 07:30:50 PM PDT 24
Finished Jul 11 07:31:08 PM PDT 24
Peak memory 399588 kb
Host smart-74933d5e-30f0-4ef9-9f63-55125d90324e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392299365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3392299365
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1195244068
Short name T973
Test name
Test status
Simulation time 1707391577 ps
CPU time 6.14 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:31:04 PM PDT 24
Peak memory 267004 kb
Host smart-1cb2cdfb-3d2d-459a-9112-6a269fbc899c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195244068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1195244068
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3405020528
Short name T678
Test name
Test status
Simulation time 1190482431 ps
CPU time 6.99 seconds
Started Jul 11 07:30:57 PM PDT 24
Finished Jul 11 07:31:06 PM PDT 24
Peak memory 221856 kb
Host smart-2aa533b5-ecc0-4aa1-b3d5-356fcc0dec74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405020528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3405020528
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.354888437
Short name T315
Test name
Test status
Simulation time 332635515 ps
CPU time 4.66 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:31:03 PM PDT 24
Peak memory 205452 kb
Host smart-06ac8633-5c9e-4a91-8357-0362ea2e49f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354888437 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.354888437
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3396837140
Short name T384
Test name
Test status
Simulation time 163393026 ps
CPU time 0.63 seconds
Started Jul 11 07:31:10 PM PDT 24
Finished Jul 11 07:31:13 PM PDT 24
Peak memory 204808 kb
Host smart-2f4c9184-f340-4204-b5fe-6e0273041df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396837140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3396837140
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3711801119
Short name T860
Test name
Test status
Simulation time 1351245673 ps
CPU time 5.31 seconds
Started Jul 11 07:31:06 PM PDT 24
Finished Jul 11 07:31:12 PM PDT 24
Peak memory 247164 kb
Host smart-02536340-623e-4e40-9344-929fc0f5e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711801119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3711801119
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2967124892
Short name T1361
Test name
Test status
Simulation time 339035799 ps
CPU time 6.61 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:31:15 PM PDT 24
Peak memory 271888 kb
Host smart-601d070e-8ede-4101-b2c7-d2765ae508c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967124892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2967124892
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2391155851
Short name T818
Test name
Test status
Simulation time 2598425848 ps
CPU time 86.75 seconds
Started Jul 11 07:31:10 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 776768 kb
Host smart-ee9f940c-da9e-43ee-8ce4-0f6b39584505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391155851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2391155851
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1935023375
Short name T766
Test name
Test status
Simulation time 1278054806 ps
CPU time 84.24 seconds
Started Jul 11 07:31:06 PM PDT 24
Finished Jul 11 07:32:31 PM PDT 24
Peak memory 504064 kb
Host smart-b5fcdb49-8190-46c0-a3b9-0a0b17f91eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935023375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1935023375
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.4135875555
Short name T1019
Test name
Test status
Simulation time 140701269 ps
CPU time 1.28 seconds
Started Jul 11 07:31:06 PM PDT 24
Finished Jul 11 07:31:09 PM PDT 24
Peak memory 205184 kb
Host smart-231e7d1c-8e29-4ea1-abfe-778c26496466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135875555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.4135875555
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1907060652
Short name T564
Test name
Test status
Simulation time 520382523 ps
CPU time 8.6 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:31:18 PM PDT 24
Peak memory 231992 kb
Host smart-768cc66b-97d5-4f53-8cbd-8e0bacb4eaca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907060652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1907060652
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3624055684
Short name T1431
Test name
Test status
Simulation time 2500192913 ps
CPU time 140.58 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:33:30 PM PDT 24
Peak memory 606744 kb
Host smart-5588ba22-68e0-484e-8c54-91b7c7b6df71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624055684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3624055684
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.1153141985
Short name T1208
Test name
Test status
Simulation time 703010391 ps
CPU time 24.3 seconds
Started Jul 11 07:31:14 PM PDT 24
Finished Jul 11 07:31:40 PM PDT 24
Peak memory 205324 kb
Host smart-a4238201-d35f-4e0c-bcf7-10e3a16f291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153141985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1153141985
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.1154072351
Short name T1196
Test name
Test status
Simulation time 25166282 ps
CPU time 0.66 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:30:59 PM PDT 24
Peak memory 205088 kb
Host smart-d60064e4-7c05-4e7d-809d-7d32fd59d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154072351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1154072351
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.716965311
Short name T1422
Test name
Test status
Simulation time 771410896 ps
CPU time 32.78 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:31:42 PM PDT 24
Peak memory 248440 kb
Host smart-e816b47a-c75a-40d2-9561-e5df4f4c3d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716965311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.716965311
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.2818698668
Short name T507
Test name
Test status
Simulation time 2588841508 ps
CPU time 45.86 seconds
Started Jul 11 07:31:08 PM PDT 24
Finished Jul 11 07:31:55 PM PDT 24
Peak memory 420744 kb
Host smart-338580b1-f202-48cf-bfcc-4b4dd786e459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818698668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2818698668
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3385081411
Short name T1524
Test name
Test status
Simulation time 1743867665 ps
CPU time 34.46 seconds
Started Jul 11 07:30:55 PM PDT 24
Finished Jul 11 07:31:33 PM PDT 24
Peak memory 355460 kb
Host smart-55194d33-8c64-4390-9e44-bb8b6ade3340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385081411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3385081411
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1544205475
Short name T1194
Test name
Test status
Simulation time 1512560790 ps
CPU time 31.39 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:31:45 PM PDT 24
Peak memory 213532 kb
Host smart-62e6e95c-8b6c-4389-820c-88698b07531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544205475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1544205475
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2811276801
Short name T1508
Test name
Test status
Simulation time 4034671352 ps
CPU time 7.2 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:31:21 PM PDT 24
Peak memory 220804 kb
Host smart-0a1214d8-2f9c-4563-b0fe-8b1d8f415ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811276801 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2811276801
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1300036992
Short name T655
Test name
Test status
Simulation time 174870400 ps
CPU time 1.12 seconds
Started Jul 11 07:31:08 PM PDT 24
Finished Jul 11 07:31:11 PM PDT 24
Peak memory 205364 kb
Host smart-59934147-6df0-45c8-a5bd-6ed238cf69cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300036992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1300036992
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3891949944
Short name T166
Test name
Test status
Simulation time 241607242 ps
CPU time 1.69 seconds
Started Jul 11 07:31:08 PM PDT 24
Finished Jul 11 07:31:11 PM PDT 24
Peak memory 205364 kb
Host smart-2aa7ab9c-3a2f-4b6a-9f95-39fb779349a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891949944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3891949944
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2603813145
Short name T1094
Test name
Test status
Simulation time 735061694 ps
CPU time 2.27 seconds
Started Jul 11 07:31:11 PM PDT 24
Finished Jul 11 07:31:16 PM PDT 24
Peak memory 205440 kb
Host smart-7d111ef8-9c93-4704-9c07-470010c7ccac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603813145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2603813145
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.3368170761
Short name T5
Test name
Test status
Simulation time 87038143 ps
CPU time 0.83 seconds
Started Jul 11 07:31:11 PM PDT 24
Finished Jul 11 07:31:14 PM PDT 24
Peak memory 205320 kb
Host smart-09272a97-39d8-4e58-9a8b-be3f52624464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368170761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.3368170761
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.136927170
Short name T1207
Test name
Test status
Simulation time 1940441043 ps
CPU time 5.18 seconds
Started Jul 11 07:31:08 PM PDT 24
Finished Jul 11 07:31:15 PM PDT 24
Peak memory 213692 kb
Host smart-b63aa0d8-5b2e-4c43-a6cf-8d2cbb82860b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136927170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.136927170
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.31186477
Short name T211
Test name
Test status
Simulation time 19847229910 ps
CPU time 46.87 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:32:01 PM PDT 24
Peak memory 777224 kb
Host smart-6b7ef6db-534a-43cf-ba55-81e10fecd3c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186477 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.31186477
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.844383976
Short name T971
Test name
Test status
Simulation time 476222275 ps
CPU time 2.8 seconds
Started Jul 11 07:31:14 PM PDT 24
Finished Jul 11 07:31:19 PM PDT 24
Peak memory 213684 kb
Host smart-06ec728c-d7f9-4a2c-b440-32feae52e0bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844383976 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_nack_acqfull.844383976
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.1717514871
Short name T1071
Test name
Test status
Simulation time 1205465775 ps
CPU time 3.02 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:31:17 PM PDT 24
Peak memory 205504 kb
Host smart-b7ae89d6-aa74-4e46-8627-9fe55f6e03fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717514871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.1717514871
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.1249603507
Short name T1053
Test name
Test status
Simulation time 530552709 ps
CPU time 2.34 seconds
Started Jul 11 07:31:13 PM PDT 24
Finished Jul 11 07:31:18 PM PDT 24
Peak memory 205352 kb
Host smart-975e5cb8-cecc-4908-b677-de4d07bf25ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249603507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.1249603507
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.591909652
Short name T832
Test name
Test status
Simulation time 1400179406 ps
CPU time 20.83 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:31:30 PM PDT 24
Peak memory 213732 kb
Host smart-d8679eed-4dab-4853-8625-4f24dc5f4923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591909652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.591909652
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.234979540
Short name T921
Test name
Test status
Simulation time 796092737 ps
CPU time 13.45 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:31:22 PM PDT 24
Peak memory 210348 kb
Host smart-c3f8fd94-2cc2-4939-a619-cb4b3a392904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234979540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.234979540
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.908391219
Short name T1558
Test name
Test status
Simulation time 46222972650 ps
CPU time 243.67 seconds
Started Jul 11 07:31:07 PM PDT 24
Finished Jul 11 07:35:13 PM PDT 24
Peak memory 2501068 kb
Host smart-eae5e8a5-8ac5-4dd1-843d-1d1daa5b8465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908391219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_wr.908391219
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1264745648
Short name T756
Test name
Test status
Simulation time 3332053220 ps
CPU time 3.83 seconds
Started Jul 11 07:31:10 PM PDT 24
Finished Jul 11 07:31:15 PM PDT 24
Peak memory 205468 kb
Host smart-edd54189-a3bb-45e5-8e8d-6841cc74fab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264745648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1264745648
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1483010800
Short name T500
Test name
Test status
Simulation time 1193524195 ps
CPU time 6.27 seconds
Started Jul 11 07:31:13 PM PDT 24
Finished Jul 11 07:31:21 PM PDT 24
Peak memory 221836 kb
Host smart-e8cda120-f76b-4c03-b2c1-272964c22d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483010800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1483010800
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1368829488
Short name T759
Test name
Test status
Simulation time 158384155 ps
CPU time 2.71 seconds
Started Jul 11 07:31:14 PM PDT 24
Finished Jul 11 07:31:19 PM PDT 24
Peak memory 205432 kb
Host smart-d4c0ea6c-68e1-4fe5-ad89-b11082e22da6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368829488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1368829488
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3275220611
Short name T1290
Test name
Test status
Simulation time 17234808 ps
CPU time 0.65 seconds
Started Jul 11 07:31:29 PM PDT 24
Finished Jul 11 07:31:31 PM PDT 24
Peak memory 204800 kb
Host smart-bc8beaec-d3ba-4853-92ac-dcaa1d8f20da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275220611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3275220611
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.772201829
Short name T635
Test name
Test status
Simulation time 150692148 ps
CPU time 1.74 seconds
Started Jul 11 07:31:16 PM PDT 24
Finished Jul 11 07:31:19 PM PDT 24
Peak memory 213696 kb
Host smart-26975a71-312f-41c6-8c12-ede5fc2f141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772201829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.772201829
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3668180510
Short name T1213
Test name
Test status
Simulation time 2012647412 ps
CPU time 26.09 seconds
Started Jul 11 07:31:11 PM PDT 24
Finished Jul 11 07:31:39 PM PDT 24
Peak memory 302564 kb
Host smart-fc2427eb-38e2-4f12-80b6-f0999f7ba4c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668180510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3668180510
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.439234639
Short name T900
Test name
Test status
Simulation time 6715332650 ps
CPU time 93.32 seconds
Started Jul 11 07:31:17 PM PDT 24
Finished Jul 11 07:32:52 PM PDT 24
Peak memory 292652 kb
Host smart-5c8e4cff-0dca-48e8-8440-36955a069238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439234639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.439234639
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3154438907
Short name T960
Test name
Test status
Simulation time 7543447604 ps
CPU time 68.66 seconds
Started Jul 11 07:31:14 PM PDT 24
Finished Jul 11 07:32:24 PM PDT 24
Peak memory 678416 kb
Host smart-fdddcf32-8ee5-4a09-a3af-392f8a0de659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154438907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3154438907
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1907025003
Short name T387
Test name
Test status
Simulation time 86319546 ps
CPU time 0.97 seconds
Started Jul 11 07:31:10 PM PDT 24
Finished Jul 11 07:31:12 PM PDT 24
Peak memory 205184 kb
Host smart-3067f455-e774-4e19-900f-31eeaa1aa9ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907025003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1907025003
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2392304664
Short name T907
Test name
Test status
Simulation time 125597869 ps
CPU time 3.3 seconds
Started Jul 11 07:31:13 PM PDT 24
Finished Jul 11 07:31:18 PM PDT 24
Peak memory 225176 kb
Host smart-6a8109a2-da54-471d-a14b-4f005b4ac009
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392304664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2392304664
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.4233414686
Short name T465
Test name
Test status
Simulation time 5006811190 ps
CPU time 293.03 seconds
Started Jul 11 07:31:11 PM PDT 24
Finished Jul 11 07:36:06 PM PDT 24
Peak memory 1218156 kb
Host smart-d334bd18-e2e5-4f9f-b064-b474b2e90692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233414686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.4233414686
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2401938189
Short name T250
Test name
Test status
Simulation time 960331909 ps
CPU time 12.69 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:36 PM PDT 24
Peak memory 205344 kb
Host smart-f2e16156-8b37-486e-b303-f789b0b2c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401938189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2401938189
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.1885358496
Short name T597
Test name
Test status
Simulation time 33314062 ps
CPU time 0.66 seconds
Started Jul 11 07:31:14 PM PDT 24
Finished Jul 11 07:31:17 PM PDT 24
Peak memory 205136 kb
Host smart-77f9c4b3-cc45-4c24-8d17-8de7a8a2a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885358496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1885358496
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3299019567
Short name T441
Test name
Test status
Simulation time 472942299 ps
CPU time 2.91 seconds
Started Jul 11 07:31:17 PM PDT 24
Finished Jul 11 07:31:22 PM PDT 24
Peak memory 229880 kb
Host smart-fe04e96f-faf0-47a6-83ff-5b6142687fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299019567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3299019567
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.4168824012
Short name T1500
Test name
Test status
Simulation time 100820572 ps
CPU time 1.34 seconds
Started Jul 11 07:31:13 PM PDT 24
Finished Jul 11 07:31:17 PM PDT 24
Peak memory 222768 kb
Host smart-aed9b310-d112-400b-a83e-0b26898bed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168824012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.4168824012
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.940461595
Short name T1288
Test name
Test status
Simulation time 3961863064 ps
CPU time 48.18 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:32:02 PM PDT 24
Peak memory 302920 kb
Host smart-db91dc52-79a6-4d5a-9e74-c7a8e80f61b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940461595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.940461595
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1275771975
Short name T680
Test name
Test status
Simulation time 4046855167 ps
CPU time 44.84 seconds
Started Jul 11 07:31:12 PM PDT 24
Finished Jul 11 07:31:59 PM PDT 24
Peak memory 221700 kb
Host smart-7288b3a3-d652-409b-bea9-2ba216df72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275771975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1275771975
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.564225469
Short name T1072
Test name
Test status
Simulation time 1939081158 ps
CPU time 5.21 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:29 PM PDT 24
Peak memory 218708 kb
Host smart-ee6d2046-2a79-4db0-869c-57a72be44ff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564225469 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.564225469
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4008384842
Short name T434
Test name
Test status
Simulation time 430552253 ps
CPU time 1.11 seconds
Started Jul 11 07:31:23 PM PDT 24
Finished Jul 11 07:31:26 PM PDT 24
Peak memory 205404 kb
Host smart-2df4126b-a72e-4de6-b1f4-574644457385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008384842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.4008384842
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3647141794
Short name T950
Test name
Test status
Simulation time 322737327 ps
CPU time 1.12 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:24 PM PDT 24
Peak memory 205324 kb
Host smart-40afc2f4-16a8-40ce-8bba-89eab6053d53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647141794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3647141794
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.90775599
Short name T1250
Test name
Test status
Simulation time 502563344 ps
CPU time 2.65 seconds
Started Jul 11 07:31:23 PM PDT 24
Finished Jul 11 07:31:27 PM PDT 24
Peak memory 205548 kb
Host smart-59f3089a-a12f-4df1-8ec6-7b86c0e53dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90775599 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.90775599
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.1310891297
Short name T1272
Test name
Test status
Simulation time 122490550 ps
CPU time 1.15 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:25 PM PDT 24
Peak memory 205388 kb
Host smart-75763cd6-4f3a-47ce-a98e-9832eadaf6de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310891297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.1310891297
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2728815140
Short name T443
Test name
Test status
Simulation time 2844374852 ps
CPU time 4.25 seconds
Started Jul 11 07:31:16 PM PDT 24
Finished Jul 11 07:31:22 PM PDT 24
Peak memory 221900 kb
Host smart-98eafcf9-dc3c-4a58-a3d8-b624f4aa779e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728815140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2728815140
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.185648216
Short name T802
Test name
Test status
Simulation time 3886042533 ps
CPU time 33.69 seconds
Started Jul 11 07:31:17 PM PDT 24
Finished Jul 11 07:31:52 PM PDT 24
Peak memory 1068676 kb
Host smart-7656510b-4104-4859-8a01-c97076c009be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185648216 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.185648216
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.3099925976
Short name T1257
Test name
Test status
Simulation time 1843932861 ps
CPU time 2.75 seconds
Started Jul 11 07:31:25 PM PDT 24
Finished Jul 11 07:31:28 PM PDT 24
Peak memory 213764 kb
Host smart-3562d260-a000-480f-849e-15312b714dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099925976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.3099925976
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.2663643275
Short name T1553
Test name
Test status
Simulation time 1621263818 ps
CPU time 2.28 seconds
Started Jul 11 07:31:28 PM PDT 24
Finished Jul 11 07:31:31 PM PDT 24
Peak memory 205404 kb
Host smart-567d28b7-4bc2-4394-aa58-707fbb338d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663643275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.2663643275
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.2792754310
Short name T1101
Test name
Test status
Simulation time 474276997 ps
CPU time 2.24 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:25 PM PDT 24
Peak memory 205304 kb
Host smart-9518abc4-eaf4-488d-9f4a-22d9d4eea716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792754310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.2792754310
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1140397969
Short name T864
Test name
Test status
Simulation time 1377267171 ps
CPU time 21.78 seconds
Started Jul 11 07:31:16 PM PDT 24
Finished Jul 11 07:31:40 PM PDT 24
Peak memory 213664 kb
Host smart-62c6bbea-30fa-4bd2-b390-add70c255290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140397969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1140397969
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.4029540214
Short name T1319
Test name
Test status
Simulation time 2451022562 ps
CPU time 9.58 seconds
Started Jul 11 07:31:17 PM PDT 24
Finished Jul 11 07:31:28 PM PDT 24
Peak memory 220428 kb
Host smart-bd3a5c47-735e-4762-992e-c34d6040848c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029540214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.4029540214
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1776318432
Short name T997
Test name
Test status
Simulation time 57137272090 ps
CPU time 549.55 seconds
Started Jul 11 07:31:17 PM PDT 24
Finished Jul 11 07:40:28 PM PDT 24
Peak memory 4454808 kb
Host smart-bb76b5d5-7534-47d7-86b5-2df763771287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776318432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1776318432
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.264996998
Short name T769
Test name
Test status
Simulation time 1267082648 ps
CPU time 6.92 seconds
Started Jul 11 07:31:15 PM PDT 24
Finished Jul 11 07:31:24 PM PDT 24
Peak memory 213800 kb
Host smart-913cc31e-2f9a-4357-9da3-210877da91f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264996998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.264996998
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.3552212322
Short name T538
Test name
Test status
Simulation time 455750759 ps
CPU time 6.04 seconds
Started Jul 11 07:31:22 PM PDT 24
Finished Jul 11 07:31:30 PM PDT 24
Peak memory 213624 kb
Host smart-24dadf57-b250-438c-b113-4033c8d560fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552212322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.3552212322
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.603888891
Short name T760
Test name
Test status
Simulation time 21606133 ps
CPU time 0.64 seconds
Started Jul 11 07:31:41 PM PDT 24
Finished Jul 11 07:31:43 PM PDT 24
Peak memory 204796 kb
Host smart-5b2f6a59-5cb1-47a9-8f2d-875b8bcf2555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603888891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.603888891
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.4105632660
Short name T1024
Test name
Test status
Simulation time 558553517 ps
CPU time 2.61 seconds
Started Jul 11 07:31:36 PM PDT 24
Finished Jul 11 07:31:39 PM PDT 24
Peak memory 213632 kb
Host smart-2b0b7409-d158-4494-967f-6facb310d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105632660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4105632660
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.925869229
Short name T390
Test name
Test status
Simulation time 280494774 ps
CPU time 4.98 seconds
Started Jul 11 07:31:33 PM PDT 24
Finished Jul 11 07:31:39 PM PDT 24
Peak memory 257048 kb
Host smart-8641139a-2fff-4ced-9c0a-93b0d8c166e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925869229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.925869229
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3656868908
Short name T1171
Test name
Test status
Simulation time 30459955533 ps
CPU time 149.91 seconds
Started Jul 11 07:31:27 PM PDT 24
Finished Jul 11 07:33:58 PM PDT 24
Peak memory 739976 kb
Host smart-f8d62ae1-9b85-485d-ae5e-47dbadc030ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656868908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3656868908
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2916193518
Short name T420
Test name
Test status
Simulation time 11173345718 ps
CPU time 157.61 seconds
Started Jul 11 07:31:28 PM PDT 24
Finished Jul 11 07:34:08 PM PDT 24
Peak memory 698992 kb
Host smart-6df003dd-5942-402d-a139-b260f8b70e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916193518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2916193518
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2103545832
Short name T237
Test name
Test status
Simulation time 95923216 ps
CPU time 1.09 seconds
Started Jul 11 07:31:32 PM PDT 24
Finished Jul 11 07:31:34 PM PDT 24
Peak memory 205188 kb
Host smart-251f6dfe-ca39-4991-9f06-f73073f39f49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103545832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2103545832
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3757524452
Short name T353
Test name
Test status
Simulation time 193243951 ps
CPU time 3.87 seconds
Started Jul 11 07:31:27 PM PDT 24
Finished Jul 11 07:31:32 PM PDT 24
Peak memory 205400 kb
Host smart-69ece0ea-f9b4-4fc9-a3f1-e92b11b01265
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757524452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3757524452
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.693985509
Short name T313
Test name
Test status
Simulation time 5444767094 ps
CPU time 164.39 seconds
Started Jul 11 07:31:27 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 1500728 kb
Host smart-f04a7ccd-46ae-4dad-87a7-7d6ea73dfb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693985509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.693985509
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2052015728
Short name T251
Test name
Test status
Simulation time 1108828923 ps
CPU time 6.76 seconds
Started Jul 11 07:31:33 PM PDT 24
Finished Jul 11 07:31:41 PM PDT 24
Peak memory 205380 kb
Host smart-74e5590a-e6cc-4361-98e6-6e8b32aca7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052015728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2052015728
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.13307432
Short name T985
Test name
Test status
Simulation time 51829146 ps
CPU time 0.68 seconds
Started Jul 11 07:31:28 PM PDT 24
Finished Jul 11 07:31:30 PM PDT 24
Peak memory 205092 kb
Host smart-ad3146c4-11ac-486c-8d45-9887dcb58323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13307432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.13307432
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3383537085
Short name T620
Test name
Test status
Simulation time 4468151264 ps
CPU time 180.19 seconds
Started Jul 11 07:31:38 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 205408 kb
Host smart-fff600f7-fb59-49a2-8f0b-6432227751f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383537085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3383537085
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.528336855
Short name T737
Test name
Test status
Simulation time 235858917 ps
CPU time 9.28 seconds
Started Jul 11 07:31:26 PM PDT 24
Finished Jul 11 07:31:36 PM PDT 24
Peak memory 205172 kb
Host smart-c3222b52-f01d-43d1-87b5-8d3ab6e5837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528336855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.528336855
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3709278563
Short name T942
Test name
Test status
Simulation time 2383710306 ps
CPU time 52.77 seconds
Started Jul 11 07:31:33 PM PDT 24
Finished Jul 11 07:32:27 PM PDT 24
Peak memory 493736 kb
Host smart-4e4841c4-17a9-4152-b1d5-091c0e91f1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709278563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3709278563
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.3031859335
Short name T751
Test name
Test status
Simulation time 919718670 ps
CPU time 13.18 seconds
Started Jul 11 07:31:38 PM PDT 24
Finished Jul 11 07:31:51 PM PDT 24
Peak memory 221672 kb
Host smart-7427cd94-8dcd-4669-a523-0bb543c4b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031859335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3031859335
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3192835391
Short name T1177
Test name
Test status
Simulation time 3857101887 ps
CPU time 5.03 seconds
Started Jul 11 07:31:38 PM PDT 24
Finished Jul 11 07:31:44 PM PDT 24
Peak memory 213852 kb
Host smart-8c88a31e-fad2-4f47-9fa6-5ea588e1e7da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192835391 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3192835391
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1431058543
Short name T168
Test name
Test status
Simulation time 211130163 ps
CPU time 1.39 seconds
Started Jul 11 07:31:34 PM PDT 24
Finished Jul 11 07:31:37 PM PDT 24
Peak memory 205392 kb
Host smart-e2ec9fdb-d29d-48fc-bf3e-c624a931eaa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431058543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1431058543
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.4065906622
Short name T549
Test name
Test status
Simulation time 456609284 ps
CPU time 0.95 seconds
Started Jul 11 07:31:35 PM PDT 24
Finished Jul 11 07:31:37 PM PDT 24
Peak memory 205400 kb
Host smart-7f0355dc-5193-42b4-9142-b0e797406e9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065906622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.4065906622
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3245171918
Short name T1449
Test name
Test status
Simulation time 357728848 ps
CPU time 2.16 seconds
Started Jul 11 07:31:37 PM PDT 24
Finished Jul 11 07:31:40 PM PDT 24
Peak memory 205452 kb
Host smart-8be274fa-fa91-47ac-a58f-b5955e7093ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245171918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3245171918
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.1963139697
Short name T1274
Test name
Test status
Simulation time 342462049 ps
CPU time 1.65 seconds
Started Jul 11 07:31:36 PM PDT 24
Finished Jul 11 07:31:38 PM PDT 24
Peak memory 205404 kb
Host smart-5eab50cb-9479-4a38-b2a7-ab9189c585d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963139697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.1963139697
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.746957675
Short name T1048
Test name
Test status
Simulation time 1053642772 ps
CPU time 6.68 seconds
Started Jul 11 07:31:37 PM PDT 24
Finished Jul 11 07:31:44 PM PDT 24
Peak memory 218352 kb
Host smart-60d1b40a-9c08-401d-9f21-f15d882cac61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746957675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.746957675
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.4234696849
Short name T284
Test name
Test status
Simulation time 7791498138 ps
CPU time 102.19 seconds
Started Jul 11 07:32:03 PM PDT 24
Finished Jul 11 07:33:46 PM PDT 24
Peak memory 1986296 kb
Host smart-744fd90f-30ea-44a8-9155-8373dd6898a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234696849 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.4234696849
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2467209956
Short name T649
Test name
Test status
Simulation time 3759735137 ps
CPU time 2.61 seconds
Started Jul 11 07:31:35 PM PDT 24
Finished Jul 11 07:31:39 PM PDT 24
Peak memory 213752 kb
Host smart-6b7177d0-a07a-462b-b458-471d6c382f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467209956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2467209956
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.2580618468
Short name T709
Test name
Test status
Simulation time 771847577 ps
CPU time 2.62 seconds
Started Jul 11 07:31:39 PM PDT 24
Finished Jul 11 07:31:43 PM PDT 24
Peak memory 205780 kb
Host smart-4470b2b4-4e33-44fb-a506-11a515a06dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580618468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.2580618468
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.3129886080
Short name T320
Test name
Test status
Simulation time 3394558672 ps
CPU time 2.25 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:44 PM PDT 24
Peak memory 205404 kb
Host smart-df413fdb-202c-4c39-8675-5ca902c1ef33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129886080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.3129886080
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1898270736
Short name T417
Test name
Test status
Simulation time 655346405 ps
CPU time 7.7 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:49 PM PDT 24
Peak memory 213712 kb
Host smart-a5ed21f3-a9a0-4e8e-b6c9-8145e0a1d1c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898270736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1898270736
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.616818145
Short name T1049
Test name
Test status
Simulation time 4223018255 ps
CPU time 17.17 seconds
Started Jul 11 07:31:33 PM PDT 24
Finished Jul 11 07:31:51 PM PDT 24
Peak memory 205564 kb
Host smart-982768a1-287e-4443-9167-0c51580381c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616818145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.616818145
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2557194519
Short name T1022
Test name
Test status
Simulation time 46025995327 ps
CPU time 1035.64 seconds
Started Jul 11 07:31:35 PM PDT 24
Finished Jul 11 07:48:52 PM PDT 24
Peak memory 6673656 kb
Host smart-0adbb1fc-81be-48de-a99f-5311762391d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557194519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2557194519
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3119330453
Short name T671
Test name
Test status
Simulation time 4172787692 ps
CPU time 44.94 seconds
Started Jul 11 07:31:34 PM PDT 24
Finished Jul 11 07:32:20 PM PDT 24
Peak memory 804316 kb
Host smart-e2259596-d2f8-476b-920c-ed624afe42cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119330453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3119330453
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.4027757119
Short name T1068
Test name
Test status
Simulation time 2748043729 ps
CPU time 7.77 seconds
Started Jul 11 07:31:35 PM PDT 24
Finished Jul 11 07:31:43 PM PDT 24
Peak memory 221904 kb
Host smart-44016342-5b35-4b11-9d62-cb9886b05951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027757119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.4027757119
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.894716599
Short name T1233
Test name
Test status
Simulation time 269675255 ps
CPU time 3.89 seconds
Started Jul 11 07:31:32 PM PDT 24
Finished Jul 11 07:31:37 PM PDT 24
Peak memory 214588 kb
Host smart-5db74e9a-7ca6-43f5-9830-b5f93de118a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894716599 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.894716599
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1032553932
Short name T1347
Test name
Test status
Simulation time 42282406 ps
CPU time 0.63 seconds
Started Jul 11 07:31:50 PM PDT 24
Finished Jul 11 07:31:53 PM PDT 24
Peak memory 204684 kb
Host smart-efccb336-6b76-4841-87d9-31b53250bd08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032553932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1032553932
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1284629352
Short name T1219
Test name
Test status
Simulation time 411604259 ps
CPU time 2.08 seconds
Started Jul 11 07:31:39 PM PDT 24
Finished Jul 11 07:31:42 PM PDT 24
Peak memory 219856 kb
Host smart-cb4d47e1-9090-42f4-b89a-b6c2b5e89ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284629352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1284629352
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2789189064
Short name T1534
Test name
Test status
Simulation time 1297717547 ps
CPU time 17.44 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:58 PM PDT 24
Peak memory 277916 kb
Host smart-3b55f206-a361-40d9-8013-e1cd000a0d09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789189064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2789189064
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2202073992
Short name T328
Test name
Test status
Simulation time 35047296561 ps
CPU time 184.62 seconds
Started Jul 11 07:31:38 PM PDT 24
Finished Jul 11 07:34:44 PM PDT 24
Peak memory 657480 kb
Host smart-433c00d8-f152-4c97-87eb-06ded0321d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202073992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2202073992
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1802579944
Short name T27
Test name
Test status
Simulation time 16041185234 ps
CPU time 170.24 seconds
Started Jul 11 07:31:39 PM PDT 24
Finished Jul 11 07:34:30 PM PDT 24
Peak memory 737564 kb
Host smart-e18ae7d8-679c-4782-87ea-ca2d11c95fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802579944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1802579944
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1657839197
Short name T974
Test name
Test status
Simulation time 232531205 ps
CPU time 1.14 seconds
Started Jul 11 07:31:42 PM PDT 24
Finished Jul 11 07:31:45 PM PDT 24
Peak memory 205144 kb
Host smart-243b260f-e1a7-4d37-b8ab-811c048c808b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657839197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1657839197
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1206703918
Short name T1551
Test name
Test status
Simulation time 193533349 ps
CPU time 10.72 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:31:58 PM PDT 24
Peak memory 241140 kb
Host smart-2e9e3132-f263-4c48-a933-53d410c3bb9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206703918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1206703918
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3613811100
Short name T1479
Test name
Test status
Simulation time 3135550296 ps
CPU time 207.63 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:35:12 PM PDT 24
Peak memory 953684 kb
Host smart-896b1d46-84e3-4ffd-b69f-2ac564ef5daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613811100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3613811100
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3514516665
Short name T1163
Test name
Test status
Simulation time 1316972321 ps
CPU time 13.2 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:32:00 PM PDT 24
Peak memory 205324 kb
Host smart-3221b518-ac4b-4775-a0e0-872287469e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514516665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3514516665
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.149675803
Short name T1227
Test name
Test status
Simulation time 57801650 ps
CPU time 0.68 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:41 PM PDT 24
Peak memory 205132 kb
Host smart-652091ab-7fca-4c54-854c-003189d911f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149675803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.149675803
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1840089853
Short name T38
Test name
Test status
Simulation time 12482141352 ps
CPU time 23.58 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:32:11 PM PDT 24
Peak memory 205628 kb
Host smart-ed7ddee9-8816-4535-97ba-30856621d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840089853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1840089853
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.3054803919
Short name T1036
Test name
Test status
Simulation time 95016564 ps
CPU time 1.99 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:31:49 PM PDT 24
Peak memory 206248 kb
Host smart-8c43f872-10c1-414c-b4af-debe30e743e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054803919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3054803919
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3262124330
Short name T1211
Test name
Test status
Simulation time 2779147678 ps
CPU time 34.09 seconds
Started Jul 11 07:31:39 PM PDT 24
Finished Jul 11 07:32:15 PM PDT 24
Peak memory 390124 kb
Host smart-a73ee045-6e55-4e8d-aba1-47a90e3519f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262124330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3262124330
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3133216516
Short name T910
Test name
Test status
Simulation time 1842042379 ps
CPU time 10.33 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:31:55 PM PDT 24
Peak memory 216684 kb
Host smart-58ea04ce-f312-435d-83da-808760b499f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133216516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3133216516
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3914275051
Short name T1475
Test name
Test status
Simulation time 1385111300 ps
CPU time 6.87 seconds
Started Jul 11 07:31:44 PM PDT 24
Finished Jul 11 07:31:52 PM PDT 24
Peak memory 221816 kb
Host smart-1377740d-6aa9-4c68-a502-a5306af7116a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914275051 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3914275051
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2252749370
Short name T1000
Test name
Test status
Simulation time 263553879 ps
CPU time 1.54 seconds
Started Jul 11 07:31:41 PM PDT 24
Finished Jul 11 07:31:44 PM PDT 24
Peak memory 206008 kb
Host smart-68762a54-5010-4dbc-9078-2bae45600978
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252749370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2252749370
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.268700336
Short name T550
Test name
Test status
Simulation time 266724095 ps
CPU time 1.06 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:31:46 PM PDT 24
Peak memory 205400 kb
Host smart-a6555fbd-aa1f-46db-85ec-2e83a1c5d99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268700336 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.268700336
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3501168319
Short name T881
Test name
Test status
Simulation time 299749797 ps
CPU time 1.83 seconds
Started Jul 11 07:31:51 PM PDT 24
Finished Jul 11 07:31:55 PM PDT 24
Peak memory 205564 kb
Host smart-b314de19-20ac-4bb6-9199-5a817a4883b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501168319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3501168319
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1056551756
Short name T612
Test name
Test status
Simulation time 165076877 ps
CPU time 1.52 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:31:48 PM PDT 24
Peak memory 205304 kb
Host smart-ab4eb8c1-dee4-49ff-b26e-3a24e4249542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056551756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1056551756
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.317946486
Short name T87
Test name
Test status
Simulation time 1211189793 ps
CPU time 7.82 seconds
Started Jul 11 07:31:41 PM PDT 24
Finished Jul 11 07:31:50 PM PDT 24
Peak memory 218208 kb
Host smart-65f0f923-f1f8-46ad-ba8c-0ca05c0e1e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317946486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.317946486
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.873194857
Short name T1206
Test name
Test status
Simulation time 12681177106 ps
CPU time 210.4 seconds
Started Jul 11 07:31:45 PM PDT 24
Finished Jul 11 07:35:17 PM PDT 24
Peak memory 3033100 kb
Host smart-616b81fb-e133-4553-bfba-1ab8f8594bc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873194857 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.873194857
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.3367388122
Short name T1359
Test name
Test status
Simulation time 1667995708 ps
CPU time 2.55 seconds
Started Jul 11 07:31:46 PM PDT 24
Finished Jul 11 07:31:50 PM PDT 24
Peak memory 213712 kb
Host smart-c947510f-445c-4187-9939-ed306ab45a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367388122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.3367388122
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.1940892638
Short name T85
Test name
Test status
Simulation time 521529077 ps
CPU time 2.61 seconds
Started Jul 11 07:31:53 PM PDT 24
Finished Jul 11 07:31:57 PM PDT 24
Peak memory 205500 kb
Host smart-81bde70c-15ae-40a1-ae30-74d459fcf8f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940892638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.1940892638
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.175545234
Short name T1090
Test name
Test status
Simulation time 490349228 ps
CPU time 2.28 seconds
Started Jul 11 07:31:45 PM PDT 24
Finished Jul 11 07:31:48 PM PDT 24
Peak memory 205360 kb
Host smart-e505cef3-2bfa-4022-a31b-997256e80582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175545234 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_smbus_maxlen.175545234
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.787420098
Short name T712
Test name
Test status
Simulation time 3112102052 ps
CPU time 15.48 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:57 PM PDT 24
Peak memory 213800 kb
Host smart-4e87c6e5-c3d4-4838-a266-3937dba6ad1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787420098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.787420098
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1125724269
Short name T811
Test name
Test status
Simulation time 2826990141 ps
CPU time 65.97 seconds
Started Jul 11 07:31:38 PM PDT 24
Finished Jul 11 07:32:45 PM PDT 24
Peak memory 216628 kb
Host smart-b80c8d56-7ab2-4b0b-a44b-9ea41dc348dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125724269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1125724269
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1857624650
Short name T833
Test name
Test status
Simulation time 23837381501 ps
CPU time 16.22 seconds
Started Jul 11 07:31:40 PM PDT 24
Finished Jul 11 07:31:57 PM PDT 24
Peak memory 340076 kb
Host smart-6765d9e1-0df4-4ff4-a2c1-2ce4e16e30f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857624650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1857624650
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.601447840
Short name T784
Test name
Test status
Simulation time 2574454801 ps
CPU time 3.29 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:31:48 PM PDT 24
Peak memory 267840 kb
Host smart-8fea288b-dd48-4ad0-91dc-3b6491a84d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601447840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.601447840
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.967606648
Short name T1230
Test name
Test status
Simulation time 1605299081 ps
CPU time 8.21 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:31:53 PM PDT 24
Peak memory 218340 kb
Host smart-8380fae5-2652-4cc6-985f-fafe009defad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967606648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.967606648
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.1845504643
Short name T565
Test name
Test status
Simulation time 59354190 ps
CPU time 1.14 seconds
Started Jul 11 07:31:43 PM PDT 24
Finished Jul 11 07:31:46 PM PDT 24
Peak memory 205480 kb
Host smart-6b7443f4-05a4-484d-9abf-272617830254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845504643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.1845504643
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3836846615
Short name T482
Test name
Test status
Simulation time 21317861 ps
CPU time 0.66 seconds
Started Jul 11 07:31:55 PM PDT 24
Finished Jul 11 07:31:57 PM PDT 24
Peak memory 204764 kb
Host smart-7fdf90b2-c900-46eb-bc56-97ff0daa26dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836846615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3836846615
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2760854367
Short name T20
Test name
Test status
Simulation time 3762739785 ps
CPU time 7.74 seconds
Started Jul 11 07:31:50 PM PDT 24
Finished Jul 11 07:31:59 PM PDT 24
Peak memory 235312 kb
Host smart-e83148ad-ec16-4356-a5ea-f03154b8747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760854367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2760854367
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.267000702
Short name T1425
Test name
Test status
Simulation time 2256604342 ps
CPU time 32.25 seconds
Started Jul 11 07:31:52 PM PDT 24
Finished Jul 11 07:32:26 PM PDT 24
Peak memory 342192 kb
Host smart-c91a07ca-8df9-49c1-8cfd-23b850779b9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267000702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.267000702
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2686158780
Short name T1305
Test name
Test status
Simulation time 4870153110 ps
CPU time 76.94 seconds
Started Jul 11 07:31:52 PM PDT 24
Finished Jul 11 07:33:11 PM PDT 24
Peak memory 801088 kb
Host smart-20724d0b-9cc9-4afe-bad0-755ee3f70146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686158780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2686158780
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1855052083
Short name T901
Test name
Test status
Simulation time 2701425000 ps
CPU time 104.25 seconds
Started Jul 11 07:31:53 PM PDT 24
Finished Jul 11 07:33:39 PM PDT 24
Peak memory 874524 kb
Host smart-6d8e59e8-a734-4eb4-92fa-5e6e9a93910a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855052083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1855052083
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1709908795
Short name T31
Test name
Test status
Simulation time 97156312 ps
CPU time 0.93 seconds
Started Jul 11 07:31:52 PM PDT 24
Finished Jul 11 07:31:55 PM PDT 24
Peak memory 205160 kb
Host smart-7f762dac-a841-47de-add0-28b0693ebe2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709908795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1709908795
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3829077583
Short name T454
Test name
Test status
Simulation time 162059508 ps
CPU time 3.46 seconds
Started Jul 11 07:31:53 PM PDT 24
Finished Jul 11 07:31:58 PM PDT 24
Peak memory 205312 kb
Host smart-428ee72b-0b18-42c3-9882-e3a13dcb8909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829077583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3829077583
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1579936279
Short name T1393
Test name
Test status
Simulation time 16367997178 ps
CPU time 104.29 seconds
Started Jul 11 07:31:53 PM PDT 24
Finished Jul 11 07:33:38 PM PDT 24
Peak memory 1072848 kb
Host smart-1abd26f7-2c15-41f9-b23a-015fb59a0c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579936279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1579936279
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_override.2402614559
Short name T585
Test name
Test status
Simulation time 46909481 ps
CPU time 0.71 seconds
Started Jul 11 07:31:52 PM PDT 24
Finished Jul 11 07:31:54 PM PDT 24
Peak memory 205160 kb
Host smart-1b3446a1-8d3b-4c86-b08e-7a2d0ac25c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402614559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2402614559
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1607319629
Short name T535
Test name
Test status
Simulation time 543955139 ps
CPU time 9.3 seconds
Started Jul 11 07:31:52 PM PDT 24
Finished Jul 11 07:32:03 PM PDT 24
Peak memory 263232 kb
Host smart-c1278d46-2853-46d0-8784-2a011b1a86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607319629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1607319629
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.1627465991
Short name T427
Test name
Test status
Simulation time 245184426 ps
CPU time 2.73 seconds
Started Jul 11 07:31:51 PM PDT 24
Finished Jul 11 07:31:56 PM PDT 24
Peak memory 220772 kb
Host smart-a62df32a-23ce-44fe-865d-13c0aa0a1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627465991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.1627465991
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1969730884
Short name T547
Test name
Test status
Simulation time 8482040757 ps
CPU time 31.83 seconds
Started Jul 11 07:31:51 PM PDT 24
Finished Jul 11 07:32:25 PM PDT 24
Peak memory 361816 kb
Host smart-6aef20b1-7078-4981-a36a-15b63a5b7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969730884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1969730884
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.266361717
Short name T444
Test name
Test status
Simulation time 2292701394 ps
CPU time 15.45 seconds
Started Jul 11 07:31:54 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 219508 kb
Host smart-e16e423a-14b0-46b0-bebd-e0a4c754d241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266361717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.266361717
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3324043098
Short name T367
Test name
Test status
Simulation time 918875785 ps
CPU time 5.84 seconds
Started Jul 11 07:31:59 PM PDT 24
Finished Jul 11 07:32:06 PM PDT 24
Peak memory 219520 kb
Host smart-804104a2-4fa8-451f-9d4a-14b7f0bf88d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324043098 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3324043098
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1121982875
Short name T848
Test name
Test status
Simulation time 276224083 ps
CPU time 1.56 seconds
Started Jul 11 07:31:58 PM PDT 24
Finished Jul 11 07:32:00 PM PDT 24
Peak memory 206908 kb
Host smart-d66eef89-bad1-4ce3-af84-9c8a9b3a4838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121982875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1121982875
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2721073827
Short name T880
Test name
Test status
Simulation time 663747229 ps
CPU time 1.07 seconds
Started Jul 11 07:31:58 PM PDT 24
Finished Jul 11 07:32:00 PM PDT 24
Peak memory 205476 kb
Host smart-e216fa6a-9d7c-4da8-9eb9-8e02dfea5a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721073827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2721073827
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1511058092
Short name T530
Test name
Test status
Simulation time 483158902 ps
CPU time 2.81 seconds
Started Jul 11 07:31:57 PM PDT 24
Finished Jul 11 07:32:00 PM PDT 24
Peak memory 205492 kb
Host smart-4b1f295e-ca56-443e-9fbe-2f858ccaade5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511058092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1511058092
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2736936759
Short name T169
Test name
Test status
Simulation time 571295408 ps
CPU time 1.31 seconds
Started Jul 11 07:31:59 PM PDT 24
Finished Jul 11 07:32:02 PM PDT 24
Peak memory 205372 kb
Host smart-fc7833d2-1bdb-4ba9-8892-fcce20459255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736936759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2736936759
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.480430925
Short name T355
Test name
Test status
Simulation time 2749961732 ps
CPU time 5.19 seconds
Started Jul 11 07:31:56 PM PDT 24
Finished Jul 11 07:32:02 PM PDT 24
Peak memory 221920 kb
Host smart-bbc1cf20-8287-4ee5-908c-43f2f27b204b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480430925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.480430925
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2548501497
Short name T713
Test name
Test status
Simulation time 3680945735 ps
CPU time 6.98 seconds
Started Jul 11 07:31:59 PM PDT 24
Finished Jul 11 07:32:07 PM PDT 24
Peak memory 400776 kb
Host smart-4357223f-41dd-44f1-ad68-97bfec20ab53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548501497 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2548501497
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.122955310
Short name T757
Test name
Test status
Simulation time 599989757 ps
CPU time 3.17 seconds
Started Jul 11 07:32:01 PM PDT 24
Finished Jul 11 07:32:05 PM PDT 24
Peak memory 213728 kb
Host smart-81c792c8-f210-40c5-8b65-bfa0702e1ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122955310 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_nack_acqfull.122955310
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.2438565155
Short name T1383
Test name
Test status
Simulation time 1040104278 ps
CPU time 2.45 seconds
Started Jul 11 07:31:55 PM PDT 24
Finished Jul 11 07:31:58 PM PDT 24
Peak memory 205504 kb
Host smart-e700abb3-4a36-4e41-86d5-7ef6bb4f2196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438565155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.2438565155
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.1274745446
Short name T1512
Test name
Test status
Simulation time 2035895650 ps
CPU time 2.29 seconds
Started Jul 11 07:32:00 PM PDT 24
Finished Jul 11 07:32:03 PM PDT 24
Peak memory 205364 kb
Host smart-0296e01d-e528-4322-b553-59e1a70d1f73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274745446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.1274745446
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3661483246
Short name T770
Test name
Test status
Simulation time 1011535354 ps
CPU time 12.53 seconds
Started Jul 11 07:31:54 PM PDT 24
Finished Jul 11 07:32:07 PM PDT 24
Peak memory 213676 kb
Host smart-0796f66b-a43c-4ee8-a835-42ceb341d649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661483246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3661483246
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1418959708
Short name T1335
Test name
Test status
Simulation time 4890901605 ps
CPU time 51.67 seconds
Started Jul 11 07:31:59 PM PDT 24
Finished Jul 11 07:32:52 PM PDT 24
Peak memory 215284 kb
Host smart-2825b860-5632-4271-be43-06ba43250109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418959708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1418959708
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.795365272
Short name T1471
Test name
Test status
Simulation time 359805464 ps
CPU time 9.65 seconds
Started Jul 11 07:31:59 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 237536 kb
Host smart-f41726d7-8b9e-43b4-8e9a-e64e1724a96b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795365272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.795365272
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1626636257
Short name T869
Test name
Test status
Simulation time 1267223708 ps
CPU time 7.36 seconds
Started Jul 11 07:31:56 PM PDT 24
Finished Jul 11 07:32:04 PM PDT 24
Peak memory 229968 kb
Host smart-b4e9dbc1-e36d-47c5-b597-58fff0c36685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626636257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1626636257
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2955493432
Short name T536
Test name
Test status
Simulation time 126242913 ps
CPU time 3.04 seconds
Started Jul 11 07:31:58 PM PDT 24
Finished Jul 11 07:32:02 PM PDT 24
Peak memory 205992 kb
Host smart-632e9126-8b96-46e0-bb8d-46b124a22811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955493432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2955493432
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.153569098
Short name T619
Test name
Test status
Simulation time 17810491 ps
CPU time 0.66 seconds
Started Jul 11 07:32:09 PM PDT 24
Finished Jul 11 07:32:12 PM PDT 24
Peak memory 204716 kb
Host smart-2fb59a21-ebf4-4666-a7e7-a6ca90f86c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153569098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.153569098
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.820226002
Short name T1419
Test name
Test status
Simulation time 661887311 ps
CPU time 4.71 seconds
Started Jul 11 07:32:02 PM PDT 24
Finished Jul 11 07:32:08 PM PDT 24
Peak memory 221716 kb
Host smart-a5d9eebb-864a-4b5d-89b3-c433dac9979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820226002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.820226002
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.4108346974
Short name T1159
Test name
Test status
Simulation time 1445954557 ps
CPU time 8.06 seconds
Started Jul 11 07:32:03 PM PDT 24
Finished Jul 11 07:32:12 PM PDT 24
Peak memory 279572 kb
Host smart-81b63b03-193b-4712-ac2d-0dbfc80c083d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108346974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.4108346974
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.3730979002
Short name T80
Test name
Test status
Simulation time 1967439758 ps
CPU time 141.05 seconds
Started Jul 11 07:32:05 PM PDT 24
Finished Jul 11 07:34:27 PM PDT 24
Peak memory 686368 kb
Host smart-e984dede-e22b-4c46-95be-cc16530115f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730979002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.3730979002
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.4139264868
Short name T908
Test name
Test status
Simulation time 5081272438 ps
CPU time 78.22 seconds
Started Jul 11 07:32:02 PM PDT 24
Finished Jul 11 07:33:22 PM PDT 24
Peak memory 438528 kb
Host smart-720e00da-7ba4-46c1-913d-707f2bb797d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139264868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.4139264868
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1656246304
Short name T235
Test name
Test status
Simulation time 135800614 ps
CPU time 1.16 seconds
Started Jul 11 07:32:05 PM PDT 24
Finished Jul 11 07:32:07 PM PDT 24
Peak memory 205184 kb
Host smart-3bb7aea0-a80d-42fd-8396-45dada9ce379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656246304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1656246304
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.791912011
Short name T636
Test name
Test status
Simulation time 428567549 ps
CPU time 2.72 seconds
Started Jul 11 07:32:06 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 205340 kb
Host smart-b66336d2-deb8-409d-954a-3415bed3322c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791912011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
791912011
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2781591258
Short name T109
Test name
Test status
Simulation time 3688978893 ps
CPU time 85.34 seconds
Started Jul 11 07:32:02 PM PDT 24
Finished Jul 11 07:33:29 PM PDT 24
Peak memory 1086232 kb
Host smart-ffc03460-158d-4538-9799-d9db0388f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781591258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2781591258
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1346954647
Short name T11
Test name
Test status
Simulation time 1638951378 ps
CPU time 6.55 seconds
Started Jul 11 07:32:14 PM PDT 24
Finished Jul 11 07:32:21 PM PDT 24
Peak memory 205352 kb
Host smart-424e7d65-2083-467e-bb83-73ced7927b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346954647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1346954647
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.4139074977
Short name T1511
Test name
Test status
Simulation time 47405217 ps
CPU time 0.67 seconds
Started Jul 11 07:32:04 PM PDT 24
Finished Jul 11 07:32:05 PM PDT 24
Peak memory 205076 kb
Host smart-e16d7b73-535a-4cac-ba7e-d63e3a282d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139074977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.4139074977
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2142165672
Short name T1291
Test name
Test status
Simulation time 4706036480 ps
CPU time 66.6 seconds
Started Jul 11 07:32:05 PM PDT 24
Finished Jul 11 07:33:13 PM PDT 24
Peak memory 227656 kb
Host smart-0ceb1471-1cde-4b02-aab0-15ae03fbe5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142165672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2142165672
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.2496447820
Short name T1315
Test name
Test status
Simulation time 479630828 ps
CPU time 1.02 seconds
Started Jul 11 07:32:06 PM PDT 24
Finished Jul 11 07:32:09 PM PDT 24
Peak memory 213428 kb
Host smart-2301ea84-1cb1-4c88-8905-37855feee252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496447820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2496447820
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3340148078
Short name T1472
Test name
Test status
Simulation time 1521079939 ps
CPU time 72.51 seconds
Started Jul 11 07:32:02 PM PDT 24
Finished Jul 11 07:33:15 PM PDT 24
Peak memory 359696 kb
Host smart-49509101-6f67-4edb-a4c4-8d92d9cf4117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340148078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3340148078
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1509445326
Short name T863
Test name
Test status
Simulation time 1363268231 ps
CPU time 6 seconds
Started Jul 11 07:32:07 PM PDT 24
Finished Jul 11 07:32:14 PM PDT 24
Peak memory 213680 kb
Host smart-c503e41b-b305-4da3-bdd7-4a00668b0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509445326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1509445326
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.913649957
Short name T476
Test name
Test status
Simulation time 2709879526 ps
CPU time 6.69 seconds
Started Jul 11 07:32:08 PM PDT 24
Finished Jul 11 07:32:17 PM PDT 24
Peak memory 213816 kb
Host smart-3fd2e6ca-3839-461b-9b5d-7e7216ef3d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913649957 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.913649957
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.47229693
Short name T232
Test name
Test status
Simulation time 345045326 ps
CPU time 0.84 seconds
Started Jul 11 07:32:08 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 205376 kb
Host smart-812b5e45-8747-4c25-87f7-920f6cc5eaf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47229693 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_acq.47229693
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.4180544365
Short name T302
Test name
Test status
Simulation time 155864551 ps
CPU time 0.91 seconds
Started Jul 11 07:32:09 PM PDT 24
Finished Jul 11 07:32:12 PM PDT 24
Peak memory 205364 kb
Host smart-69fecc61-917a-48e9-9f64-d9b40b04601e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180544365 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.4180544365
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2733659514
Short name T1212
Test name
Test status
Simulation time 540530540 ps
CPU time 2.66 seconds
Started Jul 11 07:32:10 PM PDT 24
Finished Jul 11 07:32:14 PM PDT 24
Peak memory 205524 kb
Host smart-1c568c2d-5b4a-48db-b241-db9fc31ff46b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733659514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2733659514
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.873539012
Short name T776
Test name
Test status
Simulation time 135118779 ps
CPU time 1.41 seconds
Started Jul 11 07:32:10 PM PDT 24
Finished Jul 11 07:32:13 PM PDT 24
Peak memory 205364 kb
Host smart-00932c78-f7b9-4d04-9d17-5efa89969022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873539012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.873539012
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3289279501
Short name T512
Test name
Test status
Simulation time 1593942861 ps
CPU time 5.14 seconds
Started Jul 11 07:32:04 PM PDT 24
Finished Jul 11 07:32:10 PM PDT 24
Peak memory 221856 kb
Host smart-2d37948a-74eb-4579-aefc-82fa46e9b056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289279501 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3289279501
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3644188862
Short name T52
Test name
Test status
Simulation time 13533235133 ps
CPU time 26 seconds
Started Jul 11 07:32:09 PM PDT 24
Finished Jul 11 07:32:36 PM PDT 24
Peak memory 557264 kb
Host smart-38705f91-d195-4583-a84f-51a975de3907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644188862 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3644188862
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.734985728
Short name T1496
Test name
Test status
Simulation time 590258655 ps
CPU time 2.84 seconds
Started Jul 11 07:32:08 PM PDT 24
Finished Jul 11 07:32:12 PM PDT 24
Peak memory 213672 kb
Host smart-77788421-bf9a-4ada-b0d3-28b0ba55da7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734985728 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_nack_acqfull.734985728
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.994591257
Short name T55
Test name
Test status
Simulation time 1534709036 ps
CPU time 2.31 seconds
Started Jul 11 07:32:10 PM PDT 24
Finished Jul 11 07:32:14 PM PDT 24
Peak memory 205496 kb
Host smart-c59f4dc1-c4c0-4662-a71c-9520235b11f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994591257 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.994591257
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.1502378120
Short name T885
Test name
Test status
Simulation time 2026042831 ps
CPU time 2.39 seconds
Started Jul 11 07:32:08 PM PDT 24
Finished Jul 11 07:32:11 PM PDT 24
Peak memory 205308 kb
Host smart-0a14b6e9-d697-4a23-ac4e-0e420ac0b330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502378120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.1502378120
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3850682350
Short name T1408
Test name
Test status
Simulation time 1418788622 ps
CPU time 17.51 seconds
Started Jul 11 07:32:06 PM PDT 24
Finished Jul 11 07:32:24 PM PDT 24
Peak memory 213680 kb
Host smart-e41e4990-e753-4453-b8ce-65142a41a238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850682350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3850682350
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3304547606
Short name T1073
Test name
Test status
Simulation time 862626893 ps
CPU time 39.04 seconds
Started Jul 11 07:32:02 PM PDT 24
Finished Jul 11 07:32:43 PM PDT 24
Peak memory 213748 kb
Host smart-63e76b71-f310-4394-a0a6-5a7c5fc2df12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304547606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3304547606
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3731285736
Short name T1516
Test name
Test status
Simulation time 40668819262 ps
CPU time 75.99 seconds
Started Jul 11 07:32:03 PM PDT 24
Finished Jul 11 07:33:20 PM PDT 24
Peak memory 1237828 kb
Host smart-11c73123-5c24-41a8-8e8b-7acbbc7f2804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731285736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3731285736
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1817281874
Short name T1276
Test name
Test status
Simulation time 1031597556 ps
CPU time 16.12 seconds
Started Jul 11 07:32:06 PM PDT 24
Finished Jul 11 07:32:24 PM PDT 24
Peak memory 274760 kb
Host smart-edccd308-2080-4c8e-8834-66a39edba159
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817281874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1817281874
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1266637198
Short name T981
Test name
Test status
Simulation time 4479042429 ps
CPU time 6.83 seconds
Started Jul 11 07:32:09 PM PDT 24
Finished Jul 11 07:32:17 PM PDT 24
Peak memory 213736 kb
Host smart-41f17a46-68eb-4c09-9c20-97e5faa28796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266637198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1266637198
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.3073669616
Short name T1011
Test name
Test status
Simulation time 54277337 ps
CPU time 1.32 seconds
Started Jul 11 07:32:10 PM PDT 24
Finished Jul 11 07:32:13 PM PDT 24
Peak memory 205480 kb
Host smart-b72f641a-d4c1-4856-9905-cbaf9d4bcfa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073669616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.3073669616
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2253175022
Short name T690
Test name
Test status
Simulation time 46560962 ps
CPU time 0.62 seconds
Started Jul 11 07:32:20 PM PDT 24
Finished Jul 11 07:32:22 PM PDT 24
Peak memory 204712 kb
Host smart-34c083eb-92ce-42e6-b674-e1320e237840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253175022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2253175022
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1337514848
Short name T17
Test name
Test status
Simulation time 74565993 ps
CPU time 1.12 seconds
Started Jul 11 07:32:14 PM PDT 24
Finished Jul 11 07:32:16 PM PDT 24
Peak memory 205424 kb
Host smart-b931bbc1-1bf1-4648-8f3c-5053a9460594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337514848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1337514848
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2023206971
Short name T1531
Test name
Test status
Simulation time 910708842 ps
CPU time 24.79 seconds
Started Jul 11 07:32:16 PM PDT 24
Finished Jul 11 07:32:42 PM PDT 24
Peak memory 291876 kb
Host smart-170c0e32-4b3a-41d0-b586-339c2a36cf24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023206971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2023206971
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.981906167
Short name T658
Test name
Test status
Simulation time 3440067977 ps
CPU time 62.9 seconds
Started Jul 11 07:32:16 PM PDT 24
Finished Jul 11 07:33:19 PM PDT 24
Peak memory 642496 kb
Host smart-14d79a4a-133a-4f43-9441-1096375405e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981906167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.981906167
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3360960382
Short name T576
Test name
Test status
Simulation time 519526138 ps
CPU time 1.12 seconds
Started Jul 11 07:32:16 PM PDT 24
Finished Jul 11 07:32:18 PM PDT 24
Peak memory 205164 kb
Host smart-05153614-c1b0-418b-8610-1799af2a3ff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360960382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3360960382
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3825635603
Short name T529
Test name
Test status
Simulation time 255313369 ps
CPU time 4.72 seconds
Started Jul 11 07:32:14 PM PDT 24
Finished Jul 11 07:32:19 PM PDT 24
Peak memory 234240 kb
Host smart-008bca06-f0fc-41da-9867-8d05b32d5ed5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825635603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3825635603
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.371851267
Short name T851
Test name
Test status
Simulation time 19391159858 ps
CPU time 123.64 seconds
Started Jul 11 07:32:15 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 1341476 kb
Host smart-2dd187c9-d672-4cc7-a063-8267e9767550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371851267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.371851267
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3074862610
Short name T1357
Test name
Test status
Simulation time 894350181 ps
CPU time 9.59 seconds
Started Jul 11 07:32:20 PM PDT 24
Finished Jul 11 07:32:30 PM PDT 24
Peak memory 205340 kb
Host smart-52daaf2f-9ab1-4ce5-8b96-09379cb27e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074862610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3074862610
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_override.3717778773
Short name T1519
Test name
Test status
Simulation time 34130937 ps
CPU time 0.69 seconds
Started Jul 11 07:32:15 PM PDT 24
Finished Jul 11 07:32:17 PM PDT 24
Peak memory 205084 kb
Host smart-e7cf1506-c64c-4689-b793-4a3b48ea1ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717778773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3717778773
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.4093466223
Short name T796
Test name
Test status
Simulation time 6154820309 ps
CPU time 69.81 seconds
Started Jul 11 07:32:14 PM PDT 24
Finished Jul 11 07:33:25 PM PDT 24
Peak memory 837136 kb
Host smart-0858bf0e-2a96-4b86-80e1-229a3c40980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093466223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.4093466223
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3327090662
Short name T1562
Test name
Test status
Simulation time 1577105724 ps
CPU time 28.45 seconds
Started Jul 11 07:32:12 PM PDT 24
Finished Jul 11 07:32:42 PM PDT 24
Peak memory 313536 kb
Host smart-757a37bb-5771-4cbc-aa49-2bf13677f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327090662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3327090662
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1313380126
Short name T926
Test name
Test status
Simulation time 1095385429 ps
CPU time 10.73 seconds
Started Jul 11 07:32:17 PM PDT 24
Finished Jul 11 07:32:28 PM PDT 24
Peak memory 214644 kb
Host smart-14c2e6ae-87ae-4478-8f15-1820476280b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313380126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1313380126
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1278473779
Short name T1141
Test name
Test status
Simulation time 1178483865 ps
CPU time 6.37 seconds
Started Jul 11 07:32:24 PM PDT 24
Finished Jul 11 07:32:32 PM PDT 24
Peak memory 219412 kb
Host smart-345e1277-d2d0-42eb-8274-94aba26c4407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278473779 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1278473779
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1019045263
Short name T1506
Test name
Test status
Simulation time 184432577 ps
CPU time 1.13 seconds
Started Jul 11 07:32:22 PM PDT 24
Finished Jul 11 07:32:25 PM PDT 24
Peak memory 205436 kb
Host smart-9b7312f4-4788-472e-9140-73956e187374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019045263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1019045263
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3228511377
Short name T339
Test name
Test status
Simulation time 286369139 ps
CPU time 1.67 seconds
Started Jul 11 07:32:20 PM PDT 24
Finished Jul 11 07:32:23 PM PDT 24
Peak memory 207664 kb
Host smart-b64647c0-a131-4f07-9f08-9f03565583fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228511377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3228511377
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.804060445
Short name T1146
Test name
Test status
Simulation time 669643781 ps
CPU time 2.36 seconds
Started Jul 11 07:32:21 PM PDT 24
Finished Jul 11 07:32:24 PM PDT 24
Peak memory 205476 kb
Host smart-9ad8c589-5c1e-4d24-a105-ef964a1bc4f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804060445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.804060445
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.95107465
Short name T290
Test name
Test status
Simulation time 240115047 ps
CPU time 0.87 seconds
Started Jul 11 07:32:18 PM PDT 24
Finished Jul 11 07:32:20 PM PDT 24
Peak memory 205372 kb
Host smart-10e53799-7db3-4903-ab90-36fcbb489ff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95107465 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.95107465
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3647950210
Short name T710
Test name
Test status
Simulation time 20260943062 ps
CPU time 8.76 seconds
Started Jul 11 07:32:19 PM PDT 24
Finished Jul 11 07:32:29 PM PDT 24
Peak memory 221976 kb
Host smart-a199081d-d636-4f7b-9161-6138e2bc5bc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647950210 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3647950210
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.581466438
Short name T412
Test name
Test status
Simulation time 11536569585 ps
CPU time 19.22 seconds
Started Jul 11 07:32:24 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 596580 kb
Host smart-1609f114-7fa4-4324-b20b-c57d509ce158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581466438 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.581466438
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.2748313078
Short name T1157
Test name
Test status
Simulation time 1133733235 ps
CPU time 2.69 seconds
Started Jul 11 07:32:20 PM PDT 24
Finished Jul 11 07:32:23 PM PDT 24
Peak memory 213648 kb
Host smart-34e6b2b7-a691-401d-96e6-a7f45efabf26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748313078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.2748313078
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.2630139380
Short name T54
Test name
Test status
Simulation time 544502451 ps
CPU time 2.53 seconds
Started Jul 11 07:32:21 PM PDT 24
Finished Jul 11 07:32:25 PM PDT 24
Peak memory 206472 kb
Host smart-16d68a0d-c078-4ddc-a167-ffe5b95c1c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630139380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.2630139380
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.3170852224
Short name T708
Test name
Test status
Simulation time 478412960 ps
CPU time 2.33 seconds
Started Jul 11 07:32:19 PM PDT 24
Finished Jul 11 07:32:22 PM PDT 24
Peak memory 205360 kb
Host smart-d324c51c-7362-45c1-872c-06fabd321b58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170852224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.3170852224
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1230398450
Short name T977
Test name
Test status
Simulation time 2163868853 ps
CPU time 7.94 seconds
Started Jul 11 07:32:16 PM PDT 24
Finished Jul 11 07:32:25 PM PDT 24
Peak memory 216284 kb
Host smart-a9d8115a-11bd-41f7-a84c-d3ba6a7bcb1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230398450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1230398450
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.301369716
Short name T189
Test name
Test status
Simulation time 1613347387 ps
CPU time 13.84 seconds
Started Jul 11 07:32:22 PM PDT 24
Finished Jul 11 07:32:37 PM PDT 24
Peak memory 216932 kb
Host smart-fddad9a3-6290-49c5-98f8-c552453b4e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301369716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.301369716
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1084251994
Short name T146
Test name
Test status
Simulation time 24599945747 ps
CPU time 20.86 seconds
Started Jul 11 07:32:15 PM PDT 24
Finished Jul 11 07:32:36 PM PDT 24
Peak memory 415364 kb
Host smart-183af3a1-9730-42d3-93f7-375b06bd7899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084251994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1084251994
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.4053327802
Short name T1003
Test name
Test status
Simulation time 915567587 ps
CPU time 2.45 seconds
Started Jul 11 07:32:14 PM PDT 24
Finished Jul 11 07:32:17 PM PDT 24
Peak memory 205356 kb
Host smart-781d22bd-ae09-419b-8917-a3d1cbd3d130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053327802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.4053327802
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2575962446
Short name T570
Test name
Test status
Simulation time 4104956423 ps
CPU time 6.31 seconds
Started Jul 11 07:32:21 PM PDT 24
Finished Jul 11 07:32:29 PM PDT 24
Peak memory 221884 kb
Host smart-c62d3539-72ac-47bd-aa98-e282d9b653fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575962446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2575962446
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.3939449903
Short name T326
Test name
Test status
Simulation time 375117139 ps
CPU time 5.15 seconds
Started Jul 11 07:32:22 PM PDT 24
Finished Jul 11 07:32:28 PM PDT 24
Peak memory 205476 kb
Host smart-4154aa9f-1580-4de7-bbe4-821e281577a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939449903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3939449903
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1547770985
Short name T1124
Test name
Test status
Simulation time 43913436 ps
CPU time 0.63 seconds
Started Jul 11 07:32:36 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 204812 kb
Host smart-cbe10bf1-bca0-4445-88cf-0b356b85c652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547770985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1547770985
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3280083721
Short name T1466
Test name
Test status
Simulation time 211309632 ps
CPU time 2.54 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:32:29 PM PDT 24
Peak memory 213636 kb
Host smart-c8e04230-3c21-4123-a24c-41f711bfa51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280083721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3280083721
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2635253928
Short name T385
Test name
Test status
Simulation time 1288597203 ps
CPU time 15.47 seconds
Started Jul 11 07:32:27 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 268136 kb
Host smart-a001c192-41eb-42e7-948f-c93d4c57ca05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635253928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2635253928
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3631947728
Short name T464
Test name
Test status
Simulation time 18208949022 ps
CPU time 170.31 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:35:17 PM PDT 24
Peak memory 627768 kb
Host smart-5840400b-a93e-46f1-8abd-de2b9e113827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631947728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3631947728
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1270181267
Short name T1293
Test name
Test status
Simulation time 9893575363 ps
CPU time 47.27 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:33:14 PM PDT 24
Peak memory 599732 kb
Host smart-5436befa-9e69-4645-8423-ccc5b1b0b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270181267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1270181267
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.151037769
Short name T479
Test name
Test status
Simulation time 109455397 ps
CPU time 1.11 seconds
Started Jul 11 07:32:26 PM PDT 24
Finished Jul 11 07:32:28 PM PDT 24
Peak memory 205188 kb
Host smart-5f6eb839-ef2c-4300-81a6-975bb799e995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151037769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.151037769
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1441800938
Short name T1321
Test name
Test status
Simulation time 892122125 ps
CPU time 5.26 seconds
Started Jul 11 07:32:26 PM PDT 24
Finished Jul 11 07:32:33 PM PDT 24
Peak memory 242992 kb
Host smart-574fa329-76f3-4185-bd0e-85e4685baadb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441800938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1441800938
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1622203460
Short name T1190
Test name
Test status
Simulation time 9821143358 ps
CPU time 133 seconds
Started Jul 11 07:32:26 PM PDT 24
Finished Jul 11 07:34:40 PM PDT 24
Peak memory 1381372 kb
Host smart-75e31a74-8d69-48ef-9ca0-b46164e757f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622203460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1622203460
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2641784371
Short name T22
Test name
Test status
Simulation time 744164350 ps
CPU time 16.54 seconds
Started Jul 11 07:32:31 PM PDT 24
Finished Jul 11 07:32:48 PM PDT 24
Peak memory 205296 kb
Host smart-9b023e24-fdfc-4af6-9618-14d60f7e3a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641784371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2641784371
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.3970870396
Short name T1187
Test name
Test status
Simulation time 105605586 ps
CPU time 0.63 seconds
Started Jul 11 07:32:29 PM PDT 24
Finished Jul 11 07:32:30 PM PDT 24
Peak memory 205208 kb
Host smart-94371272-7011-421b-a419-23aa586fedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970870396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3970870396
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3411861150
Short name T540
Test name
Test status
Simulation time 2876266566 ps
CPU time 83.24 seconds
Started Jul 11 07:32:26 PM PDT 24
Finished Jul 11 07:33:51 PM PDT 24
Peak memory 522392 kb
Host smart-8d71a524-f75b-4fa3-8803-48e9409134e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411861150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3411861150
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2346386549
Short name T667
Test name
Test status
Simulation time 1135883604 ps
CPU time 34.9 seconds
Started Jul 11 07:32:24 PM PDT 24
Finished Jul 11 07:33:00 PM PDT 24
Peak memory 205348 kb
Host smart-acea9dcd-bd69-4cee-ba51-bdea9925dd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346386549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2346386549
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2087198117
Short name T1446
Test name
Test status
Simulation time 4121660516 ps
CPU time 24.79 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:32:52 PM PDT 24
Peak memory 318604 kb
Host smart-8ee3d801-e245-4f74-98c4-1a2614847355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087198117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2087198117
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1247338220
Short name T230
Test name
Test status
Simulation time 124119388505 ps
CPU time 225.44 seconds
Started Jul 11 07:32:26 PM PDT 24
Finished Jul 11 07:36:13 PM PDT 24
Peak memory 1123724 kb
Host smart-468d2f6a-184e-4779-9478-48adde8e09a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247338220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1247338220
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.864500407
Short name T1313
Test name
Test status
Simulation time 3845653152 ps
CPU time 16.97 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 221120 kb
Host smart-2636749f-65a3-4827-90bb-15d12883c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864500407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.864500407
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3367279931
Short name T58
Test name
Test status
Simulation time 651818509 ps
CPU time 3.57 seconds
Started Jul 11 07:32:33 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 213884 kb
Host smart-6f0813a4-b730-44f1-9074-af3ba5bc5fc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367279931 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3367279931
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3752563936
Short name T1265
Test name
Test status
Simulation time 418591263 ps
CPU time 1.01 seconds
Started Jul 11 07:32:29 PM PDT 24
Finished Jul 11 07:32:30 PM PDT 24
Peak memory 205400 kb
Host smart-ac762773-bc25-4dae-8be2-1a32dc135b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752563936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3752563936
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1686432075
Short name T602
Test name
Test status
Simulation time 488953675 ps
CPU time 1.07 seconds
Started Jul 11 07:32:29 PM PDT 24
Finished Jul 11 07:32:31 PM PDT 24
Peak memory 205384 kb
Host smart-8cdd6b25-f840-4289-bbc3-2dab6f877ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686432075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1686432075
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.2402629733
Short name T1203
Test name
Test status
Simulation time 904551135 ps
CPU time 2.56 seconds
Started Jul 11 07:32:47 PM PDT 24
Finished Jul 11 07:32:52 PM PDT 24
Peak memory 205464 kb
Host smart-6a00bc10-0d1d-4750-a4fb-e3de794169f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402629733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.2402629733
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.4081446977
Short name T1149
Test name
Test status
Simulation time 95843156 ps
CPU time 1.09 seconds
Started Jul 11 07:32:36 PM PDT 24
Finished Jul 11 07:32:39 PM PDT 24
Peak memory 205388 kb
Host smart-1fb36e70-9e0c-42e1-9e41-ccb9de76df36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081446977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.4081446977
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.200876685
Short name T982
Test name
Test status
Simulation time 931192410 ps
CPU time 5.7 seconds
Started Jul 11 07:32:33 PM PDT 24
Finished Jul 11 07:32:39 PM PDT 24
Peak memory 213680 kb
Host smart-b740a3bf-97a2-4605-b65e-9b40c3069d5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200876685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.200876685
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2986438833
Short name T1394
Test name
Test status
Simulation time 16739975623 ps
CPU time 114.35 seconds
Started Jul 11 07:32:35 PM PDT 24
Finished Jul 11 07:34:30 PM PDT 24
Peak memory 1975632 kb
Host smart-0b51c53c-de70-402f-b319-7c01464150f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986438833 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2986438833
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.2200593937
Short name T1262
Test name
Test status
Simulation time 2601067779 ps
CPU time 3.15 seconds
Started Jul 11 07:32:37 PM PDT 24
Finished Jul 11 07:32:42 PM PDT 24
Peak memory 213788 kb
Host smart-1d5f377f-9e40-4cae-bff3-3505da41cb6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200593937 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.2200593937
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.669525258
Short name T63
Test name
Test status
Simulation time 596731125 ps
CPU time 2.86 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:47 PM PDT 24
Peak memory 205508 kb
Host smart-725fcbad-6b51-4eeb-8151-3bdd3301685b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669525258 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.669525258
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.905437542
Short name T1491
Test name
Test status
Simulation time 1354184059 ps
CPU time 2.07 seconds
Started Jul 11 07:32:41 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 205312 kb
Host smart-c5fe6ec8-0559-4872-8fe4-1a673da10124
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905437542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_smbus_maxlen.905437542
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1998328989
Short name T418
Test name
Test status
Simulation time 2591374475 ps
CPU time 16.34 seconds
Started Jul 11 07:32:25 PM PDT 24
Finished Jul 11 07:32:43 PM PDT 24
Peak memory 213744 kb
Host smart-042224c1-d7da-4770-8117-7b92cc46dca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998328989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1998328989
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1966547741
Short name T460
Test name
Test status
Simulation time 4643084091 ps
CPU time 49.04 seconds
Started Jul 11 07:32:30 PM PDT 24
Finished Jul 11 07:33:20 PM PDT 24
Peak memory 213760 kb
Host smart-3ec08ebf-9335-4a50-92f9-2ac99f47b114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966547741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1966547741
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1837735353
Short name T1526
Test name
Test status
Simulation time 32389786356 ps
CPU time 289.67 seconds
Started Jul 11 07:32:34 PM PDT 24
Finished Jul 11 07:37:24 PM PDT 24
Peak memory 3216124 kb
Host smart-275684da-6de1-4e49-8b07-e1e5f5f73c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837735353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1837735353
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.485387549
Short name T711
Test name
Test status
Simulation time 278545973 ps
CPU time 2.81 seconds
Started Jul 11 07:32:32 PM PDT 24
Finished Jul 11 07:32:35 PM PDT 24
Peak memory 220552 kb
Host smart-0a71f1e1-781f-4fee-9e1f-c81e4874d5e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485387549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.485387549
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.4131945617
Short name T610
Test name
Test status
Simulation time 6114087252 ps
CPU time 7.33 seconds
Started Jul 11 07:32:30 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 213780 kb
Host smart-1a626f0f-ae9b-4dc2-8af3-282b03c6c038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131945617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.4131945617
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.982634678
Short name T782
Test name
Test status
Simulation time 602080856 ps
CPU time 8.55 seconds
Started Jul 11 07:32:40 PM PDT 24
Finished Jul 11 07:32:50 PM PDT 24
Peak memory 205420 kb
Host smart-cbd5970a-214a-479b-a9c7-8af46b68319b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982634678 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.982634678
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1232399993
Short name T474
Test name
Test status
Simulation time 16890994 ps
CPU time 0.64 seconds
Started Jul 11 07:32:49 PM PDT 24
Finished Jul 11 07:32:51 PM PDT 24
Peak memory 204720 kb
Host smart-cc5b4bc8-477c-4a00-b520-41a9d599f74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232399993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1232399993
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1296027986
Short name T806
Test name
Test status
Simulation time 150622069 ps
CPU time 1.32 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:46 PM PDT 24
Peak memory 213676 kb
Host smart-8dc5868a-da67-4f04-aaf5-393096c95fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296027986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1296027986
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1578973768
Short name T1155
Test name
Test status
Simulation time 3212104873 ps
CPU time 12.15 seconds
Started Jul 11 07:32:37 PM PDT 24
Finished Jul 11 07:32:51 PM PDT 24
Peak memory 292768 kb
Host smart-f76e9b43-9f52-45f9-930c-95a488bb882c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578973768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1578973768
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3697304638
Short name T74
Test name
Test status
Simulation time 9205104065 ps
CPU time 120.26 seconds
Started Jul 11 07:32:38 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 497336 kb
Host smart-6954f2d7-3463-45e3-9bd4-65a2b6ee310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697304638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3697304638
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2523047626
Short name T1147
Test name
Test status
Simulation time 11208378497 ps
CPU time 164.99 seconds
Started Jul 11 07:32:38 PM PDT 24
Finished Jul 11 07:35:24 PM PDT 24
Peak memory 736124 kb
Host smart-4a1f59d1-b7af-414b-8295-821344234670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523047626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2523047626
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.4030869516
Short name T1366
Test name
Test status
Simulation time 393659535 ps
CPU time 0.91 seconds
Started Jul 11 07:32:36 PM PDT 24
Finished Jul 11 07:32:38 PM PDT 24
Peak memory 205128 kb
Host smart-5468ab44-2888-491d-b9a7-810cf2a2933f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030869516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.4030869516
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.73229325
Short name T1246
Test name
Test status
Simulation time 385519374 ps
CPU time 11.16 seconds
Started Jul 11 07:32:36 PM PDT 24
Finished Jul 11 07:32:48 PM PDT 24
Peak memory 243008 kb
Host smart-2cddaba1-c7a6-4a59-b53e-4b6bd1bdc2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73229325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.73229325
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.697226264
Short name T705
Test name
Test status
Simulation time 9628834817 ps
CPU time 370.75 seconds
Started Jul 11 07:32:37 PM PDT 24
Finished Jul 11 07:38:49 PM PDT 24
Peak memory 1382500 kb
Host smart-e0fbed6c-6210-4832-9082-b7a9d0c3b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697226264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.697226264
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3813121985
Short name T1489
Test name
Test status
Simulation time 1517472079 ps
CPU time 5.16 seconds
Started Jul 11 07:32:47 PM PDT 24
Finished Jul 11 07:32:53 PM PDT 24
Peak memory 205372 kb
Host smart-1a6d1f0d-65db-4db9-b314-804cf3eb4e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813121985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3813121985
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.3189708552
Short name T133
Test name
Test status
Simulation time 79614853 ps
CPU time 0.67 seconds
Started Jul 11 07:32:35 PM PDT 24
Finished Jul 11 07:32:37 PM PDT 24
Peak memory 205164 kb
Host smart-2e7a3f96-8917-427e-a642-eb40fc842570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189708552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3189708552
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.4177794305
Short name T1044
Test name
Test status
Simulation time 1099651987 ps
CPU time 23.92 seconds
Started Jul 11 07:32:43 PM PDT 24
Finished Jul 11 07:33:09 PM PDT 24
Peak memory 234028 kb
Host smart-07c1688e-9eba-46eb-845b-66853b0f7f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177794305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4177794305
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.735392600
Short name T1488
Test name
Test status
Simulation time 196863491 ps
CPU time 4.19 seconds
Started Jul 11 07:32:43 PM PDT 24
Finished Jul 11 07:32:49 PM PDT 24
Peak memory 206312 kb
Host smart-07705ffe-6f7c-4a6f-ab81-3d1130429495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735392600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.735392600
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.427457395
Short name T795
Test name
Test status
Simulation time 1900426980 ps
CPU time 89.31 seconds
Started Jul 11 07:32:39 PM PDT 24
Finished Jul 11 07:34:10 PM PDT 24
Peak memory 401512 kb
Host smart-b5a28a76-0296-49fc-aa3e-914a3a294b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427457395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.427457395
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.4175705680
Short name T911
Test name
Test status
Simulation time 1378591002 ps
CPU time 12.59 seconds
Started Jul 11 07:32:43 PM PDT 24
Finished Jul 11 07:32:57 PM PDT 24
Peak memory 219760 kb
Host smart-a7784580-e65a-41e6-9f8c-99c13a75fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175705680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.4175705680
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2745001358
Short name T906
Test name
Test status
Simulation time 3088500487 ps
CPU time 4.91 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:48 PM PDT 24
Peak memory 221908 kb
Host smart-9d2e0f20-7d96-451f-b077-ba73970d9afc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745001358 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2745001358
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4285982246
Short name T1151
Test name
Test status
Simulation time 243175894 ps
CPU time 1.45 seconds
Started Jul 11 07:32:41 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 205524 kb
Host smart-6b3d7f17-d4e8-4181-a60a-565068c85953
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285982246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.4285982246
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2572049851
Short name T746
Test name
Test status
Simulation time 185924145 ps
CPU time 0.92 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:44 PM PDT 24
Peak memory 205324 kb
Host smart-2ce06bff-b680-460f-8226-e24d016c7d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572049851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2572049851
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.2787789576
Short name T1245
Test name
Test status
Simulation time 448962448 ps
CPU time 2.67 seconds
Started Jul 11 07:32:47 PM PDT 24
Finished Jul 11 07:32:51 PM PDT 24
Peak memory 205452 kb
Host smart-4aee6353-344c-4245-9e06-a5fc2d2200cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787789576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2787789576
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3402315482
Short name T616
Test name
Test status
Simulation time 284692339 ps
CPU time 0.96 seconds
Started Jul 11 07:32:52 PM PDT 24
Finished Jul 11 07:32:55 PM PDT 24
Peak memory 205348 kb
Host smart-bbf9614e-d65a-4ce1-8bd8-fa4b43387529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402315482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3402315482
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1468444801
Short name T575
Test name
Test status
Simulation time 1383782295 ps
CPU time 4.81 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:49 PM PDT 24
Peak memory 221780 kb
Host smart-35d05309-c9d7-4c54-84d6-e9a7e9a2c702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468444801 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1468444801
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1790775532
Short name T862
Test name
Test status
Simulation time 4164407158 ps
CPU time 7.09 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:32:51 PM PDT 24
Peak memory 399260 kb
Host smart-e3b7e3b8-9d2d-45be-9845-b7e7f82d9d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790775532 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1790775532
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.3562835826
Short name T1009
Test name
Test status
Simulation time 1942498357 ps
CPU time 2.9 seconds
Started Jul 11 07:32:47 PM PDT 24
Finished Jul 11 07:32:51 PM PDT 24
Peak memory 213712 kb
Host smart-d241292a-5e96-488f-82e3-bbaef8aa6a7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562835826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.3562835826
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.1114629761
Short name T1445
Test name
Test status
Simulation time 435940761 ps
CPU time 2.5 seconds
Started Jul 11 07:32:53 PM PDT 24
Finished Jul 11 07:32:58 PM PDT 24
Peak memory 205508 kb
Host smart-10633618-167a-4a60-a215-e2662d99a826
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114629761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.1114629761
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3398914399
Short name T401
Test name
Test status
Simulation time 2125987573 ps
CPU time 2.58 seconds
Started Jul 11 07:32:50 PM PDT 24
Finished Jul 11 07:32:54 PM PDT 24
Peak memory 205316 kb
Host smart-faaa639d-2e39-46b6-9f37-b3faed116ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398914399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3398914399
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3893756178
Short name T299
Test name
Test status
Simulation time 1508979325 ps
CPU time 17.33 seconds
Started Jul 11 07:32:41 PM PDT 24
Finished Jul 11 07:33:00 PM PDT 24
Peak memory 213656 kb
Host smart-485f5af0-a7a8-44b0-92d1-da896a962a9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893756178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3893756178
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1171987142
Short name T679
Test name
Test status
Simulation time 525297938 ps
CPU time 8.46 seconds
Started Jul 11 07:32:43 PM PDT 24
Finished Jul 11 07:32:53 PM PDT 24
Peak memory 205532 kb
Host smart-660c700d-942c-4a4d-8a88-27615b860e41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171987142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1171987142
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.4129719724
Short name T343
Test name
Test status
Simulation time 55692465798 ps
CPU time 2279.19 seconds
Started Jul 11 07:32:41 PM PDT 24
Finished Jul 11 08:10:42 PM PDT 24
Peak memory 9101328 kb
Host smart-c8695190-20c5-4e9f-b136-ce2f57ba64e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129719724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.4129719724
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3684429854
Short name T297
Test name
Test status
Simulation time 5981834634 ps
CPU time 27.5 seconds
Started Jul 11 07:32:42 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 334836 kb
Host smart-39bd3d86-71a7-4a8f-bba0-f78c302431b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684429854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3684429854
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.674743908
Short name T998
Test name
Test status
Simulation time 9740205089 ps
CPU time 7.4 seconds
Started Jul 11 07:32:41 PM PDT 24
Finished Jul 11 07:32:50 PM PDT 24
Peak memory 221928 kb
Host smart-66513676-0c1a-4b81-9bb8-594a38bc6c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674743908 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.674743908
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1508459979
Short name T829
Test name
Test status
Simulation time 169375179 ps
CPU time 2.3 seconds
Started Jul 11 07:32:46 PM PDT 24
Finished Jul 11 07:32:49 PM PDT 24
Peak memory 221076 kb
Host smart-1a5e85c4-958c-407a-bbcb-740680b3179c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508459979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1508459979
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.498059081
Short name T1561
Test name
Test status
Simulation time 20550976 ps
CPU time 0.68 seconds
Started Jul 11 07:23:31 PM PDT 24
Finished Jul 11 07:23:32 PM PDT 24
Peak memory 204660 kb
Host smart-91b938b8-7cc5-4e98-b2bd-35ca3f0c960a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498059081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.498059081
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2082174228
Short name T990
Test name
Test status
Simulation time 76664815 ps
CPU time 1.71 seconds
Started Jul 11 07:23:15 PM PDT 24
Finished Jul 11 07:23:18 PM PDT 24
Peak memory 213644 kb
Host smart-a2684ce4-103f-4026-b762-29cd244d7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082174228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2082174228
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.291728869
Short name T865
Test name
Test status
Simulation time 209676732 ps
CPU time 4.87 seconds
Started Jul 11 07:23:16 PM PDT 24
Finished Jul 11 07:23:22 PM PDT 24
Peak memory 244560 kb
Host smart-c19b723b-4af2-4c38-9abd-93c4e755bdca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291728869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.291728869
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3449264669
Short name T1248
Test name
Test status
Simulation time 2038171455 ps
CPU time 144.33 seconds
Started Jul 11 07:23:10 PM PDT 24
Finished Jul 11 07:25:35 PM PDT 24
Peak memory 691588 kb
Host smart-879425d4-0ef8-499c-ae0e-1079354127fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449264669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3449264669
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1024141266
Short name T730
Test name
Test status
Simulation time 1525866358 ps
CPU time 43.36 seconds
Started Jul 11 07:23:10 PM PDT 24
Finished Jul 11 07:23:54 PM PDT 24
Peak memory 549048 kb
Host smart-3daf338d-6ce2-4b1f-8737-ed67f47a3e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024141266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1024141266
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1561018548
Short name T763
Test name
Test status
Simulation time 180883140 ps
CPU time 1.09 seconds
Started Jul 11 07:23:12 PM PDT 24
Finished Jul 11 07:23:13 PM PDT 24
Peak memory 205152 kb
Host smart-35728da1-ee71-4a01-9356-4513e72009a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561018548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1561018548
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3298119613
Short name T586
Test name
Test status
Simulation time 754144308 ps
CPU time 10.92 seconds
Started Jul 11 07:23:10 PM PDT 24
Finished Jul 11 07:23:22 PM PDT 24
Peak memory 240332 kb
Host smart-272d764a-5efc-4a7d-88e3-5e83bdcba703
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298119613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3298119613
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1525339428
Short name T1273
Test name
Test status
Simulation time 7475125553 ps
CPU time 91.69 seconds
Started Jul 11 07:23:13 PM PDT 24
Finished Jul 11 07:24:46 PM PDT 24
Peak memory 1087124 kb
Host smart-0889b6aa-d6fc-446d-b987-896c863ec185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525339428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1525339428
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.512340695
Short name T1420
Test name
Test status
Simulation time 1641808626 ps
CPU time 19.29 seconds
Started Jul 11 07:23:25 PM PDT 24
Finished Jul 11 07:23:45 PM PDT 24
Peak memory 205292 kb
Host smart-9f9ad4e3-91ad-4f64-bfed-5787bb01d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512340695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.512340695
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.521050740
Short name T1176
Test name
Test status
Simulation time 18879646 ps
CPU time 0.68 seconds
Started Jul 11 07:23:10 PM PDT 24
Finished Jul 11 07:23:12 PM PDT 24
Peak memory 205172 kb
Host smart-b1ef377d-2b24-4d4f-97df-ac8b3221659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521050740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.521050740
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.537168422
Short name T467
Test name
Test status
Simulation time 13400434802 ps
CPU time 325.92 seconds
Started Jul 11 07:23:13 PM PDT 24
Finished Jul 11 07:28:40 PM PDT 24
Peak memory 1342348 kb
Host smart-5da3c647-51e0-44fc-ae7d-9ea5150ff92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537168422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.537168422
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.3468571427
Short name T433
Test name
Test status
Simulation time 2560430351 ps
CPU time 15.48 seconds
Started Jul 11 07:23:16 PM PDT 24
Finished Jul 11 07:23:32 PM PDT 24
Peak memory 350088 kb
Host smart-4f847f1a-7571-443c-b966-da899128eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468571427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3468571427
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2734713793
Short name T629
Test name
Test status
Simulation time 29489340071 ps
CPU time 25.42 seconds
Started Jul 11 07:23:10 PM PDT 24
Finished Jul 11 07:23:37 PM PDT 24
Peak memory 335124 kb
Host smart-9d0dd370-a644-456b-96cd-d439f52b93ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734713793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2734713793
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3549872152
Short name T473
Test name
Test status
Simulation time 711913051 ps
CPU time 13.64 seconds
Started Jul 11 07:23:15 PM PDT 24
Finished Jul 11 07:23:30 PM PDT 24
Peak memory 217136 kb
Host smart-2bb83d47-eded-48b8-80ff-731671a86834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549872152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3549872152
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2633727158
Short name T181
Test name
Test status
Simulation time 442048230 ps
CPU time 0.86 seconds
Started Jul 11 07:23:29 PM PDT 24
Finished Jul 11 07:23:31 PM PDT 24
Peak memory 223360 kb
Host smart-9460803f-d579-4884-8f43-0e5955497210
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633727158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2633727158
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3061066128
Short name T1483
Test name
Test status
Simulation time 4979826639 ps
CPU time 6.24 seconds
Started Jul 11 07:23:27 PM PDT 24
Finished Jul 11 07:23:34 PM PDT 24
Peak memory 218140 kb
Host smart-5ddeb549-641c-4414-be42-b2b30da5f59e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061066128 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3061066128
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.88549974
Short name T10
Test name
Test status
Simulation time 343297998 ps
CPU time 1.24 seconds
Started Jul 11 07:24:10 PM PDT 24
Finished Jul 11 07:24:12 PM PDT 24
Peak memory 205488 kb
Host smart-176fb5d4-0896-468a-87a7-5e31333795fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88549974 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_acq.88549974
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.984647485
Short name T1228
Test name
Test status
Simulation time 312481929 ps
CPU time 1.26 seconds
Started Jul 11 07:23:18 PM PDT 24
Finished Jul 11 07:23:20 PM PDT 24
Peak memory 205408 kb
Host smart-8ae28678-bc1b-4929-9beb-85c699612e6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984647485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.984647485
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.4036608112
Short name T993
Test name
Test status
Simulation time 433773878 ps
CPU time 2.47 seconds
Started Jul 11 07:23:30 PM PDT 24
Finished Jul 11 07:23:33 PM PDT 24
Peak memory 205492 kb
Host smart-261fca67-1e83-44e3-94e7-be0169fb1b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036608112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.4036608112
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2074968366
Short name T305
Test name
Test status
Simulation time 226926923 ps
CPU time 1.08 seconds
Started Jul 11 07:23:36 PM PDT 24
Finished Jul 11 07:23:37 PM PDT 24
Peak memory 205360 kb
Host smart-164be700-b4e9-4574-aa15-f4a96fd49b5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074968366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2074968366
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4179914551
Short name T344
Test name
Test status
Simulation time 1000327400 ps
CPU time 5.81 seconds
Started Jul 11 07:23:18 PM PDT 24
Finished Jul 11 07:23:24 PM PDT 24
Peak memory 217732 kb
Host smart-a6d60288-e05a-450e-a6e1-4524446c40b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179914551 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4179914551
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2349801631
Short name T872
Test name
Test status
Simulation time 14174321083 ps
CPU time 37.18 seconds
Started Jul 11 07:23:16 PM PDT 24
Finished Jul 11 07:23:54 PM PDT 24
Peak memory 976036 kb
Host smart-4c9bb9b5-3cc5-4253-acfc-fea35d7c6941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349801631 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2349801631
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.615658551
Short name T670
Test name
Test status
Simulation time 486785540 ps
CPU time 2.73 seconds
Started Jul 11 07:23:31 PM PDT 24
Finished Jul 11 07:23:34 PM PDT 24
Peak memory 213776 kb
Host smart-1dbc33ff-ebb8-4e92-b9cd-11e62280fe6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615658551 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_nack_acqfull.615658551
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.3543119780
Short name T1197
Test name
Test status
Simulation time 8622068854 ps
CPU time 2.6 seconds
Started Jul 11 07:23:29 PM PDT 24
Finished Jul 11 07:23:33 PM PDT 24
Peak memory 205548 kb
Host smart-b72d5a70-8d35-4a87-9dbf-6f3989a98d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543119780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.3543119780
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.1727600725
Short name T631
Test name
Test status
Simulation time 7384216069 ps
CPU time 2 seconds
Started Jul 11 07:23:31 PM PDT 24
Finished Jul 11 07:23:34 PM PDT 24
Peak memory 205444 kb
Host smart-d408975e-8830-471e-84d6-b81277190abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727600725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_smbus_maxlen.1727600725
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3255845988
Short name T857
Test name
Test status
Simulation time 1103113567 ps
CPU time 33.85 seconds
Started Jul 11 07:23:16 PM PDT 24
Finished Jul 11 07:23:51 PM PDT 24
Peak memory 213720 kb
Host smart-6f815088-8a93-42db-83e8-c3e4e987b273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255845988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3255845988
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1324011759
Short name T1261
Test name
Test status
Simulation time 6005951961 ps
CPU time 29.76 seconds
Started Jul 11 07:23:18 PM PDT 24
Finished Jul 11 07:23:48 PM PDT 24
Peak memory 228292 kb
Host smart-c2c6bc45-0c9f-414b-9aeb-b82eb67c5d6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324011759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1324011759
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.161793494
Short name T1152
Test name
Test status
Simulation time 4559225879 ps
CPU time 6.83 seconds
Started Jul 11 07:23:20 PM PDT 24
Finished Jul 11 07:23:28 PM PDT 24
Peak memory 222084 kb
Host smart-cf35227e-2b6d-4d61-9b60-0131f67df2b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161793494 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.161793494
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.997050311
Short name T459
Test name
Test status
Simulation time 169688646 ps
CPU time 3.19 seconds
Started Jul 11 07:23:30 PM PDT 24
Finished Jul 11 07:23:34 PM PDT 24
Peak memory 205412 kb
Host smart-c8be2bb2-243a-4a32-af0e-b1215ceddfb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997050311 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.997050311
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1656679293
Short name T1441
Test name
Test status
Simulation time 30061538 ps
CPU time 0.65 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:09 PM PDT 24
Peak memory 204740 kb
Host smart-c0353ce9-0432-4843-8b32-687d5889b1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656679293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1656679293
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2882104613
Short name T1268
Test name
Test status
Simulation time 101456737 ps
CPU time 3.69 seconds
Started Jul 11 07:32:48 PM PDT 24
Finished Jul 11 07:32:53 PM PDT 24
Peak memory 213628 kb
Host smart-b1c03ed5-ed35-4342-8d7a-91fa2ee2ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882104613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2882104613
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1020590853
Short name T445
Test name
Test status
Simulation time 359794084 ps
CPU time 14.36 seconds
Started Jul 11 07:32:54 PM PDT 24
Finished Jul 11 07:33:11 PM PDT 24
Peak memory 260672 kb
Host smart-6865279a-7786-4262-b1ea-76f95b71d5e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020590853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1020590853
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3415758320
Short name T76
Test name
Test status
Simulation time 2569163280 ps
CPU time 69.93 seconds
Started Jul 11 07:32:50 PM PDT 24
Finished Jul 11 07:34:01 PM PDT 24
Peak memory 719744 kb
Host smart-9a6623db-a48f-41b3-a963-315fa9929bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415758320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3415758320
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.984923903
Short name T172
Test name
Test status
Simulation time 4409206375 ps
CPU time 167.99 seconds
Started Jul 11 07:32:48 PM PDT 24
Finished Jul 11 07:35:38 PM PDT 24
Peak memory 745040 kb
Host smart-09b15a87-01c6-494a-9467-d7c3423d401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984923903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.984923903
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1194315921
Short name T983
Test name
Test status
Simulation time 602525655 ps
CPU time 1.33 seconds
Started Jul 11 07:32:45 PM PDT 24
Finished Jul 11 07:32:48 PM PDT 24
Peak memory 205256 kb
Host smart-6862e628-8bc0-4782-aaa7-6c096e1c2efe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194315921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1194315921
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2796529598
Short name T928
Test name
Test status
Simulation time 183417600 ps
CPU time 8.62 seconds
Started Jul 11 07:32:47 PM PDT 24
Finished Jul 11 07:32:57 PM PDT 24
Peak memory 205380 kb
Host smart-1a82a55c-daef-4763-9ca8-e66fb975b328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796529598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2796529598
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2184967441
Short name T1337
Test name
Test status
Simulation time 8859499840 ps
CPU time 362.13 seconds
Started Jul 11 07:32:49 PM PDT 24
Finished Jul 11 07:38:52 PM PDT 24
Peak memory 1356924 kb
Host smart-7df7a6d5-009e-494c-ac7f-8f674d9d61f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184967441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2184967441
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3456611929
Short name T255
Test name
Test status
Simulation time 1189864639 ps
CPU time 12.96 seconds
Started Jul 11 07:32:58 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 205412 kb
Host smart-b38b5965-9760-4ec7-a9ec-12478be3676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456611929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3456611929
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.3510188476
Short name T1028
Test name
Test status
Simulation time 25113279 ps
CPU time 0.67 seconds
Started Jul 11 07:32:56 PM PDT 24
Finished Jul 11 07:32:58 PM PDT 24
Peak memory 205156 kb
Host smart-0729a3de-6a29-4f90-8b94-83394420f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510188476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3510188476
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.297741515
Short name T1229
Test name
Test status
Simulation time 48883004220 ps
CPU time 291.31 seconds
Started Jul 11 07:32:49 PM PDT 24
Finished Jul 11 07:37:42 PM PDT 24
Peak memory 205416 kb
Host smart-76556c6f-a746-4f90-a09d-884752f56bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297741515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.297741515
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.764018989
Short name T1555
Test name
Test status
Simulation time 2390565844 ps
CPU time 96.43 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:35:32 PM PDT 24
Peak memory 205324 kb
Host smart-7a373598-fe10-40d4-8d31-dcf89f144de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764018989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.764018989
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3610093945
Short name T137
Test name
Test status
Simulation time 9661836617 ps
CPU time 74.15 seconds
Started Jul 11 07:32:49 PM PDT 24
Finished Jul 11 07:34:04 PM PDT 24
Peak memory 366744 kb
Host smart-2c85b134-b4c8-4ebb-ad3b-a8973ae352de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610093945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3610093945
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1974718386
Short name T437
Test name
Test status
Simulation time 1663383344 ps
CPU time 19.88 seconds
Started Jul 11 07:32:51 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 213596 kb
Host smart-78e8b7cf-8ff5-4403-90a6-7ff3762fb0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974718386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1974718386
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2423385967
Short name T890
Test name
Test status
Simulation time 7997583459 ps
CPU time 6.6 seconds
Started Jul 11 07:32:55 PM PDT 24
Finished Jul 11 07:33:04 PM PDT 24
Peak memory 221896 kb
Host smart-90ef7428-2c05-47d1-aba6-4bb9d69b6c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423385967 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2423385967
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2036015863
Short name T1367
Test name
Test status
Simulation time 160447936 ps
CPU time 1.08 seconds
Started Jul 11 07:32:52 PM PDT 24
Finished Jul 11 07:32:56 PM PDT 24
Peak memory 205384 kb
Host smart-a7d9b066-bfef-4195-99e9-186d9817cf51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036015863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2036015863
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1413202570
Short name T304
Test name
Test status
Simulation time 288802705 ps
CPU time 1.91 seconds
Started Jul 11 07:32:50 PM PDT 24
Finished Jul 11 07:32:54 PM PDT 24
Peak memory 206548 kb
Host smart-c1fc4a6a-1543-43bf-9866-12d5ada1c1b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413202570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1413202570
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.1310921184
Short name T706
Test name
Test status
Simulation time 545709061 ps
CPU time 2.92 seconds
Started Jul 11 07:32:58 PM PDT 24
Finished Jul 11 07:33:02 PM PDT 24
Peak memory 205492 kb
Host smart-c21035ea-874c-4511-9ea6-ed28efda5304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310921184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.1310921184
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.4098112116
Short name T428
Test name
Test status
Simulation time 300746479 ps
CPU time 1.5 seconds
Started Jul 11 07:32:57 PM PDT 24
Finished Jul 11 07:33:00 PM PDT 24
Peak memory 205392 kb
Host smart-32a8857d-7b61-4869-be8b-cf0543fdf70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098112116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.4098112116
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.956330887
Short name T693
Test name
Test status
Simulation time 4391602562 ps
CPU time 5.45 seconds
Started Jul 11 07:32:53 PM PDT 24
Finished Jul 11 07:33:01 PM PDT 24
Peak memory 217472 kb
Host smart-844afbf6-68ee-41a4-a104-afb8e25ae909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956330887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.956330887
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2492301476
Short name T1040
Test name
Test status
Simulation time 24850430585 ps
CPU time 80.27 seconds
Started Jul 11 07:32:53 PM PDT 24
Finished Jul 11 07:34:16 PM PDT 24
Peak memory 1456164 kb
Host smart-546842ab-e02a-4b20-84b2-a11bf72dd59c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492301476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2492301476
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.422259909
Short name T456
Test name
Test status
Simulation time 1809645879 ps
CPU time 2.59 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 213652 kb
Host smart-01cceb4e-9e9d-418f-b04e-c2499bc3725b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422259909 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_nack_acqfull.422259909
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.3162170612
Short name T559
Test name
Test status
Simulation time 847046385 ps
CPU time 2.4 seconds
Started Jul 11 07:33:03 PM PDT 24
Finished Jul 11 07:33:07 PM PDT 24
Peak memory 205504 kb
Host smart-4cab5546-cd10-4a17-8394-34a23b427ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162170612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.3162170612
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.2088447066
Short name T696
Test name
Test status
Simulation time 422477599 ps
CPU time 2.17 seconds
Started Jul 11 07:32:58 PM PDT 24
Finished Jul 11 07:33:01 PM PDT 24
Peak memory 205320 kb
Host smart-57f40678-5049-4905-869a-ce4fdc370553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088447066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.2088447066
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1207610627
Short name T478
Test name
Test status
Simulation time 10087796342 ps
CPU time 10.44 seconds
Started Jul 11 07:32:53 PM PDT 24
Finished Jul 11 07:33:06 PM PDT 24
Peak memory 213780 kb
Host smart-1067b034-a53b-4ce4-827c-c445f5a4a8cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207610627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1207610627
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1858330453
Short name T335
Test name
Test status
Simulation time 2035156060 ps
CPU time 23.36 seconds
Started Jul 11 07:32:55 PM PDT 24
Finished Jul 11 07:33:20 PM PDT 24
Peak memory 225000 kb
Host smart-3c6bfe2b-b7c4-42c5-833c-f07764dbe801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858330453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1858330453
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2565949784
Short name T675
Test name
Test status
Simulation time 64561516485 ps
CPU time 868.65 seconds
Started Jul 11 07:32:59 PM PDT 24
Finished Jul 11 07:47:28 PM PDT 24
Peak memory 5987268 kb
Host smart-1dd70f6c-76c9-42e9-83cd-f0f221fecae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565949784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2565949784
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2294876657
Short name T66
Test name
Test status
Simulation time 4949683569 ps
CPU time 92.12 seconds
Started Jul 11 07:32:54 PM PDT 24
Finished Jul 11 07:34:29 PM PDT 24
Peak memory 652228 kb
Host smart-a3f45929-f7b2-4c84-bace-1d7a45612138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294876657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2294876657
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.409269922
Short name T423
Test name
Test status
Simulation time 9779139469 ps
CPU time 7.49 seconds
Started Jul 11 07:32:52 PM PDT 24
Finished Jul 11 07:33:02 PM PDT 24
Peak memory 221932 kb
Host smart-d2109d0c-2a80-4890-861b-7d53ff444352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409269922 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.409269922
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.3617011400
Short name T1234
Test name
Test status
Simulation time 432414292 ps
CPU time 5.92 seconds
Started Jul 11 07:33:00 PM PDT 24
Finished Jul 11 07:33:08 PM PDT 24
Peak memory 214688 kb
Host smart-8b3069c5-0718-40dd-a31d-281cf7cef0a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617011400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3617011400
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.4055427984
Short name T493
Test name
Test status
Simulation time 40047913 ps
CPU time 0.68 seconds
Started Jul 11 07:33:13 PM PDT 24
Finished Jul 11 07:33:14 PM PDT 24
Peak memory 204776 kb
Host smart-f7b92cbc-c03f-41d9-b843-4dcf62b58265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055427984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.4055427984
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3647925751
Short name T29
Test name
Test status
Simulation time 524117342 ps
CPU time 1.64 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:10 PM PDT 24
Peak memory 213612 kb
Host smart-1e127528-6dd9-434c-85d4-012e5d74a212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647925751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3647925751
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1682702976
Short name T377
Test name
Test status
Simulation time 334778260 ps
CPU time 17.06 seconds
Started Jul 11 07:33:07 PM PDT 24
Finished Jul 11 07:33:28 PM PDT 24
Peak memory 275368 kb
Host smart-b31d0941-299e-4650-b996-052ca793335b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682702976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1682702976
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3829451325
Short name T1215
Test name
Test status
Simulation time 12299199877 ps
CPU time 165.82 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:35:55 PM PDT 24
Peak memory 757520 kb
Host smart-a43b9b95-c447-4e73-8250-32cbb25bb056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829451325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3829451325
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3791320819
Short name T1316
Test name
Test status
Simulation time 2658624965 ps
CPU time 39.85 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:49 PM PDT 24
Peak memory 489644 kb
Host smart-b1866647-aa49-4cc4-b402-98c93fba2bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791320819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3791320819
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1387051052
Short name T306
Test name
Test status
Simulation time 422809169 ps
CPU time 1.37 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:11 PM PDT 24
Peak memory 205316 kb
Host smart-448b281b-4c68-4780-8c8d-033d5ca4225c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387051052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1387051052
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1910022547
Short name T40
Test name
Test status
Simulation time 251920505 ps
CPU time 7.47 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:16 PM PDT 24
Peak memory 228236 kb
Host smart-031a3f60-a4de-437a-8351-bd9af365d035
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910022547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1910022547
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1740065076
Short name T112
Test name
Test status
Simulation time 17217672731 ps
CPU time 96.97 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:34:47 PM PDT 24
Peak memory 1165364 kb
Host smart-1391bc26-63b3-44b7-9535-c6a345412540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740065076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1740065076
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3997794509
Short name T852
Test name
Test status
Simulation time 273211994 ps
CPU time 11.15 seconds
Started Jul 11 07:33:09 PM PDT 24
Finished Jul 11 07:33:23 PM PDT 24
Peak memory 205440 kb
Host smart-1d8e8e63-e82e-4c60-9c96-c2c369b66db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997794509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3997794509
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.3298734922
Short name T1074
Test name
Test status
Simulation time 30414656 ps
CPU time 0.67 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:10 PM PDT 24
Peak memory 205096 kb
Host smart-c9e4ec43-8f25-4e4b-b397-099f1ba40af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298734922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3298734922
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.4068577912
Short name T14
Test name
Test status
Simulation time 7298102323 ps
CPU time 71.65 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:34:44 PM PDT 24
Peak memory 205428 kb
Host smart-5b0705ee-a395-4364-813e-323070bcedbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068577912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.4068577912
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.2953480089
Short name T554
Test name
Test status
Simulation time 88971103 ps
CPU time 2.07 seconds
Started Jul 11 07:33:06 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 223756 kb
Host smart-5148ac0c-9408-472e-89f1-6143ac98f2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953480089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.2953480089
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1161697288
Short name T622
Test name
Test status
Simulation time 3778214086 ps
CPU time 42.77 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:52 PM PDT 24
Peak memory 432024 kb
Host smart-0a2ebeac-bc40-4c2c-8e18-67a72aaff5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161697288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1161697288
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.178533176
Short name T651
Test name
Test status
Simulation time 1182363148 ps
CPU time 9.41 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:18 PM PDT 24
Peak memory 217776 kb
Host smart-283240ec-cd4d-4a5d-8bbb-d158e1c6f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178533176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.178533176
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2441854804
Short name T855
Test name
Test status
Simulation time 3430533037 ps
CPU time 4.68 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:14 PM PDT 24
Peak memory 213764 kb
Host smart-ed753a8d-c669-4e1c-8279-26f137fd28ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441854804 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2441854804
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.286754779
Short name T593
Test name
Test status
Simulation time 308694486 ps
CPU time 0.9 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:10 PM PDT 24
Peak memory 205400 kb
Host smart-976319e6-4fc4-428a-abf2-a5bde56ad74f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286754779 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.286754779
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3961513669
Short name T1080
Test name
Test status
Simulation time 704794213 ps
CPU time 1.33 seconds
Started Jul 11 07:33:06 PM PDT 24
Finished Jul 11 07:33:11 PM PDT 24
Peak memory 205420 kb
Host smart-5f2c4a9b-4e79-4881-8053-bdf84f76ff37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961513669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3961513669
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.2561908427
Short name T1341
Test name
Test status
Simulation time 505679335 ps
CPU time 3.06 seconds
Started Jul 11 07:33:11 PM PDT 24
Finished Jul 11 07:33:16 PM PDT 24
Peak memory 205416 kb
Host smart-5c2c32d6-9132-440c-a292-9789f9129d53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561908427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.2561908427
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1842721444
Short name T1557
Test name
Test status
Simulation time 127847994 ps
CPU time 1.46 seconds
Started Jul 11 07:33:10 PM PDT 24
Finished Jul 11 07:33:14 PM PDT 24
Peak memory 205388 kb
Host smart-52a66dc8-9aea-4384-85c4-20934299f481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842721444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1842721444
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.4223013401
Short name T930
Test name
Test status
Simulation time 1324105696 ps
CPU time 7.48 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:16 PM PDT 24
Peak memory 224120 kb
Host smart-98e141ab-ee39-43e4-8ef5-832af22caeed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223013401 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.4223013401
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1021827610
Short name T641
Test name
Test status
Simulation time 13843740420 ps
CPU time 271 seconds
Started Jul 11 07:33:06 PM PDT 24
Finished Jul 11 07:37:41 PM PDT 24
Peak memory 3374512 kb
Host smart-7ebfe8bd-f52a-45bd-9e5c-7e40e1bbaa46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021827610 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1021827610
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.3340523657
Short name T159
Test name
Test status
Simulation time 646025292 ps
CPU time 3.15 seconds
Started Jul 11 07:33:10 PM PDT 24
Finished Jul 11 07:33:15 PM PDT 24
Peak memory 213688 kb
Host smart-48c57417-b0dc-4103-87b0-5508da7da39a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340523657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.3340523657
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.3828302979
Short name T1180
Test name
Test status
Simulation time 1202308906 ps
CPU time 2.9 seconds
Started Jul 11 07:33:10 PM PDT 24
Finished Jul 11 07:33:15 PM PDT 24
Peak memory 205428 kb
Host smart-d7ac1a5f-77fe-4252-9457-46b2aa02cbd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828302979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.3828302979
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.378816941
Short name T319
Test name
Test status
Simulation time 1508293368 ps
CPU time 1.94 seconds
Started Jul 11 07:33:13 PM PDT 24
Finished Jul 11 07:33:16 PM PDT 24
Peak memory 205336 kb
Host smart-7963088f-79b9-48d8-8b0f-899236e5e50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378816941 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_smbus_maxlen.378816941
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.4188375021
Short name T340
Test name
Test status
Simulation time 4766638644 ps
CPU time 36.13 seconds
Started Jul 11 07:33:07 PM PDT 24
Finished Jul 11 07:33:47 PM PDT 24
Peak memory 213740 kb
Host smart-584697a6-e1b4-4d2b-addd-e5b92481aec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188375021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.4188375021
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2021360303
Short name T845
Test name
Test status
Simulation time 1468922009 ps
CPU time 16.14 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 205468 kb
Host smart-52d75f9d-4777-4f3d-9b96-e248619d3582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021360303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2021360303
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.860113522
Short name T3
Test name
Test status
Simulation time 62193976738 ps
CPU time 2617.1 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 08:16:46 PM PDT 24
Peak memory 10623868 kb
Host smart-afa6dc59-61d9-4195-ae34-348c48c42c1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860113522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.860113522
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.448578023
Short name T1432
Test name
Test status
Simulation time 311830762 ps
CPU time 2.92 seconds
Started Jul 11 07:33:04 PM PDT 24
Finished Jul 11 07:33:11 PM PDT 24
Peak memory 227328 kb
Host smart-df78ab4b-1025-40b9-8cd5-c0cb3dc29618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448578023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.448578023
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.4089561520
Short name T316
Test name
Test status
Simulation time 21312501974 ps
CPU time 6.13 seconds
Started Jul 11 07:33:05 PM PDT 24
Finished Jul 11 07:33:15 PM PDT 24
Peak memory 220012 kb
Host smart-ffc7b0fc-1ca9-403b-a806-badd42b17d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089561520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.4089561520
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.3634421298
Short name T849
Test name
Test status
Simulation time 497059258 ps
CPU time 7.07 seconds
Started Jul 11 07:33:08 PM PDT 24
Finished Jul 11 07:33:18 PM PDT 24
Peak memory 205992 kb
Host smart-76812c05-0f40-4f0d-9750-c9dbbf412393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634421298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.3634421298
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3812516621
Short name T177
Test name
Test status
Simulation time 201976553 ps
CPU time 0.64 seconds
Started Jul 11 07:33:20 PM PDT 24
Finished Jul 11 07:33:22 PM PDT 24
Peak memory 204660 kb
Host smart-5e232712-1f67-46f3-ba34-235d1c76a55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812516621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3812516621
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1269801605
Short name T1056
Test name
Test status
Simulation time 570921404 ps
CPU time 1.55 seconds
Started Jul 11 07:33:17 PM PDT 24
Finished Jul 11 07:33:19 PM PDT 24
Peak memory 213708 kb
Host smart-73e1ab67-f650-4082-9d5b-17755b355a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269801605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1269801605
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.756023483
Short name T1301
Test name
Test status
Simulation time 363579580 ps
CPU time 7.6 seconds
Started Jul 11 07:33:14 PM PDT 24
Finished Jul 11 07:33:23 PM PDT 24
Peak memory 279028 kb
Host smart-264ffda6-a23e-4549-a829-cc67c040161f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756023483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.756023483
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.4052906137
Short name T429
Test name
Test status
Simulation time 7150274421 ps
CPU time 46.33 seconds
Started Jul 11 07:33:15 PM PDT 24
Finished Jul 11 07:34:03 PM PDT 24
Peak memory 310468 kb
Host smart-1b5de854-a519-4644-b09e-f9ffde824f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052906137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.4052906137
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1120070705
Short name T280
Test name
Test status
Simulation time 1922467631 ps
CPU time 52.34 seconds
Started Jul 11 07:33:10 PM PDT 24
Finished Jul 11 07:34:05 PM PDT 24
Peak memory 625468 kb
Host smart-f27746f7-4d09-458e-a55f-abac8f499b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120070705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1120070705
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1874559102
Short name T490
Test name
Test status
Simulation time 301945463 ps
CPU time 1.09 seconds
Started Jul 11 07:33:09 PM PDT 24
Finished Jul 11 07:33:13 PM PDT 24
Peak memory 205224 kb
Host smart-0a628234-eb1a-452f-b523-11def8368b11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874559102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1874559102
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.4251868545
Short name T999
Test name
Test status
Simulation time 371651184 ps
CPU time 5.52 seconds
Started Jul 11 07:33:16 PM PDT 24
Finished Jul 11 07:33:23 PM PDT 24
Peak memory 240764 kb
Host smart-c9427037-3d52-4c37-b01f-6b78ddd206e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251868545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.4251868545
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1453144173
Short name T123
Test name
Test status
Simulation time 18199024168 ps
CPU time 133.36 seconds
Started Jul 11 07:33:14 PM PDT 24
Finished Jul 11 07:35:28 PM PDT 24
Peak memory 1295076 kb
Host smart-4479484a-154b-4725-9d0c-1ce4392b1de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453144173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1453144173
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1173062049
Short name T243
Test name
Test status
Simulation time 976603850 ps
CPU time 10.54 seconds
Started Jul 11 07:33:21 PM PDT 24
Finished Jul 11 07:33:33 PM PDT 24
Peak memory 205388 kb
Host smart-dbb9c77e-e9ae-4c5a-8a3a-f4dba3198a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173062049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1173062049
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.2329542317
Short name T336
Test name
Test status
Simulation time 14801336 ps
CPU time 0.65 seconds
Started Jul 11 07:33:07 PM PDT 24
Finished Jul 11 07:33:12 PM PDT 24
Peak memory 205168 kb
Host smart-c660d70d-3b3d-4dfa-97f1-675bf04b15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329542317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2329542317
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.289237613
Short name T1076
Test name
Test status
Simulation time 29425975397 ps
CPU time 2072.19 seconds
Started Jul 11 07:33:16 PM PDT 24
Finished Jul 11 08:07:49 PM PDT 24
Peak memory 4326512 kb
Host smart-845571b8-b957-4ade-9b66-3451aa2076ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289237613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.289237613
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.4251227642
Short name T828
Test name
Test status
Simulation time 196369696 ps
CPU time 1.51 seconds
Started Jul 11 07:33:13 PM PDT 24
Finished Jul 11 07:33:16 PM PDT 24
Peak memory 205256 kb
Host smart-2fbf65f8-321c-4973-bdc1-de184f358e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251227642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.4251227642
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.598132609
Short name T291
Test name
Test status
Simulation time 2027390971 ps
CPU time 100.47 seconds
Started Jul 11 07:33:10 PM PDT 24
Finished Jul 11 07:34:52 PM PDT 24
Peak memory 330216 kb
Host smart-af9d00ad-223f-4e2f-9af4-93cbf661dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598132609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.598132609
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3736072731
Short name T1493
Test name
Test status
Simulation time 1503544468 ps
CPU time 14.64 seconds
Started Jul 11 07:33:14 PM PDT 24
Finished Jul 11 07:33:30 PM PDT 24
Peak memory 216020 kb
Host smart-6925e28a-65ae-4734-8d01-44c78b8b59ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736072731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3736072731
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2904653054
Short name T933
Test name
Test status
Simulation time 752903773 ps
CPU time 3.92 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:33:32 PM PDT 24
Peak memory 213652 kb
Host smart-049a5459-ea8b-4200-9ed2-a32392a9035d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904653054 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2904653054
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3456785629
Short name T935
Test name
Test status
Simulation time 156927753 ps
CPU time 1.13 seconds
Started Jul 11 07:33:20 PM PDT 24
Finished Jul 11 07:33:23 PM PDT 24
Peak memory 205396 kb
Host smart-a158bff5-052c-4a9b-94cb-4f4f83a61318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456785629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3456785629
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1030879466
Short name T1482
Test name
Test status
Simulation time 210586248 ps
CPU time 0.76 seconds
Started Jul 11 07:33:22 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 205400 kb
Host smart-bdda1c0b-6786-4c42-aeaf-4541ee7b7cab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030879466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1030879466
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.972061872
Short name T1089
Test name
Test status
Simulation time 1296631386 ps
CPU time 2 seconds
Started Jul 11 07:33:21 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 205384 kb
Host smart-51912a9a-ba6e-4890-bac1-b74c2d997068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972061872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.972061872
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.1340246307
Short name T167
Test name
Test status
Simulation time 788255605 ps
CPU time 1.37 seconds
Started Jul 11 07:33:20 PM PDT 24
Finished Jul 11 07:33:22 PM PDT 24
Peak memory 205368 kb
Host smart-788cdd4f-9c12-4c63-a115-b5ba0ebb8bf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340246307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.1340246307
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2924247010
Short name T1311
Test name
Test status
Simulation time 21181144624 ps
CPU time 6.49 seconds
Started Jul 11 07:33:18 PM PDT 24
Finished Jul 11 07:33:26 PM PDT 24
Peak memory 213920 kb
Host smart-80af216b-f68f-4eb2-ad0f-abf84d20afc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924247010 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2924247010
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2514212779
Short name T522
Test name
Test status
Simulation time 35219806025 ps
CPU time 45.1 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:34:12 PM PDT 24
Peak memory 969484 kb
Host smart-1799535c-c5bc-4c0a-9eaf-8579de219019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514212779 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2514212779
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.1117326369
Short name T704
Test name
Test status
Simulation time 519342777 ps
CPU time 3.19 seconds
Started Jul 11 07:33:19 PM PDT 24
Finished Jul 11 07:33:23 PM PDT 24
Peak memory 213692 kb
Host smart-93b99cef-4730-481c-b0b0-1f0b2abe059d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117326369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.1117326369
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.970783791
Short name T53
Test name
Test status
Simulation time 553826637 ps
CPU time 2.82 seconds
Started Jul 11 07:33:21 PM PDT 24
Finished Jul 11 07:33:25 PM PDT 24
Peak memory 206708 kb
Host smart-e46aed50-6a8c-4881-9193-262d082b2216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970783791 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.970783791
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.941453260
Short name T581
Test name
Test status
Simulation time 1005739118 ps
CPU time 2.28 seconds
Started Jul 11 07:33:18 PM PDT 24
Finished Jul 11 07:33:22 PM PDT 24
Peak memory 205360 kb
Host smart-cc31f4bd-0741-4a7a-884b-e0639aa8fd0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941453260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_smbus_maxlen.941453260
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.609867628
Short name T899
Test name
Test status
Simulation time 2194224786 ps
CPU time 8.69 seconds
Started Jul 11 07:33:16 PM PDT 24
Finished Jul 11 07:33:26 PM PDT 24
Peak memory 207044 kb
Host smart-bdb31259-cf80-49bc-a50d-947a87c679c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609867628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.609867628
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2997707756
Short name T475
Test name
Test status
Simulation time 250837619 ps
CPU time 9.84 seconds
Started Jul 11 07:33:15 PM PDT 24
Finished Jul 11 07:33:26 PM PDT 24
Peak memory 205440 kb
Host smart-d7ead40c-d9e5-4c1e-8592-c5139fa4e414
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997707756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2997707756
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2863156429
Short name T838
Test name
Test status
Simulation time 46347606291 ps
CPU time 354.9 seconds
Started Jul 11 07:33:18 PM PDT 24
Finished Jul 11 07:39:14 PM PDT 24
Peak memory 3260888 kb
Host smart-1a8f871c-d02f-40f3-8033-262e7e925c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863156429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2863156429
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3061054601
Short name T64
Test name
Test status
Simulation time 5241957699 ps
CPU time 6.17 seconds
Started Jul 11 07:33:17 PM PDT 24
Finished Jul 11 07:33:25 PM PDT 24
Peak memory 221980 kb
Host smart-d09cc40b-2417-4d72-817e-3cbb90f79f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061054601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3061054601
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.1263588389
Short name T370
Test name
Test status
Simulation time 132923591 ps
CPU time 3.18 seconds
Started Jul 11 07:33:20 PM PDT 24
Finished Jul 11 07:33:25 PM PDT 24
Peak memory 205788 kb
Host smart-d94fa0e1-8673-4395-9f6d-162d040dfe2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263588389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.1263588389
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1461234529
Short name T1270
Test name
Test status
Simulation time 30178481 ps
CPU time 0.63 seconds
Started Jul 11 07:33:32 PM PDT 24
Finished Jul 11 07:33:34 PM PDT 24
Peak memory 204816 kb
Host smart-b115dbff-77db-4a83-8740-c2aa1085bb11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461234529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1461234529
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3097092932
Short name T660
Test name
Test status
Simulation time 253542858 ps
CPU time 1.79 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:33:29 PM PDT 24
Peak memory 213720 kb
Host smart-0b65b5df-1571-4a92-9d61-5fa317730d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097092932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3097092932
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3134544899
Short name T692
Test name
Test status
Simulation time 265443782 ps
CPU time 5.84 seconds
Started Jul 11 07:33:25 PM PDT 24
Finished Jul 11 07:33:32 PM PDT 24
Peak memory 255964 kb
Host smart-0211dbbd-f2e4-4b78-a4ef-42028665091f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134544899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3134544899
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1639806238
Short name T687
Test name
Test status
Simulation time 1701381938 ps
CPU time 38.6 seconds
Started Jul 11 07:33:25 PM PDT 24
Finished Jul 11 07:34:05 PM PDT 24
Peak memory 422932 kb
Host smart-2cdc59b2-421d-49d7-9f8d-1056a8ce56e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639806238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1639806238
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1435551740
Short name T922
Test name
Test status
Simulation time 2352516115 ps
CPU time 85.3 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:34:53 PM PDT 24
Peak memory 790620 kb
Host smart-b167cc09-db8a-4df0-af6c-b7fd7d233c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435551740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1435551740
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.535989744
Short name T1287
Test name
Test status
Simulation time 663265933 ps
CPU time 0.81 seconds
Started Jul 11 07:33:24 PM PDT 24
Finished Jul 11 07:33:26 PM PDT 24
Peak memory 205196 kb
Host smart-1fef5627-01f5-41fa-8df5-85103b8ca79b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535989744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.535989744
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.509582177
Short name T1437
Test name
Test status
Simulation time 820350872 ps
CPU time 10.55 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:33:39 PM PDT 24
Peak memory 205400 kb
Host smart-733d20fe-3093-48c8-8a3d-548ea8eca5e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509582177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
509582177
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3394031138
Short name T187
Test name
Test status
Simulation time 5468259673 ps
CPU time 160.82 seconds
Started Jul 11 07:33:20 PM PDT 24
Finished Jul 11 07:36:02 PM PDT 24
Peak memory 1382268 kb
Host smart-ec94c8c1-fa48-40b1-a857-c294b2d105fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394031138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3394031138
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.541783769
Short name T917
Test name
Test status
Simulation time 798495127 ps
CPU time 3.23 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:33:36 PM PDT 24
Peak memory 205384 kb
Host smart-9718aa7c-7c79-47ab-88cd-c378d816cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541783769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.541783769
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.472932034
Short name T132
Test name
Test status
Simulation time 148103799 ps
CPU time 0.7 seconds
Started Jul 11 07:34:12 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 205148 kb
Host smart-ed0ace40-6859-45a8-ab85-65793dcc93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472932034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.472932034
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.4204503531
Short name T1032
Test name
Test status
Simulation time 5336019057 ps
CPU time 95.62 seconds
Started Jul 11 07:33:25 PM PDT 24
Finished Jul 11 07:35:01 PM PDT 24
Peak memory 605036 kb
Host smart-b384b496-4cb1-4ff5-889d-f197172be17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204503531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4204503531
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3899850924
Short name T1264
Test name
Test status
Simulation time 55530342 ps
CPU time 1.12 seconds
Started Jul 11 07:33:28 PM PDT 24
Finished Jul 11 07:33:30 PM PDT 24
Peak memory 223664 kb
Host smart-2d1f605c-3fbb-46dc-a683-a8f581b61b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899850924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3899850924
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.881762166
Short name T1192
Test name
Test status
Simulation time 11919804784 ps
CPU time 96.05 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:35:03 PM PDT 24
Peak memory 336068 kb
Host smart-b76e6fd5-05bf-4e3c-b1be-5e805284988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881762166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.881762166
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2581482673
Short name T1462
Test name
Test status
Simulation time 8398820608 ps
CPU time 42 seconds
Started Jul 11 07:33:28 PM PDT 24
Finished Jul 11 07:34:11 PM PDT 24
Peak memory 213692 kb
Host smart-e0fc4e9d-995f-43b7-bbf8-07b493b555fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581482673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2581482673
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.342272689
Short name T1026
Test name
Test status
Simulation time 5113163396 ps
CPU time 6.58 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:33:39 PM PDT 24
Peak memory 214800 kb
Host smart-f5e3e5fb-e7d9-4b9d-8f0f-986a356008b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342272689 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.342272689
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.190898540
Short name T984
Test name
Test status
Simulation time 218362955 ps
CPU time 1.18 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:33:30 PM PDT 24
Peak memory 205320 kb
Host smart-03326f87-b9b9-4fd5-a519-51e2deee2409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190898540 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.190898540
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1735257515
Short name T164
Test name
Test status
Simulation time 665889161 ps
CPU time 1.05 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:33:29 PM PDT 24
Peak memory 205328 kb
Host smart-de306601-46c0-40b5-b0d4-b65519eb86ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735257515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1735257515
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.34255628
Short name T1241
Test name
Test status
Simulation time 1649686549 ps
CPU time 2.52 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 205476 kb
Host smart-3b170e4f-94d1-4594-9ca6-35ea5275598d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34255628 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.34255628
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.1320681222
Short name T627
Test name
Test status
Simulation time 139971136 ps
CPU time 1.47 seconds
Started Jul 11 07:33:34 PM PDT 24
Finished Jul 11 07:33:37 PM PDT 24
Peak memory 205356 kb
Host smart-cf1f3af6-7a52-497f-a4ec-b9e07c8691d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320681222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.1320681222
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2864352660
Short name T399
Test name
Test status
Simulation time 4487928092 ps
CPU time 6.5 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 230092 kb
Host smart-e29bedd8-c948-4905-8b90-35f7a004d509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864352660 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2864352660
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3268812650
Short name T147
Test name
Test status
Simulation time 15268542814 ps
CPU time 23.91 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:33:52 PM PDT 24
Peak memory 537648 kb
Host smart-4bbdebed-9398-4184-8d3c-120550a8b2d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268812650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3268812650
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.3065389231
Short name T1218
Test name
Test status
Simulation time 526980839 ps
CPU time 2.94 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 213592 kb
Host smart-c37c380f-b69a-48b8-8693-5a06d1c2477d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065389231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.3065389231
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.2844424497
Short name T765
Test name
Test status
Simulation time 2232124178 ps
CPU time 2.93 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 205548 kb
Host smart-ea2bf2c2-0c65-4ea3-9ee8-0e4ac8305eba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844424497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.2844424497
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.771910437
Short name T1043
Test name
Test status
Simulation time 2001575353 ps
CPU time 2.45 seconds
Started Jul 11 07:33:33 PM PDT 24
Finished Jul 11 07:33:37 PM PDT 24
Peak memory 205368 kb
Host smart-99e6ee12-89f0-48e9-acfe-6df50e63eaa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771910437 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_smbus_maxlen.771910437
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.551458662
Short name T980
Test name
Test status
Simulation time 2826187488 ps
CPU time 45.55 seconds
Started Jul 11 07:33:26 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 213712 kb
Host smart-07f8536c-bbb3-435a-be4f-e41d85228d6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551458662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.551458662
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3230625079
Short name T720
Test name
Test status
Simulation time 4919793981 ps
CPU time 57.81 seconds
Started Jul 11 07:33:27 PM PDT 24
Finished Jul 11 07:34:26 PM PDT 24
Peak memory 216064 kb
Host smart-1963d0f1-72a4-4fba-b8c2-ff56c7b1c516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230625079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3230625079
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.170458409
Short name T519
Test name
Test status
Simulation time 24981935712 ps
CPU time 91.43 seconds
Started Jul 11 07:33:32 PM PDT 24
Finished Jul 11 07:35:05 PM PDT 24
Peak memory 1275164 kb
Host smart-9eb32a5c-1b4a-4667-80bd-995a8ca2e8a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170458409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.170458409
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.3365983770
Short name T1188
Test name
Test status
Simulation time 68539636 ps
CPU time 1.56 seconds
Started Jul 11 07:33:30 PM PDT 24
Finished Jul 11 07:33:32 PM PDT 24
Peak memory 205480 kb
Host smart-6abb632f-c8b8-4af8-844d-78d9a71bee6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365983770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3365983770
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3355235821
Short name T571
Test name
Test status
Simulation time 40243606 ps
CPU time 0.67 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:51 PM PDT 24
Peak memory 204752 kb
Host smart-b40f81da-66a8-4164-a1c0-fc25c094c7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355235821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3355235821
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.470372298
Short name T496
Test name
Test status
Simulation time 86945604 ps
CPU time 1.66 seconds
Started Jul 11 07:33:39 PM PDT 24
Finished Jul 11 07:33:42 PM PDT 24
Peak memory 213640 kb
Host smart-0a0c086d-0bca-4df7-a2e1-2c79aee0acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470372298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.470372298
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1946908192
Short name T812
Test name
Test status
Simulation time 355628982 ps
CPU time 18.37 seconds
Started Jul 11 07:33:40 PM PDT 24
Finished Jul 11 07:33:59 PM PDT 24
Peak memory 282556 kb
Host smart-0fa6ebf7-c64d-41a4-a50e-001dbdfb58ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946908192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1946908192
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3623296771
Short name T1566
Test name
Test status
Simulation time 2882957123 ps
CPU time 215.3 seconds
Started Jul 11 07:33:47 PM PDT 24
Finished Jul 11 07:37:24 PM PDT 24
Peak memory 810460 kb
Host smart-cec0144a-9f9e-433c-9df1-f5dd7acde5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623296771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3623296771
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1251399966
Short name T962
Test name
Test status
Simulation time 1409507379 ps
CPU time 40.31 seconds
Started Jul 11 07:33:33 PM PDT 24
Finished Jul 11 07:34:16 PM PDT 24
Peak memory 556460 kb
Host smart-199c450d-a0fd-43d7-bf84-017ec880eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251399966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1251399966
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2520596564
Short name T1020
Test name
Test status
Simulation time 110503255 ps
CPU time 1.04 seconds
Started Jul 11 07:33:33 PM PDT 24
Finished Jul 11 07:33:36 PM PDT 24
Peak memory 205200 kb
Host smart-8b2f2817-820e-4d8b-ab62-d1566ab02f54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520596564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2520596564
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.156292591
Short name T1085
Test name
Test status
Simulation time 133653356 ps
CPU time 7.29 seconds
Started Jul 11 07:33:38 PM PDT 24
Finished Jul 11 07:33:46 PM PDT 24
Peak memory 226040 kb
Host smart-d12efec6-60cd-4352-a9ff-b09a000554a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156292591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
156292591
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3516149328
Short name T819
Test name
Test status
Simulation time 56549475052 ps
CPU time 339.86 seconds
Started Jul 11 07:33:33 PM PDT 24
Finished Jul 11 07:39:14 PM PDT 24
Peak memory 1305136 kb
Host smart-3db6adb9-4f1c-48e7-b53a-8d1bd17c610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516149328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3516149328
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3504645015
Short name T1329
Test name
Test status
Simulation time 580550958 ps
CPU time 7.83 seconds
Started Jul 11 07:33:45 PM PDT 24
Finished Jul 11 07:33:53 PM PDT 24
Peak memory 205352 kb
Host smart-deaac2a9-8698-4f93-b9db-6b289fcdb2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504645015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3504645015
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_override.1928503245
Short name T69
Test name
Test status
Simulation time 84600751 ps
CPU time 0.68 seconds
Started Jul 11 07:33:33 PM PDT 24
Finished Jul 11 07:33:35 PM PDT 24
Peak memory 205136 kb
Host smart-1c5f8d9f-3af1-40af-9a69-660b8e37d704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928503245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1928503245
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.180274823
Short name T1222
Test name
Test status
Simulation time 2564896156 ps
CPU time 10.6 seconds
Started Jul 11 07:33:40 PM PDT 24
Finished Jul 11 07:33:51 PM PDT 24
Peak memory 221632 kb
Host smart-46074139-ba31-4b59-ad62-3d0f0311f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180274823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.180274823
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.2466639613
Short name T1351
Test name
Test status
Simulation time 6271636091 ps
CPU time 39.08 seconds
Started Jul 11 07:33:39 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 205344 kb
Host smart-6d23b79e-699f-4c67-a202-3c4708b05a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466639613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2466639613
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3580694824
Short name T624
Test name
Test status
Simulation time 8161010152 ps
CPU time 32.72 seconds
Started Jul 11 07:33:31 PM PDT 24
Finished Jul 11 07:34:05 PM PDT 24
Peak memory 479116 kb
Host smart-036a9a2b-5c5e-4a01-bc49-794e6432268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580694824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3580694824
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3504934446
Short name T1486
Test name
Test status
Simulation time 4781338699 ps
CPU time 9.47 seconds
Started Jul 11 07:33:40 PM PDT 24
Finished Jul 11 07:33:50 PM PDT 24
Peak memory 221504 kb
Host smart-e8ada5ef-2ab9-4ccc-a314-05e79261dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504934446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3504934446
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.574583287
Short name T808
Test name
Test status
Simulation time 1081251851 ps
CPU time 5.26 seconds
Started Jul 11 07:33:44 PM PDT 24
Finished Jul 11 07:33:50 PM PDT 24
Peak memory 216308 kb
Host smart-478d5247-cbc1-4e8a-a14c-e27526d8c70f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574583287 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.574583287
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.4143451668
Short name T1027
Test name
Test status
Simulation time 903859664 ps
CPU time 1.69 seconds
Started Jul 11 07:33:47 PM PDT 24
Finished Jul 11 07:33:50 PM PDT 24
Peak memory 216416 kb
Host smart-3bba2558-af95-4f4a-9366-bc2234d40860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143451668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.4143451668
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.496578431
Short name T1468
Test name
Test status
Simulation time 209025718 ps
CPU time 0.98 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:33:57 PM PDT 24
Peak memory 205364 kb
Host smart-bc008c62-0993-41ef-93c7-bddb7c4bc593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496578431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.496578431
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.3180123208
Short name T1312
Test name
Test status
Simulation time 71959273 ps
CPU time 0.68 seconds
Started Jul 11 07:33:45 PM PDT 24
Finished Jul 11 07:33:47 PM PDT 24
Peak memory 205336 kb
Host smart-bf965b8c-19fa-4fd2-bbb8-ca7319db7879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180123208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.3180123208
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.2893505619
Short name T94
Test name
Test status
Simulation time 287405341 ps
CPU time 1.32 seconds
Started Jul 11 07:33:43 PM PDT 24
Finished Jul 11 07:33:44 PM PDT 24
Peak memory 205400 kb
Host smart-f4486967-bdcc-4135-b4a5-3b2ea24b65a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893505619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2893505619
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2670996325
Short name T1376
Test name
Test status
Simulation time 12044521287 ps
CPU time 8.44 seconds
Started Jul 11 07:33:40 PM PDT 24
Finished Jul 11 07:33:49 PM PDT 24
Peak memory 234796 kb
Host smart-9f73c72a-dcee-4023-aa3c-dd9bfb76c1f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670996325 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2670996325
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3018206244
Short name T697
Test name
Test status
Simulation time 5967955883 ps
CPU time 25.23 seconds
Started Jul 11 07:33:46 PM PDT 24
Finished Jul 11 07:34:12 PM PDT 24
Peak memory 834568 kb
Host smart-33f663a9-f9d5-460a-8ea4-6ef0a8f0753b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018206244 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3018206244
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.1379989661
Short name T398
Test name
Test status
Simulation time 406477862 ps
CPU time 2.44 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:53 PM PDT 24
Peak memory 213676 kb
Host smart-9597ce49-1724-4bb7-9d0c-21d5596e4f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379989661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.1379989661
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.4110306342
Short name T1098
Test name
Test status
Simulation time 2323254520 ps
CPU time 2.65 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:54 PM PDT 24
Peak memory 205496 kb
Host smart-33f5e023-fb70-4db5-8ba1-aa2de2ade37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110306342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.4110306342
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.1702354997
Short name T1172
Test name
Test status
Simulation time 1338662520 ps
CPU time 2.38 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:53 PM PDT 24
Peak memory 205368 kb
Host smart-8a827388-bd6b-437b-88ff-5c2b1f392f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702354997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.1702354997
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.4133528953
Short name T4
Test name
Test status
Simulation time 5418112006 ps
CPU time 16.19 seconds
Started Jul 11 07:33:41 PM PDT 24
Finished Jul 11 07:33:58 PM PDT 24
Peak memory 213720 kb
Host smart-0c302529-b3ce-4bd0-beaf-e98388801e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133528953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.4133528953
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1981210769
Short name T1239
Test name
Test status
Simulation time 1133348860 ps
CPU time 12.75 seconds
Started Jul 11 07:33:38 PM PDT 24
Finished Jul 11 07:33:52 PM PDT 24
Peak memory 205364 kb
Host smart-15bcdb36-3819-44ff-b4ee-d49cd2035098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981210769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1981210769
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.4076248054
Short name T1560
Test name
Test status
Simulation time 8574943222 ps
CPU time 5.23 seconds
Started Jul 11 07:33:39 PM PDT 24
Finished Jul 11 07:33:45 PM PDT 24
Peak memory 205600 kb
Host smart-a10fe512-eb19-422d-a173-b20f45eabc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076248054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.4076248054
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.101631558
Short name T499
Test name
Test status
Simulation time 3709290634 ps
CPU time 45.45 seconds
Started Jul 11 07:33:37 PM PDT 24
Finished Jul 11 07:34:23 PM PDT 24
Peak memory 838248 kb
Host smart-1285959f-5bd8-459c-be6b-69c6b2d94b7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101631558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.101631558
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.851245136
Short name T824
Test name
Test status
Simulation time 1192280491 ps
CPU time 7.2 seconds
Started Jul 11 07:33:46 PM PDT 24
Finished Jul 11 07:33:54 PM PDT 24
Peak memory 238220 kb
Host smart-51470667-a42b-4934-8195-a3e1bbc3676b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851245136 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.851245136
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3328700186
Short name T1444
Test name
Test status
Simulation time 154756183 ps
CPU time 3.34 seconds
Started Jul 11 07:33:47 PM PDT 24
Finished Jul 11 07:33:52 PM PDT 24
Peak memory 205460 kb
Host smart-233d81cf-7b58-489f-a210-c1d95e13594e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328700186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3328700186
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.326435182
Short name T1515
Test name
Test status
Simulation time 19666432 ps
CPU time 0.65 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:33:57 PM PDT 24
Peak memory 204716 kb
Host smart-b9d60b29-672a-467a-8fd5-048fbe5f60d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326435182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.326435182
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2217268717
Short name T1380
Test name
Test status
Simulation time 478714181 ps
CPU time 4.23 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:55 PM PDT 24
Peak memory 213700 kb
Host smart-fa9c2045-8ed1-4298-9be8-e4714b702052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217268717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2217268717
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1224180245
Short name T503
Test name
Test status
Simulation time 425371660 ps
CPU time 7.63 seconds
Started Jul 11 07:33:50 PM PDT 24
Finished Jul 11 07:33:59 PM PDT 24
Peak memory 293640 kb
Host smart-9d6ef450-ee13-4e8d-81fd-646b6794b24b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224180245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1224180245
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3643967033
Short name T1440
Test name
Test status
Simulation time 3146573455 ps
CPU time 87.42 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:35:18 PM PDT 24
Peak memory 383728 kb
Host smart-26f2772b-646b-4765-bb91-7250145e1ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643967033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3643967033
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3419051475
Short name T657
Test name
Test status
Simulation time 1243148330 ps
CPU time 74.95 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:35:05 PM PDT 24
Peak memory 419740 kb
Host smart-18a33058-ceaf-45da-98fa-ce17b00f558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419051475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3419051475
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2606684430
Short name T1435
Test name
Test status
Simulation time 398251099 ps
CPU time 1.23 seconds
Started Jul 11 07:33:47 PM PDT 24
Finished Jul 11 07:33:50 PM PDT 24
Peak memory 205244 kb
Host smart-229b367d-d9c0-4667-9f54-0b15a720d9e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606684430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2606684430
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3841070901
Short name T1266
Test name
Test status
Simulation time 159059878 ps
CPU time 9.15 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 234216 kb
Host smart-2bd1d918-b202-4fc5-8b62-2b410e596df5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841070901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3841070901
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1178637854
Short name T1081
Test name
Test status
Simulation time 103529294244 ps
CPU time 171.01 seconds
Started Jul 11 07:33:58 PM PDT 24
Finished Jul 11 07:36:51 PM PDT 24
Peak memory 1529236 kb
Host smart-ed3fb671-2e86-494c-9c7a-f56f84acef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178637854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1178637854
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.69860798
Short name T913
Test name
Test status
Simulation time 353181859 ps
CPU time 4.49 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:04 PM PDT 24
Peak memory 205344 kb
Host smart-d43e2b2b-9f70-4c40-8c2b-f2710e0d59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69860798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.69860798
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.113300495
Short name T754
Test name
Test status
Simulation time 46749056 ps
CPU time 0.68 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:33:52 PM PDT 24
Peak memory 205136 kb
Host smart-2188a706-4874-4268-9b6f-6b803f2570a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113300495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.113300495
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3660671025
Short name T1154
Test name
Test status
Simulation time 418504046 ps
CPU time 3.41 seconds
Started Jul 11 07:33:50 PM PDT 24
Finished Jul 11 07:33:55 PM PDT 24
Peak memory 205392 kb
Host smart-837cb1bb-3fc6-49f5-b930-957636fbe7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660671025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3660671025
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1954800533
Short name T867
Test name
Test status
Simulation time 159850961 ps
CPU time 0.99 seconds
Started Jul 11 07:34:04 PM PDT 24
Finished Jul 11 07:34:08 PM PDT 24
Peak memory 205140 kb
Host smart-6056c0a5-6849-46de-8391-346bdb0829f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954800533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1954800533
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.738423845
Short name T1528
Test name
Test status
Simulation time 6608709897 ps
CPU time 66.32 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:35:10 PM PDT 24
Peak memory 283828 kb
Host smart-1264346b-f9f2-4c6c-8aef-2fb9714b98da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738423845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.738423845
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1923115610
Short name T300
Test name
Test status
Simulation time 914663083 ps
CPU time 43.01 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:34:45 PM PDT 24
Peak memory 213620 kb
Host smart-df79ff1b-39a6-453c-960f-54b6d9babb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923115610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1923115610
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2618213006
Short name T646
Test name
Test status
Simulation time 561895836 ps
CPU time 3.2 seconds
Started Jul 11 07:33:56 PM PDT 24
Finished Jul 11 07:34:01 PM PDT 24
Peak memory 221900 kb
Host smart-0ab8d1cf-b4c2-47fd-847a-fb9c2cd3a405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618213006 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2618213006
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.54812045
Short name T1104
Test name
Test status
Simulation time 215125187 ps
CPU time 0.94 seconds
Started Jul 11 07:33:58 PM PDT 24
Finished Jul 11 07:34:02 PM PDT 24
Peak memory 205404 kb
Host smart-9d7f0c00-6a25-4c53-8277-758f6ac5c9b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54812045 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_acq.54812045
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1966520002
Short name T1457
Test name
Test status
Simulation time 225136173 ps
CPU time 1.43 seconds
Started Jul 11 07:33:54 PM PDT 24
Finished Jul 11 07:33:57 PM PDT 24
Peak memory 210692 kb
Host smart-fcd9f08f-31c9-4ba3-bfc0-437d6821e336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966520002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1966520002
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.4132215163
Short name T1326
Test name
Test status
Simulation time 500269002 ps
CPU time 1.36 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:33:58 PM PDT 24
Peak memory 205400 kb
Host smart-4cd57490-f1c3-4113-b3f8-fd2b28b50c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132215163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.4132215163
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3826467712
Short name T797
Test name
Test status
Simulation time 170879549 ps
CPU time 1.62 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:01 PM PDT 24
Peak memory 205364 kb
Host smart-b3aeec1d-62ca-4cdd-8604-9aa1660f4aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826467712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3826467712
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.877279716
Short name T644
Test name
Test status
Simulation time 7230892789 ps
CPU time 7.48 seconds
Started Jul 11 07:33:47 PM PDT 24
Finished Jul 11 07:33:56 PM PDT 24
Peak memory 221912 kb
Host smart-81279d3e-3c68-44be-bdfe-791e757559aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877279716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_intr_smoke.877279716
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2317947373
Short name T1517
Test name
Test status
Simulation time 17056872809 ps
CPU time 365.09 seconds
Started Jul 11 07:33:49 PM PDT 24
Finished Jul 11 07:39:56 PM PDT 24
Peak memory 4162804 kb
Host smart-56f23efd-f510-4f28-9aa9-8cbf43ac9592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317947373 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2317947373
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.4246658117
Short name T498
Test name
Test status
Simulation time 453042936 ps
CPU time 2.59 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:02 PM PDT 24
Peak memory 213716 kb
Host smart-9ca0417a-1463-4bb9-8099-1fef1f5b9205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246658117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.4246658117
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.1181787710
Short name T1414
Test name
Test status
Simulation time 980330129 ps
CPU time 2.6 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:02 PM PDT 24
Peak memory 205488 kb
Host smart-9cf69422-ff2d-4b96-a7ee-416da0c50579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181787710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.1181787710
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.136875389
Short name T551
Test name
Test status
Simulation time 2038881864 ps
CPU time 2.45 seconds
Started Jul 11 07:33:56 PM PDT 24
Finished Jul 11 07:34:01 PM PDT 24
Peak memory 205352 kb
Host smart-b7804f4e-b023-4c3b-8ee6-a44aaf71c6dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136875389 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_smbus_maxlen.136875389
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1142812867
Short name T582
Test name
Test status
Simulation time 2732343165 ps
CPU time 23.06 seconds
Started Jul 11 07:33:48 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 213820 kb
Host smart-d23f2406-285d-4dbd-91e1-ccdba961582e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142812867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1142812867
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3923666526
Short name T903
Test name
Test status
Simulation time 884508632 ps
CPU time 17.33 seconds
Started Jul 11 07:33:50 PM PDT 24
Finished Jul 11 07:34:08 PM PDT 24
Peak memory 221764 kb
Host smart-4e8972f3-a4e0-47d4-886d-8e5d8097b64d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923666526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3923666526
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1912587122
Short name T281
Test name
Test status
Simulation time 59196891233 ps
CPU time 764.66 seconds
Started Jul 11 07:33:50 PM PDT 24
Finished Jul 11 07:46:36 PM PDT 24
Peak memory 5053016 kb
Host smart-62ec346c-abec-476f-9429-91809012b216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912587122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1912587122
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2698613037
Short name T1369
Test name
Test status
Simulation time 4577779466 ps
CPU time 17.48 seconds
Started Jul 11 07:33:48 PM PDT 24
Finished Jul 11 07:34:07 PM PDT 24
Peak memory 388404 kb
Host smart-09bf2518-ecf8-43af-961d-9e4f1943bab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698613037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2698613037
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3767354539
Short name T661
Test name
Test status
Simulation time 6937172903 ps
CPU time 6.21 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:34:10 PM PDT 24
Peak memory 221776 kb
Host smart-1624ea17-1f03-4f88-9c88-555b7ca14f5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767354539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3767354539
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.1422473891
Short name T634
Test name
Test status
Simulation time 571428281 ps
CPU time 7.55 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:34:03 PM PDT 24
Peak memory 205488 kb
Host smart-392cd7ce-9b15-478d-89f2-ce6e7fd31ed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422473891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.1422473891
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2569224120
Short name T817
Test name
Test status
Simulation time 25089049 ps
CPU time 0.63 seconds
Started Jul 11 07:34:07 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 204884 kb
Host smart-45df85b5-8fc3-4721-8d6f-dd3860bcdde6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569224120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2569224120
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.707001249
Short name T1017
Test name
Test status
Simulation time 75342137 ps
CPU time 2.18 seconds
Started Jul 11 07:34:01 PM PDT 24
Finished Jul 11 07:34:07 PM PDT 24
Peak memory 213668 kb
Host smart-a69445e6-93ba-4ecf-80af-dba6188d33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707001249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.707001249
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.10804773
Short name T562
Test name
Test status
Simulation time 1131183044 ps
CPU time 5.6 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 264368 kb
Host smart-52b27aff-4ec2-4bf3-9f76-2e65d55ba5df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10804773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty
.10804773
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3850884884
Short name T691
Test name
Test status
Simulation time 11414165621 ps
CPU time 107.25 seconds
Started Jul 11 07:34:01 PM PDT 24
Finished Jul 11 07:35:52 PM PDT 24
Peak memory 919032 kb
Host smart-77a56acd-996f-4781-b203-c724305f84de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850884884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3850884884
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1889613551
Short name T138
Test name
Test status
Simulation time 1838248339 ps
CPU time 123.21 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:36:02 PM PDT 24
Peak memory 574672 kb
Host smart-0d856552-459c-416d-af08-1f1cc287b10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889613551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1889613551
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2320941535
Short name T539
Test name
Test status
Simulation time 719579229 ps
CPU time 3.61 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:34:07 PM PDT 24
Peak memory 229868 kb
Host smart-a42269fe-879a-480f-a8c6-c3598dde27e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320941535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2320941535
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2695661761
Short name T912
Test name
Test status
Simulation time 4105600016 ps
CPU time 280.81 seconds
Started Jul 11 07:33:55 PM PDT 24
Finished Jul 11 07:38:38 PM PDT 24
Peak memory 1161836 kb
Host smart-466f627d-3b35-4f22-b7db-ac63bf4ea05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695661761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2695661761
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_override.1427059292
Short name T1308
Test name
Test status
Simulation time 17275815 ps
CPU time 0.69 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:34:00 PM PDT 24
Peak memory 205128 kb
Host smart-80705467-e4fd-4413-8eaf-f424d0b6d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427059292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1427059292
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2085287780
Short name T118
Test name
Test status
Simulation time 4344564774 ps
CPU time 25.05 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:33 PM PDT 24
Peak memory 325568 kb
Host smart-1dd9b649-d077-4984-8a23-67fee3a001a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085287780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2085287780
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.2272875220
Short name T286
Test name
Test status
Simulation time 94901792 ps
CPU time 1.91 seconds
Started Jul 11 07:34:04 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 205220 kb
Host smart-747b8cca-ff40-4a16-9376-a7eb7828c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272875220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.2272875220
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2134764912
Short name T669
Test name
Test status
Simulation time 7989592909 ps
CPU time 99.98 seconds
Started Jul 11 07:33:57 PM PDT 24
Finished Jul 11 07:35:39 PM PDT 24
Peak memory 383008 kb
Host smart-aa5f2c3f-5712-44df-a508-4265c2f7752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134764912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2134764912
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.4196758768
Short name T1061
Test name
Test status
Simulation time 512527541 ps
CPU time 8.73 seconds
Started Jul 11 07:34:04 PM PDT 24
Finished Jul 11 07:34:16 PM PDT 24
Peak memory 221680 kb
Host smart-c862630d-0a74-464b-8f29-d698306370ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196758768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.4196758768
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2363563150
Short name T583
Test name
Test status
Simulation time 1276570735 ps
CPU time 5.83 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:14 PM PDT 24
Peak memory 221868 kb
Host smart-44265bfd-8457-4f78-854c-3f375393d018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363563150 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2363563150
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1213541042
Short name T764
Test name
Test status
Simulation time 409789800 ps
CPU time 0.95 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 205392 kb
Host smart-aa3216f1-d95d-40e8-bb14-4912821315ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213541042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1213541042
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3163497390
Short name T145
Test name
Test status
Simulation time 246134323 ps
CPU time 1.42 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:34:05 PM PDT 24
Peak memory 205428 kb
Host smart-7a8eab38-8fbf-4e9e-bd2f-79a6aa4e29a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163497390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3163497390
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.3045401754
Short name T510
Test name
Test status
Simulation time 2229850915 ps
CPU time 2.93 seconds
Started Jul 11 07:34:01 PM PDT 24
Finished Jul 11 07:34:07 PM PDT 24
Peak memory 205564 kb
Host smart-41c79f18-156c-47bb-9941-7863f721865d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045401754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.3045401754
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.998279015
Short name T92
Test name
Test status
Simulation time 688957829 ps
CPU time 1.42 seconds
Started Jul 11 07:34:07 PM PDT 24
Finished Jul 11 07:34:10 PM PDT 24
Peak memory 205392 kb
Host smart-7d6790e4-77bb-4485-a4f8-979e2e20c5e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998279015 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.998279015
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.781792700
Short name T1106
Test name
Test status
Simulation time 1378711304 ps
CPU time 4.27 seconds
Started Jul 11 07:34:03 PM PDT 24
Finished Jul 11 07:34:10 PM PDT 24
Peak memory 217972 kb
Host smart-c6f0c854-cfe0-4993-a501-4fa8a4a8b1a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781792700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.781792700
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4275630849
Short name T537
Test name
Test status
Simulation time 18361704033 ps
CPU time 117.52 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:36:00 PM PDT 24
Peak memory 1509196 kb
Host smart-2cf40cd6-ed49-477d-a13e-f26beb522bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275630849 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4275630849
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.3657434744
Short name T402
Test name
Test status
Simulation time 2214721733 ps
CPU time 3.13 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:11 PM PDT 24
Peak memory 213816 kb
Host smart-55dc592a-7488-493c-8772-1db85f6d89e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657434744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.3657434744
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1199845478
Short name T505
Test name
Test status
Simulation time 1862149623 ps
CPU time 2.75 seconds
Started Jul 11 07:34:04 PM PDT 24
Finished Jul 11 07:34:10 PM PDT 24
Peak memory 205452 kb
Host smart-8412d469-3f7a-4d2b-b3a8-a7cc996c3558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199845478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1199845478
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.3173721344
Short name T724
Test name
Test status
Simulation time 1818527606 ps
CPU time 2.01 seconds
Started Jul 11 07:34:07 PM PDT 24
Finished Jul 11 07:34:11 PM PDT 24
Peak memory 205332 kb
Host smart-3d42dd70-82f8-4407-acad-eaa5d3226ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173721344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.3173721344
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.787952631
Short name T86
Test name
Test status
Simulation time 1009969578 ps
CPU time 11.84 seconds
Started Jul 11 07:34:00 PM PDT 24
Finished Jul 11 07:34:16 PM PDT 24
Peak memory 213688 kb
Host smart-e7f03996-9433-4dff-844d-ccbdc8011ed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787952631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.787952631
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3353181388
Short name T450
Test name
Test status
Simulation time 3675003344 ps
CPU time 11.88 seconds
Started Jul 11 07:34:01 PM PDT 24
Finished Jul 11 07:34:17 PM PDT 24
Peak memory 221816 kb
Host smart-ea1c9c3b-177a-4344-9598-f66f2aba35f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353181388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3353181388
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.4174985621
Short name T308
Test name
Test status
Simulation time 10011229664 ps
CPU time 20.1 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:34:23 PM PDT 24
Peak memory 205544 kb
Host smart-3af8f71c-7f4e-49ef-aea8-2cd68e6e6c23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174985621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.4174985621
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3334128908
Short name T1033
Test name
Test status
Simulation time 3905756952 ps
CPU time 4.8 seconds
Started Jul 11 07:34:01 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 241804 kb
Host smart-054458da-4060-4f26-a487-15d399394895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334128908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3334128908
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2963798859
Short name T1285
Test name
Test status
Simulation time 1071030041 ps
CPU time 6.29 seconds
Started Jul 11 07:34:03 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 221816 kb
Host smart-81f099f8-c950-423b-9073-cd4605d7c9b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963798859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2963798859
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.3546773484
Short name T1334
Test name
Test status
Simulation time 217584867 ps
CPU time 3.45 seconds
Started Jul 11 07:33:59 PM PDT 24
Finished Jul 11 07:34:06 PM PDT 24
Peak memory 205428 kb
Host smart-9b55fa3f-099a-4ac8-9dec-bbcdbf2afb86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546773484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3546773484
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1294341318
Short name T327
Test name
Test status
Simulation time 52578414 ps
CPU time 0.66 seconds
Started Jul 11 07:34:16 PM PDT 24
Finished Jul 11 07:34:17 PM PDT 24
Peak memory 204672 kb
Host smart-6bd87c7d-610c-4d59-bbac-9ac7c58e55cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294341318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1294341318
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.517494142
Short name T882
Test name
Test status
Simulation time 162051759 ps
CPU time 3.47 seconds
Started Jul 11 07:34:14 PM PDT 24
Finished Jul 11 07:34:18 PM PDT 24
Peak memory 221764 kb
Host smart-09008c2f-24a6-4558-8a89-e44e2803906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517494142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.517494142
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1743354225
Short name T944
Test name
Test status
Simulation time 902500911 ps
CPU time 23.29 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:31 PM PDT 24
Peak memory 268580 kb
Host smart-475c5e5f-a08c-4937-9d5f-945674506d74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743354225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1743354225
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.215638183
Short name T77
Test name
Test status
Simulation time 5013579486 ps
CPU time 73.91 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:35:22 PM PDT 24
Peak memory 806100 kb
Host smart-c0254083-3059-4003-8270-4b060b9bd020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215638183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.215638183
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.275769854
Short name T527
Test name
Test status
Simulation time 15506959552 ps
CPU time 90.84 seconds
Started Jul 11 07:34:53 PM PDT 24
Finished Jul 11 07:36:24 PM PDT 24
Peak memory 864116 kb
Host smart-4d1460d3-c125-4fbf-a344-b34eb95c7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275769854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.275769854
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3834911770
Short name T1388
Test name
Test status
Simulation time 355911835 ps
CPU time 1.08 seconds
Started Jul 11 07:34:09 PM PDT 24
Finished Jul 11 07:34:11 PM PDT 24
Peak memory 205144 kb
Host smart-5d321977-a7f6-4d7d-8cf6-3a7712aa7695
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834911770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3834911770
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2761651499
Short name T640
Test name
Test status
Simulation time 728212200 ps
CPU time 2.71 seconds
Started Jul 11 07:34:05 PM PDT 24
Finished Jul 11 07:34:11 PM PDT 24
Peak memory 205404 kb
Host smart-9d22def3-2648-4a1c-a98f-2363bf8fbe8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761651499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2761651499
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1375153389
Short name T884
Test name
Test status
Simulation time 51880247143 ps
CPU time 419.91 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:41:08 PM PDT 24
Peak memory 1529304 kb
Host smart-245c3bf4-2734-42a3-a974-8bb2261e9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375153389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1375153389
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3511355610
Short name T1060
Test name
Test status
Simulation time 356900032 ps
CPU time 4.6 seconds
Started Jul 11 07:34:13 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 205380 kb
Host smart-e5140689-ccb9-4a03-9504-c18e455a7296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511355610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3511355610
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.598506640
Short name T68
Test name
Test status
Simulation time 102651511 ps
CPU time 0.7 seconds
Started Jul 11 07:34:06 PM PDT 24
Finished Jul 11 07:34:09 PM PDT 24
Peak memory 205136 kb
Host smart-c06d4187-f490-4859-8799-467e4907803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598506640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.598506640
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1104382760
Short name T834
Test name
Test status
Simulation time 50586502940 ps
CPU time 64.05 seconds
Started Jul 11 07:34:05 PM PDT 24
Finished Jul 11 07:35:11 PM PDT 24
Peak memory 259132 kb
Host smart-fcccae94-f436-44ad-8c8f-c4120b6d24aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104382760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1104382760
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.2311322505
Short name T1067
Test name
Test status
Simulation time 1590317730 ps
CPU time 63.76 seconds
Started Jul 11 07:34:07 PM PDT 24
Finished Jul 11 07:35:13 PM PDT 24
Peak memory 420568 kb
Host smart-deda672d-6c86-4d37-80d6-11d887b57067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311322505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.2311322505
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2645817015
Short name T1470
Test name
Test status
Simulation time 1275980801 ps
CPU time 20.56 seconds
Started Jul 11 07:34:07 PM PDT 24
Finished Jul 11 07:34:29 PM PDT 24
Peak memory 278808 kb
Host smart-2378d76b-c2cd-4eed-8d36-d05ed7b27ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645817015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2645817015
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.4174036631
Short name T1401
Test name
Test status
Simulation time 2686787527 ps
CPU time 13.71 seconds
Started Jul 11 07:34:11 PM PDT 24
Finished Jul 11 07:34:26 PM PDT 24
Peak memory 221220 kb
Host smart-bbbbae21-3723-46b9-a59e-13b83e681eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174036631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.4174036631
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1754317398
Short name T1298
Test name
Test status
Simulation time 913807124 ps
CPU time 5.35 seconds
Started Jul 11 07:34:14 PM PDT 24
Finished Jul 11 07:34:20 PM PDT 24
Peak memory 221912 kb
Host smart-6faeb6c3-5491-4991-a7f6-4baf909e7a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754317398 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1754317398
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1054730941
Short name T1304
Test name
Test status
Simulation time 475703078 ps
CPU time 1 seconds
Started Jul 11 07:34:14 PM PDT 24
Finished Jul 11 07:34:16 PM PDT 24
Peak memory 205432 kb
Host smart-56ca728e-d2de-40d7-8ccf-e29e61206a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054730941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1054730941
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.643854362
Short name T295
Test name
Test status
Simulation time 263001563 ps
CPU time 1.14 seconds
Started Jul 11 07:34:12 PM PDT 24
Finished Jul 11 07:34:14 PM PDT 24
Peak memory 205484 kb
Host smart-b02a37e7-9adb-4939-b558-7c49fb7ef39d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643854362 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.643854362
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.2981427748
Short name T1058
Test name
Test status
Simulation time 373694481 ps
CPU time 2.31 seconds
Started Jul 11 07:34:10 PM PDT 24
Finished Jul 11 07:34:13 PM PDT 24
Peak memory 205440 kb
Host smart-bbbc6919-e1c3-483b-bb86-72edaf0bb7ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981427748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.2981427748
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.472883195
Short name T1370
Test name
Test status
Simulation time 716017368 ps
CPU time 1.38 seconds
Started Jul 11 07:34:17 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 205340 kb
Host smart-325973fe-c355-4573-99a5-2c3f0ea891b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472883195 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.472883195
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1886310191
Short name T1005
Test name
Test status
Simulation time 5777312650 ps
CPU time 8.56 seconds
Started Jul 11 07:34:11 PM PDT 24
Finished Jul 11 07:34:20 PM PDT 24
Peak memory 220536 kb
Host smart-04048d4b-52e7-4368-9f73-a34db0d9f20e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886310191 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1886310191
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1130022387
Short name T952
Test name
Test status
Simulation time 16242284242 ps
CPU time 28.46 seconds
Started Jul 11 07:34:13 PM PDT 24
Finished Jul 11 07:34:43 PM PDT 24
Peak memory 595468 kb
Host smart-4986845b-3f8d-4e34-9026-23765f59cdaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130022387 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1130022387
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.2086180624
Short name T1102
Test name
Test status
Simulation time 471842442 ps
CPU time 3 seconds
Started Jul 11 07:34:18 PM PDT 24
Finished Jul 11 07:34:22 PM PDT 24
Peak memory 213664 kb
Host smart-5cc53fd9-aecf-4a36-b15e-3e4da0a3bcb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086180624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.2086180624
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.1790318009
Short name T42
Test name
Test status
Simulation time 2379393893 ps
CPU time 2.9 seconds
Started Jul 11 07:34:15 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 205552 kb
Host smart-b2c66eeb-7d69-447b-8216-0995f4871c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790318009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.1790318009
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.3275657061
Short name T139
Test name
Test status
Simulation time 1455977108 ps
CPU time 2.16 seconds
Started Jul 11 07:34:17 PM PDT 24
Finished Jul 11 07:34:20 PM PDT 24
Peak memory 205312 kb
Host smart-ee0e4caa-a33e-4818-8629-71822b66ca78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275657061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.3275657061
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1152934595
Short name T287
Test name
Test status
Simulation time 1965254984 ps
CPU time 12.15 seconds
Started Jul 11 07:34:14 PM PDT 24
Finished Jul 11 07:34:27 PM PDT 24
Peak memory 213724 kb
Host smart-d95dc358-183a-4d2b-ba0e-cf6cea012863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152934595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1152934595
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2392760920
Short name T1142
Test name
Test status
Simulation time 4967184678 ps
CPU time 62.42 seconds
Started Jul 11 07:34:13 PM PDT 24
Finished Jul 11 07:35:16 PM PDT 24
Peak memory 218204 kb
Host smart-0f33ca55-2593-41e0-9f79-75a0845bd3f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392760920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2392760920
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1801725339
Short name T1439
Test name
Test status
Simulation time 58990448285 ps
CPU time 2461.26 seconds
Started Jul 11 07:34:20 PM PDT 24
Finished Jul 11 08:15:23 PM PDT 24
Peak memory 9738212 kb
Host smart-3c060628-3127-4d71-a7d9-9238aae6c3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801725339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1801725339
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1392496749
Short name T122
Test name
Test status
Simulation time 4285280811 ps
CPU time 227.39 seconds
Started Jul 11 07:34:17 PM PDT 24
Finished Jul 11 07:38:05 PM PDT 24
Peak memory 1107476 kb
Host smart-983092e5-5a80-4e98-8056-4b7d3b23598c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392496749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1392496749
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3592540136
Short name T400
Test name
Test status
Simulation time 1182593292 ps
CPU time 7.18 seconds
Started Jul 11 07:34:13 PM PDT 24
Finished Jul 11 07:34:22 PM PDT 24
Peak memory 230132 kb
Host smart-365c0956-5ec2-4a0c-8178-edfee4814197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592540136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3592540136
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3894207685
Short name T1182
Test name
Test status
Simulation time 49540121 ps
CPU time 0.69 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:38 PM PDT 24
Peak memory 204748 kb
Host smart-d5b910c0-90b2-487f-b705-de83c5e9dc73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894207685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3894207685
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2152412487
Short name T1497
Test name
Test status
Simulation time 132631863 ps
CPU time 1.83 seconds
Started Jul 11 07:34:27 PM PDT 24
Finished Jul 11 07:34:29 PM PDT 24
Peak memory 213620 kb
Host smart-381ff804-5ed5-4589-bd50-1344362bccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152412487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2152412487
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.536533327
Short name T1139
Test name
Test status
Simulation time 433047098 ps
CPU time 9.44 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:42 PM PDT 24
Peak memory 299584 kb
Host smart-4c403735-bc3a-410f-93ef-1e164f8e8179
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536533327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.536533327
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1906706270
Short name T72
Test name
Test status
Simulation time 7081278788 ps
CPU time 119.61 seconds
Started Jul 11 07:34:22 PM PDT 24
Finished Jul 11 07:36:22 PM PDT 24
Peak memory 602492 kb
Host smart-87a07a90-6093-409f-aa3f-5dcbbc9984f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906706270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1906706270
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2592307035
Short name T792
Test name
Test status
Simulation time 7954550571 ps
CPU time 144.01 seconds
Started Jul 11 07:34:27 PM PDT 24
Finished Jul 11 07:36:52 PM PDT 24
Peak memory 680936 kb
Host smart-1ac1a99e-fdb9-4126-b2d8-f9e29337b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592307035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2592307035
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1764984972
Short name T994
Test name
Test status
Simulation time 420428038 ps
CPU time 1.13 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:34 PM PDT 24
Peak memory 205124 kb
Host smart-e64c501f-748c-48d5-bc53-851b202d9298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764984972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1764984972
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1405695827
Short name T966
Test name
Test status
Simulation time 165332507 ps
CPU time 4.11 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:37 PM PDT 24
Peak memory 205340 kb
Host smart-dadb48a1-8d81-4e6a-bc0c-ff569955a253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405695827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1405695827
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.828615740
Short name T1050
Test name
Test status
Simulation time 19081445485 ps
CPU time 346.03 seconds
Started Jul 11 07:34:16 PM PDT 24
Finished Jul 11 07:40:03 PM PDT 24
Peak memory 1370260 kb
Host smart-bd5bbee0-f9e9-4c99-9b88-b5a5b898418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828615740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.828615740
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2048514099
Short name T1216
Test name
Test status
Simulation time 283419999 ps
CPU time 10.66 seconds
Started Jul 11 07:34:29 PM PDT 24
Finished Jul 11 07:34:40 PM PDT 24
Peak memory 205296 kb
Host smart-d0e6b21e-0e28-4715-a9d2-5a0a14660be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048514099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2048514099
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.2110712583
Short name T1120
Test name
Test status
Simulation time 23214415 ps
CPU time 0.67 seconds
Started Jul 11 07:34:17 PM PDT 24
Finished Jul 11 07:34:19 PM PDT 24
Peak memory 205152 kb
Host smart-81c2829f-1c9f-4d4f-8160-6e1c6e7e7e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110712583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2110712583
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3160112778
Short name T1150
Test name
Test status
Simulation time 2433671229 ps
CPU time 93.9 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:36:06 PM PDT 24
Peak memory 205460 kb
Host smart-34311d13-1fd5-49b6-bf09-23f9ffa0bf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160112778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3160112778
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1948596237
Short name T750
Test name
Test status
Simulation time 3145657957 ps
CPU time 42.7 seconds
Started Jul 11 07:34:26 PM PDT 24
Finished Jul 11 07:35:10 PM PDT 24
Peak memory 205328 kb
Host smart-0646b826-1e2b-4229-8376-9e1547711c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948596237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1948596237
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3913126876
Short name T1389
Test name
Test status
Simulation time 14465546208 ps
CPU time 27.89 seconds
Started Jul 11 07:34:17 PM PDT 24
Finished Jul 11 07:34:46 PM PDT 24
Peak memory 352532 kb
Host smart-df17a7ee-214b-4a81-ab09-46201b36d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913126876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3913126876
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2924103857
Short name T1302
Test name
Test status
Simulation time 380975439 ps
CPU time 7.16 seconds
Started Jul 11 07:35:08 PM PDT 24
Finished Jul 11 07:35:15 PM PDT 24
Peak memory 213520 kb
Host smart-7a147992-e9b7-4eb0-9da0-2c6ecd33387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924103857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2924103857
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.812730361
Short name T1035
Test name
Test status
Simulation time 3314475895 ps
CPU time 4.36 seconds
Started Jul 11 07:34:29 PM PDT 24
Finished Jul 11 07:34:35 PM PDT 24
Peak memory 217872 kb
Host smart-5d95e7b8-5017-44e9-9d06-35491a666bee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812730361 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.812730361
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.401462233
Short name T1021
Test name
Test status
Simulation time 229576597 ps
CPU time 1.4 seconds
Started Jul 11 07:34:29 PM PDT 24
Finished Jul 11 07:34:32 PM PDT 24
Peak memory 205476 kb
Host smart-d885295a-ac14-4d73-acd4-6b3eb2596bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401462233 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.401462233
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4284079158
Short name T1484
Test name
Test status
Simulation time 184885305 ps
CPU time 1.21 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:33 PM PDT 24
Peak memory 205400 kb
Host smart-912f2748-a4e7-4440-82ea-507559a2f8da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284079158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4284079158
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2858853807
Short name T348
Test name
Test status
Simulation time 261502789 ps
CPU time 1.03 seconds
Started Jul 11 07:34:32 PM PDT 24
Finished Jul 11 07:34:35 PM PDT 24
Peak memory 205396 kb
Host smart-396f0ff2-6eb8-444d-86e3-5bc1f7290fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858853807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2858853807
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1685856564
Short name T729
Test name
Test status
Simulation time 466557685 ps
CPU time 1.29 seconds
Started Jul 11 07:34:28 PM PDT 24
Finished Jul 11 07:34:30 PM PDT 24
Peak memory 205336 kb
Host smart-414174f5-61f1-47a6-b257-a6ab15a499f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685856564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1685856564
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.760423494
Short name T1283
Test name
Test status
Simulation time 8165117571 ps
CPU time 8.02 seconds
Started Jul 11 07:34:29 PM PDT 24
Finished Jul 11 07:34:38 PM PDT 24
Peak memory 238320 kb
Host smart-7d97df5c-d948-43a1-a1b2-efd4a003986d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760423494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.760423494
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.4152621552
Short name T1118
Test name
Test status
Simulation time 13302894411 ps
CPU time 117.33 seconds
Started Jul 11 07:34:29 PM PDT 24
Finished Jul 11 07:36:28 PM PDT 24
Peak memory 1669704 kb
Host smart-147c860c-0655-4be5-917a-8b49a7b312de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152621552 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4152621552
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.4262735788
Short name T767
Test name
Test status
Simulation time 792318062 ps
CPU time 2.79 seconds
Started Jul 11 07:34:32 PM PDT 24
Finished Jul 11 07:34:36 PM PDT 24
Peak memory 213740 kb
Host smart-48710cba-f613-4337-955b-6ccd69b9ad42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262735788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.4262735788
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.1090812886
Short name T504
Test name
Test status
Simulation time 691155050 ps
CPU time 2.6 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:35 PM PDT 24
Peak memory 205456 kb
Host smart-085ec8d9-8040-4f5d-a729-11c4b8c3f215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090812886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.1090812886
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.460041770
Short name T1427
Test name
Test status
Simulation time 1773998953 ps
CPU time 2.24 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:35 PM PDT 24
Peak memory 205396 kb
Host smart-809a95ef-ee19-4ffd-bdc4-ea95afbe9db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460041770 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_smbus_maxlen.460041770
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.4129172967
Short name T366
Test name
Test status
Simulation time 1240407925 ps
CPU time 19.76 seconds
Started Jul 11 07:34:28 PM PDT 24
Finished Jul 11 07:34:49 PM PDT 24
Peak memory 213900 kb
Host smart-5f113f49-52af-4bd1-86d9-93b265bb280f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129172967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.4129172967
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1761383736
Short name T1254
Test name
Test status
Simulation time 3715394892 ps
CPU time 8.25 seconds
Started Jul 11 07:34:28 PM PDT 24
Finished Jul 11 07:34:37 PM PDT 24
Peak memory 217488 kb
Host smart-b3d21914-8919-4b28-a9cf-bfbb88b63eb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761383736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1761383736
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.4273487405
Short name T1309
Test name
Test status
Simulation time 22327949388 ps
CPU time 19.15 seconds
Started Jul 11 07:34:28 PM PDT 24
Finished Jul 11 07:34:48 PM PDT 24
Peak memory 273324 kb
Host smart-9640ab31-22e4-4133-8497-f37206f8c474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273487405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.4273487405
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1563313200
Short name T1178
Test name
Test status
Simulation time 3107840286 ps
CPU time 14.28 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:47 PM PDT 24
Peak memory 355420 kb
Host smart-7523c26d-5d69-46c4-8a72-59ed43d3f88a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563313200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1563313200
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.623923551
Short name T1013
Test name
Test status
Simulation time 2591855260 ps
CPU time 6.65 seconds
Started Jul 11 07:34:26 PM PDT 24
Finished Jul 11 07:34:34 PM PDT 24
Peak memory 221888 kb
Host smart-2de25378-7831-4958-9167-334ce663e836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623923551 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.623923551
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2617327728
Short name T1010
Test name
Test status
Simulation time 200542400 ps
CPU time 2.78 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:36 PM PDT 24
Peak memory 205480 kb
Host smart-cd34f2a8-04a7-4226-a9eb-a0a65e70b48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617327728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2617327728
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4206785608
Short name T557
Test name
Test status
Simulation time 128455800 ps
CPU time 0.61 seconds
Started Jul 11 07:34:43 PM PDT 24
Finished Jul 11 07:34:45 PM PDT 24
Peak memory 204684 kb
Host smart-dfe12225-a0bf-4c49-b472-4d8be798eca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206785608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4206785608
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.434251309
Short name T414
Test name
Test status
Simulation time 583946180 ps
CPU time 1.77 seconds
Started Jul 11 07:34:33 PM PDT 24
Finished Jul 11 07:34:36 PM PDT 24
Peak memory 213668 kb
Host smart-3d3604b9-b250-4df8-8c3b-10df752f3709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434251309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.434251309
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2007427202
Short name T1418
Test name
Test status
Simulation time 291324763 ps
CPU time 6.26 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 266372 kb
Host smart-a0bda6a3-9cfd-46b1-9c89-f8b0ee384e34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007427202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2007427202
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2693274948
Short name T23
Test name
Test status
Simulation time 10478449773 ps
CPU time 96.81 seconds
Started Jul 11 07:34:31 PM PDT 24
Finished Jul 11 07:36:10 PM PDT 24
Peak memory 836072 kb
Host smart-a974b0ed-0ec0-47cf-abf1-ed32f870cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693274948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2693274948
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3759908678
Short name T1536
Test name
Test status
Simulation time 1859049637 ps
CPU time 128.06 seconds
Started Jul 11 07:34:34 PM PDT 24
Finished Jul 11 07:36:43 PM PDT 24
Peak memory 612404 kb
Host smart-15ca16c2-88a7-4058-9faa-3a427b8a8bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759908678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3759908678
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3368127478
Short name T1091
Test name
Test status
Simulation time 108143958 ps
CPU time 1.09 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:40 PM PDT 24
Peak memory 205132 kb
Host smart-24f9cc1d-4f76-45a8-ada2-eb65120b4d27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368127478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3368127478
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2769598775
Short name T1280
Test name
Test status
Simulation time 292076134 ps
CPU time 3.17 seconds
Started Jul 11 07:34:32 PM PDT 24
Finished Jul 11 07:34:37 PM PDT 24
Peak memory 205332 kb
Host smart-8c8d147e-e6a5-408c-a384-7889ba7ad442
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769598775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2769598775
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3177531114
Short name T1057
Test name
Test status
Simulation time 2611071076 ps
CPU time 69.19 seconds
Started Jul 11 07:35:27 PM PDT 24
Finished Jul 11 07:36:37 PM PDT 24
Peak memory 856616 kb
Host smart-4fd314c6-d507-4cc5-88b0-222abcc62be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177531114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3177531114
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.525647833
Short name T749
Test name
Test status
Simulation time 369928545 ps
CPU time 15.16 seconds
Started Jul 11 07:34:44 PM PDT 24
Finished Jul 11 07:35:01 PM PDT 24
Peak memory 205404 kb
Host smart-0fb0b094-3b16-4af0-9db4-d53f0a88ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525647833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.525647833
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_override.1808255057
Short name T682
Test name
Test status
Simulation time 27403142 ps
CPU time 0.68 seconds
Started Jul 11 07:34:32 PM PDT 24
Finished Jul 11 07:34:34 PM PDT 24
Peak memory 205164 kb
Host smart-60984bc2-e5a8-49c2-b3a1-d9df11221e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808255057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1808255057
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3659502198
Short name T1144
Test name
Test status
Simulation time 26617622365 ps
CPU time 1093.83 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:52:52 PM PDT 24
Peak memory 205488 kb
Host smart-0d355604-d511-43b0-9bcb-358ca63a4a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659502198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3659502198
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.1154081337
Short name T1279
Test name
Test status
Simulation time 220493822 ps
CPU time 3.97 seconds
Started Jul 11 07:34:33 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 229780 kb
Host smart-b03ac03a-ab0c-47f1-8764-92123c505ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154081337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.1154081337
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2103285012
Short name T30
Test name
Test status
Simulation time 1741725888 ps
CPU time 29.56 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:35:09 PM PDT 24
Peak memory 358924 kb
Host smart-209bd014-a3de-4a6b-b0cc-934fc970c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103285012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2103285012
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3558997444
Short name T541
Test name
Test status
Simulation time 450722362 ps
CPU time 8.9 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:47 PM PDT 24
Peak memory 213588 kb
Host smart-554c883c-8cdf-421c-a506-afaac88cc3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558997444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3558997444
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.401120589
Short name T57
Test name
Test status
Simulation time 3132841117 ps
CPU time 4.02 seconds
Started Jul 11 07:34:40 PM PDT 24
Finished Jul 11 07:34:45 PM PDT 24
Peak memory 213780 kb
Host smart-dcb61dc7-bbf1-4aef-ab39-fbbfd7fd2dc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401120589 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.401120589
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3253589091
Short name T889
Test name
Test status
Simulation time 147392667 ps
CPU time 0.97 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:39 PM PDT 24
Peak memory 205304 kb
Host smart-296e72d0-bf3f-4e56-98f2-9cbc36cc499e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253589091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3253589091
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.271722490
Short name T558
Test name
Test status
Simulation time 702046453 ps
CPU time 1.31 seconds
Started Jul 11 07:34:44 PM PDT 24
Finished Jul 11 07:34:47 PM PDT 24
Peak memory 205536 kb
Host smart-62f1fa84-dc25-454a-b60c-1c81f4219290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271722490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.271722490
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2596636826
Short name T487
Test name
Test status
Simulation time 515684750 ps
CPU time 2.56 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:41 PM PDT 24
Peak memory 205456 kb
Host smart-54a6aa6b-bf50-4d9c-9347-dc25677cac73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596636826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2596636826
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.92468517
Short name T1249
Test name
Test status
Simulation time 128404295 ps
CPU time 0.91 seconds
Started Jul 11 07:34:40 PM PDT 24
Finished Jul 11 07:34:42 PM PDT 24
Peak memory 205404 kb
Host smart-cfe73900-19a6-4124-bcf9-59564ac9eb12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92468517 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.92468517
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2400023828
Short name T1350
Test name
Test status
Simulation time 325436274 ps
CPU time 2.62 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:41 PM PDT 24
Peak memory 213768 kb
Host smart-bdc4d4e5-c642-4d81-bd2d-6fdf4d26f574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400023828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2400023828
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.881558312
Short name T310
Test name
Test status
Simulation time 14821381484 ps
CPU time 21.22 seconds
Started Jul 11 07:34:42 PM PDT 24
Finished Jul 11 07:35:04 PM PDT 24
Peak memory 508636 kb
Host smart-97b3fea1-9a79-432c-947d-faa4f899d46c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881558312 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.881558312
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.601104611
Short name T663
Test name
Test status
Simulation time 854835938 ps
CPU time 2.63 seconds
Started Jul 11 07:34:47 PM PDT 24
Finished Jul 11 07:34:50 PM PDT 24
Peak memory 213600 kb
Host smart-a9be3f5e-ac00-4f33-ad6a-f9107053719f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601104611 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_nack_acqfull.601104611
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.1180380691
Short name T1412
Test name
Test status
Simulation time 1335815976 ps
CPU time 2.52 seconds
Started Jul 11 07:34:43 PM PDT 24
Finished Jul 11 07:34:47 PM PDT 24
Peak memory 205456 kb
Host smart-79e8eb44-826a-428f-b5e2-8bc91e3e3b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180380691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.1180380691
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.4265743889
Short name T1505
Test name
Test status
Simulation time 1534268101 ps
CPU time 2.29 seconds
Started Jul 11 07:34:45 PM PDT 24
Finished Jul 11 07:34:48 PM PDT 24
Peak memory 205368 kb
Host smart-7d143cd6-dc45-4e56-8f47-0689b065b37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265743889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.4265743889
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2364230190
Short name T188
Test name
Test status
Simulation time 1547497749 ps
CPU time 25.24 seconds
Started Jul 11 07:34:36 PM PDT 24
Finished Jul 11 07:35:02 PM PDT 24
Peak memory 213616 kb
Host smart-5cd188f6-6e9b-4906-b30a-ad42e2771292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364230190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2364230190
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1827664763
Short name T548
Test name
Test status
Simulation time 1794129589 ps
CPU time 13.8 seconds
Started Jul 11 07:34:41 PM PDT 24
Finished Jul 11 07:34:56 PM PDT 24
Peak memory 224232 kb
Host smart-ab0f34e2-96c7-47d6-be1b-26672e05a781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827664763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1827664763
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2915629409
Short name T1193
Test name
Test status
Simulation time 32452984805 ps
CPU time 91.37 seconds
Started Jul 11 07:34:39 PM PDT 24
Finished Jul 11 07:36:12 PM PDT 24
Peak memory 1549140 kb
Host smart-fee9adae-16c6-407c-857c-4e27a72daf4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915629409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2915629409
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.396216432
Short name T373
Test name
Test status
Simulation time 1591376610 ps
CPU time 14.13 seconds
Started Jul 11 07:34:37 PM PDT 24
Finished Jul 11 07:34:53 PM PDT 24
Peak memory 254136 kb
Host smart-8d4686c0-3b3a-4400-8dde-053ae9e169fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396216432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.396216432
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2396373547
Short name T1402
Test name
Test status
Simulation time 6562625497 ps
CPU time 6.33 seconds
Started Jul 11 07:34:38 PM PDT 24
Finished Jul 11 07:34:46 PM PDT 24
Peak memory 213760 kb
Host smart-0d6a142c-0f75-46ec-957c-40fe223fd547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396373547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2396373547
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.2624280027
Short name T642
Test name
Test status
Simulation time 595726334 ps
CPU time 6.7 seconds
Started Jul 11 07:34:45 PM PDT 24
Finished Jul 11 07:34:53 PM PDT 24
Peak memory 221076 kb
Host smart-6019dde4-0a88-4e52-bc5d-4d40fe6426a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624280027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.2624280027
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2237007189
Short name T1221
Test name
Test status
Simulation time 18930122 ps
CPU time 0.66 seconds
Started Jul 11 07:23:57 PM PDT 24
Finished Jul 11 07:24:00 PM PDT 24
Peak memory 204972 kb
Host smart-3e95ae98-ed96-47be-b0b3-02cb09c6609e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237007189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2237007189
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1296752561
Short name T963
Test name
Test status
Simulation time 145052922 ps
CPU time 2.4 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:23:44 PM PDT 24
Peak memory 213572 kb
Host smart-fef97e5f-58a1-4f5b-926c-b8fc3abcd9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296752561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1296752561
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1764082409
Short name T408
Test name
Test status
Simulation time 927373811 ps
CPU time 3.94 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:23:46 PM PDT 24
Peak memory 240124 kb
Host smart-e52fe2e0-4f35-4a51-b92b-018cd50cbab3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764082409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1764082409
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3257810427
Short name T1111
Test name
Test status
Simulation time 4063598573 ps
CPU time 69.5 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:24:52 PM PDT 24
Peak memory 622956 kb
Host smart-6ad3aa00-370c-4778-aa63-d8bd79bb3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257810427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3257810427
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2866564649
Short name T174
Test name
Test status
Simulation time 3505931159 ps
CPU time 40.8 seconds
Started Jul 11 07:23:40 PM PDT 24
Finished Jul 11 07:24:22 PM PDT 24
Peak memory 520812 kb
Host smart-5b50e8c5-f244-4bc9-adf7-90e05da4b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866564649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2866564649
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.127263500
Short name T7
Test name
Test status
Simulation time 71979076 ps
CPU time 0.92 seconds
Started Jul 11 07:23:37 PM PDT 24
Finished Jul 11 07:23:38 PM PDT 24
Peak memory 205172 kb
Host smart-37ce8125-c444-416e-9de6-c9051befbaca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127263500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.127263500
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2311726962
Short name T936
Test name
Test status
Simulation time 421490248 ps
CPU time 5.58 seconds
Started Jul 11 07:23:42 PM PDT 24
Finished Jul 11 07:23:48 PM PDT 24
Peak memory 248088 kb
Host smart-5899cf8c-2c7d-43e4-a2e1-189a8aba8b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311726962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2311726962
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1579802456
Short name T70
Test name
Test status
Simulation time 3746672615 ps
CPU time 263.2 seconds
Started Jul 11 07:23:37 PM PDT 24
Finished Jul 11 07:28:01 PM PDT 24
Peak memory 1100508 kb
Host smart-d7842388-b6e3-407b-8be0-f1d02a53ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579802456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1579802456
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3338241789
Short name T659
Test name
Test status
Simulation time 1638017804 ps
CPU time 6.78 seconds
Started Jul 11 07:23:51 PM PDT 24
Finished Jul 11 07:23:59 PM PDT 24
Peak memory 205396 kb
Host smart-020f7440-4eeb-4809-8559-413c8901fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338241789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3338241789
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.1448661287
Short name T794
Test name
Test status
Simulation time 105705289 ps
CPU time 0.7 seconds
Started Jul 11 07:23:36 PM PDT 24
Finished Jul 11 07:23:37 PM PDT 24
Peak memory 205116 kb
Host smart-e2da861b-eb11-482d-95f2-6ff9e1fee0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448661287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1448661287
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3851504504
Short name T466
Test name
Test status
Simulation time 47522893540 ps
CPU time 561.53 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:33:04 PM PDT 24
Peak memory 267752 kb
Host smart-afd59a30-c1e8-4146-ada2-89962328dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851504504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3851504504
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.468127014
Short name T468
Test name
Test status
Simulation time 2440038941 ps
CPU time 124.7 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:25:46 PM PDT 24
Peak memory 591996 kb
Host smart-db1d0419-eddf-4ce2-8c6a-77326fce85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468127014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.468127014
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3222400697
Short name T163
Test name
Test status
Simulation time 8266339720 ps
CPU time 116.14 seconds
Started Jul 11 07:23:34 PM PDT 24
Finished Jul 11 07:25:31 PM PDT 24
Peak memory 480028 kb
Host smart-2bfbb0f7-5420-4b90-833a-fab3577f2132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222400697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3222400697
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3531633322
Short name T1062
Test name
Test status
Simulation time 1116020849 ps
CPU time 26.63 seconds
Started Jul 11 07:23:42 PM PDT 24
Finished Jul 11 07:24:09 PM PDT 24
Peak memory 213560 kb
Host smart-aac3da12-dbfd-4759-a492-96527160b157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531633322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3531633322
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3566533125
Short name T665
Test name
Test status
Simulation time 3454681079 ps
CPU time 4.56 seconds
Started Jul 11 07:23:47 PM PDT 24
Finished Jul 11 07:23:53 PM PDT 24
Peak memory 213820 kb
Host smart-a54a490d-e785-476f-ab0f-95739e560541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566533125 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3566533125
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.127476846
Short name T1539
Test name
Test status
Simulation time 936203685 ps
CPU time 1.19 seconds
Started Jul 11 07:23:45 PM PDT 24
Finished Jul 11 07:23:47 PM PDT 24
Peak memory 205364 kb
Host smart-c714b483-9392-4db3-a6dc-a7a7f530411f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127476846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.127476846
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2804588615
Short name T151
Test name
Test status
Simulation time 471820911 ps
CPU time 1.08 seconds
Started Jul 11 07:23:48 PM PDT 24
Finished Jul 11 07:23:51 PM PDT 24
Peak memory 205336 kb
Host smart-85708c70-8041-4dfe-874e-7b4381102740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804588615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2804588615
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3208519285
Short name T891
Test name
Test status
Simulation time 1474071252 ps
CPU time 2.41 seconds
Started Jul 11 07:23:52 PM PDT 24
Finished Jul 11 07:23:56 PM PDT 24
Peak memory 205176 kb
Host smart-7609d927-8ebd-4c26-bd73-80d6dacb077c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208519285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3208519285
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2135815859
Short name T1201
Test name
Test status
Simulation time 863480994 ps
CPU time 1.5 seconds
Started Jul 11 07:23:51 PM PDT 24
Finished Jul 11 07:23:53 PM PDT 24
Peak memory 205416 kb
Host smart-44690c44-7993-4ef3-ba98-508e280eb3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135815859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2135815859
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3914147489
Short name T1237
Test name
Test status
Simulation time 605342300 ps
CPU time 3.74 seconds
Started Jul 11 07:23:46 PM PDT 24
Finished Jul 11 07:23:50 PM PDT 24
Peak memory 221864 kb
Host smart-96149c75-7a00-4e84-8727-fe453beba8b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914147489 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3914147489
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1562536796
Short name T1195
Test name
Test status
Simulation time 13052823832 ps
CPU time 37.6 seconds
Started Jul 11 07:23:46 PM PDT 24
Finished Jul 11 07:24:25 PM PDT 24
Peak memory 743288 kb
Host smart-7f075161-3b3b-47a1-9832-a8447ea836ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562536796 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1562536796
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.2604227103
Short name T1199
Test name
Test status
Simulation time 552281503 ps
CPU time 2.73 seconds
Started Jul 11 07:23:50 PM PDT 24
Finished Jul 11 07:23:54 PM PDT 24
Peak memory 213724 kb
Host smart-ab3b7af0-2d89-40ca-963e-7a57e1bd09ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604227103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.2604227103
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.384219459
Short name T1346
Test name
Test status
Simulation time 2436454934 ps
CPU time 2.33 seconds
Started Jul 11 07:23:56 PM PDT 24
Finished Jul 11 07:24:00 PM PDT 24
Peak memory 205548 kb
Host smart-f1691665-28e6-4bdb-90e4-0f883dcbd240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384219459 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.384219459
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.615332551
Short name T531
Test name
Test status
Simulation time 505302370 ps
CPU time 2.39 seconds
Started Jul 11 07:23:51 PM PDT 24
Finished Jul 11 07:23:54 PM PDT 24
Peak memory 205372 kb
Host smart-8ca60ede-5140-4497-afb5-a6cde45ff041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615332551 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_smbus_maxlen.615332551
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1607506025
Short name T1077
Test name
Test status
Simulation time 22653546431 ps
CPU time 39.21 seconds
Started Jul 11 07:23:40 PM PDT 24
Finished Jul 11 07:24:20 PM PDT 24
Peak memory 213740 kb
Host smart-023d1c7f-25c4-4f7e-bf5b-0aa532c3f9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607506025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1607506025
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.676144658
Short name T1173
Test name
Test status
Simulation time 2772426236 ps
CPU time 21.56 seconds
Started Jul 11 07:23:42 PM PDT 24
Finished Jul 11 07:24:04 PM PDT 24
Peak memory 222076 kb
Host smart-b06d6323-f65e-40ac-bd15-33753e0a4ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676144658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.676144658
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.415245569
Short name T673
Test name
Test status
Simulation time 53772235011 ps
CPU time 579.7 seconds
Started Jul 11 07:23:39 PM PDT 24
Finished Jul 11 07:33:20 PM PDT 24
Peak memory 4376592 kb
Host smart-d9c62e01-1269-485a-a96d-0fc33d124c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415245569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.415245569
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3172554636
Short name T395
Test name
Test status
Simulation time 1947745310 ps
CPU time 85.78 seconds
Started Jul 11 07:23:41 PM PDT 24
Finished Jul 11 07:25:08 PM PDT 24
Peak memory 617236 kb
Host smart-1908db09-ff16-4a50-8c6e-099658ed6175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172554636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3172554636
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3515797431
Short name T268
Test name
Test status
Simulation time 19737983029 ps
CPU time 6.94 seconds
Started Jul 11 07:23:47 PM PDT 24
Finished Jul 11 07:23:55 PM PDT 24
Peak memory 230100 kb
Host smart-94e71440-fa43-4096-8ace-0575a7dcd66a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515797431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3515797431
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.3151437055
Short name T580
Test name
Test status
Simulation time 117130707 ps
CPU time 2.57 seconds
Started Jul 11 07:23:52 PM PDT 24
Finished Jul 11 07:23:56 PM PDT 24
Peak memory 205236 kb
Host smart-b518873a-b010-472e-b02c-c17be48d6602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151437055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.3151437055
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3782372907
Short name T1501
Test name
Test status
Simulation time 103172081 ps
CPU time 0.61 seconds
Started Jul 11 07:24:18 PM PDT 24
Finished Jul 11 07:24:19 PM PDT 24
Peak memory 204724 kb
Host smart-a3f3b4ad-9538-4423-985e-68fe1d4b6a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782372907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3782372907
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1411529581
Short name T508
Test name
Test status
Simulation time 99606070 ps
CPU time 1.49 seconds
Started Jul 11 07:24:01 PM PDT 24
Finished Jul 11 07:24:04 PM PDT 24
Peak memory 213636 kb
Host smart-940a3c33-4800-44e8-a2ad-4643d6019b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411529581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1411529581
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2092993229
Short name T1377
Test name
Test status
Simulation time 203118826 ps
CPU time 4.32 seconds
Started Jul 11 07:23:57 PM PDT 24
Finished Jul 11 07:24:04 PM PDT 24
Peak memory 242216 kb
Host smart-e414dbce-b0cc-4093-bc4d-f3be3168fad8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092993229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2092993229
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2771214478
Short name T142
Test name
Test status
Simulation time 3026880232 ps
CPU time 96.21 seconds
Started Jul 11 07:23:58 PM PDT 24
Finished Jul 11 07:25:36 PM PDT 24
Peak memory 865432 kb
Host smart-e6fca3bc-5ad9-40ac-981c-59c91a2a86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771214478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2771214478
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1193885293
Short name T588
Test name
Test status
Simulation time 2443832743 ps
CPU time 94.14 seconds
Started Jul 11 07:23:57 PM PDT 24
Finished Jul 11 07:25:33 PM PDT 24
Peak memory 505188 kb
Host smart-fef443c6-1165-4a43-9ad0-3a02ba306b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193885293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1193885293
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2210322365
Short name T442
Test name
Test status
Simulation time 130226290 ps
CPU time 1.05 seconds
Started Jul 11 07:23:56 PM PDT 24
Finished Jul 11 07:23:59 PM PDT 24
Peak memory 205168 kb
Host smart-5a46b8e2-03a8-4d7a-9d91-257ad745b52e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210322365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2210322365
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.208528382
Short name T341
Test name
Test status
Simulation time 167146946 ps
CPU time 3.36 seconds
Started Jul 11 07:23:56 PM PDT 24
Finished Jul 11 07:24:02 PM PDT 24
Peak memory 205356 kb
Host smart-f5a0823a-adf1-4ae1-a2af-f499b6ef7c8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208528382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.208528382
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.90616905
Short name T105
Test name
Test status
Simulation time 3581332096 ps
CPU time 86.92 seconds
Started Jul 11 07:23:57 PM PDT 24
Finished Jul 11 07:25:26 PM PDT 24
Peak memory 1096164 kb
Host smart-69524d0e-f93f-49b4-85bd-1fcaab823ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90616905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.90616905
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.337755908
Short name T254
Test name
Test status
Simulation time 1336324624 ps
CPU time 7.05 seconds
Started Jul 11 07:24:14 PM PDT 24
Finished Jul 11 07:24:22 PM PDT 24
Peak memory 205400 kb
Host smart-04be8ebd-709b-48da-9405-da63ab0f247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337755908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.337755908
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_override.1526854786
Short name T331
Test name
Test status
Simulation time 17186200 ps
CPU time 0.69 seconds
Started Jul 11 07:23:56 PM PDT 24
Finished Jul 11 07:23:59 PM PDT 24
Peak memory 205184 kb
Host smart-a2e3b6b4-31d4-46d6-b675-bdcba107dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526854786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1526854786
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1996794297
Short name T34
Test name
Test status
Simulation time 7525012650 ps
CPU time 535.05 seconds
Started Jul 11 07:23:55 PM PDT 24
Finished Jul 11 07:32:52 PM PDT 24
Peak memory 1315368 kb
Host smart-0a2f080a-fe95-4b22-95ba-3dc79af81650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996794297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1996794297
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.3031943945
Short name T231
Test name
Test status
Simulation time 286305536 ps
CPU time 3.18 seconds
Started Jul 11 07:24:03 PM PDT 24
Finished Jul 11 07:24:07 PM PDT 24
Peak memory 205264 kb
Host smart-76024228-6cef-4fde-b334-df1b185af521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031943945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.3031943945
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.4274827863
Short name T1363
Test name
Test status
Simulation time 8231173441 ps
CPU time 60.58 seconds
Started Jul 11 07:23:56 PM PDT 24
Finished Jul 11 07:24:58 PM PDT 24
Peak memory 359340 kb
Host smart-efadc869-8a31-4014-af2e-e5b4b03a35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274827863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.4274827863
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3546829149
Short name T607
Test name
Test status
Simulation time 3277200171 ps
CPU time 12.57 seconds
Started Jul 11 07:24:01 PM PDT 24
Finished Jul 11 07:24:15 PM PDT 24
Peak memory 214828 kb
Host smart-d4f98fa7-9c17-4dcc-95af-66b2ea568ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546829149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3546829149
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.779504700
Short name T856
Test name
Test status
Simulation time 3077892685 ps
CPU time 3.61 seconds
Started Jul 11 07:24:07 PM PDT 24
Finished Jul 11 07:24:12 PM PDT 24
Peak memory 213852 kb
Host smart-f5ab66fd-9c45-43b0-98e3-029bed962ced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779504700 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.779504700
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2892343330
Short name T798
Test name
Test status
Simulation time 793255069 ps
CPU time 1.03 seconds
Started Jul 11 07:24:06 PM PDT 24
Finished Jul 11 07:24:08 PM PDT 24
Peak memory 205344 kb
Host smart-026da6f4-ac97-4ae2-98da-dfee27d4655a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892343330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2892343330
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.446334696
Short name T170
Test name
Test status
Simulation time 293557302 ps
CPU time 1.97 seconds
Started Jul 11 07:24:06 PM PDT 24
Finished Jul 11 07:24:09 PM PDT 24
Peak memory 210396 kb
Host smart-e31d82bc-40d5-40b3-8eb7-9b2a54f13243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446334696 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.446334696
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.4114092754
Short name T1064
Test name
Test status
Simulation time 571125684 ps
CPU time 1.8 seconds
Started Jul 11 07:24:12 PM PDT 24
Finished Jul 11 07:24:15 PM PDT 24
Peak memory 205364 kb
Host smart-441c9a4d-e977-44af-979b-27daf30c7314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114092754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.4114092754
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.3871155352
Short name T931
Test name
Test status
Simulation time 612018260 ps
CPU time 1.36 seconds
Started Jul 11 07:24:11 PM PDT 24
Finished Jul 11 07:24:13 PM PDT 24
Peak memory 205368 kb
Host smart-932c678e-184e-4bbc-b2ab-39a0111958bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871155352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.3871155352
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3573719763
Short name T1121
Test name
Test status
Simulation time 831258514 ps
CPU time 4.81 seconds
Started Jul 11 07:24:02 PM PDT 24
Finished Jul 11 07:24:07 PM PDT 24
Peak memory 221844 kb
Host smart-0dffddb5-52b4-45a4-b461-7a136d429ecf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573719763 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3573719763
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3438238091
Short name T1546
Test name
Test status
Simulation time 10438945907 ps
CPU time 9.07 seconds
Started Jul 11 07:24:03 PM PDT 24
Finished Jul 11 07:24:13 PM PDT 24
Peak memory 279972 kb
Host smart-7b97f225-e620-46ec-944f-e4e5c1296cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438238091 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3438238091
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.685402862
Short name T61
Test name
Test status
Simulation time 1967800348 ps
CPU time 2.9 seconds
Started Jul 11 07:24:12 PM PDT 24
Finished Jul 11 07:24:16 PM PDT 24
Peak memory 213684 kb
Host smart-dd93164e-dccf-49c6-8d27-0767d2021df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685402862 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_nack_acqfull.685402862
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.3536574495
Short name T1554
Test name
Test status
Simulation time 2154831042 ps
CPU time 2.96 seconds
Started Jul 11 07:24:12 PM PDT 24
Finished Jul 11 07:24:16 PM PDT 24
Peak memory 205468 kb
Host smart-0f80a58d-ea33-4ee3-a40e-1c97e452e8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536574495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.3536574495
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.1013817867
Short name T1385
Test name
Test status
Simulation time 902869810 ps
CPU time 2.35 seconds
Started Jul 11 07:24:12 PM PDT 24
Finished Jul 11 07:24:15 PM PDT 24
Peak memory 205392 kb
Host smart-509a05f7-059c-4bea-8381-985d3ef6bbf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013817867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.1013817867
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.948433599
Short name T84
Test name
Test status
Simulation time 2082447655 ps
CPU time 8.88 seconds
Started Jul 11 07:24:03 PM PDT 24
Finished Jul 11 07:24:13 PM PDT 24
Peak memory 213688 kb
Host smart-7fac0698-b3a0-4833-b345-cb1d72a0ca3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948433599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.948433599
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2766866962
Short name T773
Test name
Test status
Simulation time 2724757848 ps
CPU time 29.65 seconds
Started Jul 11 07:24:02 PM PDT 24
Finished Jul 11 07:24:33 PM PDT 24
Peak memory 213780 kb
Host smart-b14e4566-b7d4-427b-8893-bd1fa58e2cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766866962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2766866962
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1368867082
Short name T1481
Test name
Test status
Simulation time 70757326785 ps
CPU time 326.98 seconds
Started Jul 11 07:24:01 PM PDT 24
Finished Jul 11 07:29:29 PM PDT 24
Peak memory 3103832 kb
Host smart-a83af67e-448d-45e0-8e71-f8eb15af7364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368867082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1368867082
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2002253706
Short name T916
Test name
Test status
Simulation time 1404675362 ps
CPU time 4.63 seconds
Started Jul 11 07:24:03 PM PDT 24
Finished Jul 11 07:24:09 PM PDT 24
Peak memory 259824 kb
Host smart-403ea287-5123-4b1d-95c8-bf88dc71f64b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002253706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2002253706
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.1647766372
Short name T1224
Test name
Test status
Simulation time 1004041608 ps
CPU time 12.35 seconds
Started Jul 11 07:24:13 PM PDT 24
Finished Jul 11 07:24:26 PM PDT 24
Peak memory 213644 kb
Host smart-5e0a8a14-df4a-4d58-b247-3f75f7a6c1f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647766372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.1647766372
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2830183377
Short name T175
Test name
Test status
Simulation time 29337665 ps
CPU time 0.64 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:40 PM PDT 24
Peak memory 204808 kb
Host smart-4730cec6-4426-4d7d-9ccf-b6378d5bfa3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830183377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2830183377
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2644890455
Short name T1051
Test name
Test status
Simulation time 249903818 ps
CPU time 5.17 seconds
Started Jul 11 07:24:23 PM PDT 24
Finished Jul 11 07:24:29 PM PDT 24
Peak memory 253872 kb
Host smart-ea6f299d-57ee-4be2-8d5c-91aaeee9293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644890455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2644890455
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2289012178
Short name T1322
Test name
Test status
Simulation time 1597583386 ps
CPU time 8.71 seconds
Started Jul 11 07:24:25 PM PDT 24
Finished Jul 11 07:24:34 PM PDT 24
Peak memory 282144 kb
Host smart-91d734ac-30b4-4b16-9011-9f2212558258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289012178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2289012178
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2226112513
Short name T83
Test name
Test status
Simulation time 7786027964 ps
CPU time 134.79 seconds
Started Jul 11 07:24:23 PM PDT 24
Finished Jul 11 07:26:39 PM PDT 24
Peak memory 693420 kb
Host smart-622105e9-d52d-4889-95a0-124909abe8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226112513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2226112513
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.87331737
Short name T173
Test name
Test status
Simulation time 2600786931 ps
CPU time 124.81 seconds
Started Jul 11 07:24:25 PM PDT 24
Finished Jul 11 07:26:30 PM PDT 24
Peak memory 453500 kb
Host smart-c267f0ae-4ce9-464a-a5b7-7a3233cb8d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87331737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.87331737
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2722672486
Short name T1191
Test name
Test status
Simulation time 312703430 ps
CPU time 1.27 seconds
Started Jul 11 07:24:24 PM PDT 24
Finished Jul 11 07:24:26 PM PDT 24
Peak memory 205232 kb
Host smart-dd9159ac-28bd-478a-aad9-e2a9795f88f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722672486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2722672486
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.553967775
Short name T743
Test name
Test status
Simulation time 147745173 ps
CPU time 7.29 seconds
Started Jul 11 07:24:22 PM PDT 24
Finished Jul 11 07:24:30 PM PDT 24
Peak memory 205384 kb
Host smart-daa2dd8c-c28f-4d95-ab13-13ac2829ab67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553967775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.553967775
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3806183010
Short name T919
Test name
Test status
Simulation time 16969120640 ps
CPU time 107.26 seconds
Started Jul 11 07:24:23 PM PDT 24
Finished Jul 11 07:26:11 PM PDT 24
Peak memory 1263412 kb
Host smart-f5fc507c-c075-41c2-b592-9ff1fafee76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806183010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3806183010
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3632946316
Short name T1294
Test name
Test status
Simulation time 882319328 ps
CPU time 4.6 seconds
Started Jul 11 07:24:33 PM PDT 24
Finished Jul 11 07:24:40 PM PDT 24
Peak memory 205468 kb
Host smart-e6de6e73-9e1e-4d90-a526-61e899d3c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632946316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3632946316
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.238860401
Short name T1454
Test name
Test status
Simulation time 27179465 ps
CPU time 0.7 seconds
Started Jul 11 07:24:18 PM PDT 24
Finished Jul 11 07:24:19 PM PDT 24
Peak memory 205124 kb
Host smart-795b9374-054d-44a3-bbc8-46d9c2b5e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238860401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.238860401
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3290935053
Short name T1223
Test name
Test status
Simulation time 1372869843 ps
CPU time 5.87 seconds
Started Jul 11 07:24:22 PM PDT 24
Finished Jul 11 07:24:30 PM PDT 24
Peak memory 247680 kb
Host smart-1d394532-9d28-4d68-81b0-cd0365e70bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290935053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3290935053
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.30900192
Short name T1409
Test name
Test status
Simulation time 391028602 ps
CPU time 2.85 seconds
Started Jul 11 07:24:22 PM PDT 24
Finished Jul 11 07:24:26 PM PDT 24
Peak memory 205232 kb
Host smart-fc2e6e92-c1c1-4ea6-8080-80d112ff52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30900192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.30900192
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3196974532
Short name T136
Test name
Test status
Simulation time 2449612897 ps
CPU time 23.35 seconds
Started Jul 11 07:24:17 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 294760 kb
Host smart-1490d7b7-45bf-4e22-af42-2548e76fabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196974532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3196974532
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2563948238
Short name T1296
Test name
Test status
Simulation time 10657296618 ps
CPU time 8.87 seconds
Started Jul 11 07:24:25 PM PDT 24
Finished Jul 11 07:24:34 PM PDT 24
Peak memory 216548 kb
Host smart-53dd4ffd-04af-492a-86ae-31dbfc4bb2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563948238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2563948238
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2259080820
Short name T516
Test name
Test status
Simulation time 2493659213 ps
CPU time 4.22 seconds
Started Jul 11 07:24:34 PM PDT 24
Finished Jul 11 07:24:39 PM PDT 24
Peak memory 213800 kb
Host smart-78a8f547-3abf-46b3-88bd-40a9008cea76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259080820 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2259080820
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.942716735
Short name T1016
Test name
Test status
Simulation time 166207781 ps
CPU time 1.06 seconds
Started Jul 11 07:24:27 PM PDT 24
Finished Jul 11 07:24:29 PM PDT 24
Peak memory 205400 kb
Host smart-b5b541a1-d292-4051-be14-3f01f2ada8ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942716735 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.942716735
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1929085187
Short name T1464
Test name
Test status
Simulation time 133446516 ps
CPU time 1.08 seconds
Started Jul 11 07:24:28 PM PDT 24
Finished Jul 11 07:24:30 PM PDT 24
Peak memory 205484 kb
Host smart-361e22a0-300e-47f5-9517-12ef55f0d169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929085187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1929085187
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.1233650817
Short name T114
Test name
Test status
Simulation time 657542438 ps
CPU time 2.12 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 205516 kb
Host smart-f4769d9b-9e00-4844-849c-7b551d2f3451
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233650817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.1233650817
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.2470760507
Short name T1170
Test name
Test status
Simulation time 108515747 ps
CPU time 1.16 seconds
Started Jul 11 07:24:33 PM PDT 24
Finished Jul 11 07:24:36 PM PDT 24
Peak memory 205332 kb
Host smart-9c21ceb4-fa7e-45c6-8c60-b784b1c0c190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470760507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2470760507
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3645774318
Short name T702
Test name
Test status
Simulation time 2060541692 ps
CPU time 6.42 seconds
Started Jul 11 07:24:27 PM PDT 24
Finished Jul 11 07:24:34 PM PDT 24
Peak memory 221860 kb
Host smart-8e796b6f-377f-4e6d-bf8f-8611200452c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645774318 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3645774318
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3474545801
Short name T1295
Test name
Test status
Simulation time 4658980002 ps
CPU time 4.53 seconds
Started Jul 11 07:24:28 PM PDT 24
Finished Jul 11 07:24:33 PM PDT 24
Peak memory 293876 kb
Host smart-1ae35076-e193-49e3-b5c2-8a0c1d30c032
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474545801 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3474545801
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.489255487
Short name T1518
Test name
Test status
Simulation time 2366089676 ps
CPU time 2.96 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 213760 kb
Host smart-43c06918-5cde-4988-b1d6-5f8395aca840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489255487 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_nack_acqfull.489255487
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.2542564270
Short name T1373
Test name
Test status
Simulation time 2108840888 ps
CPU time 2.7 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 205488 kb
Host smart-8468b274-a218-4d4e-84c1-1585498d2a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542564270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.2542564270
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.1375687664
Short name T416
Test name
Test status
Simulation time 497076165 ps
CPU time 2.25 seconds
Started Jul 11 07:24:33 PM PDT 24
Finished Jul 11 07:24:36 PM PDT 24
Peak memory 205452 kb
Host smart-9d735884-95fa-444f-9220-c8ee1d0e45ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375687664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.1375687664
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.643698299
Short name T1259
Test name
Test status
Simulation time 662530763 ps
CPU time 8.12 seconds
Started Jul 11 07:24:28 PM PDT 24
Finished Jul 11 07:24:37 PM PDT 24
Peak memory 213616 kb
Host smart-7f4b3277-9d32-47fa-a8f0-bae895c8e091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643698299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.643698299
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.629447246
Short name T307
Test name
Test status
Simulation time 4438938385 ps
CPU time 53.59 seconds
Started Jul 11 07:24:27 PM PDT 24
Finished Jul 11 07:25:21 PM PDT 24
Peak memory 215396 kb
Host smart-9b8567f3-0d13-4726-85a5-4ca3a17bcb2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629447246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.629447246
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.15640372
Short name T361
Test name
Test status
Simulation time 10791602990 ps
CPU time 6.49 seconds
Started Jul 11 07:24:27 PM PDT 24
Finished Jul 11 07:24:34 PM PDT 24
Peak memory 205520 kb
Host smart-293e1b8a-1eeb-4036-9d25-82f0fde19f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_wr.15640372
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.4042989080
Short name T185
Test name
Test status
Simulation time 1833926433 ps
CPU time 4.98 seconds
Started Jul 11 07:24:28 PM PDT 24
Finished Jul 11 07:24:34 PM PDT 24
Peak memory 233896 kb
Host smart-393b0199-8d40-42c4-94d4-ef83b1ab939a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042989080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.4042989080
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1822083319
Short name T788
Test name
Test status
Simulation time 5395322335 ps
CPU time 6.71 seconds
Started Jul 11 07:24:33 PM PDT 24
Finished Jul 11 07:24:42 PM PDT 24
Peak memory 230108 kb
Host smart-b03d90ab-db5a-4cf0-a29e-258f968a0c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822083319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1822083319
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.3219416990
Short name T874
Test name
Test status
Simulation time 444688318 ps
CPU time 6.27 seconds
Started Jul 11 07:24:36 PM PDT 24
Finished Jul 11 07:24:44 PM PDT 24
Peak memory 213652 kb
Host smart-af8afcbc-6508-4c23-9802-a8a7777c46d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219416990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.3219416990
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3495451812
Short name T716
Test name
Test status
Simulation time 18291009 ps
CPU time 0.67 seconds
Started Jul 11 07:25:00 PM PDT 24
Finished Jul 11 07:25:02 PM PDT 24
Peak memory 204664 kb
Host smart-7a126634-d085-451a-8763-5152991f6271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495451812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3495451812
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.350409729
Short name T747
Test name
Test status
Simulation time 220412390 ps
CPU time 4.05 seconds
Started Jul 11 07:24:42 PM PDT 24
Finished Jul 11 07:24:47 PM PDT 24
Peak memory 246664 kb
Host smart-25902573-178d-416f-9138-18d67b2b69cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350409729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.350409729
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1650495323
Short name T345
Test name
Test status
Simulation time 3779770396 ps
CPU time 12.25 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:51 PM PDT 24
Peak memory 254320 kb
Host smart-8a90e12a-497b-4f59-aac4-420f19f5820e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650495323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1650495323
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2204028761
Short name T1034
Test name
Test status
Simulation time 10583318816 ps
CPU time 173.06 seconds
Started Jul 11 07:24:43 PM PDT 24
Finished Jul 11 07:27:37 PM PDT 24
Peak memory 723920 kb
Host smart-23db1174-c2be-4fb8-91f2-73284adddef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204028761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2204028761
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.18004551
Short name T1183
Test name
Test status
Simulation time 1887121458 ps
CPU time 42.81 seconds
Started Jul 11 07:24:44 PM PDT 24
Finished Jul 11 07:25:28 PM PDT 24
Peak memory 568712 kb
Host smart-96320079-376e-4716-b791-b1e08a6480e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18004551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.18004551
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2930883762
Short name T520
Test name
Test status
Simulation time 1360906591 ps
CPU time 1.19 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:40 PM PDT 24
Peak memory 205192 kb
Host smart-d2c8cc2c-d8be-4120-85ea-9bb1f6eb1b79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930883762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2930883762
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2352696837
Short name T333
Test name
Test status
Simulation time 533355067 ps
CPU time 3.69 seconds
Started Jul 11 07:24:36 PM PDT 24
Finished Jul 11 07:24:41 PM PDT 24
Peak memory 227984 kb
Host smart-24e72438-2a78-4808-8f01-56e865832a61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352696837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2352696837
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2244400489
Short name T844
Test name
Test status
Simulation time 4068448198 ps
CPU time 259.52 seconds
Started Jul 11 07:24:39 PM PDT 24
Finished Jul 11 07:29:00 PM PDT 24
Peak memory 1102648 kb
Host smart-9c83c88c-9635-4d70-8190-09931b7d7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244400489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2244400489
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2429700037
Short name T842
Test name
Test status
Simulation time 1029345233 ps
CPU time 5.83 seconds
Started Jul 11 07:24:55 PM PDT 24
Finished Jul 11 07:25:03 PM PDT 24
Peak memory 205332 kb
Host smart-9cd0a329-c7e4-4400-a7e2-7458de826d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429700037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2429700037
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.3660212997
Short name T1143
Test name
Test status
Simulation time 17005649 ps
CPU time 0.68 seconds
Started Jul 11 07:24:38 PM PDT 24
Finished Jul 11 07:24:40 PM PDT 24
Peak memory 205144 kb
Host smart-1eb6df0b-6794-444d-9f7f-0ca1b77f0e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660212997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3660212997
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1286807292
Short name T483
Test name
Test status
Simulation time 5960591661 ps
CPU time 70.51 seconds
Started Jul 11 07:24:46 PM PDT 24
Finished Jul 11 07:25:58 PM PDT 24
Peak memory 400468 kb
Host smart-3e582af0-8dad-405a-9716-1b4d9c4c8125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286807292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1286807292
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.3852370111
Short name T357
Test name
Test status
Simulation time 757070628 ps
CPU time 7.88 seconds
Started Jul 11 07:24:43 PM PDT 24
Finished Jul 11 07:24:51 PM PDT 24
Peak memory 205216 kb
Host smart-1b2a8ece-430e-4d13-b4d0-a33dd50aa290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852370111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.3852370111
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2999924072
Short name T1429
Test name
Test status
Simulation time 2344090395 ps
CPU time 20.76 seconds
Started Jul 11 07:24:37 PM PDT 24
Finished Jul 11 07:24:58 PM PDT 24
Peak memory 328684 kb
Host smart-998d0d49-f7ab-4f30-bb9f-c5a381d36618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999924072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2999924072
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.237990614
Short name T778
Test name
Test status
Simulation time 14742600197 ps
CPU time 41.18 seconds
Started Jul 11 07:24:48 PM PDT 24
Finished Jul 11 07:25:30 PM PDT 24
Peak memory 213636 kb
Host smart-9e3af4f7-612a-4c27-af2e-fd60a959d170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237990614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.237990614
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3691919477
Short name T825
Test name
Test status
Simulation time 996642141 ps
CPU time 5.21 seconds
Started Jul 11 07:24:49 PM PDT 24
Finished Jul 11 07:24:55 PM PDT 24
Peak memory 213692 kb
Host smart-26c76306-3cc4-40b1-97c8-d71b3b5bb4e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691919477 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3691919477
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1218919399
Short name T480
Test name
Test status
Simulation time 235987431 ps
CPU time 1.4 seconds
Started Jul 11 07:24:48 PM PDT 24
Finished Jul 11 07:24:50 PM PDT 24
Peak memory 205476 kb
Host smart-d925cbba-f3da-4599-8cce-66e43c6bf147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218919399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1218919399
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2721999192
Short name T1542
Test name
Test status
Simulation time 216154546 ps
CPU time 1.01 seconds
Started Jul 11 07:24:49 PM PDT 24
Finished Jul 11 07:24:51 PM PDT 24
Peak memory 205364 kb
Host smart-415dd2ad-b4f2-4ccd-bc4a-a91417501700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721999192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2721999192
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.1596627015
Short name T1349
Test name
Test status
Simulation time 411133259 ps
CPU time 2.28 seconds
Started Jul 11 07:24:54 PM PDT 24
Finished Jul 11 07:24:58 PM PDT 24
Peak memory 205464 kb
Host smart-ccffb30c-f31b-42dd-90d8-1edbc6cd6ceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596627015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.1596627015
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.145582700
Short name T1310
Test name
Test status
Simulation time 569088832 ps
CPU time 1.18 seconds
Started Jul 11 07:25:00 PM PDT 24
Finished Jul 11 07:25:03 PM PDT 24
Peak memory 205376 kb
Host smart-379cae13-d150-4c50-b615-95f4605a721a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145582700 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.145582700
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.458910316
Short name T491
Test name
Test status
Simulation time 2902314150 ps
CPU time 4.48 seconds
Started Jul 11 07:24:49 PM PDT 24
Finished Jul 11 07:24:54 PM PDT 24
Peak memory 221824 kb
Host smart-0e8171c8-70a8-49b0-9a93-e06f7987552a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458910316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.458910316
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3202880053
Short name T1105
Test name
Test status
Simulation time 20097360505 ps
CPU time 397.37 seconds
Started Jul 11 07:24:50 PM PDT 24
Finished Jul 11 07:31:29 PM PDT 24
Peak memory 3525548 kb
Host smart-9a2281a3-4250-47c3-81a4-d247b6008a82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202880053 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3202880053
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.1931539147
Short name T365
Test name
Test status
Simulation time 2158284574 ps
CPU time 2.92 seconds
Started Jul 11 07:25:00 PM PDT 24
Finished Jul 11 07:25:05 PM PDT 24
Peak memory 213748 kb
Host smart-d44d16c2-5521-458b-808d-f377a26c1814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931539147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.1931539147
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.839890237
Short name T1235
Test name
Test status
Simulation time 5065255839 ps
CPU time 2.45 seconds
Started Jul 11 07:24:59 PM PDT 24
Finished Jul 11 07:25:03 PM PDT 24
Peak memory 205524 kb
Host smart-5b8a70b9-30d1-4f2c-97af-cbce1aae64bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839890237 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.839890237
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.4136796257
Short name T727
Test name
Test status
Simulation time 1549541062 ps
CPU time 1.93 seconds
Started Jul 11 07:24:55 PM PDT 24
Finished Jul 11 07:24:59 PM PDT 24
Peak memory 205444 kb
Host smart-75124713-916e-4253-8cde-6cb009e4da44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136796257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.4136796257
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3064823605
Short name T463
Test name
Test status
Simulation time 3745463536 ps
CPU time 14.21 seconds
Started Jul 11 07:24:46 PM PDT 24
Finished Jul 11 07:25:02 PM PDT 24
Peak memory 213716 kb
Host smart-5bddbfb9-8360-4782-a776-45674c42b980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064823605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3064823605
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2395075912
Short name T214
Test name
Test status
Simulation time 2353856974 ps
CPU time 23.92 seconds
Started Jul 11 07:24:50 PM PDT 24
Finished Jul 11 07:25:16 PM PDT 24
Peak memory 213800 kb
Host smart-f1d46fad-1e0e-408d-bdec-8007f549b79f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395075912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2395075912
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.668724457
Short name T1424
Test name
Test status
Simulation time 19779770061 ps
CPU time 20.45 seconds
Started Jul 11 07:24:49 PM PDT 24
Finished Jul 11 07:25:10 PM PDT 24
Peak memory 205500 kb
Host smart-5ecb62bf-3273-4faf-b5d5-ec9aec80c302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668724457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.668724457
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3023770304
Short name T523
Test name
Test status
Simulation time 1591876022 ps
CPU time 3.98 seconds
Started Jul 11 07:24:48 PM PDT 24
Finished Jul 11 07:24:52 PM PDT 24
Peak memory 314152 kb
Host smart-ccfcfc10-287e-4201-ab3e-a022e5aedf41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023770304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3023770304
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1378157823
Short name T1205
Test name
Test status
Simulation time 5516128181 ps
CPU time 7.4 seconds
Started Jul 11 07:24:50 PM PDT 24
Finished Jul 11 07:24:59 PM PDT 24
Peak memory 221896 kb
Host smart-710e2a16-2e49-48e8-8678-66da9f95ad8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378157823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1378157823
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.843928109
Short name T1564
Test name
Test status
Simulation time 183753873 ps
CPU time 3.69 seconds
Started Jul 11 07:24:54 PM PDT 24
Finished Jul 11 07:24:59 PM PDT 24
Peak memory 205456 kb
Host smart-3c785993-fb38-4efa-a395-ec24b934e357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843928109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.843928109
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3826698503
Short name T351
Test name
Test status
Simulation time 37557642 ps
CPU time 0.63 seconds
Started Jul 11 07:25:20 PM PDT 24
Finished Jul 11 07:25:22 PM PDT 24
Peak memory 204732 kb
Host smart-28410e87-27f8-432f-ada7-d6eb6b591ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826698503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3826698503
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1673400848
Short name T662
Test name
Test status
Simulation time 207961030 ps
CPU time 8.19 seconds
Started Jul 11 07:25:06 PM PDT 24
Finished Jul 11 07:25:15 PM PDT 24
Peak memory 213592 kb
Host smart-9c35cde8-fa6d-4e68-896d-9ec9345dd37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673400848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1673400848
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2164120524
Short name T1278
Test name
Test status
Simulation time 1353731795 ps
CPU time 7.47 seconds
Started Jul 11 07:25:09 PM PDT 24
Finished Jul 11 07:25:17 PM PDT 24
Peak memory 272260 kb
Host smart-13536607-64e6-465f-b2a0-3063fde34dc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164120524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2164120524
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1683791721
Short name T1537
Test name
Test status
Simulation time 1530809140 ps
CPU time 54.63 seconds
Started Jul 11 07:25:06 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 571576 kb
Host smart-043dba71-12b9-41cc-a0ea-9d2ad6dfed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683791721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1683791721
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1189249789
Short name T858
Test name
Test status
Simulation time 11477764640 ps
CPU time 59.1 seconds
Started Jul 11 07:25:05 PM PDT 24
Finished Jul 11 07:26:06 PM PDT 24
Peak memory 622000 kb
Host smart-68a54727-584e-4136-b885-d56ec3f2eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189249789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1189249789
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2193293211
Short name T599
Test name
Test status
Simulation time 123752182 ps
CPU time 1.12 seconds
Started Jul 11 07:25:09 PM PDT 24
Finished Jul 11 07:25:11 PM PDT 24
Peak memory 205156 kb
Host smart-b0715fa5-058e-438b-9b9d-5b81c0caf63d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193293211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2193293211
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1880755528
Short name T614
Test name
Test status
Simulation time 1059304469 ps
CPU time 8.72 seconds
Started Jul 11 07:25:04 PM PDT 24
Finished Jul 11 07:25:14 PM PDT 24
Peak memory 228944 kb
Host smart-d9696517-8ea6-4c09-b2eb-112fcc04b2a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880755528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1880755528
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1260543110
Short name T462
Test name
Test status
Simulation time 2725881027 ps
CPU time 160.5 seconds
Started Jul 11 07:25:05 PM PDT 24
Finished Jul 11 07:27:47 PM PDT 24
Peak memory 763792 kb
Host smart-48a2c7e6-41df-4942-8407-6a9aa345113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260543110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1260543110
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.94320658
Short name T248
Test name
Test status
Simulation time 236943816 ps
CPU time 9.39 seconds
Started Jul 11 07:25:21 PM PDT 24
Finished Jul 11 07:25:33 PM PDT 24
Peak memory 205296 kb
Host smart-1bd3f94b-329b-4cad-8914-2ab2828548c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94320658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.94320658
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.1793412736
Short name T325
Test name
Test status
Simulation time 25643932 ps
CPU time 0.69 seconds
Started Jul 11 07:25:00 PM PDT 24
Finished Jul 11 07:25:02 PM PDT 24
Peak memory 205124 kb
Host smart-51452298-6271-4315-99d2-6706c7e1ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793412736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1793412736
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2962895435
Short name T15
Test name
Test status
Simulation time 12221752532 ps
CPU time 179.44 seconds
Started Jul 11 07:25:07 PM PDT 24
Finished Jul 11 07:28:08 PM PDT 24
Peak memory 205424 kb
Host smart-9b929b26-fd7d-4c5a-a1b6-7f6e4a1d6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962895435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2962895435
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.383977327
Short name T6
Test name
Test status
Simulation time 313237059 ps
CPU time 3.83 seconds
Started Jul 11 07:25:05 PM PDT 24
Finished Jul 11 07:25:10 PM PDT 24
Peak memory 205228 kb
Host smart-3164d5d3-24b2-48a3-bf3b-57dc1589175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383977327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.383977327
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1709234634
Short name T1498
Test name
Test status
Simulation time 1520623025 ps
CPU time 12.32 seconds
Started Jul 11 07:24:59 PM PDT 24
Finished Jul 11 07:25:12 PM PDT 24
Peak memory 262272 kb
Host smart-491cc4ac-2729-4a9d-9920-a4296aa100ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709234634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1709234634
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.507754610
Short name T115
Test name
Test status
Simulation time 34950976696 ps
CPU time 250.11 seconds
Started Jul 11 07:25:05 PM PDT 24
Finished Jul 11 07:29:16 PM PDT 24
Peak memory 1406716 kb
Host smart-0b0ea65f-52be-4f4c-872b-00c7a8c2c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507754610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.507754610
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1858396115
Short name T317
Test name
Test status
Simulation time 9155811538 ps
CPU time 18.67 seconds
Started Jul 11 07:25:07 PM PDT 24
Finished Jul 11 07:25:26 PM PDT 24
Peak memory 230004 kb
Host smart-af187e84-96c3-4cac-804a-dbd2a78239f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858396115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1858396115
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1092573902
Short name T1001
Test name
Test status
Simulation time 6485615179 ps
CPU time 8.03 seconds
Started Jul 11 07:25:26 PM PDT 24
Finished Jul 11 07:25:35 PM PDT 24
Peak memory 220464 kb
Host smart-fa09672d-1de7-41cd-890a-3cf45c90a11d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092573902 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1092573902
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2981031469
Short name T752
Test name
Test status
Simulation time 256757376 ps
CPU time 0.82 seconds
Started Jul 11 07:25:11 PM PDT 24
Finished Jul 11 07:25:13 PM PDT 24
Peak memory 205368 kb
Host smart-2fb749f0-396f-4fe0-99ab-741092905536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981031469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2981031469
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3756428834
Short name T595
Test name
Test status
Simulation time 354698259 ps
CPU time 1.42 seconds
Started Jul 11 07:25:12 PM PDT 24
Finished Jul 11 07:25:15 PM PDT 24
Peak memory 205436 kb
Host smart-c947ed2f-621f-4677-a27b-a60ada155f11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756428834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3756428834
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.4232544333
Short name T283
Test name
Test status
Simulation time 701940655 ps
CPU time 1.33 seconds
Started Jul 11 07:25:18 PM PDT 24
Finished Jul 11 07:25:20 PM PDT 24
Peak memory 205324 kb
Host smart-cc711afc-17a2-44a0-a88e-14eea144bb57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232544333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.4232544333
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.2342912191
Short name T293
Test name
Test status
Simulation time 116580479 ps
CPU time 1.12 seconds
Started Jul 11 07:25:21 PM PDT 24
Finished Jul 11 07:25:25 PM PDT 24
Peak memory 205336 kb
Host smart-3d49d490-aaef-4da0-9d51-bf2da26757fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342912191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.2342912191
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2679789056
Short name T1317
Test name
Test status
Simulation time 896464098 ps
CPU time 5.81 seconds
Started Jul 11 07:25:12 PM PDT 24
Finished Jul 11 07:25:19 PM PDT 24
Peak memory 217712 kb
Host smart-ae3b0e50-a1a2-42c7-93f3-ceeee10efcfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679789056 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2679789056
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1309410883
Short name T452
Test name
Test status
Simulation time 19782432821 ps
CPU time 49.87 seconds
Started Jul 11 07:25:11 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 854080 kb
Host smart-1e6c3606-a64c-4258-a07f-fe82b51e34be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309410883 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1309410883
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.3435145380
Short name T1059
Test name
Test status
Simulation time 513817676 ps
CPU time 2.94 seconds
Started Jul 11 07:25:20 PM PDT 24
Finished Jul 11 07:25:25 PM PDT 24
Peak memory 213688 kb
Host smart-ebf84e21-518d-484c-a15e-4290da869983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435145380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.3435145380
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.3402927517
Short name T958
Test name
Test status
Simulation time 2568037962 ps
CPU time 2.63 seconds
Started Jul 11 07:25:20 PM PDT 24
Finished Jul 11 07:25:25 PM PDT 24
Peak memory 205528 kb
Host smart-6f8a8da7-4562-465a-bd0b-9f75290aaf45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402927517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3402927517
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.2929353321
Short name T1030
Test name
Test status
Simulation time 837404709 ps
CPU time 2.08 seconds
Started Jul 11 07:25:23 PM PDT 24
Finished Jul 11 07:25:26 PM PDT 24
Peak memory 205360 kb
Host smart-a7968da8-4080-4ff8-b2bd-f1c19835f3cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929353321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.2929353321
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2881867113
Short name T572
Test name
Test status
Simulation time 824885865 ps
CPU time 12.45 seconds
Started Jul 11 07:25:06 PM PDT 24
Finished Jul 11 07:25:20 PM PDT 24
Peak memory 213696 kb
Host smart-6f7d15dc-96ad-4f1e-a661-c229f16150e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881867113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2881867113
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.3433022722
Short name T362
Test name
Test status
Simulation time 11661843525 ps
CPU time 54.06 seconds
Started Jul 11 07:25:06 PM PDT 24
Finished Jul 11 07:26:02 PM PDT 24
Peak memory 219892 kb
Host smart-d01248de-8528-4ce1-a1ef-ba12aa13c605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433022722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.3433022722
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1162701027
Short name T269
Test name
Test status
Simulation time 32007489969 ps
CPU time 253.22 seconds
Started Jul 11 07:25:05 PM PDT 24
Finished Jul 11 07:29:20 PM PDT 24
Peak memory 3014752 kb
Host smart-29814a85-9bc4-4a42-b972-6aac3766db4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162701027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1162701027
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.791339499
Short name T396
Test name
Test status
Simulation time 216504678 ps
CPU time 1.38 seconds
Started Jul 11 07:25:10 PM PDT 24
Finished Jul 11 07:25:12 PM PDT 24
Peak memory 205524 kb
Host smart-37876eb4-b2ee-4a7c-949b-2e7849b7ee9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791339499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.791339499
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.292946720
Short name T1565
Test name
Test status
Simulation time 4988002790 ps
CPU time 7.19 seconds
Started Jul 11 07:25:11 PM PDT 24
Finished Jul 11 07:25:19 PM PDT 24
Peak memory 221844 kb
Host smart-1fcb61ea-4293-4a73-a842-e9b88bc6ee58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292946720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.292946720
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.1328762115
Short name T948
Test name
Test status
Simulation time 96975227 ps
CPU time 1.87 seconds
Started Jul 11 07:25:18 PM PDT 24
Finished Jul 11 07:25:21 PM PDT 24
Peak memory 205456 kb
Host smart-420eda7d-2f67-4a04-90e7-9d705c806777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328762115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.1328762115
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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