Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	706288	1			T1	2		T2	3		T3	2
all_values[1]	706288	1			T1	2		T2	3		T3	2
all_values[2]	706288	1			T1	2		T2	3		T3	2
all_values[3]	706288	1			T1	2		T2	3		T3	2
all_values[4]	706288	1			T1	2		T2	3		T3	2
all_values[5]	706288	1			T1	2		T2	3		T3	2
all_values[6]	706288	1			T1	2		T2	3		T3	2
all_values[7]	706288	1			T1	2		T2	3		T3	2
all_values[8]	706288	1			T1	2		T2	3		T3	2
all_values[9]	706288	1			T1	2		T2	3		T3	2
all_values[10]	706288	1			T1	2		T2	3		T3	2
all_values[11]	706288	1			T1	2		T2	3		T3	2
all_values[12]	706288	1			T1	2		T2	3		T3	2
all_values[13]	706288	1			T1	2		T2	3		T3	2
all_values[14]	706288	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8675193

1

T1

26

T2

39

T3

26

auto[1]

1919127

1

T1

4

T2

6

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9428169

1

T1

30

T2

45

T3

30

auto[1]

1166151

1

T24

14487

T132

80615

T162

179706

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	71366	1			T2	1		T9	1		T11	2
all_values[0]	auto[0]	auto[1]	5957	1			T24	94		T132	339		T162	784
all_values[0]	auto[1]	auto[0]	552603	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	76362	1			T24	891		T132	5035		T162	12053
all_values[1]	auto[0]	auto[0]	658943	1			T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	46843	1			T24	977		T132	5372		T162	12821
all_values[1]	auto[1]	auto[0]	282	1			T13	11		T21	6		T155	13
all_values[1]	auto[1]	auto[1]	220	1			T24	8		T132	2		T162	16
all_values[2]	auto[0]	auto[0]	623768	1			T1	2		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	82175	1			T24	976		T132	5373		T162	12835
all_values[2]	auto[1]	auto[0]	194	1			T159	2		T50	1		T174	1
all_values[2]	auto[1]	auto[1]	151	1			T24	7		T132	1		T162	2
all_values[3]	auto[0]	auto[0]	623954	1			T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	82125	1			T24	972		T132	5373		T162	12835
all_values[3]	auto[1]	auto[1]	209	1			T24	12		T132	1		T241	2
all_values[4]	auto[0]	auto[0]	623927	1			T1	2		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	82182	1			T24	979		T132	5373		T162	12833
all_values[4]	auto[1]	auto[0]	10	1			T28	1		T276	1		T277	1
all_values[4]	auto[1]	auto[1]	169	1			T24	6		T132	2		T162	4
all_values[5]	auto[0]	auto[0]	623936	1			T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	82142	1			T24	974		T132	5374		T162	12834
all_values[5]	auto[1]	auto[1]	210	1			T24	9		T162	3		T241	8
all_values[6]	auto[0]	auto[0]	624249	1			T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	81870	1			T24	705		T132	5371		T162	12830
all_values[6]	auto[1]	auto[1]	169	1			T24	4		T132	2		T162	6
all_values[7]	auto[0]	auto[0]	605036	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	80412	1			T24	855		T132	5210		T162	12674
all_values[7]	auto[1]	auto[0]	18927	1			T2	1		T9	1		T12	1
all_values[7]	auto[1]	auto[1]	1913	1			T24	129		T132	164		T162	158
all_values[8]	auto[0]	auto[0]	623950	1			T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	82166	1			T24	976		T132	5374		T162	12830
all_values[8]	auto[1]	auto[1]	172	1			T24	7		T132	1		T162	6
all_values[9]	auto[0]	auto[0]	126546	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	16639	1			T24	928		T132	76		T162	1515
all_values[9]	auto[1]	auto[0]	512204	1			T2	1		T9	1		T12	1
all_values[9]	auto[1]	auto[1]	50899	1			T24	57		T132	5299		T162	11322
all_values[10]	auto[0]	auto[0]	629588	1			T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	76545	1			T24	978		T132	5373		T162	12833
all_values[10]	auto[1]	auto[1]	155	1			T24	7		T132	2		T162	3
all_values[11]	auto[0]	auto[0]	2278	1			T2	1		T9	1		T11	2
all_values[11]	auto[0]	auto[1]	311	1			T24	28		T132	9		T241	8
all_values[11]	auto[1]	auto[0]	634548	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	69151	1			T24	957		T132	5366		T241	2589
all_values[12]	auto[0]	auto[0]	623896	1			T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	82182	1			T24	975		T132	5373		T162	12834
all_values[12]	auto[1]	auto[0]	60	1			T50	1		T68	1		T154	1
all_values[12]	auto[1]	auto[1]	150	1			T24	9		T132	2		T162	2
all_values[13]	auto[0]	auto[0]	623950	1			T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	82162	1			T24	975		T132	5371		T162	12831
all_values[13]	auto[1]	auto[1]	176	1			T24	8		T132	4		T162	6
all_values[14]	auto[0]	auto[0]	623954	1			T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	82141	1			T24	975		T132	5371		T162	12835
all_values[14]	auto[1]	auto[1]	193	1			T24	9		T132	2		T162	1