Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	706288	1			T1	2		T2	3		T3	2
all_pins[1]	706288	1			T1	2		T2	3		T3	2
all_pins[2]	706288	1			T1	2		T2	3		T3	2
all_pins[3]	706288	1			T1	2		T2	3		T3	2
all_pins[4]	706288	1			T1	2		T2	3		T3	2
all_pins[5]	706288	1			T1	2		T2	3		T3	2
all_pins[6]	706288	1			T1	2		T2	3		T3	2
all_pins[7]	706288	1			T1	2		T2	3		T3	2
all_pins[8]	706288	1			T1	2		T2	3		T3	2
all_pins[9]	706288	1			T1	2		T2	3		T3	2
all_pins[10]	706288	1			T1	2		T2	3		T3	2
all_pins[11]	706288	1			T1	2		T2	3		T3	2
all_pins[12]	706288	1			T1	2		T2	3		T3	2
all_pins[13]	706288	1			T1	2		T2	3		T3	2
all_pins[14]	706288	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8681609	1			T1	26		T2	39		T3	26
values[0x1]	1912711	1			T1	4		T2	6		T3	4
transitions[0x0=>0x1]	1911988	1			T1	4		T2	6		T3	4
transitions[0x1=>0x0]	1910855	1			T1	3		T2	5		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80739	1			T2	1		T9	1		T11	2
all_pins[0]	values[0x1]	625549	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	625142	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	76	1			T21	7		T24	1		T241	1
all_pins[1]	values[0x0]	705805	1			T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	483	1			T13	13		T21	7		T155	17
all_pins[1]	transitions[0x0=>0x1]	465	1			T13	13		T21	7		T155	17
all_pins[1]	transitions[0x1=>0x0]	105	1			T174	1		T154	1		T24	3
all_pins[2]	values[0x0]	706165	1			T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	123	1			T174	1		T154	1		T24	3
all_pins[2]	transitions[0x0=>0x1]	103	1			T174	1		T154	1		T24	1
all_pins[2]	transitions[0x1=>0x0]	81	1			T24	4		T132	1		T242	3
all_pins[3]	values[0x0]	706187	1			T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	101	1			T24	6		T132	1		T242	4
all_pins[3]	transitions[0x0=>0x1]	80	1			T24	5		T242	4		T35	3
all_pins[3]	transitions[0x1=>0x0]	70	1			T24	3		T28	1		T276	1
all_pins[4]	values[0x0]	706197	1			T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	91	1			T24	4		T28	1		T276	1
all_pins[4]	transitions[0x0=>0x1]	70	1			T24	3		T28	1		T276	1
all_pins[4]	transitions[0x1=>0x0]	80	1			T24	6		T162	1		T241	2
all_pins[5]	values[0x0]	706187	1			T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	101	1			T24	7		T162	2		T241	4
all_pins[5]	transitions[0x0=>0x1]	75	1			T24	6		T162	2		T241	4
all_pins[5]	transitions[0x1=>0x0]	71	1			T132	2		T162	2		T241	2
all_pins[6]	values[0x0]	706191	1			T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	97	1			T24	1		T132	2		T162	2
all_pins[6]	transitions[0x0=>0x1]	75	1			T132	2		T162	2		T241	2
all_pins[6]	transitions[0x1=>0x0]	22839	1			T2	1		T9	1		T12	1
all_pins[7]	values[0x0]	683427	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	22861	1			T2	1		T9	1		T12	1
all_pins[7]	transitions[0x0=>0x1]	22839	1			T2	1		T9	1		T12	1
all_pins[7]	transitions[0x1=>0x0]	52	1			T24	1		T162	2		T241	3
all_pins[8]	values[0x0]	706214	1			T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	74	1			T24	2		T162	2		T241	3
all_pins[8]	transitions[0x0=>0x1]	53	1			T24	2		T162	1		T241	3
all_pins[8]	transitions[0x1=>0x0]	563017	1			T2	1		T9	1		T12	1
all_pins[9]	values[0x0]	143250	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	563038	1			T2	1		T9	1		T12	1
all_pins[9]	transitions[0x0=>0x1]	563019	1			T2	1		T9	1		T12	1
all_pins[9]	transitions[0x1=>0x0]	58	1			T24	4		T132	1		T162	1
all_pins[10]	values[0x0]	706211	1			T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	77	1			T24	5		T132	1		T162	1
all_pins[10]	transitions[0x0=>0x1]	54	1			T24	4		T162	1		T241	2
all_pins[10]	transitions[0x1=>0x0]	699775	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6490	1			T2	1		T9	1		T11	2
all_pins[11]	values[0x1]	699798	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	699766	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	108	1			T50	1		T68	1		T69	1
all_pins[12]	values[0x0]	706148	1			T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	140	1			T50	1		T68	1		T154	1
all_pins[12]	transitions[0x0=>0x1]	125	1			T50	1		T68	1		T154	1
all_pins[12]	transitions[0x1=>0x0]	67	1			T24	2		T132	2		T162	1
all_pins[13]	values[0x0]	706206	1			T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	82	1			T24	4		T132	3		T162	1
all_pins[13]	transitions[0x0=>0x1]	60	1			T24	4		T132	3		T162	1
all_pins[13]	transitions[0x1=>0x0]	74	1			T24	2		T241	5		T242	3
all_pins[14]	values[0x0]	706192	1			T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	96	1			T24	2		T241	5		T242	3
all_pins[14]	transitions[0x0=>0x1]	62	1			T24	1		T241	4		T242	3
all_pins[14]	transitions[0x1=>0x0]	624382	1			T1	1		T2	1		T3	1