Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	398	1			T24	15		T132	4		T162	7
all_values[1]	398	1			T24	15		T132	4		T162	7
all_values[2]	398	1			T24	15		T132	4		T162	7
all_values[3]	398	1			T24	15		T132	4		T162	7
all_values[4]	398	1			T24	15		T132	4		T162	7
all_values[5]	398	1			T24	15		T132	4		T162	7
all_values[6]	398	1			T24	15		T132	4		T162	7
all_values[7]	398	1			T24	15		T132	4		T162	7
all_values[8]	398	1			T24	15		T132	4		T162	7
all_values[9]	398	1			T24	15		T132	4		T162	7
all_values[10]	398	1			T24	15		T132	4		T162	7
all_values[11]	398	1			T24	15		T132	4		T162	7
all_values[12]	398	1			T24	15		T132	4		T162	7
all_values[13]	398	1			T24	15		T132	4		T162	7
all_values[14]	398	1			T24	15		T132	4		T162	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3285

1

T24

122

T132

36

T162

51

auto[1]

2685

1

T24

103

T132

24

T162

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T24

19

T132

10

T162

19

auto[1]

4954

1

T24

206

T132

50

T162

86

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3569

1

T24

129

T132

35

T162

71

auto[1]

2401

1

T24

96

T132

25

T162

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	49	1			T242	1		T35	1		T285	1
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T24	2		T132	1		T241	3
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T132	1		T242	1		T285	3
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T24	6		T162	4		T241	4
all_values[0]	auto[1]	auto[0]	auto[1]	81	1			T24	3		T162	3		T241	3
all_values[0]	auto[1]	auto[1]	auto[1]	66	1			T24	4		T132	2		T241	2
all_values[1]	auto[0]	auto[0]	auto[0]	36	1			T132	1		T241	3		T35	3
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T24	6		T132	1		T162	2
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T241	1		T35	1		T286	3
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T24	3		T162	2		T241	4
all_values[1]	auto[1]	auto[0]	auto[1]	88	1			T24	4		T132	1		T162	2
all_values[1]	auto[1]	auto[1]	auto[1]	82	1			T24	2		T132	1		T162	1
all_values[2]	auto[0]	auto[0]	auto[0]	55	1			T24	2		T132	1		T241	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T24	3		T132	2		T162	3
all_values[2]	auto[0]	auto[1]	auto[0]	17	1			T133	1		T287	4		T288	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T24	3		T162	2		T241	2
all_values[2]	auto[1]	auto[0]	auto[1]	86	1			T24	5		T132	1		T162	1
all_values[2]	auto[1]	auto[1]	auto[1]	65	1			T24	2		T162	1		T241	1
all_values[3]	auto[0]	auto[0]	auto[0]	46	1			T24	1		T162	2		T35	1
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T24	3		T162	3		T241	3
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T132	1		T289	1		T286	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T24	3		T132	1		T162	1
all_values[3]	auto[1]	auto[0]	auto[1]	90	1			T24	4		T241	1		T242	3
all_values[3]	auto[1]	auto[1]	auto[1]	75	1			T24	4		T132	2		T162	1
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T35	1		T285	1		T286	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T24	2		T162	1		T241	4
all_values[4]	auto[0]	auto[1]	auto[0]	18	1			T285	1		T273	2		T290	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T24	7		T132	2		T162	2
all_values[4]	auto[1]	auto[0]	auto[1]	98	1			T24	5		T162	1		T241	1
all_values[4]	auto[1]	auto[1]	auto[1]	71	1			T24	1		T132	2		T162	3
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T241	1		T242	3		T289	2
all_values[5]	auto[0]	auto[0]	auto[1]	93	1			T24	1		T132	2		T162	3
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T24	2		T132	1		T242	1
all_values[5]	auto[0]	auto[1]	auto[1]	73	1			T24	4		T162	2		T241	2
all_values[5]	auto[1]	auto[0]	auto[1]	90	1			T24	5		T162	1		T241	1
all_values[5]	auto[1]	auto[1]	auto[1]	90	1			T24	3		T132	1		T162	1
all_values[6]	auto[0]	auto[0]	auto[0]	73	1			T24	4		T132	2		T162	1
all_values[6]	auto[0]	auto[0]	auto[1]	66	1			T24	2		T162	2		T241	1
all_values[6]	auto[0]	auto[1]	auto[0]	20	1			T24	3		T289	1		T291	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T24	1		T132	1		T162	1
all_values[6]	auto[1]	auto[0]	auto[1]	77	1			T24	5		T132	1		T162	2
all_values[6]	auto[1]	auto[1]	auto[1]	77	1			T162	1		T241	1		T242	1
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T132	1		T35	1		T289	2
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T24	4		T132	1		T241	5
all_values[7]	auto[0]	auto[1]	auto[0]	33	1			T24	1		T162	5		T285	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T24	4		T162	1		T241	1
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T24	2		T132	2		T241	5
all_values[7]	auto[1]	auto[1]	auto[1]	68	1			T24	4		T162	1		T241	1
all_values[8]	auto[0]	auto[0]	auto[0]	46	1			T162	1		T242	1		T35	1
all_values[8]	auto[0]	auto[0]	auto[1]	103	1			T24	4		T132	3		T162	3
all_values[8]	auto[0]	auto[1]	auto[0]	18	1			T24	2		T242	1		T273	1
all_values[8]	auto[0]	auto[1]	auto[1]	76	1			T24	1		T162	1		T241	3
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T24	4		T132	1		T162	2
all_values[8]	auto[1]	auto[1]	auto[1]	65	1			T24	4		T241	2		T242	1
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T241	1		T285	1		T286	3
all_values[9]	auto[0]	auto[0]	auto[1]	87	1			T24	4		T132	1		T162	2
all_values[9]	auto[0]	auto[1]	auto[0]	21	1			T241	1		T285	1		T286	2
all_values[9]	auto[0]	auto[1]	auto[1]	81	1			T24	5		T241	3		T35	5
all_values[9]	auto[1]	auto[0]	auto[1]	90	1			T24	1		T132	3		T162	2
all_values[9]	auto[1]	auto[1]	auto[1]	88	1			T24	5		T162	3		T241	3
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T242	1		T35	1		T289	5
all_values[10]	auto[0]	auto[0]	auto[1]	85	1			T24	3		T241	3		T242	2
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T162	1		T242	1		T35	1
all_values[10]	auto[0]	auto[1]	auto[1]	88	1			T24	5		T132	2		T162	3
all_values[10]	auto[1]	auto[0]	auto[1]	87	1			T24	4		T132	2		T162	1
all_values[10]	auto[1]	auto[1]	auto[1]	68	1			T24	3		T162	2		T241	3
all_values[11]	auto[0]	auto[0]	auto[0]	47	1			T162	4		T241	4		T242	1
all_values[11]	auto[0]	auto[0]	auto[1]	86	1			T24	10		T241	2		T242	1
all_values[11]	auto[0]	auto[1]	auto[0]	43	1			T162	3		T241	1		T242	3
all_values[11]	auto[0]	auto[1]	auto[1]	79	1			T24	1		T132	3		T241	2
all_values[11]	auto[1]	auto[0]	auto[1]	69	1			T24	3		T242	1		T35	3
all_values[11]	auto[1]	auto[1]	auto[1]	74	1			T24	1		T132	1		T241	3
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T241	2		T35	1		T292	2
all_values[12]	auto[0]	auto[0]	auto[1]	80	1			T24	3		T132	1		T162	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T24	1		T162	1		T285	1
all_values[12]	auto[0]	auto[1]	auto[1]	99	1			T24	2		T132	1		T162	2
all_values[12]	auto[1]	auto[0]	auto[1]	81	1			T24	4		T132	2		T241	2
all_values[12]	auto[1]	auto[1]	auto[1]	69	1			T24	5		T162	2		T241	1
all_values[13]	auto[0]	auto[0]	auto[0]	43	1			T242	1		T286	1		T292	1
all_values[13]	auto[0]	auto[0]	auto[1]	114	1			T24	4		T132	1		T162	3
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T24	2		T289	1		T293	2
all_values[13]	auto[0]	auto[1]	auto[1]	73	1			T24	4		T132	1		T162	2
all_values[13]	auto[1]	auto[0]	auto[1]	87	1			T24	2		T132	1		T162	1
all_values[13]	auto[1]	auto[1]	auto[1]	63	1			T24	3		T132	1		T162	1
all_values[14]	auto[0]	auto[0]	auto[0]	46	1			T24	1		T132	2		T162	1
all_values[14]	auto[0]	auto[0]	auto[1]	86	1			T24	8		T132	1		T162	1
all_values[14]	auto[0]	auto[1]	auto[0]	18	1			T241	1		T292	1		T294	2
all_values[14]	auto[0]	auto[1]	auto[1]	76	1			T24	2		T162	4		T241	4
all_values[14]	auto[1]	auto[0]	auto[1]	94	1			T24	4		T132	1		T162	1
all_values[14]	auto[1]	auto[1]	auto[1]	78	1			T241	3		T242	2		T35	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal