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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.16 97.15 90.03 97.22 71.43 94.18 98.44 89.68


Total test records in report: 1677
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T1559 /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3632111320 Jul 12 05:19:11 PM PDT 24 Jul 12 05:19:14 PM PDT 24 152848279 ps
T1560 /workspace/coverage/default/0.i2c_target_intr_smoke.3669261018 Jul 12 05:18:07 PM PDT 24 Jul 12 05:18:15 PM PDT 24 3901240722 ps
T1561 /workspace/coverage/default/46.i2c_target_timeout.4289964532 Jul 12 05:25:26 PM PDT 24 Jul 12 05:25:35 PM PDT 24 6117821364 ps
T1562 /workspace/coverage/default/39.i2c_host_perf.1940212937 Jul 12 05:24:33 PM PDT 24 Jul 12 05:25:13 PM PDT 24 6710449694 ps
T1563 /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.992639005 Jul 12 05:25:55 PM PDT 24 Jul 12 05:26:07 PM PDT 24 726089074 ps
T1564 /workspace/coverage/default/1.i2c_target_fifo_reset_acq.81896734 Jul 12 05:18:28 PM PDT 24 Jul 12 05:18:30 PM PDT 24 160881557 ps
T1565 /workspace/coverage/default/33.i2c_host_override.2511260411 Jul 12 05:23:52 PM PDT 24 Jul 12 05:23:54 PM PDT 24 31455217 ps
T1566 /workspace/coverage/default/32.i2c_target_stretch.3965033964 Jul 12 05:23:40 PM PDT 24 Jul 12 05:23:45 PM PDT 24 277458126 ps
T1567 /workspace/coverage/default/27.i2c_target_stress_wr.2301087755 Jul 12 05:23:03 PM PDT 24 Jul 12 05:23:20 PM PDT 24 15464514044 ps
T1568 /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1847536154 Jul 12 05:24:01 PM PDT 24 Jul 12 05:24:03 PM PDT 24 402406860 ps
T1569 /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3151286811 Jul 12 05:23:43 PM PDT 24 Jul 12 05:23:49 PM PDT 24 277712708 ps
T1570 /workspace/coverage/default/22.i2c_target_nack_acqfull.1474181838 Jul 12 05:22:28 PM PDT 24 Jul 12 05:22:33 PM PDT 24 2232603801 ps
T185 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.140707247 Jul 12 05:10:52 PM PDT 24 Jul 12 05:10:53 PM PDT 24 37071140 ps
T217 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4123068935 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:55 PM PDT 24 43769878 ps
T186 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4128991539 Jul 12 05:10:35 PM PDT 24 Jul 12 05:10:38 PM PDT 24 168782702 ps
T134 /workspace/coverage/cover_reg_top/8.i2c_intr_test.640574296 Jul 12 05:10:42 PM PDT 24 Jul 12 05:10:43 PM PDT 24 160508354 ps
T187 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2670639377 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:48 PM PDT 24 1150038903 ps
T1571 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3300955037 Jul 12 05:11:10 PM PDT 24 Jul 12 05:11:12 PM PDT 24 14654022 ps
T1572 /workspace/coverage/cover_reg_top/1.i2c_intr_test.889878744 Jul 12 05:10:17 PM PDT 24 Jul 12 05:10:18 PM PDT 24 80050905 ps
T202 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3057087394 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:35 PM PDT 24 44033592 ps
T287 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2214387895 Jul 12 05:11:14 PM PDT 24 Jul 12 05:11:15 PM PDT 24 15870771 ps
T107 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1825654482 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:35 PM PDT 24 77286719 ps
T108 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.769725318 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:38 PM PDT 24 603220009 ps
T204 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3851136332 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:35 PM PDT 24 31827107 ps
T236 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1074372484 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:36 PM PDT 24 30399043 ps
T210 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3617181972 Jul 12 05:10:50 PM PDT 24 Jul 12 05:10:52 PM PDT 24 72184936 ps
T1573 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1231749116 Jul 12 05:10:36 PM PDT 24 Jul 12 05:10:38 PM PDT 24 26786493 ps
T203 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1846371160 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 272528791 ps
T207 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1325706338 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:50 PM PDT 24 452337329 ps
T1574 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.229870252 Jul 12 05:10:25 PM PDT 24 Jul 12 05:10:26 PM PDT 24 30398664 ps
T294 /workspace/coverage/cover_reg_top/23.i2c_intr_test.319023319 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:04 PM PDT 24 35812161 ps
T109 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.58122573 Jul 12 05:10:25 PM PDT 24 Jul 12 05:10:29 PM PDT 24 1103433753 ps
T237 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2840571474 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:48 PM PDT 24 38142982 ps
T1575 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2535919063 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:06 PM PDT 24 17497555 ps
T110 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2092456236 Jul 12 05:10:17 PM PDT 24 Jul 12 05:10:18 PM PDT 24 43861912 ps
T290 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3545775654 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:07 PM PDT 24 39835481 ps
T238 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3527103409 Jul 12 05:10:35 PM PDT 24 Jul 12 05:10:38 PM PDT 24 32448205 ps
T111 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.638313719 Jul 12 05:10:26 PM PDT 24 Jul 12 05:10:28 PM PDT 24 83699421 ps
T227 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.4061844527 Jul 12 05:10:19 PM PDT 24 Jul 12 05:10:20 PM PDT 24 40222682 ps
T205 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1331133678 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:57 PM PDT 24 250980182 ps
T112 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2804577129 Jul 12 05:10:44 PM PDT 24 Jul 12 05:10:46 PM PDT 24 142256090 ps
T206 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1880588529 Jul 12 05:10:53 PM PDT 24 Jul 12 05:10:55 PM PDT 24 38449844 ps
T288 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3923358876 Jul 12 05:10:47 PM PDT 24 Jul 12 05:10:49 PM PDT 24 23317999 ps
T1576 /workspace/coverage/cover_reg_top/39.i2c_intr_test.2760642421 Jul 12 05:11:11 PM PDT 24 Jul 12 05:11:12 PM PDT 24 47881614 ps
T113 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3061141138 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:48 PM PDT 24 36129128 ps
T135 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1085153606 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:03 PM PDT 24 31838040 ps
T226 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1799293398 Jul 12 05:10:16 PM PDT 24 Jul 12 05:10:18 PM PDT 24 31035229 ps
T215 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1891550727 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:56 PM PDT 24 860968047 ps
T228 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1519888613 Jul 12 05:10:19 PM PDT 24 Jul 12 05:10:21 PM PDT 24 148518695 ps
T239 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.683067671 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:49 PM PDT 24 20901550 ps
T208 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3131932257 Jul 12 05:10:42 PM PDT 24 Jul 12 05:10:44 PM PDT 24 59322609 ps
T214 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.600676341 Jul 12 05:10:08 PM PDT 24 Jul 12 05:10:11 PM PDT 24 33235352 ps
T1577 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1902560090 Jul 12 05:10:34 PM PDT 24 Jul 12 05:10:38 PM PDT 24 352043791 ps
T1578 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1807050665 Jul 12 05:11:13 PM PDT 24 Jul 12 05:11:14 PM PDT 24 46561750 ps
T1579 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3073849218 Jul 12 05:11:11 PM PDT 24 Jul 12 05:11:13 PM PDT 24 47220623 ps
T211 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2256395334 Jul 12 05:10:22 PM PDT 24 Jul 12 05:10:24 PM PDT 24 254901202 ps
T218 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1916421474 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:34 PM PDT 24 258772861 ps
T229 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2193346803 Jul 12 05:10:17 PM PDT 24 Jul 12 05:10:18 PM PDT 24 50571274 ps
T1580 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1596472499 Jul 12 05:10:43 PM PDT 24 Jul 12 05:10:44 PM PDT 24 23387352 ps
T1581 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1369189032 Jul 12 05:11:05 PM PDT 24 Jul 12 05:11:07 PM PDT 24 60776721 ps
T1582 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2126684798 Jul 12 05:11:11 PM PDT 24 Jul 12 05:11:12 PM PDT 24 17920631 ps
T114 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2844975581 Jul 12 05:10:25 PM PDT 24 Jul 12 05:10:26 PM PDT 24 124513877 ps
T1583 /workspace/coverage/cover_reg_top/17.i2c_intr_test.519343653 Jul 12 05:10:57 PM PDT 24 Jul 12 05:10:58 PM PDT 24 43400596 ps
T115 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.209243649 Jul 12 05:10:47 PM PDT 24 Jul 12 05:10:49 PM PDT 24 26776920 ps
T1584 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3068945033 Jul 12 05:10:37 PM PDT 24 Jul 12 05:10:39 PM PDT 24 104349945 ps
T1585 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2996885382 Jul 12 05:11:07 PM PDT 24 Jul 12 05:11:08 PM PDT 24 31314113 ps
T230 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1778572054 Jul 12 05:10:48 PM PDT 24 Jul 12 05:10:49 PM PDT 24 29295059 ps
T1586 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3730011696 Jul 12 05:11:05 PM PDT 24 Jul 12 05:11:07 PM PDT 24 43293666 ps
T1587 /workspace/coverage/cover_reg_top/5.i2c_intr_test.4169901390 Jul 12 05:10:34 PM PDT 24 Jul 12 05:10:37 PM PDT 24 16331359 ps
T1588 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3233530433 Jul 12 05:10:48 PM PDT 24 Jul 12 05:10:50 PM PDT 24 80079823 ps
T231 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2450664313 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 29689156 ps
T1589 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2099964025 Jul 12 05:10:44 PM PDT 24 Jul 12 05:10:47 PM PDT 24 35683769 ps
T212 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3372993752 Jul 12 05:10:51 PM PDT 24 Jul 12 05:10:53 PM PDT 24 74789138 ps
T1590 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.575385073 Jul 12 05:10:51 PM PDT 24 Jul 12 05:10:54 PM PDT 24 110393153 ps
T240 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2455902954 Jul 12 05:10:48 PM PDT 24 Jul 12 05:10:50 PM PDT 24 91525746 ps
T1591 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1397509602 Jul 12 05:10:16 PM PDT 24 Jul 12 05:10:17 PM PDT 24 113240786 ps
T1592 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3080022657 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:47 PM PDT 24 81329856 ps
T1593 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.743409231 Jul 12 05:10:18 PM PDT 24 Jul 12 05:10:21 PM PDT 24 736440503 ps
T116 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1643657462 Jul 12 05:11:08 PM PDT 24 Jul 12 05:11:10 PM PDT 24 64341231 ps
T1594 /workspace/coverage/cover_reg_top/41.i2c_intr_test.114365063 Jul 12 05:11:09 PM PDT 24 Jul 12 05:11:10 PM PDT 24 49845460 ps
T1595 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3446481937 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:06 PM PDT 24 17821256 ps
T158 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1935074767 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:36 PM PDT 24 19413521 ps
T1596 /workspace/coverage/cover_reg_top/36.i2c_intr_test.859238842 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:06 PM PDT 24 25043917 ps
T1597 /workspace/coverage/cover_reg_top/28.i2c_intr_test.414339591 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:06 PM PDT 24 29232981 ps
T1598 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.426986770 Jul 12 05:10:24 PM PDT 24 Jul 12 05:10:25 PM PDT 24 21672184 ps
T1599 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.822243425 Jul 12 05:10:43 PM PDT 24 Jul 12 05:10:44 PM PDT 24 171040160 ps
T130 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2197057030 Jul 12 05:10:41 PM PDT 24 Jul 12 05:10:42 PM PDT 24 23778980 ps
T209 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.442666200 Jul 12 05:10:42 PM PDT 24 Jul 12 05:10:45 PM PDT 24 130045606 ps
T131 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2675842010 Jul 12 05:10:55 PM PDT 24 Jul 12 05:10:57 PM PDT 24 44747677 ps
T1600 /workspace/coverage/cover_reg_top/2.i2c_intr_test.387669840 Jul 12 05:10:18 PM PDT 24 Jul 12 05:10:19 PM PDT 24 16858321 ps
T1601 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.10560352 Jul 12 05:10:55 PM PDT 24 Jul 12 05:10:58 PM PDT 24 209699404 ps
T1602 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2419480258 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:36 PM PDT 24 81818893 ps
T163 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.93260056 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:36 PM PDT 24 87660449 ps
T1603 /workspace/coverage/cover_reg_top/24.i2c_intr_test.368205437 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:07 PM PDT 24 34891395 ps
T232 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3260045429 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:48 PM PDT 24 18777187 ps
T1604 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.475862645 Jul 12 05:10:48 PM PDT 24 Jul 12 05:10:51 PM PDT 24 339663827 ps
T1605 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1364885035 Jul 12 05:10:40 PM PDT 24 Jul 12 05:10:41 PM PDT 24 16956062 ps
T1606 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3360140733 Jul 12 05:10:37 PM PDT 24 Jul 12 05:10:40 PM PDT 24 229757203 ps
T278 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3157209908 Jul 12 05:10:18 PM PDT 24 Jul 12 05:10:21 PM PDT 24 121403996 ps
T1607 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.739061200 Jul 12 05:10:57 PM PDT 24 Jul 12 05:10:59 PM PDT 24 164379283 ps
T1608 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.160731281 Jul 12 05:10:22 PM PDT 24 Jul 12 05:10:24 PM PDT 24 102295836 ps
T1609 /workspace/coverage/cover_reg_top/4.i2c_intr_test.769410664 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:33 PM PDT 24 104175219 ps
T1610 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3008208307 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:35 PM PDT 24 19846041 ps
T233 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.304733376 Jul 12 05:10:50 PM PDT 24 Jul 12 05:10:51 PM PDT 24 17420341 ps
T1611 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.17417960 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:08 PM PDT 24 309107287 ps
T1612 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1948831108 Jul 12 05:10:40 PM PDT 24 Jul 12 05:10:42 PM PDT 24 231758961 ps
T1613 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.4075483330 Jul 12 05:10:28 PM PDT 24 Jul 12 05:10:29 PM PDT 24 32707574 ps
T1614 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2197431340 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:06 PM PDT 24 276129874 ps
T1615 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4270930016 Jul 12 05:10:40 PM PDT 24 Jul 12 05:10:43 PM PDT 24 100947522 ps
T234 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4250324321 Jul 12 05:10:17 PM PDT 24 Jul 12 05:10:19 PM PDT 24 68817185 ps
T235 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.790480878 Jul 12 05:10:32 PM PDT 24 Jul 12 05:10:38 PM PDT 24 225524160 ps
T1616 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1398602423 Jul 12 05:11:09 PM PDT 24 Jul 12 05:11:11 PM PDT 24 21184033 ps
T1617 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.499154135 Jul 12 05:10:34 PM PDT 24 Jul 12 05:10:37 PM PDT 24 118464949 ps
T1618 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1596270470 Jul 12 05:11:10 PM PDT 24 Jul 12 05:11:11 PM PDT 24 63643087 ps
T1619 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2577539165 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:06 PM PDT 24 154379639 ps
T1620 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1476976021 Jul 12 05:10:40 PM PDT 24 Jul 12 05:10:42 PM PDT 24 27286482 ps
T1621 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2437504661 Jul 12 05:10:55 PM PDT 24 Jul 12 05:10:57 PM PDT 24 55124688 ps
T1622 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1937314964 Jul 12 05:10:57 PM PDT 24 Jul 12 05:10:59 PM PDT 24 48493247 ps
T1623 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1182925680 Jul 12 05:10:21 PM PDT 24 Jul 12 05:10:23 PM PDT 24 104560883 ps
T1624 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3184972794 Jul 12 05:10:50 PM PDT 24 Jul 12 05:10:52 PM PDT 24 31127286 ps
T1625 /workspace/coverage/cover_reg_top/21.i2c_intr_test.599121758 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:06 PM PDT 24 192922703 ps
T1626 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.367961325 Jul 12 05:11:01 PM PDT 24 Jul 12 05:11:02 PM PDT 24 73335536 ps
T1627 /workspace/coverage/cover_reg_top/25.i2c_intr_test.2991086251 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:06 PM PDT 24 17616574 ps
T1628 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1078769476 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:35 PM PDT 24 70899571 ps
T1629 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1230011205 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:38 PM PDT 24 84934795 ps
T1630 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3133930172 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:04 PM PDT 24 18456636 ps
T1631 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3742110578 Jul 12 05:10:26 PM PDT 24 Jul 12 05:10:32 PM PDT 24 1452397656 ps
T1632 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3411208651 Jul 12 05:10:23 PM PDT 24 Jul 12 05:10:24 PM PDT 24 24531944 ps
T1633 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2449714201 Jul 12 05:10:18 PM PDT 24 Jul 12 05:10:19 PM PDT 24 44987447 ps
T1634 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2230908761 Jul 12 05:10:45 PM PDT 24 Jul 12 05:10:46 PM PDT 24 38433095 ps
T1635 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2247602815 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:05 PM PDT 24 15184428 ps
T1636 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2018003235 Jul 12 05:11:15 PM PDT 24 Jul 12 05:11:16 PM PDT 24 27349968 ps
T1637 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.751301789 Jul 12 05:10:22 PM PDT 24 Jul 12 05:10:25 PM PDT 24 110695347 ps
T1638 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1154714854 Jul 12 05:10:21 PM PDT 24 Jul 12 05:10:22 PM PDT 24 51989986 ps
T1639 /workspace/coverage/cover_reg_top/32.i2c_intr_test.42187627 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:05 PM PDT 24 17934884 ps
T213 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.353679558 Jul 12 05:10:20 PM PDT 24 Jul 12 05:10:22 PM PDT 24 560188638 ps
T1640 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.185473923 Jul 12 05:10:22 PM PDT 24 Jul 12 05:10:28 PM PDT 24 1532870478 ps
T1641 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1951576730 Jul 12 05:11:01 PM PDT 24 Jul 12 05:11:03 PM PDT 24 15636933 ps
T1642 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2105737288 Jul 12 05:10:29 PM PDT 24 Jul 12 05:10:30 PM PDT 24 52262631 ps
T219 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3275772457 Jul 12 05:10:55 PM PDT 24 Jul 12 05:10:58 PM PDT 24 152946017 ps
T1643 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1217923074 Jul 12 05:10:25 PM PDT 24 Jul 12 05:10:27 PM PDT 24 228576815 ps
T1644 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.329234468 Jul 12 05:10:56 PM PDT 24 Jul 12 05:10:58 PM PDT 24 210032519 ps
T1645 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3107743348 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:49 PM PDT 24 190790557 ps
T1646 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3381014877 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:48 PM PDT 24 101534262 ps
T1647 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.605323049 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:37 PM PDT 24 111757080 ps
T1648 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.213469903 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:56 PM PDT 24 441315236 ps
T1649 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1447253311 Jul 12 05:11:12 PM PDT 24 Jul 12 05:11:14 PM PDT 24 19879166 ps
T1650 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3006891252 Jul 12 05:10:27 PM PDT 24 Jul 12 05:10:29 PM PDT 24 276014194 ps
T1651 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1684570745 Jul 12 05:11:04 PM PDT 24 Jul 12 05:11:06 PM PDT 24 51122423 ps
T1652 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.466800919 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:57 PM PDT 24 437069029 ps
T164 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3094506644 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 65151238 ps
T216 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.970539160 Jul 12 05:10:38 PM PDT 24 Jul 12 05:10:41 PM PDT 24 579708017 ps
T1653 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3507769835 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 44065894 ps
T1654 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2605391858 Jul 12 05:10:21 PM PDT 24 Jul 12 05:10:22 PM PDT 24 24722358 ps
T1655 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3532425087 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:49 PM PDT 24 51767710 ps
T1656 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.377032928 Jul 12 05:10:49 PM PDT 24 Jul 12 05:10:50 PM PDT 24 161833668 ps
T1657 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3311700247 Jul 12 05:10:54 PM PDT 24 Jul 12 05:10:56 PM PDT 24 19910800 ps
T1658 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3233997638 Jul 12 05:10:45 PM PDT 24 Jul 12 05:10:48 PM PDT 24 168707856 ps
T1659 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2105359060 Jul 12 05:10:33 PM PDT 24 Jul 12 05:10:36 PM PDT 24 21096372 ps
T1660 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3064870984 Jul 12 05:10:58 PM PDT 24 Jul 12 05:11:00 PM PDT 24 32038991 ps
T1661 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2628521881 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 73892718 ps
T1662 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4000522401 Jul 12 05:11:03 PM PDT 24 Jul 12 05:11:05 PM PDT 24 24840145 ps
T1663 /workspace/coverage/cover_reg_top/14.i2c_intr_test.4090845714 Jul 12 05:10:46 PM PDT 24 Jul 12 05:10:47 PM PDT 24 20421378 ps
T1664 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.52722380 Jul 12 05:10:45 PM PDT 24 Jul 12 05:10:47 PM PDT 24 33532444 ps
T1665 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4026730888 Jul 12 05:10:47 PM PDT 24 Jul 12 05:10:49 PM PDT 24 106324514 ps
T1666 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3653402167 Jul 12 05:10:41 PM PDT 24 Jul 12 05:10:42 PM PDT 24 41317937 ps
T1667 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2678511602 Jul 12 05:11:12 PM PDT 24 Jul 12 05:11:14 PM PDT 24 28202436 ps
T1668 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1150939573 Jul 12 05:11:10 PM PDT 24 Jul 12 05:11:12 PM PDT 24 145587744 ps
T1669 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.134841831 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 70760418 ps
T1670 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.933114945 Jul 12 05:10:57 PM PDT 24 Jul 12 05:10:58 PM PDT 24 188407668 ps
T1671 /workspace/coverage/cover_reg_top/45.i2c_intr_test.4125056818 Jul 12 05:11:11 PM PDT 24 Jul 12 05:11:13 PM PDT 24 20526849 ps
T1672 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.591808049 Jul 12 05:11:02 PM PDT 24 Jul 12 05:11:04 PM PDT 24 122621851 ps
T1673 /workspace/coverage/cover_reg_top/13.i2c_intr_test.4040490234 Jul 12 05:10:51 PM PDT 24 Jul 12 05:10:53 PM PDT 24 26756913 ps
T1674 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2722873702 Jul 12 05:10:35 PM PDT 24 Jul 12 05:10:37 PM PDT 24 20537168 ps
T1675 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4033385987 Jul 12 05:10:45 PM PDT 24 Jul 12 05:10:49 PM PDT 24 2246034145 ps
T1676 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2322883154 Jul 12 05:10:23 PM PDT 24 Jul 12 05:10:24 PM PDT 24 201010775 ps
T1677 /workspace/coverage/cover_reg_top/0.i2c_intr_test.2718089345 Jul 12 05:10:18 PM PDT 24 Jul 12 05:10:20 PM PDT 24 18832685 ps

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3013480377
Short name T2
Test name
Test status
Simulation time 7496488672 ps
CPU time 60.62 seconds
Started Jul 12 05:21:32 PM PDT 24
Finished Jul 12 05:22:34 PM PDT 24
Peak memory 675532 kb
Host smart-9c083fb6-d67c-4572-bb3a-4826a42ac07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013480377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3013480377
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2175380867
Short name T53
Test name
Test status
Simulation time 3440080925 ps
CPU time 5.73 seconds
Started Jul 12 05:19:01 PM PDT 24
Finished Jul 12 05:19:07 PM PDT 24
Peak memory 215052 kb
Host smart-d3d4acba-7d34-4da3-aa50-6e6822c3a93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175380867 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2175380867
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2461203290
Short name T24
Test name
Test status
Simulation time 6801380269 ps
CPU time 412.61 seconds
Started Jul 12 05:25:48 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 713532 kb
Host smart-3232d5bb-facf-4265-9ec1-45d89fecf54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461203290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2461203290
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2818410904
Short name T48
Test name
Test status
Simulation time 9563004092 ps
CPU time 11.92 seconds
Started Jul 12 05:18:03 PM PDT 24
Finished Jul 12 05:18:16 PM PDT 24
Peak memory 213976 kb
Host smart-32495a70-55a5-482f-a7af-40e949388d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818410904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2818410904
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.1495534088
Short name T22
Test name
Test status
Simulation time 1021607601 ps
CPU time 5.54 seconds
Started Jul 12 05:23:00 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 205268 kb
Host smart-029d95cc-a42f-4b50-adc2-95c1c8ea7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495534088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1495534088
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.769725318
Short name T108
Test name
Test status
Simulation time 603220009 ps
CPU time 2.29 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204680 kb
Host smart-d8bbb2e5-0ee6-469b-ab6d-f7209cfb5f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769725318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.769725318
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.525056881
Short name T52
Test name
Test status
Simulation time 2472183502 ps
CPU time 2.89 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:28 PM PDT 24
Peak memory 213564 kb
Host smart-e486c9d1-282a-4ba1-a4cc-dbbd25233a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525056881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_nack_acqfull.525056881
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3851136332
Short name T204
Test name
Test status
Simulation time 31827107 ps
CPU time 1.49 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 204688 kb
Host smart-280b1efa-7115-4627-b69c-ceb6855b7a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851136332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3851136332
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/20.i2c_host_override.1261664438
Short name T144
Test name
Test status
Simulation time 53589064 ps
CPU time 0.66 seconds
Started Jul 12 05:22:03 PM PDT 24
Finished Jul 12 05:22:04 PM PDT 24
Peak memory 205092 kb
Host smart-14b6bd5c-bf00-41b5-b91b-25ead2a5faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261664438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1261664438
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3078667201
Short name T14
Test name
Test status
Simulation time 4279049836 ps
CPU time 117.24 seconds
Started Jul 12 05:20:15 PM PDT 24
Finished Jul 12 05:22:12 PM PDT 24
Peak memory 1182252 kb
Host smart-117280f0-2b13-49ca-b837-cbf966b4046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078667201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3078667201
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.352502022
Short name T56
Test name
Test status
Simulation time 20410557805 ps
CPU time 61.55 seconds
Started Jul 12 05:23:16 PM PDT 24
Finished Jul 12 05:24:18 PM PDT 24
Peak memory 885668 kb
Host smart-c4e4c0f7-33e7-433c-a258-a2d82161984c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352502022 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.352502022
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.180754675
Short name T35
Test name
Test status
Simulation time 25967388288 ps
CPU time 1176.37 seconds
Started Jul 12 05:22:03 PM PDT 24
Finished Jul 12 05:41:41 PM PDT 24
Peak memory 1914932 kb
Host smart-2c293cda-f788-437a-b8d9-d8055885e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180754675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.180754675
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2064039354
Short name T251
Test name
Test status
Simulation time 903898700 ps
CPU time 1.25 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:41 PM PDT 24
Peak memory 205104 kb
Host smart-97f163af-356d-418b-be94-efc65e2e009a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064039354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2064039354
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2756599297
Short name T327
Test name
Test status
Simulation time 17091326 ps
CPU time 0.63 seconds
Started Jul 12 05:18:15 PM PDT 24
Finished Jul 12 05:18:16 PM PDT 24
Peak memory 204616 kb
Host smart-e7265d7b-3eac-4fc4-be72-1daee4533436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756599297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2756599297
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.1462584946
Short name T59
Test name
Test status
Simulation time 1941596229 ps
CPU time 2.57 seconds
Started Jul 12 05:20:44 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 205416 kb
Host smart-f1384102-f1c5-43cb-9ce2-a9260144a2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462584946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.1462584946
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.2480942883
Short name T54
Test name
Test status
Simulation time 416602529 ps
CPU time 6.63 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:25:15 PM PDT 24
Peak memory 213604 kb
Host smart-0df9384b-716e-4f56-a60b-85bf3c725837
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480942883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2480942883
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1778572054
Short name T230
Test name
Test status
Simulation time 29295059 ps
CPU time 0.78 seconds
Started Jul 12 05:10:48 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204356 kb
Host smart-526ca8ea-36a4-4349-9841-bd1e8b78dfa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778572054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1778572054
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.39964042
Short name T76
Test name
Test status
Simulation time 8123255903 ps
CPU time 7.06 seconds
Started Jul 12 05:19:04 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 221820 kb
Host smart-60a0f7e8-51d0-47e6-bbc8-b77cd2c3269e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39964042 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_timeout.39964042
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3466978054
Short name T81
Test name
Test status
Simulation time 11691727059 ps
CPU time 91.33 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:22:56 PM PDT 24
Peak memory 461228 kb
Host smart-9ec13993-401e-4551-85f8-34ff91e7a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466978054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3466978054
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3131744474
Short name T637
Test name
Test status
Simulation time 25639436311 ps
CPU time 524.64 seconds
Started Jul 12 05:24:09 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 205356 kb
Host smart-15bc24f0-fe9b-4a41-96d7-6d980203882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131744474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3131744474
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.113711007
Short name T61
Test name
Test status
Simulation time 488757529 ps
CPU time 2.97 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:12 PM PDT 24
Peak memory 215308 kb
Host smart-0b6f2f79-04af-4579-8caf-e407a2508994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113711007 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.113711007
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.1388477649
Short name T65
Test name
Test status
Simulation time 1468654039 ps
CPU time 3.21 seconds
Started Jul 12 05:21:06 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 213592 kb
Host smart-e45a8297-e325-49f6-98f6-acc5db90e002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388477649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.1388477649
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.336554051
Short name T286
Test name
Test status
Simulation time 88997149608 ps
CPU time 766.01 seconds
Started Jul 12 05:20:20 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 2285780 kb
Host smart-76660b34-780e-4625-aa0e-cd7fd233b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336554051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.336554051
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2418490958
Short name T192
Test name
Test status
Simulation time 978814192 ps
CPU time 0.93 seconds
Started Jul 12 05:18:13 PM PDT 24
Finished Jul 12 05:18:15 PM PDT 24
Peak memory 223568 kb
Host smart-68e66c45-951b-462b-a16f-df344cb5c0af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418490958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2418490958
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.96374637
Short name T28
Test name
Test status
Simulation time 474315459 ps
CPU time 7.39 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:25:46 PM PDT 24
Peak memory 205316 kb
Host smart-73828d9e-deab-4332-98e9-b883df8a2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96374637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.96374637
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.105373198
Short name T106
Test name
Test status
Simulation time 596371146 ps
CPU time 1.52 seconds
Started Jul 12 05:20:45 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 205580 kb
Host smart-9ba93cfc-1079-4d2f-a136-59e9a2dd5b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105373198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.105373198
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.271473470
Short name T25
Test name
Test status
Simulation time 383796651 ps
CPU time 16.52 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:21:41 PM PDT 24
Peak memory 205280 kb
Host smart-1afe45ee-1822-40f6-b2e7-113338fcd209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271473470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.271473470
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3375285516
Short name T245
Test name
Test status
Simulation time 153137294 ps
CPU time 4.67 seconds
Started Jul 12 05:22:26 PM PDT 24
Finished Jul 12 05:22:32 PM PDT 24
Peak memory 233096 kb
Host smart-4090b97a-ab0c-4623-a682-15dbd5638b63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375285516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3375285516
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.3707021430
Short name T69
Test name
Test status
Simulation time 4663201351 ps
CPU time 2.56 seconds
Started Jul 12 05:20:39 PM PDT 24
Finished Jul 12 05:20:43 PM PDT 24
Peak memory 205500 kb
Host smart-c1b00cb4-24fe-41c6-bc88-fa86e9f724da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707021430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.3707021430
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.387669840
Short name T1600
Test name
Test status
Simulation time 16858321 ps
CPU time 0.66 seconds
Started Jul 12 05:10:18 PM PDT 24
Finished Jul 12 05:10:19 PM PDT 24
Peak memory 204332 kb
Host smart-2174ae40-722e-4ec7-a16d-60583f56cf20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387669840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.387669840
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.93260056
Short name T163
Test name
Test status
Simulation time 87660449 ps
CPU time 2.06 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 204772 kb
Host smart-665ca6ec-84d5-43e3-8073-28e144cb511e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93260056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.93260056
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.209032999
Short name T119
Test name
Test status
Simulation time 11067869691 ps
CPU time 116.34 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 1325884 kb
Host smart-90016da1-d3e7-498e-bef8-041aa57afe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209032999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.209032999
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1384523911
Short name T391
Test name
Test status
Simulation time 659643890 ps
CPU time 1.23 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:20:35 PM PDT 24
Peak memory 205116 kb
Host smart-44410c52-a8b8-42f1-ab65-4bc86c8a4eed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384523911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1384523911
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.4234467725
Short name T98
Test name
Test status
Simulation time 5550418900 ps
CPU time 10.32 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:49 PM PDT 24
Peak memory 210748 kb
Host smart-f4094849-ff50-43cf-9b54-9a286dcc95d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234467725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.4234467725
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_host_override.3279558684
Short name T271
Test name
Test status
Simulation time 82992103 ps
CPU time 0.7 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 205092 kb
Host smart-3355b082-07a4-4c0c-8c74-ae9a6b9b9906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279558684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3279558684
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1968630998
Short name T75
Test name
Test status
Simulation time 1248654659 ps
CPU time 7.8 seconds
Started Jul 12 05:22:33 PM PDT 24
Finished Jul 12 05:22:41 PM PDT 24
Peak memory 213660 kb
Host smart-9936f6bd-0f4c-4efd-9e89-6d11495f0498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968630998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1968630998
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2067982817
Short name T267
Test name
Test status
Simulation time 305334288 ps
CPU time 4.48 seconds
Started Jul 12 05:22:44 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 205356 kb
Host smart-8e219438-4912-4775-8661-46d366b51372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067982817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2067982817
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1975917052
Short name T255
Test name
Test status
Simulation time 117438432 ps
CPU time 1.11 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:05 PM PDT 24
Peak memory 205108 kb
Host smart-f654c5fd-e2b1-4e60-ae6a-d4ac6accddf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975917052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1975917052
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3676422492
Short name T86
Test name
Test status
Simulation time 2800398389 ps
CPU time 226.95 seconds
Started Jul 12 05:23:08 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 901708 kb
Host smart-21739ee9-eb38-4493-b984-b7e4f0be8b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676422492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3676422492
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.675201104
Short name T649
Test name
Test status
Simulation time 1590597062 ps
CPU time 1.61 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:37 PM PDT 24
Peak memory 213536 kb
Host smart-b553bdf2-b604-4d83-9bb0-1cad1e660a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675201104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.675201104
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2602996754
Short name T221
Test name
Test status
Simulation time 11865934015 ps
CPU time 102.05 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:22:21 PM PDT 24
Peak memory 920260 kb
Host smart-39e079b9-8aa0-470e-ba41-3a9530b9f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602996754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2602996754
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1170714053
Short name T225
Test name
Test status
Simulation time 11754832197 ps
CPU time 22.71 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 724064 kb
Host smart-381d02c7-10c9-456d-b569-b27c72705e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170714053 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1170714053
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1846371160
Short name T203
Test name
Test status
Simulation time 272528791 ps
CPU time 2.1 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204668 kb
Host smart-d653c738-ca52-4b90-bedc-fd37afea0011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846371160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1846371160
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3124935529
Short name T82
Test name
Test status
Simulation time 12769184325 ps
CPU time 117.61 seconds
Started Jul 12 05:21:05 PM PDT 24
Finished Jul 12 05:23:03 PM PDT 24
Peak memory 974372 kb
Host smart-8e3d7a8d-a8e3-4d6a-8c15-de977c8abd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124935529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3124935529
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1101812686
Short name T87
Test name
Test status
Simulation time 433450184 ps
CPU time 1.5 seconds
Started Jul 12 05:24:02 PM PDT 24
Finished Jul 12 05:24:04 PM PDT 24
Peak memory 205224 kb
Host smart-f5ca0054-c482-469f-a730-5b0d4a179d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101812686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1101812686
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1055586737
Short name T16
Test name
Test status
Simulation time 24097520540 ps
CPU time 621.14 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 205232 kb
Host smart-2321bcce-d9f2-4c9d-9cc7-fa8a163b714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055586737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1055586737
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1818895430
Short name T248
Test name
Test status
Simulation time 882524285 ps
CPU time 1.29 seconds
Started Jul 12 05:18:04 PM PDT 24
Finished Jul 12 05:18:06 PM PDT 24
Peak memory 205404 kb
Host smart-7259b088-5274-4eff-a2db-8017ecce91ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818895430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1818895430
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2780242933
Short name T615
Test name
Test status
Simulation time 1442181893 ps
CPU time 43.48 seconds
Started Jul 12 05:18:08 PM PDT 24
Finished Jul 12 05:18:52 PM PDT 24
Peak memory 523448 kb
Host smart-4d161950-5c4a-4319-8f78-db2308829b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780242933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2780242933
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2617300958
Short name T260
Test name
Test status
Simulation time 765521386 ps
CPU time 17.07 seconds
Started Jul 12 05:18:28 PM PDT 24
Finished Jul 12 05:18:46 PM PDT 24
Peak memory 205232 kb
Host smart-af3ee509-1854-4f4a-8673-12bf1f4d8a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617300958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2617300958
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2737827623
Short name T1507
Test name
Test status
Simulation time 349960637 ps
CPU time 4.66 seconds
Started Jul 12 06:45:37 PM PDT 24
Finished Jul 12 06:45:50 PM PDT 24
Peak memory 205344 kb
Host smart-b7d78344-ce0d-437c-be19-b6240cd613a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737827623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2737827623
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3134011851
Short name T281
Test name
Test status
Simulation time 703094977 ps
CPU time 33.98 seconds
Started Jul 12 05:20:59 PM PDT 24
Finished Jul 12 05:21:34 PM PDT 24
Peak memory 213644 kb
Host smart-ed6a3298-60b8-4e09-9b12-c812da846e6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134011851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3134011851
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3002364193
Short name T282
Test name
Test status
Simulation time 2909165179 ps
CPU time 7.38 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 221784 kb
Host smart-86043653-397d-40f9-8402-5480298251a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002364193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3002364193
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3763632214
Short name T419
Test name
Test status
Simulation time 1271517795 ps
CPU time 17.56 seconds
Started Jul 12 05:21:50 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 237712 kb
Host smart-5d37c384-b0fe-4459-b7ef-efc5f9cfe1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763632214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3763632214
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1389905639
Short name T258
Test name
Test status
Simulation time 1664412407 ps
CPU time 7.93 seconds
Started Jul 12 05:25:05 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 205308 kb
Host smart-f41bb791-64cd-43d0-8358-b2823e590f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389905639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1389905639
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1891550727
Short name T215
Test name
Test status
Simulation time 860968047 ps
CPU time 1.36 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 204744 kb
Host smart-bd03db4d-2b20-436e-8d81-6aa39fe86a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891550727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1891550727
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1862922327
Short name T88
Test name
Test status
Simulation time 4375019463 ps
CPU time 35.49 seconds
Started Jul 12 05:24:24 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 213648 kb
Host smart-9b2a2f00-ad8d-4794-abf0-9d680a8fd222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862922327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1862922327
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.353679558
Short name T213
Test name
Test status
Simulation time 560188638 ps
CPU time 1.41 seconds
Started Jul 12 05:10:20 PM PDT 24
Finished Jul 12 05:10:22 PM PDT 24
Peak memory 204692 kb
Host smart-5eb1dcbf-bd76-43c5-9d3c-ca378534564f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353679558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.353679558
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1325706338
Short name T207
Test name
Test status
Simulation time 452337329 ps
CPU time 2.21 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:50 PM PDT 24
Peak memory 204676 kb
Host smart-d7d2430a-5676-466f-ad09-d55fa49b55c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325706338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1325706338
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1275904300
Short name T161
Test name
Test status
Simulation time 130957558 ps
CPU time 0.93 seconds
Started Jul 12 05:22:55 PM PDT 24
Finished Jul 12 05:22:56 PM PDT 24
Peak memory 205308 kb
Host smart-e217b54b-7249-42cb-b4f8-35cfa10101c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275904300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1275904300
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4250324321
Short name T234
Test name
Test status
Simulation time 68817185 ps
CPU time 1.26 seconds
Started Jul 12 05:10:17 PM PDT 24
Finished Jul 12 05:10:19 PM PDT 24
Peak memory 204572 kb
Host smart-6898429e-457a-46dd-a8b6-23951b199a64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250324321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.4250324321
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.743409231
Short name T1593
Test name
Test status
Simulation time 736440503 ps
CPU time 2.72 seconds
Started Jul 12 05:10:18 PM PDT 24
Finished Jul 12 05:10:21 PM PDT 24
Peak memory 204616 kb
Host smart-0dfa4864-66b2-411d-ad12-61cde19a848e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743409231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.743409231
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1154714854
Short name T1638
Test name
Test status
Simulation time 51989986 ps
CPU time 0.68 seconds
Started Jul 12 05:10:21 PM PDT 24
Finished Jul 12 05:10:22 PM PDT 24
Peak memory 204356 kb
Host smart-5eaebc37-22a7-477a-9549-ee3d2642cc4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154714854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1154714854
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2605391858
Short name T1654
Test name
Test status
Simulation time 24722358 ps
CPU time 0.79 seconds
Started Jul 12 05:10:21 PM PDT 24
Finished Jul 12 05:10:22 PM PDT 24
Peak memory 204488 kb
Host smart-a6fba6b2-c9f9-4e43-b88f-e14905d9c450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605391858 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2605391858
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.4061844527
Short name T227
Test name
Test status
Simulation time 40222682 ps
CPU time 0.82 seconds
Started Jul 12 05:10:19 PM PDT 24
Finished Jul 12 05:10:20 PM PDT 24
Peak memory 204504 kb
Host smart-ac148437-3bf2-49e9-88c1-3899797094bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061844527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.4061844527
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.2718089345
Short name T1677
Test name
Test status
Simulation time 18832685 ps
CPU time 0.74 seconds
Started Jul 12 05:10:18 PM PDT 24
Finished Jul 12 05:10:20 PM PDT 24
Peak memory 204420 kb
Host smart-08737c82-fac0-4fc2-b810-92f49a1c1ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718089345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2718089345
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1397509602
Short name T1591
Test name
Test status
Simulation time 113240786 ps
CPU time 0.87 seconds
Started Jul 12 05:10:16 PM PDT 24
Finished Jul 12 05:10:17 PM PDT 24
Peak memory 204404 kb
Host smart-b7c9c7d2-c217-4692-aa02-9f8ddd8759d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397509602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1397509602
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.600676341
Short name T214
Test name
Test status
Simulation time 33235352 ps
CPU time 1.73 seconds
Started Jul 12 05:10:08 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 204736 kb
Host smart-1fb1fb30-8814-4731-b8fb-deffaf4831e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600676341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.600676341
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1519888613
Short name T228
Test name
Test status
Simulation time 148518695 ps
CPU time 1.25 seconds
Started Jul 12 05:10:19 PM PDT 24
Finished Jul 12 05:10:21 PM PDT 24
Peak memory 204636 kb
Host smart-09e6907b-a56b-4d10-93fc-1c67c1b41060
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519888613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1519888613
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.185473923
Short name T1640
Test name
Test status
Simulation time 1532870478 ps
CPU time 5.31 seconds
Started Jul 12 05:10:22 PM PDT 24
Finished Jul 12 05:10:28 PM PDT 24
Peak memory 204596 kb
Host smart-f5eab5f9-4e7a-4b37-a76e-ad171d7b54e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185473923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.185473923
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2193346803
Short name T229
Test name
Test status
Simulation time 50571274 ps
CPU time 0.68 seconds
Started Jul 12 05:10:17 PM PDT 24
Finished Jul 12 05:10:18 PM PDT 24
Peak memory 204432 kb
Host smart-583c6915-b752-4622-896c-4a067308a022
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193346803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2193346803
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1799293398
Short name T226
Test name
Test status
Simulation time 31035229 ps
CPU time 0.91 seconds
Started Jul 12 05:10:16 PM PDT 24
Finished Jul 12 05:10:18 PM PDT 24
Peak memory 204500 kb
Host smart-41b161ff-f49e-4551-a739-15ec14833481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799293398 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1799293398
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1182925680
Short name T1623
Test name
Test status
Simulation time 104560883 ps
CPU time 0.79 seconds
Started Jul 12 05:10:21 PM PDT 24
Finished Jul 12 05:10:23 PM PDT 24
Peak memory 204380 kb
Host smart-0291e9e2-4a73-426c-be93-aaa34cde7da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182925680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1182925680
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.889878744
Short name T1572
Test name
Test status
Simulation time 80050905 ps
CPU time 0.68 seconds
Started Jul 12 05:10:17 PM PDT 24
Finished Jul 12 05:10:18 PM PDT 24
Peak memory 204432 kb
Host smart-f4e469f5-cab3-4bfb-9cfa-e352f34f5bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889878744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.889878744
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2322883154
Short name T1676
Test name
Test status
Simulation time 201010775 ps
CPU time 0.89 seconds
Started Jul 12 05:10:23 PM PDT 24
Finished Jul 12 05:10:24 PM PDT 24
Peak memory 204456 kb
Host smart-fa6e98f3-2d51-4dbc-8c0a-dda2db30de0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322883154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2322883154
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.751301789
Short name T1637
Test name
Test status
Simulation time 110695347 ps
CPU time 2.25 seconds
Started Jul 12 05:10:22 PM PDT 24
Finished Jul 12 05:10:25 PM PDT 24
Peak memory 204692 kb
Host smart-ae79b23a-d15a-43a7-9ab4-f9b33f9615cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751301789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.751301789
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3157209908
Short name T278
Test name
Test status
Simulation time 121403996 ps
CPU time 2.25 seconds
Started Jul 12 05:10:18 PM PDT 24
Finished Jul 12 05:10:21 PM PDT 24
Peak memory 204776 kb
Host smart-60fd0061-7041-4f97-94df-7a71efb1057b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157209908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3157209908
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.52722380
Short name T1664
Test name
Test status
Simulation time 33532444 ps
CPU time 0.94 seconds
Started Jul 12 05:10:45 PM PDT 24
Finished Jul 12 05:10:47 PM PDT 24
Peak memory 204444 kb
Host smart-70d495fc-8741-4bcf-bc8b-e8c4f55c9aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52722380 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.52722380
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.304733376
Short name T233
Test name
Test status
Simulation time 17420341 ps
CPU time 0.84 seconds
Started Jul 12 05:10:50 PM PDT 24
Finished Jul 12 05:10:51 PM PDT 24
Peak memory 204468 kb
Host smart-a6560dc6-3f08-47e3-a2bf-0fb4b38089ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304733376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.304733376
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2230908761
Short name T1634
Test name
Test status
Simulation time 38433095 ps
CPU time 0.65 seconds
Started Jul 12 05:10:45 PM PDT 24
Finished Jul 12 05:10:46 PM PDT 24
Peak memory 204424 kb
Host smart-467bf0e9-92e1-47b3-b0e6-b12596a31aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230908761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2230908761
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.683067671
Short name T239
Test name
Test status
Simulation time 20901550 ps
CPU time 0.86 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204352 kb
Host smart-fec6fb3b-1045-4066-bf85-13c4614b2df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683067671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.683067671
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.475862645
Short name T1604
Test name
Test status
Simulation time 339663827 ps
CPU time 1.34 seconds
Started Jul 12 05:10:48 PM PDT 24
Finished Jul 12 05:10:51 PM PDT 24
Peak memory 204656 kb
Host smart-7fefe96c-efd4-4a2d-b848-9c5a80f464fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475862645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.475862645
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2670639377
Short name T187
Test name
Test status
Simulation time 1150038903 ps
CPU time 1.38 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204772 kb
Host smart-f2ea4f7b-8d62-4e33-bbf0-e2a7eb9286df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670639377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2670639377
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3184972794
Short name T1624
Test name
Test status
Simulation time 31127286 ps
CPU time 1.33 seconds
Started Jul 12 05:10:50 PM PDT 24
Finished Jul 12 05:10:52 PM PDT 24
Peak memory 220608 kb
Host smart-19892afb-b939-419c-9c79-b7b5e7b4253c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184972794 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3184972794
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3923358876
Short name T288
Test name
Test status
Simulation time 23317999 ps
CPU time 0.68 seconds
Started Jul 12 05:10:47 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204340 kb
Host smart-ba9497bb-625f-431f-b1f4-f92d53f61852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923358876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3923358876
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2455902954
Short name T240
Test name
Test status
Simulation time 91525746 ps
CPU time 1.14 seconds
Started Jul 12 05:10:48 PM PDT 24
Finished Jul 12 05:10:50 PM PDT 24
Peak memory 204720 kb
Host smart-5b42ba1e-d878-4cb0-b112-47c3dedad0dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455902954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2455902954
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3233997638
Short name T1658
Test name
Test status
Simulation time 168707856 ps
CPU time 2.67 seconds
Started Jul 12 05:10:45 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204752 kb
Host smart-23a48951-f8a3-4508-af18-04300ac35dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233997638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3233997638
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3107743348
Short name T1645
Test name
Test status
Simulation time 190790557 ps
CPU time 1.61 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204664 kb
Host smart-4a1c70ac-29c9-439b-a4bd-829fd915ce85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107743348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3107743348
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.209243649
Short name T115
Test name
Test status
Simulation time 26776920 ps
CPU time 0.89 seconds
Started Jul 12 05:10:47 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204452 kb
Host smart-736069a8-ec57-4a27-a955-444d61f6b740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209243649 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.209243649
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3260045429
Short name T232
Test name
Test status
Simulation time 18777187 ps
CPU time 0.74 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204388 kb
Host smart-c43cf4ee-57c5-4da0-a531-9f7ba0881a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260045429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3260045429
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3381014877
Short name T1646
Test name
Test status
Simulation time 101534262 ps
CPU time 0.65 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204304 kb
Host smart-2ad8fff7-2d4a-40be-9a92-c74c3fa30aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381014877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3381014877
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2840571474
Short name T237
Test name
Test status
Simulation time 38142982 ps
CPU time 0.85 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204576 kb
Host smart-5751283f-9965-4684-85c9-59400988ddae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840571474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2840571474
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.575385073
Short name T1590
Test name
Test status
Simulation time 110393153 ps
CPU time 2.43 seconds
Started Jul 12 05:10:51 PM PDT 24
Finished Jul 12 05:10:54 PM PDT 24
Peak memory 204592 kb
Host smart-f24a7fe5-4dd6-4082-a6b0-68597e2db671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575385073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.575385073
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.140707247
Short name T185
Test name
Test status
Simulation time 37071140 ps
CPU time 0.95 seconds
Started Jul 12 05:10:52 PM PDT 24
Finished Jul 12 05:10:53 PM PDT 24
Peak memory 204480 kb
Host smart-60d5d3ee-122c-46e1-bdde-44c120ce576c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140707247 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.140707247
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3080022657
Short name T1592
Test name
Test status
Simulation time 81329856 ps
CPU time 0.7 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:47 PM PDT 24
Peak memory 204436 kb
Host smart-89d3641a-69b4-45b9-a39d-feedb9629af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080022657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3080022657
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.4040490234
Short name T1673
Test name
Test status
Simulation time 26756913 ps
CPU time 0.66 seconds
Started Jul 12 05:10:51 PM PDT 24
Finished Jul 12 05:10:53 PM PDT 24
Peak memory 204328 kb
Host smart-9fc4de6f-1e83-41ae-acfb-ae221869dc63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040490234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.4040490234
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3061141138
Short name T113
Test name
Test status
Simulation time 36129128 ps
CPU time 0.85 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 204544 kb
Host smart-7c0bcfc3-037e-4563-a764-328b71c6856b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061141138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3061141138
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2099964025
Short name T1589
Test name
Test status
Simulation time 35683769 ps
CPU time 1.67 seconds
Started Jul 12 05:10:44 PM PDT 24
Finished Jul 12 05:10:47 PM PDT 24
Peak memory 204724 kb
Host smart-97d12384-de54-4d1f-a094-c11e9322d0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099964025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2099964025
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3617181972
Short name T210
Test name
Test status
Simulation time 72184936 ps
CPU time 1.39 seconds
Started Jul 12 05:10:50 PM PDT 24
Finished Jul 12 05:10:52 PM PDT 24
Peak memory 204756 kb
Host smart-cd404738-0a1b-41ab-b8bc-242bbe5da5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617181972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3617181972
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.10560352
Short name T1601
Test name
Test status
Simulation time 209699404 ps
CPU time 1.47 seconds
Started Jul 12 05:10:55 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 204736 kb
Host smart-c23261c2-2b12-4fd5-9d85-477c233afcc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10560352 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.10560352
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4033385987
Short name T1675
Test name
Test status
Simulation time 2246034145 ps
CPU time 4.25 seconds
Started Jul 12 05:10:45 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204448 kb
Host smart-7f482f92-4567-4497-98a8-654b4f3dc92c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033385987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4033385987
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.4090845714
Short name T1663
Test name
Test status
Simulation time 20421378 ps
CPU time 0.68 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:47 PM PDT 24
Peak memory 204420 kb
Host smart-b807587d-44d4-4ed6-98e8-4266ff19206d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090845714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4090845714
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.466800919
Short name T1652
Test name
Test status
Simulation time 437069029 ps
CPU time 1.09 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 204696 kb
Host smart-ed726d1a-e130-4535-87e4-ac6e7246b264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466800919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.466800919
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3532425087
Short name T1655
Test name
Test status
Simulation time 51767710 ps
CPU time 2.33 seconds
Started Jul 12 05:10:46 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 212832 kb
Host smart-c9e0f28b-1df8-4149-a1be-a4b5e9c4ee1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532425087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3532425087
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3372993752
Short name T212
Test name
Test status
Simulation time 74789138 ps
CPU time 1.37 seconds
Started Jul 12 05:10:51 PM PDT 24
Finished Jul 12 05:10:53 PM PDT 24
Peak memory 204592 kb
Host smart-20ef3c8d-6b88-4b19-a1b4-3d89fae06113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372993752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3372993752
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.739061200
Short name T1607
Test name
Test status
Simulation time 164379283 ps
CPU time 0.95 seconds
Started Jul 12 05:10:57 PM PDT 24
Finished Jul 12 05:10:59 PM PDT 24
Peak memory 204584 kb
Host smart-d00a9a69-2e5b-48b1-b462-2af51aff43b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739061200 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.739061200
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3064870984
Short name T1660
Test name
Test status
Simulation time 32038991 ps
CPU time 0.69 seconds
Started Jul 12 05:10:58 PM PDT 24
Finished Jul 12 05:11:00 PM PDT 24
Peak memory 204680 kb
Host smart-c5295cb4-a86e-460e-9407-dff7141be6cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064870984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3064870984
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2437504661
Short name T1621
Test name
Test status
Simulation time 55124688 ps
CPU time 0.68 seconds
Started Jul 12 05:10:55 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 204452 kb
Host smart-33352029-90fa-4cc7-a253-bb9435b5089e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437504661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2437504661
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.213469903
Short name T1648
Test name
Test status
Simulation time 441315236 ps
CPU time 1.09 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 204584 kb
Host smart-ce504f19-0db6-4adf-b8fa-26539d04c233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213469903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.213469903
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1937314964
Short name T1622
Test name
Test status
Simulation time 48493247 ps
CPU time 1.36 seconds
Started Jul 12 05:10:57 PM PDT 24
Finished Jul 12 05:10:59 PM PDT 24
Peak memory 204780 kb
Host smart-b10473a4-ca3d-4bd8-92b9-5a8801729c39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937314964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1937314964
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.329234468
Short name T1644
Test name
Test status
Simulation time 210032519 ps
CPU time 1.35 seconds
Started Jul 12 05:10:56 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 204788 kb
Host smart-c9374302-4297-417b-baa1-b92c40ce9001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329234468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.329234468
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2675842010
Short name T131
Test name
Test status
Simulation time 44747677 ps
CPU time 0.97 seconds
Started Jul 12 05:10:55 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 204500 kb
Host smart-f4759e8e-451e-410e-9415-f973283d45e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675842010 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2675842010
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3311700247
Short name T1657
Test name
Test status
Simulation time 19910800 ps
CPU time 0.68 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 204400 kb
Host smart-16b06fea-3fc6-4e15-ae0a-db8ad1716c29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311700247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3311700247
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3133930172
Short name T1630
Test name
Test status
Simulation time 18456636 ps
CPU time 0.66 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204424 kb
Host smart-0af65a31-7e11-41e0-acef-73e1e230a59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133930172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3133930172
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.933114945
Short name T1670
Test name
Test status
Simulation time 188407668 ps
CPU time 1.1 seconds
Started Jul 12 05:10:57 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 204824 kb
Host smart-471cd28e-e41b-4b91-97d1-357f8ef26d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933114945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.933114945
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1880588529
Short name T206
Test name
Test status
Simulation time 38449844 ps
CPU time 1.75 seconds
Started Jul 12 05:10:53 PM PDT 24
Finished Jul 12 05:10:55 PM PDT 24
Peak memory 204668 kb
Host smart-96612688-d100-497e-ba41-6f387ab037c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880588529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1880588529
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.591808049
Short name T1672
Test name
Test status
Simulation time 122621851 ps
CPU time 0.95 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204608 kb
Host smart-f885df4b-c0d8-4069-b7e1-dcd18ca42793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591808049 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.591808049
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4123068935
Short name T217
Test name
Test status
Simulation time 43769878 ps
CPU time 0.74 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:55 PM PDT 24
Peak memory 204340 kb
Host smart-6194389a-346c-417c-a325-78c38b9ca915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123068935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4123068935
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.519343653
Short name T1583
Test name
Test status
Simulation time 43400596 ps
CPU time 0.67 seconds
Started Jul 12 05:10:57 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 204432 kb
Host smart-7208d2bf-daee-4a13-b975-eb68376a100c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519343653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.519343653
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3094506644
Short name T164
Test name
Test status
Simulation time 65151238 ps
CPU time 1.19 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204724 kb
Host smart-85076b5e-8898-4f1e-aab2-f7816760322c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094506644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3094506644
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1331133678
Short name T205
Test name
Test status
Simulation time 250980182 ps
CPU time 1.89 seconds
Started Jul 12 05:10:54 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 204784 kb
Host smart-46ef5c34-5160-4a2d-b605-94053dfadaec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331133678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1331133678
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3275772457
Short name T219
Test name
Test status
Simulation time 152946017 ps
CPU time 2.44 seconds
Started Jul 12 05:10:55 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 204708 kb
Host smart-7c5ce704-8b1d-4b05-999a-e244d665e36f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275772457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3275772457
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.367961325
Short name T1626
Test name
Test status
Simulation time 73335536 ps
CPU time 1.11 seconds
Started Jul 12 05:11:01 PM PDT 24
Finished Jul 12 05:11:02 PM PDT 24
Peak memory 204748 kb
Host smart-9cfc3e00-5716-48c2-9354-3dcb592bed1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367961325 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.367961325
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.134841831
Short name T1669
Test name
Test status
Simulation time 70760418 ps
CPU time 0.75 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204400 kb
Host smart-686002c9-4c6d-4a77-85f4-81849c0e2977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134841831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.134841831
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3730011696
Short name T1586
Test name
Test status
Simulation time 43293666 ps
CPU time 0.68 seconds
Started Jul 12 05:11:05 PM PDT 24
Finished Jul 12 05:11:07 PM PDT 24
Peak memory 204308 kb
Host smart-4a0348fe-ffbf-4f63-b934-c9d680d8e53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730011696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3730011696
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2628521881
Short name T1661
Test name
Test status
Simulation time 73892718 ps
CPU time 0.94 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204440 kb
Host smart-48fd2d5f-3144-4183-b76f-380da6ed6932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628521881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2628521881
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1643657462
Short name T116
Test name
Test status
Simulation time 64341231 ps
CPU time 1.5 seconds
Started Jul 12 05:11:08 PM PDT 24
Finished Jul 12 05:11:10 PM PDT 24
Peak memory 204688 kb
Host smart-35566793-67e8-4878-8c0d-dfa19987382e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643657462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1643657462
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4000522401
Short name T1662
Test name
Test status
Simulation time 24840145 ps
CPU time 1.03 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:05 PM PDT 24
Peak memory 204480 kb
Host smart-6d01fd6b-88da-4c72-bf92-2e938582002e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000522401 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4000522401
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2450664313
Short name T231
Test name
Test status
Simulation time 29689156 ps
CPU time 0.78 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204368 kb
Host smart-2b3343c6-fa8f-441e-8c5f-5a79d175bc8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450664313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2450664313
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1085153606
Short name T135
Test name
Test status
Simulation time 31838040 ps
CPU time 0.65 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:03 PM PDT 24
Peak memory 204260 kb
Host smart-b93ebc33-9233-4fac-b4e7-46484eb75c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085153606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1085153606
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2197431340
Short name T1614
Test name
Test status
Simulation time 276129874 ps
CPU time 1.06 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204644 kb
Host smart-9e28f4b1-7f02-45b7-85be-ac89bed4f8a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197431340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2197431340
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2577539165
Short name T1619
Test name
Test status
Simulation time 154379639 ps
CPU time 2.17 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204652 kb
Host smart-1cdca9a8-8ca9-4281-a961-8cae1af2e9c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577539165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2577539165
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.17417960
Short name T1611
Test name
Test status
Simulation time 309107287 ps
CPU time 2.07 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:08 PM PDT 24
Peak memory 204924 kb
Host smart-4cefc3a4-c96a-4df8-9489-c481dacf04db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.17417960
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2844975581
Short name T114
Test name
Test status
Simulation time 124513877 ps
CPU time 1.24 seconds
Started Jul 12 05:10:25 PM PDT 24
Finished Jul 12 05:10:26 PM PDT 24
Peak memory 204532 kb
Host smart-18e4a8a0-1e11-4147-a6fe-ae467fc40c73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844975581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2844975581
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3742110578
Short name T1631
Test name
Test status
Simulation time 1452397656 ps
CPU time 5.2 seconds
Started Jul 12 05:10:26 PM PDT 24
Finished Jul 12 05:10:32 PM PDT 24
Peak memory 204540 kb
Host smart-2982f0b8-2f24-406e-bfaa-7f1d7db77de2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742110578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3742110578
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2092456236
Short name T110
Test name
Test status
Simulation time 43861912 ps
CPU time 0.76 seconds
Started Jul 12 05:10:17 PM PDT 24
Finished Jul 12 05:10:18 PM PDT 24
Peak memory 204260 kb
Host smart-f960406e-c335-43b4-8a94-11a5801a5317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092456236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2092456236
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3411208651
Short name T1632
Test name
Test status
Simulation time 24531944 ps
CPU time 0.77 seconds
Started Jul 12 05:10:23 PM PDT 24
Finished Jul 12 05:10:24 PM PDT 24
Peak memory 204524 kb
Host smart-59129b5d-62a9-44f3-a8aa-bc11114a6e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411208651 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3411208651
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2449714201
Short name T1633
Test name
Test status
Simulation time 44987447 ps
CPU time 0.67 seconds
Started Jul 12 05:10:18 PM PDT 24
Finished Jul 12 05:10:19 PM PDT 24
Peak memory 204464 kb
Host smart-148911f1-ebe8-47a3-9316-2159329f919c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449714201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2449714201
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1217923074
Short name T1643
Test name
Test status
Simulation time 228576815 ps
CPU time 0.87 seconds
Started Jul 12 05:10:25 PM PDT 24
Finished Jul 12 05:10:27 PM PDT 24
Peak memory 204512 kb
Host smart-91f9255f-9901-405b-93de-18d5d2b0f68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217923074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1217923074
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.160731281
Short name T1608
Test name
Test status
Simulation time 102295836 ps
CPU time 1.28 seconds
Started Jul 12 05:10:22 PM PDT 24
Finished Jul 12 05:10:24 PM PDT 24
Peak memory 204672 kb
Host smart-d0cad180-7d02-4078-9177-0ed6ab0aa5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160731281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.160731281
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2256395334
Short name T211
Test name
Test status
Simulation time 254901202 ps
CPU time 1.44 seconds
Started Jul 12 05:10:22 PM PDT 24
Finished Jul 12 05:10:24 PM PDT 24
Peak memory 204756 kb
Host smart-e140b2fe-022d-43b5-8931-ee19aff126f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256395334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2256395334
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2996885382
Short name T1585
Test name
Test status
Simulation time 31314113 ps
CPU time 0.69 seconds
Started Jul 12 05:11:07 PM PDT 24
Finished Jul 12 05:11:08 PM PDT 24
Peak memory 204408 kb
Host smart-125c07ad-5917-4a9b-b431-ca739288031a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996885382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2996885382
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.599121758
Short name T1625
Test name
Test status
Simulation time 192922703 ps
CPU time 0.69 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204424 kb
Host smart-73781d7a-520f-4041-a650-8edfc040513a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599121758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.599121758
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2247602815
Short name T1635
Test name
Test status
Simulation time 15184428 ps
CPU time 0.68 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:05 PM PDT 24
Peak memory 204440 kb
Host smart-21ed3192-acb4-4ba8-9357-33e936a9f09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247602815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2247602815
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.319023319
Short name T294
Test name
Test status
Simulation time 35812161 ps
CPU time 0.69 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204468 kb
Host smart-9ef3beb4-3424-43bd-a58f-5ca21bf7c941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319023319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.319023319
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.368205437
Short name T1603
Test name
Test status
Simulation time 34891395 ps
CPU time 0.65 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:07 PM PDT 24
Peak memory 204304 kb
Host smart-2b4b0f98-0e55-49c9-ba46-f151c40cf820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368205437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.368205437
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2991086251
Short name T1627
Test name
Test status
Simulation time 17616574 ps
CPU time 0.7 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204432 kb
Host smart-3f5d4341-ddc4-4ff8-a7d3-8979ec67bbae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991086251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2991086251
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1951576730
Short name T1641
Test name
Test status
Simulation time 15636933 ps
CPU time 0.77 seconds
Started Jul 12 05:11:01 PM PDT 24
Finished Jul 12 05:11:03 PM PDT 24
Peak memory 204364 kb
Host smart-f52a1c87-147b-4217-af9e-a58da84362ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951576730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1951576730
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3545775654
Short name T290
Test name
Test status
Simulation time 39835481 ps
CPU time 0.66 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:07 PM PDT 24
Peak memory 204412 kb
Host smart-3b055d10-161c-412b-a02e-a52d3d898dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545775654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3545775654
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.414339591
Short name T1597
Test name
Test status
Simulation time 29232981 ps
CPU time 0.67 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204408 kb
Host smart-1c65421a-4f00-49e5-a9bd-d5cbc4fda142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414339591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.414339591
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3446481937
Short name T1595
Test name
Test status
Simulation time 17821256 ps
CPU time 0.67 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204368 kb
Host smart-d0d8f26f-262c-42d7-83ba-083ba9050b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446481937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3446481937
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.605323049
Short name T1647
Test name
Test status
Simulation time 111757080 ps
CPU time 2 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:37 PM PDT 24
Peak memory 204592 kb
Host smart-a041c844-2f03-4550-8fb3-672a5ac6dbf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605323049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.605323049
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.58122573
Short name T109
Test name
Test status
Simulation time 1103433753 ps
CPU time 2.93 seconds
Started Jul 12 05:10:25 PM PDT 24
Finished Jul 12 05:10:29 PM PDT 24
Peak memory 204672 kb
Host smart-cb6f2a9f-2d72-43d8-999e-1a82b8fbd52e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58122573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.58122573
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.229870252
Short name T1574
Test name
Test status
Simulation time 30398664 ps
CPU time 0.67 seconds
Started Jul 12 05:10:25 PM PDT 24
Finished Jul 12 05:10:26 PM PDT 24
Peak memory 204424 kb
Host smart-0d5a6d67-bac9-45a8-af79-9569f83c11e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229870252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.229870252
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2105359060
Short name T1659
Test name
Test status
Simulation time 21096372 ps
CPU time 0.82 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 204448 kb
Host smart-21363300-c228-4c58-8642-3f3d49f5a671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105359060 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2105359060
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.4075483330
Short name T1613
Test name
Test status
Simulation time 32707574 ps
CPU time 0.68 seconds
Started Jul 12 05:10:28 PM PDT 24
Finished Jul 12 05:10:29 PM PDT 24
Peak memory 204368 kb
Host smart-47993ca9-e8e0-4cd8-a31c-95afad2957fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075483330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.4075483330
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2105737288
Short name T1642
Test name
Test status
Simulation time 52262631 ps
CPU time 0.68 seconds
Started Jul 12 05:10:29 PM PDT 24
Finished Jul 12 05:10:30 PM PDT 24
Peak memory 204436 kb
Host smart-0a3e7f01-4b80-4dd3-a66b-e1ee2ba136f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105737288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2105737288
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.426986770
Short name T1598
Test name
Test status
Simulation time 21672184 ps
CPU time 0.8 seconds
Started Jul 12 05:10:24 PM PDT 24
Finished Jul 12 05:10:25 PM PDT 24
Peak memory 204384 kb
Host smart-0aa6f6d5-c1ac-4c07-be38-bfab8618a381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426986770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.426986770
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3006891252
Short name T1650
Test name
Test status
Simulation time 276014194 ps
CPU time 2.33 seconds
Started Jul 12 05:10:27 PM PDT 24
Finished Jul 12 05:10:29 PM PDT 24
Peak memory 204740 kb
Host smart-a7d4fb8d-77da-4469-ad23-c1a584dd1906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006891252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3006891252
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.638313719
Short name T111
Test name
Test status
Simulation time 83699421 ps
CPU time 1.44 seconds
Started Jul 12 05:10:26 PM PDT 24
Finished Jul 12 05:10:28 PM PDT 24
Peak memory 204692 kb
Host smart-2ec2af2e-7f5c-48b1-8b28-8a237451c761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638313719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.638313719
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3507769835
Short name T1653
Test name
Test status
Simulation time 44065894 ps
CPU time 0.69 seconds
Started Jul 12 05:11:02 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 204352 kb
Host smart-56f41060-9587-418f-a6ab-7a86cf83e385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507769835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3507769835
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2535919063
Short name T1575
Test name
Test status
Simulation time 17497555 ps
CPU time 0.7 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204432 kb
Host smart-fb9b74f1-bdce-429c-8246-9c632ed7dba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535919063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2535919063
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.42187627
Short name T1639
Test name
Test status
Simulation time 17934884 ps
CPU time 0.67 seconds
Started Jul 12 05:11:03 PM PDT 24
Finished Jul 12 05:11:05 PM PDT 24
Peak memory 204432 kb
Host smart-e04e910f-99ea-486e-9cfb-d490d9bfabea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.42187627
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1369189032
Short name T1581
Test name
Test status
Simulation time 60776721 ps
CPU time 0.67 seconds
Started Jul 12 05:11:05 PM PDT 24
Finished Jul 12 05:11:07 PM PDT 24
Peak memory 204424 kb
Host smart-162bc47f-314d-4b92-b16c-54fbf904248a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369189032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1369189032
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3073849218
Short name T1579
Test name
Test status
Simulation time 47220623 ps
CPU time 0.67 seconds
Started Jul 12 05:11:11 PM PDT 24
Finished Jul 12 05:11:13 PM PDT 24
Peak memory 204452 kb
Host smart-7b68c95f-337a-4338-8a60-93a80285341b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073849218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3073849218
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3300955037
Short name T1571
Test name
Test status
Simulation time 14654022 ps
CPU time 0.7 seconds
Started Jul 12 05:11:10 PM PDT 24
Finished Jul 12 05:11:12 PM PDT 24
Peak memory 204464 kb
Host smart-ee9b9d04-44b6-4efa-a21f-a5d7dccb48d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300955037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3300955037
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.859238842
Short name T1596
Test name
Test status
Simulation time 25043917 ps
CPU time 0.68 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204404 kb
Host smart-61004acc-60b1-4c9f-9a1b-7f29402b06ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859238842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.859238842
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1684570745
Short name T1651
Test name
Test status
Simulation time 51122423 ps
CPU time 0.68 seconds
Started Jul 12 05:11:04 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 204404 kb
Host smart-0fbe79e3-854c-489f-a696-b7ec245d933f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684570745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1684570745
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2018003235
Short name T1636
Test name
Test status
Simulation time 27349968 ps
CPU time 0.66 seconds
Started Jul 12 05:11:15 PM PDT 24
Finished Jul 12 05:11:16 PM PDT 24
Peak memory 204456 kb
Host smart-39cbb529-a4b1-45e8-b818-a6b49df485df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018003235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2018003235
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2760642421
Short name T1576
Test name
Test status
Simulation time 47881614 ps
CPU time 0.69 seconds
Started Jul 12 05:11:11 PM PDT 24
Finished Jul 12 05:11:12 PM PDT 24
Peak memory 204328 kb
Host smart-da021722-e461-4b10-aae4-d41a2ea2599c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760642421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2760642421
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3360140733
Short name T1606
Test name
Test status
Simulation time 229757203 ps
CPU time 1.89 seconds
Started Jul 12 05:10:37 PM PDT 24
Finished Jul 12 05:10:40 PM PDT 24
Peak memory 204704 kb
Host smart-ec720698-15b7-4dc9-a545-cc38b18c624b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360140733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3360140733
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.790480878
Short name T235
Test name
Test status
Simulation time 225524160 ps
CPU time 4.5 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204548 kb
Host smart-6f3830be-9b1d-4d2f-9c9e-3cd95cbf2301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790480878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.790480878
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1231749116
Short name T1573
Test name
Test status
Simulation time 26786493 ps
CPU time 0.76 seconds
Started Jul 12 05:10:36 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204432 kb
Host smart-fc48ddea-aa1b-48e7-9ce3-063ea073b999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231749116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1231749116
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1825654482
Short name T107
Test name
Test status
Simulation time 77286719 ps
CPU time 0.85 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 204592 kb
Host smart-503c5908-3662-4432-b719-89b6f720b22a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825654482 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1825654482
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1935074767
Short name T158
Test name
Test status
Simulation time 19413521 ps
CPU time 0.71 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 204632 kb
Host smart-4a56f43d-d351-486d-8009-45945524d356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935074767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1935074767
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.769410664
Short name T1609
Test name
Test status
Simulation time 104175219 ps
CPU time 0.66 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:33 PM PDT 24
Peak memory 204428 kb
Host smart-5445e3f2-9ff5-4104-b91d-273d111ed7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769410664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.769410664
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1074372484
Short name T236
Test name
Test status
Simulation time 30399043 ps
CPU time 1.11 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 204712 kb
Host smart-87c3d295-b3dd-437b-b2c9-9575c5fbd623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074372484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1074372484
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1230011205
Short name T1629
Test name
Test status
Simulation time 84934795 ps
CPU time 2.05 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204644 kb
Host smart-840f5f98-f648-4f52-92b5-4ed5506d910c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230011205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1230011205
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1916421474
Short name T218
Test name
Test status
Simulation time 258772861 ps
CPU time 2.07 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:34 PM PDT 24
Peak memory 204604 kb
Host smart-52b4057f-d58f-40a4-9810-aea51c1e0173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916421474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1916421474
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2126684798
Short name T1582
Test name
Test status
Simulation time 17920631 ps
CPU time 0.67 seconds
Started Jul 12 05:11:11 PM PDT 24
Finished Jul 12 05:11:12 PM PDT 24
Peak memory 204436 kb
Host smart-ffa51f3b-320f-459c-a7d0-3c4bc6a2e8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126684798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2126684798
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.114365063
Short name T1594
Test name
Test status
Simulation time 49845460 ps
CPU time 0.67 seconds
Started Jul 12 05:11:09 PM PDT 24
Finished Jul 12 05:11:10 PM PDT 24
Peak memory 204404 kb
Host smart-c58d0ede-e27a-436f-af6d-6216b07319aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114365063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.114365063
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1398602423
Short name T1616
Test name
Test status
Simulation time 21184033 ps
CPU time 0.65 seconds
Started Jul 12 05:11:09 PM PDT 24
Finished Jul 12 05:11:11 PM PDT 24
Peak memory 204412 kb
Host smart-4f354b1d-5119-4f78-9fe6-afd07445f345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398602423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1398602423
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1807050665
Short name T1578
Test name
Test status
Simulation time 46561750 ps
CPU time 0.68 seconds
Started Jul 12 05:11:13 PM PDT 24
Finished Jul 12 05:11:14 PM PDT 24
Peak memory 204340 kb
Host smart-b38110be-1ccd-4a92-9281-2f1a9a0bd038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807050665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1807050665
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2214387895
Short name T287
Test name
Test status
Simulation time 15870771 ps
CPU time 0.68 seconds
Started Jul 12 05:11:14 PM PDT 24
Finished Jul 12 05:11:15 PM PDT 24
Peak memory 204428 kb
Host smart-942e8f91-c14c-4b1e-8098-f06cca092569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214387895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2214387895
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.4125056818
Short name T1671
Test name
Test status
Simulation time 20526849 ps
CPU time 0.68 seconds
Started Jul 12 05:11:11 PM PDT 24
Finished Jul 12 05:11:13 PM PDT 24
Peak memory 204348 kb
Host smart-1951229e-cd6a-4b98-b802-ea70b6f43952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125056818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.4125056818
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2678511602
Short name T1667
Test name
Test status
Simulation time 28202436 ps
CPU time 0.65 seconds
Started Jul 12 05:11:12 PM PDT 24
Finished Jul 12 05:11:14 PM PDT 24
Peak memory 204304 kb
Host smart-cbb938d5-98aa-4bd7-b6a5-bb146b049580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678511602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2678511602
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1150939573
Short name T1668
Test name
Test status
Simulation time 145587744 ps
CPU time 0.66 seconds
Started Jul 12 05:11:10 PM PDT 24
Finished Jul 12 05:11:12 PM PDT 24
Peak memory 204328 kb
Host smart-a3f51753-1c50-452b-a603-326951f8e03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150939573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1150939573
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1596270470
Short name T1618
Test name
Test status
Simulation time 63643087 ps
CPU time 0.67 seconds
Started Jul 12 05:11:10 PM PDT 24
Finished Jul 12 05:11:11 PM PDT 24
Peak memory 204348 kb
Host smart-d54298e7-62d2-4748-bac0-18d699a81e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596270470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1596270470
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1447253311
Short name T1649
Test name
Test status
Simulation time 19879166 ps
CPU time 0.69 seconds
Started Jul 12 05:11:12 PM PDT 24
Finished Jul 12 05:11:14 PM PDT 24
Peak memory 204432 kb
Host smart-e5520ab5-a952-496e-8d99-fd3687d7a338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447253311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1447253311
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3057087394
Short name T202
Test name
Test status
Simulation time 44033592 ps
CPU time 1.15 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 204836 kb
Host smart-704a1513-bf58-44cb-bcf8-55ec5ac81c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057087394 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3057087394
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2722873702
Short name T1674
Test name
Test status
Simulation time 20537168 ps
CPU time 0.71 seconds
Started Jul 12 05:10:35 PM PDT 24
Finished Jul 12 05:10:37 PM PDT 24
Peak memory 204504 kb
Host smart-912f6096-e3bc-4b6c-8aba-1c50191e275a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722873702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2722873702
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.4169901390
Short name T1587
Test name
Test status
Simulation time 16331359 ps
CPU time 0.63 seconds
Started Jul 12 05:10:34 PM PDT 24
Finished Jul 12 05:10:37 PM PDT 24
Peak memory 204272 kb
Host smart-39cc02ac-946b-42f6-a21e-704b9cdfa3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169901390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.4169901390
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3008208307
Short name T1610
Test name
Test status
Simulation time 19846041 ps
CPU time 0.83 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 204700 kb
Host smart-f71cf515-11c4-4aef-97bf-5391c9e0ae88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008208307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3008208307
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3068945033
Short name T1584
Test name
Test status
Simulation time 104349945 ps
CPU time 0.88 seconds
Started Jul 12 05:10:37 PM PDT 24
Finished Jul 12 05:10:39 PM PDT 24
Peak memory 204512 kb
Host smart-e6084d4a-7953-44d9-a3aa-50bda9bcad82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068945033 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3068945033
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.499154135
Short name T1617
Test name
Test status
Simulation time 118464949 ps
CPU time 0.75 seconds
Started Jul 12 05:10:34 PM PDT 24
Finished Jul 12 05:10:37 PM PDT 24
Peak memory 204352 kb
Host smart-278c2eb5-9591-4be0-b554-d74d6d63c053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499154135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.499154135
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1078769476
Short name T1628
Test name
Test status
Simulation time 70899571 ps
CPU time 0.68 seconds
Started Jul 12 05:10:33 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 204424 kb
Host smart-7b104174-0681-4d69-87d7-bbd83c093d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078769476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1078769476
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3527103409
Short name T238
Test name
Test status
Simulation time 32448205 ps
CPU time 1.11 seconds
Started Jul 12 05:10:35 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204972 kb
Host smart-57f8cbf7-36d3-4af2-8f24-1f089fc94ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527103409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3527103409
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2419480258
Short name T1602
Test name
Test status
Simulation time 81818893 ps
CPU time 2.39 seconds
Started Jul 12 05:10:32 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 204748 kb
Host smart-3ace4f4c-96c2-4dd6-a939-58c72cbbb518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419480258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2419480258
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4128991539
Short name T186
Test name
Test status
Simulation time 168782702 ps
CPU time 1.34 seconds
Started Jul 12 05:10:35 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204564 kb
Host smart-cfa18571-8a73-4306-b0ed-5d72e9cbe733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128991539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4128991539
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1476976021
Short name T1620
Test name
Test status
Simulation time 27286482 ps
CPU time 1.24 seconds
Started Jul 12 05:10:40 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 212992 kb
Host smart-7d5257e3-ef19-484a-8591-232ae1f7228e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476976021 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1476976021
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2804577129
Short name T112
Test name
Test status
Simulation time 142256090 ps
CPU time 0.73 seconds
Started Jul 12 05:10:44 PM PDT 24
Finished Jul 12 05:10:46 PM PDT 24
Peak memory 204412 kb
Host smart-50d01eaf-2599-4700-8146-e42808b5e167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804577129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2804577129
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1596472499
Short name T1580
Test name
Test status
Simulation time 23387352 ps
CPU time 0.66 seconds
Started Jul 12 05:10:43 PM PDT 24
Finished Jul 12 05:10:44 PM PDT 24
Peak memory 204436 kb
Host smart-5a16f578-dc22-4bc5-b149-eee52647f6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596472499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1596472499
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4026730888
Short name T1665
Test name
Test status
Simulation time 106324514 ps
CPU time 0.88 seconds
Started Jul 12 05:10:47 PM PDT 24
Finished Jul 12 05:10:49 PM PDT 24
Peak memory 204408 kb
Host smart-1e36d581-2591-4b40-9fff-8a77e899ca87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026730888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.4026730888
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1902560090
Short name T1577
Test name
Test status
Simulation time 352043791 ps
CPU time 2.02 seconds
Started Jul 12 05:10:34 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 204736 kb
Host smart-4e2c3403-200c-4f2b-aa9f-bcb75f310102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902560090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1902560090
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1948831108
Short name T1612
Test name
Test status
Simulation time 231758961 ps
CPU time 1.06 seconds
Started Jul 12 05:10:40 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 204572 kb
Host smart-7c8d7342-6bb0-4563-822c-e603ad2f3b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948831108 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1948831108
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1364885035
Short name T1605
Test name
Test status
Simulation time 16956062 ps
CPU time 0.8 seconds
Started Jul 12 05:10:40 PM PDT 24
Finished Jul 12 05:10:41 PM PDT 24
Peak memory 204452 kb
Host smart-9c7ee3d6-a543-4c12-aba9-20a2796139d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364885035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1364885035
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.640574296
Short name T134
Test name
Test status
Simulation time 160508354 ps
CPU time 0.66 seconds
Started Jul 12 05:10:42 PM PDT 24
Finished Jul 12 05:10:43 PM PDT 24
Peak memory 204408 kb
Host smart-63efa905-5617-4d2c-8b1a-73e0101227d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640574296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.640574296
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.822243425
Short name T1599
Test name
Test status
Simulation time 171040160 ps
CPU time 1.09 seconds
Started Jul 12 05:10:43 PM PDT 24
Finished Jul 12 05:10:44 PM PDT 24
Peak memory 204576 kb
Host smart-123dac84-4c7a-43b3-9447-6b3ec400a0fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822243425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.822243425
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3131932257
Short name T208
Test name
Test status
Simulation time 59322609 ps
CPU time 0.96 seconds
Started Jul 12 05:10:42 PM PDT 24
Finished Jul 12 05:10:44 PM PDT 24
Peak memory 204456 kb
Host smart-0abdd854-ee57-450e-9e50-975ed1abff76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131932257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3131932257
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.442666200
Short name T209
Test name
Test status
Simulation time 130045606 ps
CPU time 2.12 seconds
Started Jul 12 05:10:42 PM PDT 24
Finished Jul 12 05:10:45 PM PDT 24
Peak memory 204752 kb
Host smart-91904d67-9e0a-49cd-b0cd-7dc91887b1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442666200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.442666200
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3233530433
Short name T1588
Test name
Test status
Simulation time 80079823 ps
CPU time 0.87 seconds
Started Jul 12 05:10:48 PM PDT 24
Finished Jul 12 05:10:50 PM PDT 24
Peak memory 204452 kb
Host smart-308deaf9-f8dd-47dc-ac01-d8cc2bb39b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233530433 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3233530433
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2197057030
Short name T130
Test name
Test status
Simulation time 23778980 ps
CPU time 0.74 seconds
Started Jul 12 05:10:41 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 204288 kb
Host smart-de73c1f6-02f0-442e-9e23-e572764ea77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197057030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2197057030
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3653402167
Short name T1666
Test name
Test status
Simulation time 41317937 ps
CPU time 0.67 seconds
Started Jul 12 05:10:41 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 204320 kb
Host smart-1ebccac7-e8c5-4f31-8786-d5c9aaa6d7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653402167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3653402167
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.377032928
Short name T1656
Test name
Test status
Simulation time 161833668 ps
CPU time 0.9 seconds
Started Jul 12 05:10:49 PM PDT 24
Finished Jul 12 05:10:50 PM PDT 24
Peak memory 204484 kb
Host smart-fb78f8cc-6ccf-41c9-984e-9527dfab5e8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377032928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.377032928
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4270930016
Short name T1615
Test name
Test status
Simulation time 100947522 ps
CPU time 1.95 seconds
Started Jul 12 05:10:40 PM PDT 24
Finished Jul 12 05:10:43 PM PDT 24
Peak memory 212832 kb
Host smart-1930fb45-27a9-4827-932b-b3029bd87c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270930016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4270930016
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.970539160
Short name T216
Test name
Test status
Simulation time 579708017 ps
CPU time 2.3 seconds
Started Jul 12 05:10:38 PM PDT 24
Finished Jul 12 05:10:41 PM PDT 24
Peak memory 204732 kb
Host smart-aba0991d-2fcd-4b28-a1dd-dd8c18af0608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970539160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.970539160
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2964319731
Short name T1015
Test name
Test status
Simulation time 176566908 ps
CPU time 2.69 seconds
Started Jul 12 05:17:58 PM PDT 24
Finished Jul 12 05:18:02 PM PDT 24
Peak memory 231856 kb
Host smart-9d889c1e-a92b-46e7-a819-0eb31fb40d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964319731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2964319731
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2819193535
Short name T332
Test name
Test status
Simulation time 868734385 ps
CPU time 22.61 seconds
Started Jul 12 05:17:54 PM PDT 24
Finished Jul 12 05:18:17 PM PDT 24
Peak memory 291840 kb
Host smart-0fe5d939-e4e5-455c-95cc-79152831d9f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819193535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2819193535
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1875654113
Short name T658
Test name
Test status
Simulation time 2660318226 ps
CPU time 75.69 seconds
Started Jul 12 05:17:55 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 706456 kb
Host smart-13f105e4-91ad-498c-865f-3f75874d394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875654113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1875654113
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.4145791844
Short name T631
Test name
Test status
Simulation time 9688011356 ps
CPU time 120.8 seconds
Started Jul 12 05:17:55 PM PDT 24
Finished Jul 12 05:19:57 PM PDT 24
Peak memory 581740 kb
Host smart-35e75c4e-cea7-4d20-8998-8f11ead2f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145791844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.4145791844
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3913009713
Short name T1335
Test name
Test status
Simulation time 118960346 ps
CPU time 1.08 seconds
Started Jul 12 05:18:00 PM PDT 24
Finished Jul 12 05:18:01 PM PDT 24
Peak memory 205268 kb
Host smart-3693cd96-23a7-45f3-9283-bf5fe8adc05a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913009713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3913009713
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3586817980
Short name T1247
Test name
Test status
Simulation time 180083930 ps
CPU time 4.43 seconds
Started Jul 12 05:17:55 PM PDT 24
Finished Jul 12 05:18:00 PM PDT 24
Peak memory 235204 kb
Host smart-388fcc93-5c2e-4c7b-b9b5-b56d8317f1b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586817980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3586817980
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.198834476
Short name T1044
Test name
Test status
Simulation time 8085594012 ps
CPU time 90.21 seconds
Started Jul 12 05:17:57 PM PDT 24
Finished Jul 12 05:19:27 PM PDT 24
Peak memory 1062452 kb
Host smart-db86c7c1-a292-47ec-ac13-f3e126427c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198834476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.198834476
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1973289517
Short name T1072
Test name
Test status
Simulation time 1732857099 ps
CPU time 5.63 seconds
Started Jul 12 05:18:12 PM PDT 24
Finished Jul 12 05:18:18 PM PDT 24
Peak memory 205308 kb
Host smart-3acbb725-8c75-4ed6-9334-9359dca42096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973289517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1973289517
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.1122890452
Short name T1340
Test name
Test status
Simulation time 91905047 ps
CPU time 0.65 seconds
Started Jul 12 05:17:57 PM PDT 24
Finished Jul 12 05:17:58 PM PDT 24
Peak memory 205064 kb
Host smart-ff136dd8-1151-4734-8ab6-db29ddbfe6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122890452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1122890452
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1028051615
Short name T1153
Test name
Test status
Simulation time 24369091033 ps
CPU time 192.32 seconds
Started Jul 12 05:17:58 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 230924 kb
Host smart-cb45df07-64d4-421e-be71-e7e83c718a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028051615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1028051615
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.2262484346
Short name T538
Test name
Test status
Simulation time 706890721 ps
CPU time 1.53 seconds
Started Jul 12 05:17:52 PM PDT 24
Finished Jul 12 05:17:54 PM PDT 24
Peak memory 205076 kb
Host smart-7bfb1433-30d5-4925-99cd-edb88009cee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262484346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2262484346
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1880595389
Short name T1173
Test name
Test status
Simulation time 1246070198 ps
CPU time 25.67 seconds
Started Jul 12 05:17:55 PM PDT 24
Finished Jul 12 05:18:21 PM PDT 24
Peak memory 361724 kb
Host smart-ddd7d871-8773-46bf-bd21-56faff12e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880595389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1880595389
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1982567088
Short name T559
Test name
Test status
Simulation time 595749755 ps
CPU time 25.69 seconds
Started Jul 12 05:17:53 PM PDT 24
Finished Jul 12 05:18:19 PM PDT 24
Peak memory 213408 kb
Host smart-4c762b36-14ee-4036-81ca-556099094958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982567088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1982567088
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1045558936
Short name T870
Test name
Test status
Simulation time 448300995 ps
CPU time 2.6 seconds
Started Jul 12 05:18:11 PM PDT 24
Finished Jul 12 05:18:14 PM PDT 24
Peak memory 213628 kb
Host smart-bdbb39ad-3ec9-45b8-a3f0-5c86ee461246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045558936 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1045558936
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3774248954
Short name T439
Test name
Test status
Simulation time 215337089 ps
CPU time 0.85 seconds
Started Jul 12 05:18:04 PM PDT 24
Finished Jul 12 05:18:06 PM PDT 24
Peak memory 205208 kb
Host smart-c3d2e7a7-a642-468b-a249-dd9f0f5ea927
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774248954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3774248954
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.4001082892
Short name T492
Test name
Test status
Simulation time 99333270 ps
CPU time 0.95 seconds
Started Jul 12 05:18:10 PM PDT 24
Finished Jul 12 05:18:12 PM PDT 24
Peak memory 205300 kb
Host smart-4e5e12fc-ca17-4cff-b483-56692618797f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001082892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.4001082892
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.3312829742
Short name T1196
Test name
Test status
Simulation time 2132929408 ps
CPU time 1.51 seconds
Started Jul 12 05:18:15 PM PDT 24
Finished Jul 12 05:18:17 PM PDT 24
Peak memory 205300 kb
Host smart-1f6740d0-3333-4430-b011-98dd1d9bbfda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312829742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.3312829742
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3669261018
Short name T1560
Test name
Test status
Simulation time 3901240722 ps
CPU time 6.49 seconds
Started Jul 12 05:18:07 PM PDT 24
Finished Jul 12 05:18:15 PM PDT 24
Peak memory 217664 kb
Host smart-6bb77273-e8b5-4d01-9fe3-e2598c642dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669261018 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3669261018
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1365620299
Short name T1075
Test name
Test status
Simulation time 15808839856 ps
CPU time 391.22 seconds
Started Jul 12 05:18:03 PM PDT 24
Finished Jul 12 05:24:36 PM PDT 24
Peak memory 3818120 kb
Host smart-e9851943-c6a4-40c7-a3f7-c7656ca6ebb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365620299 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1365620299
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.2332256428
Short name T812
Test name
Test status
Simulation time 2356592837 ps
CPU time 3.1 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:18:24 PM PDT 24
Peak memory 213572 kb
Host smart-4b3f60d9-aa55-4a91-abfd-c30436e1c4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332256428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.2332256428
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.1211235223
Short name T650
Test name
Test status
Simulation time 567341248 ps
CPU time 2.86 seconds
Started Jul 12 05:18:08 PM PDT 24
Finished Jul 12 05:18:11 PM PDT 24
Peak memory 205428 kb
Host smart-afd99e68-9020-4aaa-a40c-98515b6bf73b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211235223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.1211235223
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.3808431128
Short name T1429
Test name
Test status
Simulation time 537268695 ps
CPU time 2.32 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:18:24 PM PDT 24
Peak memory 205192 kb
Host smart-ef4c0447-02ac-4377-9092-a8e2b5c0efff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808431128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_smbus_maxlen.3808431128
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3739051192
Short name T1080
Test name
Test status
Simulation time 979984156 ps
CPU time 12.75 seconds
Started Jul 12 05:18:08 PM PDT 24
Finished Jul 12 05:18:21 PM PDT 24
Peak memory 213580 kb
Host smart-44058c89-fb74-40de-b344-d495ecfb64d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739051192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3739051192
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1210705879
Short name T534
Test name
Test status
Simulation time 1436360956 ps
CPU time 18.39 seconds
Started Jul 12 05:18:02 PM PDT 24
Finished Jul 12 05:18:21 PM PDT 24
Peak memory 222388 kb
Host smart-5209e184-cdbd-477c-afb8-2a981869b966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210705879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1210705879
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1777672889
Short name T564
Test name
Test status
Simulation time 33584030441 ps
CPU time 343.58 seconds
Started Jul 12 05:18:02 PM PDT 24
Finished Jul 12 05:23:47 PM PDT 24
Peak memory 3494220 kb
Host smart-58a960da-36ac-4ad3-abc1-7435060bdf5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777672889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1777672889
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3236022156
Short name T703
Test name
Test status
Simulation time 5356765691 ps
CPU time 6.22 seconds
Started Jul 12 05:18:03 PM PDT 24
Finished Jul 12 05:18:10 PM PDT 24
Peak memory 285260 kb
Host smart-fb1d13ab-792d-4dcb-ada2-77010fb67250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236022156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3236022156
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.142487354
Short name T1000
Test name
Test status
Simulation time 1311156271 ps
CPU time 7.07 seconds
Started Jul 12 05:18:02 PM PDT 24
Finished Jul 12 05:18:09 PM PDT 24
Peak memory 229988 kb
Host smart-ea52e141-0734-483d-bac8-f2055cf79f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142487354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.142487354
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.2522215520
Short name T1316
Test name
Test status
Simulation time 1298301845 ps
CPU time 15.49 seconds
Started Jul 12 05:18:12 PM PDT 24
Finished Jul 12 05:18:29 PM PDT 24
Peak memory 205412 kb
Host smart-2dfdc0cd-af74-4bce-97fc-f01f4612e9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522215520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2522215520
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2760590120
Short name T1170
Test name
Test status
Simulation time 32743383 ps
CPU time 0.63 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:18:34 PM PDT 24
Peak memory 204648 kb
Host smart-2954612d-926b-4fb7-bdfe-ef72f9ff1454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760590120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2760590120
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.121589242
Short name T1189
Test name
Test status
Simulation time 130882719 ps
CPU time 1.9 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:18:18 PM PDT 24
Peak memory 213644 kb
Host smart-dcdc7301-2a55-4f9a-8d6a-36ebf7121074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121589242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.121589242
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.496415680
Short name T810
Test name
Test status
Simulation time 201444257 ps
CPU time 9.77 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:18:30 PM PDT 24
Peak memory 229500 kb
Host smart-df1bdc47-7de1-49cf-9abe-fdbf3d3e03f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496415680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.496415680
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2576005260
Short name T756
Test name
Test status
Simulation time 2410130635 ps
CPU time 182.63 seconds
Started Jul 12 05:18:19 PM PDT 24
Finished Jul 12 05:21:22 PM PDT 24
Peak memory 795712 kb
Host smart-091c55fd-f715-42df-be40-c8f25b69cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576005260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2576005260
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2293820921
Short name T1453
Test name
Test status
Simulation time 137730028 ps
CPU time 1.09 seconds
Started Jul 12 05:18:21 PM PDT 24
Finished Jul 12 05:18:23 PM PDT 24
Peak memory 205028 kb
Host smart-ecf21f23-1cbe-4724-8d94-4af9e5a2d2b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293820921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2293820921
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.4189767258
Short name T1123
Test name
Test status
Simulation time 184414454 ps
CPU time 9.27 seconds
Started Jul 12 05:18:19 PM PDT 24
Finished Jul 12 05:18:28 PM PDT 24
Peak memory 205328 kb
Host smart-133223c5-7c2c-4423-8c7f-1a18df9f05d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189767258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
4189767258
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1988123970
Short name T818
Test name
Test status
Simulation time 22561712086 ps
CPU time 161.49 seconds
Started Jul 12 05:18:11 PM PDT 24
Finished Jul 12 05:20:53 PM PDT 24
Peak memory 823928 kb
Host smart-21111c2c-aeeb-414f-80d4-7f0a697c8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988123970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1988123970
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.2851034812
Short name T148
Test name
Test status
Simulation time 29407764 ps
CPU time 0.66 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:18:22 PM PDT 24
Peak memory 204960 kb
Host smart-9abd1fd1-ba9c-4788-85e5-9bef07851356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851034812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2851034812
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3924706648
Short name T1030
Test name
Test status
Simulation time 1153589024 ps
CPU time 15.9 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:18:33 PM PDT 24
Peak memory 205308 kb
Host smart-a5b9d48b-5a96-4010-84f8-c95c98a350e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924706648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3924706648
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2603213824
Short name T685
Test name
Test status
Simulation time 5819380735 ps
CPU time 232.76 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:22:13 PM PDT 24
Peak memory 213388 kb
Host smart-9063159f-241b-4a47-9c52-9c262b7fc787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603213824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2603213824
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.734900650
Short name T1529
Test name
Test status
Simulation time 2025776508 ps
CPU time 45.48 seconds
Started Jul 12 05:18:20 PM PDT 24
Finished Jul 12 05:19:07 PM PDT 24
Peak memory 301048 kb
Host smart-823d97bb-7ae9-4d19-9132-1e4506c35290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734900650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.734900650
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3448198407
Short name T458
Test name
Test status
Simulation time 6453356696 ps
CPU time 13.51 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:18:30 PM PDT 24
Peak memory 220764 kb
Host smart-be35b653-c100-41cf-8c7f-499c4a06c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448198407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3448198407
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3566250183
Short name T189
Test name
Test status
Simulation time 631531543 ps
CPU time 0.86 seconds
Started Jul 12 05:18:31 PM PDT 24
Finished Jul 12 05:18:32 PM PDT 24
Peak memory 223300 kb
Host smart-41162b02-314c-4df1-a155-4bc4974b7b65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566250183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3566250183
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.168568015
Short name T667
Test name
Test status
Simulation time 1009014522 ps
CPU time 5.8 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:18:39 PM PDT 24
Peak memory 213828 kb
Host smart-30f8167b-85ab-4748-ad9b-f97a4778178d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168568015 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.168568015
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.81896734
Short name T1564
Test name
Test status
Simulation time 160881557 ps
CPU time 1.01 seconds
Started Jul 12 05:18:28 PM PDT 24
Finished Jul 12 05:18:30 PM PDT 24
Peak memory 205312 kb
Host smart-ea295b2c-1f7c-406b-bea8-9597f61a4b5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81896734 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_acq.81896734
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2856715105
Short name T673
Test name
Test status
Simulation time 290415946 ps
CPU time 1 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:18:34 PM PDT 24
Peak memory 205572 kb
Host smart-bb8b6478-bfe9-40ca-966a-bc868a32ed34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856715105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2856715105
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.1751801587
Short name T1159
Test name
Test status
Simulation time 1123387542 ps
CPU time 1.91 seconds
Started Jul 12 05:18:27 PM PDT 24
Finished Jul 12 05:18:29 PM PDT 24
Peak memory 205444 kb
Host smart-d307dfb6-9fe1-4ea9-8322-ce278813f197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751801587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.1751801587
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.436010965
Short name T179
Test name
Test status
Simulation time 691234063 ps
CPU time 1.36 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:18:34 PM PDT 24
Peak memory 205328 kb
Host smart-10bafb48-4f02-4eb3-a4f6-ee9c5d6396c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436010965 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.436010965
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.656638905
Short name T49
Test name
Test status
Simulation time 4278110394 ps
CPU time 11.33 seconds
Started Jul 12 05:18:17 PM PDT 24
Finished Jul 12 05:18:29 PM PDT 24
Peak memory 213904 kb
Host smart-4244505b-d8cb-479a-b9b4-af82cb1b2a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656638905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.656638905
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2114904551
Short name T1100
Test name
Test status
Simulation time 2000568007 ps
CPU time 5.42 seconds
Started Jul 12 05:18:22 PM PDT 24
Finished Jul 12 05:18:28 PM PDT 24
Peak memory 221676 kb
Host smart-de471a9f-45e2-43f8-bda8-cda64c3fc1cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114904551 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2114904551
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1403449653
Short name T1480
Test name
Test status
Simulation time 11034278254 ps
CPU time 185.37 seconds
Started Jul 12 05:18:18 PM PDT 24
Finished Jul 12 05:21:24 PM PDT 24
Peak memory 2785768 kb
Host smart-fbc0408f-6da7-4c61-aebd-10188b416d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403449653 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1403449653
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.3938718031
Short name T362
Test name
Test status
Simulation time 499164024 ps
CPU time 2.85 seconds
Started Jul 12 05:18:34 PM PDT 24
Finished Jul 12 05:18:38 PM PDT 24
Peak memory 213588 kb
Host smart-720d3f5b-7f33-455f-87b6-4944c5ef91ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938718031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.3938718031
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.2331885139
Short name T1020
Test name
Test status
Simulation time 1569565959 ps
CPU time 2.16 seconds
Started Jul 12 05:18:30 PM PDT 24
Finished Jul 12 05:18:33 PM PDT 24
Peak memory 205412 kb
Host smart-dbb1d173-59f6-47b2-a8a3-760185c87413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331885139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2331885139
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.951275060
Short name T500
Test name
Test status
Simulation time 475345910 ps
CPU time 2.12 seconds
Started Jul 12 05:18:35 PM PDT 24
Finished Jul 12 05:18:38 PM PDT 24
Peak memory 205192 kb
Host smart-424c422c-2f2d-43ea-ac8a-c31cb48c524b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951275060 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_smbus_maxlen.951275060
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1180322342
Short name T346
Test name
Test status
Simulation time 4242164815 ps
CPU time 16.45 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:18:33 PM PDT 24
Peak memory 213652 kb
Host smart-ea7df8d8-9361-4020-a272-f7582355af50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180322342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1180322342
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3510512367
Short name T1302
Test name
Test status
Simulation time 2415163178 ps
CPU time 24.99 seconds
Started Jul 12 05:18:18 PM PDT 24
Finished Jul 12 05:18:44 PM PDT 24
Peak memory 229956 kb
Host smart-079d3228-9bd3-4422-9f5d-8b10c62e7fbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510512367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3510512367
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.810258175
Short name T759
Test name
Test status
Simulation time 57462227191 ps
CPU time 74.09 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:19:31 PM PDT 24
Peak memory 1095356 kb
Host smart-b96ba8f9-5230-4ffd-8a07-feefd4deef6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810258175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.810258175
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3722974725
Short name T831
Test name
Test status
Simulation time 5205660332 ps
CPU time 18.04 seconds
Started Jul 12 05:18:16 PM PDT 24
Finished Jul 12 05:18:35 PM PDT 24
Peak memory 436076 kb
Host smart-e1620734-3fb5-4656-9425-16f9495b7b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722974725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3722974725
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.907880279
Short name T833
Test name
Test status
Simulation time 3274295362 ps
CPU time 6.69 seconds
Started Jul 12 05:18:26 PM PDT 24
Finished Jul 12 05:18:33 PM PDT 24
Peak memory 238196 kb
Host smart-f7db5e5e-48c2-4099-8a4e-d64317ddacdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907880279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.907880279
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.533013220
Short name T1172
Test name
Test status
Simulation time 176600180 ps
CPU time 3.88 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:18:37 PM PDT 24
Peak memory 206324 kb
Host smart-fac624bd-c4f5-44fd-9769-0fae55229699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533013220 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.533013220
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3693016436
Short name T459
Test name
Test status
Simulation time 15308649 ps
CPU time 0.64 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:39 PM PDT 24
Peak memory 204516 kb
Host smart-6e3082cc-7aa9-49db-a7ce-b286056d2c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693016436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3693016436
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3868852655
Short name T303
Test name
Test status
Simulation time 72391570 ps
CPU time 1.55 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:20:35 PM PDT 24
Peak memory 213532 kb
Host smart-b8fe0c2a-a5fa-4c05-aa0f-142234382b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868852655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3868852655
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.712760941
Short name T499
Test name
Test status
Simulation time 542256287 ps
CPU time 5.02 seconds
Started Jul 12 05:20:31 PM PDT 24
Finished Jul 12 05:20:37 PM PDT 24
Peak memory 257236 kb
Host smart-7b488f06-4099-45db-9692-b68892dab32a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712760941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.712760941
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.4154079180
Short name T627
Test name
Test status
Simulation time 2602549321 ps
CPU time 79.76 seconds
Started Jul 12 05:20:31 PM PDT 24
Finished Jul 12 05:21:53 PM PDT 24
Peak memory 801828 kb
Host smart-1d7baa7b-dd1b-4fd6-b5af-f12ff24f3326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154079180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.4154079180
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1083305986
Short name T869
Test name
Test status
Simulation time 726429696 ps
CPU time 9.72 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:20:43 PM PDT 24
Peak memory 237204 kb
Host smart-66e7523a-4caf-4eef-a2cf-a7f9772f9275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083305986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1083305986
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2724732533
Short name T1455
Test name
Test status
Simulation time 7453759666 ps
CPU time 102.72 seconds
Started Jul 12 05:20:34 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 1105696 kb
Host smart-239df5a7-c080-44ec-84bd-ec050101df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724732533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2724732533
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.3759155821
Short name T23
Test name
Test status
Simulation time 1860246016 ps
CPU time 7.22 seconds
Started Jul 12 05:20:29 PM PDT 24
Finished Jul 12 05:20:37 PM PDT 24
Peak memory 205224 kb
Host smart-f35fd9f7-7045-4958-a929-5ebb6c3e3963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759155821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3759155821
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.3348922271
Short name T537
Test name
Test status
Simulation time 87031071 ps
CPU time 0.67 seconds
Started Jul 12 05:20:30 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 205060 kb
Host smart-16b79f08-785c-43e8-9f6f-09e9d5bcd71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348922271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3348922271
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.920770562
Short name T1077
Test name
Test status
Simulation time 121749992 ps
CPU time 1.16 seconds
Started Jul 12 05:20:34 PM PDT 24
Finished Jul 12 05:20:36 PM PDT 24
Peak memory 205628 kb
Host smart-f2256e14-3add-40ff-98e8-b66d5e7c02e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920770562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.920770562
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.27542262
Short name T883
Test name
Test status
Simulation time 1984267007 ps
CPU time 31.1 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:21:04 PM PDT 24
Peak memory 366660 kb
Host smart-56d5df46-227f-45ae-b98a-ccd9fe44da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27542262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.27542262
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.4247662939
Short name T1090
Test name
Test status
Simulation time 1643113218 ps
CPU time 37.49 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 213488 kb
Host smart-d14641f4-9a76-4d25-a1f0-ecb7485a3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247662939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.4247662939
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2773890550
Short name T1226
Test name
Test status
Simulation time 1091724455 ps
CPU time 5.48 seconds
Started Jul 12 05:20:33 PM PDT 24
Finished Jul 12 05:20:40 PM PDT 24
Peak memory 220044 kb
Host smart-2ce7fd70-b0e7-40f4-8b3f-47203e7a61ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773890550 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2773890550
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2952184561
Short name T1320
Test name
Test status
Simulation time 173474358 ps
CPU time 1 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:20:35 PM PDT 24
Peak memory 205192 kb
Host smart-cb571123-30a6-456b-8f62-fd46da2ac7bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952184561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2952184561
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1683384747
Short name T946
Test name
Test status
Simulation time 296337525 ps
CPU time 1.38 seconds
Started Jul 12 05:20:30 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 205320 kb
Host smart-00637101-c581-44ac-951a-3210ca7bbdb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683384747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1683384747
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.593892493
Short name T390
Test name
Test status
Simulation time 593695417 ps
CPU time 2.81 seconds
Started Jul 12 05:20:40 PM PDT 24
Finished Jul 12 05:20:44 PM PDT 24
Peak memory 205428 kb
Host smart-a406e36c-6928-4a0e-83d0-bb740253f03b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593892493 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.593892493
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.3395016924
Short name T672
Test name
Test status
Simulation time 123196955 ps
CPU time 1.19 seconds
Started Jul 12 05:20:38 PM PDT 24
Finished Jul 12 05:20:41 PM PDT 24
Peak memory 205156 kb
Host smart-c9775dbc-d3ff-479b-9fef-f1053be5cef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395016924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3395016924
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2362194860
Short name T1086
Test name
Test status
Simulation time 3449308587 ps
CPU time 5.49 seconds
Started Jul 12 05:20:31 PM PDT 24
Finished Jul 12 05:20:38 PM PDT 24
Peak memory 221936 kb
Host smart-a7ca58b1-1124-4f37-ad55-9b4d32a113d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362194860 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2362194860
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1891982477
Short name T1525
Test name
Test status
Simulation time 9085368416 ps
CPU time 7.48 seconds
Started Jul 12 05:20:32 PM PDT 24
Finished Jul 12 05:20:41 PM PDT 24
Peak memory 241344 kb
Host smart-31ab4c87-a290-454f-b794-f986e50f9acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891982477 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1891982477
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.1747384570
Short name T1365
Test name
Test status
Simulation time 3088402531 ps
CPU time 3 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:42 PM PDT 24
Peak memory 213692 kb
Host smart-8183eeac-0e25-42f3-918b-9dc18df70e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747384570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.1747384570
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.4087461007
Short name T1139
Test name
Test status
Simulation time 9695433083 ps
CPU time 2.29 seconds
Started Jul 12 05:20:35 PM PDT 24
Finished Jul 12 05:20:38 PM PDT 24
Peak memory 205364 kb
Host smart-f77a7b31-6863-463d-a3e6-d99d25b38ab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087461007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.4087461007
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1109935911
Short name T336
Test name
Test status
Simulation time 3524910886 ps
CPU time 20.9 seconds
Started Jul 12 05:20:30 PM PDT 24
Finished Jul 12 05:20:51 PM PDT 24
Peak memory 213620 kb
Host smart-65d095db-fd80-4875-a36f-0c5af7c2d87b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109935911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1109935911
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.4228399360
Short name T1133
Test name
Test status
Simulation time 824643319 ps
CPU time 18.13 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:57 PM PDT 24
Peak memory 205376 kb
Host smart-6414a0ff-0383-4bdb-8035-76eeae4e777e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228399360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.4228399360
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2331199226
Short name T1034
Test name
Test status
Simulation time 52431820241 ps
CPU time 1427.87 seconds
Started Jul 12 05:20:33 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 8022960 kb
Host smart-0c165ab0-f2a4-415a-9914-e5d46c895e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331199226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2331199226
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2099225652
Short name T1339
Test name
Test status
Simulation time 4989070490 ps
CPU time 11.93 seconds
Started Jul 12 05:20:31 PM PDT 24
Finished Jul 12 05:20:43 PM PDT 24
Peak memory 237992 kb
Host smart-e6779f38-cc02-4475-9537-e180b03110f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099225652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2099225652
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.4215675853
Short name T600
Test name
Test status
Simulation time 2520315221 ps
CPU time 6.47 seconds
Started Jul 12 05:20:29 PM PDT 24
Finished Jul 12 05:20:36 PM PDT 24
Peak memory 213692 kb
Host smart-c590a30f-aa9e-45ab-b641-6a4eceef1cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215675853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.4215675853
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2660026114
Short name T1282
Test name
Test status
Simulation time 1194644463 ps
CPU time 14.32 seconds
Started Jul 12 05:20:35 PM PDT 24
Finished Jul 12 05:20:50 PM PDT 24
Peak memory 213508 kb
Host smart-aed68257-e0e3-42fd-a5eb-6f70db5a7e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660026114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2660026114
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3537292263
Short name T1530
Test name
Test status
Simulation time 68113822 ps
CPU time 0.63 seconds
Started Jul 12 05:20:43 PM PDT 24
Finished Jul 12 05:20:44 PM PDT 24
Peak memory 204648 kb
Host smart-0972f02c-eb2e-4b12-bde6-dbd673777579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537292263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3537292263
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.354792085
Short name T1557
Test name
Test status
Simulation time 2124077941 ps
CPU time 4.55 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:44 PM PDT 24
Peak memory 242900 kb
Host smart-f61c5e3b-f56f-479e-9384-303871b18f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354792085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.354792085
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2170993382
Short name T1532
Test name
Test status
Simulation time 626389942 ps
CPU time 3.07 seconds
Started Jul 12 05:20:40 PM PDT 24
Finished Jul 12 05:20:44 PM PDT 24
Peak memory 226392 kb
Host smart-f9e1f557-be84-4fc3-b7a7-963af5694a85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170993382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2170993382
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1535648318
Short name T90
Test name
Test status
Simulation time 2066940940 ps
CPU time 133.65 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:22:53 PM PDT 24
Peak memory 629908 kb
Host smart-fc9bd016-7ff9-4a4e-89da-ebc44692d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535648318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1535648318
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.837506696
Short name T1104
Test name
Test status
Simulation time 9633625005 ps
CPU time 87.85 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:22:07 PM PDT 24
Peak memory 785028 kb
Host smart-e7e21983-d7f8-4664-9322-8edac2e9bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837506696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.837506696
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.490848617
Short name T707
Test name
Test status
Simulation time 533201652 ps
CPU time 1.16 seconds
Started Jul 12 05:20:39 PM PDT 24
Finished Jul 12 05:20:41 PM PDT 24
Peak memory 205144 kb
Host smart-370579e8-bff5-48f4-8418-9687b056e90f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490848617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.490848617
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2882350438
Short name T669
Test name
Test status
Simulation time 389088766 ps
CPU time 4.72 seconds
Started Jul 12 05:20:40 PM PDT 24
Finished Jul 12 05:20:46 PM PDT 24
Peak memory 205312 kb
Host smart-a2313979-53e4-4b19-8738-d4723fd8d6e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882350438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2882350438
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2485165993
Short name T777
Test name
Test status
Simulation time 3900817969 ps
CPU time 266.83 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 1146892 kb
Host smart-3d97b019-0055-47d9-8a2b-d0c2aa3a8315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485165993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2485165993
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.348020286
Short name T570
Test name
Test status
Simulation time 1176880626 ps
CPU time 23.15 seconds
Started Jul 12 05:20:44 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 205308 kb
Host smart-a64238d4-983c-4c2f-8d91-4ebca8248afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348020286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.348020286
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.3554702791
Short name T1404
Test name
Test status
Simulation time 28272255 ps
CPU time 0.7 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:20:39 PM PDT 24
Peak memory 205048 kb
Host smart-d2f7db3a-164a-4d50-91ce-7285b79521f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554702791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3554702791
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3611249159
Short name T773
Test name
Test status
Simulation time 25449961082 ps
CPU time 1719.99 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:49:19 PM PDT 24
Peak memory 4127580 kb
Host smart-88255b01-8389-4d8c-b962-a77ef2539070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611249159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3611249159
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.1545864089
Short name T766
Test name
Test status
Simulation time 177755720 ps
CPU time 1.02 seconds
Started Jul 12 05:20:36 PM PDT 24
Finished Jul 12 05:20:38 PM PDT 24
Peak memory 205064 kb
Host smart-c0cf3ccf-d656-4910-a235-9e7fd2e993c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545864089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.1545864089
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2187518578
Short name T551
Test name
Test status
Simulation time 4460824915 ps
CPU time 36.05 seconds
Started Jul 12 05:20:37 PM PDT 24
Finished Jul 12 05:21:15 PM PDT 24
Peak memory 333404 kb
Host smart-9a94e5b0-990a-47db-b12a-c6417bf2a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187518578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2187518578
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2263564070
Short name T1145
Test name
Test status
Simulation time 11878968892 ps
CPU time 10.85 seconds
Started Jul 12 05:20:41 PM PDT 24
Finished Jul 12 05:20:52 PM PDT 24
Peak memory 217148 kb
Host smart-39fc6d95-435e-4580-bb86-61700b1e44e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263564070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2263564070
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.31461984
Short name T903
Test name
Test status
Simulation time 740543364 ps
CPU time 4.31 seconds
Started Jul 12 05:20:49 PM PDT 24
Finished Jul 12 05:20:55 PM PDT 24
Peak memory 219996 kb
Host smart-005edf84-7ad3-4d42-bf27-c07ffa29384f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31461984 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.31461984
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1666847083
Short name T1277
Test name
Test status
Simulation time 1413693466 ps
CPU time 1.1 seconds
Started Jul 12 05:20:44 PM PDT 24
Finished Jul 12 05:20:46 PM PDT 24
Peak memory 205200 kb
Host smart-15bbdaee-b401-4fa9-b7d7-61a495c0e614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666847083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1666847083
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.4050311218
Short name T922
Test name
Test status
Simulation time 703363730 ps
CPU time 2.82 seconds
Started Jul 12 05:20:45 PM PDT 24
Finished Jul 12 05:20:49 PM PDT 24
Peak memory 205420 kb
Host smart-0fce7b23-6f82-47c2-87b6-242a8c7027df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050311218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.4050311218
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.472183517
Short name T1356
Test name
Test status
Simulation time 518725023 ps
CPU time 1.14 seconds
Started Jul 12 05:23:22 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 205296 kb
Host smart-1a03369d-3a5b-42d5-a779-08143cca1baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472183517 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.472183517
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.528293060
Short name T4
Test name
Test status
Simulation time 1549387367 ps
CPU time 8.1 seconds
Started Jul 12 05:20:45 PM PDT 24
Finished Jul 12 05:20:54 PM PDT 24
Peak memory 219812 kb
Host smart-ea756b53-2fad-48ec-b887-ce5c9189a6a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528293060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.528293060
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2052485153
Short name T1493
Test name
Test status
Simulation time 4956868935 ps
CPU time 10.39 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:21:05 PM PDT 24
Peak memory 205504 kb
Host smart-8d3b84bd-7011-460d-a49f-6fa0611ec04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052485153 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2052485153
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.886624304
Short name T167
Test name
Test status
Simulation time 530626522 ps
CPU time 2.86 seconds
Started Jul 12 05:20:44 PM PDT 24
Finished Jul 12 05:20:47 PM PDT 24
Peak memory 213608 kb
Host smart-03133fc3-fb5b-4cd2-8710-9a14fdd28f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886624304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_nack_acqfull.886624304
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.2489037429
Short name T1083
Test name
Test status
Simulation time 1678838167 ps
CPU time 2.15 seconds
Started Jul 12 05:20:44 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 205304 kb
Host smart-bd4179f9-8f16-44c2-829f-27bcc4665afb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489037429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.2489037429
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.122980268
Short name T1273
Test name
Test status
Simulation time 1352119973 ps
CPU time 19.32 seconds
Started Jul 12 05:20:38 PM PDT 24
Finished Jul 12 05:20:59 PM PDT 24
Peak memory 213644 kb
Host smart-31cec8c6-2b6f-4c62-940e-829f95f2cdc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122980268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.122980268
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2421325500
Short name T1190
Test name
Test status
Simulation time 13645159642 ps
CPU time 8.67 seconds
Started Jul 12 05:20:38 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 205760 kb
Host smart-4f934482-f9dd-42ed-a5ca-362895d6e092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421325500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2421325500
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2975933262
Short name T1513
Test name
Test status
Simulation time 1490587430 ps
CPU time 26.97 seconds
Started Jul 12 05:20:45 PM PDT 24
Finished Jul 12 05:21:13 PM PDT 24
Peak memory 516824 kb
Host smart-e4b9f36c-1f30-4ad3-9e50-96e68ca85f30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975933262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2975933262
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1681735905
Short name T1274
Test name
Test status
Simulation time 2951455576 ps
CPU time 7.78 seconds
Started Jul 12 05:20:45 PM PDT 24
Finished Jul 12 05:20:54 PM PDT 24
Peak memory 221852 kb
Host smart-619b49bd-2ad4-473e-9e08-4c63dec254a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681735905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1681735905
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3421196101
Short name T301
Test name
Test status
Simulation time 961948932 ps
CPU time 12.21 seconds
Started Jul 12 05:20:43 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 205368 kb
Host smart-abbc536c-a751-4653-9729-aebc901988b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421196101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3421196101
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3304380861
Short name T1459
Test name
Test status
Simulation time 16680268 ps
CPU time 0.65 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 204608 kb
Host smart-e5cbbdb3-3022-497d-83ad-4cdbeb35704a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304380861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3304380861
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.937918878
Short name T1336
Test name
Test status
Simulation time 812474518 ps
CPU time 7.97 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:21:01 PM PDT 24
Peak memory 232572 kb
Host smart-0c95cdff-ebba-41d4-9365-38bac5d63728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937918878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.937918878
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1421098851
Short name T821
Test name
Test status
Simulation time 277468094 ps
CPU time 13.78 seconds
Started Jul 12 05:20:49 PM PDT 24
Finished Jul 12 05:21:05 PM PDT 24
Peak memory 262052 kb
Host smart-c01b8b80-f93b-4dae-a04a-17c3401fca7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421098851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1421098851
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1126235431
Short name T220
Test name
Test status
Simulation time 7979967831 ps
CPU time 59.49 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:21:55 PM PDT 24
Peak memory 685864 kb
Host smart-4ff2993f-e887-49ad-8d16-edf071db87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126235431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1126235431
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.304180937
Short name T1266
Test name
Test status
Simulation time 1401690616 ps
CPU time 95.56 seconds
Started Jul 12 05:20:49 PM PDT 24
Finished Jul 12 05:22:27 PM PDT 24
Peak memory 543984 kb
Host smart-37a3d9c9-9f71-4939-aee3-ee16de11078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304180937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.304180937
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2307583266
Short name T598
Test name
Test status
Simulation time 131799548 ps
CPU time 1.15 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:20:55 PM PDT 24
Peak memory 205108 kb
Host smart-c196d679-6de3-4e99-b928-752dbdf696c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307583266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2307583266
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.208704460
Short name T815
Test name
Test status
Simulation time 389979449 ps
CPU time 10.48 seconds
Started Jul 12 05:20:50 PM PDT 24
Finished Jul 12 05:21:02 PM PDT 24
Peak memory 241288 kb
Host smart-07bf1167-05db-4987-953d-d2d45b588137
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208704460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
208704460
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1182255461
Short name T434
Test name
Test status
Simulation time 4280662246 ps
CPU time 280.73 seconds
Started Jul 12 05:20:55 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 1135500 kb
Host smart-b0c8547a-af68-4fcb-96ee-bc0565b835d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182255461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1182255461
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_override.4109788740
Short name T645
Test name
Test status
Simulation time 55765686 ps
CPU time 0.64 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 204984 kb
Host smart-df8e3618-ce7a-4d21-aa86-5ad00cee2298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109788740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4109788740
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.9784941
Short name T944
Test name
Test status
Simulation time 2003981932 ps
CPU time 3.21 seconds
Started Jul 12 05:20:50 PM PDT 24
Finished Jul 12 05:20:55 PM PDT 24
Peak memory 222320 kb
Host smart-09ee293b-64ce-472e-bd87-9ce34726e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9784941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.9784941
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2361264681
Short name T661
Test name
Test status
Simulation time 4200983207 ps
CPU time 17.32 seconds
Started Jul 12 05:20:46 PM PDT 24
Finished Jul 12 05:21:04 PM PDT 24
Peak memory 310728 kb
Host smart-c9104424-7271-4f86-914f-c8ef6b97c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361264681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2361264681
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2231369201
Short name T36
Test name
Test status
Simulation time 22430456901 ps
CPU time 511.84 seconds
Started Jul 12 05:20:54 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 2454024 kb
Host smart-3090a83b-9fa8-41fc-8d31-77064fd1e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231369201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2231369201
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1786223101
Short name T1373
Test name
Test status
Simulation time 1042872761 ps
CPU time 19.42 seconds
Started Jul 12 05:20:50 PM PDT 24
Finished Jul 12 05:21:11 PM PDT 24
Peak memory 219120 kb
Host smart-d42a8078-ced8-4c2d-bcf3-bc367ec95508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786223101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1786223101
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.748350552
Short name T1243
Test name
Test status
Simulation time 6028014098 ps
CPU time 7.4 seconds
Started Jul 12 05:20:49 PM PDT 24
Finished Jul 12 05:20:59 PM PDT 24
Peak memory 213784 kb
Host smart-8501872e-f8df-4626-b538-bb6392720b03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748350552 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.748350552
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2049964360
Short name T223
Test name
Test status
Simulation time 371525967 ps
CPU time 1.56 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 205368 kb
Host smart-f28847ec-95ef-40a0-b2ae-da493e43d4e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049964360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2049964360
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.581999718
Short name T1545
Test name
Test status
Simulation time 396332331 ps
CPU time 1.05 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:20:56 PM PDT 24
Peak memory 205316 kb
Host smart-877a5c6c-b461-4af7-8dc9-be71bba75b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581999718 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.581999718
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.899441296
Short name T1332
Test name
Test status
Simulation time 145840223 ps
CPU time 1.19 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:20:54 PM PDT 24
Peak memory 205312 kb
Host smart-dbd59320-f9b6-4d79-bfc5-43b5b26fd9c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899441296 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.899441296
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3808109507
Short name T891
Test name
Test status
Simulation time 780804535 ps
CPU time 1.39 seconds
Started Jul 12 05:20:50 PM PDT 24
Finished Jul 12 05:20:53 PM PDT 24
Peak memory 205324 kb
Host smart-6310866c-1d1f-42e4-9e19-cf26ff467c7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808109507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3808109507
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3551082093
Short name T1079
Test name
Test status
Simulation time 11952201480 ps
CPU time 4.91 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:21:00 PM PDT 24
Peak memory 215236 kb
Host smart-8da3473e-aaa3-437c-93a2-9f84ded4d99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551082093 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3551082093
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1613728608
Short name T414
Test name
Test status
Simulation time 6254330924 ps
CPU time 5.53 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:21:00 PM PDT 24
Peak memory 205480 kb
Host smart-f6a425ef-4e8a-48bc-9fdf-2b160258d366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613728608 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1613728608
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.656968643
Short name T1224
Test name
Test status
Simulation time 2338173003 ps
CPU time 2.88 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:20:58 PM PDT 24
Peak memory 213708 kb
Host smart-b13fe9aa-d89b-4bed-97c1-6e154cb7b979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656968643 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_nack_acqfull.656968643
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.692766752
Short name T1499
Test name
Test status
Simulation time 2248577766 ps
CPU time 3.05 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:20:59 PM PDT 24
Peak memory 205492 kb
Host smart-7f9fffce-b441-461a-a185-50d8ecb7a81c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692766752 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.692766752
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.4207636761
Short name T597
Test name
Test status
Simulation time 2711083905 ps
CPU time 2.55 seconds
Started Jul 12 05:20:54 PM PDT 24
Finished Jul 12 05:20:58 PM PDT 24
Peak memory 205308 kb
Host smart-30426d8a-16bc-4e20-acbf-b89a78deac3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207636761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.4207636761
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2661235516
Short name T879
Test name
Test status
Simulation time 2064739049 ps
CPU time 30.21 seconds
Started Jul 12 05:20:53 PM PDT 24
Finished Jul 12 05:21:25 PM PDT 24
Peak memory 217636 kb
Host smart-669e5d92-ce0a-4f63-b50f-7c90e5fa707c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661235516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2661235516
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.17913734
Short name T859
Test name
Test status
Simulation time 1168501615 ps
CPU time 52.77 seconds
Started Jul 12 05:20:56 PM PDT 24
Finished Jul 12 05:21:50 PM PDT 24
Peak memory 213572 kb
Host smart-b7168a2d-7f4c-4f43-b062-98fd2543d774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stress_rd.17913734
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3660096710
Short name T623
Test name
Test status
Simulation time 34824428083 ps
CPU time 56.92 seconds
Started Jul 12 05:20:49 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 965656 kb
Host smart-363b3a0c-ac80-4e92-af46-7a4fd5b41b44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660096710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3660096710
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3049592529
Short name T196
Test name
Test status
Simulation time 2769683279 ps
CPU time 17.95 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:21:11 PM PDT 24
Peak memory 415140 kb
Host smart-5095c988-6bad-4e8e-b5b6-053ae3aeb744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049592529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3049592529
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2120243011
Short name T849
Test name
Test status
Simulation time 1317031322 ps
CPU time 7.45 seconds
Started Jul 12 05:20:54 PM PDT 24
Finished Jul 12 05:21:03 PM PDT 24
Peak memory 213580 kb
Host smart-02389592-4b73-40a4-9175-e676979c2bf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120243011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2120243011
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2373913624
Short name T924
Test name
Test status
Simulation time 76974265 ps
CPU time 1.73 seconds
Started Jul 12 05:20:50 PM PDT 24
Finished Jul 12 05:20:53 PM PDT 24
Peak memory 205356 kb
Host smart-ff2f20a1-b29c-4a20-88fd-cc5f072282ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373913624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2373913624
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3185365123
Short name T1138
Test name
Test status
Simulation time 23125989 ps
CPU time 0.63 seconds
Started Jul 12 05:21:06 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 204612 kb
Host smart-2ec87d1b-7330-4aec-b366-dfd5537e18e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185365123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3185365123
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.4082208612
Short name T20
Test name
Test status
Simulation time 1644580794 ps
CPU time 2.77 seconds
Started Jul 12 05:20:58 PM PDT 24
Finished Jul 12 05:21:02 PM PDT 24
Peak memory 213504 kb
Host smart-6b9b81fa-ec19-4b3e-99bf-31a6a48c5c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082208612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.4082208612
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3510610895
Short name T12
Test name
Test status
Simulation time 291870214 ps
CPU time 4.87 seconds
Started Jul 12 05:21:11 PM PDT 24
Finished Jul 12 05:21:16 PM PDT 24
Peak memory 259200 kb
Host smart-2fcb1998-e2ee-462b-bd65-014226402fd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510610895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3510610895
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.379000137
Short name T93
Test name
Test status
Simulation time 4009161351 ps
CPU time 140.88 seconds
Started Jul 12 05:20:55 PM PDT 24
Finished Jul 12 05:23:17 PM PDT 24
Peak memory 686980 kb
Host smart-e92143a7-ea6d-45c3-9a60-18401f3376a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379000137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.379000137
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.676260567
Short name T609
Test name
Test status
Simulation time 9120234087 ps
CPU time 66.17 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:21:59 PM PDT 24
Peak memory 708716 kb
Host smart-0c0c9480-3968-4017-a24d-e48b54637461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676260567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.676260567
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1728247099
Short name T925
Test name
Test status
Simulation time 142248459 ps
CPU time 1.1 seconds
Started Jul 12 05:20:51 PM PDT 24
Finished Jul 12 05:20:54 PM PDT 24
Peak memory 204948 kb
Host smart-a5a31797-d586-49fc-abd0-db40725e9046
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728247099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1728247099
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1475916624
Short name T490
Test name
Test status
Simulation time 383219904 ps
CPU time 11.68 seconds
Started Jul 12 05:20:57 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 244672 kb
Host smart-eb0f31dc-d880-410b-a907-1cf408a85370
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475916624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1475916624
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.4052045400
Short name T1006
Test name
Test status
Simulation time 3668462254 ps
CPU time 5.21 seconds
Started Jul 12 05:21:04 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 205388 kb
Host smart-c194424a-242f-480f-81eb-b7e6c0801f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052045400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.4052045400
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1491514562
Short name T839
Test name
Test status
Simulation time 7138015540 ps
CPU time 38.77 seconds
Started Jul 12 05:21:03 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 597864 kb
Host smart-04b2b4f8-6de4-480b-80e3-59cb4e5de1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491514562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1491514562
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.2741608433
Short name T584
Test name
Test status
Simulation time 57728175 ps
CPU time 1.16 seconds
Started Jul 12 05:21:01 PM PDT 24
Finished Jul 12 05:21:03 PM PDT 24
Peak memory 222736 kb
Host smart-f517e1de-e9b0-4ec2-88ef-d632d1afb938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741608433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.2741608433
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1153054143
Short name T325
Test name
Test status
Simulation time 1591430919 ps
CPU time 27.23 seconds
Started Jul 12 05:20:52 PM PDT 24
Finished Jul 12 05:21:21 PM PDT 24
Peak memory 282796 kb
Host smart-e341f448-47c7-45fe-af90-e9e9a787d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153054143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1153054143
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1470228162
Short name T1113
Test name
Test status
Simulation time 35698766402 ps
CPU time 297.5 seconds
Started Jul 12 05:20:57 PM PDT 24
Finished Jul 12 05:25:55 PM PDT 24
Peak memory 1046344 kb
Host smart-9141b28a-eb33-4de6-9bb3-88482d923ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470228162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1470228162
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.27977336
Short name T302
Test name
Test status
Simulation time 791533496 ps
CPU time 10.27 seconds
Started Jul 12 05:20:59 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 215956 kb
Host smart-cde7c5e0-4a55-4aa0-b26d-18ff29fc4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27977336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.27977336
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2113928135
Short name T532
Test name
Test status
Simulation time 490220090 ps
CPU time 1.05 seconds
Started Jul 12 05:20:59 PM PDT 24
Finished Jul 12 05:21:01 PM PDT 24
Peak memory 205204 kb
Host smart-66bb10de-bed6-46f8-9727-4ccd5480fa24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113928135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2113928135
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.398163691
Short name T528
Test name
Test status
Simulation time 320150886 ps
CPU time 1.25 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:11 PM PDT 24
Peak memory 205316 kb
Host smart-14352a57-6f15-4b73-9029-83d4d7f7f8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398163691 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.398163691
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3160421494
Short name T1441
Test name
Test status
Simulation time 3149472535 ps
CPU time 3.31 seconds
Started Jul 12 05:21:04 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 205492 kb
Host smart-dd915ed2-11eb-412b-b84d-64c3e821fdbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160421494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3160421494
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.1348697120
Short name T693
Test name
Test status
Simulation time 209375373 ps
CPU time 1.1 seconds
Started Jul 12 05:21:07 PM PDT 24
Finished Jul 12 05:21:09 PM PDT 24
Peak memory 205192 kb
Host smart-d8349204-848e-46f9-9bfe-f0f243458a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348697120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.1348697120
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2212705737
Short name T275
Test name
Test status
Simulation time 3049185900 ps
CPU time 4.28 seconds
Started Jul 12 05:21:01 PM PDT 24
Finished Jul 12 05:21:07 PM PDT 24
Peak memory 213672 kb
Host smart-c9a9d5a1-91be-4059-9319-19e4ce6bb7f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212705737 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2212705737
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.814538712
Short name T1081
Test name
Test status
Simulation time 14154601055 ps
CPU time 295.19 seconds
Started Jul 12 05:20:57 PM PDT 24
Finished Jul 12 05:25:53 PM PDT 24
Peak memory 3379320 kb
Host smart-37728719-5f46-43ea-ab15-b3486d06ccd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814538712 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.814538712
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.1241027033
Short name T590
Test name
Test status
Simulation time 1238538552 ps
CPU time 2.57 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:12 PM PDT 24
Peak memory 205416 kb
Host smart-56606ecd-09a0-4f20-b475-dfac583882e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241027033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.1241027033
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.3200485413
Short name T596
Test name
Test status
Simulation time 1054933386 ps
CPU time 2.44 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:12 PM PDT 24
Peak memory 205280 kb
Host smart-3e6e001f-3933-4fba-8f00-30cf755f7a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200485413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.3200485413
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2693008747
Short name T1502
Test name
Test status
Simulation time 831197916 ps
CPU time 10.79 seconds
Started Jul 12 05:20:58 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 213528 kb
Host smart-9129cfe6-90bb-4798-8499-944857eae36a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693008747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2693008747
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.4030545394
Short name T835
Test name
Test status
Simulation time 24605684275 ps
CPU time 17.23 seconds
Started Jul 12 05:20:59 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 342052 kb
Host smart-18e35483-8911-4197-a9a6-3fa4b7920f46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030545394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.4030545394
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2613525874
Short name T1063
Test name
Test status
Simulation time 2470502699 ps
CPU time 26.82 seconds
Started Jul 12 05:20:58 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 535108 kb
Host smart-a5298a79-6064-4dcd-8c72-14b8b471f994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613525874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2613525874
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2589576264
Short name T749
Test name
Test status
Simulation time 1277019758 ps
CPU time 7.65 seconds
Started Jul 12 05:20:58 PM PDT 24
Finished Jul 12 05:21:07 PM PDT 24
Peak memory 219740 kb
Host smart-0ffc3fa9-7145-4d44-87ba-a40dee750153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589576264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2589576264
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.2706974116
Short name T825
Test name
Test status
Simulation time 471730701 ps
CPU time 6.41 seconds
Started Jul 12 05:21:06 PM PDT 24
Finished Jul 12 05:21:13 PM PDT 24
Peak memory 205404 kb
Host smart-15b0cbe1-6b62-44a4-89b8-b3dbf145d858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706974116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2706974116
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2950160945
Short name T1163
Test name
Test status
Simulation time 21624612 ps
CPU time 0.66 seconds
Started Jul 12 05:21:21 PM PDT 24
Finished Jul 12 05:21:23 PM PDT 24
Peak memory 204744 kb
Host smart-7ff9faee-669a-4e77-9de8-575d703b1d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950160945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2950160945
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.859531149
Short name T1232
Test name
Test status
Simulation time 631927943 ps
CPU time 6.5 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:22 PM PDT 24
Peak memory 268200 kb
Host smart-8355486a-3960-411b-8f0c-84add12cb30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859531149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.859531149
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3172223961
Short name T956
Test name
Test status
Simulation time 575549925 ps
CPU time 12.16 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:21 PM PDT 24
Peak memory 327272 kb
Host smart-8cc04cf1-c29b-41fd-9cbc-d07010b1b824
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172223961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3172223961
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.4113916563
Short name T731
Test name
Test status
Simulation time 4601879781 ps
CPU time 63.6 seconds
Started Jul 12 05:21:07 PM PDT 24
Finished Jul 12 05:22:12 PM PDT 24
Peak memory 756152 kb
Host smart-4036f1f3-1cad-439a-860b-9557c989a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113916563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4113916563
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2902439545
Short name T401
Test name
Test status
Simulation time 372229354 ps
CPU time 0.92 seconds
Started Jul 12 05:21:06 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 205044 kb
Host smart-36091617-b1a4-434c-96c4-e87bec725107
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902439545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2902439545
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4198811173
Short name T1102
Test name
Test status
Simulation time 578036781 ps
CPU time 3.78 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:13 PM PDT 24
Peak memory 229628 kb
Host smart-584a508c-5132-49c1-9c85-2920dea68f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198811173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4198811173
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3479289030
Short name T100
Test name
Test status
Simulation time 14917923501 ps
CPU time 62.49 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:22:12 PM PDT 24
Peak memory 877000 kb
Host smart-6289b6bc-0fba-4837-8ea6-92246c794fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479289030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3479289030
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2896603672
Short name T29
Test name
Test status
Simulation time 2009899104 ps
CPU time 9.01 seconds
Started Jul 12 05:21:17 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 205288 kb
Host smart-9ff65cd8-4431-4b3b-9e9c-8995e7ba2f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896603672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2896603672
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.1721258201
Short name T1409
Test name
Test status
Simulation time 35427312 ps
CPU time 0.66 seconds
Started Jul 12 05:21:08 PM PDT 24
Finished Jul 12 05:21:10 PM PDT 24
Peak memory 205052 kb
Host smart-7f81f087-4abb-451c-9de9-38db739d8a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721258201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1721258201
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3268907272
Short name T1438
Test name
Test status
Simulation time 5058393314 ps
CPU time 73.88 seconds
Started Jul 12 05:21:05 PM PDT 24
Finished Jul 12 05:22:20 PM PDT 24
Peak memory 781692 kb
Host smart-0f975d76-a86c-4dc0-9a8e-848230076014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268907272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3268907272
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.3408019969
Short name T722
Test name
Test status
Simulation time 23320587855 ps
CPU time 116.72 seconds
Started Jul 12 05:21:06 PM PDT 24
Finished Jul 12 05:23:03 PM PDT 24
Peak memory 213392 kb
Host smart-630be7b3-f610-41ef-9ba6-b3e54e55ab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408019969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3408019969
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1201098708
Short name T589
Test name
Test status
Simulation time 2032666714 ps
CPU time 30.97 seconds
Started Jul 12 05:21:05 PM PDT 24
Finished Jul 12 05:21:37 PM PDT 24
Peak memory 365664 kb
Host smart-9abe929c-a811-4972-a0a1-32ce42b49fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201098708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1201098708
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2068566304
Short name T353
Test name
Test status
Simulation time 4074662820 ps
CPU time 35.98 seconds
Started Jul 12 05:21:12 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 213636 kb
Host smart-71ed8998-db87-4a50-b65c-02820260dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068566304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2068566304
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1857092162
Short name T354
Test name
Test status
Simulation time 4553398446 ps
CPU time 5.8 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:21 PM PDT 24
Peak memory 221776 kb
Host smart-15f8efa5-2a3f-4587-aec2-6278bf706d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857092162 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1857092162
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.1559873424
Short name T1004
Test name
Test status
Simulation time 2843603014 ps
CPU time 1.36 seconds
Started Jul 12 05:21:13 PM PDT 24
Finished Jul 12 05:21:16 PM PDT 24
Peak memory 205448 kb
Host smart-128705cb-67d2-4045-966f-90df78d0e027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559873424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.1559873424
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2077805575
Short name T8
Test name
Test status
Simulation time 337176130 ps
CPU time 1.29 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 205448 kb
Host smart-6478f819-286d-4223-bd30-22bd7431e2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077805575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2077805575
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1754910401
Short name T355
Test name
Test status
Simulation time 451352626 ps
CPU time 2.62 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:18 PM PDT 24
Peak memory 205344 kb
Host smart-4ad94e56-5dfb-437c-aca0-0d96055a37f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754910401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1754910401
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3023585453
Short name T775
Test name
Test status
Simulation time 151314008 ps
CPU time 1.29 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 205336 kb
Host smart-1b273ca7-8d66-4cdf-87f3-f4bbf658ca04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023585453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3023585453
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2259268359
Short name T1043
Test name
Test status
Simulation time 1393112446 ps
CPU time 8.35 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:24 PM PDT 24
Peak memory 229968 kb
Host smart-b97f815a-ce80-491c-b6cd-080590e6d012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259268359 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2259268359
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.570989583
Short name T555
Test name
Test status
Simulation time 18080020280 ps
CPU time 282.29 seconds
Started Jul 12 05:21:15 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 2776604 kb
Host smart-ee47656e-7bec-4446-b1fb-0b16526cb013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570989583 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.570989583
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.491873002
Short name T725
Test name
Test status
Simulation time 452772206 ps
CPU time 2.72 seconds
Started Jul 12 05:21:15 PM PDT 24
Finished Jul 12 05:21:19 PM PDT 24
Peak memory 213696 kb
Host smart-53d2dc32-456e-4690-bea9-040408299d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491873002 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_nack_acqfull.491873002
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.1067507373
Short name T930
Test name
Test status
Simulation time 2068992343 ps
CPU time 2.42 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 205408 kb
Host smart-548a26fd-93ab-43bd-9bac-9089971c999f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067507373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.1067507373
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.291655257
Short name T1534
Test name
Test status
Simulation time 1786784947 ps
CPU time 2.33 seconds
Started Jul 12 05:21:13 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 205240 kb
Host smart-0cadd40b-6779-49ed-a070-e98a71c644e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291655257 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_smbus_maxlen.291655257
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2677842255
Short name T1202
Test name
Test status
Simulation time 2563382402 ps
CPU time 19.58 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:21:34 PM PDT 24
Peak memory 213692 kb
Host smart-3c50c6b2-1390-4cc1-8faa-bb6e0973ecc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677842255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2677842255
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.554885810
Short name T1473
Test name
Test status
Simulation time 5855499968 ps
CPU time 23.14 seconds
Started Jul 12 05:21:13 PM PDT 24
Finished Jul 12 05:21:37 PM PDT 24
Peak memory 237872 kb
Host smart-f4ecc1b8-3f5d-4bd6-b711-e112268e1f0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554885810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.554885810
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1936548765
Short name T1205
Test name
Test status
Simulation time 34450116176 ps
CPU time 296.29 seconds
Started Jul 12 05:21:14 PM PDT 24
Finished Jul 12 05:26:11 PM PDT 24
Peak memory 3428328 kb
Host smart-603aff3e-7bea-44f3-b52a-f1018d1c159f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936548765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1936548765
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.184535007
Short name T515
Test name
Test status
Simulation time 5565371133 ps
CPU time 77.2 seconds
Started Jul 12 05:21:12 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 582304 kb
Host smart-78d2ba51-8e61-494d-ba72-b3f30d1d4403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184535007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.184535007
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.296572749
Short name T757
Test name
Test status
Simulation time 2672616944 ps
CPU time 7.11 seconds
Started Jul 12 05:21:11 PM PDT 24
Finished Jul 12 05:21:19 PM PDT 24
Peak memory 219680 kb
Host smart-ca963aab-373b-4676-84ef-3d0cc4d5d1ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296572749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.296572749
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1855088947
Short name T1535
Test name
Test status
Simulation time 59836989 ps
CPU time 1.16 seconds
Started Jul 12 05:21:12 PM PDT 24
Finished Jul 12 05:21:14 PM PDT 24
Peak memory 205336 kb
Host smart-1d9fd8f8-f8b7-4fe4-ba98-07e73ba16795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855088947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1855088947
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2895184307
Short name T820
Test name
Test status
Simulation time 17938561 ps
CPU time 0.67 seconds
Started Jul 12 05:21:32 PM PDT 24
Finished Jul 12 05:21:34 PM PDT 24
Peak memory 204656 kb
Host smart-44e157ce-fd48-4292-9308-5499738b714f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895184307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2895184307
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2161084272
Short name T545
Test name
Test status
Simulation time 570594712 ps
CPU time 1.53 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 213544 kb
Host smart-0e4ac4a8-6c3b-4e4e-8d75-e91ece92f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161084272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2161084272
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.708631547
Short name T817
Test name
Test status
Simulation time 1417326870 ps
CPU time 7.82 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 289800 kb
Host smart-bde10884-0c75-439f-835a-7d7ba88e1bc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708631547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.708631547
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2134249198
Short name T1233
Test name
Test status
Simulation time 5284608591 ps
CPU time 84.18 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:22:48 PM PDT 24
Peak memory 739740 kb
Host smart-6ae566aa-a665-47e6-b5cf-8c3b78e8c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134249198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2134249198
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.429092003
Short name T776
Test name
Test status
Simulation time 622241254 ps
CPU time 1.29 seconds
Started Jul 12 05:21:21 PM PDT 24
Finished Jul 12 05:21:23 PM PDT 24
Peak memory 205280 kb
Host smart-b5aece2f-0c96-452e-a65c-7c888d75a188
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429092003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.429092003
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3287127385
Short name T578
Test name
Test status
Simulation time 155251559 ps
CPU time 8.62 seconds
Started Jul 12 05:21:20 PM PDT 24
Finished Jul 12 05:21:29 PM PDT 24
Peak memory 205304 kb
Host smart-946141e7-3068-4a80-9742-c3934d73c94b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287127385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3287127385
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4077801051
Short name T663
Test name
Test status
Simulation time 3367337150 ps
CPU time 231.17 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 988488 kb
Host smart-47b4617d-3412-48b4-bece-aa591952e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077801051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4077801051
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_override.1376254765
Short name T1060
Test name
Test status
Simulation time 18628994 ps
CPU time 0.73 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:24 PM PDT 24
Peak memory 205052 kb
Host smart-637e2911-e37c-486c-921b-65935051e328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376254765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1376254765
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.152021848
Short name T743
Test name
Test status
Simulation time 25933693289 ps
CPU time 169.33 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 228928 kb
Host smart-959ca302-e56d-4eb4-8d99-45bfbe04b4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152021848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.152021848
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.2327645977
Short name T1329
Test name
Test status
Simulation time 142876025 ps
CPU time 1.11 seconds
Started Jul 12 05:21:21 PM PDT 24
Finished Jul 12 05:21:23 PM PDT 24
Peak memory 213436 kb
Host smart-281d5287-1fef-48fd-af45-e2f3be55a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327645977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2327645977
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1716896053
Short name T1124
Test name
Test status
Simulation time 4550627252 ps
CPU time 56.62 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:22:21 PM PDT 24
Peak memory 304524 kb
Host smart-62c1994f-c80a-4faf-a0dc-997209234191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716896053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1716896053
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1170586394
Short name T846
Test name
Test status
Simulation time 694083567 ps
CPU time 11.38 seconds
Started Jul 12 05:21:24 PM PDT 24
Finished Jul 12 05:21:36 PM PDT 24
Peak memory 229728 kb
Host smart-5c3444e7-5923-4113-b2b2-030d4df6b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170586394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1170586394
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3649691989
Short name T1346
Test name
Test status
Simulation time 2689248589 ps
CPU time 4.48 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:28 PM PDT 24
Peak memory 214156 kb
Host smart-6be92305-cb95-4f8a-8c85-9399b74ccc31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649691989 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3649691989
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.14720620
Short name T509
Test name
Test status
Simulation time 385414179 ps
CPU time 1.18 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 205260 kb
Host smart-e8cedb48-34e6-45a7-9f1c-6e75dc808ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720620 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_acq.14720620
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2972762904
Short name T89
Test name
Test status
Simulation time 521894960 ps
CPU time 1.15 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:25 PM PDT 24
Peak memory 205284 kb
Host smart-53c9ddb8-820d-41a8-9806-fb4abbb05457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972762904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2972762904
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1068749798
Short name T780
Test name
Test status
Simulation time 4565284715 ps
CPU time 2.77 seconds
Started Jul 12 05:21:21 PM PDT 24
Finished Jul 12 05:21:25 PM PDT 24
Peak memory 205484 kb
Host smart-22f0e92e-2092-46d9-a477-9eaec8125026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068749798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1068749798
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3811908722
Short name T918
Test name
Test status
Simulation time 2052301020 ps
CPU time 1.27 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 205212 kb
Host smart-51175f9a-91f6-4bcd-9762-11fd2c9f392a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811908722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3811908722
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3499930460
Short name T542
Test name
Test status
Simulation time 748848573 ps
CPU time 4.35 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:28 PM PDT 24
Peak memory 213572 kb
Host smart-9ef879c2-ead4-4789-b497-96e66d9e313b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499930460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3499930460
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.2702996373
Short name T856
Test name
Test status
Simulation time 594944177 ps
CPU time 2.81 seconds
Started Jul 12 05:21:28 PM PDT 24
Finished Jul 12 05:21:32 PM PDT 24
Peak memory 213524 kb
Host smart-930b66c7-a7fa-4f47-a42f-93aaac772f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702996373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.2702996373
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.1503834517
Short name T1417
Test name
Test status
Simulation time 587380979 ps
CPU time 2.65 seconds
Started Jul 12 05:21:28 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 205660 kb
Host smart-73c10d20-97be-4e24-a46e-a594b7aa4635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503834517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.1503834517
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.1691249432
Short name T159
Test name
Test status
Simulation time 458215574 ps
CPU time 2.25 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:21:56 PM PDT 24
Peak memory 205288 kb
Host smart-c141e5f2-2c5b-475d-9668-a578f9b6b362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691249432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.1691249432
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1882141454
Short name T1514
Test name
Test status
Simulation time 619430450 ps
CPU time 8.75 seconds
Started Jul 12 05:21:21 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 213468 kb
Host smart-ad3087b0-14bc-4047-afdb-f1442d78c884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882141454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1882141454
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2705016008
Short name T1140
Test name
Test status
Simulation time 2105118112 ps
CPU time 8.49 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:21:33 PM PDT 24
Peak memory 206164 kb
Host smart-8ca6d0d6-dab7-49e4-8389-759997a4e534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705016008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2705016008
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.4183249732
Short name T1216
Test name
Test status
Simulation time 52055739074 ps
CPU time 439.69 seconds
Started Jul 12 05:21:23 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 3571596 kb
Host smart-5ea123d1-ff8c-48e7-b51a-351b69a39db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183249732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.4183249732
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3289065940
Short name T72
Test name
Test status
Simulation time 2583079171 ps
CPU time 26.33 seconds
Started Jul 12 05:21:22 PM PDT 24
Finished Jul 12 05:21:49 PM PDT 24
Peak memory 324756 kb
Host smart-a1566e23-10dd-4bcf-83f5-fb55b2db54b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289065940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3289065940
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.4293698568
Short name T412
Test name
Test status
Simulation time 166096841 ps
CPU time 3.53 seconds
Started Jul 12 05:21:20 PM PDT 24
Finished Jul 12 05:21:24 PM PDT 24
Peak memory 205404 kb
Host smart-c137e380-ebaf-40c5-a84b-ce7116fc0524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293698568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.4293698568
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3297647372
Short name T1235
Test name
Test status
Simulation time 34267317 ps
CPU time 0.65 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 204664 kb
Host smart-8b131661-994c-40c9-a63f-0d1cdc3c82ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297647372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3297647372
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.382709381
Short name T868
Test name
Test status
Simulation time 391333956 ps
CPU time 2.89 seconds
Started Jul 12 05:21:28 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 213552 kb
Host smart-245cc883-40f9-460e-848c-97fb24ba5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382709381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.382709381
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2681449091
Short name T1272
Test name
Test status
Simulation time 290805485 ps
CPU time 7.18 seconds
Started Jul 12 05:21:29 PM PDT 24
Finished Jul 12 05:21:37 PM PDT 24
Peak memory 265492 kb
Host smart-7b5d690d-68cc-4059-88db-d2f53184240e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681449091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2681449091
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.36316454
Short name T1283
Test name
Test status
Simulation time 2264449629 ps
CPU time 154.99 seconds
Started Jul 12 05:21:27 PM PDT 24
Finished Jul 12 05:24:03 PM PDT 24
Peak memory 658464 kb
Host smart-36a866eb-0a58-4174-81cb-78d44782f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36316454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.36316454
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.368639928
Short name T40
Test name
Test status
Simulation time 408876686 ps
CPU time 0.91 seconds
Started Jul 12 05:21:28 PM PDT 24
Finished Jul 12 05:21:29 PM PDT 24
Peak memory 205124 kb
Host smart-99b842bd-e6d9-4c03-a61a-736f036fd976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368639928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.368639928
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3902094408
Short name T594
Test name
Test status
Simulation time 567139819 ps
CPU time 3.56 seconds
Started Jul 12 05:21:34 PM PDT 24
Finished Jul 12 05:21:38 PM PDT 24
Peak memory 205324 kb
Host smart-2e1c39d4-816e-48c4-bd24-76cd6f82110c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902094408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3902094408
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.4124618411
Short name T1448
Test name
Test status
Simulation time 58178402849 ps
CPU time 385.45 seconds
Started Jul 12 05:21:27 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 1540496 kb
Host smart-3215e7e8-5b7f-458b-be8e-f0df5e32a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124618411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.4124618411
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.4079320650
Short name T601
Test name
Test status
Simulation time 1535637783 ps
CPU time 15.99 seconds
Started Jul 12 05:21:39 PM PDT 24
Finished Jul 12 05:21:57 PM PDT 24
Peak memory 205272 kb
Host smart-bb41505e-3403-4235-b7bf-f6d6e1c36a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079320650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.4079320650
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.596567361
Short name T1255
Test name
Test status
Simulation time 63669785 ps
CPU time 0.63 seconds
Started Jul 12 05:23:42 PM PDT 24
Finished Jul 12 05:23:44 PM PDT 24
Peak memory 204936 kb
Host smart-6c8700a6-30ba-44ee-949a-becff0ea34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596567361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.596567361
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.395400325
Short name T15
Test name
Test status
Simulation time 6858644647 ps
CPU time 46.98 seconds
Started Jul 12 05:21:29 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 629716 kb
Host smart-2115c78f-3c29-4be7-8468-d8bd56bf547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395400325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.395400325
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.619372265
Short name T586
Test name
Test status
Simulation time 108154017 ps
CPU time 2.14 seconds
Started Jul 12 05:21:29 PM PDT 24
Finished Jul 12 05:21:32 PM PDT 24
Peak memory 205840 kb
Host smart-4e201f19-b298-45a4-93e1-6b65605eaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619372265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.619372265
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3760786100
Short name T1084
Test name
Test status
Simulation time 1884074681 ps
CPU time 17.94 seconds
Started Jul 12 05:21:29 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 263532 kb
Host smart-a9adea4b-42e1-4906-97c5-3ea2b730bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760786100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3760786100
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2353586935
Short name T241
Test name
Test status
Simulation time 69898748762 ps
CPU time 1145.68 seconds
Started Jul 12 05:21:30 PM PDT 24
Finished Jul 12 05:40:38 PM PDT 24
Peak memory 779584 kb
Host smart-ef469ccb-8b58-4e03-8525-5404aecb163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353586935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2353586935
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1285699872
Short name T305
Test name
Test status
Simulation time 666191423 ps
CPU time 11.54 seconds
Started Jul 12 05:21:30 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 221464 kb
Host smart-7e875217-cc96-454f-b118-5bb7d518ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285699872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1285699872
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.740984900
Short name T1256
Test name
Test status
Simulation time 8268610274 ps
CPU time 3.73 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:46 PM PDT 24
Peak memory 213676 kb
Host smart-58079e66-1a9d-4498-baee-58ddce7d4a8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740984900 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.740984900
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3262266110
Short name T1425
Test name
Test status
Simulation time 182173089 ps
CPU time 1.23 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 205336 kb
Host smart-32e2b61a-c676-4962-923d-62b30d059c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262266110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3262266110
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3618565588
Short name T96
Test name
Test status
Simulation time 206011933 ps
CPU time 1.31 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:42 PM PDT 24
Peak memory 205992 kb
Host smart-cd038a72-7d2c-46f7-8740-bcd29d10cb5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618565588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3618565588
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.184206266
Short name T471
Test name
Test status
Simulation time 2316999899 ps
CPU time 3.02 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 205744 kb
Host smart-3e64ee04-ea86-40f7-befb-de6550ed7b1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184206266 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.184206266
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3583932829
Short name T323
Test name
Test status
Simulation time 126591468 ps
CPU time 1.22 seconds
Started Jul 12 05:21:39 PM PDT 24
Finished Jul 12 05:21:43 PM PDT 24
Peak memory 205308 kb
Host smart-2863b6b9-dcc5-4cb3-9471-61f02f92eb67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583932829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3583932829
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1570107071
Short name T876
Test name
Test status
Simulation time 948732645 ps
CPU time 5.87 seconds
Started Jul 12 05:21:34 PM PDT 24
Finished Jul 12 05:21:41 PM PDT 24
Peak memory 213588 kb
Host smart-062fe90c-ee0e-4016-836e-0a0aacb92440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570107071 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1570107071
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3480350183
Short name T798
Test name
Test status
Simulation time 2928327297 ps
CPU time 25.41 seconds
Started Jul 12 05:21:30 PM PDT 24
Finished Jul 12 05:21:57 PM PDT 24
Peak memory 853008 kb
Host smart-5d979b95-67ce-444d-b543-cf7525b1b20a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480350183 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3480350183
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.172165288
Short name T423
Test name
Test status
Simulation time 654243026 ps
CPU time 3.21 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:21:41 PM PDT 24
Peak memory 213652 kb
Host smart-0e966c7c-bdef-48be-aacb-823e8a26c465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172165288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_nack_acqfull.172165288
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.624247706
Short name T1361
Test name
Test status
Simulation time 961207976 ps
CPU time 2.45 seconds
Started Jul 12 05:21:36 PM PDT 24
Finished Jul 12 05:21:39 PM PDT 24
Peak memory 205412 kb
Host smart-9a6c3315-9f91-4d46-8480-7bb67d3c13af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624247706 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.624247706
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.4047497681
Short name T768
Test name
Test status
Simulation time 535480084 ps
CPU time 2.29 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:42 PM PDT 24
Peak memory 205292 kb
Host smart-67c74f5b-ed61-4a8c-b866-ee4468014766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047497681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.4047497681
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3894543920
Short name T999
Test name
Test status
Simulation time 1026517102 ps
CPU time 32.32 seconds
Started Jul 12 05:21:35 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 213824 kb
Host smart-64b37eb2-aa03-48fd-aa97-ee4fd4c2e557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894543920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3894543920
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2393550803
Short name T715
Test name
Test status
Simulation time 1036982954 ps
CPU time 3.41 seconds
Started Jul 12 05:21:27 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 205448 kb
Host smart-4ec9e6d3-f604-4c71-bfc7-12c5a7342b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393550803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2393550803
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1850288704
Short name T57
Test name
Test status
Simulation time 24481855431 ps
CPU time 17.19 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:59 PM PDT 24
Peak memory 372396 kb
Host smart-bf07995a-98f9-409b-beae-43ba7eb4e2ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850288704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1850288704
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3651973623
Short name T1047
Test name
Test status
Simulation time 1308595677 ps
CPU time 5.25 seconds
Started Jul 12 05:21:30 PM PDT 24
Finished Jul 12 05:21:37 PM PDT 24
Peak memory 256824 kb
Host smart-7742bf77-2bd8-42c1-b306-4b6cf693e92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651973623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3651973623
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.717896024
Short name T727
Test name
Test status
Simulation time 5801214834 ps
CPU time 6.77 seconds
Started Jul 12 05:21:30 PM PDT 24
Finished Jul 12 05:21:37 PM PDT 24
Peak memory 213724 kb
Host smart-d1845af6-2506-429d-aede-33fa0ea6fa78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717896024 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.717896024
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.183479027
Short name T940
Test name
Test status
Simulation time 788396011 ps
CPU time 10.44 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:50 PM PDT 24
Peak memory 213580 kb
Host smart-dff93b26-2a5f-471a-951d-e61368e0e97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183479027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.183479027
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2393065326
Short name T1260
Test name
Test status
Simulation time 33378369 ps
CPU time 0.62 seconds
Started Jul 12 05:21:44 PM PDT 24
Finished Jul 12 05:21:45 PM PDT 24
Peak memory 204672 kb
Host smart-6ea1dc14-9dd1-4d02-a358-5942f8f91dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393065326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2393065326
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2788395029
Short name T1229
Test name
Test status
Simulation time 1068051479 ps
CPU time 4.21 seconds
Started Jul 12 05:21:39 PM PDT 24
Finished Jul 12 05:21:46 PM PDT 24
Peak memory 224004 kb
Host smart-2ad0c21b-dbea-4525-bbfb-e7bafe874861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788395029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2788395029
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.901171803
Short name T939
Test name
Test status
Simulation time 860941413 ps
CPU time 7.7 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:21:46 PM PDT 24
Peak memory 288832 kb
Host smart-0c1861ee-db35-45d5-812f-7a23a653b33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901171803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.901171803
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2648386366
Short name T1380
Test name
Test status
Simulation time 2479111941 ps
CPU time 61.87 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:22:44 PM PDT 24
Peak memory 428404 kb
Host smart-a7fa8689-90bb-4c75-b635-49437b6f5e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648386366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2648386366
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3645146383
Short name T1423
Test name
Test status
Simulation time 5237014365 ps
CPU time 177.93 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:24:35 PM PDT 24
Peak memory 741876 kb
Host smart-8c91da8c-587a-47d8-8131-43dea548ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645146383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3645146383
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1056709889
Short name T1017
Test name
Test status
Simulation time 439872685 ps
CPU time 6.91 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 224264 kb
Host smart-18fb712e-77c5-42fe-a83f-07c80c4a1b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056709889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1056709889
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.130679844
Short name T1011
Test name
Test status
Simulation time 20432083787 ps
CPU time 373.65 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 1460384 kb
Host smart-cd57c7ad-44ea-4f6f-bd4c-e6b6ba7c7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130679844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.130679844
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1807552763
Short name T994
Test name
Test status
Simulation time 545017495 ps
CPU time 4.45 seconds
Started Jul 12 05:21:48 PM PDT 24
Finished Jul 12 05:21:53 PM PDT 24
Peak memory 205292 kb
Host smart-ef323f2a-52e5-4f3c-abb8-59e2fcfc100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807552763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1807552763
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.3965277310
Short name T74
Test name
Test status
Simulation time 25538357 ps
CPU time 0.67 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:42 PM PDT 24
Peak memory 205072 kb
Host smart-a691b0a6-b486-49b1-a34f-1bddd9799d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965277310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3965277310
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3313182587
Short name T1533
Test name
Test status
Simulation time 25729504590 ps
CPU time 531.1 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 2700992 kb
Host smart-047ca3dc-bb7f-4115-aa7f-708a03351083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313182587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3313182587
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.943185782
Short name T1357
Test name
Test status
Simulation time 767410398 ps
CPU time 6.41 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 205192 kb
Host smart-66c1a001-5a20-49f0-a69a-c3ee3fbd3e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943185782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.943185782
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.4108566763
Short name T511
Test name
Test status
Simulation time 3766660896 ps
CPU time 36.92 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 365480 kb
Host smart-0cb6d96e-0693-4a55-93a0-702a69d4aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108566763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.4108566763
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1545509075
Short name T1217
Test name
Test status
Simulation time 466230918 ps
CPU time 8.28 seconds
Started Jul 12 05:21:39 PM PDT 24
Finished Jul 12 05:21:50 PM PDT 24
Peak memory 213504 kb
Host smart-a87576c5-1e01-4ddc-8986-9491f57a8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545509075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1545509075
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.156404597
Short name T495
Test name
Test status
Simulation time 1605771683 ps
CPU time 4.44 seconds
Started Jul 12 05:21:41 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 213664 kb
Host smart-83b5ab2d-1874-4b42-8e43-2b29cc2e725d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156404597 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.156404597
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1860457969
Short name T404
Test name
Test status
Simulation time 394087856 ps
CPU time 0.91 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:21:38 PM PDT 24
Peak memory 205320 kb
Host smart-941a972c-360b-4551-81b1-4578a2b368e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860457969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1860457969
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.692465693
Short name T361
Test name
Test status
Simulation time 824174739 ps
CPU time 1.8 seconds
Started Jul 12 05:21:42 PM PDT 24
Finished Jul 12 05:21:45 PM PDT 24
Peak memory 211028 kb
Host smart-5891110b-0483-481a-bea3-b31b7165b014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692465693 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.692465693
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.594663037
Short name T710
Test name
Test status
Simulation time 331741746 ps
CPU time 1.59 seconds
Started Jul 12 05:21:42 PM PDT 24
Finished Jul 12 05:21:44 PM PDT 24
Peak memory 205144 kb
Host smart-c67917c8-7fd6-482a-9a79-2ab117227efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594663037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.594663037
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.1056088768
Short name T806
Test name
Test status
Simulation time 36611145 ps
CPU time 0.75 seconds
Started Jul 12 05:21:43 PM PDT 24
Finished Jul 12 05:21:44 PM PDT 24
Peak memory 205132 kb
Host smart-dce06039-3a63-40d9-b04b-29fe5e78479d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056088768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.1056088768
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.974315122
Short name T738
Test name
Test status
Simulation time 2483197548 ps
CPU time 7.73 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 230076 kb
Host smart-78478a36-54f1-4a9b-b46d-8ea346868fc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974315122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.974315122
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.102603558
Short name T561
Test name
Test status
Simulation time 10262246001 ps
CPU time 55.39 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:22:36 PM PDT 24
Peak memory 985052 kb
Host smart-6ef406ff-5d02-40bc-b0a3-fee829fb989e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102603558 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.102603558
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1587742887
Short name T765
Test name
Test status
Simulation time 663079133 ps
CPU time 3.36 seconds
Started Jul 12 05:21:45 PM PDT 24
Finished Jul 12 05:21:49 PM PDT 24
Peak memory 213676 kb
Host smart-ad742547-f11b-4897-917f-a809e2cb06bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587742887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1587742887
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.1304281763
Short name T1177
Test name
Test status
Simulation time 3209433469 ps
CPU time 3.01 seconds
Started Jul 12 05:21:45 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 205504 kb
Host smart-f39c6169-254d-4904-a297-5cf5655e6022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304281763 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.1304281763
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.176947474
Short name T683
Test name
Test status
Simulation time 392315582 ps
CPU time 2.06 seconds
Started Jul 12 05:21:44 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 205300 kb
Host smart-73ab6f7c-71d5-452e-9d32-116953bceb63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176947474 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_smbus_maxlen.176947474
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2462868266
Short name T1032
Test name
Test status
Simulation time 1830263379 ps
CPU time 7.44 seconds
Started Jul 12 05:21:38 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 213600 kb
Host smart-350571e3-589e-41d4-a4a0-f7e6254f600d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462868266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2462868266
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2532940742
Short name T1242
Test name
Test status
Simulation time 5731254391 ps
CPU time 16.22 seconds
Started Jul 12 05:21:37 PM PDT 24
Finished Jul 12 05:21:55 PM PDT 24
Peak memory 220940 kb
Host smart-c21d4408-d71b-4514-97af-72ac2dca07b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532940742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2532940742
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3357228777
Short name T882
Test name
Test status
Simulation time 10044910052 ps
CPU time 6.06 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:48 PM PDT 24
Peak memory 205512 kb
Host smart-a543a199-84b0-4d0b-97c5-85cd8ada2be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357228777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3357228777
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2041898527
Short name T888
Test name
Test status
Simulation time 4190700256 ps
CPU time 4.5 seconds
Started Jul 12 05:21:40 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 245260 kb
Host smart-21a26fc7-baf8-48d3-a4b1-0a02814c1962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041898527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2041898527
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.125909801
Short name T577
Test name
Test status
Simulation time 9045711031 ps
CPU time 7.43 seconds
Started Jul 12 05:21:41 PM PDT 24
Finished Jul 12 05:21:50 PM PDT 24
Peak memory 232432 kb
Host smart-274ae099-a2fb-4a7a-8609-f4c50034c499
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125909801 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.125909801
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.3394719499
Short name T1321
Test name
Test status
Simulation time 99620623 ps
CPU time 2.31 seconds
Started Jul 12 05:21:43 PM PDT 24
Finished Jul 12 05:21:46 PM PDT 24
Peak memory 205352 kb
Host smart-0105a7b9-256d-4fce-ad38-24f98404e4ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394719499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3394719499
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2280631513
Short name T472
Test name
Test status
Simulation time 35984520 ps
CPU time 0.68 seconds
Started Jul 12 05:21:55 PM PDT 24
Finished Jul 12 05:21:57 PM PDT 24
Peak memory 204828 kb
Host smart-4efecd8b-2088-4155-a5c9-ae3527b6028c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280631513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2280631513
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2904385401
Short name T1286
Test name
Test status
Simulation time 111228016 ps
CPU time 2.74 seconds
Started Jul 12 05:21:51 PM PDT 24
Finished Jul 12 05:21:55 PM PDT 24
Peak memory 213560 kb
Host smart-a881d2c5-5a8f-45dd-af10-a6431ecf786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904385401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2904385401
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.537045856
Short name T297
Test name
Test status
Simulation time 533477478 ps
CPU time 14.55 seconds
Started Jul 12 05:21:44 PM PDT 24
Finished Jul 12 05:21:58 PM PDT 24
Peak memory 263296 kb
Host smart-7515708d-4772-491c-bac2-4f4613ae0d6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537045856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.537045856
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3168896106
Short name T1053
Test name
Test status
Simulation time 3594437440 ps
CPU time 115.75 seconds
Started Jul 12 05:21:47 PM PDT 24
Finished Jul 12 05:23:44 PM PDT 24
Peak memory 586232 kb
Host smart-69185930-ade3-40a2-b6ef-0cab28426378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168896106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3168896106
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1115532982
Short name T1227
Test name
Test status
Simulation time 4731997712 ps
CPU time 68.51 seconds
Started Jul 12 05:21:45 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 652936 kb
Host smart-faaa55b5-72c8-4197-be9a-3af2cfc6c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115532982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1115532982
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3197923001
Short name T11
Test name
Test status
Simulation time 526432788 ps
CPU time 1.23 seconds
Started Jul 12 05:22:09 PM PDT 24
Finished Jul 12 05:22:11 PM PDT 24
Peak memory 205176 kb
Host smart-a292fad4-02d6-4c71-9447-35bb0b8a25a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197923001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3197923001
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2980763046
Short name T165
Test name
Test status
Simulation time 3330131233 ps
CPU time 11.74 seconds
Started Jul 12 05:21:46 PM PDT 24
Finished Jul 12 05:21:58 PM PDT 24
Peak memory 245324 kb
Host smart-63a2f401-965b-4954-b6cc-d9ff43283055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980763046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2980763046
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3752464992
Short name T837
Test name
Test status
Simulation time 3231482040 ps
CPU time 85.91 seconds
Started Jul 12 05:22:06 PM PDT 24
Finished Jul 12 05:23:32 PM PDT 24
Peak memory 1000884 kb
Host smart-55b2d966-0c75-4411-ab08-df691d68d5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752464992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3752464992
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1998825933
Short name T740
Test name
Test status
Simulation time 422471284 ps
CPU time 6.73 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:22:01 PM PDT 24
Peak memory 205228 kb
Host smart-9a17d7ef-0a0b-44ce-8be6-663789868023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998825933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1998825933
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.1878231065
Short name T1135
Test name
Test status
Simulation time 18125751 ps
CPU time 0.68 seconds
Started Jul 12 05:21:42 PM PDT 24
Finished Jul 12 05:21:44 PM PDT 24
Peak memory 205092 kb
Host smart-f257d902-afdd-4f60-ac54-9801f349f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878231065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1878231065
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.850932328
Short name T1391
Test name
Test status
Simulation time 12583366848 ps
CPU time 67.84 seconds
Started Jul 12 05:21:44 PM PDT 24
Finished Jul 12 05:22:52 PM PDT 24
Peak memory 205356 kb
Host smart-15740691-5689-4a53-bcc0-226df99d7040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850932328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.850932328
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.4204467532
Short name T969
Test name
Test status
Simulation time 1412155492 ps
CPU time 11.5 seconds
Started Jul 12 05:21:50 PM PDT 24
Finished Jul 12 05:22:02 PM PDT 24
Peak memory 338636 kb
Host smart-d49ad8dd-0251-4d71-b3b9-2e68d6a28751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204467532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.4204467532
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1524456044
Short name T936
Test name
Test status
Simulation time 1975689072 ps
CPU time 49.29 seconds
Started Jul 12 05:21:43 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 330832 kb
Host smart-553ed000-f083-4430-849b-061a62ae1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524456044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1524456044
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.845343422
Short name T452
Test name
Test status
Simulation time 619714969 ps
CPU time 18.75 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:22:13 PM PDT 24
Peak memory 213460 kb
Host smart-39af57f5-f2d8-47b7-b1ed-9bc08cc5e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845343422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.845343422
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3248897654
Short name T371
Test name
Test status
Simulation time 1123885451 ps
CPU time 5.87 seconds
Started Jul 12 05:21:51 PM PDT 24
Finished Jul 12 05:21:58 PM PDT 24
Peak memory 213684 kb
Host smart-430dba61-35c3-4c85-b5a8-f3b3bc2b7e8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248897654 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3248897654
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.955161947
Short name T478
Test name
Test status
Simulation time 249456920 ps
CPU time 0.77 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:21:55 PM PDT 24
Peak memory 205316 kb
Host smart-6e052ed0-5c9e-41b5-b4ca-1f3b511d954e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955161947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.955161947
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2865387872
Short name T342
Test name
Test status
Simulation time 245623414 ps
CPU time 1.46 seconds
Started Jul 12 05:21:52 PM PDT 24
Finished Jul 12 05:21:54 PM PDT 24
Peak memory 205308 kb
Host smart-1125bc6a-7811-42d1-afad-458babfaa42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865387872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2865387872
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.1977165934
Short name T154
Test name
Test status
Simulation time 963327167 ps
CPU time 2.98 seconds
Started Jul 12 05:21:50 PM PDT 24
Finished Jul 12 05:21:54 PM PDT 24
Peak memory 205400 kb
Host smart-0ccb57c5-1776-4e04-b833-25798d7c8218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977165934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.1977165934
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.415403430
Short name T652
Test name
Test status
Simulation time 1577765296 ps
CPU time 1.06 seconds
Started Jul 12 05:21:54 PM PDT 24
Finished Jul 12 05:21:57 PM PDT 24
Peak memory 205264 kb
Host smart-66227a19-72c5-4fd3-ba65-fac21440ae25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415403430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.415403430
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1110673175
Short name T714
Test name
Test status
Simulation time 696064170 ps
CPU time 4.45 seconds
Started Jul 12 05:21:55 PM PDT 24
Finished Jul 12 05:22:01 PM PDT 24
Peak memory 216256 kb
Host smart-d4faa587-fa19-496c-9354-eeec08e200f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110673175 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1110673175
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2023757248
Short name T67
Test name
Test status
Simulation time 15738325101 ps
CPU time 194.67 seconds
Started Jul 12 05:21:50 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 2283704 kb
Host smart-943d3c2c-61aa-4faf-91e5-a79427f03aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023757248 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2023757248
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.2839157388
Short name T1046
Test name
Test status
Simulation time 9495302463 ps
CPU time 2.82 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:21:57 PM PDT 24
Peak memory 213676 kb
Host smart-f6564c33-975b-45d8-a895-f8e658810921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839157388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.2839157388
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.3149006370
Short name T913
Test name
Test status
Simulation time 1146026501 ps
CPU time 2.68 seconds
Started Jul 12 05:21:56 PM PDT 24
Finished Jul 12 05:22:00 PM PDT 24
Peak memory 205368 kb
Host smart-ea9cee57-c824-4474-8927-7e28f2df36c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149006370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.3149006370
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.1396327386
Short name T622
Test name
Test status
Simulation time 495948246 ps
CPU time 2.44 seconds
Started Jul 12 05:21:49 PM PDT 24
Finished Jul 12 05:21:51 PM PDT 24
Peak memory 205292 kb
Host smart-1f299fc0-1c1c-4567-acd0-5582371eaa47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396327386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.1396327386
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3613775218
Short name T5
Test name
Test status
Simulation time 1340873621 ps
CPU time 15.86 seconds
Started Jul 12 05:21:55 PM PDT 24
Finished Jul 12 05:22:12 PM PDT 24
Peak memory 213636 kb
Host smart-7a9a5eb0-4ddb-4d86-a06f-7e7fdade3754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613775218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3613775218
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2602397443
Short name T651
Test name
Test status
Simulation time 5180839047 ps
CPU time 61.48 seconds
Started Jul 12 05:21:50 PM PDT 24
Finished Jul 12 05:22:52 PM PDT 24
Peak memory 216584 kb
Host smart-e5c94492-0b29-4487-ae70-34aeebb49f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602397443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2602397443
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3527033310
Short name T1382
Test name
Test status
Simulation time 9028876765 ps
CPU time 5.64 seconds
Started Jul 12 05:21:55 PM PDT 24
Finished Jul 12 05:22:02 PM PDT 24
Peak memory 205556 kb
Host smart-cedaeb3b-97d7-40cc-b57d-ac8bf92cbc96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527033310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3527033310
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3730676741
Short name T576
Test name
Test status
Simulation time 1548564639 ps
CPU time 10.26 seconds
Started Jul 12 05:21:49 PM PDT 24
Finished Jul 12 05:22:01 PM PDT 24
Peak memory 319384 kb
Host smart-9cea6a33-c569-48ee-9122-7065de7db07f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730676741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3730676741
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.590267741
Short name T1362
Test name
Test status
Simulation time 4863759934 ps
CPU time 7.53 seconds
Started Jul 12 05:21:55 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 221584 kb
Host smart-6a13df35-970e-4f20-a46e-5c2f67fb528e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590267741 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.590267741
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3020060881
Short name T1445
Test name
Test status
Simulation time 1304392104 ps
CPU time 16.33 seconds
Started Jul 12 05:21:52 PM PDT 24
Finished Jul 12 05:22:09 PM PDT 24
Peak memory 205364 kb
Host smart-1c0ed96c-8c80-4115-8d41-e895df755c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020060881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3020060881
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3856186022
Short name T1167
Test name
Test status
Simulation time 17169303 ps
CPU time 0.7 seconds
Started Jul 12 05:22:03 PM PDT 24
Finished Jul 12 05:22:05 PM PDT 24
Peak memory 204740 kb
Host smart-70929a06-bbcc-429c-b901-77460686f0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856186022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3856186022
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.796427816
Short name T1180
Test name
Test status
Simulation time 1460660748 ps
CPU time 12.7 seconds
Started Jul 12 05:21:57 PM PDT 24
Finished Jul 12 05:22:12 PM PDT 24
Peak memory 225288 kb
Host smart-0f407787-2c16-46ed-9542-71722bd88a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796427816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.796427816
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1702920182
Short name T1087
Test name
Test status
Simulation time 1924486207 ps
CPU time 9.17 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 314096 kb
Host smart-d76f04ac-b1db-459d-b8b0-a4f6ff051204
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702920182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1702920182
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4241699191
Short name T745
Test name
Test status
Simulation time 2116094316 ps
CPU time 45.23 seconds
Started Jul 12 05:21:52 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 398212 kb
Host smart-15988b8f-6201-4f65-8066-22fc4a690d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241699191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4241699191
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2862113325
Short name T872
Test name
Test status
Simulation time 1637182702 ps
CPU time 39.4 seconds
Started Jul 12 05:21:54 PM PDT 24
Finished Jul 12 05:22:34 PM PDT 24
Peak memory 528128 kb
Host smart-2c1540ad-627f-466d-9bde-2064be08ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862113325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2862113325
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3579866570
Short name T873
Test name
Test status
Simulation time 83900096 ps
CPU time 0.98 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:21:55 PM PDT 24
Peak memory 205112 kb
Host smart-43eb7d72-afa8-43b1-b833-7fe1155980ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579866570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3579866570
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4083842767
Short name T895
Test name
Test status
Simulation time 336531746 ps
CPU time 3.94 seconds
Started Jul 12 05:21:49 PM PDT 24
Finished Jul 12 05:21:54 PM PDT 24
Peak memory 205276 kb
Host smart-af48e449-c95c-4b2d-ad89-85573c53a184
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083842767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4083842767
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.897620644
Short name T1150
Test name
Test status
Simulation time 10673491955 ps
CPU time 73.02 seconds
Started Jul 12 05:21:53 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 869896 kb
Host smart-2b98d9ef-5986-4c5a-bc9d-cded9dd98565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897620644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.897620644
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1600729259
Short name T1387
Test name
Test status
Simulation time 290408700 ps
CPU time 3.79 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:22:06 PM PDT 24
Peak memory 205276 kb
Host smart-d6a92d19-6709-4c17-88fc-412b23bc86e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600729259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1600729259
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.1502767767
Short name T1413
Test name
Test status
Simulation time 33797998 ps
CPU time 0.67 seconds
Started Jul 12 05:21:56 PM PDT 24
Finished Jul 12 05:21:58 PM PDT 24
Peak memory 205096 kb
Host smart-00d4a2e5-0d60-496a-94b5-cfdeebe45a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502767767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1502767767
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2582610741
Short name T1343
Test name
Test status
Simulation time 565745903 ps
CPU time 25.37 seconds
Started Jul 12 05:21:49 PM PDT 24
Finished Jul 12 05:22:16 PM PDT 24
Peak memory 273836 kb
Host smart-fd3aef1c-1db4-45e7-83a7-e5283fd41522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582610741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2582610741
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2486646015
Short name T854
Test name
Test status
Simulation time 2346103106 ps
CPU time 14.91 seconds
Started Jul 12 05:21:58 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 363796 kb
Host smart-c0e7b97f-7e74-4bb6-a22e-048482744f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486646015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2486646015
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2843066280
Short name T1137
Test name
Test status
Simulation time 5843474208 ps
CPU time 34.85 seconds
Started Jul 12 05:21:59 PM PDT 24
Finished Jul 12 05:22:35 PM PDT 24
Peak memory 213652 kb
Host smart-7a012cda-1e28-406a-91c7-cadf75041631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843066280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2843066280
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2152760169
Short name T405
Test name
Test status
Simulation time 1102608482 ps
CPU time 5.39 seconds
Started Jul 12 05:21:57 PM PDT 24
Finished Jul 12 05:22:04 PM PDT 24
Peak memory 218880 kb
Host smart-01485bbb-9dd2-47ea-b59e-42749488a11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152760169 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2152760169
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.394196357
Short name T1531
Test name
Test status
Simulation time 232350511 ps
CPU time 1.22 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:22:04 PM PDT 24
Peak memory 205236 kb
Host smart-df29f217-afe9-491e-aa3d-190b375bee00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394196357 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.394196357
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.218234125
Short name T1040
Test name
Test status
Simulation time 177944852 ps
CPU time 0.96 seconds
Started Jul 12 05:22:01 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 205320 kb
Host smart-1272bd88-955d-4482-8ea3-428ba016481c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218234125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.218234125
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3899283582
Short name T476
Test name
Test status
Simulation time 378538616 ps
CPU time 2.29 seconds
Started Jul 12 05:21:58 PM PDT 24
Finished Jul 12 05:22:02 PM PDT 24
Peak memory 205408 kb
Host smart-b8125135-2fd5-41be-921b-89453392e446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899283582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3899283582
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.563236332
Short name T568
Test name
Test status
Simulation time 271459309 ps
CPU time 1.16 seconds
Started Jul 12 05:21:56 PM PDT 24
Finished Jul 12 05:21:58 PM PDT 24
Peak memory 205252 kb
Host smart-f8c890d8-a568-43a8-81ef-9d71e444e250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563236332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.563236332
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4237207285
Short name T1494
Test name
Test status
Simulation time 2030568486 ps
CPU time 3.25 seconds
Started Jul 12 05:21:58 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 213668 kb
Host smart-21ecdc6e-4a3c-49af-b942-eb4f58cee7ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237207285 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4237207285
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1294560958
Short name T829
Test name
Test status
Simulation time 14198704233 ps
CPU time 12.52 seconds
Started Jul 12 05:21:57 PM PDT 24
Finished Jul 12 05:22:10 PM PDT 24
Peak memory 417596 kb
Host smart-270452fc-c442-4923-b497-e606428b272c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294560958 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1294560958
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.1608310501
Short name T1281
Test name
Test status
Simulation time 970871798 ps
CPU time 2.61 seconds
Started Jul 12 05:21:56 PM PDT 24
Finished Jul 12 05:22:00 PM PDT 24
Peak memory 213608 kb
Host smart-102ba703-8c73-4785-8914-926ab50e271a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608310501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.1608310501
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.1381509036
Short name T1066
Test name
Test status
Simulation time 472619396 ps
CPU time 2.52 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 205528 kb
Host smart-8fa50085-1dd2-4e0d-aa1a-9a56e7f3f7ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381509036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.1381509036
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.126625211
Short name T1465
Test name
Test status
Simulation time 2463662720 ps
CPU time 2.29 seconds
Started Jul 12 05:21:59 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 205344 kb
Host smart-5fdf61dd-5f2f-4426-8749-b137f9fe4960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126625211 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_smbus_maxlen.126625211
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1832177708
Short name T1342
Test name
Test status
Simulation time 2117676455 ps
CPU time 16.36 seconds
Started Jul 12 05:21:59 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 213576 kb
Host smart-3d62508b-cde2-4b89-9706-fbba24c2e7f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832177708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1832177708
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3106163815
Short name T1431
Test name
Test status
Simulation time 8235580328 ps
CPU time 36.91 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:22:40 PM PDT 24
Peak memory 231092 kb
Host smart-2423c078-2055-449d-8cf0-04b4e76dd803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106163815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3106163815
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.4060322624
Short name T907
Test name
Test status
Simulation time 63100302510 ps
CPU time 325.02 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:27:29 PM PDT 24
Peak memory 2788952 kb
Host smart-751a2611-2ff0-40b7-ba95-e307634d6b64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060322624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.4060322624
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2996057811
Short name T550
Test name
Test status
Simulation time 5394927056 ps
CPU time 7.63 seconds
Started Jul 12 05:21:59 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 220892 kb
Host smart-7e39c7fb-358e-47e0-8db7-32af6fa00d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996057811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2996057811
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.52202301
Short name T830
Test name
Test status
Simulation time 105288559 ps
CPU time 2.29 seconds
Started Jul 12 05:21:57 PM PDT 24
Finished Jul 12 05:22:01 PM PDT 24
Peak memory 205364 kb
Host smart-9da77165-e052-4a6c-a551-c20f7e52ec97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52202301 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.52202301
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1475195675
Short name T1420
Test name
Test status
Simulation time 20900714 ps
CPU time 0.63 seconds
Started Jul 12 05:18:53 PM PDT 24
Finished Jul 12 05:18:54 PM PDT 24
Peak memory 204624 kb
Host smart-c633ce97-4ebc-4d7a-9f1d-65ffbce9f969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475195675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1475195675
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1567269148
Short name T358
Test name
Test status
Simulation time 257666065 ps
CPU time 2.39 seconds
Started Jul 12 05:18:38 PM PDT 24
Finished Jul 12 05:18:42 PM PDT 24
Peak memory 213748 kb
Host smart-2239067b-0ec7-41a3-b988-20fe4a19011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567269148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1567269148
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2954997519
Short name T761
Test name
Test status
Simulation time 1196387058 ps
CPU time 6.12 seconds
Started Jul 12 05:18:31 PM PDT 24
Finished Jul 12 05:18:38 PM PDT 24
Peak memory 247256 kb
Host smart-e6594727-0c8a-475b-b438-d5e5297d65ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954997519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2954997519
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2065757848
Short name T1136
Test name
Test status
Simulation time 11141923665 ps
CPU time 105.83 seconds
Started Jul 12 05:18:31 PM PDT 24
Finished Jul 12 05:20:18 PM PDT 24
Peak memory 873860 kb
Host smart-22da3ff6-f8dc-43cf-962d-14c5ac196c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065757848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2065757848
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.378325088
Short name T855
Test name
Test status
Simulation time 2206561824 ps
CPU time 71.3 seconds
Started Jul 12 05:18:32 PM PDT 24
Finished Jul 12 05:19:45 PM PDT 24
Peak memory 700572 kb
Host smart-67cf4e26-913a-482c-9e2e-7204ac9180c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378325088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.378325088
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.720999900
Short name T1501
Test name
Test status
Simulation time 133255202 ps
CPU time 1.25 seconds
Started Jul 12 05:18:30 PM PDT 24
Finished Jul 12 05:18:32 PM PDT 24
Peak memory 205036 kb
Host smart-960b93e4-b0ed-44d1-b06b-4c8330f1f414
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720999900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.720999900
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.383298347
Short name T1477
Test name
Test status
Simulation time 651013678 ps
CPU time 10.43 seconds
Started Jul 12 05:18:34 PM PDT 24
Finished Jul 12 05:18:45 PM PDT 24
Peak memory 238952 kb
Host smart-f37ad4c0-b1b1-487e-8c56-d51ff8d50753
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383298347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.383298347
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3269292146
Short name T970
Test name
Test status
Simulation time 4288790869 ps
CPU time 104.2 seconds
Started Jul 12 05:18:36 PM PDT 24
Finished Jul 12 05:20:20 PM PDT 24
Peak memory 1163168 kb
Host smart-b9fb24c1-71d8-4526-9e52-1597e0b2ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269292146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3269292146
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2625144460
Short name T1553
Test name
Test status
Simulation time 718383519 ps
CPU time 5.48 seconds
Started Jul 12 05:18:45 PM PDT 24
Finished Jul 12 05:18:51 PM PDT 24
Peak memory 205328 kb
Host smart-52680702-fdf8-4404-9130-a4796f7c39bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625144460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2625144460
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.109433407
Short name T1317
Test name
Test status
Simulation time 211297288 ps
CPU time 0.69 seconds
Started Jul 12 05:18:31 PM PDT 24
Finished Jul 12 05:18:32 PM PDT 24
Peak memory 205108 kb
Host smart-d6fd9014-c9c2-4864-bd59-724375bbef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109433407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.109433407
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2847925679
Short name T343
Test name
Test status
Simulation time 150589990 ps
CPU time 1.59 seconds
Started Jul 12 05:18:38 PM PDT 24
Finished Jul 12 05:18:40 PM PDT 24
Peak memory 213444 kb
Host smart-eeb704ad-9bec-45c6-8e92-068b02e2a346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847925679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2847925679
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.686572854
Short name T448
Test name
Test status
Simulation time 8115538671 ps
CPU time 96.63 seconds
Started Jul 12 05:18:31 PM PDT 24
Finished Jul 12 05:20:09 PM PDT 24
Peak memory 359228 kb
Host smart-bed87d41-6a18-47fc-afd3-110ddcca9c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686572854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.686572854
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1344629063
Short name T256
Test name
Test status
Simulation time 24884201306 ps
CPU time 395.87 seconds
Started Jul 12 05:18:39 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 1612648 kb
Host smart-a00b1b0f-4b0b-4d2b-8713-c70093a89037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344629063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1344629063
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3415198307
Short name T1051
Test name
Test status
Simulation time 1444478287 ps
CPU time 13.51 seconds
Started Jul 12 05:18:38 PM PDT 24
Finished Jul 12 05:18:53 PM PDT 24
Peak memory 221248 kb
Host smart-9df662a6-93b4-4826-9485-90867490f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415198307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3415198307
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.677101478
Short name T188
Test name
Test status
Simulation time 1433639311 ps
CPU time 0.9 seconds
Started Jul 12 05:18:55 PM PDT 24
Finished Jul 12 05:18:56 PM PDT 24
Peak memory 223452 kb
Host smart-22f68571-7d6b-4ad5-b552-adb12cc6c5ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677101478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.677101478
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1206168436
Short name T692
Test name
Test status
Simulation time 4520920657 ps
CPU time 6.38 seconds
Started Jul 12 05:18:44 PM PDT 24
Finished Jul 12 05:18:52 PM PDT 24
Peak memory 215920 kb
Host smart-cb6729c5-3d99-430f-97b0-a884b59a53e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206168436 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1206168436
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3644900387
Short name T755
Test name
Test status
Simulation time 145104277 ps
CPU time 0.95 seconds
Started Jul 12 05:18:39 PM PDT 24
Finished Jul 12 05:18:41 PM PDT 24
Peak memory 205276 kb
Host smart-3622e108-b383-4c8b-a218-a42758af2846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644900387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3644900387
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3136482425
Short name T822
Test name
Test status
Simulation time 127056233 ps
CPU time 0.95 seconds
Started Jul 12 05:18:39 PM PDT 24
Finished Jul 12 05:18:41 PM PDT 24
Peak memory 205288 kb
Host smart-9f8aa5a5-b771-4a62-9c12-7975546907fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136482425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3136482425
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1102841909
Short name T1436
Test name
Test status
Simulation time 2066111784 ps
CPU time 2.55 seconds
Started Jul 12 05:18:44 PM PDT 24
Finished Jul 12 05:18:47 PM PDT 24
Peak memory 205396 kb
Host smart-5b9f0b50-4d0c-4521-b5e2-817c4eb0b863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102841909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1102841909
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.617636752
Short name T993
Test name
Test status
Simulation time 466041896 ps
CPU time 1.37 seconds
Started Jul 12 05:18:53 PM PDT 24
Finished Jul 12 05:18:56 PM PDT 24
Peak memory 205340 kb
Host smart-65260a53-c436-4bc4-8552-195aa277fae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617636752 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.617636752
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.190499306
Short name T416
Test name
Test status
Simulation time 6061315063 ps
CPU time 7.4 seconds
Started Jul 12 05:18:39 PM PDT 24
Finished Jul 12 05:18:47 PM PDT 24
Peak memory 213800 kb
Host smart-7773ba27-8b9c-4e68-b406-50e5a51217b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190499306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.190499306
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2294328848
Short name T654
Test name
Test status
Simulation time 19006307294 ps
CPU time 169.72 seconds
Started Jul 12 05:18:37 PM PDT 24
Finished Jul 12 05:21:28 PM PDT 24
Peak memory 2002352 kb
Host smart-5b66554f-64b4-4e85-bf07-a022a4ff03ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294328848 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2294328848
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.3133786515
Short name T1194
Test name
Test status
Simulation time 3424758952 ps
CPU time 2.91 seconds
Started Jul 12 05:18:54 PM PDT 24
Finished Jul 12 05:18:57 PM PDT 24
Peak memory 213564 kb
Host smart-e783028f-7c88-42f2-8a32-ff146775df7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133786515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.3133786515
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3329445038
Short name T730
Test name
Test status
Simulation time 1842561394 ps
CPU time 2.75 seconds
Started Jul 12 05:18:58 PM PDT 24
Finished Jul 12 05:19:01 PM PDT 24
Peak memory 205400 kb
Host smart-ced73a4a-2b2c-4eff-85a9-85ebdcbdcedb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329445038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3329445038
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.2105738249
Short name T867
Test name
Test status
Simulation time 1321682035 ps
CPU time 1.91 seconds
Started Jul 12 05:18:52 PM PDT 24
Finished Jul 12 05:18:55 PM PDT 24
Peak memory 205284 kb
Host smart-e006c51b-e439-4ba9-8bf6-153eb8374c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105738249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.2105738249
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2729140094
Short name T388
Test name
Test status
Simulation time 5384047124 ps
CPU time 7.77 seconds
Started Jul 12 05:18:41 PM PDT 24
Finished Jul 12 05:18:49 PM PDT 24
Peak memory 221768 kb
Host smart-4efc38fa-3eaf-4818-a198-af113dd7683c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729140094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2729140094
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1086896017
Short name T345
Test name
Test status
Simulation time 5943500834 ps
CPU time 17.31 seconds
Started Jul 12 05:18:39 PM PDT 24
Finished Jul 12 05:18:57 PM PDT 24
Peak memory 221804 kb
Host smart-a42c992c-18e0-43c6-8c8f-a216bb686cb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086896017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1086896017
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.52089294
Short name T428
Test name
Test status
Simulation time 20632346941 ps
CPU time 13.72 seconds
Started Jul 12 05:18:38 PM PDT 24
Finished Jul 12 05:18:53 PM PDT 24
Peak memory 205452 kb
Host smart-57c03198-b79d-4958-83ba-5c3bfff36c68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52089294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stress_wr.52089294
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1468804115
Short name T948
Test name
Test status
Simulation time 1433388055 ps
CPU time 7.56 seconds
Started Jul 12 05:18:42 PM PDT 24
Finished Jul 12 05:18:50 PM PDT 24
Peak memory 213688 kb
Host smart-9766877b-fc75-450d-be92-224e54d91441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468804115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1468804115
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.3273716947
Short name T368
Test name
Test status
Simulation time 87061663 ps
CPU time 1.54 seconds
Started Jul 12 05:18:52 PM PDT 24
Finished Jul 12 05:18:54 PM PDT 24
Peak memory 214612 kb
Host smart-2b868333-d48f-46ae-89ee-a95e798aed83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273716947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3273716947
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1431032371
Short name T129
Test name
Test status
Simulation time 17613079 ps
CPU time 0.64 seconds
Started Jul 12 05:22:10 PM PDT 24
Finished Jul 12 05:22:11 PM PDT 24
Peak memory 204608 kb
Host smart-0d2af1b2-46cf-4efb-a8e1-5fe0b28d70ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431032371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1431032371
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.779411840
Short name T31
Test name
Test status
Simulation time 1140138292 ps
CPU time 10.52 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:22:13 PM PDT 24
Peak memory 213532 kb
Host smart-2e4a9313-41a6-4f33-9d68-93aa325ba82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779411840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.779411840
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1064074746
Short name T369
Test name
Test status
Simulation time 704221580 ps
CPU time 8.83 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:22 PM PDT 24
Peak memory 237796 kb
Host smart-efc767e1-92ee-4db0-806b-1445af58e258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064074746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1064074746
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4159248892
Short name T900
Test name
Test status
Simulation time 9054281638 ps
CPU time 140.33 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 556672 kb
Host smart-b619b86a-9c93-4b78-b6fd-bdbdbcbd956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159248892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4159248892
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3513476204
Short name T1007
Test name
Test status
Simulation time 2785959102 ps
CPU time 107.47 seconds
Started Jul 12 05:22:08 PM PDT 24
Finished Jul 12 05:23:56 PM PDT 24
Peak memory 867720 kb
Host smart-4dd2748b-31a6-4c92-b339-d05ee4f28ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513476204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3513476204
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.4013412641
Short name T599
Test name
Test status
Simulation time 130145746 ps
CPU time 1.13 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:22:07 PM PDT 24
Peak memory 205056 kb
Host smart-823a397c-7a03-4a93-9138-bfe870a174ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013412641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.4013412641
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3466430539
Short name T1105
Test name
Test status
Simulation time 205929636 ps
CPU time 9.93 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:24 PM PDT 24
Peak memory 205444 kb
Host smart-8ae2a685-0bf8-4f00-be5e-ed9a792b0580
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466430539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3466430539
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1111580754
Short name T987
Test name
Test status
Simulation time 10217028235 ps
CPU time 174.46 seconds
Started Jul 12 05:22:09 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 1479500 kb
Host smart-5f8b6987-8179-46f4-8499-b551bf3defaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111580754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1111580754
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1865603328
Short name T432
Test name
Test status
Simulation time 559298903 ps
CPU time 23.11 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 205160 kb
Host smart-92014ac4-ef47-4b8a-8e5e-fed7bacf2eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865603328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1865603328
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2902776024
Short name T580
Test name
Test status
Simulation time 963894566 ps
CPU time 19.62 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:22:25 PM PDT 24
Peak memory 205140 kb
Host smart-5c9a3b02-b94c-4acc-ba04-f4fdf7c62074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902776024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2902776024
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1001689078
Short name T546
Test name
Test status
Simulation time 20118208502 ps
CPU time 28.57 seconds
Started Jul 12 05:22:07 PM PDT 24
Finished Jul 12 05:22:36 PM PDT 24
Peak memory 351244 kb
Host smart-2628c44b-6be8-4083-bfea-a85fdc1e2e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001689078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1001689078
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.481354486
Short name T1433
Test name
Test status
Simulation time 759869160 ps
CPU time 5.93 seconds
Started Jul 12 05:22:02 PM PDT 24
Finished Jul 12 05:22:09 PM PDT 24
Peak memory 213512 kb
Host smart-8cc72613-cf6c-4fb8-9e16-16df875fbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481354486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.481354486
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1138305176
Short name T427
Test name
Test status
Simulation time 1884702734 ps
CPU time 5.21 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:19 PM PDT 24
Peak memory 208360 kb
Host smart-745de3d6-2770-4a53-b327-adab6c0723f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138305176 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1138305176
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1031899350
Short name T1257
Test name
Test status
Simulation time 1266234610 ps
CPU time 1.28 seconds
Started Jul 12 05:22:09 PM PDT 24
Finished Jul 12 05:22:11 PM PDT 24
Peak memory 205400 kb
Host smart-3c369bcf-e9b3-4c5d-bd94-8284a4275993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031899350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1031899350
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1097133122
Short name T558
Test name
Test status
Simulation time 139647556 ps
CPU time 1.06 seconds
Started Jul 12 05:22:04 PM PDT 24
Finished Jul 12 05:22:06 PM PDT 24
Peak memory 205260 kb
Host smart-6bf4a410-0f60-4d74-95ad-a74749b8fd06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097133122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1097133122
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2024489848
Short name T1014
Test name
Test status
Simulation time 429041101 ps
CPU time 2.69 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 205344 kb
Host smart-f071660f-c27a-47a0-b3ce-cdacddf0e922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024489848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2024489848
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.368054602
Short name T1526
Test name
Test status
Simulation time 144620141 ps
CPU time 1.24 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:16 PM PDT 24
Peak memory 205256 kb
Host smart-0c00dbfb-f168-4b4a-8f35-fabf3edfe274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368054602 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.368054602
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2971362409
Short name T904
Test name
Test status
Simulation time 3942011390 ps
CPU time 3.69 seconds
Started Jul 12 05:22:04 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 213744 kb
Host smart-54d83b30-b3e2-4723-95ff-793f87b2fb09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971362409 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2971362409
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3717655760
Short name T1221
Test name
Test status
Simulation time 769700930 ps
CPU time 2.22 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 213640 kb
Host smart-d60708b7-f547-47c9-ba20-d2449adf04ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717655760 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3717655760
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.2605766191
Short name T863
Test name
Test status
Simulation time 482907561 ps
CPU time 2.81 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 213616 kb
Host smart-c913bf4b-d265-478c-8c36-8de1e3ef62e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605766191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.2605766191
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.1937714472
Short name T429
Test name
Test status
Simulation time 790662917 ps
CPU time 2.39 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:18 PM PDT 24
Peak memory 205432 kb
Host smart-f1bca684-7e45-4133-a4ce-b70b5818f4c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937714472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.1937714472
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.157930649
Short name T1110
Test name
Test status
Simulation time 499316088 ps
CPU time 2.24 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 205224 kb
Host smart-4e4ad12f-6906-4050-a8a3-7cad96a98593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157930649 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_smbus_maxlen.157930649
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.794401616
Short name T796
Test name
Test status
Simulation time 754374149 ps
CPU time 8.74 seconds
Started Jul 12 05:22:06 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 213496 kb
Host smart-7a98f37e-3824-4844-9375-aa91f58e3363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794401616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.794401616
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3807620713
Short name T481
Test name
Test status
Simulation time 1426504816 ps
CPU time 62.38 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:23:08 PM PDT 24
Peak memory 215028 kb
Host smart-4aaa0306-b755-44ca-b444-e129699495e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807620713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3807620713
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3033756880
Short name T539
Test name
Test status
Simulation time 27105291735 ps
CPU time 144.24 seconds
Started Jul 12 05:22:05 PM PDT 24
Finished Jul 12 05:24:30 PM PDT 24
Peak memory 1979700 kb
Host smart-ebcd7f58-426d-456a-bd6d-88129aa25b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033756880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3033756880
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2002837362
Short name T425
Test name
Test status
Simulation time 7858610657 ps
CPU time 7.72 seconds
Started Jul 12 05:22:06 PM PDT 24
Finished Jul 12 05:22:14 PM PDT 24
Peak memory 221756 kb
Host smart-e1eac60c-ac56-4b11-bfe2-5aa0a3c5c65e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002837362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2002837362
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1070887457
Short name T808
Test name
Test status
Simulation time 272474187 ps
CPU time 4.23 seconds
Started Jul 12 05:22:18 PM PDT 24
Finished Jul 12 05:22:23 PM PDT 24
Peak memory 205380 kb
Host smart-6ec2c771-2790-4423-89ba-f0539627b843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070887457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1070887457
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.98127850
Short name T962
Test name
Test status
Simulation time 15894192 ps
CPU time 0.6 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:35 PM PDT 24
Peak memory 204520 kb
Host smart-e440e1d8-522d-4272-b60e-8a1807a91536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98127850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.98127850
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3674686330
Short name T1070
Test name
Test status
Simulation time 307802107 ps
CPU time 2.33 seconds
Started Jul 12 05:22:11 PM PDT 24
Finished Jul 12 05:22:14 PM PDT 24
Peak memory 213556 kb
Host smart-03150ea5-cc8b-4d33-9438-a61f426ac5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674686330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3674686330
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3938950605
Short name T951
Test name
Test status
Simulation time 1284854891 ps
CPU time 12.23 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:28 PM PDT 24
Peak memory 311412 kb
Host smart-e9c04210-45fa-4c71-afa0-487745c92565
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938950605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3938950605
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.4230652074
Short name T44
Test name
Test status
Simulation time 3308550546 ps
CPU time 103.23 seconds
Started Jul 12 05:22:11 PM PDT 24
Finished Jul 12 05:23:55 PM PDT 24
Peak memory 886244 kb
Host smart-7d527b74-e791-4c42-8498-1d842c9ec3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230652074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.4230652074
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3400700079
Short name T379
Test name
Test status
Simulation time 5698144003 ps
CPU time 40.12 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:56 PM PDT 24
Peak memory 545264 kb
Host smart-3358c5ec-ab9d-4760-901e-c9c4378e4588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400700079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3400700079
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2048494710
Short name T252
Test name
Test status
Simulation time 1625750645 ps
CPU time 1.21 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 205024 kb
Host smart-e4b9775b-81e2-4396-bd42-b43575bfe03d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048494710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2048494710
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2772219765
Short name T565
Test name
Test status
Simulation time 349504821 ps
CPU time 4.45 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 236016 kb
Host smart-95994c5b-07a9-425f-8d07-69ab0d19ec6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772219765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2772219765
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2743872372
Short name T413
Test name
Test status
Simulation time 9560123064 ps
CPU time 361.54 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:28:14 PM PDT 24
Peak memory 1399480 kb
Host smart-17a8e996-965a-448f-8772-00a10fc2dceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743872372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2743872372
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.734938265
Short name T1344
Test name
Test status
Simulation time 453589118 ps
CPU time 7.13 seconds
Started Jul 12 05:22:21 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 205280 kb
Host smart-a5d1ca63-75f5-4ab3-a23c-bcf35a15d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734938265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.734938265
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.336486583
Short name T272
Test name
Test status
Simulation time 82686161 ps
CPU time 0.77 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 205052 kb
Host smart-83d232f9-be00-4640-9bee-d90d4aae2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336486583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.336486583
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.4015658019
Short name T1475
Test name
Test status
Simulation time 1011130278 ps
CPU time 30.88 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 213484 kb
Host smart-ce04c113-eaa7-466c-b362-4bdec4e14afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015658019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.4015658019
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3437679653
Short name T1447
Test name
Test status
Simulation time 96708011 ps
CPU time 1.46 seconds
Started Jul 12 05:22:15 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 222792 kb
Host smart-650b858e-4335-4f8a-80fb-88c20e7765fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437679653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3437679653
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3868006927
Short name T1261
Test name
Test status
Simulation time 6671189006 ps
CPU time 32.98 seconds
Started Jul 12 05:22:14 PM PDT 24
Finished Jul 12 05:22:48 PM PDT 24
Peak memory 334248 kb
Host smart-af17c720-3fcd-4282-9c85-f35028cc70ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868006927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3868006927
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.643120449
Short name T741
Test name
Test status
Simulation time 17636342665 ps
CPU time 20.09 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 229768 kb
Host smart-f082e660-84e9-4e5b-bf48-a113b8213f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643120449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.643120449
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2174941757
Short name T717
Test name
Test status
Simulation time 1012450730 ps
CPU time 5.08 seconds
Started Jul 12 05:22:18 PM PDT 24
Finished Jul 12 05:22:24 PM PDT 24
Peak memory 213612 kb
Host smart-264d13dc-d1cb-43a3-9632-a20e82119987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174941757 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2174941757
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1827732581
Short name T701
Test name
Test status
Simulation time 790602602 ps
CPU time 1.08 seconds
Started Jul 12 05:22:22 PM PDT 24
Finished Jul 12 05:22:24 PM PDT 24
Peak memory 205256 kb
Host smart-eaf11848-5caf-45c9-bd9e-70039961eafa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827732581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1827732581
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.4080591566
Short name T1297
Test name
Test status
Simulation time 256547847 ps
CPU time 0.81 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:35 PM PDT 24
Peak memory 205240 kb
Host smart-2de98822-2949-4bb1-be1d-cff0bfa38ef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080591566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.4080591566
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.2155773267
Short name T845
Test name
Test status
Simulation time 479419793 ps
CPU time 2.98 seconds
Started Jul 12 05:22:19 PM PDT 24
Finished Jul 12 05:22:23 PM PDT 24
Peak memory 205336 kb
Host smart-be1bd813-f3db-4dfa-87d7-6182c240b1c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155773267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.2155773267
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1317622617
Short name T1129
Test name
Test status
Simulation time 167310229 ps
CPU time 1.52 seconds
Started Jul 12 05:22:17 PM PDT 24
Finished Jul 12 05:22:20 PM PDT 24
Peak memory 205324 kb
Host smart-261b729c-2fe3-44fc-85d1-0cceddacf82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317622617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1317622617
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1824846129
Short name T411
Test name
Test status
Simulation time 1895223187 ps
CPU time 5.41 seconds
Started Jul 12 05:22:15 PM PDT 24
Finished Jul 12 05:22:21 PM PDT 24
Peak memory 213604 kb
Host smart-6b1e4695-11fe-4dcc-9c7d-24dce651ee21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824846129 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1824846129
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2962085712
Short name T732
Test name
Test status
Simulation time 14586452454 ps
CPU time 6.61 seconds
Started Jul 12 05:22:22 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 205568 kb
Host smart-86d1fa7a-6e04-49ee-879f-bde6a035b8d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962085712 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2962085712
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.1420138362
Short name T156
Test name
Test status
Simulation time 4262840119 ps
CPU time 3.23 seconds
Started Jul 12 05:22:19 PM PDT 24
Finished Jul 12 05:22:24 PM PDT 24
Peak memory 213680 kb
Host smart-f6424cd0-3157-4714-b10f-d26180f4b73e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420138362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.1420138362
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.942111463
Short name T50
Test name
Test status
Simulation time 960200799 ps
CPU time 2.76 seconds
Started Jul 12 05:22:19 PM PDT 24
Finished Jul 12 05:22:23 PM PDT 24
Peak memory 205312 kb
Host smart-c833dfbd-b90e-46d9-8023-fea1e39d5406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942111463 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.942111463
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.1607491798
Short name T333
Test name
Test status
Simulation time 3131802978 ps
CPU time 2.15 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:37 PM PDT 24
Peak memory 205324 kb
Host smart-2f2ff60c-b52b-400a-b30f-3a03ce2979aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607491798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.1607491798
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2965463477
Short name T805
Test name
Test status
Simulation time 756083507 ps
CPU time 23.6 seconds
Started Jul 12 05:22:11 PM PDT 24
Finished Jul 12 05:22:35 PM PDT 24
Peak memory 213608 kb
Host smart-378961e0-9a01-4d55-b114-f2ac85c36e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965463477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2965463477
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1219876285
Short name T99
Test name
Test status
Simulation time 1663121850 ps
CPU time 28.83 seconds
Started Jul 12 05:22:13 PM PDT 24
Finished Jul 12 05:22:43 PM PDT 24
Peak memory 239168 kb
Host smart-29862c82-f0fd-4074-ac52-52affea3e4cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219876285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1219876285
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.207029558
Short name T224
Test name
Test status
Simulation time 59006499911 ps
CPU time 252.56 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:26:26 PM PDT 24
Peak memory 2418180 kb
Host smart-b844fd6d-9f4c-4a04-98db-cfc50a3bffbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207029558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.207029558
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.709188714
Short name T1230
Test name
Test status
Simulation time 977923275 ps
CPU time 1.58 seconds
Started Jul 12 05:22:12 PM PDT 24
Finished Jul 12 05:22:15 PM PDT 24
Peak memory 213416 kb
Host smart-0c5cf42a-322e-49be-b01d-82db95dff81a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709188714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.709188714
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.192767886
Short name T1461
Test name
Test status
Simulation time 5879403943 ps
CPU time 6.45 seconds
Started Jul 12 05:22:20 PM PDT 24
Finished Jul 12 05:22:28 PM PDT 24
Peak memory 220012 kb
Host smart-59a2fea9-6fd3-404e-acdc-cf14ebfd9a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192767886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.192767886
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.1580932776
Short name T1158
Test name
Test status
Simulation time 419945611 ps
CPU time 6.22 seconds
Started Jul 12 05:22:19 PM PDT 24
Finished Jul 12 05:22:26 PM PDT 24
Peak memory 205404 kb
Host smart-8df70dc6-00c6-4ed5-bc23-ea3372faf9ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580932776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.1580932776
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1893363565
Short name T1258
Test name
Test status
Simulation time 27649223 ps
CPU time 0.65 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 204720 kb
Host smart-9e1c5e63-e124-48dc-808a-cd036d3943dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893363565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1893363565
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.4284725417
Short name T657
Test name
Test status
Simulation time 305218714 ps
CPU time 6.53 seconds
Started Jul 12 05:22:24 PM PDT 24
Finished Jul 12 05:22:31 PM PDT 24
Peak memory 265908 kb
Host smart-ecc980f8-144d-4280-b16a-d5b710285e88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284725417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.4284725417
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1564508202
Short name T644
Test name
Test status
Simulation time 2109061430 ps
CPU time 119.75 seconds
Started Jul 12 05:22:21 PM PDT 24
Finished Jul 12 05:24:22 PM PDT 24
Peak memory 494768 kb
Host smart-a058ac22-942d-448e-9733-a8fbab65dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564508202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1564508202
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1947177262
Short name T1120
Test name
Test status
Simulation time 2061449997 ps
CPU time 97.29 seconds
Started Jul 12 05:22:20 PM PDT 24
Finished Jul 12 05:23:58 PM PDT 24
Peak memory 552476 kb
Host smart-8d5f5bb9-8f4b-4252-bc4a-50d2cf165dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947177262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1947177262
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.1367271298
Short name T926
Test name
Test status
Simulation time 291436530 ps
CPU time 0.84 seconds
Started Jul 12 05:22:18 PM PDT 24
Finished Jul 12 05:22:19 PM PDT 24
Peak memory 205096 kb
Host smart-e1ff1dad-73dd-4758-b040-f9bc65a63c10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367271298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.1367271298
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.596561552
Short name T548
Test name
Test status
Simulation time 851436615 ps
CPU time 4.24 seconds
Started Jul 12 05:22:25 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 233964 kb
Host smart-2a3277a6-2949-496c-9cbe-a3353ac715e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596561552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
596561552
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4001299735
Short name T120
Test name
Test status
Simulation time 67013991149 ps
CPU time 169.56 seconds
Started Jul 12 05:22:22 PM PDT 24
Finished Jul 12 05:25:12 PM PDT 24
Peak memory 1574960 kb
Host smart-44a96627-934b-4670-b7f8-f5fdc7f18acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001299735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4001299735
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.757146179
Short name T1460
Test name
Test status
Simulation time 3478326141 ps
CPU time 25.6 seconds
Started Jul 12 05:22:26 PM PDT 24
Finished Jul 12 05:22:52 PM PDT 24
Peak memory 205412 kb
Host smart-f0b00137-40d3-4b82-bba3-c16c9b0cc73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757146179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.757146179
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.2803809574
Short name T1471
Test name
Test status
Simulation time 103786495 ps
CPU time 0.68 seconds
Started Jul 12 05:22:20 PM PDT 24
Finished Jul 12 05:22:22 PM PDT 24
Peak memory 205056 kb
Host smart-2293dac4-f997-4e87-a163-e30ff1d25475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803809574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2803809574
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1349631924
Short name T801
Test name
Test status
Simulation time 25923603537 ps
CPU time 235.1 seconds
Started Jul 12 05:22:18 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 1021168 kb
Host smart-91eda2f2-4070-497b-91a2-315665a23ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349631924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1349631924
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.1170326802
Short name T1416
Test name
Test status
Simulation time 237739089 ps
CPU time 2.68 seconds
Started Jul 12 05:22:19 PM PDT 24
Finished Jul 12 05:22:22 PM PDT 24
Peak memory 205188 kb
Host smart-9a0313a5-cad3-443e-8eab-236bfdb1d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170326802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1170326802
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1894459346
Short name T531
Test name
Test status
Simulation time 13085293565 ps
CPU time 31.69 seconds
Started Jul 12 05:22:32 PM PDT 24
Finished Jul 12 05:23:05 PM PDT 24
Peak memory 379096 kb
Host smart-afbbce5d-16a9-4835-aad8-c82d94429859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894459346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1894459346
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1232834953
Short name T242
Test name
Test status
Simulation time 94408207660 ps
CPU time 568.93 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:32:04 PM PDT 24
Peak memory 1697572 kb
Host smart-2c4cdf46-905d-4dff-a707-903132058064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232834953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1232834953
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1331833644
Short name T938
Test name
Test status
Simulation time 1198730234 ps
CPU time 18.01 seconds
Started Jul 12 05:22:24 PM PDT 24
Finished Jul 12 05:22:43 PM PDT 24
Peak memory 217192 kb
Host smart-48a55c22-89ac-4496-a90e-d76287c226c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331833644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1331833644
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.4153074701
Short name T1540
Test name
Test status
Simulation time 2333107892 ps
CPU time 3.1 seconds
Started Jul 12 05:22:26 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 213740 kb
Host smart-efae27f0-fa43-4559-a580-6d288367359c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153074701 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.4153074701
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1913441116
Short name T966
Test name
Test status
Simulation time 195078138 ps
CPU time 0.74 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 205316 kb
Host smart-39fadcac-3a5c-4006-8a0d-3b1865571af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913441116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1913441116
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1307902723
Short name T630
Test name
Test status
Simulation time 174391140 ps
CPU time 1.17 seconds
Started Jul 12 05:22:24 PM PDT 24
Finished Jul 12 05:22:26 PM PDT 24
Peak memory 205324 kb
Host smart-4f099a68-82b1-46c9-b360-6c65b34a5139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307902723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1307902723
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1714825595
Short name T968
Test name
Test status
Simulation time 4045157714 ps
CPU time 1.76 seconds
Started Jul 12 05:22:26 PM PDT 24
Finished Jul 12 05:22:28 PM PDT 24
Peak memory 205392 kb
Host smart-836472b6-37dc-4d37-afb5-2dd3f6cbbb0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714825595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1714825595
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2984408967
Short name T1307
Test name
Test status
Simulation time 162674119 ps
CPU time 1.37 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 205260 kb
Host smart-8508a0e1-5ad0-45b4-b6e6-7de1df0494aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984408967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2984408967
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1908969263
Short name T1352
Test name
Test status
Simulation time 824337053 ps
CPU time 4.75 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 213636 kb
Host smart-7bc04c06-2ea2-47f9-a9ac-1d4bf6a5ecd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908969263 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1908969263
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.4195423898
Short name T521
Test name
Test status
Simulation time 4028302714 ps
CPU time 3.41 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:32 PM PDT 24
Peak memory 205440 kb
Host smart-aae65180-a17b-4dbf-a33c-de51f3b416c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195423898 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.4195423898
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.1474181838
Short name T1570
Test name
Test status
Simulation time 2232603801 ps
CPU time 3.22 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 213680 kb
Host smart-c410f4d2-e77b-4220-b1c1-358b665e7040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474181838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.1474181838
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.4072160267
Short name T848
Test name
Test status
Simulation time 1954445031 ps
CPU time 2.6 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:31 PM PDT 24
Peak memory 205324 kb
Host smart-af899165-b0dd-4ca5-8539-d30f016e235b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072160267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.4072160267
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.2733175306
Short name T1082
Test name
Test status
Simulation time 1145824286 ps
CPU time 2.3 seconds
Started Jul 12 05:22:31 PM PDT 24
Finished Jul 12 05:22:34 PM PDT 24
Peak memory 205168 kb
Host smart-8549d2cb-84bc-4344-a4c0-348d3f82618d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733175306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.2733175306
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1414115724
Short name T70
Test name
Test status
Simulation time 1066556681 ps
CPU time 33.28 seconds
Started Jul 12 05:22:18 PM PDT 24
Finished Jul 12 05:22:53 PM PDT 24
Peak memory 213584 kb
Host smart-8d71853d-e898-40c2-a2c6-594173766939
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414115724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1414115724
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2130012261
Short name T1073
Test name
Test status
Simulation time 2944917885 ps
CPU time 30.65 seconds
Started Jul 12 05:22:54 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 205488 kb
Host smart-2be63190-7a53-401d-af78-af4a10b10920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130012261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2130012261
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2465907476
Short name T684
Test name
Test status
Simulation time 62662053775 ps
CPU time 947.12 seconds
Started Jul 12 05:22:33 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 5263156 kb
Host smart-22b6520a-399c-4c72-9123-6d48f1793421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465907476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2465907476
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2644527076
Short name T583
Test name
Test status
Simulation time 2308433562 ps
CPU time 5.3 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 254036 kb
Host smart-16320e3d-ff55-4324-9f97-d427c73af995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644527076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2644527076
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1528912108
Short name T709
Test name
Test status
Simulation time 10368355244 ps
CPU time 7.23 seconds
Started Jul 12 05:22:30 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 219588 kb
Host smart-6f3ebedf-0fe3-44a0-9f8a-b6b559643ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528912108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1528912108
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.819154767
Short name T720
Test name
Test status
Simulation time 88614478 ps
CPU time 1.66 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 205328 kb
Host smart-5d7f1a02-e641-4253-8f13-315bcffd5088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819154767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.819154767
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2984278848
Short name T875
Test name
Test status
Simulation time 38934040 ps
CPU time 0.67 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:36 PM PDT 24
Peak memory 204732 kb
Host smart-d8a2af46-d022-4219-9097-e4d6b3a67cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984278848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2984278848
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2439970241
Short name T1442
Test name
Test status
Simulation time 154321222 ps
CPU time 1.92 seconds
Started Jul 12 05:22:30 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 213524 kb
Host smart-07a8dffd-d3d1-4d78-bc1e-401ce6250f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439970241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2439970241
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.635946563
Short name T1509
Test name
Test status
Simulation time 750603204 ps
CPU time 4.18 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 242144 kb
Host smart-7805a393-1192-4846-b327-b7a5fa8906eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635946563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.635946563
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2143212008
Short name T656
Test name
Test status
Simulation time 1860525756 ps
CPU time 58.75 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:23:28 PM PDT 24
Peak memory 602000 kb
Host smart-4f45caad-44ac-42d2-b9a4-ea7de644c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143212008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2143212008
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3970700390
Short name T1324
Test name
Test status
Simulation time 4615233338 ps
CPU time 177.9 seconds
Started Jul 12 05:22:25 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 737076 kb
Host smart-7b674771-4d1e-4c89-a4fc-7998ca26bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970700390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3970700390
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2417801531
Short name T874
Test name
Test status
Simulation time 82389854 ps
CPU time 0.92 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:22:31 PM PDT 24
Peak memory 205120 kb
Host smart-6d030ee4-5b87-4f39-b142-7081ad3ad2b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417801531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2417801531
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3264256406
Short name T1198
Test name
Test status
Simulation time 17142677633 ps
CPU time 126.12 seconds
Started Jul 12 05:22:25 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 1216068 kb
Host smart-904528f6-0ab0-432e-8ed4-d0d035c5f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264256406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3264256406
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1401587266
Short name T680
Test name
Test status
Simulation time 159506082 ps
CPU time 2.44 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 205292 kb
Host smart-2f6aafc9-3a9b-4895-8d89-1c599f943f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401587266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1401587266
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.2343374936
Short name T470
Test name
Test status
Simulation time 39107996 ps
CPU time 0.66 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 205064 kb
Host smart-8546d71f-0759-44aa-9160-9e4628f51eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343374936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2343374936
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3531653649
Short name T200
Test name
Test status
Simulation time 3197559916 ps
CPU time 17.66 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:22:46 PM PDT 24
Peak memory 205836 kb
Host smart-821be12f-7d75-4412-bdb1-466afea13d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531653649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3531653649
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1156409815
Short name T1042
Test name
Test status
Simulation time 402060908 ps
CPU time 1.71 seconds
Started Jul 12 05:22:29 PM PDT 24
Finished Jul 12 05:22:32 PM PDT 24
Peak memory 225232 kb
Host smart-431f2af8-6a26-41d3-a143-d727810acdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156409815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1156409815
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.509141012
Short name T97
Test name
Test status
Simulation time 946712736 ps
CPU time 46.57 seconds
Started Jul 12 05:22:27 PM PDT 24
Finished Jul 12 05:23:15 PM PDT 24
Peak memory 318748 kb
Host smart-8d86b47e-ea43-4d98-8849-c21e63aa4ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509141012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.509141012
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3165391352
Short name T699
Test name
Test status
Simulation time 3217669571 ps
CPU time 13.66 seconds
Started Jul 12 05:22:26 PM PDT 24
Finished Jul 12 05:22:40 PM PDT 24
Peak memory 221764 kb
Host smart-9fa260c5-8e93-4448-86cd-f6daee29a8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165391352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3165391352
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3899569380
Short name T1550
Test name
Test status
Simulation time 1389283760 ps
CPU time 6.96 seconds
Started Jul 12 05:22:35 PM PDT 24
Finished Jul 12 05:22:43 PM PDT 24
Peak memory 213820 kb
Host smart-680c704e-9254-4294-9839-68fc24e29590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899569380 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3899569380
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.903212541
Short name T921
Test name
Test status
Simulation time 243967578 ps
CPU time 1.6 seconds
Started Jul 12 05:22:35 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 205436 kb
Host smart-aa96027c-6b11-4894-8d3a-7b3aef0b7f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903212541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.903212541
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.21137058
Short name T1472
Test name
Test status
Simulation time 261117432 ps
CPU time 1.13 seconds
Started Jul 12 05:22:35 PM PDT 24
Finished Jul 12 05:22:37 PM PDT 24
Peak memory 205256 kb
Host smart-1b2b1ac7-1db8-41aa-9206-00306ce8b85a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21137058 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_fifo_reset_tx.21137058
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2197998476
Short name T824
Test name
Test status
Simulation time 573125903 ps
CPU time 3.14 seconds
Started Jul 12 05:22:32 PM PDT 24
Finished Jul 12 05:22:37 PM PDT 24
Peak memory 205484 kb
Host smart-2aa2605f-020f-478f-a382-e103e7223796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197998476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2197998476
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.2692460086
Short name T1054
Test name
Test status
Simulation time 219841539 ps
CPU time 1.15 seconds
Started Jul 12 05:22:32 PM PDT 24
Finished Jul 12 05:22:33 PM PDT 24
Peak memory 205308 kb
Host smart-e41e43d3-dedf-4da7-9ad2-e6af04a6a1bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692460086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.2692460086
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.189231866
Short name T1308
Test name
Test status
Simulation time 1291821272 ps
CPU time 4.02 seconds
Started Jul 12 05:22:37 PM PDT 24
Finished Jul 12 05:22:42 PM PDT 24
Peak memory 213572 kb
Host smart-4e23b6ad-15c9-4b1f-9547-17404343e6aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189231866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.189231866
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1710796500
Short name T787
Test name
Test status
Simulation time 20367701358 ps
CPU time 53.31 seconds
Started Jul 12 05:22:33 PM PDT 24
Finished Jul 12 05:23:27 PM PDT 24
Peak memory 767724 kb
Host smart-404a08a1-959e-4d59-8871-c79fb04c4bdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710796500 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1710796500
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.1801891958
Short name T1162
Test name
Test status
Simulation time 539000118 ps
CPU time 2.85 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 213536 kb
Host smart-143b98f1-29e3-409d-9839-119e0f942da8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801891958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.1801891958
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.1872783142
Short name T407
Test name
Test status
Simulation time 1231761086 ps
CPU time 2.71 seconds
Started Jul 12 05:22:37 PM PDT 24
Finished Jul 12 05:22:40 PM PDT 24
Peak memory 205412 kb
Host smart-256c64ab-6f3d-446b-beba-c06ef8715b08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872783142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.1872783142
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.606159326
Short name T139
Test name
Test status
Simulation time 7931875696 ps
CPU time 2.24 seconds
Started Jul 12 05:22:35 PM PDT 24
Finished Jul 12 05:22:39 PM PDT 24
Peak memory 205288 kb
Host smart-9603540e-9801-4021-ad14-445cb4d808c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606159326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_smbus_maxlen.606159326
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.167925687
Short name T1360
Test name
Test status
Simulation time 2964910013 ps
CPU time 11.59 seconds
Started Jul 12 05:22:28 PM PDT 24
Finished Jul 12 05:22:41 PM PDT 24
Peak memory 213576 kb
Host smart-5eb80494-a0c4-4d18-b6c5-0722b3dc02bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167925687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.167925687
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.826969698
Short name T1296
Test name
Test status
Simulation time 2596459584 ps
CPU time 24.26 seconds
Started Jul 12 05:22:30 PM PDT 24
Finished Jul 12 05:22:56 PM PDT 24
Peak memory 229876 kb
Host smart-8c64383a-eab2-4dda-8065-3eb05a6b7a72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826969698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.826969698
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2734555997
Short name T973
Test name
Test status
Simulation time 33663919548 ps
CPU time 11.65 seconds
Started Jul 12 05:22:30 PM PDT 24
Finished Jul 12 05:22:42 PM PDT 24
Peak memory 337532 kb
Host smart-84efee09-70e4-4c2a-8ae6-79d986974281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734555997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2734555997
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.216008981
Short name T157
Test name
Test status
Simulation time 6128623460 ps
CPU time 59.46 seconds
Started Jul 12 05:22:31 PM PDT 24
Finished Jul 12 05:23:31 PM PDT 24
Peak memory 509220 kb
Host smart-b4c1748d-292b-4fc5-bab8-9bc36f4b57f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216008981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_t
arget_stretch.216008981
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2107499258
Short name T1201
Test name
Test status
Simulation time 479926553 ps
CPU time 7.08 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:22:42 PM PDT 24
Peak memory 221476 kb
Host smart-65406f55-79b5-4243-be09-f40002da4b1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107499258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2107499258
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1650728260
Short name T908
Test name
Test status
Simulation time 18157774 ps
CPU time 0.62 seconds
Started Jul 12 05:22:45 PM PDT 24
Finished Jul 12 05:22:47 PM PDT 24
Peak memory 204744 kb
Host smart-db818336-eba5-401f-828e-640322496ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650728260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1650728260
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.301204823
Short name T1019
Test name
Test status
Simulation time 224442854 ps
CPU time 1.22 seconds
Started Jul 12 05:22:45 PM PDT 24
Finished Jul 12 05:22:47 PM PDT 24
Peak memory 213528 kb
Host smart-7cb77fd4-ace6-4124-a0b4-91a49e8018fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301204823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.301204823
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.1748613342
Short name T1293
Test name
Test status
Simulation time 725640555 ps
CPU time 8.75 seconds
Started Jul 12 05:22:35 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 236512 kb
Host smart-aeded508-66cd-47a7-b667-440a3c2fd3ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748613342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.1748613342
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1323710430
Short name T182
Test name
Test status
Simulation time 8095950940 ps
CPU time 70.95 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:23:47 PM PDT 24
Peak memory 689980 kb
Host smart-5af4ab82-4dc8-45d0-bc0e-a4cdfaf6d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323710430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1323710430
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2886516844
Short name T1374
Test name
Test status
Simulation time 2354950518 ps
CPU time 173.34 seconds
Started Jul 12 05:22:36 PM PDT 24
Finished Jul 12 05:25:31 PM PDT 24
Peak memory 737468 kb
Host smart-b55dfa32-91e1-4727-8ca2-1e4128f8ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886516844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2886516844
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.928885653
Short name T1179
Test name
Test status
Simulation time 73229853 ps
CPU time 0.86 seconds
Started Jul 12 05:22:36 PM PDT 24
Finished Jul 12 05:22:38 PM PDT 24
Peak memory 205140 kb
Host smart-134d5b4d-eb2f-4db3-91d4-77010ee0a3ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928885653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.928885653
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1457020384
Short name T1289
Test name
Test status
Simulation time 202209535 ps
CPU time 11.17 seconds
Started Jul 12 05:22:36 PM PDT 24
Finished Jul 12 05:22:48 PM PDT 24
Peak memory 241388 kb
Host smart-18bc1133-0147-4c58-a1df-5d5ab067660f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457020384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1457020384
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3699509946
Short name T1239
Test name
Test status
Simulation time 9359841854 ps
CPU time 340.86 seconds
Started Jul 12 05:22:37 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 1275648 kb
Host smart-6f02c9e0-ce26-4af5-b4f1-9f4997e41bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699509946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3699509946
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_override.2108530235
Short name T152
Test name
Test status
Simulation time 26709724 ps
CPU time 0.68 seconds
Started Jul 12 05:22:37 PM PDT 24
Finished Jul 12 05:22:39 PM PDT 24
Peak memory 205116 kb
Host smart-286160ae-8e17-4574-a7d4-eef4012ecee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108530235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2108530235
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.68067895
Short name T689
Test name
Test status
Simulation time 29990946420 ps
CPU time 470.2 seconds
Started Jul 12 05:22:34 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 606584 kb
Host smart-89a9d388-c65d-44d9-93a4-77aac28098c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68067895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.68067895
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3218303144
Short name T1406
Test name
Test status
Simulation time 844391263 ps
CPU time 3.41 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:22:47 PM PDT 24
Peak memory 205172 kb
Host smart-8f28fa0d-51f7-4450-ae4c-c8eca7cb9d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218303144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3218303144
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2467086515
Short name T1363
Test name
Test status
Simulation time 6708854297 ps
CPU time 33.09 seconds
Started Jul 12 05:22:33 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 335292 kb
Host smart-d020c03c-2c00-4115-bce8-2a45d5d7ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467086515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2467086515
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.347298493
Short name T464
Test name
Test status
Simulation time 4834092394 ps
CPU time 35.04 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 213496 kb
Host smart-cef71856-3979-4842-ae88-bbee40dbdd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347298493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.347298493
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1254601647
Short name T953
Test name
Test status
Simulation time 766499879 ps
CPU time 3.69 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:22:48 PM PDT 24
Peak memory 213668 kb
Host smart-0d8fca36-f1ef-4961-bdd3-1841b3535fa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254601647 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1254601647
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.692614510
Short name T529
Test name
Test status
Simulation time 142073281 ps
CPU time 0.96 seconds
Started Jul 12 05:22:45 PM PDT 24
Finished Jul 12 05:22:47 PM PDT 24
Peak memory 205304 kb
Host smart-8fb05e3b-821f-4a03-bccc-23bc1d947bed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692614510 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.692614510
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3876555448
Short name T606
Test name
Test status
Simulation time 227941126 ps
CPU time 1.35 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 205372 kb
Host smart-b640e700-0eca-47f8-92c4-4dbc6da3d0f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876555448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3876555448
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.775069458
Short name T553
Test name
Test status
Simulation time 451801347 ps
CPU time 2.7 seconds
Started Jul 12 05:22:44 PM PDT 24
Finished Jul 12 05:22:48 PM PDT 24
Peak memory 205420 kb
Host smart-860bde1e-2cc2-4d2d-a7f2-84880edc5a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775069458 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.775069458
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.4028286303
Short name T1496
Test name
Test status
Simulation time 403884351 ps
CPU time 1.14 seconds
Started Jul 12 05:22:41 PM PDT 24
Finished Jul 12 05:22:43 PM PDT 24
Peak memory 205424 kb
Host smart-a872f549-205a-46e9-9cff-e1e9ff175dff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028286303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.4028286303
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.257746069
Short name T1430
Test name
Test status
Simulation time 2990468560 ps
CPU time 7.04 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 213704 kb
Host smart-d16e723f-8688-46f6-8855-d7bc0ffaeac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257746069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.257746069
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.926014644
Short name T1408
Test name
Test status
Simulation time 10866925146 ps
CPU time 9.29 seconds
Started Jul 12 05:22:44 PM PDT 24
Finished Jul 12 05:22:55 PM PDT 24
Peak memory 239864 kb
Host smart-3d232433-c69c-449d-9765-f057cbe443ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926014644 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.926014644
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3542518819
Short name T949
Test name
Test status
Simulation time 525567183 ps
CPU time 2.85 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:22:47 PM PDT 24
Peak memory 213600 kb
Host smart-2bef7e85-7336-4f67-8663-3807dc6d8d6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542518819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3542518819
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.3903985665
Short name T430
Test name
Test status
Simulation time 2306459276 ps
CPU time 2.51 seconds
Started Jul 12 05:22:46 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 205488 kb
Host smart-b61cfc5b-2815-4d30-9175-00ff75002b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903985665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3903985665
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.988897521
Short name T201
Test name
Test status
Simulation time 1987559124 ps
CPU time 2.3 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:22:46 PM PDT 24
Peak memory 205244 kb
Host smart-ddd01245-44de-40ee-be7d-d36ba3c4dbaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988897521 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.988897521
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.654694321
Short name T853
Test name
Test status
Simulation time 1560234589 ps
CPU time 16.6 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:59 PM PDT 24
Peak memory 213604 kb
Host smart-7ccb7d0e-2b62-4827-b57e-4dae7e2d2e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654694321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.654694321
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3095295913
Short name T758
Test name
Test status
Simulation time 2981555133 ps
CPU time 11.26 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:55 PM PDT 24
Peak memory 218392 kb
Host smart-6c4b88d1-e444-4e08-b105-9966205eacf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095295913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3095295913
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1074180445
Short name T981
Test name
Test status
Simulation time 50592929920 ps
CPU time 213.54 seconds
Started Jul 12 05:22:40 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 2328432 kb
Host smart-92626a48-9fd7-4c35-b913-67d165a17710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074180445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1074180445
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.4271092319
Short name T1065
Test name
Test status
Simulation time 1131028210 ps
CPU time 21.2 seconds
Started Jul 12 05:22:46 PM PDT 24
Finished Jul 12 05:23:08 PM PDT 24
Peak memory 292648 kb
Host smart-98836ddb-9ca1-489d-ab72-01ab6a571ded
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271092319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.4271092319
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1635655661
Short name T377
Test name
Test status
Simulation time 5135468298 ps
CPU time 6.28 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 230024 kb
Host smart-a95e675c-1455-4243-889f-21fa04e94eb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635655661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1635655661
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.4052897013
Short name T1265
Test name
Test status
Simulation time 465000294 ps
CPU time 5.66 seconds
Started Jul 12 05:22:44 PM PDT 24
Finished Jul 12 05:22:51 PM PDT 24
Peak memory 205376 kb
Host smart-e8ba0c60-b710-46d2-b429-a93ca1872a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052897013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.4052897013
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2346239092
Short name T899
Test name
Test status
Simulation time 25924429 ps
CPU time 0.64 seconds
Started Jul 12 05:22:49 PM PDT 24
Finished Jul 12 05:22:51 PM PDT 24
Peak memory 204620 kb
Host smart-08970a5f-4f89-4a04-ad1b-f609adba0efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346239092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2346239092
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2015527926
Short name T1178
Test name
Test status
Simulation time 562095611 ps
CPU time 2.82 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 236276 kb
Host smart-aeafc286-8eb1-48da-84a4-b4d3086c9eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015527926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2015527926
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.377021795
Short name T385
Test name
Test status
Simulation time 1555566015 ps
CPU time 27.83 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:23:11 PM PDT 24
Peak memory 316864 kb
Host smart-6b7ad022-ada5-4bc2-94d4-16afecd618d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377021795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.377021795
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3196901729
Short name T785
Test name
Test status
Simulation time 7541184596 ps
CPU time 111.5 seconds
Started Jul 12 05:22:53 PM PDT 24
Finished Jul 12 05:24:45 PM PDT 24
Peak memory 618644 kb
Host smart-048f4faf-bad8-43c3-96ae-920b5fe93b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196901729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3196901729
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2189183347
Short name T143
Test name
Test status
Simulation time 2371048446 ps
CPU time 170.78 seconds
Started Jul 12 05:22:46 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 778572 kb
Host smart-a79ebb71-f058-4fa1-8ffb-daa06488bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189183347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2189183347
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3096588730
Short name T841
Test name
Test status
Simulation time 345662115 ps
CPU time 0.94 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 205056 kb
Host smart-cd918d50-5a06-409a-8630-5bfa1ee608c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096588730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3096588730
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2665077881
Short name T493
Test name
Test status
Simulation time 729824352 ps
CPU time 10.63 seconds
Started Jul 12 05:22:42 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 238800 kb
Host smart-492a0c9e-0406-4feb-b090-ee4689c96e79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665077881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2665077881
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.698247518
Short name T122
Test name
Test status
Simulation time 10904154959 ps
CPU time 139.68 seconds
Started Jul 12 05:22:47 PM PDT 24
Finished Jul 12 05:25:07 PM PDT 24
Peak memory 1508512 kb
Host smart-240cbea0-f056-4eff-b365-ee73968fab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698247518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.698247518
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.728457778
Short name T1527
Test name
Test status
Simulation time 1221436415 ps
CPU time 3.69 seconds
Started Jul 12 05:22:52 PM PDT 24
Finished Jul 12 05:22:57 PM PDT 24
Peak memory 205272 kb
Host smart-0feed0d6-2dbf-4493-b4db-f3b271e98e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728457778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.728457778
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.1335447226
Short name T440
Test name
Test status
Simulation time 36715625 ps
CPU time 0.68 seconds
Started Jul 12 05:22:44 PM PDT 24
Finished Jul 12 05:22:46 PM PDT 24
Peak memory 205288 kb
Host smart-f5971bfd-f0cf-4065-a58c-c264b3ec9380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335447226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1335447226
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1622163076
Short name T934
Test name
Test status
Simulation time 24560701592 ps
CPU time 483.19 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 205556 kb
Host smart-8f7d342f-261d-459b-8776-a289a03df069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622163076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1622163076
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.2684107578
Short name T862
Test name
Test status
Simulation time 3253245636 ps
CPU time 9.02 seconds
Started Jul 12 05:22:49 PM PDT 24
Finished Jul 12 05:22:59 PM PDT 24
Peak memory 205972 kb
Host smart-fec9c294-3d13-411f-88f4-c533288a849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684107578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.2684107578
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2342875941
Short name T1003
Test name
Test status
Simulation time 1652099937 ps
CPU time 27.76 seconds
Started Jul 12 05:22:43 PM PDT 24
Finished Jul 12 05:23:12 PM PDT 24
Peak memory 379788 kb
Host smart-4b599fd6-b3ec-46e2-926a-e074a5cfbbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342875941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2342875941
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1957880204
Short name T309
Test name
Test status
Simulation time 838508503 ps
CPU time 20.26 seconds
Started Jul 12 05:23:29 PM PDT 24
Finished Jul 12 05:23:50 PM PDT 24
Peak memory 213480 kb
Host smart-e01ed140-6aa1-4dcc-afe0-ddc9a98baf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957880204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1957880204
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.781363227
Short name T719
Test name
Test status
Simulation time 2242503142 ps
CPU time 5.52 seconds
Started Jul 12 05:22:49 PM PDT 24
Finished Jul 12 05:22:55 PM PDT 24
Peak memory 221952 kb
Host smart-9cb1fd58-4e5f-454f-8570-2d8053c4b2eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781363227 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.781363227
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.230278698
Short name T1444
Test name
Test status
Simulation time 337471465 ps
CPU time 0.87 seconds
Started Jul 12 05:22:49 PM PDT 24
Finished Jul 12 05:22:51 PM PDT 24
Peak memory 205312 kb
Host smart-5b85f927-adae-43d6-95d1-0a44c63e1f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230278698 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.230278698
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3366098848
Short name T447
Test name
Test status
Simulation time 196847811 ps
CPU time 1.28 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:22:52 PM PDT 24
Peak memory 205332 kb
Host smart-28ebe576-5d0b-4305-b09a-60fafc476c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366098848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3366098848
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3347952502
Short name T1424
Test name
Test status
Simulation time 369945069 ps
CPU time 2.37 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 205208 kb
Host smart-ec3aeb67-1295-4ae7-a671-da84798732fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347952502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3347952502
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.506114320
Short name T611
Test name
Test status
Simulation time 501981583 ps
CPU time 1.21 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 205328 kb
Host smart-05ddd10c-fa37-4c2b-8cf0-b869317a1f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506114320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.506114320
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.96967349
Short name T357
Test name
Test status
Simulation time 1292103261 ps
CPU time 3.82 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:22:56 PM PDT 24
Peak memory 213624 kb
Host smart-7b8ac338-e99c-4975-ab90-48a3d7a70da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96967349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.96967349
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2927333192
Short name T1443
Test name
Test status
Simulation time 33916453442 ps
CPU time 29.36 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:23:22 PM PDT 24
Peak memory 638588 kb
Host smart-cf1376c6-11a5-4a84-9e21-61c74cdfc67c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927333192 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2927333192
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.1899069477
Short name T373
Test name
Test status
Simulation time 2818682523 ps
CPU time 2.95 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 213652 kb
Host smart-1976867d-cf32-446a-8798-934ef2fe1f3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899069477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.1899069477
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.419049198
Short name T1543
Test name
Test status
Simulation time 520055146 ps
CPU time 2.34 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 205436 kb
Host smart-23acd945-f16d-4010-83be-592161d5267f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419049198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.419049198
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.2383226444
Short name T508
Test name
Test status
Simulation time 2746887342 ps
CPU time 2.2 seconds
Started Jul 12 05:22:51 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 205372 kb
Host smart-29107c32-037b-4859-9126-4ffa6e67ab88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383226444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.2383226444
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3708713017
Short name T330
Test name
Test status
Simulation time 3945802306 ps
CPU time 17.88 seconds
Started Jul 12 05:22:52 PM PDT 24
Finished Jul 12 05:23:11 PM PDT 24
Peak memory 213608 kb
Host smart-554cbe68-54d1-4951-9292-9ccbc131e725
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708713017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3708713017
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3314310937
Short name T1464
Test name
Test status
Simulation time 1165468333 ps
CPU time 27.76 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 213580 kb
Host smart-4263aff7-31dd-4af1-827b-47f7640b0b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314310937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3314310937
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3122519868
Short name T329
Test name
Test status
Simulation time 60910885572 ps
CPU time 1615.41 seconds
Started Jul 12 05:22:53 PM PDT 24
Finished Jul 12 05:49:49 PM PDT 24
Peak memory 8241000 kb
Host smart-65e63c80-6156-443e-bea2-b25145631fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122519868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3122519868
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3309964723
Short name T1176
Test name
Test status
Simulation time 216384476 ps
CPU time 1.14 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:22:53 PM PDT 24
Peak memory 205416 kb
Host smart-46aa9813-86eb-42d9-8f12-63dc0f988f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309964723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3309964723
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3522111203
Short name T77
Test name
Test status
Simulation time 2404920124 ps
CPU time 6.08 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:22:57 PM PDT 24
Peak memory 219088 kb
Host smart-611701c6-144c-47d3-8050-b964a0c26697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522111203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3522111203
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.939252816
Short name T141
Test name
Test status
Simulation time 249053381 ps
CPU time 4.54 seconds
Started Jul 12 05:22:49 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 207276 kb
Host smart-352cd668-f804-4065-8ed9-47d3f3d95da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939252816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.939252816
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3224608982
Short name T1280
Test name
Test status
Simulation time 63986436 ps
CPU time 0.64 seconds
Started Jul 12 05:23:07 PM PDT 24
Finished Jul 12 05:23:08 PM PDT 24
Peak memory 204548 kb
Host smart-58ade70d-5df1-4d77-b7a6-1f06b707ce51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224608982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3224608982
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3250969347
Short name T32
Test name
Test status
Simulation time 83312774 ps
CPU time 2.09 seconds
Started Jul 12 05:22:55 PM PDT 24
Finished Jul 12 05:22:58 PM PDT 24
Peak memory 221776 kb
Host smart-fc727d09-2fef-4c3e-bf9b-a12d3bb130d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250969347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3250969347
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1157596171
Short name T772
Test name
Test status
Simulation time 1051908666 ps
CPU time 10.44 seconds
Started Jul 12 05:22:56 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 244456 kb
Host smart-0945e0f9-9929-4a09-b6eb-9415f3de8732
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157596171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1157596171
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1279037586
Short name T1504
Test name
Test status
Simulation time 9184988082 ps
CPU time 81.98 seconds
Started Jul 12 05:22:55 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 755808 kb
Host smart-64c48852-4827-4feb-96a7-8fead6403f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279037586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1279037586
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.183922085
Short name T779
Test name
Test status
Simulation time 3626171395 ps
CPU time 59.23 seconds
Started Jul 12 05:22:57 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 659280 kb
Host smart-e42f79e6-a2b4-4797-b8cb-6035cc9d2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183922085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.183922085
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2797990012
Short name T881
Test name
Test status
Simulation time 576478695 ps
CPU time 0.79 seconds
Started Jul 12 05:22:56 PM PDT 24
Finished Jul 12 05:22:57 PM PDT 24
Peak memory 205004 kb
Host smart-dc1e9eec-3e81-488a-86ca-e7c7e816f872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797990012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2797990012
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1547574887
Short name T929
Test name
Test status
Simulation time 340290877 ps
CPU time 8.95 seconds
Started Jul 12 05:22:59 PM PDT 24
Finished Jul 12 05:23:09 PM PDT 24
Peak memory 205164 kb
Host smart-bbfa70cc-8beb-4bec-8229-a3f1b908f0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547574887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1547574887
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1867606382
Short name T520
Test name
Test status
Simulation time 5437823167 ps
CPU time 160.71 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 1470032 kb
Host smart-21f4348f-e29f-43d4-b7d0-f3c4941ac70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867606382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1867606382
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_override.708638723
Short name T723
Test name
Test status
Simulation time 17780645 ps
CPU time 0.7 seconds
Started Jul 12 05:22:52 PM PDT 24
Finished Jul 12 05:22:54 PM PDT 24
Peak memory 205096 kb
Host smart-729607ee-7e61-4e4e-bed6-96f8d31905b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708638723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.708638723
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2975125109
Short name T1485
Test name
Test status
Simulation time 26854515024 ps
CPU time 117.43 seconds
Started Jul 12 05:22:59 PM PDT 24
Finished Jul 12 05:24:57 PM PDT 24
Peak memory 271428 kb
Host smart-5f361061-be74-4a48-8016-d5cb97ac294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975125109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2975125109
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3512666372
Short name T945
Test name
Test status
Simulation time 364769139 ps
CPU time 3.62 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:06 PM PDT 24
Peak memory 237448 kb
Host smart-eb87069a-dd4d-40aa-b70b-9e196286cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512666372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3512666372
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1795945390
Short name T517
Test name
Test status
Simulation time 5650092494 ps
CPU time 65.91 seconds
Started Jul 12 05:22:50 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 316128 kb
Host smart-a2ab0944-1645-4f33-8d70-a86c89a471b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795945390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1795945390
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3945452321
Short name T1427
Test name
Test status
Simulation time 528786967 ps
CPU time 9.68 seconds
Started Jul 12 05:22:56 PM PDT 24
Finished Jul 12 05:23:06 PM PDT 24
Peak memory 213536 kb
Host smart-0373244c-f137-49a1-a2f3-2a9f1cc3424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945452321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3945452321
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.208642746
Short name T998
Test name
Test status
Simulation time 4648813631 ps
CPU time 6.56 seconds
Started Jul 12 05:22:57 PM PDT 24
Finished Jul 12 05:23:04 PM PDT 24
Peak memory 221808 kb
Host smart-35a495a1-b369-4868-800b-3ca78349a2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208642746 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.208642746
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1158758901
Short name T178
Test name
Test status
Simulation time 192340361 ps
CPU time 1.58 seconds
Started Jul 12 05:22:58 PM PDT 24
Finished Jul 12 05:23:00 PM PDT 24
Peak memory 205652 kb
Host smart-ba8aa960-5b00-41e2-8822-ae282aaf074f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158758901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1158758901
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.2433077031
Short name T1010
Test name
Test status
Simulation time 7603723380 ps
CPU time 2.53 seconds
Started Jul 12 05:22:59 PM PDT 24
Finished Jul 12 05:23:02 PM PDT 24
Peak memory 205492 kb
Host smart-a96aa200-092a-4cfc-8083-52f14b249092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433077031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.2433077031
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.3847841955
Short name T1213
Test name
Test status
Simulation time 293773175 ps
CPU time 1.25 seconds
Started Jul 12 05:23:00 PM PDT 24
Finished Jul 12 05:23:02 PM PDT 24
Peak memory 205296 kb
Host smart-6a2a7da8-c605-4ff6-8aa8-6ab81ccf2257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847841955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3847841955
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.624521493
Short name T724
Test name
Test status
Simulation time 1485723079 ps
CPU time 6.02 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:08 PM PDT 24
Peak memory 216600 kb
Host smart-fee99c60-c10f-44ce-9b3f-228f7ba90279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624521493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.624521493
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2878994376
Short name T990
Test name
Test status
Simulation time 4691215343 ps
CPU time 10.27 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:13 PM PDT 24
Peak memory 458476 kb
Host smart-757dacbc-f029-478a-a1a7-5939f835e85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878994376 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2878994376
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.78727574
Short name T64
Test name
Test status
Simulation time 543556484 ps
CPU time 3.12 seconds
Started Jul 12 05:23:00 PM PDT 24
Finished Jul 12 05:23:04 PM PDT 24
Peak memory 213480 kb
Host smart-dde6dbe7-cd7f-403e-8e38-9984402cb2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78727574 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_target_nack_acqfull.78727574
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.2633218877
Short name T1418
Test name
Test status
Simulation time 1936885613 ps
CPU time 2.45 seconds
Started Jul 12 05:22:58 PM PDT 24
Finished Jul 12 05:23:01 PM PDT 24
Peak memory 205568 kb
Host smart-47eded25-691f-4a07-9c91-1e97823e480a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633218877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.2633218877
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.2950188992
Short name T681
Test name
Test status
Simulation time 981049044 ps
CPU time 2.34 seconds
Started Jul 12 05:22:58 PM PDT 24
Finished Jul 12 05:23:01 PM PDT 24
Peak memory 205220 kb
Host smart-e40e7943-3cd0-4c3b-a7ca-e62c6c1a2de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950188992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.2950188992
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.834499774
Short name T518
Test name
Test status
Simulation time 1087374622 ps
CPU time 34.88 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 213692 kb
Host smart-92324e55-dc35-4a87-b358-811896869045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834499774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.834499774
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2457481073
Short name T395
Test name
Test status
Simulation time 5323351143 ps
CPU time 20.68 seconds
Started Jul 12 05:23:00 PM PDT 24
Finished Jul 12 05:23:22 PM PDT 24
Peak memory 227108 kb
Host smart-8a983b71-5b85-403a-b56e-4ef07b364213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457481073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2457481073
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3841665513
Short name T1299
Test name
Test status
Simulation time 50099231185 ps
CPU time 167.43 seconds
Started Jul 12 05:22:57 PM PDT 24
Finished Jul 12 05:25:45 PM PDT 24
Peak memory 1906240 kb
Host smart-470ca5d1-ddab-49d0-8ebb-5003345edcd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841665513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3841665513
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.4199753329
Short name T315
Test name
Test status
Simulation time 2621204120 ps
CPU time 41.38 seconds
Started Jul 12 05:22:59 PM PDT 24
Finished Jul 12 05:23:41 PM PDT 24
Peak memory 751892 kb
Host smart-82ced34d-9b7c-47c5-90a9-3b7970f0cc0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199753329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.4199753329
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1981566000
Short name T653
Test name
Test status
Simulation time 1120559076 ps
CPU time 6.14 seconds
Started Jul 12 05:22:56 PM PDT 24
Finished Jul 12 05:23:02 PM PDT 24
Peak memory 213636 kb
Host smart-f8f33c94-6454-4a1f-9869-abd790054918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981566000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1981566000
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.2580148812
Short name T986
Test name
Test status
Simulation time 90084895 ps
CPU time 2.03 seconds
Started Jul 12 05:22:54 PM PDT 24
Finished Jul 12 05:22:57 PM PDT 24
Peak memory 205420 kb
Host smart-0b2a7504-ebf4-43a1-9b8a-a5403b63674b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580148812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.2580148812
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1594367672
Short name T1284
Test name
Test status
Simulation time 25574640 ps
CPU time 0.62 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 204784 kb
Host smart-31279426-aa1f-49b2-bee0-9f5404199cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594367672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1594367672
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3153501296
Short name T19
Test name
Test status
Simulation time 198448049 ps
CPU time 3.47 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:05 PM PDT 24
Peak memory 235968 kb
Host smart-9f70c0fa-42fa-4f53-87b7-12b3fb8283dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153501296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3153501296
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.4035135878
Short name T128
Test name
Test status
Simulation time 3968593284 ps
CPU time 5.46 seconds
Started Jul 12 05:23:08 PM PDT 24
Finished Jul 12 05:23:14 PM PDT 24
Peak memory 254860 kb
Host smart-c416e233-2d37-4013-a195-3988cffd9345
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035135878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.4035135878
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2453302597
Short name T533
Test name
Test status
Simulation time 1733605007 ps
CPU time 49.13 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 626068 kb
Host smart-6f17b260-c6f2-4743-a6ab-ebbcc5c4ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453302597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2453302597
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1364561179
Short name T1250
Test name
Test status
Simulation time 139243281 ps
CPU time 1.16 seconds
Started Jul 12 05:23:05 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 205056 kb
Host smart-06e0c56e-00b6-4658-b6bf-7832a2c52b03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364561179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1364561179
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1151670528
Short name T1267
Test name
Test status
Simulation time 462130161 ps
CPU time 3.16 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 205316 kb
Host smart-8fd4385d-3739-4146-8a13-e9dc45a2e6c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151670528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1151670528
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3868549650
Short name T1220
Test name
Test status
Simulation time 32829813135 ps
CPU time 65.75 seconds
Started Jul 12 05:23:07 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 832196 kb
Host smart-2efff423-1929-494a-b426-1d09ae53ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868549650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3868549650
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.982741418
Short name T43
Test name
Test status
Simulation time 358282489 ps
CPU time 14.48 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:23:29 PM PDT 24
Peak memory 205328 kb
Host smart-0a37fa4a-62a6-41f2-8df4-d397b0551d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982741418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.982741418
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.2161756400
Short name T372
Test name
Test status
Simulation time 15927705 ps
CPU time 0.67 seconds
Started Jul 12 05:23:06 PM PDT 24
Finished Jul 12 05:23:08 PM PDT 24
Peak memory 205060 kb
Host smart-b9663529-89ae-4899-a024-c5597ec4f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161756400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2161756400
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.961269605
Short name T172
Test name
Test status
Simulation time 3308502536 ps
CPU time 10.8 seconds
Started Jul 12 05:23:08 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 232960 kb
Host smart-85d63497-1674-4044-b683-7e7697c67af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961269605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.961269605
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.1631502787
Short name T621
Test name
Test status
Simulation time 36273020 ps
CPU time 1.11 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:23:05 PM PDT 24
Peak memory 225440 kb
Host smart-74bb0eb2-c69b-44c3-9747-4f46c012b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631502787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1631502787
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1816290041
Short name T866
Test name
Test status
Simulation time 2908097157 ps
CPU time 60.93 seconds
Started Jul 12 05:23:02 PM PDT 24
Finished Jul 12 05:24:04 PM PDT 24
Peak memory 312392 kb
Host smart-58a7e786-31c1-4dbc-8a64-e08f824eafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816290041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1816290041
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1999826864
Short name T982
Test name
Test status
Simulation time 1345129670 ps
CPU time 9.29 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:23:13 PM PDT 24
Peak memory 216480 kb
Host smart-706823b6-aa4d-4020-acae-aa329a3bb764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999826864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1999826864
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2972364180
Short name T523
Test name
Test status
Simulation time 1956494366 ps
CPU time 5.24 seconds
Started Jul 12 05:23:06 PM PDT 24
Finished Jul 12 05:23:12 PM PDT 24
Peak memory 214648 kb
Host smart-3b92df2b-22bb-4bdf-bd77-b85b38a0d711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972364180 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2972364180
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1768134694
Short name T1432
Test name
Test status
Simulation time 230287290 ps
CPU time 1.51 seconds
Started Jul 12 05:23:04 PM PDT 24
Finished Jul 12 05:23:06 PM PDT 24
Peak memory 213552 kb
Host smart-ed307f68-795e-42d1-a306-79b5500750ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768134694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1768134694
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2580202548
Short name T992
Test name
Test status
Simulation time 406197821 ps
CPU time 0.99 seconds
Started Jul 12 05:23:04 PM PDT 24
Finished Jul 12 05:23:06 PM PDT 24
Peak memory 205312 kb
Host smart-02dd3079-2423-4b23-b213-f38ac56aac12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580202548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2580202548
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2815660161
Short name T892
Test name
Test status
Simulation time 1313803949 ps
CPU time 2.38 seconds
Started Jul 12 05:23:12 PM PDT 24
Finished Jul 12 05:23:15 PM PDT 24
Peak memory 205352 kb
Host smart-cd4ff684-70f1-49b6-9d0d-ae988300cbdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815660161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2815660161
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.365859552
Short name T840
Test name
Test status
Simulation time 182263974 ps
CPU time 1.55 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:23:16 PM PDT 24
Peak memory 205348 kb
Host smart-e2e3c96a-d03c-4348-8f7f-55dd81e03e86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365859552 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.365859552
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4207390037
Short name T383
Test name
Test status
Simulation time 592384805 ps
CPU time 3.51 seconds
Started Jul 12 05:23:02 PM PDT 24
Finished Jul 12 05:23:07 PM PDT 24
Peak memory 213616 kb
Host smart-34076f5b-4677-4dd5-9c56-8371a5a9d5e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207390037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4207390037
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2692238756
Short name T400
Test name
Test status
Simulation time 17386219173 ps
CPU time 36.79 seconds
Started Jul 12 05:23:01 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 738284 kb
Host smart-3bf02a95-d2d0-4f1a-8c5b-d044d16893a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692238756 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2692238756
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.2348280556
Short name T1292
Test name
Test status
Simulation time 612225202 ps
CPU time 3.37 seconds
Started Jul 12 05:23:11 PM PDT 24
Finished Jul 12 05:23:15 PM PDT 24
Peak memory 213532 kb
Host smart-6832d152-c383-40b5-9544-bf9d6430602e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348280556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.2348280556
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.4210145974
Short name T1310
Test name
Test status
Simulation time 2110773221 ps
CPU time 2.35 seconds
Started Jul 12 05:23:14 PM PDT 24
Finished Jul 12 05:23:18 PM PDT 24
Peak memory 205568 kb
Host smart-f451ea61-fe0f-44e5-b510-de0d55c5c12e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210145974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.4210145974
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.2335241555
Short name T1209
Test name
Test status
Simulation time 824360896 ps
CPU time 2.13 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:18 PM PDT 24
Peak memory 205252 kb
Host smart-bf812c82-1cf5-49ba-92f6-4ef6ae9c92b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335241555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.2335241555
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.4176485673
Short name T655
Test name
Test status
Simulation time 970717916 ps
CPU time 30.31 seconds
Started Jul 12 05:23:02 PM PDT 24
Finished Jul 12 05:23:34 PM PDT 24
Peak memory 213580 kb
Host smart-ec63c600-d2d3-4db6-8e56-22a1411758d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176485673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.4176485673
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.119824525
Short name T1093
Test name
Test status
Simulation time 2035412724 ps
CPU time 7.97 seconds
Started Jul 12 05:23:02 PM PDT 24
Finished Jul 12 05:23:11 PM PDT 24
Peak memory 216056 kb
Host smart-73c6a8da-a735-426f-82f3-095766fa5b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119824525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.119824525
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2301087755
Short name T1567
Test name
Test status
Simulation time 15464514044 ps
CPU time 15.52 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 205592 kb
Host smart-e7c371de-3408-4b7a-a9ad-bd0d3214350f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301087755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2301087755
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2592734817
Short name T800
Test name
Test status
Simulation time 2621047464 ps
CPU time 117.77 seconds
Started Jul 12 05:23:03 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 727304 kb
Host smart-f2aa59d9-f993-41aa-97eb-b474ed0df5fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592734817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2592734817
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3380704988
Short name T1490
Test name
Test status
Simulation time 6926383088 ps
CPU time 6.4 seconds
Started Jul 12 05:23:04 PM PDT 24
Finished Jul 12 05:23:11 PM PDT 24
Peak memory 218832 kb
Host smart-73a2bc3a-0e12-499a-ba63-eefffe763759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380704988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3380704988
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1444251331
Short name T1315
Test name
Test status
Simulation time 216958611 ps
CPU time 3.16 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 205424 kb
Host smart-4ccca20b-82b5-4fc6-a74d-597c2361595d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444251331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1444251331
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.487306663
Short name T406
Test name
Test status
Simulation time 62580408 ps
CPU time 0.63 seconds
Started Jul 12 05:23:17 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 204564 kb
Host smart-c365d8ce-aca8-416d-96da-c00595b73fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487306663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.487306663
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1955077998
Short name T996
Test name
Test status
Simulation time 189917232 ps
CPU time 1.65 seconds
Started Jul 12 05:23:09 PM PDT 24
Finished Jul 12 05:23:11 PM PDT 24
Peak memory 213392 kb
Host smart-ee39675b-8c9f-43f0-9597-6116e3fff644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955077998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1955077998
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.454795573
Short name T748
Test name
Test status
Simulation time 500279525 ps
CPU time 12.58 seconds
Started Jul 12 05:23:10 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 246648 kb
Host smart-79311be7-c10a-4696-abeb-27b0f2532e80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454795573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.454795573
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.887378622
Short name T1276
Test name
Test status
Simulation time 7796434792 ps
CPU time 108.25 seconds
Started Jul 12 05:23:10 PM PDT 24
Finished Jul 12 05:24:59 PM PDT 24
Peak memory 909412 kb
Host smart-95913689-d79c-4819-b585-a1908e051421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887378622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.887378622
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2644162861
Short name T183
Test name
Test status
Simulation time 1900651781 ps
CPU time 66.9 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 676448 kb
Host smart-383091f4-88d6-476c-83f8-e95b78d4a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644162861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2644162861
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2910232227
Short name T747
Test name
Test status
Simulation time 165693838 ps
CPU time 1.22 seconds
Started Jul 12 05:23:11 PM PDT 24
Finished Jul 12 05:23:13 PM PDT 24
Peak memory 205004 kb
Host smart-1a381a46-45f3-4aa6-96c8-68a41189b6e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910232227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2910232227
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1227533648
Short name T453
Test name
Test status
Simulation time 634462513 ps
CPU time 10.97 seconds
Started Jul 12 05:23:11 PM PDT 24
Finished Jul 12 05:23:23 PM PDT 24
Peak memory 240140 kb
Host smart-8eb18896-5fa8-45a0-bffc-5d512acc8601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227533648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1227533648
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.154885978
Short name T955
Test name
Test status
Simulation time 7685060871 ps
CPU time 284 seconds
Started Jul 12 05:23:17 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 1141012 kb
Host smart-968aa012-7bf4-4480-9183-4cf217f39128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154885978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.154885978
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2184085009
Short name T1155
Test name
Test status
Simulation time 248488696 ps
CPU time 10.23 seconds
Started Jul 12 05:23:14 PM PDT 24
Finished Jul 12 05:23:26 PM PDT 24
Peak memory 205348 kb
Host smart-5c60cd8c-2b8b-44b7-a9ab-e0b5cbfeee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184085009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2184085009
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.149578778
Short name T136
Test name
Test status
Simulation time 15634113 ps
CPU time 0.65 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:26 PM PDT 24
Peak memory 205048 kb
Host smart-11157cf1-12c9-453b-abdb-c30f56ff1659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149578778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.149578778
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.961580833
Short name T931
Test name
Test status
Simulation time 3245930480 ps
CPU time 34.16 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:51 PM PDT 24
Peak memory 219976 kb
Host smart-05887dee-b7e9-47e9-bf5d-fae027870759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961580833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.961580833
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.1006839560
Short name T852
Test name
Test status
Simulation time 41316303 ps
CPU time 1.27 seconds
Started Jul 12 05:23:12 PM PDT 24
Finished Jul 12 05:23:14 PM PDT 24
Peak memory 205844 kb
Host smart-0781c797-cfaf-4d3c-b775-933e6475d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006839560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1006839560
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.603729790
Short name T995
Test name
Test status
Simulation time 4248055410 ps
CPU time 17.94 seconds
Started Jul 12 05:23:12 PM PDT 24
Finished Jul 12 05:23:30 PM PDT 24
Peak memory 313312 kb
Host smart-8f5b0e95-8a3f-4a03-9690-57c9205d6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603729790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.603729790
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.4035828467
Short name T132
Test name
Test status
Simulation time 26754647773 ps
CPU time 522.85 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 1302012 kb
Host smart-1a730691-b870-472a-a216-aa565bf86a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035828467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.4035828467
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.612570225
Short name T488
Test name
Test status
Simulation time 3819907622 ps
CPU time 17.82 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:34 PM PDT 24
Peak memory 221428 kb
Host smart-20b6eb45-5a68-4a48-98f9-0a557c3cad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612570225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.612570225
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.353466098
Short name T438
Test name
Test status
Simulation time 618262586 ps
CPU time 3.53 seconds
Started Jul 12 05:23:14 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 220708 kb
Host smart-0936c516-c8ab-4d9e-96a1-7de6ca7f83dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353466098 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.353466098
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.4187164786
Short name T249
Test name
Test status
Simulation time 333840211 ps
CPU time 0.8 seconds
Started Jul 12 05:23:12 PM PDT 24
Finished Jul 12 05:23:14 PM PDT 24
Peak memory 205244 kb
Host smart-2f717f28-b833-4b06-a9cc-0b14c0185cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187164786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.4187164786
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1785006586
Short name T1405
Test name
Test status
Simulation time 2295673374 ps
CPU time 1.44 seconds
Started Jul 12 05:23:11 PM PDT 24
Finished Jul 12 05:23:13 PM PDT 24
Peak memory 207684 kb
Host smart-ee3c3863-53d5-453a-9cac-1e5b74db533d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785006586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1785006586
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.3398385233
Short name T1538
Test name
Test status
Simulation time 584138932 ps
CPU time 2.84 seconds
Started Jul 12 05:23:14 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 205404 kb
Host smart-377b0a92-ea6e-4869-9f14-4c7ba1e108f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398385233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3398385233
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3319459269
Short name T847
Test name
Test status
Simulation time 412160241 ps
CPU time 1.16 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:17 PM PDT 24
Peak memory 205300 kb
Host smart-ad43d52d-7b89-4c2e-bb09-dcf35f3ddbaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319459269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3319459269
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.374311527
Short name T886
Test name
Test status
Simulation time 1662663689 ps
CPU time 8.96 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 229988 kb
Host smart-1f8300dd-2553-4f58-a02f-e42d17d71968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374311527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.374311527
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.901334335
Short name T782
Test name
Test status
Simulation time 3056251378 ps
CPU time 3.92 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 205416 kb
Host smart-6ee0f42a-30da-4c59-af14-cae335d038d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901334335 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.901334335
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.2259251330
Short name T1390
Test name
Test status
Simulation time 1244326108 ps
CPU time 3.24 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:23:18 PM PDT 24
Peak memory 213592 kb
Host smart-62cdde21-e4ee-47f2-a91c-8dac01cbe780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259251330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.2259251330
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.609058061
Short name T742
Test name
Test status
Simulation time 2088469291 ps
CPU time 2.22 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:23:21 PM PDT 24
Peak memory 205432 kb
Host smart-9eaff8b1-bf95-4b6d-98e4-4d4329404529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609058061 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.609058061
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.4063222813
Short name T460
Test name
Test status
Simulation time 480042382 ps
CPU time 2.24 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:23:17 PM PDT 24
Peak memory 205304 kb
Host smart-3fd05683-67f3-4c55-afad-80b8c6e5a176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063222813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.4063222813
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.442387617
Short name T3
Test name
Test status
Simulation time 1978273665 ps
CPU time 12.71 seconds
Started Jul 12 05:23:13 PM PDT 24
Finished Jul 12 05:23:27 PM PDT 24
Peak memory 207860 kb
Host smart-c6a38f67-5627-45e7-a400-8c20e33ee6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442387617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.442387617
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1485345346
Short name T976
Test name
Test status
Simulation time 343628035 ps
CPU time 8.71 seconds
Started Jul 12 05:23:17 PM PDT 24
Finished Jul 12 05:23:26 PM PDT 24
Peak memory 205380 kb
Host smart-6d007240-88a8-467a-9ce2-c857e953a21e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485345346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1485345346
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2266103190
Short name T1
Test name
Test status
Simulation time 21467095493 ps
CPU time 12.75 seconds
Started Jul 12 05:23:12 PM PDT 24
Finished Jul 12 05:23:26 PM PDT 24
Peak memory 205552 kb
Host smart-19a6203d-783f-4647-94d4-177309909203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266103190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2266103190
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1346513101
Short name T483
Test name
Test status
Simulation time 1862074902 ps
CPU time 11.12 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 329476 kb
Host smart-62e184cd-fe14-4781-bccc-3bedb233c65d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346513101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1346513101
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3696731529
Short name T1218
Test name
Test status
Simulation time 1327352803 ps
CPU time 6.87 seconds
Started Jul 12 05:23:15 PM PDT 24
Finished Jul 12 05:23:23 PM PDT 24
Peak memory 221848 kb
Host smart-4705e946-6e44-4ced-9eee-3c20528ae9da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696731529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3696731529
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.2688621182
Short name T1377
Test name
Test status
Simulation time 113016222 ps
CPU time 2.01 seconds
Started Jul 12 05:23:10 PM PDT 24
Finished Jul 12 05:23:13 PM PDT 24
Peak memory 205428 kb
Host smart-8da7fcdf-105f-4193-b3a9-8d6162a6c415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688621182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2688621182
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2859889686
Short name T540
Test name
Test status
Simulation time 24374834 ps
CPU time 0.61 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 204460 kb
Host smart-0b76a64b-06ba-4ac3-a2fe-bf763d7610c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859889686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2859889686
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.689539740
Short name T485
Test name
Test status
Simulation time 177364514 ps
CPU time 2.94 seconds
Started Jul 12 05:23:17 PM PDT 24
Finished Jul 12 05:23:21 PM PDT 24
Peak memory 232232 kb
Host smart-073a068c-e8f3-4466-86b7-84ecbf9a6a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689539740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.689539740
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1879944417
Short name T602
Test name
Test status
Simulation time 666331577 ps
CPU time 3.41 seconds
Started Jul 12 05:23:19 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 229960 kb
Host smart-11c5dcac-8816-4bc7-b849-76ee773c292e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879944417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1879944417
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3238997895
Short name T569
Test name
Test status
Simulation time 1372907147 ps
CPU time 40.78 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:24:00 PM PDT 24
Peak memory 533976 kb
Host smart-7e87e2d3-90ae-47d7-89c0-b23089c50b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238997895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3238997895
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.630734769
Short name T387
Test name
Test status
Simulation time 7024500772 ps
CPU time 50.11 seconds
Started Jul 12 05:23:19 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 517788 kb
Host smart-dcde148b-a6ce-4b1d-a74e-0723734fb45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630734769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.630734769
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3219982741
Short name T793
Test name
Test status
Simulation time 796482070 ps
CPU time 0.83 seconds
Started Jul 12 05:23:21 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 204996 kb
Host smart-189dfee0-98e9-45a0-a2da-6de38bc3f866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219982741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3219982741
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3244851434
Short name T865
Test name
Test status
Simulation time 760451111 ps
CPU time 5.14 seconds
Started Jul 12 05:23:19 PM PDT 24
Finished Jul 12 05:23:26 PM PDT 24
Peak memory 241804 kb
Host smart-29f1d62a-82ac-4269-bdd6-316ccea331a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244851434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3244851434
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.64886251
Short name T1005
Test name
Test status
Simulation time 5462322101 ps
CPU time 156.43 seconds
Started Jul 12 05:23:22 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 1533648 kb
Host smart-9077eb3e-d206-4f88-a26c-cf0201eda584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64886251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.64886251
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.788933093
Short name T257
Test name
Test status
Simulation time 2478132583 ps
CPU time 23.67 seconds
Started Jul 12 05:23:19 PM PDT 24
Finished Jul 12 05:23:44 PM PDT 24
Peak memory 205220 kb
Host smart-d968d450-cdf7-45bd-816c-260eaa2a70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788933093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.788933093
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.3057227380
Short name T102
Test name
Test status
Simulation time 86530187 ps
CPU time 0.68 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:23:20 PM PDT 24
Peak memory 205048 kb
Host smart-02185059-396b-443b-b4cb-18f67318f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057227380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3057227380
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4262444829
Short name T1354
Test name
Test status
Simulation time 3592592819 ps
CPU time 36.41 seconds
Started Jul 12 05:23:18 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 363372 kb
Host smart-d5ce7175-6db1-4547-81e5-6d7e2cf0c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262444829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4262444829
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.3748590905
Short name T1085
Test name
Test status
Simulation time 41042745 ps
CPU time 1.88 seconds
Started Jul 12 05:23:16 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 206044 kb
Host smart-a6d4d98c-f3a4-4059-ba25-8ec69a5b0fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748590905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3748590905
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.635388407
Short name T894
Test name
Test status
Simulation time 1359441225 ps
CPU time 22.91 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:44 PM PDT 24
Peak memory 313696 kb
Host smart-83aa5c79-abb9-49fb-b92f-f48d583c0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635388407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.635388407
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.277968684
Short name T1001
Test name
Test status
Simulation time 2344475307 ps
CPU time 26.67 seconds
Started Jul 12 05:23:26 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 213576 kb
Host smart-4be60107-39d9-43d3-8edf-edd94d51d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277968684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.277968684
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.472923885
Short name T647
Test name
Test status
Simulation time 566585808 ps
CPU time 3.67 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 213612 kb
Host smart-a363dbdb-87d3-428c-a742-3eabcd86dc5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472923885 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.472923885
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1190679254
Short name T1428
Test name
Test status
Simulation time 300969448 ps
CPU time 1.16 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:23 PM PDT 24
Peak memory 205304 kb
Host smart-ad8e0477-e325-4c56-86a8-3783fd7ec998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190679254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1190679254
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3803699659
Short name T1386
Test name
Test status
Simulation time 275072461 ps
CPU time 1.65 seconds
Started Jul 12 05:23:22 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 205424 kb
Host smart-63e0facd-3743-4a50-a850-8580c27f54dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803699659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3803699659
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3900609661
Short name T1398
Test name
Test status
Simulation time 1540833715 ps
CPU time 2.44 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 205432 kb
Host smart-d3921bf9-fe49-476f-94db-cb423dd93134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900609661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3900609661
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.3749634892
Short name T1355
Test name
Test status
Simulation time 83743975 ps
CPU time 1.01 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:22 PM PDT 24
Peak memory 205304 kb
Host smart-34d95e5c-8f78-48cd-a2ea-b54934126007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749634892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.3749634892
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.43782337
Short name T1238
Test name
Test status
Simulation time 11876944675 ps
CPU time 7.13 seconds
Started Jul 12 05:23:38 PM PDT 24
Finished Jul 12 05:23:47 PM PDT 24
Peak memory 213552 kb
Host smart-10ce9b49-820d-44e5-88c3-9d1c065279f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43782337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.43782337
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.3161232002
Short name T937
Test name
Test status
Simulation time 989634703 ps
CPU time 2.96 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 213624 kb
Host smart-7d03a2d1-36de-4b95-b222-d2f81fe61426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161232002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.3161232002
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.4264010430
Short name T1149
Test name
Test status
Simulation time 558286318 ps
CPU time 2.7 seconds
Started Jul 12 05:23:19 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 205356 kb
Host smart-555e274a-857c-4732-bc4b-d1450cd86cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264010430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.4264010430
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.1043331370
Short name T443
Test name
Test status
Simulation time 456700739 ps
CPU time 2.15 seconds
Started Jul 12 05:23:16 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 205252 kb
Host smart-e81122ac-7f36-4680-b4cd-7ecadbe6761b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043331370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.1043331370
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.111582608
Short name T415
Test name
Test status
Simulation time 2366050721 ps
CPU time 16.23 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:42 PM PDT 24
Peak memory 213688 kb
Host smart-10145ae8-3308-4ff3-bc02-f579d4f40cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111582608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.111582608
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3820326725
Short name T274
Test name
Test status
Simulation time 1736734792 ps
CPU time 26.61 seconds
Started Jul 12 05:23:23 PM PDT 24
Finished Jul 12 05:23:52 PM PDT 24
Peak memory 236344 kb
Host smart-567cdeb7-a76e-4a98-b1b2-24d642687371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820326725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3820326725
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2075987685
Short name T1160
Test name
Test status
Simulation time 47642147922 ps
CPU time 142.34 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 1779472 kb
Host smart-38674878-2000-4288-975b-dfe93bd40ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075987685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2075987685
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3231583539
Short name T967
Test name
Test status
Simulation time 4208032509 ps
CPU time 43.39 seconds
Started Jul 12 05:23:23 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 681732 kb
Host smart-8bc45104-afc9-4248-9507-5eb8adc5d3ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231583539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3231583539
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1455034005
Short name T1262
Test name
Test status
Simulation time 6386203253 ps
CPU time 6.66 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:32 PM PDT 24
Peak memory 221888 kb
Host smart-d3315883-164b-4dd7-a07c-11f26853ca52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455034005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1455034005
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.3120892396
Short name T984
Test name
Test status
Simulation time 93979234 ps
CPU time 2.02 seconds
Started Jul 12 05:23:21 PM PDT 24
Finished Jul 12 05:23:25 PM PDT 24
Peak memory 205396 kb
Host smart-70b126ae-5560-4bbf-85b2-9d4a9b050d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120892396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3120892396
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2101172048
Short name T175
Test name
Test status
Simulation time 50580833 ps
CPU time 0.62 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:07 PM PDT 24
Peak memory 204616 kb
Host smart-2b901e80-47ea-4828-993f-3395d6a877a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101172048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2101172048
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3697792742
Short name T635
Test name
Test status
Simulation time 164498498 ps
CPU time 1.45 seconds
Started Jul 12 05:19:05 PM PDT 24
Finished Jul 12 05:19:08 PM PDT 24
Peak memory 213516 kb
Host smart-7b3b5b30-4ad7-4ddd-ab4d-54447f88ebf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697792742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3697792742
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.594192789
Short name T1251
Test name
Test status
Simulation time 2063729881 ps
CPU time 13.09 seconds
Started Jul 12 05:19:01 PM PDT 24
Finished Jul 12 05:19:15 PM PDT 24
Peak memory 340616 kb
Host smart-1bcad250-69f1-42cf-a5af-fde7e1c12a29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594192789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.594192789
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2154056623
Short name T92
Test name
Test status
Simulation time 2293369290 ps
CPU time 162.68 seconds
Started Jul 12 05:19:04 PM PDT 24
Finished Jul 12 05:21:47 PM PDT 24
Peak memory 736976 kb
Host smart-5d548a66-a0fe-4bb1-9728-4324f4405d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154056623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2154056623
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1036007527
Short name T878
Test name
Test status
Simulation time 1494051179 ps
CPU time 94.08 seconds
Started Jul 12 05:18:55 PM PDT 24
Finished Jul 12 05:20:30 PM PDT 24
Peak memory 558692 kb
Host smart-89841cb6-d563-49df-815d-fffe7297a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036007527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1036007527
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3774977751
Short name T39
Test name
Test status
Simulation time 157560946 ps
CPU time 1.37 seconds
Started Jul 12 05:18:54 PM PDT 24
Finished Jul 12 05:18:56 PM PDT 24
Peak memory 205132 kb
Host smart-46b95cfa-6313-471a-a52c-5c5415ba12a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774977751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3774977751
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2345592531
Short name T734
Test name
Test status
Simulation time 604844266 ps
CPU time 4.82 seconds
Started Jul 12 05:19:00 PM PDT 24
Finished Jul 12 05:19:06 PM PDT 24
Peak memory 235328 kb
Host smart-93f30da6-5d2e-455e-8cdd-ac3981a080ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345592531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2345592531
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1302789940
Short name T1512
Test name
Test status
Simulation time 50378951484 ps
CPU time 136.81 seconds
Started Jul 12 05:18:51 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 1462888 kb
Host smart-492a6f1a-ac43-475b-8eab-7b52f6862470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302789940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1302789940
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3132053226
Short name T268
Test name
Test status
Simulation time 2570765806 ps
CPU time 9.78 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:17 PM PDT 24
Peak memory 205296 kb
Host smart-9ea31241-c15b-499d-aaba-08e883d45a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132053226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3132053226
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.2035498787
Short name T1031
Test name
Test status
Simulation time 30629831 ps
CPU time 0.71 seconds
Started Jul 12 05:18:53 PM PDT 24
Finished Jul 12 05:18:54 PM PDT 24
Peak memory 205068 kb
Host smart-2e127df3-b1f5-46c7-a268-5afefdcfb9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035498787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2035498787
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.4001167828
Short name T1350
Test name
Test status
Simulation time 74243492644 ps
CPU time 535.68 seconds
Started Jul 12 05:19:05 PM PDT 24
Finished Jul 12 05:28:02 PM PDT 24
Peak memory 787152 kb
Host smart-06965419-7957-4bb7-8bcf-0af13330de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001167828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.4001167828
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.359401774
Short name T317
Test name
Test status
Simulation time 51196631 ps
CPU time 1.82 seconds
Started Jul 12 05:19:03 PM PDT 24
Finished Jul 12 05:19:05 PM PDT 24
Peak memory 223344 kb
Host smart-99616f39-c750-4651-a505-9fde6f6b602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359401774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.359401774
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.298952485
Short name T1415
Test name
Test status
Simulation time 9383529385 ps
CPU time 19 seconds
Started Jul 12 05:18:53 PM PDT 24
Finished Jul 12 05:19:13 PM PDT 24
Peak memory 269684 kb
Host smart-f617621a-3cd9-4d75-b304-00bdf7b096df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298952485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.298952485
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.20883164
Short name T293
Test name
Test status
Simulation time 57916772314 ps
CPU time 1180.32 seconds
Started Jul 12 05:19:00 PM PDT 24
Finished Jul 12 05:38:41 PM PDT 24
Peak memory 957172 kb
Host smart-1e1d143a-b9a3-4dea-b928-bef0d0f19379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20883164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.20883164
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3523874013
Short name T313
Test name
Test status
Simulation time 1360022284 ps
CPU time 11.06 seconds
Started Jul 12 05:18:59 PM PDT 24
Finished Jul 12 05:19:10 PM PDT 24
Peak memory 220792 kb
Host smart-30c01b14-659a-4c70-b40e-caeef53fb0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523874013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3523874013
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3368260712
Short name T190
Test name
Test status
Simulation time 686326546 ps
CPU time 1.12 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:08 PM PDT 24
Peak memory 223524 kb
Host smart-7ccf590d-684c-43d7-89f8-c17caba19e9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368260712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3368260712
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1781032782
Short name T977
Test name
Test status
Simulation time 1954991840 ps
CPU time 6.08 seconds
Started Jul 12 05:18:58 PM PDT 24
Finished Jul 12 05:19:05 PM PDT 24
Peak memory 216860 kb
Host smart-08e94238-654c-4963-9f58-3a091a793eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781032782 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1781032782
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3964451864
Short name T194
Test name
Test status
Simulation time 309617965 ps
CPU time 0.9 seconds
Started Jul 12 05:18:58 PM PDT 24
Finished Jul 12 05:18:59 PM PDT 24
Peak memory 205264 kb
Host smart-6571b5e4-5b1b-47db-831f-9dca35b941b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964451864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3964451864
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2824909470
Short name T1326
Test name
Test status
Simulation time 209040895 ps
CPU time 1.31 seconds
Started Jul 12 05:23:04 PM PDT 24
Finished Jul 12 05:23:06 PM PDT 24
Peak memory 205340 kb
Host smart-924ece92-1f25-4cf1-84fc-9a0d32c61dcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824909470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2824909470
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2406173194
Short name T469
Test name
Test status
Simulation time 10149439820 ps
CPU time 3.2 seconds
Started Jul 12 05:19:05 PM PDT 24
Finished Jul 12 05:19:09 PM PDT 24
Peak memory 205440 kb
Host smart-f1c8eb1c-9d8b-4c90-8a84-5fbec05bf4fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406173194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2406173194
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1674992392
Short name T978
Test name
Test status
Simulation time 171726812 ps
CPU time 0.98 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:08 PM PDT 24
Peak memory 205192 kb
Host smart-440cd6ad-f513-45d5-9b81-648e37dcfd7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674992392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1674992392
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3770389981
Short name T1134
Test name
Test status
Simulation time 12291390928 ps
CPU time 71.98 seconds
Started Jul 12 05:19:01 PM PDT 24
Finished Jul 12 05:20:14 PM PDT 24
Peak memory 1554700 kb
Host smart-1bf217fd-1d9a-45ae-a09d-decbedbebc34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770389981 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3770389981
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.1830019500
Short name T1454
Test name
Test status
Simulation time 1906304973 ps
CPU time 2.95 seconds
Started Jul 12 05:19:08 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 213552 kb
Host smart-77c79da6-3ecd-437b-ab1b-0e14db4fe899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830019500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.1830019500
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.1145441354
Short name T449
Test name
Test status
Simulation time 7155947330 ps
CPU time 2.45 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:09 PM PDT 24
Peak memory 205632 kb
Host smart-e0b33695-d187-4673-b98a-305ae6b9184b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145441354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.1145441354
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.1753822892
Short name T1117
Test name
Test status
Simulation time 489690040 ps
CPU time 2.34 seconds
Started Jul 12 05:19:08 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 205288 kb
Host smart-7afa5a14-497a-4f66-ab13-83b5d7819f30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753822892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.1753822892
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.4121495642
Short name T1252
Test name
Test status
Simulation time 2092097176 ps
CPU time 7.29 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:12 PM PDT 24
Peak memory 213652 kb
Host smart-86a70f69-ff1c-4161-bedd-22f83ce08910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121495642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.4121495642
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.4257351885
Short name T909
Test name
Test status
Simulation time 7848551840 ps
CPU time 31.46 seconds
Started Jul 12 05:19:00 PM PDT 24
Finished Jul 12 05:19:32 PM PDT 24
Peak memory 231736 kb
Host smart-0cee9e10-3f63-4f90-ba35-ab42ed70981e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257351885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.4257351885
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.541575764
Short name T463
Test name
Test status
Simulation time 50451881582 ps
CPU time 460.56 seconds
Started Jul 12 05:18:58 PM PDT 24
Finished Jul 12 05:26:40 PM PDT 24
Peak memory 3732548 kb
Host smart-c6c1b519-8ae4-4bcd-93c9-8ce9ca0cdd9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541575764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.541575764
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.476921143
Short name T1048
Test name
Test status
Simulation time 3278897176 ps
CPU time 44.26 seconds
Started Jul 12 05:18:59 PM PDT 24
Finished Jul 12 05:19:44 PM PDT 24
Peak memory 524652 kb
Host smart-7f9d455e-be22-4ead-86d8-5efddf527434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476921143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.476921143
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.833535087
Short name T1182
Test name
Test status
Simulation time 596615684 ps
CPU time 8.35 seconds
Started Jul 12 05:19:08 PM PDT 24
Finished Jul 12 05:19:17 PM PDT 24
Peak memory 213484 kb
Host smart-b3850f1a-5bd4-4b68-b434-d7dae94afcfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833535087 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.833535087
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1315581041
Short name T321
Test name
Test status
Simulation time 18079307 ps
CPU time 0.64 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:23:35 PM PDT 24
Peak memory 204552 kb
Host smart-631f9298-ca3e-4c52-8933-974e344ac8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315581041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1315581041
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.765933576
Short name T527
Test name
Test status
Simulation time 401271785 ps
CPU time 1.7 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:38 PM PDT 24
Peak memory 213796 kb
Host smart-65678789-b0b9-4cef-bd36-650ba7bfaa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765933576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.765933576
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.950079292
Short name T1214
Test name
Test status
Simulation time 1452483338 ps
CPU time 18.15 seconds
Started Jul 12 05:23:25 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 281056 kb
Host smart-08f2cbf4-e8ab-49e1-a5c5-74a01afc2140
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950079292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.950079292
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2896796034
Short name T83
Test name
Test status
Simulation time 4887881545 ps
CPU time 185.95 seconds
Started Jul 12 05:23:30 PM PDT 24
Finished Jul 12 05:26:36 PM PDT 24
Peak memory 781856 kb
Host smart-bc8c4860-91fc-4129-88a5-3e9043c151fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896796034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2896796034
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3056590370
Short name T1469
Test name
Test status
Simulation time 1821574471 ps
CPU time 50.27 seconds
Started Jul 12 05:23:25 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 641476 kb
Host smart-b5a4bd46-9f4c-477e-852a-070f49157892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056590370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3056590370
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2004344193
Short name T193
Test name
Test status
Simulation time 113553686 ps
CPU time 1.26 seconds
Started Jul 12 05:23:28 PM PDT 24
Finished Jul 12 05:23:31 PM PDT 24
Peak memory 205112 kb
Host smart-464dc4b6-9492-40b3-8b3b-ca7292bce7e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004344193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2004344193
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1645585078
Short name T713
Test name
Test status
Simulation time 618858385 ps
CPU time 3.97 seconds
Started Jul 12 05:23:26 PM PDT 24
Finished Jul 12 05:23:31 PM PDT 24
Peak memory 205332 kb
Host smart-58191387-30c9-4378-84a0-b2909e0783be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645585078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1645585078
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2849771508
Short name T690
Test name
Test status
Simulation time 33895493354 ps
CPU time 108.81 seconds
Started Jul 12 05:23:27 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 1099748 kb
Host smart-66d56ff1-775c-429d-86e6-500c53a53f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849771508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2849771508
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.214752681
Short name T262
Test name
Test status
Simulation time 376086791 ps
CPU time 15.07 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:41 PM PDT 24
Peak memory 205324 kb
Host smart-0bf9d33e-ce3f-4f26-a21a-5c7113ee69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214752681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.214752681
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.3632849450
Short name T729
Test name
Test status
Simulation time 103569330 ps
CPU time 0.65 seconds
Started Jul 12 05:23:17 PM PDT 24
Finished Jul 12 05:23:19 PM PDT 24
Peak memory 204988 kb
Host smart-ba766cc4-18d3-4c78-b938-65e11ead4d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632849450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3632849450
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3237606915
Short name T633
Test name
Test status
Simulation time 13400293757 ps
CPU time 18.96 seconds
Started Jul 12 05:23:25 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 311408 kb
Host smart-c8c3abb7-9ec0-4f1c-bfd2-d23e3d35bc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237606915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3237606915
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.4058677567
Short name T632
Test name
Test status
Simulation time 859460187 ps
CPU time 19.57 seconds
Started Jul 12 05:23:25 PM PDT 24
Finished Jul 12 05:23:46 PM PDT 24
Peak memory 256916 kb
Host smart-d207ca8d-f5b7-42b8-b679-5afd97b8e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058677567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.4058677567
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2723513797
Short name T398
Test name
Test status
Simulation time 1427124854 ps
CPU time 26.96 seconds
Started Jul 12 05:23:20 PM PDT 24
Finished Jul 12 05:23:49 PM PDT 24
Peak memory 326864 kb
Host smart-1b09abcb-479f-4248-b5a2-e3886e341060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723513797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2723513797
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3803989672
Short name T13
Test name
Test status
Simulation time 648725731 ps
CPU time 10.04 seconds
Started Jul 12 05:23:27 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 216780 kb
Host smart-80e27d3d-e346-4701-a405-2f707dfbc390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803989672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3803989672
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.263806115
Short name T639
Test name
Test status
Simulation time 2407136487 ps
CPU time 5.98 seconds
Started Jul 12 05:23:31 PM PDT 24
Finished Jul 12 05:23:38 PM PDT 24
Peak memory 213680 kb
Host smart-9a1a944a-d220-4bb9-bdaf-becc3dd0eb8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263806115 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.263806115
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1589359379
Short name T1435
Test name
Test status
Simulation time 3507071988 ps
CPU time 1.38 seconds
Started Jul 12 05:23:26 PM PDT 24
Finished Jul 12 05:23:30 PM PDT 24
Peak memory 205476 kb
Host smart-65885a56-b8c9-4881-90f3-271850231b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589359379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1589359379
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2206465942
Short name T1536
Test name
Test status
Simulation time 465419902 ps
CPU time 1.25 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 205564 kb
Host smart-b03e6be6-7f2e-4c21-a4bd-ff8bfb761111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206465942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2206465942
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.1870985328
Short name T1451
Test name
Test status
Simulation time 878647481 ps
CPU time 2.56 seconds
Started Jul 12 05:23:28 PM PDT 24
Finished Jul 12 05:23:32 PM PDT 24
Peak memory 205376 kb
Host smart-47189986-461f-476b-8623-026e4ba0627e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870985328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.1870985328
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3828639707
Short name T618
Test name
Test status
Simulation time 110250607 ps
CPU time 1.12 seconds
Started Jul 12 05:23:27 PM PDT 24
Finished Jul 12 05:23:30 PM PDT 24
Peak memory 205248 kb
Host smart-4e63be0d-ab07-40fb-bb5a-16beb0fff2a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828639707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3828639707
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1490062098
Short name T279
Test name
Test status
Simulation time 5048800349 ps
CPU time 7.14 seconds
Started Jul 12 05:23:28 PM PDT 24
Finished Jul 12 05:23:36 PM PDT 24
Peak memory 213696 kb
Host smart-d9f5f57f-1523-4288-b075-80ff89dbdd82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490062098 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1490062098
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.4002558821
Short name T1254
Test name
Test status
Simulation time 5937986686 ps
CPU time 29.51 seconds
Started Jul 12 05:23:27 PM PDT 24
Finished Jul 12 05:23:58 PM PDT 24
Peak memory 918472 kb
Host smart-788a6b53-91a4-469c-8a33-85f61c8d649d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002558821 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.4002558821
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.138966460
Short name T1033
Test name
Test status
Simulation time 4194256298 ps
CPU time 2.84 seconds
Started Jul 12 05:23:30 PM PDT 24
Finished Jul 12 05:23:34 PM PDT 24
Peak memory 213760 kb
Host smart-508c26c7-fa4e-4f4d-a358-7ad1f17ac5b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138966460 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_nack_acqfull.138966460
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.2983918396
Short name T58
Test name
Test status
Simulation time 1067736319 ps
CPU time 2.41 seconds
Started Jul 12 05:23:27 PM PDT 24
Finished Jul 12 05:23:31 PM PDT 24
Peak memory 205420 kb
Host smart-109080cb-e9aa-49c6-ac70-c0366ba2ae14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983918396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.2983918396
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.445395159
Short name T1414
Test name
Test status
Simulation time 1049789791 ps
CPU time 2.35 seconds
Started Jul 12 05:23:26 PM PDT 24
Finished Jul 12 05:23:30 PM PDT 24
Peak memory 205212 kb
Host smart-644b0d40-6631-4d89-9aa1-e9c33be1b53e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445395159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_smbus_maxlen.445395159
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3441842693
Short name T365
Test name
Test status
Simulation time 3025294327 ps
CPU time 8.7 seconds
Started Jul 12 05:23:36 PM PDT 24
Finished Jul 12 05:23:47 PM PDT 24
Peak memory 217216 kb
Host smart-906acacf-36a7-4249-88ef-90bdd1740598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441842693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3441842693
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4095707847
Short name T1492
Test name
Test status
Simulation time 529120472 ps
CPU time 6.59 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:43 PM PDT 24
Peak memory 205628 kb
Host smart-11266480-1bca-45dd-8e38-150586b8eade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095707847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4095707847
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3704187342
Short name T1174
Test name
Test status
Simulation time 28271505735 ps
CPU time 67.14 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:24:42 PM PDT 24
Peak memory 1145452 kb
Host smart-3c6e8333-815c-452e-8c17-053af19beced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704187342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3704187342
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2897584081
Short name T711
Test name
Test status
Simulation time 1786840230 ps
CPU time 13.18 seconds
Started Jul 12 05:23:26 PM PDT 24
Finished Jul 12 05:23:41 PM PDT 24
Peak memory 371696 kb
Host smart-c9bcc396-6b61-4ddf-9263-4cefb7337906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897584081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2897584081
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1826536198
Short name T1524
Test name
Test status
Simulation time 26694102995 ps
CPU time 7.08 seconds
Started Jul 12 05:23:28 PM PDT 24
Finished Jul 12 05:23:36 PM PDT 24
Peak memory 213756 kb
Host smart-73486c84-941a-4539-aa1a-58de894081d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826536198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1826536198
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.1788199944
Short name T1537
Test name
Test status
Simulation time 347384167 ps
CPU time 4.9 seconds
Started Jul 12 05:23:24 PM PDT 24
Finished Jul 12 05:23:31 PM PDT 24
Peak memory 205428 kb
Host smart-e7a9cc4b-d708-40b3-9625-a792773377f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788199944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.1788199944
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.497834952
Short name T1108
Test name
Test status
Simulation time 22648071 ps
CPU time 0.66 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:23:38 PM PDT 24
Peak memory 204420 kb
Host smart-52c0832a-0ccc-4e0f-8db2-88131de39f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497834952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.497834952
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2645711378
Short name T462
Test name
Test status
Simulation time 58370707 ps
CPU time 1.48 seconds
Started Jul 12 05:23:36 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 213568 kb
Host smart-41f779cf-642d-4b13-af17-f22f8177be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645711378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2645711378
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.4209929220
Short name T579
Test name
Test status
Simulation time 2145250219 ps
CPU time 5.77 seconds
Started Jul 12 05:23:36 PM PDT 24
Finished Jul 12 05:23:44 PM PDT 24
Peak memory 254048 kb
Host smart-a661c331-c2a7-44f7-b501-e7763e94b9ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209929220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.4209929220
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.988208517
Short name T604
Test name
Test status
Simulation time 3177118313 ps
CPU time 50.44 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 568812 kb
Host smart-ab2f4b90-751f-4301-9ae8-72b74943ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988208517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.988208517
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3759537851
Short name T629
Test name
Test status
Simulation time 5763337940 ps
CPU time 55.07 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 607592 kb
Host smart-a540e21f-998c-4361-8eb6-3954c966b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759537851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3759537851
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2721549702
Short name T250
Test name
Test status
Simulation time 1608777623 ps
CPU time 1.19 seconds
Started Jul 12 05:23:36 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 205056 kb
Host smart-e9903d9d-2408-4de9-b60b-f20b48b386a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721549702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2721549702
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.60398103
Short name T457
Test name
Test status
Simulation time 143706233 ps
CPU time 3.38 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:23:40 PM PDT 24
Peak memory 205320 kb
Host smart-90f8d9d6-cdf6-4ea6-a0d1-df5065b3ef71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60398103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.60398103
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3603935169
Short name T850
Test name
Test status
Simulation time 2931499772 ps
CPU time 75.54 seconds
Started Jul 12 05:23:37 PM PDT 24
Finished Jul 12 05:24:54 PM PDT 24
Peak memory 870932 kb
Host smart-26d76707-20a9-4612-9f12-d806a80c6d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603935169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3603935169
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3434958520
Short name T21
Test name
Test status
Simulation time 3212541872 ps
CPU time 4.63 seconds
Started Jul 12 05:23:32 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 205428 kb
Host smart-e1e39eb3-5bf0-4bfd-b4ed-69ed5f996ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434958520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3434958520
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.1951965471
Short name T682
Test name
Test status
Simulation time 80900746 ps
CPU time 0.68 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:23:35 PM PDT 24
Peak memory 205052 kb
Host smart-9b122356-093f-403f-befc-c9bea1e0db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951965471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1951965471
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2453054030
Short name T1099
Test name
Test status
Simulation time 1452539473 ps
CPU time 11.97 seconds
Started Jul 12 05:23:37 PM PDT 24
Finished Jul 12 05:23:51 PM PDT 24
Peak memory 296912 kb
Host smart-01fa9e93-ac34-43aa-8633-9e0caf9979d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453054030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2453054030
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1262346430
Short name T244
Test name
Test status
Simulation time 399271687 ps
CPU time 2.04 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 221416 kb
Host smart-0eb0d35f-3780-498f-a975-3eb1b32bd58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262346430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1262346430
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1048145644
Short name T566
Test name
Test status
Simulation time 1876136033 ps
CPU time 40.36 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 432340 kb
Host smart-f830f69b-a302-415f-b886-879ef11ad26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048145644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1048145644
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3371363163
Short name T1345
Test name
Test status
Simulation time 863819597 ps
CPU time 7.8 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 213504 kb
Host smart-13b2ad80-5484-4a08-9095-899999c08741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371363163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3371363163
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3067324053
Short name T504
Test name
Test status
Simulation time 5811907037 ps
CPU time 7.93 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 221868 kb
Host smart-1f303822-ad88-4e05-a85d-de762759a7ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067324053 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3067324053
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.242326080
Short name T1403
Test name
Test status
Simulation time 761467285 ps
CPU time 1.52 seconds
Started Jul 12 05:23:32 PM PDT 24
Finished Jul 12 05:23:34 PM PDT 24
Peak memory 205404 kb
Host smart-fc9d8212-5f98-4ad9-b51e-b79ef306e8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242326080 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.242326080
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.911683390
Short name T819
Test name
Test status
Simulation time 229476465 ps
CPU time 0.83 seconds
Started Jul 12 05:23:32 PM PDT 24
Finished Jul 12 05:23:34 PM PDT 24
Peak memory 205320 kb
Host smart-4f35f4c1-47f0-4bec-8eff-e226570a3ba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911683390 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.911683390
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.3509211336
Short name T1028
Test name
Test status
Simulation time 859011472 ps
CPU time 2.31 seconds
Started Jul 12 05:23:36 PM PDT 24
Finished Jul 12 05:23:40 PM PDT 24
Peak memory 205416 kb
Host smart-b4d535fc-c8f0-4f02-84de-c8ed158d4016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509211336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.3509211336
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1487366394
Short name T843
Test name
Test status
Simulation time 871596195 ps
CPU time 5.49 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:41 PM PDT 24
Peak memory 221608 kb
Host smart-979723a2-a3c6-4ab2-8fc4-5b5232921446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487366394 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1487366394
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2635821650
Short name T1185
Test name
Test status
Simulation time 6416060843 ps
CPU time 68.34 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:24:45 PM PDT 24
Peak memory 1682856 kb
Host smart-a5e9d7ec-1dd0-4079-8316-ae2e9a0d1584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635821650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2635821650
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.2144116043
Short name T51
Test name
Test status
Simulation time 561562115 ps
CPU time 2.85 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 213556 kb
Host smart-9f13939d-ccda-4b8d-9ea8-a0d88e063c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144116043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.2144116043
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.2972054030
Short name T344
Test name
Test status
Simulation time 2350648939 ps
CPU time 2.54 seconds
Started Jul 12 05:23:41 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 205632 kb
Host smart-06ed7be0-1929-49de-8df8-1e0487f4df67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972054030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.2972054030
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.2964478408
Short name T716
Test name
Test status
Simulation time 494677509 ps
CPU time 2.31 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:38 PM PDT 24
Peak memory 205312 kb
Host smart-e0282104-86c7-4767-8022-cecb127aba62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964478408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.2964478408
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1860831702
Short name T1396
Test name
Test status
Simulation time 2465408995 ps
CPU time 15.22 seconds
Started Jul 12 05:23:34 PM PDT 24
Finished Jul 12 05:23:50 PM PDT 24
Peak memory 213688 kb
Host smart-6ad596cc-53d7-4d71-9881-e5c05b2c63bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860831702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1860831702
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.4033791815
Short name T901
Test name
Test status
Simulation time 5828475798 ps
CPU time 26.87 seconds
Started Jul 12 05:23:33 PM PDT 24
Finished Jul 12 05:24:00 PM PDT 24
Peak memory 238952 kb
Host smart-001b0513-546b-4535-bb7b-ff87abe1af5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033791815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.4033791815
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2635129974
Short name T1219
Test name
Test status
Simulation time 48036631657 ps
CPU time 117.42 seconds
Started Jul 12 05:23:32 PM PDT 24
Finished Jul 12 05:25:31 PM PDT 24
Peak memory 1552944 kb
Host smart-b208f742-8a8f-4a9c-9e3c-16d8efddade9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635129974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2635129974
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.37835475
Short name T1554
Test name
Test status
Simulation time 3729495078 ps
CPU time 77.14 seconds
Started Jul 12 05:23:35 PM PDT 24
Finished Jul 12 05:24:54 PM PDT 24
Peak memory 575912 kb
Host smart-b7c676b8-18b7-460b-8cc1-c1b05e953dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37835475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_stretch.37835475
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2209329633
Short name T1166
Test name
Test status
Simulation time 9623081023 ps
CPU time 7.27 seconds
Started Jul 12 05:23:37 PM PDT 24
Finished Jul 12 05:23:46 PM PDT 24
Peak memory 219072 kb
Host smart-39254ca7-05eb-4c37-8eb5-f72b388d51eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209329633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2209329633
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.2473032248
Short name T480
Test name
Test status
Simulation time 448730555 ps
CPU time 4.73 seconds
Started Jul 12 05:24:19 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 205424 kb
Host smart-ae7138e5-33b4-401a-b408-b020646e33dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473032248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2473032248
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1939070648
Short name T502
Test name
Test status
Simulation time 15460412 ps
CPU time 0.64 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:23:52 PM PDT 24
Peak memory 204492 kb
Host smart-32d0166a-f0ad-4e52-b902-e8205fcead26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939070648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1939070648
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2361526256
Short name T34
Test name
Test status
Simulation time 933426355 ps
CPU time 3.1 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 216616 kb
Host smart-0125c491-f2d2-402c-8f01-1f5b00b26c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361526256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2361526256
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3151286811
Short name T1569
Test name
Test status
Simulation time 277712708 ps
CPU time 4.98 seconds
Started Jul 12 05:23:43 PM PDT 24
Finished Jul 12 05:23:49 PM PDT 24
Peak memory 254604 kb
Host smart-cbacfd93-a708-43ff-b4c8-2a252ba38798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151286811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3151286811
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.808287302
Short name T1193
Test name
Test status
Simulation time 23146816243 ps
CPU time 106.66 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:25:29 PM PDT 24
Peak memory 551424 kb
Host smart-e10ae9a8-4f65-40ed-b937-c4cd9069d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808287302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.808287302
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1625847348
Short name T1402
Test name
Test status
Simulation time 5555774102 ps
CPU time 91.49 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 870920 kb
Host smart-49140182-0bea-4b70-a0b4-c97a94dab429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625847348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1625847348
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3606553936
Short name T142
Test name
Test status
Simulation time 149319241 ps
CPU time 1.21 seconds
Started Jul 12 05:23:42 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 205124 kb
Host smart-d9210eb9-e40a-4ac5-a5fe-cbb492c18e10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606553936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3606553936
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.4235027072
Short name T960
Test name
Test status
Simulation time 231320862 ps
CPU time 5.66 seconds
Started Jul 12 05:23:42 PM PDT 24
Finished Jul 12 05:23:50 PM PDT 24
Peak memory 205280 kb
Host smart-a9486bb2-464b-4cf8-8a1c-41dc2c74a9fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235027072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.4235027072
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1372498577
Short name T118
Test name
Test status
Simulation time 7902387903 ps
CPU time 75.61 seconds
Started Jul 12 05:23:44 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 1034644 kb
Host smart-68da3f75-0f1f-47f5-8836-94665f9bb7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372498577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1372498577
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1739002249
Short name T764
Test name
Test status
Simulation time 601605274 ps
CPU time 23.99 seconds
Started Jul 12 05:23:53 PM PDT 24
Finished Jul 12 05:24:18 PM PDT 24
Peak memory 205584 kb
Host smart-399aa563-8ecd-4e93-ab07-04f963a0cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739002249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1739002249
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.3561587947
Short name T620
Test name
Test status
Simulation time 41027596 ps
CPU time 0.68 seconds
Started Jul 12 05:23:43 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 205048 kb
Host smart-08945fbd-b920-4be3-b94f-d2bb43486d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561587947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3561587947
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2959997805
Short name T972
Test name
Test status
Simulation time 6978353087 ps
CPU time 70.66 seconds
Started Jul 12 05:23:44 PM PDT 24
Finished Jul 12 05:24:56 PM PDT 24
Peak memory 205484 kb
Host smart-af1ec3c1-0a47-40f9-af51-fcfc89e948fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959997805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2959997805
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.702345348
Short name T807
Test name
Test status
Simulation time 263474131 ps
CPU time 2.17 seconds
Started Jul 12 05:23:42 PM PDT 24
Finished Jul 12 05:23:46 PM PDT 24
Peak memory 213376 kb
Host smart-fa44b482-c268-40f1-84e6-cb3e894dce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702345348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.702345348
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1076651808
Short name T1069
Test name
Test status
Simulation time 1556201278 ps
CPU time 32.16 seconds
Started Jul 12 05:23:38 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 409176 kb
Host smart-296e4cac-07bf-4d32-89fc-b833da6b0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076651808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1076651808
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2572355230
Short name T510
Test name
Test status
Simulation time 847356067 ps
CPU time 14.46 seconds
Started Jul 12 05:23:41 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 216140 kb
Host smart-2695a45c-298c-4c03-96b2-4d78680574cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572355230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2572355230
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.164017395
Short name T1029
Test name
Test status
Simulation time 2905766111 ps
CPU time 8.23 seconds
Started Jul 12 05:23:52 PM PDT 24
Finished Jul 12 05:24:01 PM PDT 24
Peak memory 213600 kb
Host smart-1284f3a5-689a-4bcb-9469-1031fb09c276
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164017395 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.164017395
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.195504382
Short name T403
Test name
Test status
Simulation time 803327695 ps
CPU time 1.96 seconds
Started Jul 12 05:23:41 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 206136 kb
Host smart-5c996879-4c30-41b8-b91d-da22dfcd70c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195504382 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.195504382
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3830762500
Short name T1122
Test name
Test status
Simulation time 474075005 ps
CPU time 1.14 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:23:43 PM PDT 24
Peak memory 205360 kb
Host smart-386fdec9-19a7-4fa8-a0ba-72ecee90e87f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830762500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3830762500
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1473972474
Short name T933
Test name
Test status
Simulation time 384610864 ps
CPU time 2.77 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:23:54 PM PDT 24
Peak memory 205296 kb
Host smart-2c4ed31f-85bd-490c-89d0-f5a641b0a387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473972474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1473972474
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.3534204583
Short name T104
Test name
Test status
Simulation time 654091488 ps
CPU time 1.5 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 205320 kb
Host smart-f9e83e48-51ac-4bad-a716-67c21bd5324d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534204583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.3534204583
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2320290244
Short name T1058
Test name
Test status
Simulation time 2913111905 ps
CPU time 3.85 seconds
Started Jul 12 05:23:44 PM PDT 24
Finished Jul 12 05:23:49 PM PDT 24
Peak memory 213704 kb
Host smart-b57efc60-6ff7-4ab8-9159-67d352fd6274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320290244 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2320290244
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.946619781
Short name T466
Test name
Test status
Simulation time 8472731211 ps
CPU time 25.13 seconds
Started Jul 12 05:23:41 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 459388 kb
Host smart-519f5abe-e594-40e6-b130-799f128e6edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946619781 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.946619781
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.3306849921
Short name T1181
Test name
Test status
Simulation time 1778304629 ps
CPU time 2.5 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 213480 kb
Host smart-5249f0ba-5f61-490d-a11c-9a8596000b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306849921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.3306849921
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.3743142786
Short name T1101
Test name
Test status
Simulation time 567327341 ps
CPU time 3.11 seconds
Started Jul 12 05:23:48 PM PDT 24
Finished Jul 12 05:23:52 PM PDT 24
Peak memory 205256 kb
Host smart-589dc10d-c242-4f20-9566-c92c152f23d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743142786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.3743142786
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.1674181682
Short name T614
Test name
Test status
Simulation time 952680027 ps
CPU time 2.27 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:23:54 PM PDT 24
Peak memory 205288 kb
Host smart-ae6e24c0-d382-43dc-b069-e9bebe8075d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674181682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.1674181682
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3178194460
Short name T770
Test name
Test status
Simulation time 2934856771 ps
CPU time 24.61 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 213708 kb
Host smart-1d9c429c-4cf6-4977-acda-e27f2b402caa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178194460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3178194460
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1324957821
Short name T735
Test name
Test status
Simulation time 6212640236 ps
CPU time 19.22 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:24:01 PM PDT 24
Peak memory 213624 kb
Host smart-c26e12a9-23fc-4071-9dbd-749d03c84e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324957821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1324957821
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.4137394940
Short name T360
Test name
Test status
Simulation time 43551946832 ps
CPU time 970.76 seconds
Started Jul 12 05:23:42 PM PDT 24
Finished Jul 12 05:39:55 PM PDT 24
Peak memory 6070708 kb
Host smart-b2678a62-9b3c-4950-b173-347d2e17f88b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137394940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.4137394940
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3965033964
Short name T1566
Test name
Test status
Simulation time 277458126 ps
CPU time 4.8 seconds
Started Jul 12 05:23:40 PM PDT 24
Finished Jul 12 05:23:45 PM PDT 24
Peak memory 213740 kb
Host smart-5b0d0826-b007-4282-87c5-1f59da43b24a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965033964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3965033964
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2399010110
Short name T1025
Test name
Test status
Simulation time 1236295204 ps
CPU time 6.96 seconds
Started Jul 12 05:23:43 PM PDT 24
Finished Jul 12 05:23:51 PM PDT 24
Peak memory 221688 kb
Host smart-6c109752-8f3a-4b5e-ad21-0f6df9ae494b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399010110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2399010110
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.1388085875
Short name T828
Test name
Test status
Simulation time 463850579 ps
CPU time 6.44 seconds
Started Jul 12 05:23:52 PM PDT 24
Finished Jul 12 05:23:59 PM PDT 24
Peak memory 205828 kb
Host smart-4d46fadb-dab7-49d5-96f1-0d45fc9398bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388085875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1388085875
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3408310381
Short name T552
Test name
Test status
Simulation time 17333372 ps
CPU time 0.68 seconds
Started Jul 12 05:23:58 PM PDT 24
Finished Jul 12 05:23:59 PM PDT 24
Peak memory 204648 kb
Host smart-5d93100c-39fb-4492-a632-30a242256cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408310381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3408310381
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2129935414
Short name T712
Test name
Test status
Simulation time 187292512 ps
CPU time 2.42 seconds
Started Jul 12 05:23:54 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 231080 kb
Host smart-3d1dd20e-b38f-488b-9572-da9144ac66e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129935414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2129935414
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.754975178
Short name T1259
Test name
Test status
Simulation time 800951957 ps
CPU time 22.88 seconds
Started Jul 12 05:23:48 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 299196 kb
Host smart-963b3f36-5535-4094-aa25-c435c11189e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754975178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.754975178
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2901892490
Short name T803
Test name
Test status
Simulation time 6590641084 ps
CPU time 52.97 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 557620 kb
Host smart-5efa59d9-d4c1-461b-b07b-83a0a80f88ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901892490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2901892490
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.963188391
Short name T1466
Test name
Test status
Simulation time 5231010552 ps
CPU time 40.63 seconds
Started Jul 12 05:23:52 PM PDT 24
Finished Jul 12 05:24:33 PM PDT 24
Peak memory 519572 kb
Host smart-f3c4fb71-4405-41fc-95dd-509bd5939ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963188391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.963188391
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.155465343
Short name T1061
Test name
Test status
Simulation time 2149857360 ps
CPU time 1.06 seconds
Started Jul 12 05:23:51 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 205040 kb
Host smart-bf1784f3-fd9c-4a74-8b4e-293d8edd600b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155465343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.155465343
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1564169102
Short name T1337
Test name
Test status
Simulation time 158594310 ps
CPU time 3.48 seconds
Started Jul 12 05:23:53 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 205192 kb
Host smart-3add1bff-5df4-414f-8b52-962a3192fcea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564169102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1564169102
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2757206023
Short name T1008
Test name
Test status
Simulation time 3753044639 ps
CPU time 95.41 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:25:27 PM PDT 24
Peak memory 1141988 kb
Host smart-36e2ae31-bfdb-4027-ab12-251dfec8f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757206023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2757206023
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2768787855
Short name T261
Test name
Test status
Simulation time 359861359 ps
CPU time 6.11 seconds
Started Jul 12 05:24:01 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 205240 kb
Host smart-b817a13c-7299-4ca3-854c-1fc52ba2f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768787855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2768787855
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.2511260411
Short name T1565
Test name
Test status
Simulation time 31455217 ps
CPU time 0.69 seconds
Started Jul 12 05:23:52 PM PDT 24
Finished Jul 12 05:23:54 PM PDT 24
Peak memory 204972 kb
Host smart-ead45ca2-285e-4cba-b38d-7596cf386707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511260411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2511260411
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3022948654
Short name T1467
Test name
Test status
Simulation time 7249297715 ps
CPU time 52.24 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 227264 kb
Host smart-a529410a-7c1e-4544-895c-b176d44be454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022948654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3022948654
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.3260848756
Short name T750
Test name
Test status
Simulation time 1785734579 ps
CPU time 12.94 seconds
Started Jul 12 05:23:52 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 312556 kb
Host smart-f4377631-4087-4ef5-ab01-a2820449edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260848756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.3260848756
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2440196724
Short name T695
Test name
Test status
Simulation time 8766098849 ps
CPU time 50.84 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:24:42 PM PDT 24
Peak memory 316124 kb
Host smart-02b3900b-c5b0-483e-a04c-7c5a52cfa087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440196724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2440196724
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.325707405
Short name T1130
Test name
Test status
Simulation time 2335823746 ps
CPU time 24.17 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:24:15 PM PDT 24
Peak memory 213592 kb
Host smart-c2ef4c18-5bb3-4faf-a7a7-b51e4635739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325707405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.325707405
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1414255384
Short name T63
Test name
Test status
Simulation time 3972627150 ps
CPU time 5.49 seconds
Started Jul 12 05:23:58 PM PDT 24
Finished Jul 12 05:24:05 PM PDT 24
Peak memory 220996 kb
Host smart-3f533e62-852d-4864-b260-4b454231b4ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414255384 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1414255384
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3553881526
Short name T1388
Test name
Test status
Simulation time 483596015 ps
CPU time 1.15 seconds
Started Jul 12 05:24:11 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 213540 kb
Host smart-19f55d72-0b0a-40c2-86cf-031e5ca6ec4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553881526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3553881526
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1669461947
Short name T1186
Test name
Test status
Simulation time 302871252 ps
CPU time 0.88 seconds
Started Jul 12 05:23:54 PM PDT 24
Finished Jul 12 05:23:56 PM PDT 24
Peak memory 205284 kb
Host smart-f332e59e-da11-43c4-b0ef-e9ac2476773e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669461947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1669461947
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.2922165705
Short name T1109
Test name
Test status
Simulation time 4089641666 ps
CPU time 2.09 seconds
Started Jul 12 05:23:59 PM PDT 24
Finished Jul 12 05:24:02 PM PDT 24
Peak memory 205620 kb
Host smart-3044a567-17ca-4593-9032-2bdbadd90de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922165705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.2922165705
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.1744238639
Short name T802
Test name
Test status
Simulation time 227408383 ps
CPU time 1.35 seconds
Started Jul 12 05:23:57 PM PDT 24
Finished Jul 12 05:23:59 PM PDT 24
Peak memory 205320 kb
Host smart-1a9dfc98-4e9c-4ae5-89bf-a7c049a1e8e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744238639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.1744238639
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2833221319
Short name T1304
Test name
Test status
Simulation time 842614713 ps
CPU time 5.64 seconds
Started Jul 12 05:23:48 PM PDT 24
Finished Jul 12 05:23:55 PM PDT 24
Peak memory 219220 kb
Host smart-4449be71-caa0-4c1e-b249-9fa12deecfb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833221319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2833221319
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2102537203
Short name T1434
Test name
Test status
Simulation time 7523810900 ps
CPU time 11.43 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:24:02 PM PDT 24
Peak memory 510112 kb
Host smart-2cac40d3-3498-4b66-b97e-9cc6b8d0faa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102537203 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2102537203
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2362403944
Short name T1449
Test name
Test status
Simulation time 1082078962 ps
CPU time 2.94 seconds
Started Jul 12 05:23:59 PM PDT 24
Finished Jul 12 05:24:03 PM PDT 24
Peak memory 213608 kb
Host smart-ad29587d-b877-468a-bec0-cd811b7df6be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362403944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2362403944
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.3510700811
Short name T530
Test name
Test status
Simulation time 1492274444 ps
CPU time 2.29 seconds
Started Jul 12 05:23:59 PM PDT 24
Finished Jul 12 05:24:02 PM PDT 24
Peak memory 205412 kb
Host smart-69013e6e-87a1-4667-8631-331438307e9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510700811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.3510700811
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.1893022934
Short name T753
Test name
Test status
Simulation time 837784226 ps
CPU time 2.16 seconds
Started Jul 12 05:23:57 PM PDT 24
Finished Jul 12 05:24:00 PM PDT 24
Peak memory 205196 kb
Host smart-c7c1e4f5-a57d-40ac-82be-87e80e9fde49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893022934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.1893022934
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.488445557
Short name T1341
Test name
Test status
Simulation time 357427525 ps
CPU time 10.93 seconds
Started Jul 12 05:23:50 PM PDT 24
Finished Jul 12 05:24:02 PM PDT 24
Peak memory 213808 kb
Host smart-8282fe94-477f-46e5-8b7b-d775b548993b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488445557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.488445557
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1935161431
Short name T501
Test name
Test status
Simulation time 5052395739 ps
CPU time 54.78 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:24:45 PM PDT 24
Peak memory 217828 kb
Host smart-e8670ae7-e659-4cd7-9cb8-d3f029c3a2f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935161431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1935161431
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2715415680
Short name T335
Test name
Test status
Simulation time 25934132785 ps
CPU time 9.19 seconds
Started Jul 12 05:23:51 PM PDT 24
Finished Jul 12 05:24:01 PM PDT 24
Peak memory 233220 kb
Host smart-f5eb0a1d-d3fc-420e-97fa-4fc1535ffa76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715415680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2715415680
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.407537854
Short name T676
Test name
Test status
Simulation time 165654745 ps
CPU time 1.17 seconds
Started Jul 12 05:23:49 PM PDT 24
Finished Jul 12 05:23:51 PM PDT 24
Peak memory 205308 kb
Host smart-ad94a7d4-da16-45b8-8c7f-3e0e190fcaee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407537854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.407537854
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.4287057950
Short name T832
Test name
Test status
Simulation time 2815407279 ps
CPU time 6.17 seconds
Started Jul 12 05:23:58 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 213676 kb
Host smart-43513360-0f12-472b-b54f-55d0c294a025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287057950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.4287057950
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.1802114356
Short name T497
Test name
Test status
Simulation time 101547157 ps
CPU time 1.8 seconds
Started Jul 12 05:23:56 PM PDT 24
Finished Jul 12 05:23:59 PM PDT 24
Peak memory 214500 kb
Host smart-da6ee687-0f00-42cd-9a14-3173e13d54f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802114356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.1802114356
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.873113917
Short name T571
Test name
Test status
Simulation time 157434166 ps
CPU time 0.63 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:10 PM PDT 24
Peak memory 204664 kb
Host smart-6bbde268-1116-4987-87e0-43c8025e78c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873113917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.873113917
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2349957612
Short name T1045
Test name
Test status
Simulation time 665665690 ps
CPU time 1.63 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:07 PM PDT 24
Peak memory 213568 kb
Host smart-2973affa-47a6-4d37-879e-a87bebe7bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349957612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2349957612
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1291061707
Short name T636
Test name
Test status
Simulation time 648735274 ps
CPU time 16.06 seconds
Started Jul 12 05:23:58 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 271824 kb
Host smart-1539af05-d135-4502-8055-99a37efd1055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291061707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1291061707
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3095699979
Short name T30
Test name
Test status
Simulation time 2278696360 ps
CPU time 75.77 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:25:20 PM PDT 24
Peak memory 717360 kb
Host smart-b1686b0a-b1a9-4c7a-9b40-014794c7dd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095699979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3095699979
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2605747355
Short name T1064
Test name
Test status
Simulation time 5291458722 ps
CPU time 203.06 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:27:28 PM PDT 24
Peak memory 853676 kb
Host smart-d0c61442-e082-4253-a1da-1892789eadb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605747355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2605747355
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2936359726
Short name T1328
Test name
Test status
Simulation time 282675943 ps
CPU time 9.38 seconds
Started Jul 12 05:24:01 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 234984 kb
Host smart-16cb2dcc-75fd-4217-83ba-303241404590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936359726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2936359726
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2524300670
Short name T1076
Test name
Test status
Simulation time 5659211669 ps
CPU time 60.07 seconds
Started Jul 12 05:23:56 PM PDT 24
Finished Jul 12 05:24:56 PM PDT 24
Peak memory 848912 kb
Host smart-05231932-1c68-4322-a8e4-0610d934f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524300670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2524300670
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3597186716
Short name T263
Test name
Test status
Simulation time 494184002 ps
CPU time 10.6 seconds
Started Jul 12 05:24:02 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 205220 kb
Host smart-c06acee0-c1da-4a69-bb77-95cad8e733b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597186716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3597186716
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.421183932
Short name T402
Test name
Test status
Simulation time 75004343 ps
CPU time 0.7 seconds
Started Jul 12 05:23:58 PM PDT 24
Finished Jul 12 05:24:01 PM PDT 24
Peak memory 205128 kb
Host smart-68152642-1aba-4571-80ff-3a1601cb3873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421183932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.421183932
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.618042162
Short name T1128
Test name
Test status
Simulation time 69704836959 ps
CPU time 2767.44 seconds
Started Jul 12 05:24:00 PM PDT 24
Finished Jul 12 06:10:08 PM PDT 24
Peak memory 213552 kb
Host smart-2260623f-e8bd-437b-a214-1ee8fbbc7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618042162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.618042162
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.84464281
Short name T1089
Test name
Test status
Simulation time 1398517939 ps
CPU time 63.44 seconds
Started Jul 12 05:23:57 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 399056 kb
Host smart-864f4201-94fe-4861-8ca3-b0be78b8fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84464281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.84464281
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.783487105
Short name T691
Test name
Test status
Simulation time 3043301128 ps
CPU time 72.09 seconds
Started Jul 12 05:24:05 PM PDT 24
Finished Jul 12 05:25:18 PM PDT 24
Peak memory 356928 kb
Host smart-05a38b2a-763b-45c5-b01d-557217f119e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783487105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.783487105
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2792542985
Short name T1313
Test name
Test status
Simulation time 644670123 ps
CPU time 28.43 seconds
Started Jul 12 05:24:00 PM PDT 24
Finished Jul 12 05:24:29 PM PDT 24
Peak memory 213448 kb
Host smart-97ae2c3c-d04d-409b-b92a-c92e51e120ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792542985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2792542985
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.196926301
Short name T911
Test name
Test status
Simulation time 10926181855 ps
CPU time 5.98 seconds
Started Jul 12 05:24:13 PM PDT 24
Finished Jul 12 05:24:20 PM PDT 24
Peak memory 213704 kb
Host smart-01464d69-407e-4383-8bc5-98813034380d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196926301 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.196926301
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4035895524
Short name T1169
Test name
Test status
Simulation time 813948347 ps
CPU time 0.93 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 205336 kb
Host smart-3b8f66e7-a838-40b3-9a39-726cb69611cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035895524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4035895524
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1966419942
Short name T359
Test name
Test status
Simulation time 1355875252 ps
CPU time 1.14 seconds
Started Jul 12 05:24:01 PM PDT 24
Finished Jul 12 05:24:03 PM PDT 24
Peak memory 213596 kb
Host smart-3ccba4fb-851f-450a-b208-753fdb3481a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966419942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1966419942
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.2651265674
Short name T1222
Test name
Test status
Simulation time 1361074145 ps
CPU time 2.07 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:07 PM PDT 24
Peak memory 205448 kb
Host smart-c9d4ef4a-e5f6-48fe-be1d-b49283aa4c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651265674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.2651265674
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.2122645099
Short name T356
Test name
Test status
Simulation time 501244295 ps
CPU time 1.47 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205328 kb
Host smart-864e0499-46ef-4ac8-8caa-89595c97d6c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122645099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.2122645099
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3818501578
Short name T1279
Test name
Test status
Simulation time 4728875094 ps
CPU time 6.84 seconds
Started Jul 12 05:23:59 PM PDT 24
Finished Jul 12 05:24:07 PM PDT 24
Peak memory 219984 kb
Host smart-8b1ab5f1-9498-42f3-a292-d29e96c27917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818501578 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3818501578
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2387035523
Short name T556
Test name
Test status
Simulation time 3224796347 ps
CPU time 5.03 seconds
Started Jul 12 05:24:00 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 205508 kb
Host smart-c059926a-def3-4abb-992b-40030e04759d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387035523 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2387035523
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.2734271627
Short name T1278
Test name
Test status
Simulation time 1217624258 ps
CPU time 2.93 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:24:21 PM PDT 24
Peak memory 213612 kb
Host smart-007a0363-bc6e-44b9-ab4d-decc7e18ba1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734271627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.2734271627
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.3306704894
Short name T1294
Test name
Test status
Simulation time 2098027096 ps
CPU time 2.63 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 205432 kb
Host smart-b67bacc1-7c4b-402f-90d7-e243d4c99d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306704894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.3306704894
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.1134884429
Short name T324
Test name
Test status
Simulation time 1233203105 ps
CPU time 2.05 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 205544 kb
Host smart-07d4a876-4dd1-43ad-a35a-f48cf9318294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134884429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.1134884429
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3054424156
Short name T1539
Test name
Test status
Simulation time 618429774 ps
CPU time 10.8 seconds
Started Jul 12 05:23:55 PM PDT 24
Finished Jul 12 05:24:06 PM PDT 24
Peak memory 213600 kb
Host smart-e8cfe18f-8ef7-406a-8334-070102e11c33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054424156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3054424156
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.728671915
Short name T1558
Test name
Test status
Simulation time 6915374285 ps
CPU time 56.46 seconds
Started Jul 12 05:23:56 PM PDT 24
Finished Jul 12 05:24:53 PM PDT 24
Peak memory 217056 kb
Host smart-4346444e-128a-444a-bdcf-73cda551a895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728671915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.728671915
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3283588997
Short name T935
Test name
Test status
Simulation time 38999911837 ps
CPU time 325.03 seconds
Started Jul 12 05:24:01 PM PDT 24
Finished Jul 12 05:29:27 PM PDT 24
Peak memory 3068088 kb
Host smart-28f9f1d9-bb73-49c5-b60c-23cb4520452f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283588997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3283588997
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1605104560
Short name T591
Test name
Test status
Simulation time 1950009310 ps
CPU time 40.67 seconds
Started Jul 12 05:23:59 PM PDT 24
Finished Jul 12 05:24:41 PM PDT 24
Peak memory 397500 kb
Host smart-4e2badeb-95cb-4f99-809b-9d3aacb699c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605104560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1605104560
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1144362171
Short name T1249
Test name
Test status
Simulation time 2252775040 ps
CPU time 7.17 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:12 PM PDT 24
Peak memory 221892 kb
Host smart-6f9e9d26-5cc8-4a0c-a9ed-a987bcf24688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144362171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1144362171
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.3182981024
Short name T890
Test name
Test status
Simulation time 177114876 ps
CPU time 3.59 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 205412 kb
Host smart-ae609d72-fafc-45a2-bab1-755724b9d9fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182981024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3182981024
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.966034353
Short name T1147
Test name
Test status
Simulation time 20976287 ps
CPU time 0.63 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 204448 kb
Host smart-e3c8285e-b763-4ffb-ad04-2689fdd013e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966034353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.966034353
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3169171654
Short name T794
Test name
Test status
Simulation time 148089575 ps
CPU time 1.7 seconds
Started Jul 12 05:24:06 PM PDT 24
Finished Jul 12 05:24:08 PM PDT 24
Peak memory 213456 kb
Host smart-5028cfa5-4741-47be-b1b9-08f7cb3990bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169171654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3169171654
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.733799584
Short name T1156
Test name
Test status
Simulation time 1132232467 ps
CPU time 13.77 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:19 PM PDT 24
Peak memory 260360 kb
Host smart-db8bf56d-6a10-4a52-a8f3-358d16983022
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733799584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.733799584
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3845605309
Short name T1505
Test name
Test status
Simulation time 20423258175 ps
CPU time 73.93 seconds
Started Jul 12 05:24:02 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 715404 kb
Host smart-b35a5cf3-4fec-4864-b958-702c8872bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845605309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3845605309
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.429420731
Short name T560
Test name
Test status
Simulation time 8419038319 ps
CPU time 51.45 seconds
Started Jul 12 05:24:09 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 574436 kb
Host smart-cb65ef76-3fbb-4baf-ba8d-aef7e8374e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429420731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.429420731
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1847536154
Short name T1568
Test name
Test status
Simulation time 402406860 ps
CPU time 1.03 seconds
Started Jul 12 05:24:01 PM PDT 24
Finished Jul 12 05:24:03 PM PDT 24
Peak memory 205128 kb
Host smart-b8c1df04-024f-46fa-83f4-845b78203efa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847536154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1847536154
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1731101350
Short name T246
Test name
Test status
Simulation time 540390957 ps
CPU time 4.43 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:10 PM PDT 24
Peak memory 230504 kb
Host smart-e1c439cf-d7d9-4ce1-8baa-6194388fa6fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731101350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1731101350
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3436825998
Short name T1026
Test name
Test status
Simulation time 5556450456 ps
CPU time 142.28 seconds
Started Jul 12 05:24:05 PM PDT 24
Finished Jul 12 05:26:29 PM PDT 24
Peak memory 1535292 kb
Host smart-9323d48e-87a7-4f0d-aef1-c6dbbcf4e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436825998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3436825998
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2230762871
Short name T1301
Test name
Test status
Simulation time 602325455 ps
CPU time 3.76 seconds
Started Jul 12 05:24:07 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205288 kb
Host smart-96e1c1d4-84cc-4a0e-9200-46231db79f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230762871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2230762871
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.2997479685
Short name T149
Test name
Test status
Simulation time 66011612 ps
CPU time 0.66 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:05 PM PDT 24
Peak memory 205064 kb
Host smart-4eb7318c-d371-4591-8081-a861b6ecc0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997479685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2997479685
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2057149454
Short name T610
Test name
Test status
Simulation time 718880181 ps
CPU time 3.63 seconds
Started Jul 12 05:24:06 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 213880 kb
Host smart-aabb37c3-24f4-4889-9f07-8be4ba903e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057149454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2057149454
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.1704357171
Short name T1291
Test name
Test status
Simulation time 540720466 ps
CPU time 7.1 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205168 kb
Host smart-e14dc4bd-fefb-4bf2-89a3-5859099dc1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704357171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.1704357171
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3237825080
Short name T781
Test name
Test status
Simulation time 8192461815 ps
CPU time 30.82 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:35 PM PDT 24
Peak memory 341192 kb
Host smart-0752a548-8e03-4c1f-a028-b7f57a11a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237825080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3237825080
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3648401509
Short name T285
Test name
Test status
Simulation time 23889757058 ps
CPU time 454.41 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 989084 kb
Host smart-2f23b597-d9fe-461b-88d7-265bf6cbf562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648401509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3648401509
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1727757709
Short name T1056
Test name
Test status
Simulation time 487444044 ps
CPU time 7.43 seconds
Started Jul 12 05:24:05 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 221676 kb
Host smart-f35f8393-7ed5-4c4f-a085-a8b4fb5fd0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727757709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1727757709
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1789399138
Short name T486
Test name
Test status
Simulation time 1548740002 ps
CPU time 4.57 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 213700 kb
Host smart-ca3887c2-0b93-4944-817f-b1f1e595877e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789399138 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1789399138
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1169164626
Short name T153
Test name
Test status
Simulation time 222193339 ps
CPU time 1.08 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:05 PM PDT 24
Peak memory 205260 kb
Host smart-16d8dcd5-8ff5-4f8d-b19a-a7032e85d355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169164626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1169164626
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.772637160
Short name T1463
Test name
Test status
Simulation time 2110323654 ps
CPU time 2.83 seconds
Started Jul 12 05:24:09 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 205416 kb
Host smart-b03b3720-99a7-46a5-8875-675b6dc0f6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772637160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.772637160
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.3145277539
Short name T450
Test name
Test status
Simulation time 141113711 ps
CPU time 1.24 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205332 kb
Host smart-b67a948d-2230-4d93-81ab-22295f689f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145277539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.3145277539
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2490903252
Short name T367
Test name
Test status
Simulation time 7822764494 ps
CPU time 6.92 seconds
Started Jul 12 05:24:03 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 230608 kb
Host smart-55cbfe7a-bb88-4e51-b159-33b700def8cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490903252 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2490903252
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1031288085
Short name T7
Test name
Test status
Simulation time 16939249110 ps
CPU time 37.08 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:53 PM PDT 24
Peak memory 655364 kb
Host smart-0884a64c-62da-449c-94a7-fe691c3130e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031288085 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1031288085
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.1362237180
Short name T665
Test name
Test status
Simulation time 921716161 ps
CPU time 2.71 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 213656 kb
Host smart-3024233d-c5fb-4e80-b0ce-5ff13bd95322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362237180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.1362237180
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3138194987
Short name T503
Test name
Test status
Simulation time 1275640679 ps
CPU time 2.59 seconds
Started Jul 12 05:24:07 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205400 kb
Host smart-8dc9dae4-56ba-4854-9efd-8d013fc1c878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138194987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3138194987
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.820839676
Short name T826
Test name
Test status
Simulation time 385523584 ps
CPU time 2.12 seconds
Started Jul 12 05:24:07 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205188 kb
Host smart-ef1a48a2-ec2f-4279-8c77-c5fba759ffbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820839676 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_smbus_maxlen.820839676
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1474114384
Short name T1555
Test name
Test status
Simulation time 3294554988 ps
CPU time 10.86 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 213672 kb
Host smart-da505598-412b-4bd1-848d-a47d4c08db5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474114384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1474114384
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2721007245
Short name T1359
Test name
Test status
Simulation time 966325665 ps
CPU time 16.88 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 221764 kb
Host smart-a5d4c8c0-71b9-4b8f-b681-e64a4d2673ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721007245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2721007245
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3152416325
Short name T1107
Test name
Test status
Simulation time 39161779217 ps
CPU time 118.01 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 1654732 kb
Host smart-b4590c4a-8eae-4478-9b95-7d6dc84d7c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152416325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3152416325
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2172959898
Short name T1379
Test name
Test status
Simulation time 2018446900 ps
CPU time 4.83 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:10 PM PDT 24
Peak memory 247556 kb
Host smart-cfb125d6-adaa-49d5-9ac2-d126428b339a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172959898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2172959898
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.323249140
Short name T1027
Test name
Test status
Simulation time 1066613315 ps
CPU time 6.26 seconds
Started Jul 12 05:24:04 PM PDT 24
Finished Jul 12 05:24:12 PM PDT 24
Peak memory 213608 kb
Host smart-5de46804-8703-423a-8cb1-6a9f0a0de0ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323249140 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.323249140
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2741390128
Short name T660
Test name
Test status
Simulation time 111581906 ps
CPU time 2.5 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:12 PM PDT 24
Peak memory 205440 kb
Host smart-fc9ec99a-fe9f-4496-9095-e2002965ea35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741390128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2741390128
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.162943394
Short name T420
Test name
Test status
Simulation time 51169228 ps
CPU time 0.64 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 204640 kb
Host smart-3fefc5d4-3f49-4a7b-a20a-e1b1a9de6f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162943394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.162943394
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.651835392
Short name T674
Test name
Test status
Simulation time 743850430 ps
CPU time 9.88 seconds
Started Jul 12 05:24:11 PM PDT 24
Finished Jul 12 05:24:22 PM PDT 24
Peak memory 213532 kb
Host smart-deae0609-a956-4269-86f8-91b9cd6f7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651835392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.651835392
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.484510557
Short name T1244
Test name
Test status
Simulation time 928057067 ps
CPU time 8.74 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:21 PM PDT 24
Peak memory 290124 kb
Host smart-78be64fb-6d28-43e0-971e-f73898630478
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484510557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.484510557
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.133307229
Short name T1091
Test name
Test status
Simulation time 16064991958 ps
CPU time 112.86 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 606488 kb
Host smart-d111b83f-7d8c-4320-9696-4b8a86ca0d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133307229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.133307229
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1016675982
Short name T679
Test name
Test status
Simulation time 2412133987 ps
CPU time 83.73 seconds
Started Jul 12 05:24:13 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 784160 kb
Host smart-aae7ce6c-29e6-4ea7-abd4-23df01c2f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016675982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1016675982
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2274496018
Short name T880
Test name
Test status
Simulation time 143535728 ps
CPU time 1.19 seconds
Started Jul 12 05:24:11 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 205252 kb
Host smart-64eefd03-c64b-4412-9ed9-de05bcf4ac3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274496018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2274496018
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3112413399
Short name T477
Test name
Test status
Simulation time 203866976 ps
CPU time 9.49 seconds
Started Jul 12 05:24:11 PM PDT 24
Finished Jul 12 05:24:22 PM PDT 24
Peak memory 205240 kb
Host smart-c5e30393-adf2-4754-9bea-6fd1d49e4962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112413399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3112413399
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.398601830
Short name T1142
Test name
Test status
Simulation time 23970200727 ps
CPU time 75.95 seconds
Started Jul 12 05:24:07 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 1033512 kb
Host smart-58dcd741-6626-4e2c-a804-094ca0123331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398601830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.398601830
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3237077383
Short name T1119
Test name
Test status
Simulation time 6748805591 ps
CPU time 23.34 seconds
Started Jul 12 05:24:16 PM PDT 24
Finished Jul 12 05:24:41 PM PDT 24
Peak memory 205388 kb
Host smart-e3bd27e7-9fdf-414d-8a4b-e97bf83502b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237077383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3237077383
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.2804620581
Short name T1306
Test name
Test status
Simulation time 80853039 ps
CPU time 0.68 seconds
Started Jul 12 05:24:10 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 205000 kb
Host smart-976e7727-b252-4890-a5a9-dabad00e8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804620581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2804620581
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.2659308204
Short name T1358
Test name
Test status
Simulation time 99414314 ps
CPU time 1.03 seconds
Started Jul 12 05:24:09 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 205068 kb
Host smart-83743f32-9347-4747-88fb-3b20c510aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659308204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2659308204
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2085611013
Short name T1187
Test name
Test status
Simulation time 5888443413 ps
CPU time 24.53 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:34 PM PDT 24
Peak memory 295500 kb
Host smart-52716a28-6aa4-4c4f-ab3a-0fd8a827a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085611013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2085611013
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.782591048
Short name T155
Test name
Test status
Simulation time 12662711664 ps
CPU time 14.36 seconds
Started Jul 12 05:24:09 PM PDT 24
Finished Jul 12 05:24:25 PM PDT 24
Peak memory 221624 kb
Host smart-6bc182bb-0772-42cd-b883-24474a868a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782591048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.782591048
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.6683866
Short name T1487
Test name
Test status
Simulation time 1339699676 ps
CPU time 6.42 seconds
Started Jul 12 05:24:19 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 213652 kb
Host smart-ebc411d6-bbc6-4339-bbb9-310a62b0019c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6683866 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_bad_addr.6683866
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.924873862
Short name T617
Test name
Test status
Simulation time 170351920 ps
CPU time 1.2 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:18 PM PDT 24
Peak memory 205208 kb
Host smart-acfc5b17-fc8e-444e-892a-06fb0798b25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924873862 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.924873862
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.984574652
Short name T473
Test name
Test status
Simulation time 490335459 ps
CPU time 1.19 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 205444 kb
Host smart-0715abb5-af04-495b-9539-acbb39873b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984574652 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.984574652
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.207729635
Short name T526
Test name
Test status
Simulation time 829875510 ps
CPU time 2.18 seconds
Started Jul 12 05:24:16 PM PDT 24
Finished Jul 12 05:24:19 PM PDT 24
Peak memory 205476 kb
Host smart-f6fbcad3-330d-4cfd-b624-2b81cc276d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207729635 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.207729635
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.177445483
Short name T979
Test name
Test status
Simulation time 348157794 ps
CPU time 0.92 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:24:19 PM PDT 24
Peak memory 205320 kb
Host smart-a909be40-8a29-47d5-9689-a5646b994162
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177445483 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.177445483
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2550080174
Short name T389
Test name
Test status
Simulation time 1554666684 ps
CPU time 4.36 seconds
Started Jul 12 05:24:11 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 213624 kb
Host smart-6566bdfa-f55a-489e-90f8-f188d0030b66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550080174 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2550080174
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.913657902
Short name T1068
Test name
Test status
Simulation time 9742392384 ps
CPU time 20.6 seconds
Started Jul 12 05:24:19 PM PDT 24
Finished Jul 12 05:24:40 PM PDT 24
Peak memory 679820 kb
Host smart-633fec3c-4906-43c7-8633-b6d8936b79f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913657902 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.913657902
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.249589865
Short name T887
Test name
Test status
Simulation time 488105976 ps
CPU time 2.81 seconds
Started Jul 12 05:24:13 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 213612 kb
Host smart-0a4558e7-40cf-4308-8226-353e0bb0c5b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249589865 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_nack_acqfull.249589865
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.3342500997
Short name T997
Test name
Test status
Simulation time 915729447 ps
CPU time 2.45 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:19 PM PDT 24
Peak memory 205256 kb
Host smart-c19a60f2-714c-4014-a75a-34808d9abd16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342500997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.3342500997
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.3687951755
Short name T1528
Test name
Test status
Simulation time 2023718239 ps
CPU time 2.36 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:24:21 PM PDT 24
Peak memory 205292 kb
Host smart-a2161316-2c7e-4fc8-b0d7-280ee8cbe01b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687951755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.3687951755
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.228227799
Short name T1551
Test name
Test status
Simulation time 11523703143 ps
CPU time 26.71 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:24:36 PM PDT 24
Peak memory 213684 kb
Host smart-6b8f89df-3789-4dd0-8965-bf03f1485ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228227799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.228227799
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1771064699
Short name T1474
Test name
Test status
Simulation time 7720445049 ps
CPU time 50.4 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:25:05 PM PDT 24
Peak memory 216092 kb
Host smart-7b5594b0-da8a-458f-99bb-f3c4a9af51d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771064699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1771064699
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.553815422
Short name T352
Test name
Test status
Simulation time 48513958698 ps
CPU time 191.96 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:27:28 PM PDT 24
Peak memory 2181804 kb
Host smart-0a0629d4-0518-4523-b0b3-e96354073941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553815422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.553815422
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2616808870
Short name T1353
Test name
Test status
Simulation time 4984559863 ps
CPU time 55.71 seconds
Started Jul 12 05:24:08 PM PDT 24
Finished Jul 12 05:25:05 PM PDT 24
Peak memory 917744 kb
Host smart-f519cdb2-e91f-419c-897c-60ae372ed281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616808870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2616808870
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3811629970
Short name T1515
Test name
Test status
Simulation time 8232122758 ps
CPU time 6.64 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 219620 kb
Host smart-8a5f6bf2-a84c-4caf-9dcc-8f0d85bd1a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811629970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3811629970
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.2535121071
Short name T364
Test name
Test status
Simulation time 178775747 ps
CPU time 3.31 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:20 PM PDT 24
Peak memory 205404 kb
Host smart-30b852b8-708b-4f9f-bef3-c7a89f9b4ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535121071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2535121071
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2131769551
Short name T1384
Test name
Test status
Simulation time 16821456 ps
CPU time 0.63 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 204660 kb
Host smart-4e01c8e2-10f0-4795-9ddd-5d7147f08762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131769551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2131769551
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3563046457
Short name T541
Test name
Test status
Simulation time 212306044 ps
CPU time 1.97 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:24:16 PM PDT 24
Peak memory 213536 kb
Host smart-fa570e77-702b-411c-817f-bac7e8fa3391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563046457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3563046457
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3498226220
Short name T1319
Test name
Test status
Simulation time 4149810894 ps
CPU time 5.79 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 267976 kb
Host smart-827cb7ab-02a6-4d10-8dc1-1aced613c1e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498226220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3498226220
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2446294943
Short name T1318
Test name
Test status
Simulation time 2054985551 ps
CPU time 138.47 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:26:36 PM PDT 24
Peak memory 640512 kb
Host smart-20aa3046-c6be-467f-9957-8b99f05779ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446294943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2446294943
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3908866953
Short name T1191
Test name
Test status
Simulation time 10421456128 ps
CPU time 92.6 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:25:51 PM PDT 24
Peak memory 882764 kb
Host smart-50ad7d41-e993-47c2-9b05-5a113672d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908866953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3908866953
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1824691257
Short name T1330
Test name
Test status
Simulation time 217067806 ps
CPU time 1.06 seconds
Started Jul 12 05:24:15 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 205060 kb
Host smart-b8451594-ee10-4489-974b-76e99fd76a2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824691257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1824691257
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1653607623
Short name T1096
Test name
Test status
Simulation time 271291918 ps
CPU time 2.92 seconds
Started Jul 12 05:24:17 PM PDT 24
Finished Jul 12 05:24:21 PM PDT 24
Peak memory 205316 kb
Host smart-427b932d-86b0-48b6-8013-4b8d8cf8ff21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653607623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1653607623
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3726338098
Short name T124
Test name
Test status
Simulation time 12917409965 ps
CPU time 81.78 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 1077564 kb
Host smart-9224d5c4-9a8c-48d9-a78f-d896be6531eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726338098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3726338098
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.952589488
Short name T1057
Test name
Test status
Simulation time 771913211 ps
CPU time 12.09 seconds
Started Jul 12 05:24:24 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 205284 kb
Host smart-b868687b-3ba6-4022-870f-314d3826972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952589488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.952589488
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_override.2795970710
Short name T150
Test name
Test status
Simulation time 52677086 ps
CPU time 0.71 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 205012 kb
Host smart-95657556-8cf7-4470-8804-38acd0c5dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795970710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2795970710
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.445236219
Short name T1223
Test name
Test status
Simulation time 12805121781 ps
CPU time 778.48 seconds
Started Jul 12 05:24:19 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 1569464 kb
Host smart-fb279117-b256-46ce-be0f-6f75e3590b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445236219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.445236219
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.4019593246
Short name T762
Test name
Test status
Simulation time 176530908 ps
CPU time 5.52 seconds
Started Jul 12 05:24:24 PM PDT 24
Finished Jul 12 05:24:31 PM PDT 24
Peak memory 222112 kb
Host smart-5db1657a-dc34-41b5-89d7-4ba79a1a2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019593246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.4019593246
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2463566925
Short name T38
Test name
Test status
Simulation time 1973411441 ps
CPU time 48.33 seconds
Started Jul 12 05:24:24 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 457696 kb
Host smart-f4453a61-468d-4b90-998c-e9fbb85f6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463566925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2463566925
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.4023472907
Short name T739
Test name
Test status
Simulation time 823538372 ps
CPU time 39.66 seconds
Started Jul 12 05:24:14 PM PDT 24
Finished Jul 12 05:24:55 PM PDT 24
Peak memory 213380 kb
Host smart-52a69f34-b1f2-427b-a2ee-0fe8068eb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023472907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4023472907
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.131400308
Short name T1098
Test name
Test status
Simulation time 1214205651 ps
CPU time 6.13 seconds
Started Jul 12 05:24:21 PM PDT 24
Finished Jul 12 05:24:28 PM PDT 24
Peak memory 217140 kb
Host smart-061789e2-61b9-4c68-bd61-c5974aa69746
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131400308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.131400308
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2619118098
Short name T643
Test name
Test status
Simulation time 411803708 ps
CPU time 1.38 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 205292 kb
Host smart-9d056e69-1f74-4b9b-9357-3a814113b673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619118098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2619118098
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1935644772
Short name T1511
Test name
Test status
Simulation time 367208935 ps
CPU time 1.56 seconds
Started Jul 12 05:24:21 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 205460 kb
Host smart-c0f01dee-a4a5-464e-a931-1c3a771a4b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935644772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1935644772
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.355616735
Short name T783
Test name
Test status
Simulation time 396905310 ps
CPU time 2.22 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:27 PM PDT 24
Peak memory 205288 kb
Host smart-0c4eb6f7-7198-4483-a3fc-850bc35e2304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355616735 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.355616735
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3422190415
Short name T1050
Test name
Test status
Simulation time 672229861 ps
CPU time 4.87 seconds
Started Jul 12 05:24:24 PM PDT 24
Finished Jul 12 05:24:30 PM PDT 24
Peak memory 210640 kb
Host smart-1366da27-b0ab-4bf5-9a94-e19142b1ac9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422190415 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3422190415
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1395165965
Short name T816
Test name
Test status
Simulation time 995724251 ps
CPU time 1.63 seconds
Started Jul 12 05:24:20 PM PDT 24
Finished Jul 12 05:24:22 PM PDT 24
Peak memory 205304 kb
Host smart-117bc550-6935-4d0d-b485-c0f70896b3ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395165965 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1395165965
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.2555795404
Short name T1264
Test name
Test status
Simulation time 1689377512 ps
CPU time 2.61 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 205416 kb
Host smart-c3130b07-d664-426e-b6b4-dac2d63560e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555795404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.2555795404
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.3878947553
Short name T397
Test name
Test status
Simulation time 413544583 ps
CPU time 2.09 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:24:25 PM PDT 24
Peak memory 205292 kb
Host smart-7c6acec6-7570-4045-807e-51231348ffde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878947553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.3878947553
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2679867891
Short name T613
Test name
Test status
Simulation time 1625299908 ps
CPU time 74.25 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:25:40 PM PDT 24
Peak memory 216656 kb
Host smart-11ed307a-1579-4cab-9e41-768c5ee746e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679867891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2679867891
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2917145166
Short name T484
Test name
Test status
Simulation time 21438721335 ps
CPU time 23.53 seconds
Started Jul 12 05:24:20 PM PDT 24
Finished Jul 12 05:24:44 PM PDT 24
Peak memory 248480 kb
Host smart-7854955f-ffc2-4504-8b06-6c4e7bdca41a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917145166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2917145166
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3179258297
Short name T814
Test name
Test status
Simulation time 3562703682 ps
CPU time 42.36 seconds
Started Jul 12 05:24:25 PM PDT 24
Finished Jul 12 05:25:09 PM PDT 24
Peak memory 659796 kb
Host smart-306611d8-666a-46de-b735-7f1ba0edba95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179258297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3179258297
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3992825496
Short name T860
Test name
Test status
Simulation time 4468410371 ps
CPU time 6.06 seconds
Started Jul 12 05:24:31 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 213696 kb
Host smart-3dd62070-9860-4195-aa5f-b2e40559288b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992825496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3992825496
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.1305931827
Short name T55
Test name
Test status
Simulation time 74885785 ps
CPU time 1.71 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:24:24 PM PDT 24
Peak memory 205388 kb
Host smart-3ccb7156-4fa4-4c96-8c57-f5ad5fd786e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305931827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.1305931827
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3547532472
Short name T1303
Test name
Test status
Simulation time 19400944 ps
CPU time 0.67 seconds
Started Jul 12 05:24:35 PM PDT 24
Finished Jul 12 05:24:37 PM PDT 24
Peak memory 204732 kb
Host smart-6211eff3-79a4-4d44-957d-2301adc42a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547532472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3547532472
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3765057965
Short name T1207
Test name
Test status
Simulation time 282395862 ps
CPU time 3.86 seconds
Started Jul 12 05:24:26 PM PDT 24
Finished Jul 12 05:24:31 PM PDT 24
Peak memory 218400 kb
Host smart-8ff6fa56-d87c-426b-862c-1843055165df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765057965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3765057965
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1866998286
Short name T1164
Test name
Test status
Simulation time 1447368812 ps
CPU time 19.63 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 287272 kb
Host smart-d1e9a8fb-9190-40e6-9c06-9f2de96139bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866998286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1866998286
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.842863078
Short name T27
Test name
Test status
Simulation time 8680106631 ps
CPU time 165.93 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:27:09 PM PDT 24
Peak memory 713468 kb
Host smart-3aafde4c-4b86-4fe1-b0c4-f6406f2f079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842863078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.842863078
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3580780684
Short name T1522
Test name
Test status
Simulation time 8662743118 ps
CPU time 175.33 seconds
Started Jul 12 05:24:22 PM PDT 24
Finished Jul 12 05:27:18 PM PDT 24
Peak memory 758904 kb
Host smart-afb9122c-2a9b-4b8f-9826-eb0f19eaaccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580780684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3580780684
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3660086345
Short name T1114
Test name
Test status
Simulation time 81560578 ps
CPU time 1 seconds
Started Jul 12 05:24:30 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 205092 kb
Host smart-f23a6f63-61da-47c0-bfd7-dff938a67769
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660086345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3660086345
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3456060599
Short name T980
Test name
Test status
Simulation time 762859628 ps
CPU time 3.67 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:28 PM PDT 24
Peak memory 205220 kb
Host smart-721101b5-96a4-4535-9810-194031ad3395
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456060599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3456060599
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2364557561
Short name T184
Test name
Test status
Simulation time 7438987699 ps
CPU time 256.51 seconds
Started Jul 12 05:24:30 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 1101992 kb
Host smart-29a2d735-7c6e-4999-9d3e-3af080ca1778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364557561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2364557561
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3566101829
Short name T1095
Test name
Test status
Simulation time 2598020586 ps
CPU time 12.37 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:42 PM PDT 24
Peak memory 205252 kb
Host smart-966e7f04-5ffc-47a5-80e3-486fa82ec426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566101829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3566101829
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.3547307972
Short name T494
Test name
Test status
Simulation time 19530485 ps
CPU time 0.69 seconds
Started Jul 12 05:24:23 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 205060 kb
Host smart-6b480bed-77ec-4abe-bf3d-41383955dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547307972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3547307972
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.4028039669
Short name T1327
Test name
Test status
Simulation time 8296329129 ps
CPU time 113.86 seconds
Started Jul 12 05:24:30 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 603880 kb
Host smart-aeed717d-949d-4367-8641-7c2ba6ea1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028039669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.4028039669
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.3832033299
Short name T125
Test name
Test status
Simulation time 3141836693 ps
CPU time 15.94 seconds
Started Jul 12 05:24:20 PM PDT 24
Finished Jul 12 05:24:37 PM PDT 24
Peak memory 357924 kb
Host smart-3d4cec3c-3d75-4c7d-a0da-717ec8b1fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832033299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.3832033299
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4082105466
Short name T1127
Test name
Test status
Simulation time 1770660440 ps
CPU time 92.6 seconds
Started Jul 12 05:24:26 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 416696 kb
Host smart-1f3a0bf8-652b-427f-a397-19a371048865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082105466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4082105466
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1191502886
Short name T292
Test name
Test status
Simulation time 75171531460 ps
CPU time 2479.4 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 06:05:54 PM PDT 24
Peak memory 2504072 kb
Host smart-1c1c3a82-9b65-4f2f-8bca-2b5fc45bddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191502886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1191502886
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1803515680
Short name T708
Test name
Test status
Simulation time 647810722 ps
CPU time 30.03 seconds
Started Jul 12 05:24:32 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 213444 kb
Host smart-d3bf5590-19af-40c5-b691-8ac48cbbc01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803515680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1803515680
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.950970864
Short name T1484
Test name
Test status
Simulation time 5551530156 ps
CPU time 5.04 seconds
Started Jul 12 05:24:30 PM PDT 24
Finished Jul 12 05:24:36 PM PDT 24
Peak memory 213784 kb
Host smart-7b744c4a-5812-4f59-847c-de374d504b3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950970864 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.950970864
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2851767816
Short name T1184
Test name
Test status
Simulation time 332692237 ps
CPU time 1.39 seconds
Started Jul 12 05:24:31 PM PDT 24
Finished Jul 12 05:24:34 PM PDT 24
Peak memory 205384 kb
Host smart-000fdc28-6ffc-4fe7-88ce-2177dfde8565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851767816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2851767816
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.109890165
Short name T105
Test name
Test status
Simulation time 697571729 ps
CPU time 1.64 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:31 PM PDT 24
Peak memory 205844 kb
Host smart-43a70ba0-5701-437d-8bbe-5146f2eec464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109890165 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.109890165
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.2915575867
Short name T1078
Test name
Test status
Simulation time 3127849470 ps
CPU time 3.89 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:34 PM PDT 24
Peak memory 205312 kb
Host smart-a77875e8-0683-4bd0-8d43-8a910fac597a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915575867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.2915575867
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.344859495
Short name T71
Test name
Test status
Simulation time 146889756 ps
CPU time 0.77 seconds
Started Jul 12 05:24:30 PM PDT 24
Finished Jul 12 05:24:32 PM PDT 24
Peak memory 205308 kb
Host smart-44044942-72b8-4c5c-b8d9-8ba5014517cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344859495 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.344859495
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2289247558
Short name T304
Test name
Test status
Simulation time 3887454650 ps
CPU time 5.69 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:35 PM PDT 24
Peak memory 221848 kb
Host smart-e722a361-b936-41ee-aa8e-90b790a9fffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289247558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2289247558
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3039637851
Short name T790
Test name
Test status
Simulation time 9577861861 ps
CPU time 129.25 seconds
Started Jul 12 05:24:31 PM PDT 24
Finished Jul 12 05:26:42 PM PDT 24
Peak memory 2418944 kb
Host smart-1a35ce9d-5a72-4365-97aa-2004a9c43a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039637851 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3039637851
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.955533082
Short name T169
Test name
Test status
Simulation time 616626995 ps
CPU time 3.37 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:33 PM PDT 24
Peak memory 213588 kb
Host smart-bf07881e-37dc-4414-90fb-6824d26971f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955533082 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_nack_acqfull.955533082
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.2217677115
Short name T1348
Test name
Test status
Simulation time 706239520 ps
CPU time 2.89 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 205296 kb
Host smart-b671dfdf-7bc1-41d2-ac6e-b92fadf93958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217677115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.2217677115
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.613196639
Short name T1121
Test name
Test status
Simulation time 470452223 ps
CPU time 2.24 seconds
Started Jul 12 05:24:26 PM PDT 24
Finished Jul 12 05:24:30 PM PDT 24
Peak memory 205408 kb
Host smart-badeec32-4988-4b7e-8a4d-e7cce08b5117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613196639 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_smbus_maxlen.613196639
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2651172084
Short name T1062
Test name
Test status
Simulation time 938871266 ps
CPU time 28.45 seconds
Started Jul 12 05:24:28 PM PDT 24
Finished Jul 12 05:24:58 PM PDT 24
Peak memory 213600 kb
Host smart-ab955900-4362-4d52-be6f-98f6bdc3a20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651172084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2651172084
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.91449608
Short name T612
Test name
Test status
Simulation time 1492407502 ps
CPU time 30.66 seconds
Started Jul 12 05:24:29 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 232328 kb
Host smart-5af9aaa4-23f9-4a2a-a0d2-e69978c2ba71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91449608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stress_rd.91449608
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.554117555
Short name T1450
Test name
Test status
Simulation time 52747503064 ps
CPU time 1844.68 seconds
Started Jul 12 05:24:32 PM PDT 24
Finished Jul 12 05:55:18 PM PDT 24
Peak memory 8414456 kb
Host smart-8ef66e85-4b00-4c74-83c4-61e02bf3049c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554117555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.554117555
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1404448129
Short name T1498
Test name
Test status
Simulation time 1091916731 ps
CPU time 6.23 seconds
Started Jul 12 05:24:27 PM PDT 24
Finished Jul 12 05:24:35 PM PDT 24
Peak memory 213540 kb
Host smart-10e8a17f-bec0-432e-b612-a2307b70fb0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404448129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1404448129
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.3992890082
Short name T1426
Test name
Test status
Simulation time 282229985 ps
CPU time 4.51 seconds
Started Jul 12 05:24:31 PM PDT 24
Finished Jul 12 05:24:37 PM PDT 24
Peak memory 214580 kb
Host smart-8ab8906f-3331-4d33-9f9a-8fc0e9f3f82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992890082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3992890082
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2656292347
Short name T1002
Test name
Test status
Simulation time 96062590 ps
CPU time 0.61 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:42 PM PDT 24
Peak memory 204592 kb
Host smart-26846081-9440-4bf4-8985-292953a20f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656292347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2656292347
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2211243757
Short name T659
Test name
Test status
Simulation time 146122761 ps
CPU time 2.09 seconds
Started Jul 12 05:24:35 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 213388 kb
Host smart-ede50ffb-8a0c-4ae2-a0c0-aee43d58def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211243757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2211243757
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1611838232
Short name T898
Test name
Test status
Simulation time 2615115633 ps
CPU time 5.62 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:24:40 PM PDT 24
Peak memory 258272 kb
Host smart-9fbbe909-8d85-4a37-b8c5-406d47ba8d19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611838232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1611838232
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3269001649
Short name T91
Test name
Test status
Simulation time 11322577032 ps
CPU time 182.56 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:27:49 PM PDT 24
Peak memory 757724 kb
Host smart-9893e9c1-67c1-426f-a2c2-ee0e39f961ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269001649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3269001649
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3723575080
Short name T103
Test name
Test status
Simulation time 8794305868 ps
CPU time 53.29 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:25:40 PM PDT 24
Peak memory 624060 kb
Host smart-64e0d367-c0e3-4fba-9627-f2b59f597261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723575080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3723575080
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.397323202
Short name T957
Test name
Test status
Simulation time 68188678 ps
CPU time 0.88 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:47 PM PDT 24
Peak memory 204980 kb
Host smart-88c071e3-83fd-4d9d-99df-095e48e1aedf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397323202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.397323202
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.87710268
Short name T543
Test name
Test status
Simulation time 301039747 ps
CPU time 11.19 seconds
Started Jul 12 05:24:35 PM PDT 24
Finished Jul 12 05:24:48 PM PDT 24
Peak memory 205228 kb
Host smart-5e52c5b6-4c4a-4b45-a3bc-38a8aa1277b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87710268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.87710268
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3117162619
Short name T1074
Test name
Test status
Simulation time 4899631936 ps
CPU time 164.39 seconds
Started Jul 12 05:24:35 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 839428 kb
Host smart-768f70ed-7382-4e2c-ac09-fd8578cbb720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117162619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3117162619
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1876340672
Short name T276
Test name
Test status
Simulation time 1041206222 ps
CPU time 21.52 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 205308 kb
Host smart-d00d655f-6b0d-48f4-b821-00d073a30294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876340672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1876340672
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.411882490
Short name T914
Test name
Test status
Simulation time 15601445 ps
CPU time 0.65 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:47 PM PDT 24
Peak memory 204944 kb
Host smart-1ff94bf1-f54f-4d32-98a8-26fb2dac3978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411882490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.411882490
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1940212937
Short name T1562
Test name
Test status
Simulation time 6710449694 ps
CPU time 38.01 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:25:13 PM PDT 24
Peak memory 263484 kb
Host smart-df1ad4fd-cb25-40ca-a453-963e394db910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940212937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1940212937
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.2889642918
Short name T1422
Test name
Test status
Simulation time 331437158 ps
CPU time 1.13 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:41 PM PDT 24
Peak memory 204980 kb
Host smart-678598e5-6ca0-481f-bf1a-8facca5dbeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889642918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2889642918
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.701159427
Short name T1542
Test name
Test status
Simulation time 2853259197 ps
CPU time 80.01 seconds
Started Jul 12 05:24:32 PM PDT 24
Finished Jul 12 05:25:53 PM PDT 24
Peak memory 326576 kb
Host smart-ea2a2ba1-6a30-487a-ab26-ac098de6b275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701159427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.701159427
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.562730729
Short name T296
Test name
Test status
Simulation time 1873589613 ps
CPU time 7.64 seconds
Started Jul 12 05:24:35 PM PDT 24
Finished Jul 12 05:24:44 PM PDT 24
Peak memory 220964 kb
Host smart-d48366cb-5562-450c-b5b2-8ecdb0a157a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562730729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.562730729
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1969030883
Short name T557
Test name
Test status
Simulation time 1270349020 ps
CPU time 3.59 seconds
Started Jul 12 05:24:34 PM PDT 24
Finished Jul 12 05:24:39 PM PDT 24
Peak memory 215500 kb
Host smart-a8fead5f-6ea5-43c9-817d-dc8b8409f812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969030883 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1969030883
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3521887742
Short name T897
Test name
Test status
Simulation time 203688323 ps
CPU time 1.31 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:47 PM PDT 24
Peak memory 205288 kb
Host smart-bde24ff6-97f6-4293-9259-67c1442cc850
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521887742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3521887742
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3558481941
Short name T1067
Test name
Test status
Simulation time 219625267 ps
CPU time 1.46 seconds
Started Jul 12 05:24:34 PM PDT 24
Finished Jul 12 05:24:37 PM PDT 24
Peak memory 205300 kb
Host smart-5d73300a-fce9-4a16-ad06-fefc70085e38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558481941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3558481941
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.1350618676
Short name T910
Test name
Test status
Simulation time 780262314 ps
CPU time 2.65 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 205296 kb
Host smart-983fa5c2-4e3b-428a-8ba0-9f61267952de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350618676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.1350618676
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2571955664
Short name T733
Test name
Test status
Simulation time 572624995 ps
CPU time 1.32 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:24:41 PM PDT 24
Peak memory 205292 kb
Host smart-93c0994f-f3e7-4be5-9c14-684664f0ae3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571955664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2571955664
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2321537650
Short name T1241
Test name
Test status
Simulation time 2609700723 ps
CPU time 4.6 seconds
Started Jul 12 05:24:32 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 221808 kb
Host smart-c78f9f4c-b965-4cbe-b253-2adc6d536563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321537650 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2321537650
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1929360265
Short name T338
Test name
Test status
Simulation time 7194046324 ps
CPU time 12.29 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:24:46 PM PDT 24
Peak memory 466236 kb
Host smart-2fc195c7-2414-41ce-90be-a49706da7435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929360265 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1929360265
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.2666486886
Short name T885
Test name
Test status
Simulation time 1618481728 ps
CPU time 2.44 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:24:42 PM PDT 24
Peak memory 213628 kb
Host smart-779978e3-852a-47ae-b73e-68c897ecbffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666486886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.2666486886
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.3091729353
Short name T197
Test name
Test status
Simulation time 952510076 ps
CPU time 2.5 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 205388 kb
Host smart-f08739a9-fc5c-45fb-9eaf-52220f887aa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091729353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.3091729353
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.4049374876
Short name T1481
Test name
Test status
Simulation time 537548870 ps
CPU time 2.28 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:43 PM PDT 24
Peak memory 205288 kb
Host smart-5e53972f-e4ad-46e5-8ce7-9a7a7de4b265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049374876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.4049374876
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3690078556
Short name T382
Test name
Test status
Simulation time 5449497077 ps
CPU time 18.92 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:24:54 PM PDT 24
Peak memory 213940 kb
Host smart-7275990a-2411-4b4f-959f-b726b906a8ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690078556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3690078556
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.785377873
Short name T378
Test name
Test status
Simulation time 1616607763 ps
CPU time 29.3 seconds
Started Jul 12 05:24:32 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 226916 kb
Host smart-538e2938-7a37-46d6-9e1e-3e1ed9e61011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785377873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.785377873
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.401247597
Short name T718
Test name
Test status
Simulation time 27385599465 ps
CPU time 6.06 seconds
Started Jul 12 05:24:33 PM PDT 24
Finished Jul 12 05:24:40 PM PDT 24
Peak memory 213668 kb
Host smart-c45772c3-130e-448c-bebb-5fd90d550864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401247597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.401247597
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1999400525
Short name T1510
Test name
Test status
Simulation time 3929175050 ps
CPU time 17.66 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:25:05 PM PDT 24
Peak memory 448924 kb
Host smart-bddb16ba-054f-457e-b165-3896eaa6e314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999400525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1999400525
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1916393162
Short name T1482
Test name
Test status
Simulation time 5343526476 ps
CPU time 6.89 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:53 PM PDT 24
Peak memory 217688 kb
Host smart-15350e3e-8073-4fd6-9068-c09ea348d460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916393162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1916393162
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1126731372
Short name T1253
Test name
Test status
Simulation time 361287733 ps
CPU time 5.05 seconds
Started Jul 12 05:24:38 PM PDT 24
Finished Jul 12 05:24:44 PM PDT 24
Peak memory 205328 kb
Host smart-d9a83c1d-087b-4b3a-b7ed-550e04eef09c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126731372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1126731372
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2854704374
Short name T474
Test name
Test status
Simulation time 18059961 ps
CPU time 0.66 seconds
Started Jul 12 05:19:22 PM PDT 24
Finished Jul 12 05:19:23 PM PDT 24
Peak memory 204640 kb
Host smart-c947b9b8-c90b-4f4c-b345-1a43a456356a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854704374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2854704374
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3956568369
Short name T698
Test name
Test status
Simulation time 353399607 ps
CPU time 1.47 seconds
Started Jul 12 05:19:07 PM PDT 24
Finished Jul 12 05:19:10 PM PDT 24
Peak memory 213580 kb
Host smart-3940f3b3-a672-4bff-af54-73e69637ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956568369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3956568369
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.572807643
Short name T1126
Test name
Test status
Simulation time 286624042 ps
CPU time 5.03 seconds
Started Jul 12 05:19:07 PM PDT 24
Finished Jul 12 05:19:13 PM PDT 24
Peak memory 262488 kb
Host smart-1aa6a487-9de5-4fd0-b947-67b8e3a39aea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572807643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.572807643
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1722232896
Short name T441
Test name
Test status
Simulation time 1806433563 ps
CPU time 125.8 seconds
Started Jul 12 05:19:07 PM PDT 24
Finished Jul 12 05:21:14 PM PDT 24
Peak memory 653416 kb
Host smart-fea74fa7-7adc-4777-8813-86dc2c0ca657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722232896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1722232896
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.4275275842
Short name T1314
Test name
Test status
Simulation time 2481053998 ps
CPU time 178.28 seconds
Started Jul 12 05:19:04 PM PDT 24
Finished Jul 12 05:22:03 PM PDT 24
Peak memory 757980 kb
Host smart-1460001d-12c3-4a39-a95a-b21898b0f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275275842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.4275275842
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2796953577
Short name T916
Test name
Test status
Simulation time 198168402 ps
CPU time 1.03 seconds
Started Jul 12 05:19:19 PM PDT 24
Finished Jul 12 05:19:21 PM PDT 24
Peak memory 205120 kb
Host smart-4d048a51-e3ac-4868-8035-9bc1e3ab755e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796953577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2796953577
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1740508808
Short name T932
Test name
Test status
Simulation time 330850238 ps
CPU time 5.66 seconds
Started Jul 12 05:19:07 PM PDT 24
Finished Jul 12 05:19:14 PM PDT 24
Peak memory 247276 kb
Host smart-862c252c-86f4-4c20-84a3-b95ef6334c30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740508808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1740508808
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.342661517
Short name T80
Test name
Test status
Simulation time 5259163051 ps
CPU time 414.62 seconds
Started Jul 12 05:19:08 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 1453824 kb
Host smart-512d9558-f0e7-44a7-a092-828659c220f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342661517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.342661517
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3496679919
Short name T917
Test name
Test status
Simulation time 287676515 ps
CPU time 3.83 seconds
Started Jul 12 05:19:13 PM PDT 24
Finished Jul 12 05:19:18 PM PDT 24
Peak memory 205300 kb
Host smart-ebba671b-2c7b-459f-aa4d-a2d44a33ac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496679919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3496679919
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.1633422332
Short name T146
Test name
Test status
Simulation time 17551719 ps
CPU time 0.67 seconds
Started Jul 12 05:19:09 PM PDT 24
Finished Jul 12 05:19:10 PM PDT 24
Peak memory 205092 kb
Host smart-099427c4-c682-455e-bf0e-6ef4302f9d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633422332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1633422332
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2722676096
Short name T1215
Test name
Test status
Simulation time 4999182758 ps
CPU time 165.98 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:21:52 PM PDT 24
Peak memory 1347280 kb
Host smart-e5c97989-5a90-4bc6-be32-6baf520e2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722676096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2722676096
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.2133758072
Short name T1211
Test name
Test status
Simulation time 102360054 ps
CPU time 1.35 seconds
Started Jul 12 05:19:09 PM PDT 24
Finished Jul 12 05:19:11 PM PDT 24
Peak memory 226488 kb
Host smart-2a4f263b-47d2-407e-8604-cd7378f3e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133758072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.2133758072
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1544589708
Short name T1052
Test name
Test status
Simulation time 2255396184 ps
CPU time 15.55 seconds
Started Jul 12 05:19:06 PM PDT 24
Finished Jul 12 05:19:23 PM PDT 24
Peak memory 271316 kb
Host smart-a446540d-af41-4b39-8a86-bb92f23c6167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544589708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1544589708
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1013224
Short name T664
Test name
Test status
Simulation time 1050384843 ps
CPU time 14.03 seconds
Started Jul 12 05:19:08 PM PDT 24
Finished Jul 12 05:19:23 PM PDT 24
Peak memory 218836 kb
Host smart-bc0e8d79-e933-4457-a6bf-4c8836238302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1013224
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2780762768
Short name T191
Test name
Test status
Simulation time 256516834 ps
CPU time 0.94 seconds
Started Jul 12 05:19:21 PM PDT 24
Finished Jul 12 05:19:23 PM PDT 24
Peak memory 223572 kb
Host smart-cdf8ab40-9802-4af6-93bd-cea07f4dc581
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780762768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2780762768
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.229456633
Short name T1410
Test name
Test status
Simulation time 2009052216 ps
CPU time 5.9 seconds
Started Jul 12 05:19:14 PM PDT 24
Finished Jul 12 05:19:20 PM PDT 24
Peak memory 214028 kb
Host smart-d7f6b385-40c9-411e-abda-d039eabb2da4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229456633 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.229456633
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3632111320
Short name T1559
Test name
Test status
Simulation time 152848279 ps
CPU time 1.08 seconds
Started Jul 12 05:19:11 PM PDT 24
Finished Jul 12 05:19:14 PM PDT 24
Peak memory 205308 kb
Host smart-7bbccbe1-304a-4c13-ba6e-261c74b1f934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632111320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3632111320
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3156967004
Short name T642
Test name
Test status
Simulation time 271638037 ps
CPU time 1.64 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:19:15 PM PDT 24
Peak memory 205404 kb
Host smart-fffa55e2-7ab9-4d0e-b964-735727e055eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156967004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3156967004
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.782852896
Short name T1115
Test name
Test status
Simulation time 566669369 ps
CPU time 2.92 seconds
Started Jul 12 05:19:16 PM PDT 24
Finished Jul 12 05:19:19 PM PDT 24
Peak memory 205640 kb
Host smart-52d577d0-1801-4b58-bbb5-025adb9f8aa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782852896 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.782852896
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.436183693
Short name T482
Test name
Test status
Simulation time 722817111 ps
CPU time 0.94 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:19:14 PM PDT 24
Peak memory 205240 kb
Host smart-428345a8-6899-410f-8b1f-2b903d9e0942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436183693 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.436183693
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3470494099
Short name T858
Test name
Test status
Simulation time 1045412345 ps
CPU time 6.23 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:19:19 PM PDT 24
Peak memory 221840 kb
Host smart-6ba7bfbc-248c-40c1-8edd-7ab399116cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470494099 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3470494099
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.372040427
Short name T1125
Test name
Test status
Simulation time 20888453432 ps
CPU time 171.57 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:22:05 PM PDT 24
Peak memory 1877612 kb
Host smart-ed01d6d8-0ae2-4a3f-aec6-3eab7fabeba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372040427 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.372040427
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.3553545783
Short name T1483
Test name
Test status
Simulation time 2141612649 ps
CPU time 2.73 seconds
Started Jul 12 05:19:22 PM PDT 24
Finished Jul 12 05:19:26 PM PDT 24
Peak memory 213608 kb
Host smart-2c0f7f77-9dfa-448d-9be4-cd1ece93be57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553545783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.3553545783
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.2917826576
Short name T505
Test name
Test status
Simulation time 603003177 ps
CPU time 3.11 seconds
Started Jul 12 05:19:22 PM PDT 24
Finished Jul 12 05:19:26 PM PDT 24
Peak memory 205912 kb
Host smart-ec5f880f-140e-4321-b49f-336a06cf2d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917826576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.2917826576
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.601279588
Short name T339
Test name
Test status
Simulation time 429900368 ps
CPU time 2.07 seconds
Started Jul 12 05:19:20 PM PDT 24
Finished Jul 12 05:19:22 PM PDT 24
Peak memory 205288 kb
Host smart-ea7243d4-1fcf-4e3c-97e6-54cf60f29c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601279588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_smbus_maxlen.601279588
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.4201122663
Short name T754
Test name
Test status
Simulation time 2438659797 ps
CPU time 37.18 seconds
Started Jul 12 05:19:16 PM PDT 24
Finished Jul 12 05:19:53 PM PDT 24
Peak memory 213952 kb
Host smart-6c60b367-bee6-46bd-8f79-10c745a2c6f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201122663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.4201122663
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2030662965
Short name T983
Test name
Test status
Simulation time 790636877 ps
CPU time 13.68 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:19:27 PM PDT 24
Peak memory 221676 kb
Host smart-a27f6ba0-8bc7-4cc3-a888-01d3c680d9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030662965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2030662965
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.4270265775
Short name T641
Test name
Test status
Simulation time 46409033081 ps
CPU time 391.76 seconds
Started Jul 12 05:19:11 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 3275520 kb
Host smart-3ac79d6f-182b-414f-8b5d-0ba442c28ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270265775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.4270265775
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3200444881
Short name T300
Test name
Test status
Simulation time 1662343460 ps
CPU time 4.92 seconds
Started Jul 12 05:19:12 PM PDT 24
Finished Jul 12 05:19:18 PM PDT 24
Peak memory 213596 kb
Host smart-9b46fd9d-2f85-4740-8f25-94378b29c61c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200444881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3200444881
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3330972759
Short name T140
Test name
Test status
Simulation time 3115192706 ps
CPU time 8.77 seconds
Started Jul 12 05:19:11 PM PDT 24
Finished Jul 12 05:19:21 PM PDT 24
Peak memory 230032 kb
Host smart-be688c4b-d1b7-4ef5-8e9c-fbd0414035b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330972759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3330972759
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1881626106
Short name T535
Test name
Test status
Simulation time 74073369 ps
CPU time 1.77 seconds
Started Jul 12 05:19:19 PM PDT 24
Finished Jul 12 05:19:22 PM PDT 24
Peak memory 205416 kb
Host smart-840e670c-4a4a-4eeb-9f2e-3e956c1e48cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881626106 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1881626106
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2772197203
Short name T1546
Test name
Test status
Simulation time 15977409 ps
CPU time 0.64 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:24:57 PM PDT 24
Peak memory 204484 kb
Host smart-9132a066-954d-4373-89f9-07b98a0dfec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772197203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2772197203
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3131561332
Short name T1037
Test name
Test status
Simulation time 1096580635 ps
CPU time 5.07 seconds
Started Jul 12 05:24:40 PM PDT 24
Finished Jul 12 05:24:46 PM PDT 24
Peak memory 236148 kb
Host smart-48784c00-5658-4086-9341-06a52bf85086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131561332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3131561332
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3389417466
Short name T487
Test name
Test status
Simulation time 305142052 ps
CPU time 5.55 seconds
Started Jul 12 05:24:38 PM PDT 24
Finished Jul 12 05:24:44 PM PDT 24
Peak memory 266272 kb
Host smart-4305f545-29c8-48d8-92e9-f6d6bfe553eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389417466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3389417466
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3369013327
Short name T1452
Test name
Test status
Simulation time 3251230630 ps
CPU time 60.97 seconds
Started Jul 12 05:24:42 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 612752 kb
Host smart-72850ad6-bfe5-4fa2-b234-e95ea09b5edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369013327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3369013327
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3319858791
Short name T1399
Test name
Test status
Simulation time 8248480005 ps
CPU time 56.28 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:25:36 PM PDT 24
Peak memory 550648 kb
Host smart-46da65c0-cf90-4129-97dd-6322c8f0e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319858791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3319858791
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2020973508
Short name T593
Test name
Test status
Simulation time 116774827 ps
CPU time 1.07 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:24:56 PM PDT 24
Peak memory 204948 kb
Host smart-520de1e3-4ff0-4c35-b8ba-647343b28840
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020973508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2020973508
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3673932022
Short name T446
Test name
Test status
Simulation time 1270704150 ps
CPU time 12.89 seconds
Started Jul 12 05:24:41 PM PDT 24
Finished Jul 12 05:24:55 PM PDT 24
Peak memory 247668 kb
Host smart-f522a9ee-38c9-41d9-9820-feac4f4106ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673932022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3673932022
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3337112844
Short name T694
Test name
Test status
Simulation time 19941441037 ps
CPU time 362.52 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 1478128 kb
Host smart-440516fc-278c-475f-85cc-24b17a8fe8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337112844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3337112844
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.75406474
Short name T1491
Test name
Test status
Simulation time 600829963 ps
CPU time 5.96 seconds
Started Jul 12 05:24:44 PM PDT 24
Finished Jul 12 05:24:51 PM PDT 24
Peak memory 205308 kb
Host smart-2c4ad009-05f1-4745-ae54-2cc199cd16f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75406474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.75406474
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.2875479332
Short name T991
Test name
Test status
Simulation time 29853427 ps
CPU time 0.69 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:24:40 PM PDT 24
Peak memory 204984 kb
Host smart-50f6b47f-6a32-4403-9f09-dfc8c236f034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875479332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2875479332
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1605753822
Short name T1039
Test name
Test status
Simulation time 51405992418 ps
CPU time 182.29 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 362800 kb
Host smart-d4d87e9d-b6af-408c-8670-bf9397c0f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605753822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1605753822
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.2116378035
Short name T595
Test name
Test status
Simulation time 24382453008 ps
CPU time 229.19 seconds
Started Jul 12 05:24:42 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 205228 kb
Host smart-d5ea74e0-69a7-4db6-98a5-17d3c8c06f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116378035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.2116378035
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3169048470
Short name T328
Test name
Test status
Simulation time 7787653021 ps
CPU time 34.87 seconds
Started Jul 12 05:24:41 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 420500 kb
Host smart-2a7f5e96-88ed-4743-a6a9-e39f0c1232a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169048470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3169048470
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2837438596
Short name T1541
Test name
Test status
Simulation time 2231025108 ps
CPU time 24.23 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:19 PM PDT 24
Peak memory 213420 kb
Host smart-d277ae50-7fd2-42c7-83e7-a050529fa707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837438596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2837438596
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1208487714
Short name T380
Test name
Test status
Simulation time 1960333590 ps
CPU time 4.96 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 215992 kb
Host smart-cc7db80c-9134-4886-aee5-239bb187d5be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208487714 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1208487714
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2098773932
Short name T363
Test name
Test status
Simulation time 249039250 ps
CPU time 1.59 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:24:53 PM PDT 24
Peak memory 205436 kb
Host smart-7c4d4f59-439f-40f9-8022-fa9cea91a6d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098773932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2098773932
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4031026529
Short name T809
Test name
Test status
Simulation time 155808015 ps
CPU time 1.09 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:47 PM PDT 24
Peak memory 205428 kb
Host smart-7831be26-8250-4615-b4fd-408febac2f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031026529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4031026529
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.788602152
Short name T334
Test name
Test status
Simulation time 429426919 ps
CPU time 2.51 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:24:53 PM PDT 24
Peak memory 205476 kb
Host smart-379013d6-6311-4486-be48-9547fa215abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788602152 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.788602152
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.675611490
Short name T308
Test name
Test status
Simulation time 621651816 ps
CPU time 1.46 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:24:50 PM PDT 24
Peak memory 205292 kb
Host smart-1fc3f925-5278-4707-a16d-257985efd2ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675611490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.675611490
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2482927298
Short name T668
Test name
Test status
Simulation time 2344526571 ps
CPU time 3.98 seconds
Started Jul 12 05:24:39 PM PDT 24
Finished Jul 12 05:24:44 PM PDT 24
Peak memory 218096 kb
Host smart-cd5af9a9-a6cb-4f00-9edd-92c4897ec088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482927298 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2482927298
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.143139489
Short name T1367
Test name
Test status
Simulation time 4914034168 ps
CPU time 18.23 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 674324 kb
Host smart-70383c6c-b9e8-4334-a996-22e3a38b768a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143139489 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.143139489
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.1123539014
Short name T588
Test name
Test status
Simulation time 1699529083 ps
CPU time 2.74 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:24:51 PM PDT 24
Peak memory 213604 kb
Host smart-50dc774c-5858-4dfd-841a-408bf4042cdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123539014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.1123539014
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.3162508698
Short name T985
Test name
Test status
Simulation time 2170189161 ps
CPU time 2.6 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:24:51 PM PDT 24
Peak memory 205468 kb
Host smart-47baa23f-4c5c-44a3-92e1-c75e348aadfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162508698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.3162508698
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.3971216379
Short name T1144
Test name
Test status
Simulation time 540235569 ps
CPU time 2.49 seconds
Started Jul 12 05:24:45 PM PDT 24
Finished Jul 12 05:24:48 PM PDT 24
Peak memory 205280 kb
Host smart-4bbbdbe8-ee40-425f-9098-2ec37fcaf3c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971216379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.3971216379
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2960643541
Short name T1349
Test name
Test status
Simulation time 1511939600 ps
CPU time 22.98 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:19 PM PDT 24
Peak memory 213464 kb
Host smart-2d09b181-2be0-4b44-9554-25e44d66f4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960643541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2960643541
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2531322687
Short name T1372
Test name
Test status
Simulation time 1353880382 ps
CPU time 61.31 seconds
Started Jul 12 05:24:38 PM PDT 24
Finished Jul 12 05:25:40 PM PDT 24
Peak memory 217212 kb
Host smart-e431122d-8302-406a-aa25-ca4319c84ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531322687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2531322687
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2089595840
Short name T912
Test name
Test status
Simulation time 34401020102 ps
CPU time 46.71 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 946072 kb
Host smart-caaae0c2-e681-4851-9f07-1a8ec447f9b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089595840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2089595840
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2158394432
Short name T384
Test name
Test status
Simulation time 2720300465 ps
CPU time 6.97 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:24:58 PM PDT 24
Peak memory 230064 kb
Host smart-c8799907-5d5c-4d38-93b4-e3541de0a1cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158394432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2158394432
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.4097590869
Short name T424
Test name
Test status
Simulation time 58151801 ps
CPU time 1.36 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:24:50 PM PDT 24
Peak memory 205428 kb
Host smart-be60d258-5e1b-4804-a55a-7b62373f40c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097590869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.4097590869
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3019396927
Short name T1393
Test name
Test status
Simulation time 30118438 ps
CPU time 0.61 seconds
Started Jul 12 05:24:53 PM PDT 24
Finished Jul 12 05:24:55 PM PDT 24
Peak memory 204532 kb
Host smart-f853c342-8d25-4a44-8d85-674d6e5e7b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019396927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3019396927
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1802260354
Short name T700
Test name
Test status
Simulation time 294506943 ps
CPU time 1.2 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:24:52 PM PDT 24
Peak memory 213468 kb
Host smart-533efce9-8a15-4a7c-972a-2586cf26b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802260354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1802260354
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3872897851
Short name T619
Test name
Test status
Simulation time 1379584536 ps
CPU time 17.14 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 243668 kb
Host smart-39c67806-15ab-48cc-9a65-c38185b17852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872897851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3872897851
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.4240390202
Short name T84
Test name
Test status
Simulation time 2530045513 ps
CPU time 155.61 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 664348 kb
Host smart-27776853-a932-4d7c-bfe0-0ef3f68608da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240390202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.4240390202
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2478145880
Short name T1547
Test name
Test status
Simulation time 5945116362 ps
CPU time 49.21 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:25:39 PM PDT 24
Peak memory 560236 kb
Host smart-4cc0b190-44e1-45fc-b123-0655e024dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478145880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2478145880
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.942257944
Short name T1143
Test name
Test status
Simulation time 484170975 ps
CPU time 1.08 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:24:50 PM PDT 24
Peak memory 205072 kb
Host smart-7de8292d-94ba-42d5-addd-beb4abe00c11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942257944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.942257944
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1222332992
Short name T767
Test name
Test status
Simulation time 492331690 ps
CPU time 6.71 seconds
Started Jul 12 05:24:51 PM PDT 24
Finished Jul 12 05:24:58 PM PDT 24
Peak memory 205288 kb
Host smart-9eef2a3f-ff81-4677-b80e-219919d5612c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222332992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1222332992
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2073774853
Short name T121
Test name
Test status
Simulation time 2807210431 ps
CPU time 58.79 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:25:46 PM PDT 24
Peak memory 850588 kb
Host smart-caaa7366-5271-4390-9bda-545b9be65231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073774853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2073774853
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3660052114
Short name T266
Test name
Test status
Simulation time 905338984 ps
CPU time 5.88 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 205292 kb
Host smart-61321b18-1354-4c06-9efb-cd025df8d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660052114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3660052114
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.4146212649
Short name T1154
Test name
Test status
Simulation time 23823800 ps
CPU time 0.65 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:24:50 PM PDT 24
Peak memory 205080 kb
Host smart-216d6c7e-7550-43f7-b689-78284aeb9045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146212649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.4146212649
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.427525063
Short name T26
Test name
Test status
Simulation time 5765515969 ps
CPU time 27.9 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 386276 kb
Host smart-13fe6d2f-2fba-4e3d-bd7e-0f163c89bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427525063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.427525063
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3732387668
Short name T46
Test name
Test status
Simulation time 240651260 ps
CPU time 4.55 seconds
Started Jul 12 05:24:44 PM PDT 24
Finished Jul 12 05:24:49 PM PDT 24
Peak memory 239668 kb
Host smart-c3e7b646-fabe-407f-a911-b9d44b26e458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732387668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3732387668
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2416746544
Short name T567
Test name
Test status
Simulation time 1528199510 ps
CPU time 24.2 seconds
Started Jul 12 05:24:51 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 317168 kb
Host smart-5f2acad2-b6d3-4027-b0ba-0b3f5aa53a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416746544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2416746544
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3222485388
Short name T1311
Test name
Test status
Simulation time 3418132669 ps
CPU time 28.28 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:25 PM PDT 24
Peak memory 213420 kb
Host smart-d8026f24-52a9-4750-b4bd-261da6cb6dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222485388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3222485388
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.4245599251
Short name T436
Test name
Test status
Simulation time 1385584763 ps
CPU time 6.83 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:02 PM PDT 24
Peak memory 221452 kb
Host smart-6560e531-d588-4821-9d9f-f8309ea4d101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245599251 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.4245599251
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3146968065
Short name T774
Test name
Test status
Simulation time 213010335 ps
CPU time 1.6 seconds
Started Jul 12 05:24:52 PM PDT 24
Finished Jul 12 05:24:54 PM PDT 24
Peak memory 205412 kb
Host smart-b0c5f0f6-1348-4b4f-b0f8-cc82878a1d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146968065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3146968065
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.588474197
Short name T1245
Test name
Test status
Simulation time 314847241 ps
CPU time 2.03 seconds
Started Jul 12 05:24:56 PM PDT 24
Finished Jul 12 05:25:00 PM PDT 24
Peak memory 212060 kb
Host smart-dc3bc576-1218-4a0d-9249-4406ee4c5288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588474197 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.588474197
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.2764038183
Short name T1290
Test name
Test status
Simulation time 493093896 ps
CPU time 1.23 seconds
Started Jul 12 05:25:02 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 205288 kb
Host smart-d721b9a6-aeb6-4aaf-9f41-9abba00ff45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764038183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.2764038183
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3127330801
Short name T1351
Test name
Test status
Simulation time 117756231 ps
CPU time 1.41 seconds
Started Jul 12 05:24:56 PM PDT 24
Finished Jul 12 05:24:59 PM PDT 24
Peak memory 205332 kb
Host smart-8ebebb77-40c0-4d31-b28e-089f4bd70205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127330801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3127330801
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.930289143
Short name T813
Test name
Test status
Simulation time 1517863083 ps
CPU time 8.93 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:24:58 PM PDT 24
Peak memory 221760 kb
Host smart-4d7bf733-0bd2-419d-bdbd-9f797d486abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930289143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.930289143
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2371743202
Short name T331
Test name
Test status
Simulation time 24164942032 ps
CPU time 578.64 seconds
Started Jul 12 05:24:47 PM PDT 24
Finished Jul 12 05:34:27 PM PDT 24
Peak memory 4279472 kb
Host smart-f85ed6bd-feb1-4595-a7fb-017db5c2571d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371743202 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2371743202
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.200308687
Short name T1269
Test name
Test status
Simulation time 899637532 ps
CPU time 2.63 seconds
Started Jul 12 05:24:56 PM PDT 24
Finished Jul 12 05:25:00 PM PDT 24
Peak memory 213628 kb
Host smart-cd594b8d-40d6-401d-b1bc-05ad76ab66aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200308687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_nack_acqfull.200308687
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.2796120060
Short name T310
Test name
Test status
Simulation time 545373422 ps
CPU time 2.98 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:00 PM PDT 24
Peak memory 205420 kb
Host smart-35a85c79-d065-4ddf-966d-f57d61ad89ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796120060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.2796120060
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.3102016197
Short name T370
Test name
Test status
Simulation time 1279855024 ps
CPU time 1.95 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:25:02 PM PDT 24
Peak memory 205224 kb
Host smart-e937d9e4-7941-4ea7-84b8-9ffc89da609e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102016197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.3102016197
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1559568951
Short name T1298
Test name
Test status
Simulation time 4226591106 ps
CPU time 37.04 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 213664 kb
Host smart-84686396-1699-4545-bd6f-c6c7f2a186d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559568951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1559568951
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.363810
Short name T1112
Test name
Test status
Simulation time 3208880983 ps
CPU time 15.73 seconds
Started Jul 12 05:24:46 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 218416 kb
Host smart-396e9633-5ba2-48f3-914c-cb72858a7c2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2
c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_stress_rd.363810
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1920675575
Short name T906
Test name
Test status
Simulation time 48021228373 ps
CPU time 1403.38 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:48:14 PM PDT 24
Peak memory 6992988 kb
Host smart-aa4e4f95-9090-4ff1-8cf2-f51a5b7445cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920675575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1920675575
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.606777427
Short name T625
Test name
Test status
Simulation time 5022226245 ps
CPU time 190.76 seconds
Started Jul 12 05:24:48 PM PDT 24
Finished Jul 12 05:28:00 PM PDT 24
Peak memory 1324636 kb
Host smart-078649bd-26c2-4eb7-823d-335f7f1bf630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606777427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.606777427
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.44439179
Short name T417
Test name
Test status
Simulation time 3704508103 ps
CPU time 6.73 seconds
Started Jul 12 05:24:50 PM PDT 24
Finished Jul 12 05:24:58 PM PDT 24
Peak memory 221836 kb
Host smart-7e4bab13-1ae6-4f15-8471-77ea804c5951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44439179 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_timeout.44439179
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.594934211
Short name T1548
Test name
Test status
Simulation time 152954938 ps
CPU time 3.58 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 205816 kb
Host smart-62140e12-6bee-4c5a-9bcd-88a4b5b3dc1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594934211 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.594934211
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3148740413
Short name T947
Test name
Test status
Simulation time 23724225 ps
CPU time 0.64 seconds
Started Jul 12 05:25:01 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 204636 kb
Host smart-e988b222-bbf8-41cd-afb1-3c8d5055e046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148740413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3148740413
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2406739778
Short name T18
Test name
Test status
Simulation time 124461720 ps
CPU time 2.33 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 216052 kb
Host smart-4e0127dd-e253-459c-88dc-8185c5d7058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406739778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2406739778
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2797883103
Short name T737
Test name
Test status
Simulation time 1811644088 ps
CPU time 7.71 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 274528 kb
Host smart-3b0fc313-13af-43ca-9007-7906879ccbcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797883103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2797883103
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3898989417
Short name T1036
Test name
Test status
Simulation time 2781723662 ps
CPU time 107.48 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:26:44 PM PDT 24
Peak memory 872780 kb
Host smart-6ab7be62-c3a3-4cc2-b9e9-f3305a791e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898989417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3898989417
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2322022363
Short name T1376
Test name
Test status
Simulation time 1300971044 ps
CPU time 79.02 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 433488 kb
Host smart-1f7919bc-6aa2-47a9-ad9a-3e2ea0136a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322022363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2322022363
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.4251001605
Short name T666
Test name
Test status
Simulation time 431174948 ps
CPU time 1.2 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:24:57 PM PDT 24
Peak memory 205188 kb
Host smart-802b0a2f-79b3-4262-bdf8-97992dbe18cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251001605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.4251001605
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2295397911
Short name T1231
Test name
Test status
Simulation time 280269483 ps
CPU time 4 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 227140 kb
Host smart-033c1048-f92f-4a20-8056-1725f3282802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295397911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2295397911
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3910118288
Short name T1516
Test name
Test status
Simulation time 18238598418 ps
CPU time 110 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:26:46 PM PDT 24
Peak memory 1299932 kb
Host smart-9860a403-b898-4c6c-8ef6-cfbaa03d8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910118288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3910118288
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.255263620
Short name T259
Test name
Test status
Simulation time 2751795516 ps
CPU time 9.09 seconds
Started Jul 12 05:24:59 PM PDT 24
Finished Jul 12 05:25:09 PM PDT 24
Peak memory 205344 kb
Host smart-b4698529-1ad0-4388-a552-5526cda8436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255263620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.255263620
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.884827150
Short name T1038
Test name
Test status
Simulation time 22079365 ps
CPU time 0.69 seconds
Started Jul 12 05:25:02 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 205116 kb
Host smart-74b57d9b-1677-4f7c-8027-7a79761d9f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884827150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.884827150
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2148591384
Short name T686
Test name
Test status
Simulation time 361642434 ps
CPU time 14.52 seconds
Started Jul 12 05:24:56 PM PDT 24
Finished Jul 12 05:25:12 PM PDT 24
Peak memory 214244 kb
Host smart-2ea581ba-1bf2-4bfa-abc1-b169989e1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148591384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2148591384
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.2092143092
Short name T47
Test name
Test status
Simulation time 3167606344 ps
CPU time 41.63 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 205144 kb
Host smart-0cf8e155-3850-4bd2-a047-70c9745bda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092143092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.2092143092
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.979616755
Short name T312
Test name
Test status
Simulation time 1333969769 ps
CPU time 60.09 seconds
Started Jul 12 05:24:53 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 334864 kb
Host smart-df697875-d123-4d95-a6af-a58d5c98af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979616755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.979616755
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3291301063
Short name T1312
Test name
Test status
Simulation time 1902232498 ps
CPU time 7.45 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:03 PM PDT 24
Peak memory 214744 kb
Host smart-9a1c7eb2-6f8d-4422-9a38-a571e9874503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291301063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3291301063
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1254697762
Short name T688
Test name
Test status
Simulation time 17953479278 ps
CPU time 6.23 seconds
Started Jul 12 05:24:54 PM PDT 24
Finished Jul 12 05:25:02 PM PDT 24
Peak memory 219828 kb
Host smart-b6b73043-1db7-473d-a4b6-f7b1f3012372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254697762 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1254697762
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1802856804
Short name T283
Test name
Test status
Simulation time 265953524 ps
CPU time 1.08 seconds
Started Jul 12 05:24:53 PM PDT 24
Finished Jul 12 05:24:56 PM PDT 24
Peak memory 205296 kb
Host smart-e6962412-5714-443d-af06-f54b75946735
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802856804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1802856804
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.591810717
Short name T181
Test name
Test status
Simulation time 828847562 ps
CPU time 1.76 seconds
Started Jul 12 05:24:53 PM PDT 24
Finished Jul 12 05:24:57 PM PDT 24
Peak memory 207396 kb
Host smart-c61b30f6-272c-4666-889f-04b088c4c070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591810717 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.591810717
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.187256060
Short name T562
Test name
Test status
Simulation time 943656955 ps
CPU time 2.39 seconds
Started Jul 12 05:25:00 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 205228 kb
Host smart-819db93c-bfc1-4af7-a144-cf71959110ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187256060 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.187256060
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.4283345513
Short name T1370
Test name
Test status
Simulation time 154473009 ps
CPU time 1.37 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 205260 kb
Host smart-e83048e8-ef9f-45f5-b0dd-e66cc2122053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283345513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.4283345513
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.4269965722
Short name T341
Test name
Test status
Simulation time 3525145911 ps
CPU time 5.47 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 213712 kb
Host smart-03c8c5af-09bc-44c4-8f92-fcb698051643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269965722 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.4269965722
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3935723086
Short name T1383
Test name
Test status
Simulation time 4904811203 ps
CPU time 8.25 seconds
Started Jul 12 05:24:52 PM PDT 24
Finished Jul 12 05:25:00 PM PDT 24
Peak memory 430764 kb
Host smart-aa10f587-a25d-4769-955a-7be352b01113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935723086 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3935723086
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.2342050930
Short name T1106
Test name
Test status
Simulation time 3351692681 ps
CPU time 3.04 seconds
Started Jul 12 05:24:59 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 213676 kb
Host smart-29765bd4-6561-4e60-91e6-44fe2d510f4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342050930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.2342050930
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.21387725
Short name T1457
Test name
Test status
Simulation time 2009844309 ps
CPU time 2.62 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:25:02 PM PDT 24
Peak memory 205308 kb
Host smart-a7409ac6-a2e7-4369-a4c2-4d85933633a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21387725 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_nack_acqfull_addr.21387725
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.2925087594
Short name T804
Test name
Test status
Simulation time 402792288 ps
CPU time 1.98 seconds
Started Jul 12 05:25:09 PM PDT 24
Finished Jul 12 05:25:11 PM PDT 24
Peak memory 205300 kb
Host smart-440a746c-b1eb-4dd1-8b66-62b11836987c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925087594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_smbus_maxlen.2925087594
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2632723616
Short name T827
Test name
Test status
Simulation time 3118968557 ps
CPU time 25.18 seconds
Started Jul 12 05:26:47 PM PDT 24
Finished Jul 12 05:27:14 PM PDT 24
Peak memory 213628 kb
Host smart-c1528a5c-b7d2-4413-97a7-01a9796f7eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632723616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2632723616
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3071681155
Short name T408
Test name
Test status
Simulation time 1211906756 ps
CPU time 27.59 seconds
Started Jul 12 05:24:56 PM PDT 24
Finished Jul 12 05:25:25 PM PDT 24
Peak memory 213604 kb
Host smart-00d8bd98-39e2-4ff5-bd32-b60a5174be7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071681155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3071681155
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.4084172934
Short name T467
Test name
Test status
Simulation time 11768638019 ps
CPU time 5.15 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:25:04 PM PDT 24
Peak memory 205476 kb
Host smart-200ef6fd-d55d-421e-959a-778cddc01c2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084172934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.4084172934
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1952589263
Short name T792
Test name
Test status
Simulation time 1946255408 ps
CPU time 85.72 seconds
Started Jul 12 05:24:55 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 610428 kb
Host smart-ce388b6e-3146-4dd1-8c69-707120f9e2ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952589263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1952589263
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2124981180
Short name T437
Test name
Test status
Simulation time 1024436595 ps
CPU time 6.14 seconds
Started Jul 12 05:24:57 PM PDT 24
Finished Jul 12 05:25:05 PM PDT 24
Peak memory 221780 kb
Host smart-b6a0084c-d9d9-48b6-8331-a43eade1173d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124981180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2124981180
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.3623993301
Short name T1518
Test name
Test status
Simulation time 576644684 ps
CPU time 8.56 seconds
Started Jul 12 05:25:00 PM PDT 24
Finished Jul 12 05:25:10 PM PDT 24
Peak memory 205480 kb
Host smart-f1a900cd-463e-4015-878b-67151709fb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623993301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3623993301
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2932766994
Short name T1197
Test name
Test status
Simulation time 17587945 ps
CPU time 0.66 seconds
Started Jul 12 05:25:06 PM PDT 24
Finished Jul 12 05:25:08 PM PDT 24
Peak memory 204748 kb
Host smart-cf783add-22ce-4611-b3c6-e08e0193290d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932766994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2932766994
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2176136548
Short name T726
Test name
Test status
Simulation time 694586558 ps
CPU time 4.37 seconds
Started Jul 12 05:25:03 PM PDT 24
Finished Jul 12 05:25:08 PM PDT 24
Peak memory 221084 kb
Host smart-e4de607c-b94f-4458-bced-733ad76bfb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176136548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2176136548
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.116688132
Short name T942
Test name
Test status
Simulation time 317563541 ps
CPU time 14.66 seconds
Started Jul 12 05:25:02 PM PDT 24
Finished Jul 12 05:25:18 PM PDT 24
Peak memory 264748 kb
Host smart-53e6a01b-1eed-47d3-ba06-d72ae4dba090
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116688132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.116688132
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1430513878
Short name T137
Test name
Test status
Simulation time 1924661056 ps
CPU time 51.49 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:25:51 PM PDT 24
Peak memory 566276 kb
Host smart-790c8a67-cb0c-4303-a03f-49f065354973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430513878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1430513878
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1941628748
Short name T1305
Test name
Test status
Simulation time 1375528408 ps
CPU time 94.87 seconds
Started Jul 12 05:25:03 PM PDT 24
Finished Jul 12 05:26:39 PM PDT 24
Peak memory 537984 kb
Host smart-898e95bb-d2c3-4dfa-8a0f-26bc87976ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941628748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1941628748
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.701906062
Short name T253
Test name
Test status
Simulation time 358678057 ps
CPU time 0.92 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 205108 kb
Host smart-64ff639c-9145-412c-b3b1-f96e74d41abb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701906062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.701906062
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1104471330
Short name T1458
Test name
Test status
Simulation time 411089159 ps
CPU time 4.98 seconds
Started Jul 12 05:24:59 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 242952 kb
Host smart-870125d2-2aae-4304-9945-16b00c5a5b2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104471330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1104471330
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.4013497918
Short name T1400
Test name
Test status
Simulation time 3871366138 ps
CPU time 117.39 seconds
Started Jul 12 05:24:58 PM PDT 24
Finished Jul 12 05:26:57 PM PDT 24
Peak memory 1169084 kb
Host smart-c21d82b5-36d0-423e-bbd9-2c7b609c4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013497918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.4013497918
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_override.4277192990
Short name T101
Test name
Test status
Simulation time 57967696 ps
CPU time 0.65 seconds
Started Jul 12 05:25:10 PM PDT 24
Finished Jul 12 05:25:11 PM PDT 24
Peak memory 205084 kb
Host smart-584f351a-1a0c-4594-9725-49d0fd18b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277192990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4277192990
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1058537883
Short name T17
Test name
Test status
Simulation time 5600772042 ps
CPU time 21.12 seconds
Started Jul 12 05:24:59 PM PDT 24
Finished Jul 12 05:25:21 PM PDT 24
Peak memory 222924 kb
Host smart-786dca7a-aebf-43ed-9873-8b98cc3f23bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058537883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1058537883
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1931113488
Short name T1506
Test name
Test status
Simulation time 865215006 ps
CPU time 34 seconds
Started Jul 12 05:25:10 PM PDT 24
Finished Jul 12 05:25:45 PM PDT 24
Peak memory 205208 kb
Host smart-bf170907-a9ab-4203-9424-1373227bf278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931113488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1931113488
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1923125725
Short name T298
Test name
Test status
Simulation time 2125639152 ps
CPU time 47.18 seconds
Started Jul 12 05:25:09 PM PDT 24
Finished Jul 12 05:25:57 PM PDT 24
Peak memory 265684 kb
Host smart-9e478387-4c7a-42e0-9ab1-dfebb0ccc28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923125725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1923125725
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2309189188
Short name T1111
Test name
Test status
Simulation time 1136139458 ps
CPU time 16.19 seconds
Started Jul 12 05:25:00 PM PDT 24
Finished Jul 12 05:25:18 PM PDT 24
Peak memory 213396 kb
Host smart-a72a3c05-7d24-4449-a15c-da287e800e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309189188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2309189188
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.284817436
Short name T433
Test name
Test status
Simulation time 1332761208 ps
CPU time 5.95 seconds
Started Jul 12 05:25:06 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 221816 kb
Host smart-24446cfc-f268-4376-84e7-33faa6d8008e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284817436 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.284817436
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1364521350
Short name T1331
Test name
Test status
Simulation time 1320444042 ps
CPU time 1.48 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 205420 kb
Host smart-44977f38-e076-4e99-a4a9-4b0377ed9715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364521350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1364521350
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3830382752
Short name T314
Test name
Test status
Simulation time 164877485 ps
CPU time 0.93 seconds
Started Jul 12 05:25:09 PM PDT 24
Finished Jul 12 05:25:11 PM PDT 24
Peak memory 205332 kb
Host smart-bad90289-b60a-449f-bba4-045b35b832be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830382752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3830382752
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2882077745
Short name T778
Test name
Test status
Simulation time 871666142 ps
CPU time 2.72 seconds
Started Jul 12 05:25:08 PM PDT 24
Finished Jul 12 05:25:12 PM PDT 24
Peak memory 205292 kb
Host smart-736d51d7-1d0c-47ab-aabd-6af4bfd1833c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882077745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2882077745
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.3322961052
Short name T1206
Test name
Test status
Simulation time 1207929301 ps
CPU time 1.61 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:25:10 PM PDT 24
Peak memory 205316 kb
Host smart-28e61873-822e-49fd-9fea-9b6f4962d47c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322961052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.3322961052
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.831493120
Short name T525
Test name
Test status
Simulation time 1005541903 ps
CPU time 5.92 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 221800 kb
Host smart-833b6226-41ad-4247-9816-cc7439a9ecd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831493120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.831493120
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2910787487
Short name T585
Test name
Test status
Simulation time 21413143020 ps
CPU time 151.37 seconds
Started Jul 12 05:25:04 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 1730584 kb
Host smart-a636b0df-d67d-4a87-b3ad-2e51f6967524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910787487 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2910787487
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.2873813200
Short name T1395
Test name
Test status
Simulation time 594074811 ps
CPU time 3.04 seconds
Started Jul 12 05:25:06 PM PDT 24
Finished Jul 12 05:25:10 PM PDT 24
Peak memory 213512 kb
Host smart-b6538382-256c-49d3-8bb8-f381a96bb353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873813200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.2873813200
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.1627555534
Short name T1489
Test name
Test status
Simulation time 5346074631 ps
CPU time 2.75 seconds
Started Jul 12 05:25:04 PM PDT 24
Finished Jul 12 05:25:07 PM PDT 24
Peak memory 205464 kb
Host smart-20531c22-e762-466f-b3a2-9228dca093fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627555534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.1627555534
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.920073645
Short name T1270
Test name
Test status
Simulation time 1920171615 ps
CPU time 2.37 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:25:10 PM PDT 24
Peak memory 205296 kb
Host smart-cef7a023-38e6-4510-82ba-2a63aabe568b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920073645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_smbus_maxlen.920073645
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2056926613
Short name T941
Test name
Test status
Simulation time 1200545177 ps
CPU time 17.42 seconds
Started Jul 12 05:24:59 PM PDT 24
Finished Jul 12 05:25:18 PM PDT 24
Peak memory 213604 kb
Host smart-46d9f3af-21eb-4eb7-99d5-48c072adf3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056926613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2056926613
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1178027228
Short name T1500
Test name
Test status
Simulation time 850660221 ps
CPU time 37.66 seconds
Started Jul 12 05:25:05 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 213584 kb
Host smart-dbc5cc30-4101-4d59-92db-8256d0719857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178027228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1178027228
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.100463612
Short name T648
Test name
Test status
Simulation time 13718555221 ps
CPU time 9.25 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 205316 kb
Host smart-12ba198f-51bf-4565-979f-d4995c6bc91f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100463612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.100463612
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.34348416
Short name T455
Test name
Test status
Simulation time 1462113117 ps
CPU time 3.98 seconds
Started Jul 12 05:25:08 PM PDT 24
Finished Jul 12 05:25:13 PM PDT 24
Peak memory 258740 kb
Host smart-94faf969-ae63-4bb0-9d18-566cb577e990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34348416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_stretch.34348416
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.102211947
Short name T1488
Test name
Test status
Simulation time 14373325708 ps
CPU time 6.65 seconds
Started Jul 12 05:25:05 PM PDT 24
Finished Jul 12 05:25:13 PM PDT 24
Peak memory 221008 kb
Host smart-38d460f4-af34-4a3e-b33f-c9a0e5928480
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102211947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.102211947
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3950815159
Short name T1375
Test name
Test status
Simulation time 35878696 ps
CPU time 0.64 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 204620 kb
Host smart-87cc3b1d-309d-4ffb-97a5-f7083e67b513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950815159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3950815159
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.57453389
Short name T784
Test name
Test status
Simulation time 87239004 ps
CPU time 1.78 seconds
Started Jul 12 05:25:12 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 214644 kb
Host smart-9798633c-11b9-47d6-b467-9c1c085d1989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57453389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.57453389
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2814935507
Short name T1022
Test name
Test status
Simulation time 303153484 ps
CPU time 9.15 seconds
Started Jul 12 05:25:16 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 234716 kb
Host smart-ca55c1ff-78da-44b8-a9ae-73ab13432dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814935507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2814935507
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.115628053
Short name T1146
Test name
Test status
Simulation time 4564641032 ps
CPU time 61.55 seconds
Started Jul 12 05:25:12 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 384600 kb
Host smart-d2f880c2-985e-4aa3-a5a0-76935f01322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115628053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.115628053
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2347306883
Short name T426
Test name
Test status
Simulation time 2583986640 ps
CPU time 191.2 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 805436 kb
Host smart-a1a8c28e-1453-40f5-8189-e82d1316c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347306883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2347306883
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3287362937
Short name T624
Test name
Test status
Simulation time 36929061 ps
CPU time 0.92 seconds
Started Jul 12 05:25:11 PM PDT 24
Finished Jul 12 05:25:13 PM PDT 24
Peak memory 205228 kb
Host smart-b9044479-fac8-4d34-88af-ac8023e6ecb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287362937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3287362937
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3547780321
Short name T171
Test name
Test status
Simulation time 133831209 ps
CPU time 7.98 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:27 PM PDT 24
Peak memory 229148 kb
Host smart-28ef3a87-81ac-4b4e-8898-9b9c61291961
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547780321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3547780321
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.724565452
Short name T771
Test name
Test status
Simulation time 18751265676 ps
CPU time 97.95 seconds
Started Jul 12 05:25:07 PM PDT 24
Finished Jul 12 05:26:46 PM PDT 24
Peak memory 1008700 kb
Host smart-c0a60656-3ccd-4902-95ef-9d63c2faceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724565452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.724565452
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1180426960
Short name T264
Test name
Test status
Simulation time 1127747081 ps
CPU time 4.57 seconds
Started Jul 12 05:25:11 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 205264 kb
Host smart-172f52a4-ac9c-40ea-84f5-ba99804b309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180426960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1180426960
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_override.1621380455
Short name T811
Test name
Test status
Simulation time 77577364 ps
CPU time 0.66 seconds
Started Jul 12 05:25:05 PM PDT 24
Finished Jul 12 05:25:07 PM PDT 24
Peak memory 205104 kb
Host smart-eb851245-636b-4404-94be-6c2a6afdc4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621380455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1621380455
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2268500457
Short name T789
Test name
Test status
Simulation time 31425572790 ps
CPU time 143.74 seconds
Started Jul 12 05:25:14 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 318688 kb
Host smart-1394c221-0ce5-4550-9e58-7f3a4ec66d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268500457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2268500457
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1387185834
Short name T366
Test name
Test status
Simulation time 67602054 ps
CPU time 1.67 seconds
Started Jul 12 05:25:14 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 223128 kb
Host smart-99d47555-9220-4c3e-a931-c98d30033bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387185834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1387185834
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2427895740
Short name T1131
Test name
Test status
Simulation time 7535759566 ps
CPU time 39.59 seconds
Started Jul 12 05:25:06 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 403384 kb
Host smart-b63ba290-8c54-4807-9a16-5ea313ca6b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427895740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2427895740
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.938521240
Short name T844
Test name
Test status
Simulation time 510716623 ps
CPU time 21.5 seconds
Started Jul 12 05:25:11 PM PDT 24
Finished Jul 12 05:25:33 PM PDT 24
Peak memory 213516 kb
Host smart-77162698-6222-46a4-bff9-ac56aca23c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938521240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.938521240
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.558526828
Short name T974
Test name
Test status
Simulation time 1098875599 ps
CPU time 5.77 seconds
Started Jul 12 05:25:17 PM PDT 24
Finished Jul 12 05:25:25 PM PDT 24
Peak memory 208648 kb
Host smart-81810c13-f8fb-41fb-8e5f-bc2b4fea35f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558526828 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.558526828
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.810053060
Short name T1165
Test name
Test status
Simulation time 333303085 ps
CPU time 1.25 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205324 kb
Host smart-73953b24-42da-4006-b056-26759c85ce25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810053060 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.810053060
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2820224212
Short name T1322
Test name
Test status
Simulation time 135237196 ps
CPU time 0.98 seconds
Started Jul 12 05:25:14 PM PDT 24
Finished Jul 12 05:25:16 PM PDT 24
Peak memory 205280 kb
Host smart-6643f07c-248d-4f25-977c-2b100b40bb84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820224212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2820224212
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.2997965124
Short name T1071
Test name
Test status
Simulation time 490548575 ps
CPU time 2.85 seconds
Started Jul 12 05:25:16 PM PDT 24
Finished Jul 12 05:25:20 PM PDT 24
Peak memory 205500 kb
Host smart-92fc4ddb-7884-40dc-b2a7-95a954500532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997965124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.2997965124
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.3537326130
Short name T1517
Test name
Test status
Simulation time 875004371 ps
CPU time 1.2 seconds
Started Jul 12 05:25:15 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 205328 kb
Host smart-91c14917-5b30-45a2-8fe6-17599fef7ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537326130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.3537326130
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1302518706
Short name T454
Test name
Test status
Simulation time 2265737469 ps
CPU time 5.15 seconds
Started Jul 12 05:25:13 PM PDT 24
Finished Jul 12 05:25:19 PM PDT 24
Peak memory 213692 kb
Host smart-af428d32-a380-4f72-8f7b-66655ed977ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302518706 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1302518706
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3395888359
Short name T6
Test name
Test status
Simulation time 23642429966 ps
CPU time 36.06 seconds
Started Jul 12 05:25:12 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 721444 kb
Host smart-259fd2a8-fab2-48b9-981b-40e6e26ff299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395888359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3395888359
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.2159321845
Short name T1175
Test name
Test status
Simulation time 542414524 ps
CPU time 3.08 seconds
Started Jul 12 05:25:13 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 213620 kb
Host smart-b94012da-d569-433c-a4b2-6776108d9eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159321845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.2159321845
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.2330071111
Short name T60
Test name
Test status
Simulation time 544850617 ps
CPU time 3.03 seconds
Started Jul 12 05:25:17 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205360 kb
Host smart-76d80ce1-8213-4a32-998e-a279e87142cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330071111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.2330071111
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.2405109799
Short name T126
Test name
Test status
Simulation time 7677005319 ps
CPU time 2.15 seconds
Started Jul 12 05:25:15 PM PDT 24
Finished Jul 12 05:25:18 PM PDT 24
Peak memory 205348 kb
Host smart-74cbc2e9-0c92-4113-8a50-c9e9b75d3b97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405109799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.2405109799
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2609089763
Short name T1421
Test name
Test status
Simulation time 8103815009 ps
CPU time 18.96 seconds
Started Jul 12 05:25:13 PM PDT 24
Finished Jul 12 05:25:33 PM PDT 24
Peak memory 213648 kb
Host smart-e8b60b70-58b8-48b6-bc4d-bebdfcbd60ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609089763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2609089763
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1151153801
Short name T1508
Test name
Test status
Simulation time 1334304881 ps
CPU time 6.66 seconds
Started Jul 12 05:25:13 PM PDT 24
Finished Jul 12 05:25:20 PM PDT 24
Peak memory 205420 kb
Host smart-5e5d54ef-2505-4300-b50b-a0b1ca4f52a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151153801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1151153801
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2596225949
Short name T1323
Test name
Test status
Simulation time 53576109233 ps
CPU time 189.45 seconds
Started Jul 12 05:25:13 PM PDT 24
Finished Jul 12 05:28:23 PM PDT 24
Peak memory 2073264 kb
Host smart-394ea0d5-0280-44e2-b34f-c45659bdc158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596225949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2596225949
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1379292322
Short name T498
Test name
Test status
Simulation time 5773703443 ps
CPU time 7.52 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 213668 kb
Host smart-c683d7c6-e6f2-4ac0-b952-7657000331a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379292322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1379292322
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.2213775355
Short name T10
Test name
Test status
Simulation time 76439788 ps
CPU time 1.45 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:21 PM PDT 24
Peak memory 205384 kb
Host smart-1105a914-1429-412c-b918-dc5821a066cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213775355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.2213775355
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2720623537
Short name T444
Test name
Test status
Simulation time 27866722 ps
CPU time 0.63 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 204612 kb
Host smart-42e18ac7-f9e7-4ae4-b409-2f82f2623582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720623537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2720623537
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3216482110
Short name T1118
Test name
Test status
Simulation time 90408888 ps
CPU time 1.94 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 213500 kb
Host smart-95708930-fd5f-46d3-92bc-0e4f77e98575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216482110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3216482110
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.648399327
Short name T1268
Test name
Test status
Simulation time 2234861394 ps
CPU time 11.3 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:25:33 PM PDT 24
Peak memory 321040 kb
Host smart-584f7261-6e2f-4507-8ef0-5620e45a6c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648399327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.648399327
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3731664642
Short name T1132
Test name
Test status
Simulation time 2730427580 ps
CPU time 95.34 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:26:56 PM PDT 24
Peak memory 888568 kb
Host smart-316342ea-c333-4767-98e6-2dc93e98e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731664642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3731664642
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3380773746
Short name T1092
Test name
Test status
Simulation time 8397605545 ps
CPU time 123.42 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 451288 kb
Host smart-2c9170f0-16e4-4f39-a37b-ca28cd5a0b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380773746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3380773746
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3840574026
Short name T431
Test name
Test status
Simulation time 121048313 ps
CPU time 1.17 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205124 kb
Host smart-c682e97e-043f-488b-aa3a-5cb5d8e8ffa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840574026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3840574026
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.300931571
Short name T1397
Test name
Test status
Simulation time 320269281 ps
CPU time 3.63 seconds
Started Jul 12 05:25:17 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205316 kb
Host smart-fda2fb1f-19f2-4309-9cc5-126acbf6fbe3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300931571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
300931571
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2127850187
Short name T79
Test name
Test status
Simulation time 20926036591 ps
CPU time 59.33 seconds
Started Jul 12 05:25:17 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 825964 kb
Host smart-54b19b61-4b51-4a9c-8196-896dab79ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127850187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2127850187
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3371407465
Short name T270
Test name
Test status
Simulation time 1984510643 ps
CPU time 7.22 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:25:29 PM PDT 24
Peak memory 205332 kb
Host smart-fdb190e2-42d5-4780-a411-89dfa1336ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371407465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3371407465
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.1527772681
Short name T145
Test name
Test status
Simulation time 19800456 ps
CPU time 0.7 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205268 kb
Host smart-e9485866-f41d-4a3f-86cc-141fbe1069aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527772681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1527772681
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2939525373
Short name T1479
Test name
Test status
Simulation time 2341341739 ps
CPU time 9.23 seconds
Started Jul 12 05:25:21 PM PDT 24
Finished Jul 12 05:25:32 PM PDT 24
Peak memory 234152 kb
Host smart-d4be6026-4124-4d62-a533-90128ed49e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939525373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2939525373
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.2851752624
Short name T1055
Test name
Test status
Simulation time 227491381 ps
CPU time 1.47 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:22 PM PDT 24
Peak memory 205128 kb
Host smart-acab93d3-c20a-47c5-9ca1-36cc9d82dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851752624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.2851752624
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3383813466
Short name T1389
Test name
Test status
Simulation time 7415854959 ps
CPU time 23.18 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:25:46 PM PDT 24
Peak memory 324468 kb
Host smart-99d7965b-e165-4219-af06-f4dbba8185be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383813466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3383813466
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.601554678
Short name T289
Test name
Test status
Simulation time 40928673469 ps
CPU time 611.54 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:35:34 PM PDT 24
Peak memory 1341604 kb
Host smart-51998ae6-90d6-472e-aca8-d755461cd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601554678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.601554678
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.541096383
Short name T575
Test name
Test status
Simulation time 7327153035 ps
CPU time 44.3 seconds
Started Jul 12 05:25:21 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 214248 kb
Host smart-1a4d89c3-b5cd-469a-b228-d2a586f3bd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541096383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.541096383
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.461997164
Short name T1183
Test name
Test status
Simulation time 3393831455 ps
CPU time 5.42 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 218280 kb
Host smart-4bed98bc-d5a3-42b6-bf7e-1e78d4db86b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461997164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.461997164
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1379702453
Short name T1364
Test name
Test status
Simulation time 157687445 ps
CPU time 0.78 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:21 PM PDT 24
Peak memory 205172 kb
Host smart-6e935e2f-5808-45fe-80fd-87483bb4369f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379702453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1379702453
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3354759132
Short name T307
Test name
Test status
Simulation time 312476678 ps
CPU time 0.92 seconds
Started Jul 12 05:25:17 PM PDT 24
Finished Jul 12 05:25:20 PM PDT 24
Peak memory 205316 kb
Host smart-b6b79c45-b35f-4a4c-9e7e-2560914703e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354759132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3354759132
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.725442006
Short name T1309
Test name
Test status
Simulation time 379326366 ps
CPU time 2.36 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 205380 kb
Host smart-115a2b06-cab3-44f9-92e5-6473603c4714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725442006 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.725442006
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3526166387
Short name T176
Test name
Test status
Simulation time 664411064 ps
CPU time 1.2 seconds
Started Jul 12 05:25:20 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 205264 kb
Host smart-41cadc1c-8bdc-47e6-ac9b-a66d05b0d4e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526166387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3526166387
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1796843610
Short name T322
Test name
Test status
Simulation time 3380608725 ps
CPU time 5.61 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:25 PM PDT 24
Peak memory 221812 kb
Host smart-36a45d9b-4811-48bf-8031-0f0e5779054f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796843610 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1796843610
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1095799256
Short name T374
Test name
Test status
Simulation time 10771261159 ps
CPU time 7.37 seconds
Started Jul 12 05:25:19 PM PDT 24
Finished Jul 12 05:25:29 PM PDT 24
Peak memory 205528 kb
Host smart-87c4c6e3-67cf-47f4-b720-54b0cfe0192e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095799256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1095799256
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.4279536592
Short name T751
Test name
Test status
Simulation time 491255309 ps
CPU time 2.95 seconds
Started Jul 12 05:25:23 PM PDT 24
Finished Jul 12 05:25:27 PM PDT 24
Peak memory 213596 kb
Host smart-27ab549b-80a5-4dbb-9066-bb9772c7c253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279536592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.4279536592
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.1443206451
Short name T68
Test name
Test status
Simulation time 1967967802 ps
CPU time 2.76 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:27 PM PDT 24
Peak memory 205360 kb
Host smart-a02743eb-8ff0-4295-a0ec-2ab3ea791612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443206451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.1443206451
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.3539234654
Short name T524
Test name
Test status
Simulation time 1571539029 ps
CPU time 2.13 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 205120 kb
Host smart-a2681d82-b7c8-448f-b6eb-31d1facd4549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539234654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.3539234654
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.3720786902
Short name T1192
Test name
Test status
Simulation time 1039845166 ps
CPU time 14.25 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 213464 kb
Host smart-139ba1a9-3ece-47f7-ae34-eb5ac5876470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720786902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.3720786902
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.433558587
Short name T199
Test name
Test status
Simulation time 1096817784 ps
CPU time 23.66 seconds
Started Jul 12 05:25:23 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 213616 kb
Host smart-2b689f48-34e8-4b9f-95b4-329fcf54a9f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433558587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.433558587
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.386252195
Short name T386
Test name
Test status
Simulation time 14305633945 ps
CPU time 8.03 seconds
Started Jul 12 05:25:23 PM PDT 24
Finished Jul 12 05:25:32 PM PDT 24
Peak memory 205488 kb
Host smart-01aaaed6-654a-42b6-a87a-ad67ad0451ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386252195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.386252195
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.242176934
Short name T319
Test name
Test status
Simulation time 1979441536 ps
CPU time 5.75 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 266688 kb
Host smart-32e202c1-ca66-4b9e-9beb-21525f5e0b97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242176934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_t
arget_stretch.242176934
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1623280266
Short name T952
Test name
Test status
Simulation time 6524012700 ps
CPU time 7.72 seconds
Started Jul 12 05:25:18 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 220472 kb
Host smart-8693cb34-7642-4d06-b855-58507ac30325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623280266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1623280266
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2331497879
Short name T1116
Test name
Test status
Simulation time 65176945 ps
CPU time 1.54 seconds
Started Jul 12 05:25:21 PM PDT 24
Finished Jul 12 05:25:24 PM PDT 24
Peak memory 205424 kb
Host smart-9c23bd96-0788-4b1c-a628-01b2cb6b99f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331497879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2331497879
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3257454762
Short name T376
Test name
Test status
Simulation time 49636275 ps
CPU time 0.63 seconds
Started Jul 12 05:25:31 PM PDT 24
Finished Jul 12 05:25:33 PM PDT 24
Peak memory 204752 kb
Host smart-b34a721f-3f2f-4417-9189-ffab9ed0aefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257454762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3257454762
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.4266923042
Short name T410
Test name
Test status
Simulation time 149119093 ps
CPU time 1.31 seconds
Started Jul 12 05:25:25 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 213560 kb
Host smart-6e5e25c5-400e-43cb-a975-86891ee20a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266923042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.4266923042
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2739710519
Short name T9
Test name
Test status
Simulation time 325530900 ps
CPU time 15.72 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:39 PM PDT 24
Peak memory 240256 kb
Host smart-29f982b1-3def-46c3-935b-e382cfbcd8bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739710519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2739710519
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.343345575
Short name T392
Test name
Test status
Simulation time 3093532916 ps
CPU time 105.03 seconds
Started Jul 12 05:25:26 PM PDT 24
Finished Jul 12 05:27:12 PM PDT 24
Peak memory 911860 kb
Host smart-e3cd8806-8a28-4824-9b87-8b8d88d0ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343345575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.343345575
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1549698122
Short name T1275
Test name
Test status
Simulation time 3161877617 ps
CPU time 47.37 seconds
Started Jul 12 05:25:24 PM PDT 24
Finished Jul 12 05:26:13 PM PDT 24
Peak memory 523972 kb
Host smart-28e1bd83-bf54-4b5d-9681-8de8c3778156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549698122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1549698122
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1372941027
Short name T702
Test name
Test status
Simulation time 83525100 ps
CPU time 0.99 seconds
Started Jul 12 05:25:24 PM PDT 24
Finished Jul 12 05:25:26 PM PDT 24
Peak memory 205032 kb
Host smart-5f8931e2-9ab9-4604-923b-bb88b8a7f148
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372941027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1372941027
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.864406940
Short name T943
Test name
Test status
Simulation time 237826223 ps
CPU time 6.56 seconds
Started Jul 12 05:25:24 PM PDT 24
Finished Jul 12 05:25:32 PM PDT 24
Peak memory 205268 kb
Host smart-8d24b255-a171-43e3-b1b9-e4dab66b32b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864406940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
864406940
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1716316600
Short name T1419
Test name
Test status
Simulation time 8511195867 ps
CPU time 121.15 seconds
Started Jul 12 05:25:27 PM PDT 24
Finished Jul 12 05:27:29 PM PDT 24
Peak memory 1223444 kb
Host smart-73495db1-687c-4c98-bcd4-a112401814e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716316600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1716316600
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1246020048
Short name T277
Test name
Test status
Simulation time 566131568 ps
CPU time 6.55 seconds
Started Jul 12 05:25:30 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 205280 kb
Host smart-3494b2d3-af98-4266-91fe-899aac99ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246020048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1246020048
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.1952270132
Short name T1497
Test name
Test status
Simulation time 32354090 ps
CPU time 0.74 seconds
Started Jul 12 05:25:27 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 205076 kb
Host smart-a6770e17-cd0b-4e8b-b734-7cbe2082cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952270132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1952270132
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3161660747
Short name T1018
Test name
Test status
Simulation time 3536474888 ps
CPU time 8.3 seconds
Started Jul 12 05:25:24 PM PDT 24
Finished Jul 12 05:25:34 PM PDT 24
Peak memory 225252 kb
Host smart-e13d3841-0942-471a-9877-6f8134ab34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161660747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3161660747
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.652747218
Short name T1325
Test name
Test status
Simulation time 204380039 ps
CPU time 1.06 seconds
Started Jul 12 05:25:22 PM PDT 24
Finished Jul 12 05:25:25 PM PDT 24
Peak memory 222888 kb
Host smart-39c987a2-5696-42a0-9bee-9d55d695e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652747218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.652747218
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3593750767
Short name T318
Test name
Test status
Simulation time 6088422836 ps
CPU time 32.81 seconds
Started Jul 12 05:25:28 PM PDT 24
Finished Jul 12 05:26:01 PM PDT 24
Peak memory 407116 kb
Host smart-4a587dc4-88da-4d5d-9b40-7f09fd99e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593750767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3593750767
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2514798454
Short name T273
Test name
Test status
Simulation time 53119740999 ps
CPU time 583.51 seconds
Started Jul 12 05:25:25 PM PDT 24
Finished Jul 12 05:35:10 PM PDT 24
Peak memory 2071272 kb
Host smart-062e3436-4953-48c7-a9de-725fd765b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514798454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2514798454
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2272550115
Short name T646
Test name
Test status
Simulation time 589235807 ps
CPU time 11.93 seconds
Started Jul 12 05:25:25 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 221756 kb
Host smart-5de82e6e-d500-46ae-9f82-fb9639d9317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272550115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2272550115
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1211500703
Short name T1263
Test name
Test status
Simulation time 1548814440 ps
CPU time 3.83 seconds
Started Jul 12 05:25:30 PM PDT 24
Finished Jul 12 05:25:35 PM PDT 24
Peak memory 213620 kb
Host smart-eab3cf81-ef9d-4bc1-93ab-b05d68e74171
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211500703 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1211500703
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.875908033
Short name T1204
Test name
Test status
Simulation time 140226334 ps
CPU time 1.01 seconds
Started Jul 12 05:25:35 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 205312 kb
Host smart-47b1aaf6-727a-4f97-938a-2887982e410d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875908033 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.875908033
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2884931312
Short name T280
Test name
Test status
Simulation time 226801761 ps
CPU time 1.49 seconds
Started Jul 12 05:25:34 PM PDT 24
Finished Jul 12 05:25:36 PM PDT 24
Peak memory 206204 kb
Host smart-2439b43f-c815-4711-bc8a-e28d98eebc35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884931312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2884931312
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1955220646
Short name T1212
Test name
Test status
Simulation time 581343275 ps
CPU time 3.09 seconds
Started Jul 12 05:25:30 PM PDT 24
Finished Jul 12 05:25:34 PM PDT 24
Peak memory 205392 kb
Host smart-4b4e7d85-5bea-4933-82bd-c8b49787ae0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955220646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1955220646
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.1790510591
Short name T1151
Test name
Test status
Simulation time 464358898 ps
CPU time 1.2 seconds
Started Jul 12 05:25:32 PM PDT 24
Finished Jul 12 05:25:34 PM PDT 24
Peak memory 205196 kb
Host smart-620deafb-fe95-4cd2-8f3d-df38b8d37021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790510591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.1790510591
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.389257610
Short name T959
Test name
Test status
Simulation time 3118705896 ps
CPU time 4.38 seconds
Started Jul 12 05:25:26 PM PDT 24
Finished Jul 12 05:25:31 PM PDT 24
Peak memory 213772 kb
Host smart-0c15aaa2-2705-4453-8365-e35f4ffbc0d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389257610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.389257610
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2854950416
Short name T73
Test name
Test status
Simulation time 10224500947 ps
CPU time 175.77 seconds
Started Jul 12 05:25:28 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 2501880 kb
Host smart-fe558546-8037-4e01-8851-f0e4fe383098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854950416 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2854950416
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.3928256051
Short name T1411
Test name
Test status
Simulation time 458335203 ps
CPU time 2.81 seconds
Started Jul 12 05:25:30 PM PDT 24
Finished Jul 12 05:25:34 PM PDT 24
Peak memory 213696 kb
Host smart-4d99803f-a8e9-4a51-80bd-066c29ee5b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928256051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.3928256051
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.4034683468
Short name T311
Test name
Test status
Simulation time 1650423715 ps
CPU time 2.81 seconds
Started Jul 12 05:25:31 PM PDT 24
Finished Jul 12 05:25:35 PM PDT 24
Peak memory 205428 kb
Host smart-a68cc898-8a1b-411f-a337-4f40e8f7ddf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034683468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.4034683468
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.1994106035
Short name T491
Test name
Test status
Simulation time 1950639908 ps
CPU time 2.25 seconds
Started Jul 12 05:25:28 PM PDT 24
Finished Jul 12 05:25:31 PM PDT 24
Peak memory 205264 kb
Host smart-015e8e77-f309-4fe6-a133-51d4432bff3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994106035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.1994106035
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2768451258
Short name T522
Test name
Test status
Simulation time 2386198474 ps
CPU time 19.3 seconds
Started Jul 12 05:25:27 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 213692 kb
Host smart-0b955c99-6d6d-4e2e-a0c2-3e09a1787541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768451258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2768451258
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3442735733
Short name T456
Test name
Test status
Simulation time 1449518919 ps
CPU time 66.28 seconds
Started Jul 12 05:25:25 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 218040 kb
Host smart-5c078ea8-4d47-4e3f-addc-3b5ebe50efdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442735733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3442735733
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.4153123869
Short name T1024
Test name
Test status
Simulation time 17630703916 ps
CPU time 33.42 seconds
Started Jul 12 05:25:26 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 205488 kb
Host smart-e3120f09-a9b8-46d8-a7d1-4acffca2f129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153123869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.4153123869
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.4128201354
Short name T1009
Test name
Test status
Simulation time 1307906711 ps
CPU time 2.31 seconds
Started Jul 12 05:25:24 PM PDT 24
Finished Jul 12 05:25:28 PM PDT 24
Peak memory 213544 kb
Host smart-ed7c21ff-838a-4c9c-a736-6bac1157fabc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128201354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.4128201354
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.4289964532
Short name T1561
Test name
Test status
Simulation time 6117821364 ps
CPU time 7.58 seconds
Started Jul 12 05:25:26 PM PDT 24
Finished Jul 12 05:25:35 PM PDT 24
Peak memory 213680 kb
Host smart-5efbcf7e-de27-48c8-a35f-0a58bd920d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289964532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.4289964532
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.4080160414
Short name T786
Test name
Test status
Simulation time 186555005 ps
CPU time 3.1 seconds
Started Jul 12 05:25:33 PM PDT 24
Finished Jul 12 05:25:37 PM PDT 24
Peak memory 205392 kb
Host smart-6ac94cbf-f9c5-42bd-a4a2-b8985b883e0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080160414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.4080160414
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3172446338
Short name T791
Test name
Test status
Simulation time 35636277 ps
CPU time 0.63 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:25:40 PM PDT 24
Peak memory 204628 kb
Host smart-1f2c7d9a-0b8e-46db-801b-0abcdfe45475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172446338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3172446338
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.788341868
Short name T704
Test name
Test status
Simulation time 433587751 ps
CPU time 2.14 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 218496 kb
Host smart-92844cf6-fc6e-4363-81b2-b4bcb364bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788341868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.788341868
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.107652101
Short name T1288
Test name
Test status
Simulation time 265874996 ps
CPU time 5.51 seconds
Started Jul 12 05:25:29 PM PDT 24
Finished Jul 12 05:25:35 PM PDT 24
Peak memory 233364 kb
Host smart-110fc52e-5beb-48f5-8932-1d6e7e8fe8ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107652101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.107652101
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.4143823358
Short name T1478
Test name
Test status
Simulation time 1093579259 ps
CPU time 32.62 seconds
Started Jul 12 05:25:30 PM PDT 24
Finished Jul 12 05:26:03 PM PDT 24
Peak memory 477404 kb
Host smart-58febca0-35bc-45f2-af03-49e9f73c6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143823358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.4143823358
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3440884707
Short name T795
Test name
Test status
Simulation time 2664822174 ps
CPU time 97.34 seconds
Started Jul 12 05:25:32 PM PDT 24
Finished Jul 12 05:27:10 PM PDT 24
Peak memory 827288 kb
Host smart-4c011607-9e29-4a41-83d3-0b014b031de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440884707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3440884707
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2374973219
Short name T963
Test name
Test status
Simulation time 159773308 ps
CPU time 0.96 seconds
Started Jul 12 05:25:31 PM PDT 24
Finished Jul 12 05:25:33 PM PDT 24
Peak memory 205100 kb
Host smart-a07dd7eb-4a20-44b0-9aa8-026e0955d7e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374973219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2374973219
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3992015744
Short name T1347
Test name
Test status
Simulation time 144637966 ps
CPU time 3.75 seconds
Started Jul 12 05:25:31 PM PDT 24
Finished Jul 12 05:25:36 PM PDT 24
Peak memory 205292 kb
Host smart-a6c08e08-3492-4d71-8e29-99712a0ef183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992015744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3992015744
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.822521410
Short name T1462
Test name
Test status
Simulation time 5380514698 ps
CPU time 139.18 seconds
Started Jul 12 05:25:29 PM PDT 24
Finished Jul 12 05:27:49 PM PDT 24
Peak memory 1490504 kb
Host smart-d5166287-9bfc-4bcf-b6b3-3878a454cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822521410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.822521410
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_override.1030328634
Short name T1248
Test name
Test status
Simulation time 34055300 ps
CPU time 0.69 seconds
Started Jul 12 05:25:33 PM PDT 24
Finished Jul 12 05:25:34 PM PDT 24
Peak memory 205044 kb
Host smart-6277f05a-7559-4919-990d-e6a1f6f8c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030328634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1030328634
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3835367332
Short name T1094
Test name
Test status
Simulation time 1845239774 ps
CPU time 36.79 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:26:19 PM PDT 24
Peak memory 230296 kb
Host smart-33f57aa2-81fd-47e0-b910-cf2b85f64e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835367332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3835367332
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.49225723
Short name T893
Test name
Test status
Simulation time 294541486 ps
CPU time 1.87 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 213772 kb
Host smart-7f073add-2555-42f3-b31f-1338e6a86f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49225723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.49225723
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3289433055
Short name T506
Test name
Test status
Simulation time 40741243538 ps
CPU time 34.9 seconds
Started Jul 12 05:25:32 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 416612 kb
Host smart-8662930e-48f2-411e-8991-c27ad2ec6d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289433055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3289433055
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.538071087
Short name T409
Test name
Test status
Simulation time 1003674848 ps
CPU time 22.67 seconds
Started Jul 12 05:25:47 PM PDT 24
Finished Jul 12 05:26:11 PM PDT 24
Peak memory 213548 kb
Host smart-c2b26450-8a62-43a3-9995-8d697c733810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538071087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.538071087
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2924719455
Short name T62
Test name
Test status
Simulation time 2591116336 ps
CPU time 6.27 seconds
Started Jul 12 05:25:37 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 208464 kb
Host smart-b83562ae-b81f-47b4-913e-10603dd7fd9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924719455 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2924719455
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.4187991928
Short name T675
Test name
Test status
Simulation time 403669403 ps
CPU time 1.65 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:25:42 PM PDT 24
Peak memory 205508 kb
Host smart-840f573f-08f6-4fa0-a894-212131cbe4db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187991928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.4187991928
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3547784610
Short name T95
Test name
Test status
Simulation time 272352369 ps
CPU time 1.13 seconds
Started Jul 12 05:25:37 PM PDT 24
Finished Jul 12 05:25:39 PM PDT 24
Peak memory 213664 kb
Host smart-251ca981-a342-4a2c-bf63-5044956ef245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547784610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3547784610
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.1249526700
Short name T1237
Test name
Test status
Simulation time 514525478 ps
CPU time 1.64 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 205308 kb
Host smart-0f9f0e05-c7be-4521-8ea0-ed789a2d8ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249526700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.1249526700
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.519621127
Short name T1188
Test name
Test status
Simulation time 120733881 ps
CPU time 1.13 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 205320 kb
Host smart-14d74ece-28e2-46c1-9249-a705a60cc7c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519621127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.519621127
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3674152557
Short name T769
Test name
Test status
Simulation time 1230106717 ps
CPU time 7.84 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 221180 kb
Host smart-d7ba70af-1404-4885-9a76-41275fb19e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674152557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3674152557
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.4061311893
Short name T461
Test name
Test status
Simulation time 5004118287 ps
CPU time 2.05 seconds
Started Jul 12 05:25:40 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 205400 kb
Host smart-4abf4ad6-228d-417f-97bd-4032661c073b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061311893 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.4061311893
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.672019076
Short name T1285
Test name
Test status
Simulation time 1280401928 ps
CPU time 2.86 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 213420 kb
Host smart-0ea52430-45ec-479e-b8e0-4cfcec585a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672019076 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_nack_acqfull.672019076
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.2152564640
Short name T421
Test name
Test status
Simulation time 448530539 ps
CPU time 2.36 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 205416 kb
Host smart-77a053fe-e398-4f5a-ab4d-429076cee232
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152564640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.2152564640
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.1590691371
Short name T418
Test name
Test status
Simulation time 2031964317 ps
CPU time 2.27 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:25:41 PM PDT 24
Peak memory 205264 kb
Host smart-bc94d6c4-b4b6-4be4-8dcc-9ea888d8bea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590691371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.1590691371
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1372060467
Short name T928
Test name
Test status
Simulation time 5640902115 ps
CPU time 8.16 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 213528 kb
Host smart-c88e3d4f-6d70-4763-9155-bd5cd2888d8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372060467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1372060467
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3415380079
Short name T923
Test name
Test status
Simulation time 1456488992 ps
CPU time 27.13 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 230840 kb
Host smart-7d3484a7-5db0-4755-b3d5-30313b85e2ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415380079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3415380079
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1881885660
Short name T451
Test name
Test status
Simulation time 13388311268 ps
CPU time 14.41 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:25:53 PM PDT 24
Peak memory 205464 kb
Host smart-c00fe0a8-a297-4168-beb4-0458b6b25923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881885660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1881885660
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3517783714
Short name T513
Test name
Test status
Simulation time 3641727777 ps
CPU time 25.56 seconds
Started Jul 12 05:25:37 PM PDT 24
Finished Jul 12 05:26:03 PM PDT 24
Peak memory 570624 kb
Host smart-b9eba7a5-50cf-4dc9-a938-0008e11b070c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517783714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3517783714
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1419080898
Short name T1059
Test name
Test status
Simulation time 4773165991 ps
CPU time 6.77 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:52 PM PDT 24
Peak memory 221272 kb
Host smart-6ef228e5-57a0-4347-ab2c-cf935b4175ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419080898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1419080898
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.4266503745
Short name T871
Test name
Test status
Simulation time 146645353 ps
CPU time 3 seconds
Started Jul 12 05:25:35 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 205388 kb
Host smart-5b1acded-4439-4c9e-9dd0-b208a1565667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266503745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.4266503745
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3008425919
Short name T760
Test name
Test status
Simulation time 63040779 ps
CPU time 0.63 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:43 PM PDT 24
Peak memory 204452 kb
Host smart-f156ec05-3b2d-42e0-ad03-11c5d253dd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008425919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3008425919
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.220194986
Short name T1437
Test name
Test status
Simulation time 164408974 ps
CPU time 1.53 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 213436 kb
Host smart-0a7afaa6-a343-49ad-b1a9-db08f13a0497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220194986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.220194986
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3896204480
Short name T1378
Test name
Test status
Simulation time 489429598 ps
CPU time 19.51 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 286396 kb
Host smart-2142f33e-ef93-40e8-9f82-900dbbae75f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896204480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3896204480
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1605775108
Short name T1157
Test name
Test status
Simulation time 1832641892 ps
CPU time 48.8 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:26:29 PM PDT 24
Peak memory 576000 kb
Host smart-08821594-5371-43f0-a5fe-fc332abb3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605775108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1605775108
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.4246113821
Short name T1035
Test name
Test status
Simulation time 2361771105 ps
CPU time 81.03 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 796016 kb
Host smart-bfbd0d0b-1532-4741-8ce2-e5d0bdd99096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246113821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.4246113821
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1001375653
Short name T582
Test name
Test status
Simulation time 397734029 ps
CPU time 1.02 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 205116 kb
Host smart-20da3956-7303-4a71-847f-726f7f4eb992
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001375653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1001375653
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3435286910
Short name T166
Test name
Test status
Simulation time 701425669 ps
CPU time 10.74 seconds
Started Jul 12 05:25:36 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 241112 kb
Host smart-9dacacac-fe79-4968-aa9d-8620a53df3f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435286910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3435286910
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4050223907
Short name T349
Test name
Test status
Simulation time 2786601070 ps
CPU time 168.3 seconds
Started Jul 12 05:25:38 PM PDT 24
Finished Jul 12 05:28:27 PM PDT 24
Peak memory 844140 kb
Host smart-e07f3e79-bdc2-45ce-aa7f-5de98652744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050223907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4050223907
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2922651057
Short name T836
Test name
Test status
Simulation time 368667851 ps
CPU time 5.94 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:51 PM PDT 24
Peak memory 205204 kb
Host smart-911904d4-9b20-48b0-8d0a-4a9365d1660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922651057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2922651057
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.4194211910
Short name T78
Test name
Test status
Simulation time 31546910 ps
CPU time 0.67 seconds
Started Jul 12 05:25:39 PM PDT 24
Finished Jul 12 05:25:40 PM PDT 24
Peak memory 204948 kb
Host smart-001556b2-7bc5-4dcf-b7b9-534f5fe16717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194211910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4194211910
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.85522139
Short name T1334
Test name
Test status
Simulation time 3464268024 ps
CPU time 21.61 seconds
Started Jul 12 05:25:40 PM PDT 24
Finished Jul 12 05:26:02 PM PDT 24
Peak memory 223920 kb
Host smart-fccf0695-a54c-47af-9121-08f9d2420091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85522139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.85522139
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.3512360720
Short name T638
Test name
Test status
Simulation time 890873906 ps
CPU time 28.59 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:26:13 PM PDT 24
Peak memory 205144 kb
Host smart-b79aeb92-166f-4a77-a08d-13fd204ec02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512360720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.3512360720
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.4066641519
Short name T1023
Test name
Test status
Simulation time 2202969487 ps
CPU time 113.28 seconds
Started Jul 12 05:25:35 PM PDT 24
Finished Jul 12 05:27:29 PM PDT 24
Peak memory 380156 kb
Host smart-cc4379e2-cce6-4164-b248-3086700e58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066641519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.4066641519
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1360050680
Short name T442
Test name
Test status
Simulation time 8274815015 ps
CPU time 37.05 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:26:23 PM PDT 24
Peak memory 213596 kb
Host smart-29e5291e-d84a-4f8a-8773-f4bba1f09c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360050680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1360050680
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1259383610
Short name T1012
Test name
Test status
Simulation time 2356404747 ps
CPU time 5.63 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 213692 kb
Host smart-538eeb7e-0383-4df2-816c-c2ce0a1cd3f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259383610 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1259383610
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.4026009065
Short name T177
Test name
Test status
Simulation time 287631695 ps
CPU time 1.86 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:44 PM PDT 24
Peak memory 205696 kb
Host smart-f5e8ddbd-e95a-466c-86ad-861ebd3f1524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026009065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.4026009065
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2375986753
Short name T861
Test name
Test status
Simulation time 183428918 ps
CPU time 1.2 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 205328 kb
Host smart-6252ab3f-388b-42dd-a858-c5ad31a0e4a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375986753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2375986753
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.3557388376
Short name T961
Test name
Test status
Simulation time 1213226813 ps
CPU time 3.09 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 205464 kb
Host smart-96af49f6-5765-414e-acbb-dedef5a14f62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557388376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.3557388376
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1097719133
Short name T1369
Test name
Test status
Simulation time 117590776 ps
CPU time 1.24 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 205320 kb
Host smart-6c090a7a-c702-4549-97fb-10ab44a0f005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097719133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1097719133
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1976536070
Short name T605
Test name
Test status
Simulation time 5926822001 ps
CPU time 8.16 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 222540 kb
Host smart-d5cec273-24f4-45bc-8f7d-1f698b5780b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976536070 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1976536070
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.79539867
Short name T1439
Test name
Test status
Simulation time 14935061259 ps
CPU time 314 seconds
Started Jul 12 05:25:47 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 3740644 kb
Host smart-562cae31-9ba6-4c99-81cc-11de814a37e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79539867 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.79539867
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.3047216928
Short name T671
Test name
Test status
Simulation time 2414715490 ps
CPU time 3 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 213736 kb
Host smart-aefaf3cc-c684-4867-84aa-2b4daee0805a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047216928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.3047216928
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.3845879662
Short name T1368
Test name
Test status
Simulation time 1902575253 ps
CPU time 2.71 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:45 PM PDT 24
Peak memory 205360 kb
Host smart-2e50fe32-acba-4073-a2f0-7ec785775f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845879662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.3845879662
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.1888731981
Short name T607
Test name
Test status
Simulation time 1692160139 ps
CPU time 2.02 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 205308 kb
Host smart-548b484a-3321-4e87-afa2-175b1b9e9de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888731981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.1888731981
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1484744393
Short name T465
Test name
Test status
Simulation time 3349792406 ps
CPU time 9.6 seconds
Started Jul 12 05:25:45 PM PDT 24
Finished Jul 12 05:25:57 PM PDT 24
Peak memory 213696 kb
Host smart-ca505c33-9f73-4b6b-8e15-8b22b867f6f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484744393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1484744393
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.520399699
Short name T351
Test name
Test status
Simulation time 6302462601 ps
CPU time 75.9 seconds
Started Jul 12 05:25:43 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 218632 kb
Host smart-ec1cbaf0-f90c-4505-9527-eb9d9004b613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520399699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.520399699
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3693589450
Short name T915
Test name
Test status
Simulation time 57819986184 ps
CPU time 104.46 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 1274120 kb
Host smart-255e9575-da40-4da3-aaa2-cb463cb23d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693589450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3693589450
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3681155703
Short name T1141
Test name
Test status
Simulation time 794164734 ps
CPU time 2.24 seconds
Started Jul 12 05:25:45 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 205232 kb
Host smart-9bf5d555-2cba-4cae-913d-7da52f3f184c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681155703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3681155703
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.239643349
Short name T1519
Test name
Test status
Simulation time 5069973840 ps
CPU time 7.07 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:25:51 PM PDT 24
Peak memory 213960 kb
Host smart-b935aff4-6754-4325-ad35-76b4014d6134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239643349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.239643349
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.1099057132
Short name T1456
Test name
Test status
Simulation time 152813960 ps
CPU time 3.04 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 205416 kb
Host smart-a6b7ed08-bc39-4636-a38b-07e2b9709c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099057132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.1099057132
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4166840963
Short name T592
Test name
Test status
Simulation time 50671128 ps
CPU time 0.72 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:25:55 PM PDT 24
Peak memory 204688 kb
Host smart-3c9c81db-80c6-445e-a2e7-bf4c04807854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166840963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4166840963
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.4218310603
Short name T975
Test name
Test status
Simulation time 988270603 ps
CPU time 4.57 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:25:59 PM PDT 24
Peak memory 234848 kb
Host smart-cabf60cf-c2f2-4b3d-9d09-098a5328bb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218310603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.4218310603
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3577199684
Short name T45
Test name
Test status
Simulation time 205544585 ps
CPU time 4.01 seconds
Started Jul 12 05:25:41 PM PDT 24
Finished Jul 12 05:25:46 PM PDT 24
Peak memory 246520 kb
Host smart-acf53aa1-6720-4dad-8019-a4992da36b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577199684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3577199684
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1372767368
Short name T788
Test name
Test status
Simulation time 3990699709 ps
CPU time 133.53 seconds
Started Jul 12 05:25:50 PM PDT 24
Finished Jul 12 05:28:04 PM PDT 24
Peak memory 685016 kb
Host smart-c39df27b-335c-4be3-8f4e-5d0cfe18616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372767368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1372767368
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3056971704
Short name T1446
Test name
Test status
Simulation time 5338255397 ps
CPU time 35.04 seconds
Started Jul 12 05:25:46 PM PDT 24
Finished Jul 12 05:26:23 PM PDT 24
Peak memory 508404 kb
Host smart-5e827cd2-2534-43e2-a833-3e7a83493f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056971704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3056971704
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2936144622
Short name T574
Test name
Test status
Simulation time 163228882 ps
CPU time 1.35 seconds
Started Jul 12 05:25:45 PM PDT 24
Finished Jul 12 05:25:48 PM PDT 24
Peak memory 205132 kb
Host smart-33096d8e-ef30-4453-b11a-9c93d439ae70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936144622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2936144622
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3776382970
Short name T1300
Test name
Test status
Simulation time 609244020 ps
CPU time 2.96 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 205308 kb
Host smart-661a34b7-abd0-439d-9f59-a3aeea136f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776382970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3776382970
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.658040240
Short name T920
Test name
Test status
Simulation time 5354008070 ps
CPU time 161.57 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 820008 kb
Host smart-045f6b43-001a-498a-a00b-9c2ecd98cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658040240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.658040240
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3022124631
Short name T706
Test name
Test status
Simulation time 2047383613 ps
CPU time 7.17 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:25:59 PM PDT 24
Peak memory 205200 kb
Host smart-74df2d49-b197-466c-b5f6-adca06c8f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022124631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3022124631
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_override.1775371970
Short name T1401
Test name
Test status
Simulation time 28329029 ps
CPU time 0.71 seconds
Started Jul 12 05:25:44 PM PDT 24
Finished Jul 12 05:25:46 PM PDT 24
Peak memory 205036 kb
Host smart-da712949-d9ad-462e-8b01-d366fb630245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775371970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1775371970
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.396989171
Short name T864
Test name
Test status
Simulation time 361906896 ps
CPU time 11.62 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:25:55 PM PDT 24
Peak memory 229624 kb
Host smart-ff01edb2-a9dd-416d-93dc-8fc2de2a2c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396989171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.396989171
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.3949483617
Short name T1041
Test name
Test status
Simulation time 214559587 ps
CPU time 2.87 seconds
Started Jul 12 05:25:45 PM PDT 24
Finished Jul 12 05:25:50 PM PDT 24
Peak memory 218136 kb
Host smart-c9999e11-bbaa-4ae0-b552-d06cf49f28bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949483617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3949483617
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1637828491
Short name T1240
Test name
Test status
Simulation time 8816987381 ps
CPU time 94.94 seconds
Started Jul 12 05:25:42 PM PDT 24
Finished Jul 12 05:27:18 PM PDT 24
Peak memory 366776 kb
Host smart-fd4c27a1-4168-49bc-b594-d8eb057fc7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637828491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1637828491
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3453835968
Short name T1392
Test name
Test status
Simulation time 853052736 ps
CPU time 12.88 seconds
Started Jul 12 05:25:53 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 229772 kb
Host smart-5840769f-2d09-4302-8b47-37fec36f25d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453835968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3453835968
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1366777929
Short name T549
Test name
Test status
Simulation time 822205149 ps
CPU time 5.4 seconds
Started Jul 12 05:25:49 PM PDT 24
Finished Jul 12 05:25:55 PM PDT 24
Peak memory 221348 kb
Host smart-98151eea-371c-492f-8089-4908782e4f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366777929 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1366777929
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3598855869
Short name T746
Test name
Test status
Simulation time 1196705245 ps
CPU time 1.24 seconds
Started Jul 12 05:25:50 PM PDT 24
Finished Jul 12 05:25:52 PM PDT 24
Peak memory 205336 kb
Host smart-05b4f5ac-8086-40b1-9b8b-5b66fb8a7eef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598855869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3598855869
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3943241591
Short name T1495
Test name
Test status
Simulation time 99498080 ps
CPU time 0.9 seconds
Started Jul 12 05:25:53 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 205208 kb
Host smart-530bf6c0-019e-48c9-b944-77fc1b6e789e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943241591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3943241591
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.3317360274
Short name T174
Test name
Test status
Simulation time 919104754 ps
CPU time 2.32 seconds
Started Jul 12 05:25:50 PM PDT 24
Finished Jul 12 05:25:53 PM PDT 24
Peak memory 205312 kb
Host smart-dc23c397-10a3-482a-8a5f-74795805345a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317360274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.3317360274
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2502262739
Short name T519
Test name
Test status
Simulation time 229499516 ps
CPU time 1.22 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 205264 kb
Host smart-fdf6977f-8a34-4210-ae7c-7619d0c47afd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502262739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2502262739
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2784608378
Short name T1470
Test name
Test status
Simulation time 1595067746 ps
CPU time 8.41 seconds
Started Jul 12 05:25:50 PM PDT 24
Finished Jul 12 05:25:59 PM PDT 24
Peak memory 223664 kb
Host smart-e929dd4b-0f81-4792-ba1e-c02907ddac04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784608378 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2784608378
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2103832195
Short name T628
Test name
Test status
Simulation time 9283342926 ps
CPU time 21.17 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 659688 kb
Host smart-c4e00e55-e1de-455e-ba86-877e0855d27e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103832195 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2103832195
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.2902948647
Short name T902
Test name
Test status
Simulation time 5590908693 ps
CPU time 2.56 seconds
Started Jul 12 05:25:51 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 213704 kb
Host smart-3ee94924-39da-4dd3-856d-beea82936e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902948647 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.2902948647
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.3945258418
Short name T299
Test name
Test status
Simulation time 489179873 ps
CPU time 2.8 seconds
Started Jul 12 05:25:50 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 205396 kb
Host smart-2150d2e8-0cde-49bf-b89e-12e3e5e07071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945258418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.3945258418
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.3705380219
Short name T573
Test name
Test status
Simulation time 472174079 ps
CPU time 2.34 seconds
Started Jul 12 05:25:48 PM PDT 24
Finished Jul 12 05:25:51 PM PDT 24
Peak memory 205532 kb
Host smart-f1851829-9f94-4a68-8ea5-6c9af09b4702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705380219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.3705380219
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.280567282
Short name T306
Test name
Test status
Simulation time 17966735682 ps
CPU time 18.37 seconds
Started Jul 12 05:25:51 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 213696 kb
Host smart-8620714b-5117-46f3-a091-1e21f3ae984e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280567282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.280567282
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4003441268
Short name T1523
Test name
Test status
Simulation time 824844593 ps
CPU time 6.62 seconds
Started Jul 12 05:25:49 PM PDT 24
Finished Jul 12 05:25:56 PM PDT 24
Peak memory 205328 kb
Host smart-dde8f4b4-e5f1-4d26-ac0d-8ebd1e4de592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003441268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4003441268
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.493017750
Short name T127
Test name
Test status
Simulation time 9029062802 ps
CPU time 20.18 seconds
Started Jul 12 05:25:53 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 205532 kb
Host smart-7a9a3c68-f1c5-479c-88ea-12261aafb15a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493017750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.493017750
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.497104583
Short name T705
Test name
Test status
Simulation time 807471687 ps
CPU time 9.82 seconds
Started Jul 12 05:25:56 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 343140 kb
Host smart-57dc4b41-d9d2-473d-8979-d90dcae18cc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497104583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.497104583
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.524031237
Short name T496
Test name
Test status
Simulation time 3914891745 ps
CPU time 6.61 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 221952 kb
Host smart-8dff21b3-f871-4913-8f4b-f77c530abf47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524031237 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.524031237
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.992639005
Short name T1563
Test name
Test status
Simulation time 726089074 ps
CPU time 10.59 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 206468 kb
Host smart-5cb247a1-423a-4b28-bcb7-a13b133b9ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992639005 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.992639005
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2260543793
Short name T393
Test name
Test status
Simulation time 33061939 ps
CPU time 0.64 seconds
Started Jul 12 05:19:46 PM PDT 24
Finished Jul 12 05:19:48 PM PDT 24
Peak memory 204728 kb
Host smart-1fe65956-fd83-4d65-a400-2a1540acc621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260543793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2260543793
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3218093028
Short name T964
Test name
Test status
Simulation time 237906785 ps
CPU time 1.58 seconds
Started Jul 12 05:19:26 PM PDT 24
Finished Jul 12 05:19:28 PM PDT 24
Peak memory 213576 kb
Host smart-64626578-debc-4e07-8f45-2e0cd7e71e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218093028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3218093028
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.599274194
Short name T1246
Test name
Test status
Simulation time 1325369890 ps
CPU time 8.75 seconds
Started Jul 12 05:19:23 PM PDT 24
Finished Jul 12 05:19:32 PM PDT 24
Peak memory 289496 kb
Host smart-aa61bb57-115f-4911-8b4a-3662abcad00b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599274194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.599274194
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.941059937
Short name T85
Test name
Test status
Simulation time 6055927448 ps
CPU time 120.23 seconds
Started Jul 12 05:19:19 PM PDT 24
Finished Jul 12 05:21:20 PM PDT 24
Peak memory 597840 kb
Host smart-2fd930cb-d117-4eda-bbb5-a6bc1ab7eb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941059937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.941059937
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1517061862
Short name T797
Test name
Test status
Simulation time 11865471905 ps
CPU time 49.51 seconds
Started Jul 12 05:19:22 PM PDT 24
Finished Jul 12 05:20:13 PM PDT 24
Peak memory 622400 kb
Host smart-e6fbbb22-d7ff-4a80-b4a4-f126911f79c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517061862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1517061862
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3073860284
Short name T1088
Test name
Test status
Simulation time 541866412 ps
CPU time 0.99 seconds
Started Jul 12 05:19:18 PM PDT 24
Finished Jul 12 05:19:19 PM PDT 24
Peak memory 205084 kb
Host smart-e2b979ae-08f2-4ae5-973e-7dd7e7070dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073860284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3073860284
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2241667281
Short name T138
Test name
Test status
Simulation time 224042934 ps
CPU time 5.64 seconds
Started Jul 12 05:19:21 PM PDT 24
Finished Jul 12 05:19:27 PM PDT 24
Peak memory 242792 kb
Host smart-63ac2be9-8a67-4138-99bb-051f45e04e05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241667281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2241667281
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3381678182
Short name T896
Test name
Test status
Simulation time 13450364215 ps
CPU time 82.12 seconds
Started Jul 12 05:19:20 PM PDT 24
Finished Jul 12 05:20:43 PM PDT 24
Peak memory 912956 kb
Host smart-44867d3c-d946-4763-9765-8809fd40034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381678182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3381678182
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1628121036
Short name T399
Test name
Test status
Simulation time 637603683 ps
CPU time 17.9 seconds
Started Jul 12 05:19:35 PM PDT 24
Finished Jul 12 05:19:53 PM PDT 24
Peak memory 205272 kb
Host smart-3e3693eb-25d8-44a2-9682-b27ee3810b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628121036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1628121036
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.1065858800
Short name T877
Test name
Test status
Simulation time 45079874 ps
CPU time 0.66 seconds
Started Jul 12 05:19:21 PM PDT 24
Finished Jul 12 05:19:22 PM PDT 24
Peak memory 205092 kb
Host smart-a1d38b65-ae71-434d-b41d-2d11151bf907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065858800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1065858800
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1187746016
Short name T42
Test name
Test status
Simulation time 51032080079 ps
CPU time 56.91 seconds
Started Jul 12 05:19:23 PM PDT 24
Finished Jul 12 05:20:20 PM PDT 24
Peak memory 221516 kb
Host smart-6ceddafe-31ec-4ef8-81e8-5ef0c1ad0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187746016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1187746016
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.161159176
Short name T838
Test name
Test status
Simulation time 206536019 ps
CPU time 8.34 seconds
Started Jul 12 05:19:31 PM PDT 24
Finished Jul 12 05:19:40 PM PDT 24
Peak memory 225092 kb
Host smart-7dbd2674-023b-435f-b709-ba761bfc453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161159176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.161159176
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3285138875
Short name T37
Test name
Test status
Simulation time 6800125182 ps
CPU time 35.32 seconds
Started Jul 12 05:19:20 PM PDT 24
Finished Jul 12 05:19:56 PM PDT 24
Peak memory 328340 kb
Host smart-3d327cbd-4038-4f51-a78c-8c0d2fc928ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285138875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3285138875
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3454195415
Short name T162
Test name
Test status
Simulation time 5272967446 ps
CPU time 401.22 seconds
Started Jul 12 05:19:28 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 1117140 kb
Host smart-e9960d98-42f4-4e33-9d5e-98cb19a5fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454195415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3454195415
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1922374586
Short name T1394
Test name
Test status
Simulation time 1438267289 ps
CPU time 6.11 seconds
Started Jul 12 05:19:20 PM PDT 24
Finished Jul 12 05:19:26 PM PDT 24
Peak memory 213448 kb
Host smart-de0bbee5-d0da-46f1-85fd-9b4c41056cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922374586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1922374586
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.738273324
Short name T587
Test name
Test status
Simulation time 3360989115 ps
CPU time 3.99 seconds
Started Jul 12 05:19:33 PM PDT 24
Finished Jul 12 05:19:37 PM PDT 24
Peak memory 217916 kb
Host smart-fc3e81c6-c1cc-4cb6-bf28-5fd39ad2db5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738273324 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.738273324
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1255503416
Short name T1556
Test name
Test status
Simulation time 457430014 ps
CPU time 1.4 seconds
Started Jul 12 05:19:28 PM PDT 24
Finished Jul 12 05:19:30 PM PDT 24
Peak memory 205324 kb
Host smart-7944e9eb-5ff8-4854-81a5-ecaec040ea12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255503416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1255503416
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3777380023
Short name T950
Test name
Test status
Simulation time 183654665 ps
CPU time 0.92 seconds
Started Jul 12 05:19:28 PM PDT 24
Finished Jul 12 05:19:29 PM PDT 24
Peak memory 205312 kb
Host smart-ea4b977c-fbf3-42cf-bc07-e13626fa88c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777380023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3777380023
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.1745062081
Short name T889
Test name
Test status
Simulation time 385758976 ps
CPU time 2.43 seconds
Started Jul 12 05:19:33 PM PDT 24
Finished Jul 12 05:19:36 PM PDT 24
Peak memory 205404 kb
Host smart-d5f0a367-da5e-4c08-93ff-7b75e21898ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745062081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.1745062081
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.3873023219
Short name T572
Test name
Test status
Simulation time 145218235 ps
CPU time 1.14 seconds
Started Jul 12 05:19:37 PM PDT 24
Finished Jul 12 05:19:38 PM PDT 24
Peak memory 205312 kb
Host smart-0b699bfd-e92e-43a6-ab2e-12daaae5f381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873023219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.3873023219
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.84687590
Short name T1152
Test name
Test status
Simulation time 1938165092 ps
CPU time 5.83 seconds
Started Jul 12 05:19:24 PM PDT 24
Finished Jul 12 05:19:31 PM PDT 24
Peak memory 221844 kb
Host smart-231cb676-a75f-45c5-bd9a-ffbe984ddc82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84687590 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.84687590
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.578477781
Short name T544
Test name
Test status
Simulation time 422017602 ps
CPU time 2.31 seconds
Started Jul 12 05:19:28 PM PDT 24
Finished Jul 12 05:19:30 PM PDT 24
Peak memory 205628 kb
Host smart-7ab81d01-a42c-4577-a047-e5cd8bd31b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578477781 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.578477781
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.318546563
Short name T168
Test name
Test status
Simulation time 570641980 ps
CPU time 3 seconds
Started Jul 12 05:19:33 PM PDT 24
Finished Jul 12 05:19:36 PM PDT 24
Peak memory 213576 kb
Host smart-f3bdb568-5f89-4804-8bd8-816fc5c17363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318546563 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_nack_acqfull.318546563
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.3183432470
Short name T1486
Test name
Test status
Simulation time 1183444085 ps
CPU time 2.95 seconds
Started Jul 12 05:19:50 PM PDT 24
Finished Jul 12 05:19:54 PM PDT 24
Peak memory 205812 kb
Host smart-04aaf215-ccd7-48f2-968d-7bf481c9c48f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183432470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.3183432470
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.912099846
Short name T375
Test name
Test status
Simulation time 794172376 ps
CPU time 2.23 seconds
Started Jul 12 05:19:33 PM PDT 24
Finished Jul 12 05:19:36 PM PDT 24
Peak memory 205268 kb
Host smart-214dd63e-622b-4606-b215-e0171ad1e9a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912099846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_smbus_maxlen.912099846
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2362131953
Short name T823
Test name
Test status
Simulation time 1750640198 ps
CPU time 19.79 seconds
Started Jul 12 05:19:29 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 213548 kb
Host smart-ae0f5cce-83ef-41f5-a495-6847aee6cba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362131953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2362131953
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.455695730
Short name T1195
Test name
Test status
Simulation time 6430921995 ps
CPU time 13.6 seconds
Started Jul 12 05:19:25 PM PDT 24
Finished Jul 12 05:19:39 PM PDT 24
Peak memory 216652 kb
Host smart-9c31ca50-4b5c-4745-aeaf-1223ec54328f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455695730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.455695730
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3396266669
Short name T1271
Test name
Test status
Simulation time 39294563531 ps
CPU time 627.84 seconds
Started Jul 12 05:19:24 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 4885136 kb
Host smart-c2af0b9b-cfbf-466e-b786-d2674b7b4e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396266669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3396266669
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3464376300
Short name T396
Test name
Test status
Simulation time 259230886 ps
CPU time 1.01 seconds
Started Jul 12 05:19:25 PM PDT 24
Finished Jul 12 05:19:26 PM PDT 24
Peak memory 205296 kb
Host smart-94c4ff1c-c29c-4dda-ac12-08b0b0efbd92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464376300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3464376300
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3047456979
Short name T1103
Test name
Test status
Simulation time 4014697898 ps
CPU time 7.7 seconds
Started Jul 12 05:19:26 PM PDT 24
Finished Jul 12 05:19:35 PM PDT 24
Peak memory 230060 kb
Host smart-d768ee7e-3ad4-4182-b3fb-f8617be61c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047456979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3047456979
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.2213762046
Short name T1236
Test name
Test status
Simulation time 236138489 ps
CPU time 3.38 seconds
Started Jul 12 05:19:32 PM PDT 24
Finished Jul 12 05:19:36 PM PDT 24
Peak memory 205364 kb
Host smart-36ceb6ff-628d-4136-9f0b-a5c008f74f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213762046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2213762046
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2860959662
Short name T173
Test name
Test status
Simulation time 17831256 ps
CPU time 0.65 seconds
Started Jul 12 05:19:48 PM PDT 24
Finished Jul 12 05:19:50 PM PDT 24
Peak memory 204608 kb
Host smart-a5b6bbbe-993a-4a8f-9cca-ad938ea82b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860959662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2860959662
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.4019447549
Short name T1013
Test name
Test status
Simulation time 115739166 ps
CPU time 1.28 seconds
Started Jul 12 05:19:41 PM PDT 24
Finished Jul 12 05:19:42 PM PDT 24
Peak memory 213544 kb
Host smart-90e3e9e5-df5e-4c7a-83a8-c0d749e95e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019447549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.4019447549
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.4141592563
Short name T1210
Test name
Test status
Simulation time 885311017 ps
CPU time 8.21 seconds
Started Jul 12 05:19:40 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 298992 kb
Host smart-fd5338f8-3d14-4bd7-9008-480a40a18ff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141592563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.4141592563
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.389876453
Short name T857
Test name
Test status
Simulation time 10253470132 ps
CPU time 110.16 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:21:30 PM PDT 24
Peak memory 543096 kb
Host smart-3762bd73-9fcc-4fdb-9c72-df5dd17ae362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389876453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.389876453
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.7307773
Short name T1228
Test name
Test status
Simulation time 6283425045 ps
CPU time 107.15 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 568364 kb
Host smart-b408dfcd-179c-45eb-a4ad-76a0b40d8794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7307773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.7307773
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1754397396
Short name T254
Test name
Test status
Simulation time 139873412 ps
CPU time 1.33 seconds
Started Jul 12 05:20:03 PM PDT 24
Finished Jul 12 05:20:05 PM PDT 24
Peak memory 205084 kb
Host smart-0c33faf7-7d3b-45ac-9714-0f787603bec7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754397396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1754397396
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2204875255
Short name T247
Test name
Test status
Simulation time 284678119 ps
CPU time 3.52 seconds
Started Jul 12 05:19:42 PM PDT 24
Finished Jul 12 05:19:46 PM PDT 24
Peak memory 205324 kb
Host smart-484ae7f4-4476-4319-96fa-b13efeb11b38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204875255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2204875255
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1003250028
Short name T1199
Test name
Test status
Simulation time 10253800586 ps
CPU time 172.61 seconds
Started Jul 12 05:19:41 PM PDT 24
Finished Jul 12 05:22:34 PM PDT 24
Peak memory 845820 kb
Host smart-6baeb2da-8d3d-4182-8f83-8dd3fd94324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003250028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1003250028
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2253282191
Short name T1200
Test name
Test status
Simulation time 843473504 ps
CPU time 8.86 seconds
Started Jul 12 05:19:50 PM PDT 24
Finished Jul 12 05:20:00 PM PDT 24
Peak memory 205280 kb
Host smart-632cae2e-d317-4982-8102-1aa293dd10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253282191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2253282191
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_override.2742606052
Short name T151
Test name
Test status
Simulation time 27357616 ps
CPU time 0.67 seconds
Started Jul 12 05:20:27 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 205072 kb
Host smart-7a571bc5-2b74-44fd-a033-a3584cf054f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742606052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2742606052
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.4221986460
Short name T1203
Test name
Test status
Simulation time 12496316037 ps
CPU time 63.3 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:20:43 PM PDT 24
Peak memory 670552 kb
Host smart-290577d1-bfea-4050-9e85-0598922f4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221986460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.4221986460
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1862941375
Short name T662
Test name
Test status
Simulation time 652393921 ps
CPU time 6.76 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:19:46 PM PDT 24
Peak memory 205076 kb
Host smart-c65ebd0b-bd64-4929-b83c-b3c65ad07804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862941375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1862941375
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3060610341
Short name T919
Test name
Test status
Simulation time 1570564783 ps
CPU time 25.32 seconds
Started Jul 12 05:19:38 PM PDT 24
Finished Jul 12 05:20:04 PM PDT 24
Peak memory 327564 kb
Host smart-a29ad9af-6d5e-46f8-88e8-77244b7760fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060610341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3060610341
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.930129239
Short name T133
Test name
Test status
Simulation time 60811206628 ps
CPU time 540.32 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 1536444 kb
Host smart-fcfeba57-4ce0-4c4e-b6aa-07b8d7c62393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930129239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.930129239
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1040233681
Short name T1468
Test name
Test status
Simulation time 3020844942 ps
CPU time 35.83 seconds
Started Jul 12 05:19:41 PM PDT 24
Finished Jul 12 05:20:18 PM PDT 24
Peak memory 213572 kb
Host smart-9b460dcb-eabe-4d1b-a5d4-2fe00c1769fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040233681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1040233681
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2110715529
Short name T1385
Test name
Test status
Simulation time 651516680 ps
CPU time 3.3 seconds
Started Jul 12 05:19:48 PM PDT 24
Finished Jul 12 05:19:53 PM PDT 24
Peak memory 217612 kb
Host smart-b7bea52c-dce8-4a0e-9adb-abce209ec71c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110715529 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2110715529
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.397981393
Short name T180
Test name
Test status
Simulation time 346946474 ps
CPU time 1.56 seconds
Started Jul 12 05:19:52 PM PDT 24
Finished Jul 12 05:19:55 PM PDT 24
Peak memory 205292 kb
Host smart-25244f25-8afd-40c5-94c5-8ed0ad2780f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397981393 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.397981393
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2026910004
Short name T1503
Test name
Test status
Simulation time 122215477 ps
CPU time 0.99 seconds
Started Jul 12 05:19:47 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 205336 kb
Host smart-f4c948e0-a649-4444-a8a8-7ae4425efd3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026910004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2026910004
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.4282960668
Short name T347
Test name
Test status
Simulation time 449579068 ps
CPU time 2.76 seconds
Started Jul 12 05:19:49 PM PDT 24
Finished Jul 12 05:19:52 PM PDT 24
Peak memory 205416 kb
Host smart-7202e1d4-a813-4174-a023-15b042a53170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282960668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.4282960668
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2287975659
Short name T1549
Test name
Test status
Simulation time 619972186 ps
CPU time 1.15 seconds
Started Jul 12 05:19:46 PM PDT 24
Finished Jul 12 05:19:48 PM PDT 24
Peak memory 205320 kb
Host smart-35da214d-1ee3-45c8-b97e-4899d6243e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287975659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2287975659
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2189817045
Short name T851
Test name
Test status
Simulation time 1412203317 ps
CPU time 9.01 seconds
Started Jul 12 05:19:41 PM PDT 24
Finished Jul 12 05:19:50 PM PDT 24
Peak memory 218444 kb
Host smart-b9bb16fc-2597-4334-85ae-a107d0418b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189817045 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2189817045
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.984521067
Short name T1338
Test name
Test status
Simulation time 9350000076 ps
CPU time 13.57 seconds
Started Jul 12 05:19:41 PM PDT 24
Finished Jul 12 05:19:55 PM PDT 24
Peak memory 337880 kb
Host smart-d8b28006-ad48-402f-a2be-64dff4d923f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984521067 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.984521067
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.990849891
Short name T696
Test name
Test status
Simulation time 431186647 ps
CPU time 2.64 seconds
Started Jul 12 05:19:50 PM PDT 24
Finished Jul 12 05:19:53 PM PDT 24
Peak memory 213672 kb
Host smart-3b2bc18c-e1b5-4576-9e4f-09484868cca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990849891 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_nack_acqfull.990849891
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.2765147526
Short name T603
Test name
Test status
Simulation time 2290685031 ps
CPU time 2.68 seconds
Started Jul 12 05:19:46 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 205492 kb
Host smart-c3d2e277-3af4-4827-8204-450fc874db82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765147526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.2765147526
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.1928204261
Short name T394
Test name
Test status
Simulation time 434587118 ps
CPU time 2.26 seconds
Started Jul 12 05:19:52 PM PDT 24
Finished Jul 12 05:19:55 PM PDT 24
Peak memory 205288 kb
Host smart-6082d380-57ad-4132-b562-95e3cb8d520d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928204261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.1928204261
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2624186428
Short name T160
Test name
Test status
Simulation time 5848753660 ps
CPU time 15.84 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:19:56 PM PDT 24
Peak memory 213728 kb
Host smart-823cb5f4-60b9-4266-b790-59702843ada6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624186428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2624186428
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2293745725
Short name T1381
Test name
Test status
Simulation time 625499387 ps
CPU time 28.86 seconds
Started Jul 12 05:19:40 PM PDT 24
Finished Jul 12 05:20:10 PM PDT 24
Peak memory 213664 kb
Host smart-d787fe7d-d617-42a1-aa91-618a81247699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293745725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2293745725
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2774092790
Short name T954
Test name
Test status
Simulation time 12723817834 ps
CPU time 23.13 seconds
Started Jul 12 05:19:42 PM PDT 24
Finished Jul 12 05:20:05 PM PDT 24
Peak memory 205496 kb
Host smart-916c004d-0efb-4145-9325-cd8e6ffd73b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774092790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2774092790
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2205989819
Short name T1412
Test name
Test status
Simulation time 2768212541 ps
CPU time 27.22 seconds
Started Jul 12 05:19:39 PM PDT 24
Finished Jul 12 05:20:07 PM PDT 24
Peak memory 487136 kb
Host smart-e52d4fc4-a8a8-4d0c-9fea-75d358595081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205989819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2205989819
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3456130068
Short name T381
Test name
Test status
Simulation time 1305555491 ps
CPU time 7.05 seconds
Started Jul 12 05:19:42 PM PDT 24
Finished Jul 12 05:19:50 PM PDT 24
Peak memory 221800 kb
Host smart-22a7a531-159c-4d03-90c6-bbe52e48091f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456130068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3456130068
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2810350806
Short name T195
Test name
Test status
Simulation time 28129408 ps
CPU time 0.67 seconds
Started Jul 12 05:20:05 PM PDT 24
Finished Jul 12 05:20:07 PM PDT 24
Peak memory 204660 kb
Host smart-e4659002-b3d5-4800-91e1-c6eb62959477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810350806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2810350806
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1968483795
Short name T33
Test name
Test status
Simulation time 226809172 ps
CPU time 1.46 seconds
Started Jul 12 05:19:58 PM PDT 24
Finished Jul 12 05:20:00 PM PDT 24
Peak memory 213492 kb
Host smart-bd577263-03c7-493d-8000-acc60e5e0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968483795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1968483795
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1161230807
Short name T1333
Test name
Test status
Simulation time 614346906 ps
CPU time 6 seconds
Started Jul 12 05:19:57 PM PDT 24
Finished Jul 12 05:20:04 PM PDT 24
Peak memory 269836 kb
Host smart-246b6618-f369-4adf-a3c7-2e39843c8251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161230807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1161230807
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3461636121
Short name T1208
Test name
Test status
Simulation time 3312977425 ps
CPU time 80.43 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 777572 kb
Host smart-bba988b1-fd0e-4387-b58b-40f6eb465b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461636121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3461636121
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1997734817
Short name T422
Test name
Test status
Simulation time 11517606107 ps
CPU time 168.91 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 719284 kb
Host smart-16dda880-393d-4f2f-9c87-098e40569f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997734817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1997734817
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3063196357
Short name T1148
Test name
Test status
Simulation time 308340123 ps
CPU time 1.11 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:19:58 PM PDT 24
Peak memory 205124 kb
Host smart-a668fedf-2759-4a33-bf50-734e44e37b69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063196357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3063196357
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2397432170
Short name T1521
Test name
Test status
Simulation time 211224309 ps
CPU time 3.04 seconds
Started Jul 12 05:19:53 PM PDT 24
Finished Jul 12 05:19:56 PM PDT 24
Peak memory 205524 kb
Host smart-d07bdbfd-d218-48be-8911-efde4d6ac1c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397432170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2397432170
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1872581256
Short name T117
Test name
Test status
Simulation time 4978039387 ps
CPU time 131.56 seconds
Started Jul 12 05:19:56 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 1408840 kb
Host smart-f7b26b3d-60ec-4a60-9a68-93e6b2c094e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872581256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1872581256
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3541271612
Short name T320
Test name
Test status
Simulation time 1483727870 ps
CPU time 4.16 seconds
Started Jul 12 05:19:52 PM PDT 24
Finished Jul 12 05:19:57 PM PDT 24
Peak memory 205208 kb
Host smart-bf8836f8-8af6-4c17-b6c8-01dc0bb121fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541271612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3541271612
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.4196796554
Short name T1552
Test name
Test status
Simulation time 19360676 ps
CPU time 0.71 seconds
Started Jul 12 05:19:47 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 205084 kb
Host smart-d9ca90c4-48ac-4e85-909a-da34908fe7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196796554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.4196796554
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2774510111
Short name T468
Test name
Test status
Simulation time 6351701634 ps
CPU time 59.97 seconds
Started Jul 12 05:19:52 PM PDT 24
Finished Jul 12 05:20:52 PM PDT 24
Peak memory 205260 kb
Host smart-6a84d173-a09e-42a8-a778-d0f4d8de24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774510111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2774510111
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.3115764317
Short name T243
Test name
Test status
Simulation time 2405936686 ps
CPU time 94.28 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:21:31 PM PDT 24
Peak memory 205140 kb
Host smart-6a94f77c-6967-4a58-833b-b0f99e449209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115764317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.3115764317
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.521397216
Short name T435
Test name
Test status
Simulation time 2574138306 ps
CPU time 59.72 seconds
Started Jul 12 05:19:47 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 313312 kb
Host smart-3f54d9b9-0970-41ce-a9ef-3b3498c003b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521397216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.521397216
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.800393204
Short name T291
Test name
Test status
Simulation time 83189309581 ps
CPU time 1013.87 seconds
Started Jul 12 05:19:54 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 2961512 kb
Host smart-054fa85d-1e08-4149-aced-d7d3d21c558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800393204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.800393204
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1267931926
Short name T752
Test name
Test status
Simulation time 2196719847 ps
CPU time 11.05 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:20:07 PM PDT 24
Peak memory 221580 kb
Host smart-ecc2760b-f511-43fa-b0b2-f79416136831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267931926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1267931926
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2907138602
Short name T1287
Test name
Test status
Simulation time 870627350 ps
CPU time 5.04 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:20:02 PM PDT 24
Peak memory 213604 kb
Host smart-c5d402f7-46ad-448e-94e4-5616001d7b4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907138602 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2907138602
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2617897003
Short name T581
Test name
Test status
Simulation time 697344172 ps
CPU time 0.97 seconds
Started Jul 12 05:20:00 PM PDT 24
Finished Jul 12 05:20:02 PM PDT 24
Peak memory 205304 kb
Host smart-b00d9626-df23-4e34-8ca9-79b8d4db7928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617897003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2617897003
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.4090366916
Short name T799
Test name
Test status
Simulation time 276509305 ps
CPU time 1.69 seconds
Started Jul 12 05:20:00 PM PDT 24
Finished Jul 12 05:20:02 PM PDT 24
Peak memory 209516 kb
Host smart-154cb466-c5e6-4dc0-8391-31a7ca7cf93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090366916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.4090366916
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.476103125
Short name T563
Test name
Test status
Simulation time 525168427 ps
CPU time 1.88 seconds
Started Jul 12 05:20:03 PM PDT 24
Finished Jul 12 05:20:06 PM PDT 24
Peak memory 205308 kb
Host smart-5726f7cb-57ef-45b8-8ffc-d17a87a69b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476103125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.476103125
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.3214653349
Short name T350
Test name
Test status
Simulation time 126714240 ps
CPU time 0.94 seconds
Started Jul 12 05:20:00 PM PDT 24
Finished Jul 12 05:20:02 PM PDT 24
Peak memory 205336 kb
Host smart-b9639b45-eea5-4049-9a1c-85ded568e813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214653349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.3214653349
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2255482482
Short name T634
Test name
Test status
Simulation time 950217512 ps
CPU time 5.96 seconds
Started Jul 12 05:19:54 PM PDT 24
Finished Jul 12 05:20:01 PM PDT 24
Peak memory 219920 kb
Host smart-652d6be6-c994-4e2f-a08c-44e5ace8035f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255482482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2255482482
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.769554709
Short name T554
Test name
Test status
Simulation time 12545895117 ps
CPU time 85.58 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:21:21 PM PDT 24
Peak memory 1584472 kb
Host smart-868d7220-f606-40aa-ad94-205c30ab6d7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769554709 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.769554709
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.142846431
Short name T640
Test name
Test status
Simulation time 476715457 ps
CPU time 3.01 seconds
Started Jul 12 05:20:05 PM PDT 24
Finished Jul 12 05:20:10 PM PDT 24
Peak memory 213580 kb
Host smart-bf96f40e-d1f1-43a0-b2a0-8ecc20ca5470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142846431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_nack_acqfull.142846431
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.2232373920
Short name T170
Test name
Test status
Simulation time 977722518 ps
CPU time 2.51 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:08 PM PDT 24
Peak memory 205408 kb
Host smart-f08e202e-9045-459d-9f58-19cf279db4f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232373920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.2232373920
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.1151831271
Short name T507
Test name
Test status
Simulation time 2112240942 ps
CPU time 2.05 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:07 PM PDT 24
Peak memory 205224 kb
Host smart-860b045d-d70b-4792-bf49-bdb781c5c8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151831271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.1151831271
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2231961468
Short name T514
Test name
Test status
Simulation time 1420862570 ps
CPU time 8.09 seconds
Started Jul 12 05:19:56 PM PDT 24
Finished Jul 12 05:20:05 PM PDT 24
Peak memory 206756 kb
Host smart-f3c4c7af-fd15-41d3-bd5d-89e1b1809fa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231961468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2231961468
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.4205854404
Short name T337
Test name
Test status
Simulation time 359847443 ps
CPU time 13.61 seconds
Started Jul 12 05:19:53 PM PDT 24
Finished Jul 12 05:20:07 PM PDT 24
Peak memory 205460 kb
Host smart-b36d39cd-fcd6-4c56-8e71-4d7ff0659ca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205854404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.4205854404
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2283349110
Short name T1168
Test name
Test status
Simulation time 17946679379 ps
CPU time 32.57 seconds
Started Jul 12 05:19:55 PM PDT 24
Finished Jul 12 05:20:29 PM PDT 24
Peak memory 206224 kb
Host smart-999f0418-930c-45b2-af2c-afc718fbbb70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283349110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2283349110
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3971231685
Short name T1366
Test name
Test status
Simulation time 1407176193 ps
CPU time 19.35 seconds
Started Jul 12 05:19:54 PM PDT 24
Finished Jul 12 05:20:15 PM PDT 24
Peak memory 490176 kb
Host smart-26ba0259-79bb-4ee4-b5c9-966978049f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971231685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3971231685
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.434776732
Short name T1171
Test name
Test status
Simulation time 1365860690 ps
CPU time 8.1 seconds
Started Jul 12 05:19:54 PM PDT 24
Finished Jul 12 05:20:03 PM PDT 24
Peak memory 221836 kb
Host smart-5809c336-7463-48c7-910e-d8becbcd54ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434776732 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.434776732
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2079462402
Short name T697
Test name
Test status
Simulation time 79644651 ps
CPU time 1.44 seconds
Started Jul 12 05:20:01 PM PDT 24
Finished Jul 12 05:20:02 PM PDT 24
Peak memory 221536 kb
Host smart-a41ba3be-849f-4e57-bda2-036c3e19c839
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079462402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2079462402
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.512312132
Short name T721
Test name
Test status
Simulation time 19343720 ps
CPU time 0.64 seconds
Started Jul 12 05:20:15 PM PDT 24
Finished Jul 12 05:20:16 PM PDT 24
Peak memory 204732 kb
Host smart-51aec16c-b603-4728-88bd-46815d54c21d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512312132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.512312132
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.642642724
Short name T1097
Test name
Test status
Simulation time 145700108 ps
CPU time 2.29 seconds
Started Jul 12 05:20:09 PM PDT 24
Finished Jul 12 05:20:12 PM PDT 24
Peak memory 216908 kb
Host smart-bda45d05-eff4-444f-ad06-275834d2eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642642724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.642642724
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1188378743
Short name T687
Test name
Test status
Simulation time 319959812 ps
CPU time 4.97 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:14 PM PDT 24
Peak memory 247356 kb
Host smart-e7536c93-4350-475e-897d-79d6067bb16e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188378743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1188378743
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.596138241
Short name T516
Test name
Test status
Simulation time 10742617289 ps
CPU time 33.9 seconds
Started Jul 12 05:20:03 PM PDT 24
Finished Jul 12 05:20:38 PM PDT 24
Peak memory 313584 kb
Host smart-0f39d5e7-b092-4868-94b8-a11f02f02898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596138241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.596138241
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2558735418
Short name T547
Test name
Test status
Simulation time 2440999148 ps
CPU time 73.75 seconds
Started Jul 12 05:20:02 PM PDT 24
Finished Jul 12 05:21:17 PM PDT 24
Peak memory 701412 kb
Host smart-3d5da757-ab76-4b9f-9c3b-0a8c59cfd328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558735418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2558735418
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3275744726
Short name T489
Test name
Test status
Simulation time 275791233 ps
CPU time 1 seconds
Started Jul 12 05:20:07 PM PDT 24
Finished Jul 12 05:20:09 PM PDT 24
Peak memory 205012 kb
Host smart-aca694cc-96d6-429b-86f9-e0631a647619
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275744726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3275744726
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2035760665
Short name T616
Test name
Test status
Simulation time 556219060 ps
CPU time 2.85 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:09 PM PDT 24
Peak memory 205320 kb
Host smart-430bb84a-7865-4baf-8d57-e7434222a726
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035760665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2035760665
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3133765617
Short name T123
Test name
Test status
Simulation time 21586481783 ps
CPU time 137.43 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:22:23 PM PDT 24
Peak memory 1529380 kb
Host smart-86d011d8-e40c-477d-8ef4-8dcb3131be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133765617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3133765617
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1817797458
Short name T265
Test name
Test status
Simulation time 640866983 ps
CPU time 9.1 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:18 PM PDT 24
Peak memory 204688 kb
Host smart-ae54475f-4363-48b7-b88c-6d43453bc748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817797458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1817797458
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.96583264
Short name T316
Test name
Test status
Simulation time 29920539 ps
CPU time 0.69 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:06 PM PDT 24
Peak memory 205060 kb
Host smart-f83e6402-bd65-43bd-86d1-542fe0eb9fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96583264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.96583264
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3721761280
Short name T41
Test name
Test status
Simulation time 28447295203 ps
CPU time 103.23 seconds
Started Jul 12 05:20:05 PM PDT 24
Finished Jul 12 05:21:49 PM PDT 24
Peak memory 1024436 kb
Host smart-bb644fd0-32f0-47ae-b3aa-b53bd989c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721761280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3721761280
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2085980880
Short name T677
Test name
Test status
Simulation time 231638357 ps
CPU time 3.71 seconds
Started Jul 12 05:20:05 PM PDT 24
Finished Jul 12 05:20:10 PM PDT 24
Peak memory 205040 kb
Host smart-a3ec56cb-31cb-48ea-aedf-a938c8771118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085980880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2085980880
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2472027954
Short name T1161
Test name
Test status
Simulation time 4714907501 ps
CPU time 56.02 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:21:01 PM PDT 24
Peak memory 293088 kb
Host smart-248001c9-f22b-4596-b470-a986bc2fa6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472027954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2472027954
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1021598901
Short name T1407
Test name
Test status
Simulation time 6081295270 ps
CPU time 41.69 seconds
Started Jul 12 05:20:05 PM PDT 24
Finished Jul 12 05:20:48 PM PDT 24
Peak memory 213588 kb
Host smart-be2201f9-f72c-4fea-9d33-b6e40aaf946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021598901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1021598901
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1674859946
Short name T512
Test name
Test status
Simulation time 366193830 ps
CPU time 2.42 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 205580 kb
Host smart-bf2bd158-cd1e-4084-8465-ec101ab4cc16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674859946 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1674859946
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1858661207
Short name T1520
Test name
Test status
Simulation time 389332780 ps
CPU time 1.48 seconds
Started Jul 12 05:20:07 PM PDT 24
Finished Jul 12 05:20:09 PM PDT 24
Peak memory 205320 kb
Host smart-9a2f0f91-ab6a-4095-bdd8-e1d715cbc2a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858661207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1858661207
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.205490314
Short name T905
Test name
Test status
Simulation time 220309809 ps
CPU time 1.38 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 205400 kb
Host smart-99c163e0-3345-47d6-9f03-260e379a5941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205490314 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.205490314
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2351657371
Short name T842
Test name
Test status
Simulation time 408881328 ps
CPU time 1.77 seconds
Started Jul 12 05:20:10 PM PDT 24
Finished Jul 12 05:20:12 PM PDT 24
Peak memory 205220 kb
Host smart-2ab1591a-1092-4661-b8da-665c78e53f14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351657371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2351657371
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3695527419
Short name T626
Test name
Test status
Simulation time 276892457 ps
CPU time 1.18 seconds
Started Jul 12 05:20:12 PM PDT 24
Finished Jul 12 05:20:13 PM PDT 24
Peak memory 205296 kb
Host smart-0628c073-0a76-40a1-ae8f-690e7eb400be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695527419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3695527419
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1664727779
Short name T763
Test name
Test status
Simulation time 2518678365 ps
CPU time 7.82 seconds
Started Jul 12 05:20:07 PM PDT 24
Finished Jul 12 05:20:16 PM PDT 24
Peak memory 219440 kb
Host smart-64a0fdb1-d52f-4f38-8801-e1e498a95f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664727779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1664727779
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2221259994
Short name T94
Test name
Test status
Simulation time 8863257960 ps
CPU time 39.01 seconds
Started Jul 12 05:20:06 PM PDT 24
Finished Jul 12 05:20:46 PM PDT 24
Peak memory 1123624 kb
Host smart-b438ab6e-224b-4a15-8ee6-cbe8ed46dabe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221259994 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2221259994
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.1541752001
Short name T66
Test name
Test status
Simulation time 536717458 ps
CPU time 2.99 seconds
Started Jul 12 05:20:10 PM PDT 24
Finished Jul 12 05:20:14 PM PDT 24
Peak memory 213604 kb
Host smart-96dbde8d-dca9-46c6-9a9b-24b2bb1da32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541752001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.1541752001
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.1416529221
Short name T536
Test name
Test status
Simulation time 565534921 ps
CPU time 2.77 seconds
Started Jul 12 05:20:11 PM PDT 24
Finished Jul 12 05:20:14 PM PDT 24
Peak memory 206396 kb
Host smart-baf310d8-68b5-4204-89c9-3b387e219eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416529221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1416529221
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.4040973759
Short name T1049
Test name
Test status
Simulation time 506460899 ps
CPU time 2.3 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 204724 kb
Host smart-ffb712e8-f6ce-454f-b9e1-e71dc1955c85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040973759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.4040973759
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.526421753
Short name T670
Test name
Test status
Simulation time 3241263431 ps
CPU time 10.48 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:15 PM PDT 24
Peak memory 213640 kb
Host smart-d31b4435-cfa9-49fa-ba4d-bc75fdfd420a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526421753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.526421753
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.839418410
Short name T1021
Test name
Test status
Simulation time 638752143 ps
CPU time 24.77 seconds
Started Jul 12 05:20:06 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 213628 kb
Host smart-e92a4ba9-1f9e-4495-87db-887baec55b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839418410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.839418410
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.845280474
Short name T884
Test name
Test status
Simulation time 8000285126 ps
CPU time 5.09 seconds
Started Jul 12 05:20:04 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 205348 kb
Host smart-92c735b0-724a-4fb1-82b6-95155dfe6b6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845280474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.845280474
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1148246699
Short name T326
Test name
Test status
Simulation time 1681270069 ps
CPU time 3.44 seconds
Started Jul 12 05:20:07 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 205312 kb
Host smart-31182f81-b1fa-4feb-9c6d-6637f30b7968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148246699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1148246699
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.4029627342
Short name T1440
Test name
Test status
Simulation time 5299344351 ps
CPU time 7.67 seconds
Started Jul 12 05:20:10 PM PDT 24
Finished Jul 12 05:20:18 PM PDT 24
Peak memory 230044 kb
Host smart-421e2c0e-c508-452b-908c-b4a5e6d9436e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029627342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.4029627342
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.4088181443
Short name T971
Test name
Test status
Simulation time 242555859 ps
CPU time 3.47 seconds
Started Jul 12 05:20:08 PM PDT 24
Finished Jul 12 05:20:12 PM PDT 24
Peak memory 205324 kb
Host smart-bf52dc32-9a0b-4b4a-99c3-5dff44d5c7c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088181443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4088181443
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2361417730
Short name T198
Test name
Test status
Simulation time 18115147 ps
CPU time 0.7 seconds
Started Jul 12 05:20:29 PM PDT 24
Finished Jul 12 05:20:30 PM PDT 24
Peak memory 204648 kb
Host smart-9a1a5407-9b57-4ec0-b266-2b0416990bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361417730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2361417730
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2092043973
Short name T445
Test name
Test status
Simulation time 593508312 ps
CPU time 11.91 seconds
Started Jul 12 05:20:17 PM PDT 24
Finished Jul 12 05:20:29 PM PDT 24
Peak memory 304608 kb
Host smart-ebf0f43c-3786-4727-a5d9-7fbb6660d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092043973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2092043973
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3937290142
Short name T295
Test name
Test status
Simulation time 479090135 ps
CPU time 4.63 seconds
Started Jul 12 05:20:38 PM PDT 24
Finished Jul 12 05:20:44 PM PDT 24
Peak memory 252360 kb
Host smart-32a4cd8c-0d41-40fd-b828-ef3cca4ee20e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937290142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3937290142
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1840045583
Short name T736
Test name
Test status
Simulation time 1935464380 ps
CPU time 128.98 seconds
Started Jul 12 05:20:18 PM PDT 24
Finished Jul 12 05:22:28 PM PDT 24
Peak memory 644980 kb
Host smart-b8c8268b-cec6-4af2-a3e4-ced23191f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840045583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1840045583
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1883857746
Short name T965
Test name
Test status
Simulation time 5495400865 ps
CPU time 42.87 seconds
Started Jul 12 05:20:21 PM PDT 24
Finished Jul 12 05:21:04 PM PDT 24
Peak memory 533092 kb
Host smart-050f4a7f-1e53-4302-9551-4eaf353cdea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883857746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1883857746
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.581308848
Short name T958
Test name
Test status
Simulation time 122274405 ps
CPU time 1.05 seconds
Started Jul 12 05:20:18 PM PDT 24
Finished Jul 12 05:20:20 PM PDT 24
Peak memory 205004 kb
Host smart-4e67859b-20fa-4a2f-82d5-581e770ae8e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581308848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.581308848
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3694342914
Short name T1016
Test name
Test status
Simulation time 145159352 ps
CPU time 8.4 seconds
Started Jul 12 05:20:20 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 231040 kb
Host smart-81955d20-ddd6-4a04-8c44-221f0270bdb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694342914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3694342914
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2727071928
Short name T269
Test name
Test status
Simulation time 2696225448 ps
CPU time 5.38 seconds
Started Jul 12 05:20:28 PM PDT 24
Finished Jul 12 05:20:34 PM PDT 24
Peak memory 205340 kb
Host smart-44cef6c1-12f5-4ce8-a116-e8cc915ac982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727071928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2727071928
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.2773646980
Short name T147
Test name
Test status
Simulation time 43345943 ps
CPU time 0.64 seconds
Started Jul 12 05:20:19 PM PDT 24
Finished Jul 12 05:20:20 PM PDT 24
Peak memory 205032 kb
Host smart-23dbaa96-db1e-423e-b108-eba186ed0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773646980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2773646980
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1561097591
Short name T927
Test name
Test status
Simulation time 6690395935 ps
CPU time 282.33 seconds
Started Jul 12 05:20:18 PM PDT 24
Finished Jul 12 05:25:01 PM PDT 24
Peak memory 205324 kb
Host smart-5ae2318a-9280-4afb-905b-31f4cd87f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561097591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1561097591
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.2407153133
Short name T1234
Test name
Test status
Simulation time 23692804413 ps
CPU time 76.64 seconds
Started Jul 12 05:20:17 PM PDT 24
Finished Jul 12 05:21:34 PM PDT 24
Peak memory 205176 kb
Host smart-8d570bd7-0ec2-464a-bb56-01efc6752c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407153133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.2407153133
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.4206362924
Short name T1371
Test name
Test status
Simulation time 8557244744 ps
CPU time 32.59 seconds
Started Jul 12 05:20:16 PM PDT 24
Finished Jul 12 05:20:49 PM PDT 24
Peak memory 347772 kb
Host smart-bc5e21b2-b35a-4904-a461-acc576262c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206362924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4206362924
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1106958310
Short name T1295
Test name
Test status
Simulation time 1720749597 ps
CPU time 13.62 seconds
Started Jul 12 05:20:18 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 218624 kb
Host smart-64d137b5-d716-48fa-934a-ea8d866a4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106958310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1106958310
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1032396991
Short name T988
Test name
Test status
Simulation time 859379939 ps
CPU time 5.14 seconds
Started Jul 12 05:20:26 PM PDT 24
Finished Jul 12 05:20:31 PM PDT 24
Peak memory 213704 kb
Host smart-aaa9b761-4fc7-4a75-acfc-018b4b8510f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032396991 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1032396991
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3612259783
Short name T834
Test name
Test status
Simulation time 204502666 ps
CPU time 1.24 seconds
Started Jul 12 05:20:26 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 205104 kb
Host smart-42c1b684-31e7-49bd-8264-ac735e7ac4d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612259783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3612259783
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3068833899
Short name T222
Test name
Test status
Simulation time 178401304 ps
CPU time 1.16 seconds
Started Jul 12 05:20:23 PM PDT 24
Finished Jul 12 05:20:25 PM PDT 24
Peak memory 205332 kb
Host smart-8e329eb1-aedc-40c9-8d16-aa80aeb562cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068833899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3068833899
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1776905903
Short name T728
Test name
Test status
Simulation time 399510989 ps
CPU time 2.34 seconds
Started Jul 12 05:20:28 PM PDT 24
Finished Jul 12 05:20:31 PM PDT 24
Peak memory 205436 kb
Host smart-f6129faa-3572-419a-a6a0-2621639aba40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776905903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1776905903
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3170961070
Short name T479
Test name
Test status
Simulation time 292466152 ps
CPU time 1.17 seconds
Started Jul 12 05:20:24 PM PDT 24
Finished Jul 12 05:20:26 PM PDT 24
Peak memory 205300 kb
Host smart-d62225cf-1411-408f-b80b-a3bd8de69e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170961070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3170961070
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2205072057
Short name T284
Test name
Test status
Simulation time 9157083962 ps
CPU time 6.76 seconds
Started Jul 12 05:20:17 PM PDT 24
Finished Jul 12 05:20:24 PM PDT 24
Peak memory 221852 kb
Host smart-cd93cb20-9da5-4a25-95de-dcc08ae0018e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205072057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2205072057
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.266500867
Short name T744
Test name
Test status
Simulation time 2040338927 ps
CPU time 2.01 seconds
Started Jul 12 05:20:26 PM PDT 24
Finished Jul 12 05:20:29 PM PDT 24
Peak memory 205296 kb
Host smart-ef8892dd-b147-4d9c-a271-1ffd526e9f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266500867 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.266500867
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.3415361216
Short name T989
Test name
Test status
Simulation time 640900134 ps
CPU time 3.12 seconds
Started Jul 12 05:20:26 PM PDT 24
Finished Jul 12 05:20:29 PM PDT 24
Peak memory 213596 kb
Host smart-f1f9fa56-772d-4ac7-93ce-b0916c0a632a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415361216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.3415361216
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.2372147257
Short name T678
Test name
Test status
Simulation time 2326868548 ps
CPU time 2.46 seconds
Started Jul 12 05:20:25 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 205344 kb
Host smart-f11aae06-d0ea-4f6c-bdee-25bd2fd05229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372147257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.2372147257
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.1352271651
Short name T1476
Test name
Test status
Simulation time 588642114 ps
CPU time 2.52 seconds
Started Jul 12 05:20:27 PM PDT 24
Finished Jul 12 05:20:30 PM PDT 24
Peak memory 205224 kb
Host smart-bc05ee0b-6aaa-455e-8e9d-54632a205448
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352271651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.1352271651
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1386105143
Short name T348
Test name
Test status
Simulation time 1035694230 ps
CPU time 17.95 seconds
Started Jul 12 05:20:16 PM PDT 24
Finished Jul 12 05:20:34 PM PDT 24
Peak memory 213532 kb
Host smart-2abf67b3-fbff-4350-b6b8-5e8683ea0be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386105143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1386105143
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.535184928
Short name T340
Test name
Test status
Simulation time 2494295266 ps
CPU time 54.14 seconds
Started Jul 12 05:20:18 PM PDT 24
Finished Jul 12 05:21:12 PM PDT 24
Peak memory 217692 kb
Host smart-a0c9425c-eaef-4819-99bf-d62d7f77cb29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535184928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.535184928
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1210954659
Short name T1544
Test name
Test status
Simulation time 38807518131 ps
CPU time 199.23 seconds
Started Jul 12 05:20:19 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 2424300 kb
Host smart-68dff2c7-882f-4f0e-ad4b-2ab5913a1108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210954659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1210954659
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.772219816
Short name T1225
Test name
Test status
Simulation time 2756609992 ps
CPU time 23.28 seconds
Started Jul 12 05:20:17 PM PDT 24
Finished Jul 12 05:20:41 PM PDT 24
Peak memory 803328 kb
Host smart-e80ae45d-38e5-4d30-96b8-10dc39ec9877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772219816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.772219816
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3645154004
Short name T475
Test name
Test status
Simulation time 1196306931 ps
CPU time 6.15 seconds
Started Jul 12 05:20:25 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 213532 kb
Host smart-f8798f83-94bf-4aa3-a305-71030bc7dba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645154004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3645154004
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.2032467482
Short name T608
Test name
Test status
Simulation time 174812820 ps
CPU time 3.81 seconds
Started Jul 12 05:20:27 PM PDT 24
Finished Jul 12 05:20:32 PM PDT 24
Peak memory 206132 kb
Host smart-bf8e8c46-0a94-4857-a23e-bc2694557b7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032467482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2032467482
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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