Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	873437	1			T1	2		T2	2		T3	14
all_values[1]	873437	1			T1	2		T2	2		T3	14
all_values[2]	873437	1			T1	2		T2	2		T3	14
all_values[3]	873437	1			T1	2		T2	2		T3	14
all_values[4]	873437	1			T1	2		T2	2		T3	14
all_values[5]	873437	1			T1	2		T2	2		T3	14
all_values[6]	873437	1			T1	2		T2	2		T3	14
all_values[7]	873437	1			T1	2		T2	2		T3	14
all_values[8]	873437	1			T1	2		T2	2		T3	14
all_values[9]	873437	1			T1	2		T2	2		T3	14
all_values[10]	873437	1			T1	2		T2	2		T3	14
all_values[11]	873437	1			T1	2		T2	2		T3	14
all_values[12]	873437	1			T1	2		T2	2		T3	14
all_values[13]	873437	1			T1	2		T2	2		T3	14
all_values[14]	873437	1			T1	2		T2	2		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10745584

1

T1

26

T2

26

T3

182

auto[1]

2355971

1

T1

4

T2

4

T3

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11024324

1

T1

30

T2

30

T3

210

auto[1]

2077231

1

T14

18335

T26

18209

T178

82923

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97387	1			T6	1		T7	1		T8	2
all_values[0]	auto[0]	auto[1]	15702	1			T14	23		T26	1007		T178	623
all_values[0]	auto[1]	auto[0]	631887	1			T1	2		T2	2		T3	14
all_values[0]	auto[1]	auto[1]	128461	1			T14	1196		T26	208		T178	4906
all_values[1]	auto[0]	auto[0]	734462	1			T1	2		T2	2		T3	14
all_values[1]	auto[0]	auto[1]	138305	1			T14	1218		T26	1209		T178	5462
all_values[1]	auto[1]	auto[0]	441	1			T262	3		T263	2		T264	36
all_values[1]	auto[1]	auto[1]	229	1			T14	5		T26	6		T178	66
all_values[2]	auto[0]	auto[0]	784576	1			T1	2		T2	2		T3	14
all_values[2]	auto[0]	auto[1]	88515	1			T14	1219		T26	1208		T178	5526
all_values[2]	auto[1]	auto[0]	193	1			T47	1		T140	2		T54	1
all_values[2]	auto[1]	auto[1]	153	1			T14	3		T26	5		T178	2
all_values[3]	auto[0]	auto[0]	736835	1			T1	2		T2	2		T3	14
all_values[3]	auto[0]	auto[1]	136408	1			T14	1219		T26	1210		T178	5523
all_values[3]	auto[1]	auto[1]	194	1			T14	3		T26	4		T178	6
all_values[4]	auto[0]	auto[0]	729268	1			T1	2		T2	2		T3	14
all_values[4]	auto[0]	auto[1]	144007	1			T14	1220		T26	1211		T178	5525
all_values[4]	auto[1]	auto[0]	16	1			T252	1		T23	1		T242	1
all_values[4]	auto[1]	auto[1]	146	1			T14	3		T26	4		T178	4
all_values[5]	auto[0]	auto[0]	729310	1			T1	2		T2	2		T3	14
all_values[5]	auto[0]	auto[1]	143943	1			T14	1218		T26	1207		T178	5523
all_values[5]	auto[1]	auto[1]	184	1			T14	5		T26	6		T178	5
all_values[6]	auto[0]	auto[0]	729298	1			T1	2		T2	2		T3	14
all_values[6]	auto[0]	auto[1]	143961	1			T14	1220		T26	1207		T178	5524
all_values[6]	auto[1]	auto[1]	178	1			T14	3		T26	7		T178	4
all_values[7]	auto[0]	auto[0]	705084	1			T1	2		T2	2		T3	14
all_values[7]	auto[0]	auto[1]	135111	1			T14	1216		T26	980		T178	5296
all_values[7]	auto[1]	auto[0]	29570	1			T6	1		T7	1		T19	16
all_values[7]	auto[1]	auto[1]	3672	1			T14	5		T26	235		T178	231
all_values[8]	auto[0]	auto[0]	729299	1			T1	2		T2	2		T3	14
all_values[8]	auto[0]	auto[1]	143967	1			T14	1219		T26	1207		T178	5524
all_values[8]	auto[1]	auto[1]	171	1			T14	4		T26	7		T178	4
all_values[9]	auto[0]	auto[0]	168725	1			T1	2		T2	2		T3	14
all_values[9]	auto[0]	auto[1]	15642	1			T14	1214		T26	1197		T178	328
all_values[9]	auto[1]	auto[0]	560577	1			T6	1		T7	1		T19	4
all_values[9]	auto[1]	auto[1]	128493	1			T14	9		T26	16		T178	5200
all_values[10]	auto[0]	auto[0]	729290	1			T1	2		T2	2		T3	14
all_values[10]	auto[0]	auto[1]	143983	1			T14	1218		T26	1209		T178	5527
all_values[10]	auto[1]	auto[1]	164	1			T14	5		T26	6		T178	2
all_values[11]	auto[0]	auto[0]	2315	1			T6	1		T7	1		T8	2
all_values[11]	auto[0]	auto[1]	482	1			T14	17		T26	20		T178	30
all_values[11]	auto[1]	auto[0]	726965	1			T1	2		T2	2		T3	14
all_values[11]	auto[1]	auto[1]	143675	1			T14	1205		T26	1194		T178	5498
all_values[12]	auto[0]	auto[0]	734809	1			T1	2		T2	2		T3	14
all_values[12]	auto[0]	auto[1]	138392	1			T14	1221		T26	1210		T178	5526
all_values[12]	auto[1]	auto[0]	74	1			T47	1		T54	1		T67	2
all_values[12]	auto[1]	auto[1]	162	1			T14	1		T26	5		T178	2
all_values[13]	auto[0]	auto[0]	734633	1			T1	2		T2	2		T3	14
all_values[13]	auto[0]	auto[1]	138620	1			T14	1219		T26	1209		T178	5522
all_values[13]	auto[1]	auto[1]	184	1			T14	4		T26	5		T178	6
all_values[14]	auto[0]	auto[0]	729310	1			T1	2		T2	2		T3	14
all_values[14]	auto[0]	auto[1]	143945	1			T14	1218		T26	1206		T178	5524
all_values[14]	auto[1]	auto[1]	182	1			T14	5		T26	4		T178	4