Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	873437	1			T1	2		T2	2		T3	14
all_pins[1]	873437	1			T1	2		T2	2		T3	14
all_pins[2]	873437	1			T1	2		T2	2		T3	14
all_pins[3]	873437	1			T1	2		T2	2		T3	14
all_pins[4]	873437	1			T1	2		T2	2		T3	14
all_pins[5]	873437	1			T1	2		T2	2		T3	14
all_pins[6]	873437	1			T1	2		T2	2		T3	14
all_pins[7]	873437	1			T1	2		T2	2		T3	14
all_pins[8]	873437	1			T1	2		T2	2		T3	14
all_pins[9]	873437	1			T1	2		T2	2		T3	14
all_pins[10]	873437	1			T1	2		T2	2		T3	14
all_pins[11]	873437	1			T1	2		T2	2		T3	14
all_pins[12]	873437	1			T1	2		T2	2		T3	14
all_pins[13]	873437	1			T1	2		T2	2		T3	14
all_pins[14]	873437	1			T1	2		T2	2		T3	14

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10750878	1			T1	26		T2	26		T3	182
values[0x1]	2350677	1			T1	4		T2	4		T3	28
transitions[0x0=>0x1]	2349779	1			T1	4		T2	4		T3	28
transitions[0x1=>0x0]	2348478	1			T1	3		T2	3		T3	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	116466	1			T6	1		T7	1		T8	2
all_pins[0]	values[0x1]	756971	1			T1	2		T2	2		T3	14
all_pins[0]	transitions[0x0=>0x1]	756420	1			T1	2		T2	2		T3	14
all_pins[0]	transitions[0x1=>0x0]	146	1			T14	3		T26	1		T262	1
all_pins[1]	values[0x0]	872740	1			T1	2		T2	2		T3	14
all_pins[1]	values[0x1]	697	1			T14	3		T26	2		T262	3
all_pins[1]	transitions[0x0=>0x1]	677	1			T14	2		T26	2		T262	3
all_pins[1]	transitions[0x1=>0x0]	113	1			T26	3		T270	1		T271	1
all_pins[2]	values[0x0]	873304	1			T1	2		T2	2		T3	14
all_pins[2]	values[0x1]	133	1			T14	1		T26	3		T270	1
all_pins[2]	transitions[0x0=>0x1]	115	1			T26	3		T270	1		T271	1
all_pins[2]	transitions[0x1=>0x0]	64	1			T14	2		T178	1		T272	3
all_pins[3]	values[0x0]	873355	1			T1	2		T2	2		T3	14
all_pins[3]	values[0x1]	82	1			T14	3		T178	1		T229	1
all_pins[3]	transitions[0x0=>0x1]	66	1			T14	3		T272	3		T115	3
all_pins[3]	transitions[0x1=>0x0]	76	1			T252	1		T26	3		T23	1
all_pins[4]	values[0x0]	873345	1			T1	2		T2	2		T3	14
all_pins[4]	values[0x1]	92	1			T252	1		T26	3		T23	1
all_pins[4]	transitions[0x0=>0x1]	73	1			T252	1		T26	3		T23	1
all_pins[4]	transitions[0x1=>0x0]	61	1			T14	3		T26	4		T272	3
all_pins[5]	values[0x0]	873357	1			T1	2		T2	2		T3	14
all_pins[5]	values[0x1]	80	1			T14	3		T26	4		T178	1
all_pins[5]	transitions[0x0=>0x1]	57	1			T14	2		T26	3		T229	1
all_pins[5]	transitions[0x1=>0x0]	75	1			T26	4		T178	2		T229	3
all_pins[6]	values[0x0]	873339	1			T1	2		T2	2		T3	14
all_pins[6]	values[0x1]	98	1			T14	1		T26	5		T178	3
all_pins[6]	transitions[0x0=>0x1]	65	1			T14	1		T26	4		T178	2
all_pins[6]	transitions[0x1=>0x0]	36253	1			T6	1		T7	1		T14	2
all_pins[7]	values[0x0]	837151	1			T1	2		T2	2		T3	14
all_pins[7]	values[0x1]	36286	1			T6	1		T7	1		T14	2
all_pins[7]	transitions[0x0=>0x1]	36260	1			T6	1		T7	1		T14	2
all_pins[7]	transitions[0x1=>0x0]	70	1			T14	2		T26	3		T178	2
all_pins[8]	values[0x0]	873341	1			T1	2		T2	2		T3	14
all_pins[8]	values[0x1]	96	1			T14	2		T26	5		T178	3
all_pins[8]	transitions[0x0=>0x1]	67	1			T26	5		T178	2		T229	1
all_pins[8]	transitions[0x1=>0x0]	688999	1			T6	1		T7	1		T14	7
all_pins[9]	values[0x0]	184409	1			T1	2		T2	2		T3	14
all_pins[9]	values[0x1]	689028	1			T6	1		T7	1		T14	9
all_pins[9]	transitions[0x0=>0x1]	689010	1			T6	1		T7	1		T14	8
all_pins[9]	transitions[0x1=>0x0]	70	1			T14	2		T26	4		T229	1
all_pins[10]	values[0x0]	873349	1			T1	2		T2	2		T3	14
all_pins[10]	values[0x1]	88	1			T14	3		T26	5		T229	2
all_pins[10]	transitions[0x0=>0x1]	69	1			T14	3		T26	2		T229	2
all_pins[10]	transitions[0x1=>0x0]	866677	1			T1	2		T2	2		T3	14
all_pins[11]	values[0x0]	6741	1			T6	1		T7	1		T8	2
all_pins[11]	values[0x1]	866696	1			T1	2		T2	2		T3	14
all_pins[11]	transitions[0x0=>0x1]	866644	1			T1	2		T2	2		T3	14
all_pins[11]	transitions[0x1=>0x0]	110	1			T47	1		T26	3		T54	1
all_pins[12]	values[0x0]	873275	1			T1	2		T2	2		T3	14
all_pins[12]	values[0x1]	162	1			T47	1		T26	4		T54	1
all_pins[12]	transitions[0x0=>0x1]	147	1			T47	1		T26	2		T54	1
all_pins[12]	transitions[0x1=>0x0]	58	1			T14	3		T178	2		T229	1
all_pins[13]	values[0x0]	873364	1			T1	2		T2	2		T3	14
all_pins[13]	values[0x1]	73	1			T14	3		T26	2		T178	4
all_pins[13]	transitions[0x0=>0x1]	49	1			T26	1		T178	2		T229	2
all_pins[13]	transitions[0x1=>0x0]	71	1			T14	1		T26	1		T229	2
all_pins[14]	values[0x0]	873342	1			T1	2		T2	2		T3	14
all_pins[14]	values[0x1]	95	1			T14	4		T26	2		T178	2
all_pins[14]	transitions[0x0=>0x1]	60	1			T14	4		T26	2		T178	2
all_pins[14]	transitions[0x1=>0x0]	755635	1			T1	1		T2	1		T3	13