Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	390	1			T14	7		T26	11		T178	7
all_values[1]	390	1			T14	7		T26	11		T178	7
all_values[2]	390	1			T14	7		T26	11		T178	7
all_values[3]	390	1			T14	7		T26	11		T178	7
all_values[4]	390	1			T14	7		T26	11		T178	7
all_values[5]	390	1			T14	7		T26	11		T178	7
all_values[6]	390	1			T14	7		T26	11		T178	7
all_values[7]	390	1			T14	7		T26	11		T178	7
all_values[8]	390	1			T14	7		T26	11		T178	7
all_values[9]	390	1			T14	7		T26	11		T178	7
all_values[10]	390	1			T14	7		T26	11		T178	7
all_values[11]	390	1			T14	7		T26	11		T178	7
all_values[12]	390	1			T14	7		T26	11		T178	7
all_values[13]	390	1			T14	7		T26	11		T178	7
all_values[14]	390	1			T14	7		T26	11		T178	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3047

1

T14

43

T26

89

T178

55

auto[1]

2803

1

T14

62

T26

76

T178

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T14

10

T26

15

T178

12

auto[1]

4869

1

T14

95

T26

150

T178

93

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3470

1

T14

54

T26

92

T178

61

auto[1]

2380

1

T14

51

T26

73

T178

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1			T14	2		T32	1		T273	1
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T26	4		T178	3
all_values[0]	auto[0]	auto[1]	auto[0]	21	1			T14	2		T238	1		T125	1
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T26	1		T178	1		T229	1
all_values[0]	auto[1]	auto[0]	auto[1]	95	1			T14	2		T26	4		T178	1
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T26	2		T178	2		T229	3
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T178	1		T229	3		T274	1
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T14	2		T26	2		T229	1
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T229	1		T272	1		T33	3
all_values[1]	auto[0]	auto[1]	auto[1]	92	1			T26	3		T178	2		T229	1
all_values[1]	auto[1]	auto[0]	auto[1]	87	1			T14	2		T26	4		T178	1
all_values[1]	auto[1]	auto[1]	auto[1]	71	1			T14	3		T26	2		T178	3
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T26	2		T178	1		T274	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T14	1		T26	2		T178	3
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T14	1		T274	1		T275	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T14	2		T26	2		T178	1
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T14	2		T26	2		T178	1
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T14	1		T26	3		T178	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T26	1		T274	4		T43	1
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T26	4		T178	2		T229	2
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T14	1		T32	1		T273	1
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T14	2		T26	1		T229	1
all_values[3]	auto[1]	auto[0]	auto[1]	97	1			T26	5		T178	4		T229	3
all_values[3]	auto[1]	auto[1]	auto[1]	76	1			T14	4		T178	1		T229	1
all_values[4]	auto[0]	auto[0]	auto[0]	36	1			T238	1		T125	1		T118	2
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T14	3		T26	4		T178	1
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T272	1		T238	3		T117	1
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T14	1		T26	3		T178	2
all_values[4]	auto[1]	auto[0]	auto[1]	76	1			T14	2		T26	2		T178	1
all_values[4]	auto[1]	auto[1]	auto[1]	70	1			T14	1		T26	2		T178	3
all_values[5]	auto[0]	auto[0]	auto[0]	50	1			T26	2		T272	4		T274	1
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T178	2		T229	3
all_values[5]	auto[0]	auto[1]	auto[0]	31	1			T178	1		T272	1		T274	1
all_values[5]	auto[0]	auto[1]	auto[1]	75	1			T14	2		T26	4		T178	1
all_values[5]	auto[1]	auto[0]	auto[1]	77	1			T14	1		T26	2		T178	1
all_values[5]	auto[1]	auto[1]	auto[1]	74	1			T14	3		T26	3		T178	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T26	1		T229	1		T272	1
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T14	2		T26	1		T229	1
all_values[6]	auto[0]	auto[1]	auto[0]	34	1			T178	1		T229	1		T272	1
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T14	1		T26	3		T178	3
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T14	2		T26	2		T178	2
all_values[6]	auto[1]	auto[1]	auto[1]	79	1			T14	2		T26	4		T178	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T14	1		T178	1		T229	2
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T14	1		T26	2		T178	1
all_values[7]	auto[0]	auto[1]	auto[0]	32	1			T14	1		T178	1		T32	2
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T14	1		T26	5		T178	2
all_values[7]	auto[1]	auto[0]	auto[1]	77	1			T14	2		T26	3		T178	2
all_values[7]	auto[1]	auto[1]	auto[1]	62	1			T14	1		T26	1		T229	1
all_values[8]	auto[0]	auto[0]	auto[0]	41	1			T26	1		T32	1		T238	1
all_values[8]	auto[0]	auto[0]	auto[1]	74	1			T14	1		T26	2		T229	2
all_values[8]	auto[0]	auto[1]	auto[0]	27	1			T178	1		T238	1		T115	1
all_values[8]	auto[0]	auto[1]	auto[1]	93	1			T26	3		T178	3		T229	2
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T14	1		T26	2		T178	1
all_values[8]	auto[1]	auto[1]	auto[1]	83	1			T14	5		T26	3		T178	2
all_values[9]	auto[0]	auto[0]	auto[0]	40	1			T26	2		T43	1		T238	2
all_values[9]	auto[0]	auto[0]	auto[1]	78	1			T14	1		T26	3		T178	1
all_values[9]	auto[0]	auto[1]	auto[0]	36	1			T178	1		T272	2		T238	2
all_values[9]	auto[0]	auto[1]	auto[1]	66	1			T14	1		T26	3		T178	2
all_values[9]	auto[1]	auto[0]	auto[1]	89	1			T26	2		T178	3		T229	3
all_values[9]	auto[1]	auto[1]	auto[1]	81	1			T14	5		T26	1		T229	2
all_values[10]	auto[0]	auto[0]	auto[0]	45	1			T229	1		T274	1		T32	2
all_values[10]	auto[0]	auto[0]	auto[1]	72	1			T26	2		T178	4		T229	2
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T238	1		T125	1		T33	1
all_values[10]	auto[0]	auto[1]	auto[1]	89	1			T14	2		T26	3		T178	1
all_values[10]	auto[1]	auto[0]	auto[1]	79	1			T14	3		T26	3		T178	2
all_values[10]	auto[1]	auto[1]	auto[1]	85	1			T14	2		T26	3		T229	2
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T26	1		T229	1		T274	1
all_values[11]	auto[0]	auto[0]	auto[1]	82	1			T14	1		T178	3		T229	1
all_values[11]	auto[0]	auto[1]	auto[0]	19	1			T14	1		T178	1		T229	1
all_values[11]	auto[0]	auto[1]	auto[1]	97	1			T14	3		T26	3		T178	2
all_values[11]	auto[1]	auto[0]	auto[1]	71	1			T14	1		T26	3		T178	1
all_values[11]	auto[1]	auto[1]	auto[1]	85	1			T14	1		T26	4		T229	2
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T178	1		T274	1		T125	1
all_values[12]	auto[0]	auto[0]	auto[1]	82	1			T14	2		T26	2		T178	3
all_values[12]	auto[0]	auto[1]	auto[0]	18	1			T14	1		T229	2		T272	1
all_values[12]	auto[0]	auto[1]	auto[1]	95	1			T14	3		T26	4		T178	1
all_values[12]	auto[1]	auto[0]	auto[1]	78	1			T14	1		T26	2		T178	1
all_values[12]	auto[1]	auto[1]	auto[1]	84	1			T26	3		T178	1		T229	3
all_values[13]	auto[0]	auto[0]	auto[0]	35	1			T26	1		T178	1		T125	2
all_values[13]	auto[0]	auto[0]	auto[1]	93	1			T14	1		T26	3		T178	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1			T125	1		T116	3		T275	1
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T14	4		T26	4		T178	1
all_values[13]	auto[1]	auto[0]	auto[1]	100	1			T14	1		T26	2		T178	2
all_values[13]	auto[1]	auto[1]	auto[1]	65	1			T14	1		T26	1		T178	2
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T26	4		T178	1		T229	1
all_values[14]	auto[0]	auto[0]	auto[1]	72	1			T14	2		T26	4		T178	1
all_values[14]	auto[0]	auto[1]	auto[0]	32	1			T229	1		T272	1		T274	1
all_values[14]	auto[0]	auto[1]	auto[1]	84	1			T14	3		T178	2		T229	1
all_values[14]	auto[1]	auto[0]	auto[1]	84	1			T14	1		T26	1		T178	1
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T14	1		T26	2		T178	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal