Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	710442	1			T1	2547		T2	5570		T3	2
all_values[1]	710442	1			T1	2547		T2	5570		T3	2
all_values[2]	710442	1			T1	2547		T2	5570		T3	2
all_values[3]	710442	1			T1	2547		T2	5570		T3	2
all_values[4]	710442	1			T1	2547		T2	5570		T3	2
all_values[5]	710442	1			T1	2547		T2	5570		T3	2
all_values[6]	710442	1			T1	2547		T2	5570		T3	2
all_values[7]	710442	1			T1	2547		T2	5570		T3	2
all_values[8]	710442	1			T1	2547		T2	5570		T3	2
all_values[9]	710442	1			T1	2547		T2	5570		T3	2
all_values[10]	710442	1			T1	2547		T2	5570		T3	2
all_values[11]	710442	1			T1	2547		T2	5570		T3	2
all_values[12]	710442	1			T1	2547		T2	5570		T3	2
all_values[13]	710442	1			T1	2547		T2	5570		T3	2
all_values[14]	710442	1			T1	2547		T2	5570		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8774321

1

T1

34997

T2

67975

T3

26

auto[1]

1882309

1

T1

3208

T2

15575

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10347066

1

T1

38205

T2

83320

T3

30

auto[1]

309564

1

T2

230

T18

268

T31

13695

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	93238	1			T1	1891		T2	636		T6	111
all_values[0]	auto[0]	auto[1]	7611	1			T2	7		T18	8		T31	505
all_values[0]	auto[1]	auto[0]	593888	1			T1	656		T2	4918		T3	2
all_values[0]	auto[1]	auto[1]	15705	1			T2	9		T18	11		T31	473
all_values[1]	auto[0]	auto[0]	686156	1			T1	2547		T2	5544		T3	2
all_values[1]	auto[0]	auto[1]	23987	1			T2	7		T18	18		T31	975
all_values[1]	auto[1]	auto[0]	142	1			T2	11		T6	1		T42	2
all_values[1]	auto[1]	auto[1]	157	1			T2	8		T18	2		T31	2
all_values[2]	auto[0]	auto[0]	686123	1			T1	2547		T2	5555		T3	2
all_values[2]	auto[0]	auto[1]	23976	1			T2	8		T18	17		T31	976
all_values[2]	auto[1]	auto[0]	189	1			T10	1		T51	1		T259	2
all_values[2]	auto[1]	auto[1]	154	1			T2	7		T18	3		T31	2
all_values[3]	auto[0]	auto[0]	693410	1			T1	2547		T2	5555		T3	2
all_values[3]	auto[0]	auto[1]	16879	1			T2	10		T18	18		T31	975
all_values[3]	auto[1]	auto[1]	153	1			T2	5		T31	4		T110	5
all_values[4]	auto[0]	auto[0]	686285	1			T1	2547		T2	5554		T3	2
all_values[4]	auto[0]	auto[1]	23987	1			T2	8		T18	18		T31	977
all_values[4]	auto[1]	auto[0]	30	1			T20	1		T21	3		T22	1
all_values[4]	auto[1]	auto[1]	140	1			T2	8		T18	2		T31	1
all_values[5]	auto[0]	auto[0]	687118	1			T1	2547		T2	5555		T3	2
all_values[5]	auto[0]	auto[1]	23164	1			T2	10		T31	977		T110	5586
all_values[5]	auto[1]	auto[1]	160	1			T2	5		T31	2		T110	4
all_values[6]	auto[0]	auto[0]	693404	1			T1	2547		T2	5554		T3	2
all_values[6]	auto[0]	auto[1]	16872	1			T2	10		T18	18		T31	977
all_values[6]	auto[1]	auto[1]	166	1			T2	6		T18	2		T31	1
all_values[7]	auto[0]	auto[0]	667091	1			T1	2542		T2	5223		T3	2
all_values[7]	auto[0]	auto[1]	15568	1			T2	10		T18	14		T31	869
all_values[7]	auto[1]	auto[0]	26323	1			T1	5		T2	331		T6	94
all_values[7]	auto[1]	auto[1]	1460	1			T2	6		T18	4		T31	110
all_values[8]	auto[0]	auto[0]	686320	1			T1	2547		T2	5554		T3	2
all_values[8]	auto[0]	auto[1]	23951	1			T2	12		T18	16		T31	975
all_values[8]	auto[1]	auto[1]	171	1			T2	4		T18	3		T31	3
all_values[9]	auto[0]	auto[0]	160860	1			T1	2545		T2	863		T3	2
all_values[9]	auto[0]	auto[1]	14635	1			T2	10		T18	16		T31	945
all_values[9]	auto[1]	auto[0]	525441	1			T1	2		T2	4691		T6	2771
all_values[9]	auto[1]	auto[1]	9506	1			T2	6		T18	3		T31	33
all_values[10]	auto[0]	auto[0]	699645	1			T1	2547		T2	5558		T3	2
all_values[10]	auto[0]	auto[1]	10652	1			T2	10		T18	18		T110	337
all_values[10]	auto[1]	auto[1]	145	1			T2	2		T18	1		T110	2
all_values[11]	auto[0]	auto[0]	2248	1			T1	2		T2	15		T6	9
all_values[11]	auto[0]	auto[1]	310	1			T2	6		T18	8		T31	27
all_values[11]	auto[1]	auto[0]	684049	1			T1	2545		T2	5541		T3	2
all_values[11]	auto[1]	auto[1]	23835	1			T2	8		T18	12		T31	951
all_values[12]	auto[0]	auto[0]	691513	1			T1	2547		T2	5554		T3	2
all_values[12]	auto[0]	auto[1]	18734	1			T2	11		T18	18		T31	976
all_values[12]	auto[1]	auto[0]	61	1			T10	1		T51	1		T65	1
all_values[12]	auto[1]	auto[1]	134	1			T2	5		T18	1		T31	3
all_values[13]	auto[0]	auto[0]	694708	1			T1	2547		T2	5554		T3	2
all_values[13]	auto[0]	auto[1]	15583	1			T2	14		T18	16		T31	978
all_values[13]	auto[1]	auto[1]	151	1			T2	2		T18	2		T31	1
all_values[14]	auto[0]	auto[0]	688824	1			T1	2547		T2	5554		T3	2
all_values[14]	auto[0]	auto[1]	21469	1			T2	14		T18	18		T31	975
all_values[14]	auto[1]	auto[1]	149	1			T2	2		T18	1		T31	2