Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	710442	1			T1	2547		T2	5570		T3	2
all_pins[1]	710442	1			T1	2547		T2	5570		T3	2
all_pins[2]	710442	1			T1	2547		T2	5570		T3	2
all_pins[3]	710442	1			T1	2547		T2	5570		T3	2
all_pins[4]	710442	1			T1	2547		T2	5570		T3	2
all_pins[5]	710442	1			T1	2547		T2	5570		T3	2
all_pins[6]	710442	1			T1	2547		T2	5570		T3	2
all_pins[7]	710442	1			T1	2547		T2	5570		T3	2
all_pins[8]	710442	1			T1	2547		T2	5570		T3	2
all_pins[9]	710442	1			T1	2547		T2	5570		T3	2
all_pins[10]	710442	1			T1	2547		T2	5570		T3	2
all_pins[11]	710442	1			T1	2547		T2	5570		T3	2
all_pins[12]	710442	1			T1	2547		T2	5570		T3	2
all_pins[13]	710442	1			T1	2547		T2	5570		T3	2
all_pins[14]	710442	1			T1	2547		T2	5570		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8780497	1			T1	34997		T2	67996		T3	26
values[0x1]	1876133	1			T1	3208		T2	15554		T3	4
transitions[0x0=>0x1]	1875657	1			T1	3208		T2	15530		T3	4
transitions[0x1=>0x0]	1874358	1			T1	3207		T2	15530		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	104517	1			T1	1891		T2	647		T6	111
all_pins[0]	values[0x1]	605925	1			T1	656		T2	4923		T3	2
all_pins[0]	transitions[0x0=>0x1]	605737	1			T1	656		T2	4909		T3	2
all_pins[0]	transitions[0x1=>0x0]	61	1			T22	1		T110	2		T114	4
all_pins[1]	values[0x0]	710193	1			T1	2547		T2	5556		T3	2
all_pins[1]	values[0x1]	249	1			T2	14		T6	2		T42	3
all_pins[1]	transitions[0x0=>0x1]	227	1			T2	13		T6	2		T42	3
all_pins[1]	transitions[0x1=>0x0]	107	1			T2	5		T18	1		T265	1
all_pins[2]	values[0x0]	710313	1			T1	2547		T2	5564		T3	2
all_pins[2]	values[0x1]	129	1			T2	6		T18	2		T265	1
all_pins[2]	transitions[0x0=>0x1]	106	1			T2	3		T18	2		T265	1
all_pins[2]	transitions[0x1=>0x0]	67	1			T31	2		T110	3		T114	2
all_pins[3]	values[0x0]	710352	1			T1	2547		T2	5567		T3	2
all_pins[3]	values[0x1]	90	1			T2	3		T31	3		T110	3
all_pins[3]	transitions[0x0=>0x1]	69	1			T2	3		T31	3		T110	3
all_pins[3]	transitions[0x1=>0x0]	85	1			T2	2		T20	1		T21	3
all_pins[4]	values[0x0]	710336	1			T1	2547		T2	5568		T3	2
all_pins[4]	values[0x1]	106	1			T2	2		T20	1		T21	3
all_pins[4]	transitions[0x0=>0x1]	92	1			T2	1		T20	1		T21	3
all_pins[4]	transitions[0x1=>0x0]	67	1			T31	1		T110	1		T266	4
all_pins[5]	values[0x0]	710361	1			T1	2547		T2	5569		T3	2
all_pins[5]	values[0x1]	81	1			T2	1		T31	1		T110	1
all_pins[5]	transitions[0x0=>0x1]	58	1			T2	1		T31	1		T114	2
all_pins[5]	transitions[0x1=>0x0]	65	1			T2	4		T18	1		T114	1
all_pins[6]	values[0x0]	710354	1			T1	2547		T2	5566		T3	2
all_pins[6]	values[0x1]	88	1			T2	4		T18	1		T110	1
all_pins[6]	transitions[0x0=>0x1]	71	1			T2	3		T18	1		T110	1
all_pins[6]	transitions[0x1=>0x0]	30465	1			T1	5		T2	354		T6	124
all_pins[7]	values[0x0]	679960	1			T1	2542		T2	5215		T3	2
all_pins[7]	values[0x1]	30482	1			T1	5		T2	355		T6	124
all_pins[7]	transitions[0x0=>0x1]	30454	1			T1	5		T2	354		T6	124
all_pins[7]	transitions[0x1=>0x0]	60	1			T2	1		T18	3		T31	1
all_pins[8]	values[0x0]	710354	1			T1	2547		T2	5568		T3	2
all_pins[8]	values[0x1]	88	1			T2	2		T18	3		T31	1
all_pins[8]	transitions[0x0=>0x1]	68	1			T18	3		T110	2		T115	1
all_pins[8]	transitions[0x1=>0x0]	534869	1			T1	2		T2	4694		T6	2771
all_pins[9]	values[0x0]	175553	1			T1	2545		T2	874		T3	2
all_pins[9]	values[0x1]	534889	1			T1	2		T2	4696		T6	2771
all_pins[9]	transitions[0x0=>0x1]	534872	1			T1	2		T2	4696		T6	2771
all_pins[9]	transitions[0x1=>0x0]	65	1			T114	3		T267	1		T116	1
all_pins[10]	values[0x0]	710360	1			T1	2547		T2	5570		T3	2
all_pins[10]	values[0x1]	82	1			T114	5		T267	2		T115	1
all_pins[10]	transitions[0x0=>0x1]	59	1			T114	3		T267	2		T115	1
all_pins[10]	transitions[0x1=>0x0]	703617	1			T1	2545		T2	5545		T3	2
all_pins[11]	values[0x0]	6802	1			T1	2		T2	25		T6	9
all_pins[11]	values[0x1]	703640	1			T1	2545		T2	5545		T3	2
all_pins[11]	transitions[0x0=>0x1]	703612	1			T1	2545		T2	5545		T3	2
all_pins[11]	transitions[0x1=>0x0]	107	1			T2	1		T10	1		T51	1
all_pins[12]	values[0x0]	710307	1			T1	2547		T2	5569		T3	2
all_pins[12]	values[0x1]	135	1			T2	1		T10	1		T51	1
all_pins[12]	transitions[0x0=>0x1]	123	1			T2	1		T10	1		T51	1
all_pins[12]	transitions[0x1=>0x0]	70	1			T2	1		T18	2		T110	3
all_pins[13]	values[0x0]	710360	1			T1	2547		T2	5569		T3	2
all_pins[13]	values[0x1]	82	1			T2	1		T18	2		T31	1
all_pins[13]	transitions[0x0=>0x1]	64	1			T2	1		T18	2		T31	1
all_pins[13]	transitions[0x1=>0x0]	49	1			T2	1		T114	2		T267	1
all_pins[14]	values[0x0]	710375	1			T1	2547		T2	5569		T3	2
all_pins[14]	values[0x1]	67	1			T2	1		T110	1		T114	2
all_pins[14]	transitions[0x0=>0x1]	45	1			T110	1		T114	2		T267	1
all_pins[14]	transitions[0x1=>0x0]	604604	1			T1	655		T2	4922		T3	1