Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	348	1			T2	14		T18	4		T31	4
all_values[1]	348	1			T2	14		T18	4		T31	4
all_values[2]	348	1			T2	14		T18	4		T31	4
all_values[3]	348	1			T2	14		T18	4		T31	4
all_values[4]	348	1			T2	14		T18	4		T31	4
all_values[5]	348	1			T2	14		T18	4		T31	4
all_values[6]	348	1			T2	14		T18	4		T31	4
all_values[7]	348	1			T2	14		T18	4		T31	4
all_values[8]	348	1			T2	14		T18	4		T31	4
all_values[9]	348	1			T2	14		T18	4		T31	4
all_values[10]	348	1			T2	14		T18	4		T31	4
all_values[11]	348	1			T2	14		T18	4		T31	4
all_values[12]	348	1			T2	14		T18	4		T31	4
all_values[13]	348	1			T2	14		T18	4		T31	4
all_values[14]	348	1			T2	14		T18	4		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2713

1

T2

94

T18

27

T31

26

auto[1]

2507

1

T2

116

T18

33

T31

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844

1

T2

10

T18

16

T31

15

auto[1]

4376

1

T2

200

T18

44

T31

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3081

1

T2

126

T18

36

T31

37

auto[1]

2139

1

T2

84

T18

24

T31

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	37	1			T114	2		T115	1		T116	2
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T2	4		T110	2		T114	5
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T18	1		T31	1		T267	4
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T2	6		T18	1		T31	1
all_values[0]	auto[1]	auto[0]	auto[1]	86	1			T18	2		T110	2		T114	6
all_values[0]	auto[1]	auto[1]	auto[1]	61	1			T2	4		T31	2		T110	2
all_values[1]	auto[0]	auto[0]	auto[0]	23	1			T31	2		T23	1		T268	1
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T2	2		T18	1		T110	2
all_values[1]	auto[0]	auto[1]	auto[0]	16	1			T2	1		T119	1		T268	1
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T2	3		T18	1		T31	1
all_values[1]	auto[1]	auto[0]	auto[1]	87	1			T2	5		T18	1		T31	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1			T2	3		T18	1		T110	1
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T110	2		T114	1		T267	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T2	3		T31	1		T110	1
all_values[2]	auto[0]	auto[1]	auto[0]	20	1			T2	1		T31	1		T267	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T2	3		T18	1		T110	4
all_values[2]	auto[1]	auto[0]	auto[1]	72	1			T2	3		T114	3		T266	3
all_values[2]	auto[1]	auto[1]	auto[1]	82	1			T2	4		T18	3		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T18	1		T114	1		T267	1
all_values[3]	auto[0]	auto[0]	auto[1]	61	1			T2	6		T18	1		T110	3
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T2	1		T18	1		T266	3
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T2	2		T31	1		T110	1
all_values[3]	auto[1]	auto[0]	auto[1]	67	1			T2	2		T18	1		T31	1
all_values[3]	auto[1]	auto[1]	auto[1]	71	1			T2	3		T31	2		T110	2
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T31	1		T114	1		T115	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T2	4		T18	2		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T110	1		T118	1		T269	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T2	2		T31	1		T110	4
all_values[4]	auto[1]	auto[0]	auto[1]	84	1			T2	5		T18	1		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1			T2	3		T18	1		T110	2
all_values[5]	auto[0]	auto[0]	auto[0]	32	1			T18	2		T267	3		T23	1
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T2	5		T110	2		T114	2
all_values[5]	auto[0]	auto[1]	auto[0]	13	1			T2	1		T18	2		T110	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T2	3		T31	1		T110	1
all_values[5]	auto[1]	auto[0]	auto[1]	77	1			T2	4		T31	1		T110	2
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T2	1		T31	2		T110	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T31	1		T110	1		T115	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T2	5		T31	1		T110	4
all_values[6]	auto[0]	auto[1]	auto[0]	16	1			T270	1		T271	2		T272	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T2	2		T18	1		T114	5
all_values[6]	auto[1]	auto[0]	auto[1]	72	1			T2	3		T18	2		T31	2
all_values[6]	auto[1]	auto[1]	auto[1]	74	1			T2	4		T18	1		T114	3
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T115	3		T266	4		T117	1
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T2	3		T18	1		T110	3
all_values[7]	auto[0]	auto[1]	auto[0]	26	1			T18	2		T114	1		T115	1
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T2	4		T31	3		T110	3
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T2	2		T31	1		T110	1
all_values[7]	auto[1]	auto[1]	auto[1]	71	1			T2	5		T18	1		T110	1
all_values[8]	auto[0]	auto[0]	auto[0]	35	1			T31	1		T266	1		T119	1
all_values[8]	auto[0]	auto[0]	auto[1]	72	1			T2	1		T31	1		T110	3
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T18	1		T110	1		T114	2
all_values[8]	auto[0]	auto[1]	auto[1]	77	1			T2	8		T18	1		T31	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1			T2	1		T110	1		T114	3
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T2	4		T18	2		T31	1
all_values[9]	auto[0]	auto[0]	auto[0]	27	1			T266	2		T23	2		T117	1
all_values[9]	auto[0]	auto[0]	auto[1]	79	1			T2	5		T18	1		T110	4
all_values[9]	auto[0]	auto[1]	auto[0]	16	1			T18	1		T31	1		T119	3
all_values[9]	auto[0]	auto[1]	auto[1]	77	1			T2	3		T18	1		T31	2
all_values[9]	auto[1]	auto[0]	auto[1]	86	1			T2	2		T18	1		T114	4
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T2	4		T31	1		T110	1
all_values[10]	auto[0]	auto[0]	auto[0]	41	1			T2	2		T31	2		T110	1
all_values[10]	auto[0]	auto[0]	auto[1]	57	1			T2	2		T18	2		T110	2
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T2	2		T18	1		T31	2
all_values[10]	auto[0]	auto[1]	auto[1]	73	1			T2	6		T114	6		T267	1
all_values[10]	auto[1]	auto[0]	auto[1]	66	1			T2	2		T18	1		T110	2
all_values[10]	auto[1]	auto[1]	auto[1]	79	1			T114	4		T267	2		T115	1
all_values[11]	auto[0]	auto[0]	auto[0]	22	1			T2	1		T266	2		T118	2
all_values[11]	auto[0]	auto[0]	auto[1]	84	1			T2	3		T31	1		T110	2
all_values[11]	auto[0]	auto[1]	auto[0]	15	1			T2	1		T31	1		T118	2
all_values[11]	auto[0]	auto[1]	auto[1]	78	1			T2	4		T18	1		T31	1
all_values[11]	auto[1]	auto[0]	auto[1]	85	1			T2	1		T18	2		T31	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T2	4		T18	1		T110	4
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T110	3		T267	1		T23	1
all_values[12]	auto[0]	auto[0]	auto[1]	64	1			T2	7		T18	1		T110	1
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T18	1		T110	2		T114	1
all_values[12]	auto[0]	auto[1]	auto[1]	87	1			T2	2		T18	1		T31	1
all_values[12]	auto[1]	auto[0]	auto[1]	65	1			T2	3		T18	1		T110	1
all_values[12]	auto[1]	auto[1]	auto[1]	69	1			T2	2		T31	3		T110	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T114	1		T267	3		T266	4
all_values[13]	auto[0]	auto[0]	auto[1]	64	1			T2	2		T31	3		T110	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1			T18	2		T114	1		T267	1
all_values[13]	auto[0]	auto[1]	auto[1]	82	1			T2	6		T18	1		T110	1
all_values[13]	auto[1]	auto[0]	auto[1]	70	1			T110	2		T114	5		T115	3
all_values[13]	auto[1]	auto[1]	auto[1]	76	1			T2	6		T18	1		T31	1
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T31	1		T114	2		T267	1
all_values[14]	auto[0]	auto[0]	auto[1]	78	1			T2	4		T18	2		T31	1
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T18	1		T31	1		T23	4
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T2	6		T110	3		T114	9
all_values[14]	auto[1]	auto[0]	auto[1]	66	1			T2	2		T18	1		T31	1
all_values[14]	auto[1]	auto[1]	auto[1]	54	1			T2	2		T110	1		T114	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal