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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.25 97.21 89.50 97.22 72.02 94.26 98.44 90.11


Total test records in report: 1835
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T195 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3070042156 Jul 14 05:33:20 PM PDT 24 Jul 14 05:33:23 PM PDT 24 49638468 ps
T1765 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.926098413 Jul 14 05:33:24 PM PDT 24 Jul 14 05:33:25 PM PDT 24 39441886 ps
T253 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2321994532 Jul 14 05:33:07 PM PDT 24 Jul 14 05:33:10 PM PDT 24 50704959 ps
T1766 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.21737624 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:06 PM PDT 24 33008142 ps
T199 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2245782930 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:30 PM PDT 24 552975043 ps
T1767 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3923259241 Jul 14 05:33:06 PM PDT 24 Jul 14 05:33:09 PM PDT 24 90136073 ps
T1768 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4041187967 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:07 PM PDT 24 161356055 ps
T1769 /workspace/coverage/cover_reg_top/45.i2c_intr_test.854175296 Jul 14 05:33:29 PM PDT 24 Jul 14 05:33:30 PM PDT 24 26713340 ps
T1770 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.609529669 Jul 14 05:33:16 PM PDT 24 Jul 14 05:33:18 PM PDT 24 36853273 ps
T210 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1835432419 Jul 14 05:33:24 PM PDT 24 Jul 14 05:33:25 PM PDT 24 65929888 ps
T188 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2184553713 Jul 14 05:32:56 PM PDT 24 Jul 14 05:33:00 PM PDT 24 116506135 ps
T1771 /workspace/coverage/cover_reg_top/48.i2c_intr_test.853422277 Jul 14 05:33:28 PM PDT 24 Jul 14 05:33:29 PM PDT 24 167852953 ps
T1772 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1681182420 Jul 14 05:33:02 PM PDT 24 Jul 14 05:33:05 PM PDT 24 23246463 ps
T1773 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1013173667 Jul 14 05:33:02 PM PDT 24 Jul 14 05:33:05 PM PDT 24 19665037 ps
T211 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1641680831 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:28 PM PDT 24 26883037 ps
T1774 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2343384927 Jul 14 05:33:15 PM PDT 24 Jul 14 05:33:17 PM PDT 24 51902504 ps
T1775 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2975626336 Jul 14 05:32:58 PM PDT 24 Jul 14 05:33:01 PM PDT 24 318565186 ps
T1776 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.265098286 Jul 14 05:33:01 PM PDT 24 Jul 14 05:33:06 PM PDT 24 705080326 ps
T212 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2112939024 Jul 14 05:33:07 PM PDT 24 Jul 14 05:33:10 PM PDT 24 245720967 ps
T1777 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3058858795 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:07 PM PDT 24 37933752 ps
T1778 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3450760595 Jul 14 05:33:14 PM PDT 24 Jul 14 05:33:15 PM PDT 24 132501936 ps
T1779 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4025302627 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:07 PM PDT 24 402558571 ps
T1780 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.587433356 Jul 14 05:33:14 PM PDT 24 Jul 14 05:33:16 PM PDT 24 35814312 ps
T1781 /workspace/coverage/cover_reg_top/5.i2c_intr_test.489988582 Jul 14 05:33:01 PM PDT 24 Jul 14 05:33:03 PM PDT 24 29448864 ps
T1782 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1677269925 Jul 14 05:33:09 PM PDT 24 Jul 14 05:33:11 PM PDT 24 17341077 ps
T1783 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4239312210 Jul 14 05:33:15 PM PDT 24 Jul 14 05:33:16 PM PDT 24 21358492 ps
T213 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2363407825 Jul 14 05:32:58 PM PDT 24 Jul 14 05:33:01 PM PDT 24 19999756 ps
T1784 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.221003905 Jul 14 05:33:08 PM PDT 24 Jul 14 05:33:10 PM PDT 24 28893896 ps
T1785 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.655530431 Jul 14 05:33:06 PM PDT 24 Jul 14 05:33:08 PM PDT 24 31278961 ps
T1786 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2717769001 Jul 14 05:33:06 PM PDT 24 Jul 14 05:33:09 PM PDT 24 237412506 ps
T1787 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.51902607 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:06 PM PDT 24 42611320 ps
T214 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1080211054 Jul 14 05:33:17 PM PDT 24 Jul 14 05:33:19 PM PDT 24 56571600 ps
T1788 /workspace/coverage/cover_reg_top/17.i2c_intr_test.691933242 Jul 14 05:33:23 PM PDT 24 Jul 14 05:33:24 PM PDT 24 26389635 ps
T1789 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2511535641 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:06 PM PDT 24 47827412 ps
T1790 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2156643532 Jul 14 05:33:30 PM PDT 24 Jul 14 05:33:31 PM PDT 24 45005613 ps
T1791 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3499013234 Jul 14 05:33:28 PM PDT 24 Jul 14 05:33:29 PM PDT 24 16143189 ps
T1792 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2900282394 Jul 14 05:32:57 PM PDT 24 Jul 14 05:33:00 PM PDT 24 124922572 ps
T1793 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3522339455 Jul 14 05:33:10 PM PDT 24 Jul 14 05:33:12 PM PDT 24 226314372 ps
T1794 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3526007651 Jul 14 05:33:10 PM PDT 24 Jul 14 05:33:12 PM PDT 24 79677993 ps
T1795 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.820281725 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:08 PM PDT 24 53673309 ps
T1796 /workspace/coverage/cover_reg_top/20.i2c_intr_test.806079510 Jul 14 05:33:23 PM PDT 24 Jul 14 05:33:24 PM PDT 24 47204853 ps
T1797 /workspace/coverage/cover_reg_top/26.i2c_intr_test.4178681918 Jul 14 05:33:30 PM PDT 24 Jul 14 05:33:31 PM PDT 24 17281166 ps
T1798 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1310787868 Jul 14 05:33:25 PM PDT 24 Jul 14 05:33:26 PM PDT 24 19225134 ps
T1799 /workspace/coverage/cover_reg_top/34.i2c_intr_test.4266913139 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:28 PM PDT 24 18650248 ps
T1800 /workspace/coverage/cover_reg_top/22.i2c_intr_test.302405110 Jul 14 05:33:18 PM PDT 24 Jul 14 05:33:20 PM PDT 24 23248729 ps
T1801 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3162367785 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:28 PM PDT 24 25351611 ps
T1802 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.342550546 Jul 14 05:33:10 PM PDT 24 Jul 14 05:33:14 PM PDT 24 114499325 ps
T1803 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3514940427 Jul 14 05:33:25 PM PDT 24 Jul 14 05:33:27 PM PDT 24 18226435 ps
T1804 /workspace/coverage/cover_reg_top/44.i2c_intr_test.693606824 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:28 PM PDT 24 48830012 ps
T1805 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.629763844 Jul 14 05:32:57 PM PDT 24 Jul 14 05:33:01 PM PDT 24 635610283 ps
T1806 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2616761586 Jul 14 05:33:09 PM PDT 24 Jul 14 05:33:11 PM PDT 24 37554667 ps
T215 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3487925467 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:06 PM PDT 24 90176403 ps
T1807 /workspace/coverage/cover_reg_top/7.i2c_intr_test.772900358 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:05 PM PDT 24 86862833 ps
T1808 /workspace/coverage/cover_reg_top/8.i2c_intr_test.4288490435 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:07 PM PDT 24 20611630 ps
T1809 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2924384024 Jul 14 05:33:06 PM PDT 24 Jul 14 05:33:11 PM PDT 24 266408268 ps
T1810 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3487641924 Jul 14 05:33:05 PM PDT 24 Jul 14 05:33:10 PM PDT 24 155818441 ps
T1811 /workspace/coverage/cover_reg_top/9.i2c_intr_test.611648369 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:06 PM PDT 24 40000976 ps
T1812 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1394155015 Jul 14 05:33:16 PM PDT 24 Jul 14 05:33:18 PM PDT 24 16576162 ps
T1813 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.860505368 Jul 14 05:33:17 PM PDT 24 Jul 14 05:33:21 PM PDT 24 501655411 ps
T1814 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.999403118 Jul 14 05:33:00 PM PDT 24 Jul 14 05:33:03 PM PDT 24 21642870 ps
T1815 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1387492707 Jul 14 05:33:30 PM PDT 24 Jul 14 05:33:32 PM PDT 24 54772000 ps
T1816 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3111286077 Jul 14 05:33:30 PM PDT 24 Jul 14 05:33:32 PM PDT 24 49347817 ps
T1817 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.567373929 Jul 14 05:33:02 PM PDT 24 Jul 14 05:33:06 PM PDT 24 183142668 ps
T1818 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2798774298 Jul 14 05:33:26 PM PDT 24 Jul 14 05:33:29 PM PDT 24 76381121 ps
T1819 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4136577942 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:07 PM PDT 24 40074996 ps
T1820 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3093928568 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:05 PM PDT 24 21488811 ps
T1821 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3555941425 Jul 14 05:33:08 PM PDT 24 Jul 14 05:33:10 PM PDT 24 19260935 ps
T216 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3977374398 Jul 14 05:33:10 PM PDT 24 Jul 14 05:33:12 PM PDT 24 63384270 ps
T1822 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3300817773 Jul 14 05:33:20 PM PDT 24 Jul 14 05:33:22 PM PDT 24 26260559 ps
T1823 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1820882558 Jul 14 05:33:28 PM PDT 24 Jul 14 05:33:30 PM PDT 24 19445941 ps
T1824 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.363268808 Jul 14 05:32:54 PM PDT 24 Jul 14 05:32:58 PM PDT 24 47121582 ps
T1825 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.681202035 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:08 PM PDT 24 173090189 ps
T1826 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.501893353 Jul 14 05:32:56 PM PDT 24 Jul 14 05:32:58 PM PDT 24 162565619 ps
T1827 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.443983471 Jul 14 05:33:11 PM PDT 24 Jul 14 05:33:12 PM PDT 24 78702921 ps
T1828 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1016265436 Jul 14 05:33:17 PM PDT 24 Jul 14 05:33:20 PM PDT 24 244668480 ps
T1829 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1443380638 Jul 14 05:33:15 PM PDT 24 Jul 14 05:33:17 PM PDT 24 53196070 ps
T194 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1821220399 Jul 14 05:33:07 PM PDT 24 Jul 14 05:33:11 PM PDT 24 276849678 ps
T1830 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1736624593 Jul 14 05:33:03 PM PDT 24 Jul 14 05:33:07 PM PDT 24 19499538 ps
T217 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2058776678 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:08 PM PDT 24 411078892 ps
T1831 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1392674272 Jul 14 05:33:00 PM PDT 24 Jul 14 05:33:03 PM PDT 24 31980696 ps
T1832 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3267949094 Jul 14 05:33:19 PM PDT 24 Jul 14 05:33:21 PM PDT 24 32694077 ps
T1833 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1780204591 Jul 14 05:33:24 PM PDT 24 Jul 14 05:33:26 PM PDT 24 110544722 ps
T218 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3811557763 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:07 PM PDT 24 70240633 ps
T1834 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3101960858 Jul 14 05:33:04 PM PDT 24 Jul 14 05:33:08 PM PDT 24 42997954 ps
T1835 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4025324882 Jul 14 05:33:19 PM PDT 24 Jul 14 05:33:21 PM PDT 24 200249064 ps

Test location /workspace/coverage/default/46.i2c_host_perf.3484847998
Short name T1
Test name
Test status
Simulation time 27639556392 ps
CPU time 179.94 seconds
Started Jul 14 06:09:03 PM PDT 24
Finished Jul 14 06:12:05 PM PDT 24
Peak memory 249932 kb
Host smart-bc620b51-a2f7-458c-8e22-ddc1a1fff7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484847998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3484847998
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3624066468
Short name T3
Test name
Test status
Simulation time 814373045 ps
CPU time 4.01 seconds
Started Jul 14 06:08:00 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 213788 kb
Host smart-4132fd07-9987-4eec-87d5-7b4068b91dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624066468 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3624066468
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.428755513
Short name T2
Test name
Test status
Simulation time 9672099429 ps
CPU time 161.85 seconds
Started Jul 14 06:08:46 PM PDT 24
Finished Jul 14 06:11:29 PM PDT 24
Peak memory 641660 kb
Host smart-a98f4053-63da-47ab-aa11-ab052113880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428755513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.428755513
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2029327712
Short name T49
Test name
Test status
Simulation time 2302204450 ps
CPU time 11.89 seconds
Started Jul 14 06:00:25 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 214184 kb
Host smart-e650f425-478e-437a-81e8-32795e735c55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029327712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2029327712
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.946752778
Short name T96
Test name
Test status
Simulation time 144796136 ps
CPU time 2.35 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 204576 kb
Host smart-4982971c-cef3-4006-9595-436c8784eb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946752778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.946752778
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2459592251
Short name T18
Test name
Test status
Simulation time 17507583434 ps
CPU time 400.66 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:09:28 PM PDT 24
Peak memory 1219188 kb
Host smart-4b312598-fba2-4c46-8b88-107562f5037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459592251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2459592251
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.1926033291
Short name T57
Test name
Test status
Simulation time 28957014843 ps
CPU time 841.05 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:20:16 PM PDT 24
Peak memory 3963888 kb
Host smart-81cb34c2-0d81-48b3-a9b3-fe7a425187c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926033291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.1926033291
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.3736563770
Short name T46
Test name
Test status
Simulation time 149559501 ps
CPU time 1.4 seconds
Started Jul 14 06:04:01 PM PDT 24
Finished Jul 14 06:04:03 PM PDT 24
Peak memory 222408 kb
Host smart-b8665c24-ed1e-4926-8407-c4f2c2362635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736563770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.3736563770
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_host_override.1674811731
Short name T89
Test name
Test status
Simulation time 29496959 ps
CPU time 0.72 seconds
Started Jul 14 06:09:01 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 205152 kb
Host smart-fade4de1-23ad-4de2-8f63-b4812db963a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674811731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1674811731
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.27381284
Short name T22
Test name
Test status
Simulation time 662695188 ps
CPU time 7.41 seconds
Started Jul 14 06:06:38 PM PDT 24
Finished Jul 14 06:06:46 PM PDT 24
Peak memory 205396 kb
Host smart-14e84445-6b22-4788-9398-97992e08c3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27381284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.27381284
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2063684112
Short name T172
Test name
Test status
Simulation time 36342635 ps
CPU time 0.85 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:01:10 PM PDT 24
Peak memory 223780 kb
Host smart-348f8d7b-c933-4a90-b608-2a575bf165ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063684112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2063684112
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.739747678
Short name T31
Test name
Test status
Simulation time 11351200066 ps
CPU time 376.07 seconds
Started Jul 14 06:02:29 PM PDT 24
Finished Jul 14 06:08:46 PM PDT 24
Peak memory 890148 kb
Host smart-13937dcb-fddf-4722-a786-e9c7b507557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739747678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.739747678
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3009974940
Short name T34
Test name
Test status
Simulation time 140710553 ps
CPU time 1.15 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:33 PM PDT 24
Peak memory 205244 kb
Host smart-d4b789e5-ff15-4e08-8844-bca042fc760f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009974940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3009974940
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.1121067837
Short name T51
Test name
Test status
Simulation time 3344647663 ps
CPU time 2.62 seconds
Started Jul 14 06:03:10 PM PDT 24
Finished Jul 14 06:03:14 PM PDT 24
Peak memory 205668 kb
Host smart-c0a9ab73-4a97-4e42-b30f-a8297d415c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121067837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.1121067837
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.2130541041
Short name T59
Test name
Test status
Simulation time 1983436326 ps
CPU time 2.63 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:03:35 PM PDT 24
Peak memory 205608 kb
Host smart-5adc806e-847f-4182-9e89-935b117227a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130541041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.2130541041
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3040075724
Short name T187
Test name
Test status
Simulation time 438489204 ps
CPU time 1.82 seconds
Started Jul 14 05:33:06 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204584 kb
Host smart-7ebc8ddf-6321-4b87-857b-851fe1b2f198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040075724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3040075724
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2798796088
Short name T209
Test name
Test status
Simulation time 47012506 ps
CPU time 0.74 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 204436 kb
Host smart-f0f30d49-6f83-4f3a-b8d1-0489baa14224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798796088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2798796088
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1411279376
Short name T114
Test name
Test status
Simulation time 38815618237 ps
CPU time 604.16 seconds
Started Jul 14 06:06:42 PM PDT 24
Finished Jul 14 06:16:47 PM PDT 24
Peak memory 776084 kb
Host smart-8cd6c64e-94b8-46b8-9346-e2b8bf1d3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411279376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1411279376
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.1478936378
Short name T684
Test name
Test status
Simulation time 1956489905 ps
CPU time 2.55 seconds
Started Jul 14 06:04:45 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 213788 kb
Host smart-de4014a3-dd56-4a85-b68b-a7cce8098831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478936378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.1478936378
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.355194112
Short name T29
Test name
Test status
Simulation time 24542758410 ps
CPU time 70.19 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:05:57 PM PDT 24
Peak memory 935452 kb
Host smart-ee8a2997-04eb-4c50-934e-ee3fbc379b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355194112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.355194112
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3292761113
Short name T159
Test name
Test status
Simulation time 309925382 ps
CPU time 5.37 seconds
Started Jul 14 06:03:15 PM PDT 24
Finished Jul 14 06:03:21 PM PDT 24
Peak memory 234408 kb
Host smart-d07aa4bb-7642-458a-b0cb-b6a6aed04343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292761113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3292761113
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_alert_test.4038698815
Short name T523
Test name
Test status
Simulation time 17411171 ps
CPU time 0.65 seconds
Started Jul 14 06:01:09 PM PDT 24
Finished Jul 14 06:01:10 PM PDT 24
Peak memory 204796 kb
Host smart-be3aa6ae-8c70-424b-a726-1182496d319d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038698815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.4038698815
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.621088853
Short name T202
Test name
Test status
Simulation time 51955425157 ps
CPU time 36.51 seconds
Started Jul 14 06:08:52 PM PDT 24
Finished Jul 14 06:09:30 PM PDT 24
Peak memory 356636 kb
Host smart-57cb9fbe-4715-456a-8895-62a41d7c51fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621088853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.621088853
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2679758453
Short name T241
Test name
Test status
Simulation time 4524454340 ps
CPU time 7.36 seconds
Started Jul 14 06:04:11 PM PDT 24
Finished Jul 14 06:04:19 PM PDT 24
Peak memory 205516 kb
Host smart-c0dc2e54-690f-441d-81e8-3e9975b23be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679758453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2679758453
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1331531638
Short name T77
Test name
Test status
Simulation time 627532031 ps
CPU time 1.73 seconds
Started Jul 14 06:07:32 PM PDT 24
Finished Jul 14 06:07:34 PM PDT 24
Peak memory 205576 kb
Host smart-50664079-5523-4a78-9f1a-077c47c7c8e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331531638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1331531638
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2065294587
Short name T271
Test name
Test status
Simulation time 50552626 ps
CPU time 0.67 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 204356 kb
Host smart-d87241d5-b8f2-42e3-a6c2-b132d1bd6354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065294587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2065294587
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2346757528
Short name T167
Test name
Test status
Simulation time 1173569137 ps
CPU time 2.25 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:20 PM PDT 24
Peak memory 204508 kb
Host smart-5f836b00-b6f3-4457-83a1-3fea6a9163ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346757528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2346757528
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2399415774
Short name T255
Test name
Test status
Simulation time 92912556 ps
CPU time 1.68 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:27 PM PDT 24
Peak memory 205480 kb
Host smart-e4f3d155-040e-445a-a2e0-92ead57090be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399415774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2399415774
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_target_perf.9855010
Short name T282
Test name
Test status
Simulation time 3457809551 ps
CPU time 5.52 seconds
Started Jul 14 06:06:42 PM PDT 24
Finished Jul 14 06:06:48 PM PDT 24
Peak memory 219156 kb
Host smart-854641b9-a42c-4dd0-8ee3-58f97d739c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9855010 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.i2c_target_perf.9855010
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3472456721
Short name T224
Test name
Test status
Simulation time 61041832 ps
CPU time 0.88 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 204464 kb
Host smart-c57d7309-727d-445b-92fa-7a0edb6b8d60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472456721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3472456721
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.220781054
Short name T1757
Test name
Test status
Simulation time 21546604 ps
CPU time 0.69 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:27 PM PDT 24
Peak memory 204364 kb
Host smart-bc9f98de-465d-4aac-b49f-e43e41197d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220781054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.220781054
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4218032942
Short name T250
Test name
Test status
Simulation time 558190229 ps
CPU time 22.62 seconds
Started Jul 14 06:00:50 PM PDT 24
Finished Jul 14 06:01:13 PM PDT 24
Peak memory 205492 kb
Host smart-fe4f7b45-8603-4b46-b30d-71e8a08e219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218032942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4218032942
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.901627676
Short name T227
Test name
Test status
Simulation time 338157523 ps
CPU time 1.14 seconds
Started Jul 14 06:00:43 PM PDT 24
Finished Jul 14 06:00:44 PM PDT 24
Peak memory 205472 kb
Host smart-b5f3f59d-e5b6-4a23-8027-3874ecebc188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901627676 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.901627676
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.383940273
Short name T274
Test name
Test status
Simulation time 55269568196 ps
CPU time 125.08 seconds
Started Jul 14 06:00:43 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 1924188 kb
Host smart-bf0604f0-a02a-499f-b42d-ccaf5c2d6ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383940273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.383940273
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2534181608
Short name T233
Test name
Test status
Simulation time 101740963 ps
CPU time 1.35 seconds
Started Jul 14 06:02:50 PM PDT 24
Finished Jul 14 06:02:52 PM PDT 24
Peak memory 205312 kb
Host smart-0b757a58-4286-4bdc-82ac-6ad708321aa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534181608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2534181608
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3926044295
Short name T109
Test name
Test status
Simulation time 14372955266 ps
CPU time 684.83 seconds
Started Jul 14 06:03:13 PM PDT 24
Finished Jul 14 06:14:39 PM PDT 24
Peak memory 2407504 kb
Host smart-f6c58f1b-89e1-4bd6-9b2d-c9770995a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926044295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3926044295
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_perf.123359795
Short name T36
Test name
Test status
Simulation time 6356036517 ps
CPU time 262.17 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 218932 kb
Host smart-5ca2b0df-4f61-4c59-bb49-52810c131546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123359795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.123359795
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2321994532
Short name T253
Test name
Test status
Simulation time 50704959 ps
CPU time 1.1 seconds
Started Jul 14 05:33:07 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204440 kb
Host smart-d6190af1-77ef-4efc-803f-0851be1734f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321994532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2321994532
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.844853322
Short name T1656
Test name
Test status
Simulation time 492729222 ps
CPU time 3.41 seconds
Started Jul 14 06:02:51 PM PDT 24
Finished Jul 14 06:02:55 PM PDT 24
Peak memory 205408 kb
Host smart-d9c31c63-18f7-47d4-86c0-0a9c04e5fbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844853322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.844853322
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3327930902
Short name T405
Test name
Test status
Simulation time 3660582456 ps
CPU time 19.55 seconds
Started Jul 14 06:03:41 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 222008 kb
Host smart-2a6ea8a6-5eaa-47a0-b61e-87251075d2e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327930902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3327930902
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.3351517919
Short name T56
Test name
Test status
Simulation time 81331952 ps
CPU time 1.85 seconds
Started Jul 14 06:05:04 PM PDT 24
Finished Jul 14 06:05:06 PM PDT 24
Peak memory 205604 kb
Host smart-6e7a8f85-2239-4c5b-9387-b8766c144a25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351517919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.3351517919
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3463617116
Short name T186
Test name
Test status
Simulation time 253178163 ps
CPU time 1.53 seconds
Started Jul 14 05:33:17 PM PDT 24
Finished Jul 14 05:33:20 PM PDT 24
Peak memory 204568 kb
Host smart-42bab448-0422-401e-869a-f57605d4b99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463617116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3463617116
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.145733278
Short name T185
Test name
Test status
Simulation time 67902455 ps
CPU time 1.55 seconds
Started Jul 14 05:33:05 PM PDT 24
Finished Jul 14 05:33:09 PM PDT 24
Peak memory 204608 kb
Host smart-ce082263-399b-4c50-8b2b-0f5727c6048b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145733278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.145733278
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.907789699
Short name T192
Test name
Test status
Simulation time 175522815 ps
CPU time 1.39 seconds
Started Jul 14 05:33:15 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 204616 kb
Host smart-3dec61fd-159a-4e46-bd16-94d03f38f159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907789699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.907789699
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3605833741
Short name T191
Test name
Test status
Simulation time 83978950 ps
CPU time 1.42 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:26 PM PDT 24
Peak memory 204564 kb
Host smart-14ccaab5-b542-43bc-9f85-203409d98bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605833741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3605833741
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3629519080
Short name T11
Test name
Test status
Simulation time 72594182 ps
CPU time 1.3 seconds
Started Jul 14 06:03:12 PM PDT 24
Finished Jul 14 06:03:14 PM PDT 24
Peak memory 213872 kb
Host smart-4fa09b96-a5c0-4caa-aed4-7072eb52ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629519080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3629519080
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1154428992
Short name T673
Test name
Test status
Simulation time 1317414022 ps
CPU time 2.43 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 221828 kb
Host smart-736e5e63-8964-419d-a276-e920f3a5ea6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154428992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1154428992
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2553365073
Short name T23
Test name
Test status
Simulation time 66098782249 ps
CPU time 778.24 seconds
Started Jul 14 06:05:42 PM PDT 24
Finished Jul 14 06:18:41 PM PDT 24
Peak memory 2571348 kb
Host smart-f9ce6760-4ef7-4905-8a70-8c7f3168a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553365073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2553365073
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2023127142
Short name T205
Test name
Test status
Simulation time 191851047 ps
CPU time 1.25 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:32:58 PM PDT 24
Peak memory 204572 kb
Host smart-27a6fc91-9ba9-41aa-b4b4-7b24af81514a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023127142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2023127142
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.265098286
Short name T1776
Test name
Test status
Simulation time 705080326 ps
CPU time 2.84 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204580 kb
Host smart-d9dc0dc7-fa13-4fc4-891f-b46fd34bfbcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265098286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.265098286
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.202296932
Short name T208
Test name
Test status
Simulation time 25455316 ps
CPU time 0.85 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 204436 kb
Host smart-2a6cb0ea-66e4-4ba7-8f95-9b2a3d40bf3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202296932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.202296932
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.999403118
Short name T1814
Test name
Test status
Simulation time 21642870 ps
CPU time 0.9 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 204460 kb
Host smart-2a0565a8-b3f5-4c1d-86db-6d466909b4cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999403118 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.999403118
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2363407825
Short name T213
Test name
Test status
Simulation time 19999756 ps
CPU time 0.78 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204420 kb
Host smart-859d698a-7ca3-42ed-9e94-5d6384bdeafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363407825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2363407825
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.350383190
Short name T270
Test name
Test status
Simulation time 33357509 ps
CPU time 0.64 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 204252 kb
Host smart-179d3880-763c-4089-bf16-62f1b698a549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350383190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.350383190
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2975626336
Short name T1775
Test name
Test status
Simulation time 318565186 ps
CPU time 0.9 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204356 kb
Host smart-cee31f0c-3f8a-46df-9ef8-54ef4110ade8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975626336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2975626336
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.363268808
Short name T1824
Test name
Test status
Simulation time 47121582 ps
CPU time 2.49 seconds
Started Jul 14 05:32:54 PM PDT 24
Finished Jul 14 05:32:58 PM PDT 24
Peak memory 204524 kb
Host smart-db94d5ee-9d02-4279-a4e4-6eb5bd358a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363268808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.363268808
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.501893353
Short name T1826
Test name
Test status
Simulation time 162565619 ps
CPU time 1.46 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:32:58 PM PDT 24
Peak memory 204592 kb
Host smart-465afd92-aedf-4ccb-aae9-9518abfa77ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501893353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.501893353
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1393436594
Short name T1749
Test name
Test status
Simulation time 66453362 ps
CPU time 1.33 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 204612 kb
Host smart-a51a1b50-f640-40cc-945b-ff1c4258c49d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393436594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1393436594
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.629763844
Short name T1805
Test name
Test status
Simulation time 635610283 ps
CPU time 2.81 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204568 kb
Host smart-f0fb6d27-fa3a-44c5-b055-873f9fa551a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629763844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.629763844
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2331112939
Short name T1741
Test name
Test status
Simulation time 17349586 ps
CPU time 0.69 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 204392 kb
Host smart-098412e9-fec8-4495-bcdf-47fefced291b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331112939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2331112939
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.588820179
Short name T1747
Test name
Test status
Simulation time 38075788 ps
CPU time 1.01 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204500 kb
Host smart-ab34a2d8-9fa8-4986-8230-47446ce1db65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588820179 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.588820179
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3555925078
Short name T1736
Test name
Test status
Simulation time 42511912 ps
CPU time 0.66 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 204352 kb
Host smart-3fdaab64-288a-4aee-94b7-bc3e4e1c3f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555925078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3555925078
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2184553713
Short name T188
Test name
Test status
Simulation time 116506135 ps
CPU time 2.86 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 204628 kb
Host smart-087e5dbd-bd06-4985-aa0b-8c5aab2d83ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184553713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2184553713
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2216361578
Short name T166
Test name
Test status
Simulation time 153542763 ps
CPU time 2.34 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204632 kb
Host smart-14f80e56-09a0-4f60-8c93-a485a8d9287e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216361578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2216361578
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3526007651
Short name T1794
Test name
Test status
Simulation time 79677993 ps
CPU time 0.84 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204548 kb
Host smart-86b6589b-a7d5-42be-b62e-b205ffb93e20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526007651 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3526007651
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3977374398
Short name T216
Test name
Test status
Simulation time 63384270 ps
CPU time 0.7 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204308 kb
Host smart-f05a773d-3a22-4c19-8220-494d159632c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977374398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3977374398
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1677269925
Short name T1782
Test name
Test status
Simulation time 17341077 ps
CPU time 0.67 seconds
Started Jul 14 05:33:09 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204356 kb
Host smart-72a8a342-eb10-46d6-85b8-97b37356bc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677269925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1677269925
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1999049511
Short name T1756
Test name
Test status
Simulation time 48949214 ps
CPU time 1.14 seconds
Started Jul 14 05:33:08 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204500 kb
Host smart-a35ae9a9-e5c1-45e7-8f48-89b00a91c0ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999049511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1999049511
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.342550546
Short name T1802
Test name
Test status
Simulation time 114499325 ps
CPU time 2.53 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:14 PM PDT 24
Peak memory 204684 kb
Host smart-23a70621-5071-44d3-9103-7993e9bebdf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342550546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.342550546
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2195432367
Short name T190
Test name
Test status
Simulation time 51946017 ps
CPU time 1.45 seconds
Started Jul 14 05:33:09 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204508 kb
Host smart-f29f58aa-fc40-4336-9a0a-6d684fa5b65e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195432367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2195432367
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2065281983
Short name T1758
Test name
Test status
Simulation time 82851225 ps
CPU time 0.79 seconds
Started Jul 14 05:33:11 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204408 kb
Host smart-b7bfbe43-4c34-491e-8481-857703f172e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065281983 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2065281983
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2757439100
Short name T206
Test name
Test status
Simulation time 239451843 ps
CPU time 0.79 seconds
Started Jul 14 05:33:07 PM PDT 24
Finished Jul 14 05:33:09 PM PDT 24
Peak memory 204396 kb
Host smart-71e37f9d-bf8e-42cf-abe6-2168b27b8d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757439100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2757439100
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3555941425
Short name T1821
Test name
Test status
Simulation time 19260935 ps
CPU time 0.67 seconds
Started Jul 14 05:33:08 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204368 kb
Host smart-5b9d43b1-6fef-45ba-b471-d4f180cc30a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555941425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3555941425
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2696354255
Short name T1755
Test name
Test status
Simulation time 56908378 ps
CPU time 0.88 seconds
Started Jul 14 05:33:09 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204292 kb
Host smart-4ebeff94-9878-465b-a0a8-72191570f977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696354255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2696354255
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2654627808
Short name T103
Test name
Test status
Simulation time 59188430 ps
CPU time 1.33 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204548 kb
Host smart-dfec1763-2048-4b1b-adc9-cf3c58c2dac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654627808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2654627808
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.281504067
Short name T1764
Test name
Test status
Simulation time 72968090 ps
CPU time 1.48 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:13 PM PDT 24
Peak memory 204636 kb
Host smart-d2576983-942b-40e6-af25-81ee8ecb54b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281504067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.281504067
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.221003905
Short name T1784
Test name
Test status
Simulation time 28893896 ps
CPU time 1.27 seconds
Started Jul 14 05:33:08 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204664 kb
Host smart-5d6443c8-6c21-46ad-abfb-55e75da1f782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221003905 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.221003905
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3457417941
Short name T97
Test name
Test status
Simulation time 21587573 ps
CPU time 0.74 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204400 kb
Host smart-0d2da595-789e-40c3-858c-0e71a9c12bc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457417941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3457417941
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2616761586
Short name T1806
Test name
Test status
Simulation time 37554667 ps
CPU time 0.71 seconds
Started Jul 14 05:33:09 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204336 kb
Host smart-6d8d1b34-f292-4514-8b4f-f3ca2fe16118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616761586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2616761586
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3522339455
Short name T1793
Test name
Test status
Simulation time 226314372 ps
CPU time 1.62 seconds
Started Jul 14 05:33:10 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204524 kb
Host smart-fae52df6-61fb-4a0f-861a-73fdfc4d2fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522339455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3522339455
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.996894939
Short name T104
Test name
Test status
Simulation time 431113386 ps
CPU time 1.53 seconds
Started Jul 14 05:33:11 PM PDT 24
Finished Jul 14 05:33:13 PM PDT 24
Peak memory 204540 kb
Host smart-466a8b5e-cab2-4b93-b15b-e73a9df47852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996894939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.996894939
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.424810432
Short name T99
Test name
Test status
Simulation time 45764928 ps
CPU time 0.83 seconds
Started Jul 14 05:33:19 PM PDT 24
Finished Jul 14 05:33:21 PM PDT 24
Peak memory 204472 kb
Host smart-16565e7d-d587-447b-abbc-4588d9c6ba5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424810432 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.424810432
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1080211054
Short name T214
Test name
Test status
Simulation time 56571600 ps
CPU time 0.7 seconds
Started Jul 14 05:33:17 PM PDT 24
Finished Jul 14 05:33:19 PM PDT 24
Peak memory 204412 kb
Host smart-33812df3-fc47-4733-b641-9e12a2f64c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080211054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1080211054
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1443380638
Short name T1829
Test name
Test status
Simulation time 53196070 ps
CPU time 0.72 seconds
Started Jul 14 05:33:15 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 204356 kb
Host smart-36b30111-f5ec-4daa-adae-d69f1c6d0f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443380638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1443380638
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1035719086
Short name T220
Test name
Test status
Simulation time 98890875 ps
CPU time 0.85 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 204408 kb
Host smart-cee258cd-e578-4cac-862e-66f12a90277f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035719086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1035719086
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3267949094
Short name T1832
Test name
Test status
Simulation time 32694077 ps
CPU time 1.49 seconds
Started Jul 14 05:33:19 PM PDT 24
Finished Jul 14 05:33:21 PM PDT 24
Peak memory 204636 kb
Host smart-3602ef77-9fb4-4264-bcb0-78ce620f78fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267949094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3267949094
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.896967554
Short name T260
Test name
Test status
Simulation time 463231478 ps
CPU time 1.41 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:19 PM PDT 24
Peak memory 204632 kb
Host smart-9f02dcf9-73c9-4658-8b98-fc7c377cbc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896967554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.896967554
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3161254476
Short name T1746
Test name
Test status
Simulation time 309886762 ps
CPU time 0.84 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 204512 kb
Host smart-2d4abe39-f855-417a-bf8c-de8a5e07aa60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161254476 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3161254476
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4239312210
Short name T1783
Test name
Test status
Simulation time 21358492 ps
CPU time 0.73 seconds
Started Jul 14 05:33:15 PM PDT 24
Finished Jul 14 05:33:16 PM PDT 24
Peak memory 204436 kb
Host smart-a66c7575-7a81-4c0b-9df9-6519874567e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239312210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4239312210
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2343384927
Short name T1774
Test name
Test status
Simulation time 51902504 ps
CPU time 0.66 seconds
Started Jul 14 05:33:15 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 204316 kb
Host smart-2e33a381-57ce-48cb-81fb-c775cd0e3835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343384927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2343384927
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3890562328
Short name T221
Test name
Test status
Simulation time 32172654 ps
CPU time 1.23 seconds
Started Jul 14 05:33:14 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 204396 kb
Host smart-e00d513c-f88a-4346-b19c-8d959befe384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890562328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3890562328
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1944082198
Short name T105
Test name
Test status
Simulation time 362925900 ps
CPU time 3.38 seconds
Started Jul 14 05:33:14 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 204648 kb
Host smart-7dc8673f-a442-46b9-b00e-e5ed22678b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944082198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1944082198
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1837518989
Short name T170
Test name
Test status
Simulation time 124535923 ps
CPU time 1.78 seconds
Started Jul 14 05:33:17 PM PDT 24
Finished Jul 14 05:33:20 PM PDT 24
Peak memory 214224 kb
Host smart-96e4260c-1df0-46cb-9c73-9c024ddddce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837518989 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1837518989
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.587433356
Short name T1780
Test name
Test status
Simulation time 35814312 ps
CPU time 0.68 seconds
Started Jul 14 05:33:14 PM PDT 24
Finished Jul 14 05:33:16 PM PDT 24
Peak memory 204292 kb
Host smart-c497984c-861b-4674-9e3d-a8559a3f2003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587433356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.587433356
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1554904422
Short name T1750
Test name
Test status
Simulation time 16985870 ps
CPU time 0.67 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 204316 kb
Host smart-02568279-b31f-42a0-9634-f4a5850b284d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554904422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1554904422
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3450760595
Short name T1778
Test name
Test status
Simulation time 132501936 ps
CPU time 0.87 seconds
Started Jul 14 05:33:14 PM PDT 24
Finished Jul 14 05:33:15 PM PDT 24
Peak memory 204396 kb
Host smart-67bbed38-35d3-470f-950c-525a105511ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450760595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3450760595
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.860505368
Short name T1813
Test name
Test status
Simulation time 501655411 ps
CPU time 2.67 seconds
Started Jul 14 05:33:17 PM PDT 24
Finished Jul 14 05:33:21 PM PDT 24
Peak memory 204612 kb
Host smart-e59fd9e2-46e2-4ba2-9034-16b42dcc9b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860505368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.860505368
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1932604590
Short name T102
Test name
Test status
Simulation time 41277533 ps
CPU time 1.04 seconds
Started Jul 14 05:33:22 PM PDT 24
Finished Jul 14 05:33:24 PM PDT 24
Peak memory 204384 kb
Host smart-13095d20-c2ac-430a-a4cd-0f1eff459bd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932604590 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1932604590
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.794817700
Short name T1752
Test name
Test status
Simulation time 22334887 ps
CPU time 0.71 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:19 PM PDT 24
Peak memory 204420 kb
Host smart-e53aa41e-34ad-4a44-b2a8-356e1077c346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794817700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.794817700
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1394155015
Short name T1812
Test name
Test status
Simulation time 16576162 ps
CPU time 0.71 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 204352 kb
Host smart-25dd2fb7-778d-4155-8492-796c77c3f44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394155015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1394155015
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.609529669
Short name T1770
Test name
Test status
Simulation time 36853273 ps
CPU time 0.9 seconds
Started Jul 14 05:33:16 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 204432 kb
Host smart-60c02a6e-898a-4f5e-b011-d9e3aa1e84c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609529669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.609529669
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1016265436
Short name T1828
Test name
Test status
Simulation time 244668480 ps
CPU time 1.59 seconds
Started Jul 14 05:33:17 PM PDT 24
Finished Jul 14 05:33:20 PM PDT 24
Peak memory 204568 kb
Host smart-5e397c5e-a95a-4be4-968c-2d39d67ee549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016265436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1016265436
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.926098413
Short name T1765
Test name
Test status
Simulation time 39441886 ps
CPU time 0.83 seconds
Started Jul 14 05:33:24 PM PDT 24
Finished Jul 14 05:33:25 PM PDT 24
Peak memory 204440 kb
Host smart-3fd44e15-1f48-43bd-ab80-4e4e5ec09ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926098413 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.926098413
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1641680831
Short name T211
Test name
Test status
Simulation time 26883037 ps
CPU time 0.7 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:28 PM PDT 24
Peak memory 204424 kb
Host smart-708e592b-09e2-4cc3-95d9-697040cb98cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641680831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1641680831
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.691933242
Short name T1788
Test name
Test status
Simulation time 26389635 ps
CPU time 0.71 seconds
Started Jul 14 05:33:23 PM PDT 24
Finished Jul 14 05:33:24 PM PDT 24
Peak memory 204320 kb
Host smart-e0949050-faca-4d62-ba94-63ddeb1435ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691933242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.691933242
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4025324882
Short name T1835
Test name
Test status
Simulation time 200249064 ps
CPU time 1.1 seconds
Started Jul 14 05:33:19 PM PDT 24
Finished Jul 14 05:33:21 PM PDT 24
Peak memory 204448 kb
Host smart-5adcf69b-0c93-4030-b0bd-e9dd6f54d494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025324882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4025324882
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1438443761
Short name T184
Test name
Test status
Simulation time 44571138 ps
CPU time 1.35 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204564 kb
Host smart-fa0efd0f-e8c9-4f10-a097-cdeabe539fef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438443761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1438443761
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3070042156
Short name T195
Test name
Test status
Simulation time 49638468 ps
CPU time 1.42 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 204628 kb
Host smart-d5b1e7f9-ed2c-47ce-8a17-cbb66f678089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070042156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3070042156
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2018515826
Short name T100
Test name
Test status
Simulation time 27620553 ps
CPU time 0.85 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204508 kb
Host smart-04d63a76-6a19-48f9-9b8e-8d861b30175b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018515826 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2018515826
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1835432419
Short name T210
Test name
Test status
Simulation time 65929888 ps
CPU time 0.71 seconds
Started Jul 14 05:33:24 PM PDT 24
Finished Jul 14 05:33:25 PM PDT 24
Peak memory 204368 kb
Host smart-15988b23-fa0a-41ed-9b52-0233e6485884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835432419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1835432419
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3573984947
Short name T1753
Test name
Test status
Simulation time 45127489 ps
CPU time 0.63 seconds
Started Jul 14 05:33:21 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204372 kb
Host smart-768a1bcd-b1a8-418e-a7c4-ab4347f24f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573984947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3573984947
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1737319366
Short name T196
Test name
Test status
Simulation time 30713409 ps
CPU time 1.4 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 204516 kb
Host smart-5029af5d-1335-4086-a4dd-446e99eaed98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737319366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1737319366
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2245782930
Short name T199
Test name
Test status
Simulation time 552975043 ps
CPU time 2.33 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 204652 kb
Host smart-8d07c5bc-0f22-49a0-8c04-04ad008e0a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245782930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2245782930
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3300817773
Short name T1822
Test name
Test status
Simulation time 26260559 ps
CPU time 1.24 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204884 kb
Host smart-7926f3b8-0367-4733-9aec-2bb3c947f4c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300817773 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3300817773
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2620615025
Short name T225
Test name
Test status
Simulation time 33610694 ps
CPU time 0.74 seconds
Started Jul 14 05:33:21 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 204416 kb
Host smart-2ca5cf97-00bb-462e-a010-80635feed772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620615025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2620615025
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1330751423
Short name T117
Test name
Test status
Simulation time 25126570 ps
CPU time 0.66 seconds
Started Jul 14 05:33:21 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 204356 kb
Host smart-f15cb7b1-6818-4600-9dfa-c1f00b3148f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330751423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1330751423
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1780204591
Short name T1833
Test name
Test status
Simulation time 110544722 ps
CPU time 1.15 seconds
Started Jul 14 05:33:24 PM PDT 24
Finished Jul 14 05:33:26 PM PDT 24
Peak memory 204604 kb
Host smart-5dd6d248-d467-4e8f-b929-793cec2a9ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780204591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1780204591
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2798774298
Short name T1818
Test name
Test status
Simulation time 76381121 ps
CPU time 1.62 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204652 kb
Host smart-add57e8e-2cc6-4088-81ba-dfea936ae9e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798774298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2798774298
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1899281571
Short name T98
Test name
Test status
Simulation time 446148048 ps
CPU time 1.27 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 204528 kb
Host smart-97b1a0aa-1a00-4772-b924-0e0e0effc62c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899281571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1899281571
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3441969754
Short name T1762
Test name
Test status
Simulation time 616082190 ps
CPU time 2.82 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204584 kb
Host smart-2f01a21e-67ae-41ba-bade-a8d80e274857
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441969754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3441969754
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1862575040
Short name T200
Test name
Test status
Simulation time 34091997 ps
CPU time 0.7 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 204412 kb
Host smart-8950933e-0896-415b-a9f1-377a9fdf705d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862575040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1862575040
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1703899129
Short name T193
Test name
Test status
Simulation time 187773056 ps
CPU time 0.93 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 204504 kb
Host smart-bf3762b1-675b-429c-9fbf-0bf3d662f022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703899129 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1703899129
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3570347138
Short name T101
Test name
Test status
Simulation time 46753425 ps
CPU time 0.8 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 204420 kb
Host smart-2955bc11-6538-441b-aa12-a94334c0b732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570347138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3570347138
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1922675707
Short name T219
Test name
Test status
Simulation time 88798661 ps
CPU time 1.1 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 204604 kb
Host smart-35c1c509-4364-4b8a-aa61-de3e3a5aa1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922675707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1922675707
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2900282394
Short name T1792
Test name
Test status
Simulation time 124922572 ps
CPU time 1.84 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 204696 kb
Host smart-1ed51202-0d77-4c27-9c6f-023aa491b543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900282394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2900282394
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3974739741
Short name T189
Test name
Test status
Simulation time 505982565 ps
CPU time 2.01 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204476 kb
Host smart-a28263ce-7a1f-423c-9f44-7a966ee13607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974739741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3974739741
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.806079510
Short name T1796
Test name
Test status
Simulation time 47204853 ps
CPU time 0.74 seconds
Started Jul 14 05:33:23 PM PDT 24
Finished Jul 14 05:33:24 PM PDT 24
Peak memory 204352 kb
Host smart-fd45060a-1086-4912-b2e1-dec0de442bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806079510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.806079510
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2553732779
Short name T1740
Test name
Test status
Simulation time 18146254 ps
CPU time 0.69 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204360 kb
Host smart-cbb81a4f-1f44-447d-b5fd-9bafa8c12b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553732779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2553732779
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.302405110
Short name T1800
Test name
Test status
Simulation time 23248729 ps
CPU time 0.62 seconds
Started Jul 14 05:33:18 PM PDT 24
Finished Jul 14 05:33:20 PM PDT 24
Peak memory 204204 kb
Host smart-02da1fc5-ee1c-4402-9dd0-80a883cfbcce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302405110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.302405110
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3324568365
Short name T1763
Test name
Test status
Simulation time 19106579 ps
CPU time 0.68 seconds
Started Jul 14 05:33:20 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 204344 kb
Host smart-e5b6d5ec-04c3-4d70-be07-80250ecf4412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324568365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3324568365
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1820882558
Short name T1823
Test name
Test status
Simulation time 19445941 ps
CPU time 0.69 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 204352 kb
Host smart-8333284c-1229-446b-a879-3a5015eefd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820882558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1820882558
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.4178681918
Short name T1797
Test name
Test status
Simulation time 17281166 ps
CPU time 0.68 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:31 PM PDT 24
Peak memory 204356 kb
Host smart-1e23aedd-05da-4690-b82f-4aa331dcc835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178681918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4178681918
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3499013234
Short name T1791
Test name
Test status
Simulation time 16143189 ps
CPU time 0.66 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204208 kb
Host smart-ec6feac4-9910-441d-9cf4-eb53dceaf217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499013234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3499013234
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2156643532
Short name T1790
Test name
Test status
Simulation time 45005613 ps
CPU time 0.64 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:31 PM PDT 24
Peak memory 204356 kb
Host smart-63a60dc6-fa5f-4a7f-a723-4f8d025ed7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156643532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2156643532
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1706638216
Short name T1739
Test name
Test status
Simulation time 46567043 ps
CPU time 0.66 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204328 kb
Host smart-8f572ada-e4ee-45bf-a1c8-ee767d0e55fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706638216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1706638216
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2058776678
Short name T217
Test name
Test status
Simulation time 411078892 ps
CPU time 1.26 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204588 kb
Host smart-3b2e9c95-acc1-4393-bad4-01a7ffae7ba7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058776678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2058776678
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2924384024
Short name T1809
Test name
Test status
Simulation time 266408268 ps
CPU time 2.83 seconds
Started Jul 14 05:33:06 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204528 kb
Host smart-f1fe5f58-684f-4e81-99e1-8b1122de38f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924384024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2924384024
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2511535641
Short name T1789
Test name
Test status
Simulation time 47827412 ps
CPU time 0.7 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204420 kb
Host smart-bb68f461-ea8c-466a-9232-34dae07de4b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511535641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2511535641
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3219350681
Short name T1745
Test name
Test status
Simulation time 33411136 ps
CPU time 0.91 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204408 kb
Host smart-24ade730-5500-4720-ae2c-2d6cc07cdde8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219350681 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3219350681
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.655530431
Short name T1785
Test name
Test status
Simulation time 31278961 ps
CPU time 0.76 seconds
Started Jul 14 05:33:06 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204288 kb
Host smart-e02e95e0-451f-4324-a0f8-b35e657583e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655530431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.655530431
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.895064721
Short name T1761
Test name
Test status
Simulation time 156163723 ps
CPU time 0.69 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 204352 kb
Host smart-f8a01fd8-a39c-448d-bef3-d0c1d69dc97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895064721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.895064721
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.21737624
Short name T1766
Test name
Test status
Simulation time 33008142 ps
CPU time 0.87 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204380 kb
Host smart-f6267425-796d-4d7a-851c-9cb3b8ff058a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outs
tanding.21737624
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2696168136
Short name T197
Test name
Test status
Simulation time 126335834 ps
CPU time 2.62 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 204700 kb
Host smart-ba2b7b35-349d-4d0e-ab1f-bac4abc5f02e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696168136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2696168136
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2824440552
Short name T268
Test name
Test status
Simulation time 19003882 ps
CPU time 0.69 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 204356 kb
Host smart-53dfc61b-e280-4563-9bce-a3fe8f56aff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824440552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2824440552
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3514940427
Short name T1803
Test name
Test status
Simulation time 18226435 ps
CPU time 0.72 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:27 PM PDT 24
Peak memory 204364 kb
Host smart-c753fb78-916d-4b70-b534-cafbbebf6c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514940427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3514940427
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3925826534
Short name T1743
Test name
Test status
Simulation time 26544638 ps
CPU time 0.74 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204368 kb
Host smart-97f07a34-52f7-4580-a641-baa80f91b5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925826534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3925826534
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3663279303
Short name T1742
Test name
Test status
Simulation time 16642644 ps
CPU time 0.69 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204208 kb
Host smart-3b27bf79-9a2f-4261-bf4b-db1a13b00c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663279303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3663279303
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4266913139
Short name T1799
Test name
Test status
Simulation time 18650248 ps
CPU time 0.68 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:28 PM PDT 24
Peak memory 204216 kb
Host smart-cd879e4f-bc72-42ad-8a5a-dff1fe1c3d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266913139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4266913139
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3544766587
Short name T1751
Test name
Test status
Simulation time 33278892 ps
CPU time 0.7 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204348 kb
Host smart-e5e8a719-9e27-4b18-8cb1-b8a515599e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544766587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3544766587
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1534987387
Short name T1759
Test name
Test status
Simulation time 53306254 ps
CPU time 0.71 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:26 PM PDT 24
Peak memory 204348 kb
Host smart-4f5383cd-8a2f-4484-8346-54bc7d0f55ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534987387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1534987387
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.713957074
Short name T1744
Test name
Test status
Simulation time 48666873 ps
CPU time 0.65 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204348 kb
Host smart-c727e3e2-693f-41b4-9e1a-ee94f0fe101a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713957074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.713957074
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2749751645
Short name T118
Test name
Test status
Simulation time 28891182 ps
CPU time 0.69 seconds
Started Jul 14 05:33:29 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 204380 kb
Host smart-166dada9-2de7-4a08-ba7a-098f74f845d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749751645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2749751645
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1310787868
Short name T1798
Test name
Test status
Simulation time 19225134 ps
CPU time 0.68 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:26 PM PDT 24
Peak memory 204208 kb
Host smart-8a9bd08d-edc7-49c0-b5cd-981fcabc9280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310787868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1310787868
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2112939024
Short name T212
Test name
Test status
Simulation time 245720967 ps
CPU time 1.2 seconds
Started Jul 14 05:33:07 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204524 kb
Host smart-8c211e31-e0c8-42cc-9e1d-c1e0fdc17153
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112939024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2112939024
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1895635045
Short name T1737
Test name
Test status
Simulation time 62936992 ps
CPU time 2.52 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:09 PM PDT 24
Peak memory 204548 kb
Host smart-2d58f715-ddf7-4536-9514-de8c5fd7cdc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895635045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1895635045
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1013173667
Short name T1773
Test name
Test status
Simulation time 19665037 ps
CPU time 0.71 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204404 kb
Host smart-4354f740-7ab6-441a-afad-5170f089825b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013173667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1013173667
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2717769001
Short name T1786
Test name
Test status
Simulation time 237412506 ps
CPU time 1.02 seconds
Started Jul 14 05:33:06 PM PDT 24
Finished Jul 14 05:33:09 PM PDT 24
Peak memory 204524 kb
Host smart-f58668d2-e7bb-4720-9368-3ae2f475a754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717769001 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2717769001
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.142557516
Short name T207
Test name
Test status
Simulation time 23007287 ps
CPU time 0.76 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 204416 kb
Host smart-4a095231-61ad-4d55-809d-11a2dacb15d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142557516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.142557516
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3058858795
Short name T1777
Test name
Test status
Simulation time 37933752 ps
CPU time 0.65 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204344 kb
Host smart-2b6104a2-94f4-4e84-a909-a84cc53a1f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058858795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3058858795
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.933904065
Short name T223
Test name
Test status
Simulation time 180854114 ps
CPU time 1.17 seconds
Started Jul 14 05:33:05 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204492 kb
Host smart-7fdb9c14-d346-441c-bdf5-ae562786ba04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933904065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.933904065
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4136577942
Short name T1819
Test name
Test status
Simulation time 40074996 ps
CPU time 2.16 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204708 kb
Host smart-3d2212ac-b14d-4f15-bcca-af06c309f4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136577942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.4136577942
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2421452781
Short name T198
Test name
Test status
Simulation time 275269356 ps
CPU time 1.44 seconds
Started Jul 14 05:33:05 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204588 kb
Host smart-87aefd2c-fc5d-4050-900d-0d76389f9e91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421452781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2421452781
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3111286077
Short name T1816
Test name
Test status
Simulation time 49347817 ps
CPU time 0.64 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 204092 kb
Host smart-6bcb252d-747c-46b2-90c7-8e3ade5e23ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111286077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3111286077
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.40685702
Short name T119
Test name
Test status
Simulation time 34793662 ps
CPU time 0.77 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 204356 kb
Host smart-c4546a7c-4b83-43f3-86a6-b846e5a674bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.40685702
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1567006592
Short name T1738
Test name
Test status
Simulation time 22467705 ps
CPU time 0.68 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 204352 kb
Host smart-b753be20-171b-47af-8277-f53c1a52b7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567006592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1567006592
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1387492707
Short name T1815
Test name
Test status
Simulation time 54772000 ps
CPU time 0.71 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 204236 kb
Host smart-f01d0930-d8f5-4e4c-a620-88320b3b9ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387492707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1387492707
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.693606824
Short name T1804
Test name
Test status
Simulation time 48830012 ps
CPU time 0.7 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:28 PM PDT 24
Peak memory 204344 kb
Host smart-635a610c-3807-4584-b43c-4b4e371f4b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693606824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.693606824
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.854175296
Short name T1769
Test name
Test status
Simulation time 26713340 ps
CPU time 0.69 seconds
Started Jul 14 05:33:29 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 204352 kb
Host smart-8b8b7b49-4035-4e28-a3a5-ebf2e3df2258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854175296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.854175296
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3162367785
Short name T1801
Test name
Test status
Simulation time 25351611 ps
CPU time 0.65 seconds
Started Jul 14 05:33:26 PM PDT 24
Finished Jul 14 05:33:28 PM PDT 24
Peak memory 204312 kb
Host smart-705fc908-22a5-44a9-a931-620860660309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162367785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3162367785
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3229537648
Short name T1754
Test name
Test status
Simulation time 17512542 ps
CPU time 0.68 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:26 PM PDT 24
Peak memory 204272 kb
Host smart-87682447-2981-4ed8-812c-1168a90d0035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229537648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3229537648
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.853422277
Short name T1771
Test name
Test status
Simulation time 167852953 ps
CPU time 0.68 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204360 kb
Host smart-f8cc2553-82de-4031-ae30-33a723a46c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853422277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.853422277
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.25104508
Short name T272
Test name
Test status
Simulation time 35699138 ps
CPU time 0.71 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:29 PM PDT 24
Peak memory 204368 kb
Host smart-dca08ef7-6f3c-4720-b26a-8c1b20fff866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.25104508
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3093928568
Short name T1820
Test name
Test status
Simulation time 21488811 ps
CPU time 0.81 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204484 kb
Host smart-d8bca276-7ab5-4f78-af4d-94a0c70d669a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093928568 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3093928568
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3487925467
Short name T215
Test name
Test status
Simulation time 90176403 ps
CPU time 0.82 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204680 kb
Host smart-2e92a828-bf49-4fc0-b316-1fee60f10c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487925467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3487925467
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.489988582
Short name T1781
Test name
Test status
Simulation time 29448864 ps
CPU time 0.71 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 204364 kb
Host smart-38a1e323-3627-40de-b30a-0bff9da5d1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489988582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.489988582
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4041187967
Short name T1768
Test name
Test status
Simulation time 161356055 ps
CPU time 1.19 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204552 kb
Host smart-0daaa1d4-f96c-44c6-80a2-be8a4d18f6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041187967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4041187967
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.681202035
Short name T1825
Test name
Test status
Simulation time 173090189 ps
CPU time 2.55 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204660 kb
Host smart-a384e386-94e8-4d93-b1ce-abe6ebdd02d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681202035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.681202035
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1821220399
Short name T194
Test name
Test status
Simulation time 276849678 ps
CPU time 2.13 seconds
Started Jul 14 05:33:07 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204556 kb
Host smart-f5bb58a7-e723-4347-ba5d-5dbeeccf1a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821220399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1821220399
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.115701064
Short name T171
Test name
Test status
Simulation time 36162726 ps
CPU time 1 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204396 kb
Host smart-a79aa1a2-f3e5-4586-93ab-d4bab36aff1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115701064 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.115701064
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1681182420
Short name T1772
Test name
Test status
Simulation time 23246463 ps
CPU time 0.73 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204424 kb
Host smart-b4b84660-526c-4323-9a98-a6b80fe78398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681182420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1681182420
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2391209120
Short name T269
Test name
Test status
Simulation time 16034180 ps
CPU time 0.68 seconds
Started Jul 14 05:33:05 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204340 kb
Host smart-a2797ede-0350-4a71-88c4-d212f911eb81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391209120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2391209120
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4025302627
Short name T1779
Test name
Test status
Simulation time 402558571 ps
CPU time 1.25 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204624 kb
Host smart-eea4ddd9-c78d-4c1e-a710-9873f0c31634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025302627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4025302627
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.567373929
Short name T1817
Test name
Test status
Simulation time 183142668 ps
CPU time 1.24 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204716 kb
Host smart-cfcfd85a-4785-4408-819f-ad1c4448b3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567373929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.567373929
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3923259241
Short name T1767
Test name
Test status
Simulation time 90136073 ps
CPU time 1.52 seconds
Started Jul 14 05:33:06 PM PDT 24
Finished Jul 14 05:33:09 PM PDT 24
Peak memory 204580 kb
Host smart-5b93dee2-a46f-47e7-8fe4-fbc94a1dff4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923259241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3923259241
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1392674272
Short name T1831
Test name
Test status
Simulation time 31980696 ps
CPU time 1.37 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 212896 kb
Host smart-2eaeb4e9-f348-43a8-b709-c758c71b6874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392674272 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1392674272
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3811557763
Short name T218
Test name
Test status
Simulation time 70240633 ps
CPU time 0.78 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204332 kb
Host smart-400168cc-d37b-4329-ae0a-65d363e93b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811557763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3811557763
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.772900358
Short name T1807
Test name
Test status
Simulation time 86862833 ps
CPU time 0.68 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204316 kb
Host smart-7315580d-73cf-415d-a2cc-8bdae5fa9f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772900358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.772900358
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.820281725
Short name T1795
Test name
Test status
Simulation time 53673309 ps
CPU time 1.19 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204616 kb
Host smart-5a4bc6d8-bc4d-4488-b39d-89b0e180d3e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820281725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.820281725
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2267117699
Short name T1748
Test name
Test status
Simulation time 63499490 ps
CPU time 0.84 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 204424 kb
Host smart-0b2bbd66-9f42-4278-b9c7-3f04fa6abed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267117699 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2267117699
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2258209482
Short name T222
Test name
Test status
Simulation time 47361444 ps
CPU time 0.69 seconds
Started Jul 14 05:33:09 PM PDT 24
Finished Jul 14 05:33:11 PM PDT 24
Peak memory 204388 kb
Host smart-cbaebd6c-b91d-48b3-b2fc-8ba2101c6ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258209482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2258209482
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.4288490435
Short name T1808
Test name
Test status
Simulation time 20611630 ps
CPU time 0.74 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204344 kb
Host smart-9616fac8-e10f-4e8e-87a6-801f41ce8ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288490435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4288490435
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1736624593
Short name T1830
Test name
Test status
Simulation time 19499538 ps
CPU time 0.83 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204464 kb
Host smart-e7d556dd-94fe-465d-9825-4d2cadf23167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736624593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1736624593
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3487641924
Short name T1810
Test name
Test status
Simulation time 155818441 ps
CPU time 2.83 seconds
Started Jul 14 05:33:05 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204656 kb
Host smart-64293d92-b548-4312-b487-8de0a47aa9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487641924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3487641924
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2290339077
Short name T201
Test name
Test status
Simulation time 140819153 ps
CPU time 1.49 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 204512 kb
Host smart-18d7d906-2ea0-4007-9024-f89769e5aeed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290339077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2290339077
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.443983471
Short name T1827
Test name
Test status
Simulation time 78702921 ps
CPU time 0.9 seconds
Started Jul 14 05:33:11 PM PDT 24
Finished Jul 14 05:33:12 PM PDT 24
Peak memory 204416 kb
Host smart-6b343d0c-f6bc-41ea-ac8f-c97a9a57d354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443983471 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.443983471
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.51902607
Short name T1787
Test name
Test status
Simulation time 42611320 ps
CPU time 0.8 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204436 kb
Host smart-cad3fb94-3333-431d-82fc-8fe3f07e8a26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51902607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.51902607
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.611648369
Short name T1811
Test name
Test status
Simulation time 40000976 ps
CPU time 0.73 seconds
Started Jul 14 05:33:03 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 204368 kb
Host smart-5fae3dc7-39b8-46c7-9b5f-02fc6ee13cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611648369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.611648369
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3523016810
Short name T138
Test name
Test status
Simulation time 62709284 ps
CPU time 1.27 seconds
Started Jul 14 05:33:07 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 204516 kb
Host smart-d18472d8-9acf-4b25-9df6-c0a24979fb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523016810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3523016810
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3101960858
Short name T1834
Test name
Test status
Simulation time 42997954 ps
CPU time 2 seconds
Started Jul 14 05:33:04 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204640 kb
Host smart-32af3188-1d38-441e-8b6a-bb22e35aef81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101960858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3101960858
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1542855496
Short name T1760
Test name
Test status
Simulation time 105267852 ps
CPU time 1.53 seconds
Started Jul 14 05:33:02 PM PDT 24
Finished Jul 14 05:33:05 PM PDT 24
Peak memory 204596 kb
Host smart-06803a52-f503-4448-bb80-0673d1154049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542855496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1542855496
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1825958762
Short name T741
Test name
Test status
Simulation time 47847148 ps
CPU time 0.62 seconds
Started Jul 14 06:00:33 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 204812 kb
Host smart-3a5b93aa-e873-47b0-9bfa-e58827fc6289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825958762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1825958762
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2889804488
Short name T1297
Test name
Test status
Simulation time 206421611 ps
CPU time 9.72 seconds
Started Jul 14 06:00:25 PM PDT 24
Finished Jul 14 06:00:35 PM PDT 24
Peak memory 251092 kb
Host smart-3ebdbb3e-ae19-4a07-a878-51eaae91844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889804488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2889804488
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2936532957
Short name T396
Test name
Test status
Simulation time 3128167986 ps
CPU time 6.98 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:36 PM PDT 24
Peak memory 273156 kb
Host smart-8bab23ed-6b99-4ac3-914d-7cdb963a305a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936532957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2936532957
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.588111035
Short name T1399
Test name
Test status
Simulation time 9344043860 ps
CPU time 138.91 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 424136 kb
Host smart-4bc8d17b-1762-4f1e-9029-2f8a5c4f3de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588111035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.588111035
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2799889956
Short name T810
Test name
Test status
Simulation time 3437818134 ps
CPU time 37.66 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:01:05 PM PDT 24
Peak memory 546664 kb
Host smart-2c81bf97-cd87-4bba-b7ae-b92d47e58fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799889956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2799889956
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2186052419
Short name T732
Test name
Test status
Simulation time 143796837 ps
CPU time 0.84 seconds
Started Jul 14 06:00:25 PM PDT 24
Finished Jul 14 06:00:26 PM PDT 24
Peak memory 205216 kb
Host smart-cc73d4fb-230f-47cd-bf19-03caa471e65d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186052419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2186052419
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1546776375
Short name T639
Test name
Test status
Simulation time 452050229 ps
CPU time 11.11 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:00:41 PM PDT 24
Peak memory 205496 kb
Host smart-722ff35b-20ad-465d-8821-f79050a86404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546776375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1546776375
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2914661003
Short name T755
Test name
Test status
Simulation time 18386115235 ps
CPU time 137.02 seconds
Started Jul 14 06:00:29 PM PDT 24
Finished Jul 14 06:02:47 PM PDT 24
Peak memory 1306480 kb
Host smart-3b1336cf-f42d-4e8c-9bc8-8bde6056bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914661003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2914661003
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.534677604
Short name T578
Test name
Test status
Simulation time 373229390 ps
CPU time 1.94 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 205448 kb
Host smart-c966282b-17c0-4a66-b6e5-4c1eda37f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534677604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.534677604
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.4065726945
Short name T1145
Test name
Test status
Simulation time 30565894 ps
CPU time 0.76 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 205180 kb
Host smart-fecb4a1d-0aa7-4002-8e78-2856c0b81e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065726945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4065726945
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1071038680
Short name T15
Test name
Test status
Simulation time 26252138356 ps
CPU time 1106.23 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:18:55 PM PDT 24
Peak memory 248272 kb
Host smart-c0acd198-61b7-4029-b430-ece574055dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071038680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1071038680
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.1680391089
Short name T917
Test name
Test status
Simulation time 6339521598 ps
CPU time 57.67 seconds
Started Jul 14 06:00:29 PM PDT 24
Finished Jul 14 06:01:28 PM PDT 24
Peak memory 205768 kb
Host smart-7ca622b1-61e0-4780-a311-81efdc97783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680391089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.1680391089
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3111249331
Short name T534
Test name
Test status
Simulation time 6460797188 ps
CPU time 29.41 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:57 PM PDT 24
Peak memory 326624 kb
Host smart-6d564f20-1e6d-4653-b86c-ef8c3998d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111249331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3111249331
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2445513889
Short name T1336
Test name
Test status
Simulation time 622386032 ps
CPU time 11.01 seconds
Started Jul 14 06:00:25 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 213672 kb
Host smart-ca04e65d-9875-4c1d-ac09-223d22557f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445513889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2445513889
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1381067510
Short name T173
Test name
Test status
Simulation time 184081831 ps
CPU time 0.84 seconds
Started Jul 14 06:00:39 PM PDT 24
Finished Jul 14 06:00:40 PM PDT 24
Peak memory 223812 kb
Host smart-182231de-1456-4b51-b1b2-dfb1169df700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381067510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1381067510
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1619613399
Short name T470
Test name
Test status
Simulation time 1616727727 ps
CPU time 7.75 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:36 PM PDT 24
Peak memory 221056 kb
Host smart-3a4cc2a0-5c1e-4ff7-a58a-d169286af344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619613399 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1619613399
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3516658711
Short name T82
Test name
Test status
Simulation time 546236737 ps
CPU time 0.76 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:27 PM PDT 24
Peak memory 205400 kb
Host smart-998ada2d-f67a-42fc-8186-faafa0253d2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516658711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3516658711
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3877079052
Short name T929
Test name
Test status
Simulation time 241821522 ps
CPU time 1.02 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:27 PM PDT 24
Peak memory 205444 kb
Host smart-7db27c11-8ac7-4f9c-b007-c26b3c8c6ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877079052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3877079052
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1909201948
Short name T1392
Test name
Test status
Simulation time 1622767292 ps
CPU time 2.41 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:31 PM PDT 24
Peak memory 205664 kb
Host smart-fcf2842e-fa99-4eb9-9f27-58b9c42116da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909201948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1909201948
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.221879050
Short name T522
Test name
Test status
Simulation time 640083143 ps
CPU time 1.13 seconds
Started Jul 14 06:00:29 PM PDT 24
Finished Jul 14 06:00:31 PM PDT 24
Peak memory 205424 kb
Host smart-d64a779b-00ca-46d3-ba04-e63b351c734f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221879050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.221879050
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3748018609
Short name T1670
Test name
Test status
Simulation time 3974460216 ps
CPU time 5.8 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 222636 kb
Host smart-ef5a061f-61bd-4ee7-9ebc-5622d0f29092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748018609 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3748018609
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3475181460
Short name T726
Test name
Test status
Simulation time 10182549412 ps
CPU time 23.65 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:52 PM PDT 24
Peak memory 674972 kb
Host smart-a373d89c-d601-4d29-9884-b42fe7cfcd37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475181460 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3475181460
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.2476425220
Short name T404
Test name
Test status
Simulation time 2372350579 ps
CPU time 2.9 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 213888 kb
Host smart-b2fc76c9-8d38-4177-90b2-c333b7314ceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476425220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.2476425220
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.2584506703
Short name T1585
Test name
Test status
Simulation time 639941362 ps
CPU time 2.82 seconds
Started Jul 14 06:00:25 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 205944 kb
Host smart-d16d3f59-fdee-4b74-8b02-006a18e6a440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584506703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2584506703
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.3916503652
Short name T1198
Test name
Test status
Simulation time 560467640 ps
CPU time 1.39 seconds
Started Jul 14 06:00:33 PM PDT 24
Finished Jul 14 06:00:35 PM PDT 24
Peak memory 222376 kb
Host smart-756967ba-d965-4da8-9152-9bbb12c66f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916503652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.3916503652
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.1438357259
Short name T439
Test name
Test status
Simulation time 3150381811 ps
CPU time 4.5 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 222056 kb
Host smart-9e21744e-e17c-480b-a025-b265b8fc191d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438357259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.1438357259
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.721642970
Short name T1015
Test name
Test status
Simulation time 3337650646 ps
CPU time 2.47 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 205468 kb
Host smart-af6527dd-24f5-4bc7-8ba7-7cf0dac9ebba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721642970 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_smbus_maxlen.721642970
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1758539860
Short name T1611
Test name
Test status
Simulation time 2183584473 ps
CPU time 35.02 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:01:05 PM PDT 24
Peak memory 213844 kb
Host smart-9e2a3e74-48bb-4e09-9cce-1e11187c6729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758539860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1758539860
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.570500418
Short name T1375
Test name
Test status
Simulation time 29572723876 ps
CPU time 63.9 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:01:33 PM PDT 24
Peak memory 508596 kb
Host smart-12b0b7d2-5e64-4d26-ab47-04571fd331e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570500418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.570500418
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.476481584
Short name T869
Test name
Test status
Simulation time 1374091671 ps
CPU time 22.92 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:49 PM PDT 24
Peak memory 238136 kb
Host smart-69f57b56-42f2-4b40-a15d-f698d1accda1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476481584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.476481584
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.173649140
Short name T1206
Test name
Test status
Simulation time 45346819136 ps
CPU time 973.08 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:16:40 PM PDT 24
Peak memory 6631396 kb
Host smart-7188d634-5837-4554-b06c-fc86c96bc108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173649140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.173649140
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3528241119
Short name T1222
Test name
Test status
Simulation time 1522412226 ps
CPU time 3.29 seconds
Started Jul 14 06:00:30 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 213848 kb
Host smart-1a40b922-9aae-4c45-9b78-646857a44840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528241119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3528241119
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2754608594
Short name T1330
Test name
Test status
Simulation time 2674619954 ps
CPU time 7.42 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 230108 kb
Host smart-4eaf1dcb-d176-46b4-a96a-b30bd48cd8e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754608594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2754608594
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.251386442
Short name T606
Test name
Test status
Simulation time 101810159 ps
CPU time 2.33 seconds
Started Jul 14 06:00:28 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 205584 kb
Host smart-715ef50d-cfbc-4c1f-9522-e4208b233801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251386442 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.251386442
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1169629131
Short name T420
Test name
Test status
Simulation time 326896977 ps
CPU time 1.46 seconds
Started Jul 14 06:00:35 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 213772 kb
Host smart-3a099341-c81f-41ed-8f75-0559ac8fb76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169629131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1169629131
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.994280993
Short name T840
Test name
Test status
Simulation time 723138604 ps
CPU time 7.65 seconds
Started Jul 14 06:00:32 PM PDT 24
Finished Jul 14 06:00:40 PM PDT 24
Peak memory 277580 kb
Host smart-95793da6-c60e-4117-88db-57273842860a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994280993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.994280993
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3730071255
Short name T1212
Test name
Test status
Simulation time 12040381451 ps
CPU time 193.31 seconds
Started Jul 14 06:00:34 PM PDT 24
Finished Jul 14 06:03:48 PM PDT 24
Peak memory 606736 kb
Host smart-c1095f1f-5b4d-4188-9fd9-690bfffbcfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730071255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3730071255
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1817379072
Short name T927
Test name
Test status
Simulation time 9473584477 ps
CPU time 62.09 seconds
Started Jul 14 06:00:33 PM PDT 24
Finished Jul 14 06:01:36 PM PDT 24
Peak memory 677596 kb
Host smart-cd64ab85-eab5-4ce4-b442-4ac50f778231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817379072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1817379072
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.56323160
Short name T1197
Test name
Test status
Simulation time 211125562 ps
CPU time 1 seconds
Started Jul 14 06:00:41 PM PDT 24
Finished Jul 14 06:00:42 PM PDT 24
Peak memory 205236 kb
Host smart-0e64724c-f994-4263-b3fe-6c8e6e030268
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56323160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.56323160
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.696400905
Short name T730
Test name
Test status
Simulation time 557416377 ps
CPU time 3.83 seconds
Started Jul 14 06:00:39 PM PDT 24
Finished Jul 14 06:00:43 PM PDT 24
Peak memory 226888 kb
Host smart-51791570-2808-4f6a-be8c-df6d56d4120d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696400905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.696400905
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.823250687
Short name T899
Test name
Test status
Simulation time 4650967114 ps
CPU time 145.26 seconds
Started Jul 14 06:00:35 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 1337748 kb
Host smart-7c2338e4-1017-4c00-ba21-351e91112d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823250687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.823250687
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.1338893457
Short name T131
Test name
Test status
Simulation time 93965733 ps
CPU time 0.68 seconds
Started Jul 14 06:00:33 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 205192 kb
Host smart-2f9a35a0-b532-41e5-892d-b951141babbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338893457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1338893457
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2391845648
Short name T675
Test name
Test status
Simulation time 2911773486 ps
CPU time 149.46 seconds
Started Jul 14 06:00:32 PM PDT 24
Finished Jul 14 06:03:02 PM PDT 24
Peak memory 759428 kb
Host smart-bc9da94c-bc48-4b70-a4e7-36bbc5406955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391845648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2391845648
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2354660415
Short name T1588
Test name
Test status
Simulation time 24620783115 ps
CPU time 71.87 seconds
Started Jul 14 06:00:33 PM PDT 24
Finished Jul 14 06:01:46 PM PDT 24
Peak memory 213712 kb
Host smart-c2f74bbd-0450-4bf1-89b6-aa49037660de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354660415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2354660415
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4158067680
Short name T984
Test name
Test status
Simulation time 3893340853 ps
CPU time 38.54 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 406324 kb
Host smart-494315cb-cd1e-47e0-8db2-5021602a3e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158067680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4158067680
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2408621539
Short name T1707
Test name
Test status
Simulation time 827800804 ps
CPU time 15.03 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:56 PM PDT 24
Peak memory 221772 kb
Host smart-b2c42de4-14f5-4f0b-95cd-10ef84035de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408621539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2408621539
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.194696456
Short name T175
Test name
Test status
Simulation time 151491332 ps
CPU time 0.96 seconds
Started Jul 14 06:01:10 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 223752 kb
Host smart-3fa4b094-af42-4121-b87d-ae2e0e2abed6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194696456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.194696456
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1564567328
Short name T1542
Test name
Test status
Simulation time 2601784429 ps
CPU time 6.25 seconds
Started Jul 14 06:00:41 PM PDT 24
Finished Jul 14 06:00:48 PM PDT 24
Peak memory 214112 kb
Host smart-42fd4ea7-9c86-4c21-b6f9-42c66e8344b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564567328 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1564567328
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.287012826
Short name T1123
Test name
Test status
Simulation time 125470131 ps
CPU time 0.96 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:41 PM PDT 24
Peak memory 205432 kb
Host smart-452d62b0-fd6c-4267-9bb0-6718479e3063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287012826 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.287012826
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.3455856005
Short name T1526
Test name
Test status
Simulation time 1156857946 ps
CPU time 3.27 seconds
Started Jul 14 06:00:59 PM PDT 24
Finished Jul 14 06:01:02 PM PDT 24
Peak memory 205636 kb
Host smart-53f043ab-1b0a-4602-a4e7-1aa86dc7eea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455856005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.3455856005
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2327259554
Short name T1002
Test name
Test status
Simulation time 651048979 ps
CPU time 1.48 seconds
Started Jul 14 06:00:57 PM PDT 24
Finished Jul 14 06:00:59 PM PDT 24
Peak memory 205436 kb
Host smart-bc833bf2-9903-427e-8608-500045ef09d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327259554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2327259554
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.270872220
Short name T50
Test name
Test status
Simulation time 9555557703 ps
CPU time 11.03 seconds
Started Jul 14 06:00:35 PM PDT 24
Finished Jul 14 06:00:46 PM PDT 24
Peak memory 214188 kb
Host smart-f9fc701a-f7c8-4722-a036-2dce8151b86f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270872220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.270872220
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2433857706
Short name T1703
Test name
Test status
Simulation time 1029284875 ps
CPU time 6.72 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:47 PM PDT 24
Peak memory 216932 kb
Host smart-df5f04bc-375a-4e98-8884-5d455bf636ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433857706 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2433857706
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3235501388
Short name T1148
Test name
Test status
Simulation time 4985356647 ps
CPU time 22.1 seconds
Started Jul 14 06:00:38 PM PDT 24
Finished Jul 14 06:01:01 PM PDT 24
Peak memory 726412 kb
Host smart-de90175a-be86-4d7d-b568-5be6755e92df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235501388 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3235501388
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.4093071436
Short name T1335
Test name
Test status
Simulation time 485080677 ps
CPU time 2.91 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 213732 kb
Host smart-1aa5032a-b9e0-490a-8d9e-77f2feaa1ec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093071436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.4093071436
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.1316928545
Short name T1305
Test name
Test status
Simulation time 1832957901 ps
CPU time 2.42 seconds
Started Jul 14 06:01:04 PM PDT 24
Finished Jul 14 06:01:07 PM PDT 24
Peak memory 205596 kb
Host smart-bcad68bd-04d5-4e8e-a7a0-5cef0c0dae4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316928545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1316928545
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.2822379246
Short name T1122
Test name
Test status
Simulation time 957571441 ps
CPU time 5.05 seconds
Started Jul 14 06:00:38 PM PDT 24
Finished Jul 14 06:00:44 PM PDT 24
Peak memory 221968 kb
Host smart-c75acf7c-2b23-409f-b3e1-f0ec4fa1dc28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822379246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.2822379246
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.2756920715
Short name T1454
Test name
Test status
Simulation time 563744847 ps
CPU time 2.78 seconds
Started Jul 14 06:01:00 PM PDT 24
Finished Jul 14 06:01:03 PM PDT 24
Peak memory 205384 kb
Host smart-2fadaf04-ee5d-4e83-b3b3-e1d15179ef9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756920715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.2756920715
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.595990304
Short name T1456
Test name
Test status
Simulation time 4520299385 ps
CPU time 12.81 seconds
Started Jul 14 06:00:39 PM PDT 24
Finished Jul 14 06:00:52 PM PDT 24
Peak memory 213864 kb
Host smart-2ec08736-9fc2-4a31-885e-2739905d4948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595990304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.595990304
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3922942544
Short name T1447
Test name
Test status
Simulation time 1687282205 ps
CPU time 7.97 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:49 PM PDT 24
Peak memory 205612 kb
Host smart-86a4474a-0f46-4a1c-9d22-0bbe813f13b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922942544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3922942544
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.602063074
Short name T1195
Test name
Test status
Simulation time 55049462615 ps
CPU time 1733.97 seconds
Started Jul 14 06:00:39 PM PDT 24
Finished Jul 14 06:29:34 PM PDT 24
Peak memory 8067124 kb
Host smart-2a030de6-f207-4019-8146-4b18fc5b57d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602063074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.602063074
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1724980429
Short name T979
Test name
Test status
Simulation time 985547397 ps
CPU time 3.54 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:44 PM PDT 24
Peak memory 221872 kb
Host smart-1e9a379d-80b4-41e8-bcff-049d824d3ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724980429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1724980429
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1643702233
Short name T69
Test name
Test status
Simulation time 1277789569 ps
CPU time 6.87 seconds
Started Jul 14 06:00:40 PM PDT 24
Finished Jul 14 06:00:47 PM PDT 24
Peak memory 221956 kb
Host smart-3f704070-e292-44ee-80a7-baaa8b16d9f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643702233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1643702233
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.1778259649
Short name T473
Test name
Test status
Simulation time 151879292 ps
CPU time 3.38 seconds
Started Jul 14 06:00:59 PM PDT 24
Finished Jul 14 06:01:03 PM PDT 24
Peak memory 206692 kb
Host smart-ec6e97d4-f8b1-43d1-a51b-c274cd0470c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778259649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1778259649
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.57868367
Short name T703
Test name
Test status
Simulation time 15591843 ps
CPU time 0.65 seconds
Started Jul 14 06:03:02 PM PDT 24
Finished Jul 14 06:03:03 PM PDT 24
Peak memory 204752 kb
Host smart-5d18aeaf-b632-4d00-9af3-df4bfd4ddbc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57868367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.57868367
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.497226372
Short name T294
Test name
Test status
Simulation time 688090393 ps
CPU time 6.21 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:02:54 PM PDT 24
Peak memory 254396 kb
Host smart-e60a957c-7a0b-40d8-92b6-2861b72b2b3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497226372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.497226372
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1994669392
Short name T1663
Test name
Test status
Simulation time 62385670843 ps
CPU time 80.02 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:04:15 PM PDT 24
Peak memory 346492 kb
Host smart-ac8ae562-ce1a-40b6-9192-3c31a3b9d4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994669392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1994669392
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1292851932
Short name T1372
Test name
Test status
Simulation time 2126098134 ps
CPU time 113.69 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 610040 kb
Host smart-7487de7c-fb10-4589-b7ac-a79ba6771ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292851932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1292851932
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1710538379
Short name T1623
Test name
Test status
Simulation time 4399983412 ps
CPU time 4.9 seconds
Started Jul 14 06:02:44 PM PDT 24
Finished Jul 14 06:02:50 PM PDT 24
Peak memory 205504 kb
Host smart-f9738f06-fc02-44ed-a597-60abec39453f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710538379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1710538379
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.4248985246
Short name T694
Test name
Test status
Simulation time 21492929441 ps
CPU time 306.45 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:07:54 PM PDT 24
Peak memory 1240884 kb
Host smart-d180263e-5334-4255-99d1-01273d5bb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248985246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.4248985246
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_override.4244644650
Short name T968
Test name
Test status
Simulation time 338023163 ps
CPU time 0.66 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:02:47 PM PDT 24
Peak memory 205196 kb
Host smart-73865b98-fb3c-4a7c-80aa-5f1efe87d724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244644650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.4244644650
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3407847064
Short name T1482
Test name
Test status
Simulation time 2613613055 ps
CPU time 58.69 seconds
Started Jul 14 06:02:45 PM PDT 24
Finished Jul 14 06:03:44 PM PDT 24
Peak memory 764620 kb
Host smart-f0a386fb-6db9-4ebe-82bd-af4b68501fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407847064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3407847064
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1079379457
Short name T933
Test name
Test status
Simulation time 1752456863 ps
CPU time 23.46 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 352368 kb
Host smart-548489e8-35d4-47c6-90a7-e800753892a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079379457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1079379457
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.152226935
Short name T1383
Test name
Test status
Simulation time 1921701800 ps
CPU time 32.48 seconds
Started Jul 14 06:02:48 PM PDT 24
Finished Jul 14 06:03:21 PM PDT 24
Peak memory 378472 kb
Host smart-bedabd0d-4d96-4c62-8844-a88ad9284b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152226935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.152226935
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.138675007
Short name T894
Test name
Test status
Simulation time 916765587 ps
CPU time 14.58 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:03:02 PM PDT 24
Peak memory 238292 kb
Host smart-78fb3e25-46c5-4a14-bb65-eb656308a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138675007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.138675007
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1007964688
Short name T1334
Test name
Test status
Simulation time 3430143810 ps
CPU time 4.32 seconds
Started Jul 14 06:02:55 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 213912 kb
Host smart-1f8acc61-cfaf-4f75-8dc7-538ac6e6a902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007964688 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1007964688
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2492625698
Short name T1507
Test name
Test status
Simulation time 157097640 ps
CPU time 0.87 seconds
Started Jul 14 06:02:51 PM PDT 24
Finished Jul 14 06:02:53 PM PDT 24
Peak memory 205380 kb
Host smart-568bda00-3b34-4932-aa1a-698b6304980d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492625698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2492625698
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3598604799
Short name T679
Test name
Test status
Simulation time 262030555 ps
CPU time 0.88 seconds
Started Jul 14 06:02:55 PM PDT 24
Finished Jul 14 06:02:57 PM PDT 24
Peak memory 205420 kb
Host smart-192d54e3-6529-4659-8508-23b69b84e8c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598604799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3598604799
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.2453106358
Short name T1192
Test name
Test status
Simulation time 973343637 ps
CPU time 2.55 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:02:57 PM PDT 24
Peak memory 205640 kb
Host smart-81726884-7887-4104-b742-dd6e8cb31220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453106358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.2453106358
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2003250212
Short name T751
Test name
Test status
Simulation time 280677307 ps
CPU time 1.2 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:02:56 PM PDT 24
Peak memory 205364 kb
Host smart-47661e00-de54-48c5-879e-79b0841dfa5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003250212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2003250212
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.4218877592
Short name T1180
Test name
Test status
Simulation time 1475595853 ps
CPU time 2.41 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:02:58 PM PDT 24
Peak memory 215412 kb
Host smart-feda43ea-0fe5-4b59-a599-b9eb7fcf3d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218877592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.4218877592
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3320374119
Short name T1073
Test name
Test status
Simulation time 8866566091 ps
CPU time 8.66 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:02:57 PM PDT 24
Peak memory 220668 kb
Host smart-1ba3b6eb-2528-4dcd-b26e-661d605571c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320374119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3320374119
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1681355446
Short name T1098
Test name
Test status
Simulation time 18134167736 ps
CPU time 403.26 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 4244684 kb
Host smart-3907ffb7-0dd5-441a-a72d-b924eb1fbea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681355446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1681355446
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.1721606990
Short name T146
Test name
Test status
Simulation time 799832163 ps
CPU time 2.86 seconds
Started Jul 14 06:02:55 PM PDT 24
Finished Jul 14 06:02:58 PM PDT 24
Peak memory 213804 kb
Host smart-608216c8-90e1-45a0-b63c-be59ce4f5a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721606990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.1721606990
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.3749704315
Short name T1350
Test name
Test status
Simulation time 622050783 ps
CPU time 2.48 seconds
Started Jul 14 06:03:07 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 205532 kb
Host smart-33c9dd69-54f2-4ca0-9443-b7201a7682f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749704315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.3749704315
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.1232673421
Short name T595
Test name
Test status
Simulation time 147413925 ps
CPU time 1.41 seconds
Started Jul 14 06:03:03 PM PDT 24
Finished Jul 14 06:03:04 PM PDT 24
Peak memory 222204 kb
Host smart-f6846bbe-4d4b-40b0-938a-d867f7e17f71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232673421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_nack_txstretch.1232673421
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2853201932
Short name T1285
Test name
Test status
Simulation time 2227707947 ps
CPU time 4.24 seconds
Started Jul 14 06:02:55 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 216200 kb
Host smart-53123804-c462-405a-9053-9f31d57f1858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853201932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2853201932
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2528661898
Short name T1485
Test name
Test status
Simulation time 1611559086 ps
CPU time 2.12 seconds
Started Jul 14 06:02:51 PM PDT 24
Finished Jul 14 06:02:54 PM PDT 24
Peak memory 205420 kb
Host smart-17abcb3e-93b2-445a-a4d9-6ad521b12259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528661898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2528661898
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1052802003
Short name T1632
Test name
Test status
Simulation time 1112603036 ps
CPU time 14.6 seconds
Started Jul 14 06:02:44 PM PDT 24
Finished Jul 14 06:02:59 PM PDT 24
Peak memory 213804 kb
Host smart-dcf2887d-735c-4ff5-8b2e-fc110ec02ed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052802003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1052802003
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.322445432
Short name T335
Test name
Test status
Simulation time 42901385283 ps
CPU time 58 seconds
Started Jul 14 06:02:54 PM PDT 24
Finished Jul 14 06:03:53 PM PDT 24
Peak memory 328632 kb
Host smart-9d9d466c-b33a-418c-be42-5dfd3e5dc9e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322445432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_target_stress_all.322445432
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2322148961
Short name T1193
Test name
Test status
Simulation time 914884037 ps
CPU time 42.6 seconds
Started Jul 14 06:02:53 PM PDT 24
Finished Jul 14 06:03:36 PM PDT 24
Peak memory 213784 kb
Host smart-496f7392-fcf7-4bae-906c-4ba0eedc3692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322148961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2322148961
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2279284955
Short name T1054
Test name
Test status
Simulation time 55107620268 ps
CPU time 2061.53 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:37:08 PM PDT 24
Peak memory 8959060 kb
Host smart-1c3be806-d175-40bc-93d6-495b57a184c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279284955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2279284955
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2497155269
Short name T1625
Test name
Test status
Simulation time 4897340452 ps
CPU time 48.58 seconds
Started Jul 14 06:02:45 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 903640 kb
Host smart-6478322c-1e34-48a3-8435-4eec9291cfb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497155269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2497155269
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1749347174
Short name T793
Test name
Test status
Simulation time 6309065353 ps
CPU time 7.75 seconds
Started Jul 14 06:02:51 PM PDT 24
Finished Jul 14 06:02:59 PM PDT 24
Peak memory 231280 kb
Host smart-cfa7d741-8b91-4b44-aa85-e61207678326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749347174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1749347174
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2393959457
Short name T728
Test name
Test status
Simulation time 302683078 ps
CPU time 4.26 seconds
Started Jul 14 06:02:55 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 205552 kb
Host smart-e5c5e9e5-590a-42fd-8630-fd434abdfd09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393959457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2393959457
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3323885466
Short name T804
Test name
Test status
Simulation time 101483362 ps
CPU time 0.59 seconds
Started Jul 14 06:03:13 PM PDT 24
Finished Jul 14 06:03:14 PM PDT 24
Peak memory 204756 kb
Host smart-197c8e77-784e-4c60-b13f-d85d1c444fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323885466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3323885466
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1626858884
Short name T1078
Test name
Test status
Simulation time 94640647 ps
CPU time 1.24 seconds
Started Jul 14 06:02:58 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 213760 kb
Host smart-5585e46c-70cd-48c4-9587-3713ab686b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626858884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1626858884
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2650955067
Short name T1071
Test name
Test status
Simulation time 435699874 ps
CPU time 23.78 seconds
Started Jul 14 06:02:59 PM PDT 24
Finished Jul 14 06:03:24 PM PDT 24
Peak memory 302412 kb
Host smart-49ad63db-9f24-433d-847d-5d60a852ccc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650955067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2650955067
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1462150642
Short name T1653
Test name
Test status
Simulation time 3412602012 ps
CPU time 126.29 seconds
Started Jul 14 06:03:02 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 711564 kb
Host smart-6f9a1fb2-90b0-4a1f-931d-13777e1e2cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462150642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1462150642
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2243385892
Short name T1366
Test name
Test status
Simulation time 51252130541 ps
CPU time 192.61 seconds
Started Jul 14 06:03:00 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 776540 kb
Host smart-68ff1f35-5ad6-4af7-b2cc-973771bc33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243385892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2243385892
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.522254362
Short name T7
Test name
Test status
Simulation time 80447398 ps
CPU time 0.83 seconds
Started Jul 14 06:02:59 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 205228 kb
Host smart-607f52ab-f212-471f-8014-8874d6609a10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522254362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.522254362
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2675722821
Short name T575
Test name
Test status
Simulation time 554640592 ps
CPU time 8.73 seconds
Started Jul 14 06:03:01 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 231412 kb
Host smart-80575300-23f6-4ea2-9070-fa2b509137c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675722821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2675722821
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2301385508
Short name T107
Test name
Test status
Simulation time 11342742812 ps
CPU time 65.63 seconds
Started Jul 14 06:03:02 PM PDT 24
Finished Jul 14 06:04:08 PM PDT 24
Peak memory 896640 kb
Host smart-2b2c5d6e-2acc-4e1b-9493-f37113c22829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301385508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2301385508
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2612556336
Short name T240
Test name
Test status
Simulation time 1040127434 ps
CPU time 21.89 seconds
Started Jul 14 06:03:10 PM PDT 24
Finished Jul 14 06:03:32 PM PDT 24
Peak memory 205536 kb
Host smart-2037eb83-703d-485c-8c3b-3c866ea578f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612556336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2612556336
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.1263077706
Short name T91
Test name
Test status
Simulation time 28952988 ps
CPU time 0.71 seconds
Started Jul 14 06:03:03 PM PDT 24
Finished Jul 14 06:03:04 PM PDT 24
Peak memory 205196 kb
Host smart-69bb9a89-0ce9-440c-b1de-8903693409ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263077706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1263077706
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.520265263
Short name T436
Test name
Test status
Simulation time 1448723732 ps
CPU time 18.13 seconds
Started Jul 14 06:03:00 PM PDT 24
Finished Jul 14 06:03:18 PM PDT 24
Peak memory 296564 kb
Host smart-eb963fd1-a542-4044-b3f8-501c58bc497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520265263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.520265263
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.3791030380
Short name T1118
Test name
Test status
Simulation time 57025133 ps
CPU time 1.29 seconds
Started Jul 14 06:03:03 PM PDT 24
Finished Jul 14 06:03:05 PM PDT 24
Peak memory 223944 kb
Host smart-8f94c687-081a-4496-b569-622dc3202247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791030380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3791030380
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.4157589757
Short name T638
Test name
Test status
Simulation time 9059817970 ps
CPU time 40.82 seconds
Started Jul 14 06:03:06 PM PDT 24
Finished Jul 14 06:03:48 PM PDT 24
Peak memory 367900 kb
Host smart-9d2b4b9a-8895-4431-9d08-dc615b058a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157589757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.4157589757
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2868124505
Short name T835
Test name
Test status
Simulation time 70288092692 ps
CPU time 2140.67 seconds
Started Jul 14 06:03:03 PM PDT 24
Finished Jul 14 06:38:45 PM PDT 24
Peak memory 2513424 kb
Host smart-57258034-a583-4f37-a6c4-c8accc717028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868124505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2868124505
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2069341787
Short name T177
Test name
Test status
Simulation time 12004925548 ps
CPU time 27.3 seconds
Started Jul 14 06:03:01 PM PDT 24
Finished Jul 14 06:03:29 PM PDT 24
Peak memory 213932 kb
Host smart-1231cfbe-622a-449c-af83-9365c2ab0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069341787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2069341787
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4224479802
Short name T1530
Test name
Test status
Simulation time 10529839419 ps
CPU time 3.43 seconds
Started Jul 14 06:03:13 PM PDT 24
Finished Jul 14 06:03:17 PM PDT 24
Peak memory 218212 kb
Host smart-f8ad6aac-515d-49c3-ab98-aedc9b404b97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224479802 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4224479802
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.437397202
Short name T795
Test name
Test status
Simulation time 389148596 ps
CPU time 1.11 seconds
Started Jul 14 06:03:08 PM PDT 24
Finished Jul 14 06:03:09 PM PDT 24
Peak memory 205628 kb
Host smart-96b1fc83-4cc5-4c7d-9aff-1ad37ce1ac71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437397202 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.437397202
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1936984357
Short name T765
Test name
Test status
Simulation time 350143266 ps
CPU time 0.91 seconds
Started Jul 14 06:03:09 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 205384 kb
Host smart-e253f507-cd0e-482d-8bab-a96515bfe512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936984357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1936984357
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.339638337
Short name T641
Test name
Test status
Simulation time 1539633354 ps
CPU time 2.76 seconds
Started Jul 14 06:03:07 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 205592 kb
Host smart-567dd90a-922c-4a68-a967-1c849876186f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339638337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.339638337
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.4070341919
Short name T695
Test name
Test status
Simulation time 125896368 ps
CPU time 1.17 seconds
Started Jul 14 06:03:09 PM PDT 24
Finished Jul 14 06:03:11 PM PDT 24
Peak memory 205472 kb
Host smart-de6c33aa-40a2-4e2c-9421-b96b5f6323d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070341919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.4070341919
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.464617656
Short name T407
Test name
Test status
Simulation time 4252012765 ps
CPU time 6.18 seconds
Started Jul 14 06:03:12 PM PDT 24
Finished Jul 14 06:03:19 PM PDT 24
Peak memory 223380 kb
Host smart-2a174d65-6e13-4f34-94d9-819b4fb5894f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464617656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.464617656
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1122774558
Short name T693
Test name
Test status
Simulation time 18945347347 ps
CPU time 52.82 seconds
Started Jul 14 06:03:12 PM PDT 24
Finished Jul 14 06:04:05 PM PDT 24
Peak memory 1123832 kb
Host smart-b94dd563-03d6-43c9-be22-1ee28273e7c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122774558 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1122774558
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.626007588
Short name T752
Test name
Test status
Simulation time 635621234 ps
CPU time 3.31 seconds
Started Jul 14 06:03:09 PM PDT 24
Finished Jul 14 06:03:12 PM PDT 24
Peak memory 213788 kb
Host smart-d6366c82-10fe-4a53-850e-ae96cc6990a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626007588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_nack_acqfull.626007588
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.3728962426
Short name T1189
Test name
Test status
Simulation time 134884987 ps
CPU time 1.38 seconds
Started Jul 14 06:03:09 PM PDT 24
Finished Jul 14 06:03:11 PM PDT 24
Peak memory 222284 kb
Host smart-4331d507-5c69-4371-8877-88abe0d5b6fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728962426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.3728962426
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_perf.306120758
Short name T1017
Test name
Test status
Simulation time 1776058377 ps
CPU time 6.16 seconds
Started Jul 14 06:03:09 PM PDT 24
Finished Jul 14 06:03:16 PM PDT 24
Peak memory 222040 kb
Host smart-006e7616-24d7-49a1-8c1c-e6a992df94b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306120758 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.306120758
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.3339600036
Short name T1671
Test name
Test status
Simulation time 517280454 ps
CPU time 2.29 seconds
Started Jul 14 06:03:12 PM PDT 24
Finished Jul 14 06:03:15 PM PDT 24
Peak memory 205396 kb
Host smart-6ecc9d2b-ad3e-4e1a-bc6f-576ebde2b256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339600036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.3339600036
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.804415897
Short name T1697
Test name
Test status
Simulation time 1071496234 ps
CPU time 15.75 seconds
Started Jul 14 06:03:06 PM PDT 24
Finished Jul 14 06:03:23 PM PDT 24
Peak memory 213776 kb
Host smart-549ddc27-6cb4-4466-9c97-c80b5f2cdfc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804415897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.804415897
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.3195264097
Short name T665
Test name
Test status
Simulation time 7564373161 ps
CPU time 38.49 seconds
Started Jul 14 06:03:13 PM PDT 24
Finished Jul 14 06:03:52 PM PDT 24
Peak memory 238412 kb
Host smart-0a1a1464-ac3d-4c06-a952-cd5a682e8c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195264097 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.3195264097
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2788558010
Short name T1700
Test name
Test status
Simulation time 6289387477 ps
CPU time 30.53 seconds
Started Jul 14 06:03:10 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 238244 kb
Host smart-8517d255-3e1b-4a1d-b9a6-610c53329f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788558010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2788558010
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2988514388
Short name T1413
Test name
Test status
Simulation time 12645089079 ps
CPU time 22.62 seconds
Started Jul 14 06:03:07 PM PDT 24
Finished Jul 14 06:03:30 PM PDT 24
Peak memory 205684 kb
Host smart-a43f2a63-4e08-43fe-afec-a1040a481b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988514388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2988514388
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3771901106
Short name T536
Test name
Test status
Simulation time 806127537 ps
CPU time 16.67 seconds
Started Jul 14 06:03:11 PM PDT 24
Finished Jul 14 06:03:28 PM PDT 24
Peak memory 263344 kb
Host smart-0324e1a9-1e50-462c-98a2-a3688d4c953c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771901106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3771901106
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4192519872
Short name T1512
Test name
Test status
Simulation time 2267586771 ps
CPU time 5.97 seconds
Started Jul 14 06:03:10 PM PDT 24
Finished Jul 14 06:03:17 PM PDT 24
Peak memory 218960 kb
Host smart-37bfbb63-6fd3-42ba-a2ca-3858640d19d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192519872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4192519872
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3749231330
Short name T880
Test name
Test status
Simulation time 144696140 ps
CPU time 2.55 seconds
Started Jul 14 06:03:10 PM PDT 24
Finished Jul 14 06:03:14 PM PDT 24
Peak memory 205728 kb
Host smart-d1c3c942-6f9a-4d1b-97c6-58cfcfee0dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749231330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3749231330
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3716640012
Short name T1327
Test name
Test status
Simulation time 33372818 ps
CPU time 0.64 seconds
Started Jul 14 06:03:25 PM PDT 24
Finished Jul 14 06:03:26 PM PDT 24
Peak memory 204704 kb
Host smart-d11b55c9-fb9f-420e-a64f-7212abdc6a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716640012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3716640012
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3274206694
Short name T670
Test name
Test status
Simulation time 302977930 ps
CPU time 1.58 seconds
Started Jul 14 06:03:15 PM PDT 24
Finished Jul 14 06:03:17 PM PDT 24
Peak memory 221828 kb
Host smart-28ed7c22-496f-4464-9d1f-2cfdfc6d2dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274206694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3274206694
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1904645029
Short name T886
Test name
Test status
Simulation time 1996306949 ps
CPU time 14.82 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:03:32 PM PDT 24
Peak memory 262396 kb
Host smart-8f618689-3a1b-4724-a832-12101c3f9cd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904645029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1904645029
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.651523573
Short name T885
Test name
Test status
Simulation time 6535300542 ps
CPU time 231.46 seconds
Started Jul 14 06:03:16 PM PDT 24
Finished Jul 14 06:07:08 PM PDT 24
Peak memory 770860 kb
Host smart-379381d6-60c5-467c-849a-6c76bc9a8a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651523573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.651523573
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.372437069
Short name T506
Test name
Test status
Simulation time 22436855676 ps
CPU time 93.85 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:04:51 PM PDT 24
Peak memory 789864 kb
Host smart-f11c1c89-2361-455c-826f-f51632b0a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372437069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.372437069
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2177267813
Short name T1590
Test name
Test status
Simulation time 128511269 ps
CPU time 1.14 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:03:19 PM PDT 24
Peak memory 205244 kb
Host smart-4c42ec0f-4274-4143-a901-5dd0d1a419b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177267813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2177267813
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.263823012
Short name T1596
Test name
Test status
Simulation time 13613657958 ps
CPU time 71.05 seconds
Started Jul 14 06:03:14 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 951804 kb
Host smart-7160776f-6a6c-4a8f-b609-2fa07706e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263823012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.263823012
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2385243917
Short name T247
Test name
Test status
Simulation time 792198479 ps
CPU time 33.36 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:56 PM PDT 24
Peak memory 205480 kb
Host smart-e2b7d645-609e-4096-ba7b-fab7e6219a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385243917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2385243917
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3435382442
Short name T1722
Test name
Test status
Simulation time 867515627 ps
CPU time 2.38 seconds
Started Jul 14 06:03:24 PM PDT 24
Finished Jul 14 06:03:27 PM PDT 24
Peak memory 215028 kb
Host smart-11871acb-a934-44ef-b736-30afc8017f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435382442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3435382442
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3986810719
Short name T136
Test name
Test status
Simulation time 47549699 ps
CPU time 0.72 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:03:18 PM PDT 24
Peak memory 205100 kb
Host smart-e5480869-c878-422d-a06b-ee3c82988f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986810719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3986810719
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2017874960
Short name T541
Test name
Test status
Simulation time 7314822947 ps
CPU time 13.13 seconds
Started Jul 14 06:03:18 PM PDT 24
Finished Jul 14 06:03:32 PM PDT 24
Peak memory 354952 kb
Host smart-6890d9c0-5f41-427e-b8f4-281bfc2382bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017874960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2017874960
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.328215794
Short name T838
Test name
Test status
Simulation time 892307937 ps
CPU time 8.63 seconds
Started Jul 14 06:03:14 PM PDT 24
Finished Jul 14 06:03:23 PM PDT 24
Peak memory 205444 kb
Host smart-c3a133bf-a17a-4a34-8749-5f52f487714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328215794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.328215794
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3961621386
Short name T758
Test name
Test status
Simulation time 21564264736 ps
CPU time 79.03 seconds
Started Jul 14 06:03:08 PM PDT 24
Finished Jul 14 06:04:28 PM PDT 24
Peak memory 292500 kb
Host smart-bbb0f01e-1df0-4afa-8d32-acc6e52b501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961621386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3961621386
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3149383979
Short name T530
Test name
Test status
Simulation time 424964038 ps
CPU time 18.52 seconds
Started Jul 14 06:12:57 PM PDT 24
Finished Jul 14 06:13:17 PM PDT 24
Peak memory 213728 kb
Host smart-f707bce8-4727-495d-8dbc-dba9086a7587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149383979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3149383979
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1524637811
Short name T1371
Test name
Test status
Simulation time 3193158378 ps
CPU time 4.45 seconds
Started Jul 14 06:03:15 PM PDT 24
Finished Jul 14 06:03:19 PM PDT 24
Peak memory 213892 kb
Host smart-f332da10-2b9f-4e93-bba7-f3c382f665db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524637811 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1524637811
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1453690338
Short name T519
Test name
Test status
Simulation time 235854901 ps
CPU time 0.74 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:03:19 PM PDT 24
Peak memory 205380 kb
Host smart-6d150296-80e1-40b9-8591-741398763a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453690338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1453690338
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.106400949
Short name T1161
Test name
Test status
Simulation time 181726180 ps
CPU time 1.25 seconds
Started Jul 14 06:03:18 PM PDT 24
Finished Jul 14 06:03:20 PM PDT 24
Peak memory 205624 kb
Host smart-7a3345f1-94d8-4f46-a318-e6377892e04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106400949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.106400949
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.2713099765
Short name T1694
Test name
Test status
Simulation time 5997502295 ps
CPU time 2.23 seconds
Started Jul 14 06:03:24 PM PDT 24
Finished Jul 14 06:03:27 PM PDT 24
Peak memory 205500 kb
Host smart-4968be2b-feab-4307-81b4-b58cb97998ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713099765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2713099765
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.2336459578
Short name T1289
Test name
Test status
Simulation time 605963766 ps
CPU time 1.27 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:24 PM PDT 24
Peak memory 205436 kb
Host smart-247fd8b7-8208-4c66-9546-274c79d25c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336459578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.2336459578
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.564278151
Short name T1614
Test name
Test status
Simulation time 4769803804 ps
CPU time 7.1 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:03:25 PM PDT 24
Peak memory 230420 kb
Host smart-87158071-052d-4443-9ba0-c6d2379b36f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564278151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.564278151
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1892315918
Short name T1309
Test name
Test status
Simulation time 4665633023 ps
CPU time 3.55 seconds
Started Jul 14 06:03:16 PM PDT 24
Finished Jul 14 06:03:20 PM PDT 24
Peak memory 205684 kb
Host smart-476840ce-dbf2-40ff-bcf4-7260656ae8de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892315918 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1892315918
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.3857135229
Short name T438
Test name
Test status
Simulation time 1630057895 ps
CPU time 2.62 seconds
Started Jul 14 06:03:24 PM PDT 24
Finished Jul 14 06:03:27 PM PDT 24
Peak memory 213776 kb
Host smart-e0f5e146-be0a-4e3b-918f-ad8d848dad4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857135229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.3857135229
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.2449883140
Short name T84
Test name
Test status
Simulation time 1797099750 ps
CPU time 2.31 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:03:29 PM PDT 24
Peak memory 205576 kb
Host smart-b32e9ca0-a7de-441c-bc89-ce05204eb6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449883140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.2449883140
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.3611533303
Short name T151
Test name
Test status
Simulation time 523374826 ps
CPU time 1.44 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:25 PM PDT 24
Peak memory 222032 kb
Host smart-672f16a1-f230-4016-9465-ff3a46b82b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611533303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.3611533303
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3107594242
Short name T1097
Test name
Test status
Simulation time 533421687 ps
CPU time 3.72 seconds
Started Jul 14 06:03:16 PM PDT 24
Finished Jul 14 06:03:20 PM PDT 24
Peak memory 214872 kb
Host smart-87285ef4-d67c-4143-837c-32564902771f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107594242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3107594242
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.2591678142
Short name T1352
Test name
Test status
Simulation time 1930560086 ps
CPU time 2.33 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:03:29 PM PDT 24
Peak memory 205388 kb
Host smart-adcb5907-fc1a-43a6-bdba-40e40b9d5d2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591678142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.2591678142
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3692595447
Short name T1110
Test name
Test status
Simulation time 1315218095 ps
CPU time 40.53 seconds
Started Jul 14 06:03:15 PM PDT 24
Finished Jul 14 06:03:56 PM PDT 24
Peak memory 213828 kb
Host smart-67b725aa-261c-49be-aa4e-91d352c6335c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692595447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3692595447
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2990648740
Short name T1070
Test name
Test status
Simulation time 28027706711 ps
CPU time 618.87 seconds
Started Jul 14 06:03:17 PM PDT 24
Finished Jul 14 06:13:36 PM PDT 24
Peak memory 3654568 kb
Host smart-26b98a6b-8550-44dc-82a9-937a681d3829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990648740 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2990648740
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1678876254
Short name T362
Test name
Test status
Simulation time 556648579 ps
CPU time 6.05 seconds
Started Jul 14 06:03:18 PM PDT 24
Finished Jul 14 06:03:24 PM PDT 24
Peak memory 205540 kb
Host smart-86372760-9b5c-4a31-b15f-e8c16fbedf89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678876254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1678876254
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.369188964
Short name T478
Test name
Test status
Simulation time 33832370400 ps
CPU time 320.93 seconds
Started Jul 14 06:03:16 PM PDT 24
Finished Jul 14 06:08:37 PM PDT 24
Peak memory 3496412 kb
Host smart-3358d353-ce7f-4115-bc83-2a77430bbe81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369188964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.369188964
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3101719358
Short name T1319
Test name
Test status
Simulation time 1877904214 ps
CPU time 7.01 seconds
Started Jul 14 06:03:18 PM PDT 24
Finished Jul 14 06:03:26 PM PDT 24
Peak memory 268784 kb
Host smart-dc3df624-fbde-4a11-90bb-52eadcb2024a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101719358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3101719358
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2778998993
Short name T313
Test name
Test status
Simulation time 1392727732 ps
CPU time 7.54 seconds
Started Jul 14 06:03:18 PM PDT 24
Finished Jul 14 06:03:27 PM PDT 24
Peak memory 230264 kb
Host smart-336cf3c9-3034-4b35-a6e9-50bf96774331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778998993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2778998993
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2373947824
Short name T1019
Test name
Test status
Simulation time 266145342 ps
CPU time 3.66 seconds
Started Jul 14 06:03:24 PM PDT 24
Finished Jul 14 06:03:28 PM PDT 24
Peak memory 205544 kb
Host smart-57a8e7ba-8b95-4562-9d4d-8fde41223427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373947824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2373947824
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2384876370
Short name T983
Test name
Test status
Simulation time 21123044 ps
CPU time 0.66 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:03:33 PM PDT 24
Peak memory 204760 kb
Host smart-69ba270b-27e5-4fce-b18b-f14b1b6bf0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384876370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2384876370
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2243014091
Short name T368
Test name
Test status
Simulation time 462660195 ps
CPU time 8.52 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:32 PM PDT 24
Peak memory 238784 kb
Host smart-da683a57-1160-4319-a07e-ffee6c80b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243014091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2243014091
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3186576228
Short name T411
Test name
Test status
Simulation time 984507760 ps
CPU time 30.28 seconds
Started Jul 14 06:03:24 PM PDT 24
Finished Jul 14 06:03:55 PM PDT 24
Peak memory 331916 kb
Host smart-57351fb7-5f73-4f14-bfee-7eb318f076b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186576228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3186576228
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3088235188
Short name T999
Test name
Test status
Simulation time 7023422551 ps
CPU time 113.52 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:05:20 PM PDT 24
Peak memory 588116 kb
Host smart-f81f28b7-02c0-4a4a-b307-afebc0318c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088235188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3088235188
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1009758465
Short name T471
Test name
Test status
Simulation time 7233530788 ps
CPU time 53.37 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:04:17 PM PDT 24
Peak memory 628472 kb
Host smart-5cf50113-90a3-46d2-aee3-c7792aec1189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009758465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1009758465
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3648306006
Short name T1379
Test name
Test status
Simulation time 134608238 ps
CPU time 1.08 seconds
Started Jul 14 06:03:28 PM PDT 24
Finished Jul 14 06:03:29 PM PDT 24
Peak memory 205200 kb
Host smart-d73c7aba-34de-4348-84b4-9522a267e275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648306006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3648306006
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1476702624
Short name T618
Test name
Test status
Simulation time 172621829 ps
CPU time 4.41 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:03:31 PM PDT 24
Peak memory 234328 kb
Host smart-f76aadcb-69dd-4fde-b527-907867ec8b25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476702624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1476702624
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.638024482
Short name T143
Test name
Test status
Simulation time 39897600889 ps
CPU time 188.34 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:06:36 PM PDT 24
Peak memory 904352 kb
Host smart-a11900fb-252e-471c-8f86-edbc7f69aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638024482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.638024482
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.4036896759
Short name T1505
Test name
Test status
Simulation time 1438177370 ps
CPU time 15.84 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 205468 kb
Host smart-d5f96fc1-08f4-430f-9736-c06b1ae4d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036896759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.4036896759
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.2377171701
Short name T1695
Test name
Test status
Simulation time 27172566 ps
CPU time 0.68 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:24 PM PDT 24
Peak memory 205180 kb
Host smart-f378418d-6455-47a5-94ff-949ac3da50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377171701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2377171701
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.517301530
Short name T1368
Test name
Test status
Simulation time 12169909795 ps
CPU time 164.56 seconds
Started Jul 14 06:03:28 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 205524 kb
Host smart-2c99d2dd-8831-43df-8500-450742d697bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517301530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.517301530
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.4225196329
Short name T1491
Test name
Test status
Simulation time 224293039 ps
CPU time 10.17 seconds
Started Jul 14 06:03:23 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 235768 kb
Host smart-6d190be2-bd8e-466e-877d-843fa40343b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225196329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.4225196329
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.4234213389
Short name T531
Test name
Test status
Simulation time 34479732564 ps
CPU time 42.42 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:04:09 PM PDT 24
Peak memory 408196 kb
Host smart-5f0743ee-e6e6-4fef-be6c-357825e018fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234213389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.4234213389
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3971734162
Short name T1258
Test name
Test status
Simulation time 848488144 ps
CPU time 37.25 seconds
Started Jul 14 06:03:26 PM PDT 24
Finished Jul 14 06:04:04 PM PDT 24
Peak memory 213712 kb
Host smart-2b7a3161-dfdc-4aba-9eba-4eb3fd23a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971734162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3971734162
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.608486841
Short name T646
Test name
Test status
Simulation time 11869735878 ps
CPU time 5.75 seconds
Started Jul 14 06:03:35 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 213960 kb
Host smart-1b3ca3d3-6c70-4564-9387-facdb42fb13d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608486841 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.608486841
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3807566567
Short name T1301
Test name
Test status
Simulation time 354252086 ps
CPU time 1.16 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 213764 kb
Host smart-33e457c4-99c6-4f70-86f8-7bd3630afa83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807566567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3807566567
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.4216131394
Short name T1187
Test name
Test status
Simulation time 161446541 ps
CPU time 1.17 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:36 PM PDT 24
Peak memory 213832 kb
Host smart-7718b052-069a-487d-af7d-ef09a067e1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216131394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.4216131394
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.4198856483
Short name T507
Test name
Test status
Simulation time 943684686 ps
CPU time 2.53 seconds
Started Jul 14 06:03:35 PM PDT 24
Finished Jul 14 06:03:38 PM PDT 24
Peak memory 205568 kb
Host smart-262d43ab-c5d7-4270-a36a-747f1e52cd5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198856483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.4198856483
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.511604488
Short name T601
Test name
Test status
Simulation time 561452173 ps
CPU time 1.02 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:35 PM PDT 24
Peak memory 205356 kb
Host smart-ca65ce4d-c3e9-411b-8447-2e4ff91f7e66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511604488 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.511604488
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.4280542379
Short name T1607
Test name
Test status
Simulation time 924790723 ps
CPU time 5.33 seconds
Started Jul 14 06:03:35 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 218172 kb
Host smart-073b51a3-e1e1-4a40-9bf6-2c40eea1b1f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280542379 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.4280542379
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2942972336
Short name T1048
Test name
Test status
Simulation time 3088039836 ps
CPU time 6.77 seconds
Started Jul 14 06:03:35 PM PDT 24
Finished Jul 14 06:03:43 PM PDT 24
Peak memory 205728 kb
Host smart-203577d4-9818-4a67-84c8-d76139e180fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942972336 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2942972336
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.3906939327
Short name T1152
Test name
Test status
Simulation time 999360454 ps
CPU time 2.94 seconds
Started Jul 14 06:03:33 PM PDT 24
Finished Jul 14 06:03:36 PM PDT 24
Peak memory 213848 kb
Host smart-6f3741fa-6ebd-4da2-8412-5f0cc04c7550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906939327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.3906939327
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.205733389
Short name T47
Test name
Test status
Simulation time 506311904 ps
CPU time 1.36 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 222048 kb
Host smart-bb05a189-e689-4c01-928f-55ede5eaec4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205733389 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_nack_txstretch.205733389
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.867818469
Short name T403
Test name
Test status
Simulation time 1909593770 ps
CPU time 7.27 seconds
Started Jul 14 06:03:33 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 213772 kb
Host smart-360409ce-d6eb-4566-80cb-2918c031f3d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867818469 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_perf.867818469
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.840632219
Short name T861
Test name
Test status
Simulation time 438357261 ps
CPU time 2.14 seconds
Started Jul 14 06:03:30 PM PDT 24
Finished Jul 14 06:03:33 PM PDT 24
Peak memory 205300 kb
Host smart-35ad4ebf-f428-4fc2-86f5-98dbe13d19b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840632219 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_smbus_maxlen.840632219
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.4143299279
Short name T1023
Test name
Test status
Simulation time 1074899694 ps
CPU time 14.38 seconds
Started Jul 14 06:03:33 PM PDT 24
Finished Jul 14 06:03:49 PM PDT 24
Peak memory 213828 kb
Host smart-02806242-496e-4a3b-8a4c-59991c8abc71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143299279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.4143299279
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.3007111341
Short name T363
Test name
Test status
Simulation time 44855180262 ps
CPU time 917.43 seconds
Started Jul 14 06:03:35 PM PDT 24
Finished Jul 14 06:18:53 PM PDT 24
Peak memory 4611112 kb
Host smart-71e645b2-bf9f-4928-9379-076c575cf87c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007111341 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.3007111341
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2825421909
Short name T283
Test name
Test status
Simulation time 2220818851 ps
CPU time 10.87 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:45 PM PDT 24
Peak memory 208176 kb
Host smart-086f4343-17a5-478b-bc41-a39a1e251b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825421909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2825421909
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.739976852
Short name T1248
Test name
Test status
Simulation time 11347591795 ps
CPU time 6.78 seconds
Started Jul 14 06:03:30 PM PDT 24
Finished Jul 14 06:03:37 PM PDT 24
Peak memory 205572 kb
Host smart-3f20656c-f64b-4c67-a790-229ab86b5e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739976852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.739976852
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3220847896
Short name T509
Test name
Test status
Simulation time 1752851736 ps
CPU time 2.68 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:38 PM PDT 24
Peak memory 221172 kb
Host smart-33e4275a-3d94-4273-9275-d4608912dda1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220847896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3220847896
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2961736762
Short name T1714
Test name
Test status
Simulation time 1327178230 ps
CPU time 7.13 seconds
Started Jul 14 06:03:33 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 213860 kb
Host smart-e0033f59-7f0d-4243-b81a-2ab2830913c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961736762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2961736762
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.651067579
Short name T1179
Test name
Test status
Simulation time 148068571 ps
CPU time 3.32 seconds
Started Jul 14 06:03:34 PM PDT 24
Finished Jul 14 06:03:38 PM PDT 24
Peak memory 206372 kb
Host smart-25a9c6ca-6ba9-431d-9928-edf27b29d2bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651067579 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.651067579
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.1452245737
Short name T1584
Test name
Test status
Simulation time 28477882 ps
CPU time 0.63 seconds
Started Jul 14 06:03:49 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 204788 kb
Host smart-288271bd-2942-4ec1-a675-d5884c7e6611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452245737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1452245737
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2094457446
Short name T27
Test name
Test status
Simulation time 577640328 ps
CPU time 2.34 seconds
Started Jul 14 06:03:38 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 221844 kb
Host smart-0e070a3d-6775-4a53-9ebf-d9e1540543ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094457446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2094457446
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1268074035
Short name T336
Test name
Test status
Simulation time 360165805 ps
CPU time 18.51 seconds
Started Jul 14 06:03:38 PM PDT 24
Finished Jul 14 06:03:57 PM PDT 24
Peak memory 282472 kb
Host smart-4e6ef9e4-b6ff-4aa2-b4e3-f387d54a7220
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268074035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1268074035
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.4135528105
Short name T1676
Test name
Test status
Simulation time 3869901113 ps
CPU time 42.66 seconds
Started Jul 14 06:03:47 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 239076 kb
Host smart-08da53a5-5b85-42a0-91f5-fbb1ad195968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135528105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.4135528105
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.4183514955
Short name T1449
Test name
Test status
Simulation time 2954569382 ps
CPU time 183.44 seconds
Started Jul 14 06:03:33 PM PDT 24
Finished Jul 14 06:06:38 PM PDT 24
Peak memory 776108 kb
Host smart-58f93833-54a4-437a-95e2-d90c0ea7d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183514955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4183514955
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2557031261
Short name T1360
Test name
Test status
Simulation time 187692764 ps
CPU time 0.92 seconds
Started Jul 14 06:03:40 PM PDT 24
Finished Jul 14 06:03:41 PM PDT 24
Peak memory 205460 kb
Host smart-5713cf26-5cd9-4a0f-a88c-97e25741e938
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557031261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2557031261
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4279469523
Short name T564
Test name
Test status
Simulation time 190997306 ps
CPU time 9.04 seconds
Started Jul 14 06:03:43 PM PDT 24
Finished Jul 14 06:03:53 PM PDT 24
Peak memory 205448 kb
Host smart-d98b66b2-c779-4ce8-b590-b26500bc82d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279469523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4279469523
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1419214980
Short name T1321
Test name
Test status
Simulation time 22302107201 ps
CPU time 149.16 seconds
Started Jul 14 06:03:36 PM PDT 24
Finished Jul 14 06:06:05 PM PDT 24
Peak memory 1539232 kb
Host smart-fcc78a41-2cb1-4d4e-811b-73493fba7f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419214980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1419214980
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.757533940
Short name T1314
Test name
Test status
Simulation time 184637586 ps
CPU time 7.13 seconds
Started Jul 14 06:03:47 PM PDT 24
Finished Jul 14 06:03:54 PM PDT 24
Peak memory 205444 kb
Host smart-86a0f7a0-4619-4c5d-af7d-e74c9e19250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757533940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.757533940
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1609227949
Short name T13
Test name
Test status
Simulation time 267068802 ps
CPU time 1.17 seconds
Started Jul 14 06:03:43 PM PDT 24
Finished Jul 14 06:03:45 PM PDT 24
Peak memory 205364 kb
Host smart-18fb4c40-9697-4f7d-9b64-266c5386971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609227949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1609227949
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.2208174552
Short name T843
Test name
Test status
Simulation time 16437549 ps
CPU time 0.67 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:03:33 PM PDT 24
Peak memory 205156 kb
Host smart-36bf64d8-9856-42b9-81db-01108af64139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208174552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2208174552
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.558254135
Short name T226
Test name
Test status
Simulation time 25600376562 ps
CPU time 1368.57 seconds
Started Jul 14 06:03:41 PM PDT 24
Finished Jul 14 06:26:31 PM PDT 24
Peak memory 526252 kb
Host smart-2815eba5-138b-422d-a767-bde6e6e3d02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558254135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.558254135
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.120998315
Short name T583
Test name
Test status
Simulation time 239472777 ps
CPU time 3.52 seconds
Started Jul 14 06:03:40 PM PDT 24
Finished Jul 14 06:03:44 PM PDT 24
Peak memory 221584 kb
Host smart-27d43858-5b9b-4246-bf3d-c2ff5f25a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120998315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.120998315
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2874435177
Short name T1591
Test name
Test status
Simulation time 2900502330 ps
CPU time 28.14 seconds
Started Jul 14 06:03:32 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 344212 kb
Host smart-df7f92f2-afb6-4c6f-8491-64535251285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874435177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2874435177
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.4178742762
Short name T416
Test name
Test status
Simulation time 1548572537 ps
CPU time 13.04 seconds
Started Jul 14 06:03:41 PM PDT 24
Finished Jul 14 06:03:55 PM PDT 24
Peak memory 221180 kb
Host smart-ac771e73-0dd8-49c2-a6a9-2b5114ec091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178742762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.4178742762
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.259264848
Short name T1644
Test name
Test status
Simulation time 790133732 ps
CPU time 4.33 seconds
Started Jul 14 06:03:38 PM PDT 24
Finished Jul 14 06:03:42 PM PDT 24
Peak memory 213784 kb
Host smart-57e25a14-092a-40f9-815c-ed6db058acb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259264848 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.259264848
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.371329187
Short name T229
Test name
Test status
Simulation time 473705953 ps
CPU time 1.04 seconds
Started Jul 14 06:03:42 PM PDT 24
Finished Jul 14 06:03:44 PM PDT 24
Peak memory 205444 kb
Host smart-c909f526-860a-44ac-9d5c-5eb6279881cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371329187 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.371329187
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.30035913
Short name T1209
Test name
Test status
Simulation time 133119974 ps
CPU time 0.97 seconds
Started Jul 14 06:03:40 PM PDT 24
Finished Jul 14 06:03:42 PM PDT 24
Peak memory 205404 kb
Host smart-5bfdda01-90ee-4e11-a9a7-7f1fce416b67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035913 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_fifo_reset_tx.30035913
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1979516795
Short name T1470
Test name
Test status
Simulation time 369039844 ps
CPU time 2.08 seconds
Started Jul 14 06:03:48 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 205444 kb
Host smart-36f414ef-b96e-44a0-9189-6186d425df08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979516795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1979516795
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.462355250
Short name T615
Test name
Test status
Simulation time 529546848 ps
CPU time 1.21 seconds
Started Jul 14 06:03:45 PM PDT 24
Finished Jul 14 06:03:47 PM PDT 24
Peak memory 205380 kb
Host smart-dce22d24-88d2-47b1-8607-c4f448315412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462355250 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.462355250
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.218144329
Short name T87
Test name
Test status
Simulation time 1269591212 ps
CPU time 8 seconds
Started Jul 14 06:03:45 PM PDT 24
Finished Jul 14 06:03:54 PM PDT 24
Peak memory 221900 kb
Host smart-139542c3-c5cc-49da-b000-7323c6799d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218144329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.218144329
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2274539416
Short name T412
Test name
Test status
Simulation time 17809140358 ps
CPU time 21.51 seconds
Started Jul 14 06:03:48 PM PDT 24
Finished Jul 14 06:04:10 PM PDT 24
Peak memory 670188 kb
Host smart-02de3b98-5b17-492a-9ec7-564be28632ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274539416 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2274539416
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.4124033133
Short name T603
Test name
Test status
Simulation time 2033928902 ps
CPU time 3.01 seconds
Started Jul 14 06:03:49 PM PDT 24
Finished Jul 14 06:03:53 PM PDT 24
Peak memory 213824 kb
Host smart-6fd5a642-b2cf-4184-84b8-2a4ca55ab543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124033133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.4124033133
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.3882710790
Short name T598
Test name
Test status
Simulation time 705731715 ps
CPU time 2.2 seconds
Started Jul 14 06:03:46 PM PDT 24
Finished Jul 14 06:03:48 PM PDT 24
Peak memory 205604 kb
Host smart-e41cf9fa-21e8-49fb-9972-fcecdd8a59fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882710790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3882710790
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.1589081199
Short name T572
Test name
Test status
Simulation time 233675338 ps
CPU time 1.55 seconds
Started Jul 14 06:03:50 PM PDT 24
Finished Jul 14 06:03:52 PM PDT 24
Peak memory 222048 kb
Host smart-5f486917-c108-4614-9eab-df9ffc8397af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589081199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_nack_txstretch.1589081199
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1907708759
Short name T1115
Test name
Test status
Simulation time 813225804 ps
CPU time 6.17 seconds
Started Jul 14 06:03:40 PM PDT 24
Finished Jul 14 06:03:46 PM PDT 24
Peak memory 218028 kb
Host smart-1f9e328d-ca14-4ffe-8d0c-b1edb5fd793a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907708759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1907708759
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.2155228333
Short name T1188
Test name
Test status
Simulation time 483664169 ps
CPU time 2.35 seconds
Started Jul 14 06:03:49 PM PDT 24
Finished Jul 14 06:03:52 PM PDT 24
Peak memory 205432 kb
Host smart-0a4edf41-5f84-47f1-9555-d6312c25fb46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155228333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.2155228333
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3560492692
Short name T1650
Test name
Test status
Simulation time 1259055835 ps
CPU time 16.04 seconds
Started Jul 14 06:03:45 PM PDT 24
Finished Jul 14 06:04:02 PM PDT 24
Peak memory 213672 kb
Host smart-82139bab-4f72-41c4-bb46-6b74fb9cf01e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560492692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3560492692
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.1652078266
Short name T415
Test name
Test status
Simulation time 66752797938 ps
CPU time 33.57 seconds
Started Jul 14 06:03:42 PM PDT 24
Finished Jul 14 06:04:17 PM PDT 24
Peak memory 238440 kb
Host smart-5f3c7b3a-76d3-46be-a01a-06b8457a7fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652078266 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.1652078266
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1665023050
Short name T413
Test name
Test status
Simulation time 55861832652 ps
CPU time 637.29 seconds
Started Jul 14 06:03:39 PM PDT 24
Finished Jul 14 06:14:17 PM PDT 24
Peak memory 4610612 kb
Host smart-0cda1d8f-dfe7-4b6b-b2eb-fff7274b6a9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665023050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1665023050
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3259824757
Short name T1134
Test name
Test status
Simulation time 1973599564 ps
CPU time 4.25 seconds
Started Jul 14 06:03:41 PM PDT 24
Finished Jul 14 06:03:46 PM PDT 24
Peak memory 249568 kb
Host smart-9aa4ad6f-7495-458e-8fe3-21601b7c5aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259824757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3259824757
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2869056601
Short name T1532
Test name
Test status
Simulation time 1882803222 ps
CPU time 5.85 seconds
Started Jul 14 06:03:37 PM PDT 24
Finished Jul 14 06:03:43 PM PDT 24
Peak memory 222112 kb
Host smart-ee399b9c-c055-420e-be68-9bafcc287206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869056601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2869056601
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1374570631
Short name T1240
Test name
Test status
Simulation time 452520170 ps
CPU time 6.44 seconds
Started Jul 14 06:03:49 PM PDT 24
Finished Jul 14 06:03:56 PM PDT 24
Peak memory 205512 kb
Host smart-23c7d891-02f8-49bf-9ea2-a4850aa1ac8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374570631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1374570631
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1727088198
Short name T1564
Test name
Test status
Simulation time 43893833 ps
CPU time 0.66 seconds
Started Jul 14 06:04:04 PM PDT 24
Finished Jul 14 06:04:05 PM PDT 24
Peak memory 204836 kb
Host smart-ba829322-4092-48a2-b8b3-8ff429dc2917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727088198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1727088198
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1816492501
Short name T360
Test name
Test status
Simulation time 217928240 ps
CPU time 10.18 seconds
Started Jul 14 06:03:58 PM PDT 24
Finished Jul 14 06:04:09 PM PDT 24
Peak memory 248480 kb
Host smart-0781fd06-58c0-4b5e-a688-ed4eeec88f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816492501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1816492501
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2885649513
Short name T538
Test name
Test status
Simulation time 1271953763 ps
CPU time 30.58 seconds
Started Jul 14 06:03:50 PM PDT 24
Finished Jul 14 06:04:21 PM PDT 24
Peak memory 312588 kb
Host smart-70a9356c-5bba-43aa-92fe-d1b73e73091c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885649513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2885649513
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1337612652
Short name T1088
Test name
Test status
Simulation time 3540926438 ps
CPU time 143.76 seconds
Started Jul 14 06:03:57 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 844756 kb
Host smart-6a8a341f-d979-46a5-b899-18e64d70b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337612652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1337612652
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.636009745
Short name T1549
Test name
Test status
Simulation time 10887378173 ps
CPU time 70.74 seconds
Started Jul 14 06:03:49 PM PDT 24
Finished Jul 14 06:05:00 PM PDT 24
Peak memory 769556 kb
Host smart-054ea4f3-3598-4b53-9708-620009397b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636009745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.636009745
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2347632092
Short name T981
Test name
Test status
Simulation time 115473769 ps
CPU time 1.04 seconds
Started Jul 14 06:03:51 PM PDT 24
Finished Jul 14 06:03:52 PM PDT 24
Peak memory 205136 kb
Host smart-74bf3a1f-85d2-44d1-b757-bb852c31ab4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347632092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2347632092
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2103605200
Short name T158
Test name
Test status
Simulation time 266155662 ps
CPU time 7.25 seconds
Started Jul 14 06:03:59 PM PDT 24
Finished Jul 14 06:04:07 PM PDT 24
Peak memory 205448 kb
Host smart-33b92e0e-0be7-4135-9a8e-85d8a4d84f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103605200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2103605200
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.937163064
Short name T1264
Test name
Test status
Simulation time 4954699493 ps
CPU time 158.25 seconds
Started Jul 14 06:03:46 PM PDT 24
Finished Jul 14 06:06:25 PM PDT 24
Peak memory 824436 kb
Host smart-36b4b5f1-f9d0-4d89-8dfa-5e328e59f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937163064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.937163064
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2849262339
Short name T245
Test name
Test status
Simulation time 4446324581 ps
CPU time 20.47 seconds
Started Jul 14 06:04:00 PM PDT 24
Finished Jul 14 06:04:21 PM PDT 24
Peak memory 205556 kb
Host smart-59956765-6f9c-49e0-ba42-62507c5b1953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849262339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2849262339
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.1756105468
Short name T129
Test name
Test status
Simulation time 62468949 ps
CPU time 0.7 seconds
Started Jul 14 06:03:50 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 205188 kb
Host smart-91704c4a-0b39-45b2-a35c-a7652a62e544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756105468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1756105468
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1819739900
Short name T1688
Test name
Test status
Simulation time 49247369451 ps
CPU time 633.74 seconds
Started Jul 14 06:03:55 PM PDT 24
Finished Jul 14 06:14:30 PM PDT 24
Peak memory 2613916 kb
Host smart-4064080a-03d4-4a68-b22c-64295978da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819739900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1819739900
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3689195966
Short name T431
Test name
Test status
Simulation time 231509028 ps
CPU time 4.28 seconds
Started Jul 14 06:03:57 PM PDT 24
Finished Jul 14 06:04:02 PM PDT 24
Peak memory 247308 kb
Host smart-3d71a708-1e61-4deb-957b-a92754ec5f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689195966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3689195966
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.500026993
Short name T1171
Test name
Test status
Simulation time 2988484624 ps
CPU time 26.62 seconds
Started Jul 14 06:03:50 PM PDT 24
Finished Jul 14 06:04:17 PM PDT 24
Peak memory 333860 kb
Host smart-47ab0b46-d468-425d-9fd0-c7dffda982ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500026993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.500026993
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3830891654
Short name T1269
Test name
Test status
Simulation time 1608156178 ps
CPU time 13.87 seconds
Started Jul 14 06:03:59 PM PDT 24
Finished Jul 14 06:04:13 PM PDT 24
Peak memory 230040 kb
Host smart-63083e34-3cc1-412f-8831-078ee758ce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830891654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3830891654
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.850308960
Short name T1377
Test name
Test status
Simulation time 6882626805 ps
CPU time 4.28 seconds
Started Jul 14 06:03:56 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 213856 kb
Host smart-7670449b-ff9b-48ab-a00c-c703d203ba5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850308960 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.850308960
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1430528640
Short name T1729
Test name
Test status
Simulation time 705830601 ps
CPU time 1.55 seconds
Started Jul 14 06:03:55 PM PDT 24
Finished Jul 14 06:03:57 PM PDT 24
Peak memory 213744 kb
Host smart-c92e995d-8184-4448-a41f-a312508bdd85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430528640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1430528640
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2605535897
Short name T1128
Test name
Test status
Simulation time 678579555 ps
CPU time 1.58 seconds
Started Jul 14 06:03:55 PM PDT 24
Finished Jul 14 06:03:58 PM PDT 24
Peak memory 205620 kb
Host smart-2476678a-653e-43dd-af87-c32acc76e577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605535897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2605535897
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1189332310
Short name T1433
Test name
Test status
Simulation time 444673511 ps
CPU time 2.48 seconds
Started Jul 14 06:03:56 PM PDT 24
Finished Jul 14 06:03:59 PM PDT 24
Peak memory 205584 kb
Host smart-7468f7b5-6e40-4e96-bad7-27aebc2b43ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189332310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1189332310
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.928692152
Short name T1693
Test name
Test status
Simulation time 50559499 ps
CPU time 0.84 seconds
Started Jul 14 06:03:58 PM PDT 24
Finished Jul 14 06:04:00 PM PDT 24
Peak memory 205464 kb
Host smart-c943f94f-765d-4bc4-a8b5-9920fdece3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928692152 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.928692152
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1225452731
Short name T289
Test name
Test status
Simulation time 6556425157 ps
CPU time 4.04 seconds
Started Jul 14 06:03:56 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 213856 kb
Host smart-560eb86e-1e9d-46dc-a1ca-096ec6b28cf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225452731 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1225452731
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.4132973136
Short name T1730
Test name
Test status
Simulation time 14861030451 ps
CPU time 33.3 seconds
Started Jul 14 06:03:54 PM PDT 24
Finished Jul 14 06:04:28 PM PDT 24
Peak memory 853696 kb
Host smart-38dd0b28-ee0d-4940-9b57-c9fa0614baa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132973136 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.4132973136
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.1779886702
Short name T427
Test name
Test status
Simulation time 2112752554 ps
CPU time 2.8 seconds
Started Jul 14 06:04:01 PM PDT 24
Finished Jul 14 06:04:05 PM PDT 24
Peak memory 213824 kb
Host smart-d9630972-1cdd-411c-b643-27019fa38b4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779886702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.1779886702
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.2870693024
Short name T123
Test name
Test status
Simulation time 530507527 ps
CPU time 2.91 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:04:13 PM PDT 24
Peak memory 205528 kb
Host smart-32f17646-e395-44c3-a5d3-ae539a600433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870693024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.2870693024
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.1768364794
Short name T308
Test name
Test status
Simulation time 2811428751 ps
CPU time 4.85 seconds
Started Jul 14 06:03:58 PM PDT 24
Finished Jul 14 06:04:04 PM PDT 24
Peak memory 218652 kb
Host smart-17408d51-02bb-4ecb-a8c4-6c92f9e749aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768364794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.1768364794
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.3048788535
Short name T297
Test name
Test status
Simulation time 524245766 ps
CPU time 2.51 seconds
Started Jul 14 06:04:01 PM PDT 24
Finished Jul 14 06:04:04 PM PDT 24
Peak memory 205376 kb
Host smart-b3cbdbd3-f240-457a-a1b2-f3a3bae696b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048788535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.3048788535
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3695710858
Short name T327
Test name
Test status
Simulation time 1875264458 ps
CPU time 27.91 seconds
Started Jul 14 06:03:57 PM PDT 24
Finished Jul 14 06:04:25 PM PDT 24
Peak memory 213880 kb
Host smart-ac0ef082-ff9d-4a23-b8df-74b213ff711a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695710858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3695710858
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1040737834
Short name T1061
Test name
Test status
Simulation time 18207553639 ps
CPU time 49.29 seconds
Started Jul 14 06:03:58 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 282492 kb
Host smart-3f948db6-5dc7-43fd-98f6-77733bdd6c3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040737834 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1040737834
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3177851877
Short name T873
Test name
Test status
Simulation time 6138006511 ps
CPU time 69.78 seconds
Started Jul 14 06:03:56 PM PDT 24
Finished Jul 14 06:05:07 PM PDT 24
Peak memory 217532 kb
Host smart-548af4b4-88b1-436d-a117-3ce41e3d60ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177851877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3177851877
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.101918997
Short name T991
Test name
Test status
Simulation time 61395713786 ps
CPU time 294.16 seconds
Started Jul 14 06:03:59 PM PDT 24
Finished Jul 14 06:08:54 PM PDT 24
Peak memory 2656484 kb
Host smart-d852345c-c4f6-4c26-a3cf-23b513ad2413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101918997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.101918997
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2875999787
Short name T1021
Test name
Test status
Simulation time 4132338185 ps
CPU time 229.72 seconds
Started Jul 14 06:03:55 PM PDT 24
Finished Jul 14 06:07:45 PM PDT 24
Peak memory 1127664 kb
Host smart-10d8ca7d-d805-44b9-a115-f574a4f8caaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875999787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2875999787
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1087944396
Short name T903
Test name
Test status
Simulation time 3140107746 ps
CPU time 7.2 seconds
Started Jul 14 06:04:00 PM PDT 24
Finished Jul 14 06:04:08 PM PDT 24
Peak memory 222040 kb
Host smart-25eaef82-f1e2-4d5b-a840-f5b41bb59799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087944396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1087944396
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.4212042290
Short name T604
Test name
Test status
Simulation time 91229257 ps
CPU time 1.98 seconds
Started Jul 14 06:03:55 PM PDT 24
Finished Jul 14 06:03:58 PM PDT 24
Peak memory 205600 kb
Host smart-4cc78a3e-98a4-4239-a99e-2e57e7990db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212042290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.4212042290
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.387860430
Short name T946
Test name
Test status
Simulation time 44490935 ps
CPU time 0.66 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:04:10 PM PDT 24
Peak memory 204812 kb
Host smart-dea5188c-cc93-4f67-929a-e45f979064cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387860430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.387860430
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1755121685
Short name T1077
Test name
Test status
Simulation time 421441006 ps
CPU time 4.25 seconds
Started Jul 14 06:04:02 PM PDT 24
Finished Jul 14 06:04:07 PM PDT 24
Peak memory 234620 kb
Host smart-03165da3-0cce-486a-8188-17d1c64ab045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755121685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1755121685
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2617162827
Short name T85
Test name
Test status
Simulation time 467406635 ps
CPU time 4.33 seconds
Started Jul 14 06:04:07 PM PDT 24
Finished Jul 14 06:04:12 PM PDT 24
Peak memory 250332 kb
Host smart-84388659-bced-4a91-adc2-c99ae91f763f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617162827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2617162827
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3347257059
Short name T1107
Test name
Test status
Simulation time 3471779482 ps
CPU time 299.03 seconds
Started Jul 14 06:04:05 PM PDT 24
Finished Jul 14 06:09:05 PM PDT 24
Peak memory 1034052 kb
Host smart-48380964-2e82-4a57-875e-8ee11db9f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347257059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3347257059
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.381938808
Short name T1125
Test name
Test status
Simulation time 2371771717 ps
CPU time 67.21 seconds
Started Jul 14 06:04:02 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 760188 kb
Host smart-3b425514-ee94-4ce7-8806-a2073991af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381938808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.381938808
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.4122096754
Short name T692
Test name
Test status
Simulation time 437270440 ps
CPU time 1.1 seconds
Started Jul 14 06:04:02 PM PDT 24
Finished Jul 14 06:04:03 PM PDT 24
Peak memory 205240 kb
Host smart-ef79fb20-ce41-4d4b-b37b-e21f3be1380b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122096754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.4122096754
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2689792141
Short name T145
Test name
Test status
Simulation time 173859628 ps
CPU time 4.34 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:16 PM PDT 24
Peak memory 205124 kb
Host smart-676a7a52-0626-4623-a0f2-f180d047c5c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689792141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2689792141
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3518669845
Short name T113
Test name
Test status
Simulation time 3128937459 ps
CPU time 67.08 seconds
Started Jul 14 06:04:05 PM PDT 24
Finished Jul 14 06:05:13 PM PDT 24
Peak memory 874112 kb
Host smart-1555d549-3542-424c-93a0-76fe1139ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518669845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3518669845
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_override.715172338
Short name T1177
Test name
Test status
Simulation time 88089694 ps
CPU time 0.77 seconds
Started Jul 14 06:04:04 PM PDT 24
Finished Jul 14 06:04:05 PM PDT 24
Peak memory 205192 kb
Host smart-4b1c6284-db23-46e9-8f6e-2d53f5a828d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715172338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.715172338
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3702838529
Short name T566
Test name
Test status
Simulation time 27465554294 ps
CPU time 137.24 seconds
Started Jul 14 06:04:03 PM PDT 24
Finished Jul 14 06:06:20 PM PDT 24
Peak memory 205504 kb
Host smart-b4989a70-4308-4766-a834-727e28552f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702838529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3702838529
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3544698677
Short name T1344
Test name
Test status
Simulation time 80904955 ps
CPU time 1.61 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:13 PM PDT 24
Peak memory 223236 kb
Host smart-82fb08ee-53f9-47fc-bddb-4a07a7baf2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544698677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3544698677
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3468956201
Short name T183
Test name
Test status
Simulation time 4614615933 ps
CPU time 123.05 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 477188 kb
Host smart-9baa6592-949f-446b-a345-3d541b390a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468956201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3468956201
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.735906470
Short name T459
Test name
Test status
Simulation time 2626170078 ps
CPU time 30.64 seconds
Started Jul 14 06:04:05 PM PDT 24
Finished Jul 14 06:04:36 PM PDT 24
Peak memory 213652 kb
Host smart-78ec5ff9-4e95-4563-86af-1e07f7542c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735906470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.735906470
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3802978922
Short name T910
Test name
Test status
Simulation time 2146007825 ps
CPU time 5.85 seconds
Started Jul 14 06:04:11 PM PDT 24
Finished Jul 14 06:04:18 PM PDT 24
Peak memory 213700 kb
Host smart-fd256c99-766d-4a21-b064-bff347ceda38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802978922 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3802978922
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.543851312
Short name T277
Test name
Test status
Simulation time 647256962 ps
CPU time 1.34 seconds
Started Jul 14 06:04:08 PM PDT 24
Finished Jul 14 06:04:10 PM PDT 24
Peak memory 205408 kb
Host smart-2811f9b3-fc05-40a5-9b53-ccd2c366ff8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543851312 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.543851312
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2177244575
Short name T1364
Test name
Test status
Simulation time 1320964309 ps
CPU time 1.12 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:13 PM PDT 24
Peak memory 205468 kb
Host smart-53bb7678-3d23-43e2-9b68-61abd69790fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177244575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2177244575
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.919827329
Short name T1072
Test name
Test status
Simulation time 1108491524 ps
CPU time 2.58 seconds
Started Jul 14 06:04:08 PM PDT 24
Finished Jul 14 06:04:12 PM PDT 24
Peak memory 205536 kb
Host smart-c972b44e-c7fd-463b-8a89-a38541d330a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919827329 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.919827329
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.10469750
Short name T1204
Test name
Test status
Simulation time 418519035 ps
CPU time 1.15 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:04:11 PM PDT 24
Peak memory 205436 kb
Host smart-7508a44d-dcf2-4a5e-804a-bd32be611d91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10469750 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.10469750
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1466641498
Short name T1393
Test name
Test status
Simulation time 4322188561 ps
CPU time 6.02 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:17 PM PDT 24
Peak memory 222036 kb
Host smart-8bbe3b44-79c3-4b39-a077-e184df74bc58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466641498 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1466641498
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.4128110182
Short name T763
Test name
Test status
Simulation time 17106446962 ps
CPU time 37.73 seconds
Started Jul 14 06:04:08 PM PDT 24
Finished Jul 14 06:04:46 PM PDT 24
Peak memory 712452 kb
Host smart-b136ff99-9138-40c3-a5c6-446e2b37a62c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128110182 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.4128110182
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.1426371003
Short name T963
Test name
Test status
Simulation time 2226818695 ps
CPU time 2.73 seconds
Started Jul 14 06:04:12 PM PDT 24
Finished Jul 14 06:04:15 PM PDT 24
Peak memory 213888 kb
Host smart-5c3d013d-222f-4641-9a61-b5a52949c8a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426371003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_acqfull.1426371003
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.2652142865
Short name T419
Test name
Test status
Simulation time 2119429137 ps
CPU time 2.65 seconds
Started Jul 14 06:04:11 PM PDT 24
Finished Jul 14 06:04:15 PM PDT 24
Peak memory 205536 kb
Host smart-ed632243-ece9-4387-9e7a-85946108e85f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652142865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.2652142865
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.3645565237
Short name T1045
Test name
Test status
Simulation time 177268005 ps
CPU time 1.72 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:14 PM PDT 24
Peak memory 222396 kb
Host smart-7b8e4582-d93a-412e-9331-1e40c75ef713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645565237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_txstretch.3645565237
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/16.i2c_target_perf.1967097442
Short name T1337
Test name
Test status
Simulation time 957449657 ps
CPU time 4.5 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:16 PM PDT 24
Peak memory 221752 kb
Host smart-6d26b2b7-e21d-4c04-989f-3ba4981cf0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967097442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.1967097442
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.3238067026
Short name T399
Test name
Test status
Simulation time 880441510 ps
CPU time 2.28 seconds
Started Jul 14 06:04:18 PM PDT 24
Finished Jul 14 06:04:20 PM PDT 24
Peak memory 205316 kb
Host smart-aa7d1634-94c0-4e4a-892a-4ce8a7a2c6ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238067026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.3238067026
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.1928517635
Short name T73
Test name
Test status
Simulation time 3264644508 ps
CPU time 26.43 seconds
Started Jul 14 06:04:04 PM PDT 24
Finished Jul 14 06:04:31 PM PDT 24
Peak memory 213772 kb
Host smart-250b25fa-9dfe-409e-8986-9e5cb41db5b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928517635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.1928517635
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.3935843291
Short name T1672
Test name
Test status
Simulation time 88698905420 ps
CPU time 77.21 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:05:27 PM PDT 24
Peak memory 811048 kb
Host smart-c2034bb0-c7c8-47dd-95f6-a8a5e3bb2fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935843291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.3935843291
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3296432145
Short name T554
Test name
Test status
Simulation time 3073626947 ps
CPU time 40.16 seconds
Started Jul 14 06:04:01 PM PDT 24
Finished Jul 14 06:04:42 PM PDT 24
Peak memory 213852 kb
Host smart-df5640dc-99cf-483e-800c-7a04d449f2e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296432145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3296432145
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1518647731
Short name T934
Test name
Test status
Simulation time 7756300226 ps
CPU time 15.36 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:27 PM PDT 24
Peak memory 205692 kb
Host smart-e1994532-4e78-434d-a4dd-4e3ddcc3272b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518647731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1518647731
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3826129037
Short name T339
Test name
Test status
Simulation time 5089874293 ps
CPU time 20.87 seconds
Started Jul 14 06:04:04 PM PDT 24
Finished Jul 14 06:04:25 PM PDT 24
Peak memory 297796 kb
Host smart-66411809-a474-4822-9f31-b066f867c5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826129037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3826129037
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1832458717
Short name T1194
Test name
Test status
Simulation time 1291524537 ps
CPU time 6.56 seconds
Started Jul 14 06:04:14 PM PDT 24
Finished Jul 14 06:04:21 PM PDT 24
Peak memory 213696 kb
Host smart-a89d8538-fd70-44d2-bee0-cfc0d9e0ccbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832458717 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1832458717
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.2965305904
Short name T346
Test name
Test status
Simulation time 408114995 ps
CPU time 5.06 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:16 PM PDT 24
Peak memory 205556 kb
Host smart-beeab62a-b89b-4904-aa85-350fbaa9bc87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965305904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2965305904
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2938200920
Short name T1239
Test name
Test status
Simulation time 15948252 ps
CPU time 0.65 seconds
Started Jul 14 06:04:28 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 204756 kb
Host smart-19fdbd4a-fd5d-424f-adf7-e59cdb833713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938200920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2938200920
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1127751995
Short name T28
Test name
Test status
Simulation time 46547125 ps
CPU time 1.69 seconds
Started Jul 14 06:04:23 PM PDT 24
Finished Jul 14 06:04:25 PM PDT 24
Peak memory 213784 kb
Host smart-d06ae1a0-e63d-45df-98e1-6d9e7d425284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127751995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1127751995
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2016841437
Short name T563
Test name
Test status
Simulation time 4046910664 ps
CPU time 5.98 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:04:15 PM PDT 24
Peak memory 256504 kb
Host smart-adca8191-865d-49f9-83ae-b8567ae5d46b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016841437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2016841437
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1128611870
Short name T1615
Test name
Test status
Simulation time 14744908280 ps
CPU time 62.1 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:05:14 PM PDT 24
Peak memory 281192 kb
Host smart-1cff999e-1ac1-412f-9457-d260f27fc082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128611870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1128611870
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2846946639
Short name T1131
Test name
Test status
Simulation time 2039338143 ps
CPU time 32.77 seconds
Started Jul 14 06:04:08 PM PDT 24
Finished Jul 14 06:04:41 PM PDT 24
Peak memory 378780 kb
Host smart-9b33e4b6-decf-4cb6-82a6-db98c5c08f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846946639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2846946639
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2118660618
Short name T722
Test name
Test status
Simulation time 123195321 ps
CPU time 1.08 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:12 PM PDT 24
Peak memory 205216 kb
Host smart-1fda42da-3563-4e8c-adaf-ffff4e68d597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118660618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2118660618
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.846484936
Short name T408
Test name
Test status
Simulation time 153546152 ps
CPU time 3.95 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:04:16 PM PDT 24
Peak memory 231416 kb
Host smart-ec332751-12cc-4ea3-bd36-c4e5ef7a2898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846484936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
846484936
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2196290035
Short name T740
Test name
Test status
Simulation time 9067914495 ps
CPU time 326.2 seconds
Started Jul 14 06:04:10 PM PDT 24
Finished Jul 14 06:09:37 PM PDT 24
Peak memory 1313916 kb
Host smart-0b57ffa4-9ede-483b-8efe-d42105557653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196290035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2196290035
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1109754246
Short name T987
Test name
Test status
Simulation time 585606212 ps
CPU time 7.46 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:04:35 PM PDT 24
Peak memory 205508 kb
Host smart-ec6b621a-25ef-4072-a2f7-10744a178382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109754246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1109754246
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.1404531842
Short name T1489
Test name
Test status
Simulation time 50899760 ps
CPU time 0.67 seconds
Started Jul 14 06:04:09 PM PDT 24
Finished Jul 14 06:04:11 PM PDT 24
Peak memory 205120 kb
Host smart-ef847027-4f16-47bf-bb8d-aa668b911541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404531842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1404531842
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.737494510
Short name T387
Test name
Test status
Simulation time 8156709022 ps
CPU time 120.61 seconds
Started Jul 14 06:04:08 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 685288 kb
Host smart-2f56ca85-0645-4193-b8e5-5c0c4f829bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737494510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.737494510
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.1007993497
Short name T584
Test name
Test status
Simulation time 131758738 ps
CPU time 1.12 seconds
Started Jul 14 06:04:11 PM PDT 24
Finished Jul 14 06:04:13 PM PDT 24
Peak memory 205956 kb
Host smart-113598ca-d8c3-46b3-a7b9-1e47292e384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007993497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.1007993497
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1577723319
Short name T1355
Test name
Test status
Simulation time 6043246032 ps
CPU time 31.68 seconds
Started Jul 14 06:04:16 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 366952 kb
Host smart-7d44be35-e7fc-44c5-b6d3-b846997429c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577723319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1577723319
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1056574255
Short name T1580
Test name
Test status
Simulation time 383133083 ps
CPU time 16.18 seconds
Started Jul 14 06:04:23 PM PDT 24
Finished Jul 14 06:04:41 PM PDT 24
Peak memory 213716 kb
Host smart-a6fce945-ac50-4a6a-a9c1-2ca199e54794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056574255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1056574255
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.322008974
Short name T1420
Test name
Test status
Simulation time 2621810666 ps
CPU time 3.39 seconds
Started Jul 14 06:04:27 PM PDT 24
Finished Jul 14 06:04:32 PM PDT 24
Peak memory 216352 kb
Host smart-afb91957-6901-4555-888d-9ab5e413a44d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322008974 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.322008974
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2086193328
Short name T1026
Test name
Test status
Simulation time 189039812 ps
CPU time 1.04 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 205292 kb
Host smart-6bc1258b-1b38-4ed6-b202-a1da08cdf1a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086193328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2086193328
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3183803777
Short name T94
Test name
Test status
Simulation time 239639885 ps
CPU time 1.76 seconds
Started Jul 14 06:04:23 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 213844 kb
Host smart-e5f02978-3cb7-4b6b-85e5-5291e9612ab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183803777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3183803777
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.448909615
Short name T333
Test name
Test status
Simulation time 485891375 ps
CPU time 2.94 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 205624 kb
Host smart-619be466-3581-4ce3-92b2-5729dc9626e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448909615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.448909615
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.365686841
Short name T1058
Test name
Test status
Simulation time 155690954 ps
CPU time 1.27 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 205452 kb
Host smart-e7467a26-7d49-4c5b-89f7-36c952723ebb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365686841 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.365686841
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.4071680760
Short name T125
Test name
Test status
Simulation time 5873063543 ps
CPU time 7.28 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:04:32 PM PDT 24
Peak memory 230416 kb
Host smart-d5ba5dea-551e-4ea3-ad7e-5a2fcb305f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071680760 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.4071680760
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2134376757
Short name T745
Test name
Test status
Simulation time 18551171976 ps
CPU time 330.98 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:09:58 PM PDT 24
Peak memory 3026000 kb
Host smart-2730f973-d17d-4b79-96df-3712c3a860d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134376757 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2134376757
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1943933098
Short name T817
Test name
Test status
Simulation time 540780891 ps
CPU time 2.97 seconds
Started Jul 14 06:04:22 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 213800 kb
Host smart-4e14f090-cf11-4587-94a9-e82c864dc9f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943933098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1943933098
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.483085235
Short name T1506
Test name
Test status
Simulation time 517017261 ps
CPU time 2.49 seconds
Started Jul 14 06:04:27 PM PDT 24
Finished Jul 14 06:04:31 PM PDT 24
Peak memory 205624 kb
Host smart-4bd490d6-c644-41f8-9dd4-1e55ac1c982f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483085235 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.483085235
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.1568268442
Short name T1423
Test name
Test status
Simulation time 1903821862 ps
CPU time 6.36 seconds
Started Jul 14 06:04:23 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 214080 kb
Host smart-84f0c2bf-4f1c-421c-ba85-3a03b78b40d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568268442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.1568268442
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.672162180
Short name T1463
Test name
Test status
Simulation time 446969049 ps
CPU time 2.14 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:04:28 PM PDT 24
Peak memory 205372 kb
Host smart-1be10c96-feb0-47fc-8752-aa85d680901c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672162180 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_smbus_maxlen.672162180
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.122262185
Short name T1634
Test name
Test status
Simulation time 2980725318 ps
CPU time 9.78 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 213860 kb
Host smart-958e9984-f023-420d-859d-cb559b464b7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122262185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_tar
get_smoke.122262185
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.690353434
Short name T481
Test name
Test status
Simulation time 12845753391 ps
CPU time 86.51 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 1309232 kb
Host smart-6e2784f4-119c-43ad-b840-dcc45c08c701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690353434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_target_stress_all.690353434
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3988430476
Short name T1080
Test name
Test status
Simulation time 3640908252 ps
CPU time 20.02 seconds
Started Jul 14 06:04:26 PM PDT 24
Finished Jul 14 06:04:47 PM PDT 24
Peak memory 222168 kb
Host smart-a9d768d0-de39-45c1-8143-e64cf1bcccb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988430476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3988430476
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3304887621
Short name T425
Test name
Test status
Simulation time 57652591351 ps
CPU time 229.35 seconds
Started Jul 14 06:04:22 PM PDT 24
Finished Jul 14 06:08:12 PM PDT 24
Peak memory 2452352 kb
Host smart-b6517b98-bcb8-4b83-acb0-b6f219441a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304887621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3304887621
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.377704372
Short name T295
Test name
Test status
Simulation time 2293004092 ps
CPU time 19.11 seconds
Started Jul 14 06:04:22 PM PDT 24
Finished Jul 14 06:04:42 PM PDT 24
Peak memory 282212 kb
Host smart-634a528d-1782-40be-9e6c-4a64e70c9c7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377704372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.377704372
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.946035778
Short name T1304
Test name
Test status
Simulation time 5104979190 ps
CPU time 7.52 seconds
Started Jul 14 06:04:21 PM PDT 24
Finished Jul 14 06:04:29 PM PDT 24
Peak memory 230212 kb
Host smart-722c90b4-ef3f-4a13-a884-8b63678d8db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946035778 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.946035778
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.168854738
Short name T1613
Test name
Test status
Simulation time 128619962 ps
CPU time 1.93 seconds
Started Jul 14 06:04:23 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 205504 kb
Host smart-62d391a9-e63f-4e5e-9295-4d132859d786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168854738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.168854738
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3643905389
Short name T154
Test name
Test status
Simulation time 19662395 ps
CPU time 0.63 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:04:34 PM PDT 24
Peak memory 204788 kb
Host smart-5e7ddb7e-b723-4dd1-97b7-54016b6b3f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643905389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3643905389
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1994354860
Short name T1075
Test name
Test status
Simulation time 1755019027 ps
CPU time 2.29 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:04:33 PM PDT 24
Peak memory 218228 kb
Host smart-0bd7ec08-c918-4e5f-ac7f-39263a5723fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994354860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1994354860
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3372497526
Short name T953
Test name
Test status
Simulation time 6123828877 ps
CPU time 7.08 seconds
Started Jul 14 06:04:36 PM PDT 24
Finished Jul 14 06:04:43 PM PDT 24
Peak memory 288528 kb
Host smart-c204109b-56f1-4838-ad0a-ee56561ad656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372497526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3372497526
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2861006735
Short name T141
Test name
Test status
Simulation time 15967338302 ps
CPU time 77.68 seconds
Started Jul 14 06:04:26 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 334156 kb
Host smart-74e43135-6327-49ce-acd3-761c1105c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861006735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2861006735
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1730849468
Short name T1478
Test name
Test status
Simulation time 7780218008 ps
CPU time 66.85 seconds
Started Jul 14 06:04:26 PM PDT 24
Finished Jul 14 06:05:35 PM PDT 24
Peak memory 673928 kb
Host smart-b4bb0b4d-6370-4368-b8d7-7a96aa0a01ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730849468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1730849468
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2961683351
Short name T589
Test name
Test status
Simulation time 261508334 ps
CPU time 1.28 seconds
Started Jul 14 06:04:26 PM PDT 24
Finished Jul 14 06:04:29 PM PDT 24
Peak memory 205372 kb
Host smart-ba748fb9-e2b9-4425-8f93-bf8e91399ac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961683351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2961683351
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.570301972
Short name T1260
Test name
Test status
Simulation time 318549516 ps
CPU time 3.6 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:04:30 PM PDT 24
Peak memory 205472 kb
Host smart-71f43053-6baa-4765-8854-a0fbe3702bdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570301972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
570301972
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2759831958
Short name T1235
Test name
Test status
Simulation time 6760794096 ps
CPU time 197.73 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 860200 kb
Host smart-8a3a739f-7748-4912-a031-b92cc49cf76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759831958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2759831958
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.226136406
Short name T239
Test name
Test status
Simulation time 786103519 ps
CPU time 6.12 seconds
Started Jul 14 06:04:31 PM PDT 24
Finished Jul 14 06:04:38 PM PDT 24
Peak memory 205492 kb
Host smart-87ed8695-b514-4c77-82af-7ae58059aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226136406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.226136406
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.2153293285
Short name T1578
Test name
Test status
Simulation time 142791296 ps
CPU time 0.65 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:04:32 PM PDT 24
Peak memory 205224 kb
Host smart-11bdc023-1318-41b4-b4af-a3af2b10fb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153293285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2153293285
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.1768514546
Short name T1569
Test name
Test status
Simulation time 67558164 ps
CPU time 1.33 seconds
Started Jul 14 06:04:24 PM PDT 24
Finished Jul 14 06:04:27 PM PDT 24
Peak memory 223544 kb
Host smart-f53290a2-7329-4a03-bb4a-43e42c411b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768514546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1768514546
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3158390469
Short name T691
Test name
Test status
Simulation time 2380141197 ps
CPU time 86.24 seconds
Started Jul 14 06:04:25 PM PDT 24
Finished Jul 14 06:05:53 PM PDT 24
Peak memory 347464 kb
Host smart-48b5cfaf-35d9-4412-85a5-918c36334d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158390469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3158390469
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1185213634
Short name T1127
Test name
Test status
Simulation time 3370200466 ps
CPU time 14.3 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:04:45 PM PDT 24
Peak memory 229296 kb
Host smart-ea6ee6d9-1502-4bea-8cea-1e2681676f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185213634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1185213634
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.486151770
Short name T288
Test name
Test status
Simulation time 1240975851 ps
CPU time 3.63 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:38 PM PDT 24
Peak memory 219296 kb
Host smart-46da0bd4-98e5-478a-afdb-1610571fef05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486151770 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.486151770
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2516141577
Short name T502
Test name
Test status
Simulation time 413810215 ps
CPU time 0.9 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:36 PM PDT 24
Peak memory 213620 kb
Host smart-9045f73a-e87d-44ac-bc61-faa57ff579c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516141577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2516141577
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3148603860
Short name T847
Test name
Test status
Simulation time 214015395 ps
CPU time 0.82 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:04:35 PM PDT 24
Peak memory 205448 kb
Host smart-a8b8b254-b57d-4fdb-8b42-d5cc422012b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148603860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3148603860
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2585127153
Short name T1514
Test name
Test status
Simulation time 2178927304 ps
CPU time 3.03 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 205688 kb
Host smart-b73bc41b-346c-4fce-99d6-e555cf9030f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585127153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2585127153
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3147701547
Short name T964
Test name
Test status
Simulation time 151298674 ps
CPU time 1.23 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:04:32 PM PDT 24
Peak memory 205412 kb
Host smart-59635eb6-5180-4eaa-9fee-428d4c9606cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147701547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3147701547
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2484463388
Short name T1728
Test name
Test status
Simulation time 17370434074 ps
CPU time 6.61 seconds
Started Jul 14 06:04:35 PM PDT 24
Finished Jul 14 06:04:42 PM PDT 24
Peak memory 221284 kb
Host smart-bb666003-7bae-4ba3-8e17-f7d755a5da75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484463388 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2484463388
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3962614656
Short name T1102
Test name
Test status
Simulation time 549156182 ps
CPU time 2.88 seconds
Started Jul 14 06:04:32 PM PDT 24
Finished Jul 14 06:04:36 PM PDT 24
Peak memory 205624 kb
Host smart-929cec73-3433-47a8-96ca-85fbc6623104
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962614656 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3962614656
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.2650752076
Short name T690
Test name
Test status
Simulation time 3316049219 ps
CPU time 2.64 seconds
Started Jul 14 06:04:32 PM PDT 24
Finished Jul 14 06:04:35 PM PDT 24
Peak memory 213880 kb
Host smart-72336c11-f08b-428d-b0d2-f21ccb4dee39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650752076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.2650752076
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.3206261672
Short name T1001
Test name
Test status
Simulation time 957964704 ps
CPU time 2.82 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:04:36 PM PDT 24
Peak memory 205844 kb
Host smart-ebba9f46-7ec5-43d3-99df-e712f79987c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206261672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.3206261672
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.550660032
Short name T48
Test name
Test status
Simulation time 517066164 ps
CPU time 1.47 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 222756 kb
Host smart-4116bba6-79b4-4701-b733-5c099ad81e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550660032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_nack_txstretch.550660032
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.2871708247
Short name T988
Test name
Test status
Simulation time 2380370085 ps
CPU time 7.39 seconds
Started Jul 14 06:04:32 PM PDT 24
Finished Jul 14 06:04:40 PM PDT 24
Peak memory 222036 kb
Host smart-28421edd-c2e9-4778-9f71-8a4739e66d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871708247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.2871708247
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.24988455
Short name T1243
Test name
Test status
Simulation time 4849639770 ps
CPU time 2.46 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 205384 kb
Host smart-0b8965d1-7fc6-49d5-a2db-40042c6bd3f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24988455 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_target_smbus_maxlen.24988455
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.335137293
Short name T322
Test name
Test status
Simulation time 1226417283 ps
CPU time 6.42 seconds
Started Jul 14 06:04:26 PM PDT 24
Finished Jul 14 06:04:34 PM PDT 24
Peak memory 213844 kb
Host smart-b7bf6d98-fba9-4a7e-8751-56000a0b2efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335137293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.335137293
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.3013357009
Short name T164
Test name
Test status
Simulation time 71338515968 ps
CPU time 117.42 seconds
Started Jul 14 06:04:36 PM PDT 24
Finished Jul 14 06:06:34 PM PDT 24
Peak memory 861060 kb
Host smart-ab92c6bf-c045-4d8b-9abe-88bd46d12588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013357009 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.3013357009
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3473055990
Short name T1049
Test name
Test status
Simulation time 2891344411 ps
CPU time 24.79 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:59 PM PDT 24
Peak memory 237696 kb
Host smart-0d0423b7-089c-41f2-a6e8-c442b3987e8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473055990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3473055990
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1235896533
Short name T1520
Test name
Test status
Simulation time 43927533467 ps
CPU time 111.72 seconds
Started Jul 14 06:04:28 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 1598316 kb
Host smart-87ddd08e-7dc6-458b-97d8-7ecfdaa31c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235896533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1235896533
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4191061283
Short name T402
Test name
Test status
Simulation time 3815928657 ps
CPU time 85.68 seconds
Started Jul 14 06:04:31 PM PDT 24
Finished Jul 14 06:05:57 PM PDT 24
Peak memory 611316 kb
Host smart-87dad851-de2e-47e6-84d4-973991682ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191061283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4191061283
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3173981183
Short name T477
Test name
Test status
Simulation time 4920334732 ps
CPU time 6.98 seconds
Started Jul 14 06:04:32 PM PDT 24
Finished Jul 14 06:04:39 PM PDT 24
Peak memory 230216 kb
Host smart-6a84ff9c-081e-448c-a345-bb5a2aca9505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173981183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3173981183
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.2621348048
Short name T1059
Test name
Test status
Simulation time 415480566 ps
CPU time 5.92 seconds
Started Jul 14 06:04:30 PM PDT 24
Finished Jul 14 06:04:37 PM PDT 24
Peak memory 205576 kb
Host smart-6904b616-e0e7-4af7-8d8d-7803eca1956f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621348048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.2621348048
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1039993758
Short name T1659
Test name
Test status
Simulation time 39205529 ps
CPU time 0.61 seconds
Started Jul 14 06:04:45 PM PDT 24
Finished Jul 14 06:04:46 PM PDT 24
Peak memory 204840 kb
Host smart-ba866f8e-8a38-4660-8b72-4521ea7aed53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039993758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1039993758
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.287682687
Short name T777
Test name
Test status
Simulation time 841816662 ps
CPU time 3.21 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:42 PM PDT 24
Peak memory 205508 kb
Host smart-acee059b-4327-487b-9aba-5b610e846eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287682687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.287682687
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3283445145
Short name T1428
Test name
Test status
Simulation time 1033217312 ps
CPU time 10.69 seconds
Started Jul 14 06:04:32 PM PDT 24
Finished Jul 14 06:04:44 PM PDT 24
Peak memory 242256 kb
Host smart-512dbfb9-2060-4150-8575-28c2df49b8f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283445145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3283445145
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3502585332
Short name T1010
Test name
Test status
Simulation time 5444011453 ps
CPU time 86.94 seconds
Started Jul 14 06:04:40 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 665264 kb
Host smart-e5755396-3853-4d60-8108-223d96bf24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502585332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3502585332
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1166192774
Short name T715
Test name
Test status
Simulation time 3255472360 ps
CPU time 47.51 seconds
Started Jul 14 06:04:31 PM PDT 24
Finished Jul 14 06:05:19 PM PDT 24
Peak memory 579788 kb
Host smart-3a273354-50d9-4621-ad21-d0f0cd448db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166192774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1166192774
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3046955644
Short name T1340
Test name
Test status
Simulation time 542012851 ps
CPU time 1.18 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:04:35 PM PDT 24
Peak memory 205240 kb
Host smart-1e97b300-8409-4681-a8e3-1b9d650f0878
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046955644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3046955644
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1976477970
Short name T882
Test name
Test status
Simulation time 884352134 ps
CPU time 6.05 seconds
Started Jul 14 06:04:31 PM PDT 24
Finished Jul 14 06:04:38 PM PDT 24
Peak memory 246200 kb
Host smart-087a97c3-f815-4404-b6e2-832e9b863c9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976477970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1976477970
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2768121821
Short name T1116
Test name
Test status
Simulation time 8494944085 ps
CPU time 76.34 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:05:50 PM PDT 24
Peak memory 934428 kb
Host smart-a2fddcfb-e72d-4893-af14-b128cafce72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768121821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2768121821
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3248362905
Short name T1184
Test name
Test status
Simulation time 763624395 ps
CPU time 6.54 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:46 PM PDT 24
Peak memory 205460 kb
Host smart-5bc24bb6-1e6e-4fc0-8c69-d2f5d12f8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248362905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3248362905
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.1832075343
Short name T1157
Test name
Test status
Simulation time 18402759 ps
CPU time 0.67 seconds
Started Jul 14 06:04:33 PM PDT 24
Finished Jul 14 06:04:35 PM PDT 24
Peak memory 205172 kb
Host smart-17826a45-1b99-4ef6-8567-c3918c238840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832075343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1832075343
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2868028925
Short name T1277
Test name
Test status
Simulation time 25590928745 ps
CPU time 294.13 seconds
Started Jul 14 06:04:37 PM PDT 24
Finished Jul 14 06:09:32 PM PDT 24
Peak memory 269136 kb
Host smart-80c58148-9351-4646-8d6a-28b81dcc4c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868028925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2868028925
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2886932038
Short name T1479
Test name
Test status
Simulation time 23254095765 ps
CPU time 558.67 seconds
Started Jul 14 06:04:36 PM PDT 24
Finished Jul 14 06:13:56 PM PDT 24
Peak memory 2538888 kb
Host smart-3ba8472a-a38f-4505-b935-a3dc4d91adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886932038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2886932038
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1268034060
Short name T1101
Test name
Test status
Simulation time 1622988970 ps
CPU time 33.13 seconds
Started Jul 14 06:04:34 PM PDT 24
Finished Jul 14 06:05:08 PM PDT 24
Peak memory 373704 kb
Host smart-3a6b7622-6c47-49ee-be07-1c7d4f9e27a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268034060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1268034060
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2971308344
Short name T266
Test name
Test status
Simulation time 37452456541 ps
CPU time 958.34 seconds
Started Jul 14 06:04:39 PM PDT 24
Finished Jul 14 06:20:38 PM PDT 24
Peak memory 1951740 kb
Host smart-7fbbab60-0e8a-4c2d-9acd-c3217cbfa937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971308344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2971308344
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3266684184
Short name T460
Test name
Test status
Simulation time 1475440796 ps
CPU time 12.99 seconds
Started Jul 14 06:04:37 PM PDT 24
Finished Jul 14 06:04:51 PM PDT 24
Peak memory 221800 kb
Host smart-e2e2d37d-4cf4-44c3-8586-4803e8c5e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266684184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3266684184
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1275962901
Short name T1674
Test name
Test status
Simulation time 1383518868 ps
CPU time 8 seconds
Started Jul 14 06:04:39 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 215740 kb
Host smart-f41a88b7-06cd-4600-8e2b-789d3745ec15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275962901 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1275962901
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2425635763
Short name T1661
Test name
Test status
Simulation time 435954514 ps
CPU time 1.1 seconds
Started Jul 14 06:04:39 PM PDT 24
Finished Jul 14 06:04:40 PM PDT 24
Peak memory 205396 kb
Host smart-caea7537-26ca-460c-9ae9-2d5986295bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425635763 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2425635763
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1959658156
Short name T1313
Test name
Test status
Simulation time 198656371 ps
CPU time 0.99 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:40 PM PDT 24
Peak memory 205388 kb
Host smart-7c029f71-6427-4836-8ae6-b163804eceb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959658156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1959658156
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3237425437
Short name T887
Test name
Test status
Simulation time 1830275306 ps
CPU time 2.51 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:41 PM PDT 24
Peak memory 205624 kb
Host smart-5810458d-605a-43d3-a54d-90bdb166650c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237425437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3237425437
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1014421943
Short name T1544
Test name
Test status
Simulation time 399366001 ps
CPU time 0.99 seconds
Started Jul 14 06:04:40 PM PDT 24
Finished Jul 14 06:04:42 PM PDT 24
Peak memory 205376 kb
Host smart-5d437d6b-bb70-4a35-b37a-ee41f3ae0238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014421943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1014421943
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2759041568
Short name T397
Test name
Test status
Simulation time 2056798277 ps
CPU time 5.65 seconds
Started Jul 14 06:04:41 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 216308 kb
Host smart-38ea955e-098a-4172-a737-ef35aab5b50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759041568 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2759041568
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2279188203
Short name T1009
Test name
Test status
Simulation time 8728790978 ps
CPU time 5.89 seconds
Started Jul 14 06:04:40 PM PDT 24
Finished Jul 14 06:04:47 PM PDT 24
Peak memory 205696 kb
Host smart-942f1f06-424a-4b44-916b-34a4d8c5a80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279188203 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2279188203
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.350896241
Short name T1521
Test name
Test status
Simulation time 489493812 ps
CPU time 2.46 seconds
Started Jul 14 06:04:43 PM PDT 24
Finished Jul 14 06:04:46 PM PDT 24
Peak memory 205572 kb
Host smart-7056774e-9e48-4336-b83b-4b3cda336f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350896241 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.350896241
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.806707770
Short name T1541
Test name
Test status
Simulation time 778878332 ps
CPU time 5.62 seconds
Started Jul 14 06:04:41 PM PDT 24
Finished Jul 14 06:04:47 PM PDT 24
Peak memory 220628 kb
Host smart-25f8e615-6ada-4862-9e8f-ff0ec5f15574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806707770 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_perf.806707770
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.2079639537
Short name T735
Test name
Test status
Simulation time 1531749940 ps
CPU time 2.24 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:04:49 PM PDT 24
Peak memory 205300 kb
Host smart-d4d51321-3fa6-4066-bbd0-bae6d316e375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079639537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.2079639537
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.768867659
Short name T516
Test name
Test status
Simulation time 4609366933 ps
CPU time 37.25 seconds
Started Jul 14 06:04:40 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 213720 kb
Host smart-f6149251-95ea-470e-bbf3-6ac9b4a17edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768867659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.768867659
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2720264105
Short name T1448
Test name
Test status
Simulation time 47283723057 ps
CPU time 1271.35 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:25:50 PM PDT 24
Peak memory 5663876 kb
Host smart-0148b4ec-789d-4017-abc3-a6e762f317ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720264105 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2720264105
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4046282935
Short name T323
Test name
Test status
Simulation time 1074533670 ps
CPU time 19.16 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:58 PM PDT 24
Peak memory 222124 kb
Host smart-06fded8e-8152-4df6-88c2-fed943d686f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046282935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4046282935
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3927155337
Short name T1621
Test name
Test status
Simulation time 42036202327 ps
CPU time 258.55 seconds
Started Jul 14 06:04:40 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 2816156 kb
Host smart-f76f21c4-1ebd-44e0-98f2-54e71af39211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927155337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3927155337
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1605813256
Short name T1408
Test name
Test status
Simulation time 936235296 ps
CPU time 11.4 seconds
Started Jul 14 06:04:37 PM PDT 24
Finished Jul 14 06:04:49 PM PDT 24
Peak memory 347660 kb
Host smart-bd7fb418-a906-4869-a82c-e5f44e35f115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605813256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1605813256
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.832728511
Short name T944
Test name
Test status
Simulation time 20575990870 ps
CPU time 6.81 seconds
Started Jul 14 06:04:39 PM PDT 24
Finished Jul 14 06:04:47 PM PDT 24
Peak memory 230124 kb
Host smart-c1aa8b91-4b0c-4ecf-8420-1e46486a8162
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832728511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.832728511
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.972097170
Short name T1523
Test name
Test status
Simulation time 285362643 ps
CPU time 3.98 seconds
Started Jul 14 06:04:38 PM PDT 24
Finished Jul 14 06:04:43 PM PDT 24
Peak memory 213752 kb
Host smart-c114cb57-4c34-4fda-bd5d-11179914ee17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972097170 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.972097170
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4003272492
Short name T788
Test name
Test status
Simulation time 19657215 ps
CPU time 0.68 seconds
Started Jul 14 06:01:03 PM PDT 24
Finished Jul 14 06:01:04 PM PDT 24
Peak memory 204864 kb
Host smart-ec3e726a-e583-4582-91e8-6289979a46f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003272492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4003272492
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.180865507
Short name T495
Test name
Test status
Simulation time 213011278 ps
CPU time 5.42 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:13 PM PDT 24
Peak memory 229984 kb
Host smart-a63df066-13fa-4367-b9ad-f0d78e0a9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180865507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.180865507
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1858210234
Short name T1543
Test name
Test status
Simulation time 1418550918 ps
CPU time 6.11 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:13 PM PDT 24
Peak memory 272144 kb
Host smart-a6ade30d-16c0-4315-972b-8a8f4d066caa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858210234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1858210234
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3038408096
Short name T971
Test name
Test status
Simulation time 4024700750 ps
CPU time 133.27 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:03:21 PM PDT 24
Peak memory 549824 kb
Host smart-ccc94fe3-f192-49ae-92d1-6fff4d2245d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038408096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3038408096
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3332912643
Short name T1135
Test name
Test status
Simulation time 2326518389 ps
CPU time 121.06 seconds
Started Jul 14 06:01:04 PM PDT 24
Finished Jul 14 06:03:06 PM PDT 24
Peak memory 528640 kb
Host smart-415f9c56-72db-4787-8029-b6d8b9cb68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332912643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3332912643
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1482655082
Short name T1622
Test name
Test status
Simulation time 489281749 ps
CPU time 1.03 seconds
Started Jul 14 06:01:05 PM PDT 24
Finished Jul 14 06:01:06 PM PDT 24
Peak memory 205184 kb
Host smart-11deb76f-a7c1-443a-89c9-38c5ef5988a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482655082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1482655082
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.130201500
Short name T941
Test name
Test status
Simulation time 159312738 ps
CPU time 3.33 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 205496 kb
Host smart-b6c3b64d-cd2b-4538-a3a5-1bd81a8cd50d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130201500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.130201500
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.4175136488
Short name T800
Test name
Test status
Simulation time 18106801836 ps
CPU time 165.04 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 822092 kb
Host smart-cd734293-ff02-41d6-b6bb-b6a8c2de3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175136488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.4175136488
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2503658100
Short name T251
Test name
Test status
Simulation time 3251179422 ps
CPU time 7.14 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:14 PM PDT 24
Peak memory 205464 kb
Host smart-01b89e4d-97b6-4fbf-9488-faae3e3d3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503658100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2503658100
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.3820423083
Short name T1183
Test name
Test status
Simulation time 86429949 ps
CPU time 0.67 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:07 PM PDT 24
Peak memory 205188 kb
Host smart-26349129-ad4a-485c-ab8c-ffe20b9e046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820423083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3820423083
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3384930671
Short name T719
Test name
Test status
Simulation time 7162634484 ps
CPU time 95.84 seconds
Started Jul 14 06:01:10 PM PDT 24
Finished Jul 14 06:02:47 PM PDT 24
Peak memory 987792 kb
Host smart-b9f6942e-1f56-4d88-8c93-b664e5ec2f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384930671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3384930671
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.1489806520
Short name T1270
Test name
Test status
Simulation time 236184481 ps
CPU time 4.48 seconds
Started Jul 14 06:01:04 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 239244 kb
Host smart-3970fb84-1902-4458-aacc-eca7b89ac5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489806520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.1489806520
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2114078403
Short name T1571
Test name
Test status
Simulation time 1576554824 ps
CPU time 78.57 seconds
Started Jul 14 06:01:09 PM PDT 24
Finished Jul 14 06:02:28 PM PDT 24
Peak memory 382708 kb
Host smart-ead07050-64aa-4e51-a98d-d5fd9e56cab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114078403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2114078403
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.647487594
Short name T343
Test name
Test status
Simulation time 459039349 ps
CPU time 7.66 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:16 PM PDT 24
Peak memory 213940 kb
Host smart-e7e1f5ef-1923-452a-9042-35ea4599e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647487594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.647487594
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.33204536
Short name T977
Test name
Test status
Simulation time 2357942610 ps
CPU time 6.31 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:14 PM PDT 24
Peak memory 218992 kb
Host smart-f79e2add-6713-45c3-a734-03bdbe47f585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204536 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.33204536
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3098739195
Short name T1216
Test name
Test status
Simulation time 171141003 ps
CPU time 1.13 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:08 PM PDT 24
Peak memory 205572 kb
Host smart-bb83c4ba-49b4-4e4b-be2c-40d5d2f1b501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098739195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3098739195
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1836466100
Short name T1617
Test name
Test status
Simulation time 373627761 ps
CPU time 1.1 seconds
Started Jul 14 06:01:10 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 205336 kb
Host smart-60ea3ae1-45e0-4c6a-baf4-e3de9689bbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836466100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1836466100
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.4061656383
Short name T1411
Test name
Test status
Simulation time 1716257837 ps
CPU time 2.5 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:01:10 PM PDT 24
Peak memory 205604 kb
Host smart-d30f5f27-6892-4abf-bc2f-b37024a95a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061656383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.4061656383
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.1752359027
Short name T652
Test name
Test status
Simulation time 189492710 ps
CPU time 1.69 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:01:11 PM PDT 24
Peak memory 205328 kb
Host smart-c1e7777b-ca11-44c5-92af-a06d16cf12a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752359027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.1752359027
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2626278396
Short name T1251
Test name
Test status
Simulation time 906793091 ps
CPU time 5.11 seconds
Started Jul 14 06:01:03 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 219788 kb
Host smart-1b770c8a-26c6-477f-aebf-a111cd3ed5a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626278396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2626278396
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.533743863
Short name T852
Test name
Test status
Simulation time 27656998069 ps
CPU time 1000.6 seconds
Started Jul 14 06:01:05 PM PDT 24
Finished Jul 14 06:17:46 PM PDT 24
Peak memory 6718516 kb
Host smart-9390f2d4-5065-4ace-bdae-d1561af55f91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533743863 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.533743863
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.939240668
Short name T1388
Test name
Test status
Simulation time 1268616210 ps
CPU time 3.32 seconds
Started Jul 14 06:01:04 PM PDT 24
Finished Jul 14 06:01:08 PM PDT 24
Peak memory 213812 kb
Host smart-5655bc9d-9f62-46dd-92e1-838b29f8f594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939240668 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_nack_acqfull.939240668
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3589546959
Short name T1146
Test name
Test status
Simulation time 2114507574 ps
CPU time 2.94 seconds
Started Jul 14 06:01:10 PM PDT 24
Finished Jul 14 06:01:13 PM PDT 24
Peak memory 205480 kb
Host smart-bfac372a-3e23-404b-832d-7dc325808836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589546959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3589546959
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.1604180394
Short name T45
Test name
Test status
Simulation time 841686099 ps
CPU time 5.99 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:15 PM PDT 24
Peak memory 218284 kb
Host smart-bc60faac-5fe2-463f-b9ec-f27e8ba40099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604180394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.1604180394
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.3684950628
Short name T644
Test name
Test status
Simulation time 978194449 ps
CPU time 2.22 seconds
Started Jul 14 06:01:05 PM PDT 24
Finished Jul 14 06:01:08 PM PDT 24
Peak memory 205336 kb
Host smart-2dd5b98c-d51b-4cda-a2d4-c64bb531f756
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684950628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.3684950628
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.4182445480
Short name T78
Test name
Test status
Simulation time 15513617797 ps
CPU time 25.83 seconds
Started Jul 14 06:01:04 PM PDT 24
Finished Jul 14 06:01:31 PM PDT 24
Peak memory 213872 kb
Host smart-b3482ccb-3a35-4036-a842-71af92d753db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182445480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.4182445480
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1466813460
Short name T912
Test name
Test status
Simulation time 43913583929 ps
CPU time 1102.88 seconds
Started Jul 14 06:01:05 PM PDT 24
Finished Jul 14 06:19:28 PM PDT 24
Peak memory 6611632 kb
Host smart-a534833d-04d2-4be6-a397-3a47927476e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466813460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1466813460
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3435420335
Short name T4
Test name
Test status
Simulation time 5910182868 ps
CPU time 66.12 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:02:15 PM PDT 24
Peak memory 219172 kb
Host smart-0d28ba23-fa36-4b9c-b2d0-56a0e29ae88c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435420335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3435420335
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2467915695
Short name T853
Test name
Test status
Simulation time 42946568649 ps
CPU time 264.1 seconds
Started Jul 14 06:01:05 PM PDT 24
Finished Jul 14 06:05:30 PM PDT 24
Peak memory 2867712 kb
Host smart-372a0e4f-ef1c-47af-8671-59597d78bb13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467915695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2467915695
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.338522264
Short name T376
Test name
Test status
Simulation time 773478110 ps
CPU time 14.91 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:23 PM PDT 24
Peak memory 262144 kb
Host smart-4a4be363-66bd-4bd8-a090-4608f5d132ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338522264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.338522264
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2468508633
Short name T686
Test name
Test status
Simulation time 4548846496 ps
CPU time 6.2 seconds
Started Jul 14 06:01:09 PM PDT 24
Finished Jul 14 06:01:16 PM PDT 24
Peak memory 213876 kb
Host smart-1762bdb3-fe1c-4678-bd5a-8702893d948d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468508633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2468508633
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.4206522600
Short name T1172
Test name
Test status
Simulation time 43493885 ps
CPU time 0.65 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:51 PM PDT 24
Peak memory 204788 kb
Host smart-aae45a18-5b1f-4a4d-a207-927e9d8e8552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206522600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.4206522600
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.993974613
Short name T537
Test name
Test status
Simulation time 162955507 ps
CPU time 4.82 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:04:52 PM PDT 24
Peak memory 213744 kb
Host smart-c4cf2e46-8d20-4202-90f2-bb95de47d9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993974613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.993974613
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.4086240720
Short name T517
Test name
Test status
Simulation time 343134348 ps
CPU time 17.69 seconds
Started Jul 14 06:04:44 PM PDT 24
Finished Jul 14 06:05:02 PM PDT 24
Peak memory 277824 kb
Host smart-0a58b77c-923f-49e5-9964-d430d9ad50e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086240720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.4086240720
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1243411134
Short name T1156
Test name
Test status
Simulation time 6374356432 ps
CPU time 200.97 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 601128 kb
Host smart-9cdb3c56-5aa8-471e-b2d9-905b054a8945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243411134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1243411134
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3281773560
Short name T1089
Test name
Test status
Simulation time 38020475254 ps
CPU time 65.49 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 707636 kb
Host smart-c6e3f711-8e96-4ce5-a1b1-b3366feca244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281773560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3281773560
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3238074968
Short name T1455
Test name
Test status
Simulation time 75888322 ps
CPU time 0.92 seconds
Started Jul 14 06:04:47 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 205116 kb
Host smart-c752e32d-1472-4775-a12b-a5045a0d2f58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238074968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3238074968
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.182028268
Short name T1727
Test name
Test status
Simulation time 276305268 ps
CPU time 3.71 seconds
Started Jul 14 06:04:47 PM PDT 24
Finished Jul 14 06:04:51 PM PDT 24
Peak memory 228112 kb
Host smart-4312fb0a-133a-4b57-a368-fa525b01bfc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182028268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
182028268
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.4029980666
Short name T689
Test name
Test status
Simulation time 1459670687 ps
CPU time 7.65 seconds
Started Jul 14 06:04:49 PM PDT 24
Finished Jul 14 06:04:57 PM PDT 24
Peak memory 205456 kb
Host smart-bf7d4a65-2d1f-4d29-a03c-a18d1405986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029980666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.4029980666
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1354566101
Short name T1692
Test name
Test status
Simulation time 104914590 ps
CPU time 1.79 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:53 PM PDT 24
Peak memory 220844 kb
Host smart-83676a4c-88e1-4062-843f-0e5279331cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354566101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1354566101
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.996193196
Short name T134
Test name
Test status
Simulation time 29122642 ps
CPU time 0.69 seconds
Started Jul 14 06:04:45 PM PDT 24
Finished Jul 14 06:04:47 PM PDT 24
Peak memory 205200 kb
Host smart-936ff3f1-ec46-4921-b123-8cb6723e27be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996193196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.996193196
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3301654050
Short name T1030
Test name
Test status
Simulation time 53400771187 ps
CPU time 842.05 seconds
Started Jul 14 06:04:43 PM PDT 24
Finished Jul 14 06:18:46 PM PDT 24
Peak memory 2338896 kb
Host smart-67230519-a685-4186-bcf4-7f09832219c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301654050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3301654050
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.1591298607
Short name T685
Test name
Test status
Simulation time 286965219 ps
CPU time 1.83 seconds
Started Jul 14 06:04:45 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 219628 kb
Host smart-06c9326d-5d0b-40fe-b00b-926813583261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591298607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.1591298607
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3712725079
Short name T338
Test name
Test status
Simulation time 1894738424 ps
CPU time 44.48 seconds
Started Jul 14 06:04:46 PM PDT 24
Finished Jul 14 06:05:31 PM PDT 24
Peak memory 273404 kb
Host smart-0100e425-a5b3-4e71-8f6d-0ee19f4b55d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712725079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3712725079
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.992528642
Short name T1039
Test name
Test status
Simulation time 799660253 ps
CPU time 13.1 seconds
Started Jul 14 06:04:44 PM PDT 24
Finished Jul 14 06:04:58 PM PDT 24
Peak memory 221436 kb
Host smart-9a926681-bd20-4238-a173-fe3765c1e097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992528642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.992528642
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.400262703
Short name T445
Test name
Test status
Simulation time 5146250308 ps
CPU time 4.96 seconds
Started Jul 14 06:04:51 PM PDT 24
Finished Jul 14 06:04:57 PM PDT 24
Peak memory 218796 kb
Host smart-8b7ae9a5-78a4-4b8b-83f2-d47900a4f675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400262703 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.400262703
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.527281881
Short name T1038
Test name
Test status
Simulation time 237561827 ps
CPU time 1.43 seconds
Started Jul 14 06:04:49 PM PDT 24
Finished Jul 14 06:04:51 PM PDT 24
Peak memory 205600 kb
Host smart-7eb742cf-68df-4506-876f-33e45b948ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527281881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.527281881
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.663813866
Short name T156
Test name
Test status
Simulation time 368335939 ps
CPU time 0.92 seconds
Started Jul 14 06:04:52 PM PDT 24
Finished Jul 14 06:04:53 PM PDT 24
Peak memory 205464 kb
Host smart-7cfb9920-bd22-4c24-859e-f34cb2922481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663813866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.663813866
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3466663557
Short name T1094
Test name
Test status
Simulation time 2237294413 ps
CPU time 3.14 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:54 PM PDT 24
Peak memory 205572 kb
Host smart-0e840a48-fb96-42d6-af1a-a89ddfbe05f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466663557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3466663557
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.77962921
Short name T1354
Test name
Test status
Simulation time 112503541 ps
CPU time 1.25 seconds
Started Jul 14 06:04:54 PM PDT 24
Finished Jul 14 06:04:56 PM PDT 24
Peak memory 205372 kb
Host smart-dfbcb8c8-8540-437d-827b-394f75fce19e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77962921 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.77962921
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1055172478
Short name T543
Test name
Test status
Simulation time 4737115494 ps
CPU time 6.94 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:58 PM PDT 24
Peak memory 217680 kb
Host smart-3a17bed2-c779-47fe-abf6-9e492df3cd7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055172478 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1055172478
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4286552973
Short name T1437
Test name
Test status
Simulation time 17949101437 ps
CPU time 99.99 seconds
Started Jul 14 06:04:51 PM PDT 24
Finished Jul 14 06:06:32 PM PDT 24
Peak memory 1380020 kb
Host smart-6da551c3-1033-4720-aaf7-045bd2464078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286552973 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4286552973
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.2565131750
Short name T1032
Test name
Test status
Simulation time 1527765320 ps
CPU time 2.34 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:53 PM PDT 24
Peak memory 213840 kb
Host smart-771cda10-ebdd-4654-a1ce-c242b5cab72d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565131750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.2565131750
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.3419427019
Short name T497
Test name
Test status
Simulation time 1718985178 ps
CPU time 2.3 seconds
Started Jul 14 06:04:55 PM PDT 24
Finished Jul 14 06:04:58 PM PDT 24
Peak memory 205588 kb
Host smart-290aaa57-fbfc-445f-b2b8-966f65225eef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419427019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.3419427019
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.3343596056
Short name T834
Test name
Test status
Simulation time 138625579 ps
CPU time 1.32 seconds
Started Jul 14 06:04:48 PM PDT 24
Finished Jul 14 06:04:50 PM PDT 24
Peak memory 222308 kb
Host smart-0612ed08-5e86-4ec2-a032-8c39eaf755ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343596056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.3343596056
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.163251274
Short name T908
Test name
Test status
Simulation time 556922566 ps
CPU time 4.48 seconds
Started Jul 14 06:04:54 PM PDT 24
Finished Jul 14 06:05:00 PM PDT 24
Peak memory 214076 kb
Host smart-1b2f9b79-0673-438f-abe0-056ab7fc1d6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163251274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_perf.163251274
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.4164617566
Short name T780
Test name
Test status
Simulation time 585014411 ps
CPU time 2.19 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:04:53 PM PDT 24
Peak memory 205424 kb
Host smart-01f17aaf-27f1-4c4c-a299-ed2866fcedb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164617566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.4164617566
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3205589688
Short name T707
Test name
Test status
Simulation time 9671545974 ps
CPU time 7.23 seconds
Started Jul 14 06:04:49 PM PDT 24
Finished Jul 14 06:04:57 PM PDT 24
Peak memory 213820 kb
Host smart-06838c5d-0697-472b-ae30-54d93f333afa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205589688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3205589688
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.1748280469
Short name T925
Test name
Test status
Simulation time 68490822781 ps
CPU time 331.68 seconds
Started Jul 14 06:04:55 PM PDT 24
Finished Jul 14 06:10:27 PM PDT 24
Peak memory 2315436 kb
Host smart-ab101f3e-5e52-4c7a-9201-f0cebe1967e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748280469 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.1748280469
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.354323301
Short name T256
Test name
Test status
Simulation time 1890963480 ps
CPU time 28.57 seconds
Started Jul 14 06:04:57 PM PDT 24
Finished Jul 14 06:05:26 PM PDT 24
Peak memory 238188 kb
Host smart-510fb744-6928-41ed-88aa-1870ae8e61cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354323301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.354323301
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.908513997
Short name T678
Test name
Test status
Simulation time 65151215421 ps
CPU time 933.41 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:20:24 PM PDT 24
Peak memory 5769648 kb
Host smart-ec395214-a039-468a-94ad-944cf3f71f91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908513997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.908513997
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1532640048
Short name T1582
Test name
Test status
Simulation time 5690391619 ps
CPU time 10.6 seconds
Started Jul 14 06:04:50 PM PDT 24
Finished Jul 14 06:05:01 PM PDT 24
Peak memory 309888 kb
Host smart-f4d6b70d-7585-4e9e-9ef6-e0dd1edbc926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532640048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1532640048
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1985473068
Short name T358
Test name
Test status
Simulation time 2565001843 ps
CPU time 6.91 seconds
Started Jul 14 06:04:53 PM PDT 24
Finished Jul 14 06:05:00 PM PDT 24
Peak memory 220364 kb
Host smart-a142deb3-a563-4371-9523-6c0656612954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985473068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1985473068
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.3379078439
Short name T1150
Test name
Test status
Simulation time 301701905 ps
CPU time 4.02 seconds
Started Jul 14 06:04:55 PM PDT 24
Finished Jul 14 06:04:59 PM PDT 24
Peak memory 213760 kb
Host smart-73304b9d-709f-490c-8c8a-b2b278e887ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379078439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.3379078439
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.4022740214
Short name T1255
Test name
Test status
Simulation time 35060640 ps
CPU time 0.64 seconds
Started Jul 14 06:05:05 PM PDT 24
Finished Jul 14 06:05:06 PM PDT 24
Peak memory 204856 kb
Host smart-a7174541-61ca-4764-9e12-bc865dbed494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022740214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.4022740214
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2563306710
Short name T1322
Test name
Test status
Simulation time 847371932 ps
CPU time 6.42 seconds
Started Jul 14 06:05:02 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 221628 kb
Host smart-81783ae7-9d62-49ce-b496-8ebc2c0ab37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563306710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2563306710
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.965101526
Short name T532
Test name
Test status
Simulation time 277712369 ps
CPU time 6.32 seconds
Started Jul 14 06:04:57 PM PDT 24
Finished Jul 14 06:05:04 PM PDT 24
Peak memory 261564 kb
Host smart-22c4ec6a-2f32-47c0-a97d-f77a4f896899
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965101526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.965101526
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2195975085
Short name T782
Test name
Test status
Simulation time 5572968492 ps
CPU time 182.69 seconds
Started Jul 14 06:04:59 PM PDT 24
Finished Jul 14 06:08:02 PM PDT 24
Peak memory 524660 kb
Host smart-bf06a206-f988-4630-a0b1-8670bde92d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195975085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2195975085
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2712407360
Short name T161
Test name
Test status
Simulation time 2497004133 ps
CPU time 178.55 seconds
Started Jul 14 06:04:57 PM PDT 24
Finished Jul 14 06:07:56 PM PDT 24
Peak memory 763452 kb
Host smart-5c7530a4-accc-4225-b35c-bb495e30fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712407360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2712407360
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3014516042
Short name T1163
Test name
Test status
Simulation time 131509763 ps
CPU time 1.23 seconds
Started Jul 14 06:04:59 PM PDT 24
Finished Jul 14 06:05:01 PM PDT 24
Peak memory 205088 kb
Host smart-1d064b19-cc27-40a2-8e35-e7836c3ec2ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014516042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3014516042
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.411918013
Short name T380
Test name
Test status
Simulation time 117345142 ps
CPU time 6.59 seconds
Started Jul 14 06:05:00 PM PDT 24
Finished Jul 14 06:05:07 PM PDT 24
Peak memory 205492 kb
Host smart-858602b9-b0da-4069-a10d-10d1ee2af7b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411918013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
411918013
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.175861863
Short name T153
Test name
Test status
Simulation time 14349056038 ps
CPU time 238.79 seconds
Started Jul 14 06:04:58 PM PDT 24
Finished Jul 14 06:08:58 PM PDT 24
Peak memory 1102320 kb
Host smart-e69a343c-b4e9-4061-ae26-5fc21736bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175861863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.175861863
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1883045695
Short name T20
Test name
Test status
Simulation time 955466622 ps
CPU time 7.1 seconds
Started Jul 14 06:05:03 PM PDT 24
Finished Jul 14 06:05:11 PM PDT 24
Peak memory 205452 kb
Host smart-40dc471a-bba5-48f0-925f-cd7070cddaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883045695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1883045695
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.1316683778
Short name T708
Test name
Test status
Simulation time 17971971 ps
CPU time 0.68 seconds
Started Jul 14 06:05:00 PM PDT 24
Finished Jul 14 06:05:01 PM PDT 24
Peak memory 205228 kb
Host smart-7a98d7de-fcf1-43dd-9d9d-57e32889db1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316683778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1316683778
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2022544109
Short name T1325
Test name
Test status
Simulation time 10141564177 ps
CPU time 25.36 seconds
Started Jul 14 06:04:57 PM PDT 24
Finished Jul 14 06:05:23 PM PDT 24
Peak memory 313936 kb
Host smart-e82ec345-5c49-467f-b0b1-b5d88cbfded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022544109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2022544109
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.263924270
Short name T1356
Test name
Test status
Simulation time 73378808 ps
CPU time 1.92 seconds
Started Jul 14 06:04:58 PM PDT 24
Finished Jul 14 06:05:00 PM PDT 24
Peak memory 221600 kb
Host smart-16b89661-0562-43c0-8015-1a70cc57251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263924270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.263924270
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3672944893
Short name T753
Test name
Test status
Simulation time 3387826800 ps
CPU time 107.33 seconds
Started Jul 14 06:04:56 PM PDT 24
Finished Jul 14 06:06:44 PM PDT 24
Peak memory 367352 kb
Host smart-a23582d3-b4f9-4a55-8ff1-e647dd4d9c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672944893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3672944893
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.325754240
Short name T1147
Test name
Test status
Simulation time 2745972894 ps
CPU time 20.84 seconds
Started Jul 14 06:05:01 PM PDT 24
Finished Jul 14 06:05:22 PM PDT 24
Peak memory 221724 kb
Host smart-4f7ae7d3-6565-4b56-b071-49cb1b887137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325754240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.325754240
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.4243465014
Short name T937
Test name
Test status
Simulation time 4595897462 ps
CPU time 6.65 seconds
Started Jul 14 06:05:05 PM PDT 24
Finished Jul 14 06:05:12 PM PDT 24
Peak memory 222056 kb
Host smart-1bdd48a6-f405-44c5-9731-c42453501b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243465014 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.4243465014
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1458599316
Short name T1699
Test name
Test status
Simulation time 707335988 ps
CPU time 1.89 seconds
Started Jul 14 06:05:06 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 205744 kb
Host smart-10e7d1c1-76ab-4849-9be3-07ffe38ba9a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458599316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1458599316
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1426493829
Short name T922
Test name
Test status
Simulation time 154097430 ps
CPU time 0.99 seconds
Started Jul 14 06:05:03 PM PDT 24
Finished Jul 14 06:05:05 PM PDT 24
Peak memory 205440 kb
Host smart-34d16f6e-485c-430e-a032-735909dfea5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426493829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1426493829
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.4174303209
Short name T1453
Test name
Test status
Simulation time 1383308965 ps
CPU time 2.4 seconds
Started Jul 14 06:05:03 PM PDT 24
Finished Jul 14 06:05:06 PM PDT 24
Peak memory 205880 kb
Host smart-a584c637-4ff2-4752-9dc1-880b02b3aec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174303209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.4174303209
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.2578430313
Short name T1475
Test name
Test status
Simulation time 132308832 ps
CPU time 1.13 seconds
Started Jul 14 06:05:01 PM PDT 24
Finished Jul 14 06:05:03 PM PDT 24
Peak memory 205444 kb
Host smart-b5872634-4e60-4331-a677-22c0fa7b13dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578430313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.2578430313
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3421613309
Short name T1628
Test name
Test status
Simulation time 545942265 ps
CPU time 2.23 seconds
Started Jul 14 06:05:07 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 213716 kb
Host smart-69ee8240-a4b0-4c11-8283-a206d0b6dd80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421613309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3421613309
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1070723807
Short name T996
Test name
Test status
Simulation time 694649528 ps
CPU time 3.88 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:05:14 PM PDT 24
Peak memory 213824 kb
Host smart-92b9a3ba-d649-4a98-a78e-1adb5b11fdec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070723807 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1070723807
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3447153990
Short name T1025
Test name
Test status
Simulation time 8745059701 ps
CPU time 29.4 seconds
Started Jul 14 06:05:04 PM PDT 24
Finished Jul 14 06:05:34 PM PDT 24
Peak memory 556200 kb
Host smart-baa3b43b-7fa0-42d7-9282-2a6dc3f16b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447153990 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3447153990
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.408608818
Short name T1484
Test name
Test status
Simulation time 452539973 ps
CPU time 2.77 seconds
Started Jul 14 06:05:06 PM PDT 24
Finished Jul 14 06:05:10 PM PDT 24
Peak memory 213764 kb
Host smart-49c33fe7-eb70-40bf-8544-7f03962e5f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408608818 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_nack_acqfull.408608818
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.1458799557
Short name T467
Test name
Test status
Simulation time 2466967625 ps
CPU time 2.71 seconds
Started Jul 14 06:05:10 PM PDT 24
Finished Jul 14 06:05:13 PM PDT 24
Peak memory 205632 kb
Host smart-1615beae-60ba-4b3b-bab6-3ea24bafed93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458799557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.1458799557
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.1492332345
Short name T935
Test name
Test status
Simulation time 537581281 ps
CPU time 1.39 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:05:11 PM PDT 24
Peak memory 222412 kb
Host smart-16c487cc-e2cf-4aed-bee4-e453266e5734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492332345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_nack_txstretch.1492332345
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.1010880198
Short name T314
Test name
Test status
Simulation time 853647666 ps
CPU time 5.49 seconds
Started Jul 14 06:05:02 PM PDT 24
Finished Jul 14 06:05:08 PM PDT 24
Peak memory 218652 kb
Host smart-9c2b530f-89dd-4ec9-8c27-3fa4159a22ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010880198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.1010880198
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.2599858261
Short name T328
Test name
Test status
Simulation time 3486251768 ps
CPU time 2.5 seconds
Started Jul 14 06:05:01 PM PDT 24
Finished Jul 14 06:05:04 PM PDT 24
Peak memory 205424 kb
Host smart-e068863f-f285-419f-8ab3-18d304d0976b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599858261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.2599858261
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1094407648
Short name T1238
Test name
Test status
Simulation time 1101332060 ps
CPU time 7.99 seconds
Started Jul 14 06:05:07 PM PDT 24
Finished Jul 14 06:05:15 PM PDT 24
Peak memory 213744 kb
Host smart-ced228a8-857e-4034-916d-1e9d8d6f2b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094407648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1094407648
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.405440926
Short name T488
Test name
Test status
Simulation time 20475087091 ps
CPU time 249.36 seconds
Started Jul 14 06:05:02 PM PDT 24
Finished Jul 14 06:09:11 PM PDT 24
Peak memory 2728460 kb
Host smart-b2a0f5d1-3837-4a43-9aa0-513b9684076b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405440926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.405440926
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1318528874
Short name T614
Test name
Test status
Simulation time 5071010710 ps
CPU time 62.23 seconds
Started Jul 14 06:05:02 PM PDT 24
Finished Jul 14 06:06:05 PM PDT 24
Peak memory 215168 kb
Host smart-b054d00c-4ff8-491d-9567-804ade4d0a6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318528874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1318528874
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3002970296
Short name T1586
Test name
Test status
Simulation time 26804666646 ps
CPU time 21.93 seconds
Started Jul 14 06:05:05 PM PDT 24
Finished Jul 14 06:05:28 PM PDT 24
Peak memory 506232 kb
Host smart-6722db55-3b5e-431b-a24a-f1dd2791a266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002970296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3002970296
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.797126610
Short name T647
Test name
Test status
Simulation time 7025239015 ps
CPU time 7.24 seconds
Started Jul 14 06:05:03 PM PDT 24
Finished Jul 14 06:05:11 PM PDT 24
Peak memory 221960 kb
Host smart-9e5217db-9e0c-4ba6-8173-e1144c040fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797126610 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.797126610
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1847771147
Short name T337
Test name
Test status
Simulation time 24031289 ps
CPU time 0.67 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:05:19 PM PDT 24
Peak memory 204688 kb
Host smart-626ce694-6a7b-4dc8-ace9-addd9af17b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847771147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1847771147
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3514566467
Short name T300
Test name
Test status
Simulation time 359832934 ps
CPU time 1.56 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:05:11 PM PDT 24
Peak memory 213792 kb
Host smart-4c647ad7-761b-426d-b0c3-83317fe1f3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514566467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3514566467
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3186049457
Short name T581
Test name
Test status
Simulation time 1701367132 ps
CPU time 23.15 seconds
Started Jul 14 06:05:08 PM PDT 24
Finished Jul 14 06:05:32 PM PDT 24
Peak memory 300564 kb
Host smart-fc895c37-6be8-4cda-8874-b00ce576a051
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186049457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3186049457
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3387495996
Short name T1242
Test name
Test status
Simulation time 10717541687 ps
CPU time 145.83 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 592136 kb
Host smart-9bd995c1-cca4-4799-a6a2-05c712bc2c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387495996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3387495996
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1788236926
Short name T93
Test name
Test status
Simulation time 19572895640 ps
CPU time 64.14 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:06:16 PM PDT 24
Peak memory 703476 kb
Host smart-f508de63-45a3-49a1-904a-ba0df88fe0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788236926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1788236926
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.789713840
Short name T825
Test name
Test status
Simulation time 859745168 ps
CPU time 1.29 seconds
Started Jul 14 06:05:10 PM PDT 24
Finished Jul 14 06:05:12 PM PDT 24
Peak memory 205472 kb
Host smart-d941dcd2-7f30-4c7b-bbcb-a10f31fc8a83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789713840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.789713840
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1779726130
Short name T1374
Test name
Test status
Simulation time 143448485 ps
CPU time 7.12 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:05:17 PM PDT 24
Peak memory 205460 kb
Host smart-c2fa46fa-fbc1-4b10-9533-19eff9038842
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779726130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1779726130
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4009667773
Short name T1043
Test name
Test status
Simulation time 25664388463 ps
CPU time 140.75 seconds
Started Jul 14 06:05:10 PM PDT 24
Finished Jul 14 06:07:31 PM PDT 24
Peak memory 1515308 kb
Host smart-a70266d7-fe08-45c2-ad9f-8df3a3752e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009667773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4009667773
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.285576250
Short name T1415
Test name
Test status
Simulation time 733281960 ps
CPU time 4.53 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:20 PM PDT 24
Peak memory 205432 kb
Host smart-13a1c6fa-a595-4873-ab95-3a72e68dc2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285576250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.285576250
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.4238232132
Short name T71
Test name
Test status
Simulation time 29549147 ps
CPU time 0.68 seconds
Started Jul 14 06:05:07 PM PDT 24
Finished Jul 14 06:05:08 PM PDT 24
Peak memory 205156 kb
Host smart-306f35dc-ead4-4a55-bf99-fe1b197705da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238232132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.4238232132
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2381541598
Short name T819
Test name
Test status
Simulation time 973452914 ps
CPU time 4.57 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:05:16 PM PDT 24
Peak memory 230068 kb
Host smart-deef6a64-7a79-4913-a73e-65caf19a6459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381541598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2381541598
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.223614568
Short name T1236
Test name
Test status
Simulation time 5848281244 ps
CPU time 141.6 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:07:34 PM PDT 24
Peak memory 1211432 kb
Host smart-53a846eb-b038-4b5e-a6bc-e19b5f42ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223614568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.223614568
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1191227176
Short name T349
Test name
Test status
Simulation time 1225326229 ps
CPU time 58.32 seconds
Started Jul 14 06:05:01 PM PDT 24
Finished Jul 14 06:06:00 PM PDT 24
Peak memory 334816 kb
Host smart-ef8ef3a8-2e8d-4b74-bb19-6b1ce993c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191227176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1191227176
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.732581240
Short name T116
Test name
Test status
Simulation time 50732452410 ps
CPU time 221.94 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:08:51 PM PDT 24
Peak memory 1202952 kb
Host smart-e74ede44-32b4-43e6-a8e8-27bde2104d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732581240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.732581240
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3215347218
Short name T550
Test name
Test status
Simulation time 2139849140 ps
CPU time 11.12 seconds
Started Jul 14 06:05:12 PM PDT 24
Finished Jul 14 06:05:24 PM PDT 24
Peak memory 214052 kb
Host smart-44b2f207-b833-4669-9ec8-7305ce1fcd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215347218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3215347218
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2400518115
Short name T974
Test name
Test status
Simulation time 6816875644 ps
CPU time 4.99 seconds
Started Jul 14 06:05:18 PM PDT 24
Finished Jul 14 06:05:23 PM PDT 24
Peak memory 222092 kb
Host smart-1440c482-6f24-4842-9b76-55d2e4208b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400518115 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2400518115
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2789340677
Short name T656
Test name
Test status
Simulation time 310137658 ps
CPU time 0.79 seconds
Started Jul 14 06:05:07 PM PDT 24
Finished Jul 14 06:05:09 PM PDT 24
Peak memory 205420 kb
Host smart-6a1e5aa8-6691-481c-913b-1679ed4a05d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789340677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2789340677
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3863540408
Short name T1675
Test name
Test status
Simulation time 539344912 ps
CPU time 1.15 seconds
Started Jul 14 06:05:18 PM PDT 24
Finished Jul 14 06:05:20 PM PDT 24
Peak memory 205368 kb
Host smart-7c89f211-a21c-4cfd-8c90-fee6e754ecd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863540408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3863540408
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1256591731
Short name T1572
Test name
Test status
Simulation time 1031489503 ps
CPU time 2.83 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 205584 kb
Host smart-42495ce5-e096-46c9-8d03-81084cee1aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256591731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1256591731
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.4199498892
Short name T1317
Test name
Test status
Simulation time 128556260 ps
CPU time 1.1 seconds
Started Jul 14 06:05:16 PM PDT 24
Finished Jul 14 06:05:17 PM PDT 24
Peak memory 205396 kb
Host smart-3c2e3536-dfb9-48df-80da-1ed37f676af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199498892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.4199498892
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2249037129
Short name T1050
Test name
Test status
Simulation time 971114605 ps
CPU time 6.16 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 217192 kb
Host smart-55532775-e4cd-493e-b5b9-00c4255bff6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249037129 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2249037129
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1574502778
Short name T883
Test name
Test status
Simulation time 11540211793 ps
CPU time 69.9 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 1480120 kb
Host smart-b0257d77-06d7-40ba-b75a-8fccb83e657a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574502778 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1574502778
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.2129958374
Short name T64
Test name
Test status
Simulation time 424546457 ps
CPU time 2.69 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:05:21 PM PDT 24
Peak memory 213776 kb
Host smart-9752eb64-608a-4227-a6b0-4174880ef571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129958374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.2129958374
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.3363000958
Short name T555
Test name
Test status
Simulation time 2331770289 ps
CPU time 2.86 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 205636 kb
Host smart-acfbb536-4a39-4406-8f57-847ffa334a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363000958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.3363000958
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1172076593
Short name T911
Test name
Test status
Simulation time 872780898 ps
CPU time 6.36 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:05:23 PM PDT 24
Peak memory 220196 kb
Host smart-ed75bd80-7b7d-4b4c-80ea-1a960bb42d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172076593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1172076593
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.3733280303
Short name T914
Test name
Test status
Simulation time 2445940776 ps
CPU time 2.15 seconds
Started Jul 14 06:05:18 PM PDT 24
Finished Jul 14 06:05:21 PM PDT 24
Peak memory 205344 kb
Host smart-46ab0bf4-2826-4b25-9867-06f95651d9b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733280303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.3733280303
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.597615736
Short name T1503
Test name
Test status
Simulation time 4827091262 ps
CPU time 36.7 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:05:48 PM PDT 24
Peak memory 213860 kb
Host smart-7cf08664-f172-4435-8399-709b2617ffa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597615736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.597615736
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.1445018432
Short name T163
Test name
Test status
Simulation time 41315435664 ps
CPU time 31.62 seconds
Started Jul 14 06:05:16 PM PDT 24
Finished Jul 14 06:05:48 PM PDT 24
Peak memory 255568 kb
Host smart-0e64a634-fab7-43d5-8de8-831da2762aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445018432 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.1445018432
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3961458956
Short name T1716
Test name
Test status
Simulation time 890329730 ps
CPU time 19.47 seconds
Started Jul 14 06:05:10 PM PDT 24
Finished Jul 14 06:05:30 PM PDT 24
Peak memory 205624 kb
Host smart-ef094e02-2543-4b1c-8b39-fc588eba4c15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961458956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3961458956
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.870482566
Short name T121
Test name
Test status
Simulation time 39231947426 ps
CPU time 82.46 seconds
Started Jul 14 06:05:11 PM PDT 24
Finished Jul 14 06:06:34 PM PDT 24
Peak memory 1236236 kb
Host smart-07e94a8e-6c52-46e7-89f6-383cbe0c1b9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870482566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.870482566
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2924917221
Short name T709
Test name
Test status
Simulation time 2295268587 ps
CPU time 9.54 seconds
Started Jul 14 06:05:09 PM PDT 24
Finished Jul 14 06:05:20 PM PDT 24
Peak memory 303712 kb
Host smart-b5fce706-d13c-4b50-86ad-5fba15bc1c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924917221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2924917221
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.4108534231
Short name T558
Test name
Test status
Simulation time 1448887626 ps
CPU time 7.81 seconds
Started Jul 14 06:05:10 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 233612 kb
Host smart-226b4a76-15c2-400c-a52d-d5781dc74cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108534231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.4108534231
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.3355612830
Short name T465
Test name
Test status
Simulation time 421936913 ps
CPU time 5.82 seconds
Started Jul 14 06:05:19 PM PDT 24
Finished Jul 14 06:05:25 PM PDT 24
Peak memory 221268 kb
Host smart-65567e38-a9aa-46fe-98a6-fc7290ec8553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355612830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3355612830
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3549018176
Short name T1282
Test name
Test status
Simulation time 16945545 ps
CPU time 0.65 seconds
Started Jul 14 06:05:25 PM PDT 24
Finished Jul 14 06:05:26 PM PDT 24
Peak memory 204728 kb
Host smart-3194a375-48de-491e-8ac7-d3b45f534fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549018176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3549018176
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.170696777
Short name T1253
Test name
Test status
Simulation time 350034920 ps
CPU time 2.63 seconds
Started Jul 14 06:05:26 PM PDT 24
Finished Jul 14 06:05:30 PM PDT 24
Peak memory 213736 kb
Host smart-0d364f93-3434-431d-ad45-b1e1078c7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170696777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.170696777
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3363540974
Short name T1028
Test name
Test status
Simulation time 200620552 ps
CPU time 9.82 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:05:28 PM PDT 24
Peak memory 238092 kb
Host smart-f3ac557c-c152-44b1-b727-bdf4972a63f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363540974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3363540974
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.975688554
Short name T545
Test name
Test status
Simulation time 2386562936 ps
CPU time 72.05 seconds
Started Jul 14 06:05:21 PM PDT 24
Finished Jul 14 06:06:33 PM PDT 24
Peak memory 418996 kb
Host smart-e0289f4b-6e93-4679-989b-493c7aa4567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975688554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.975688554
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2705674578
Short name T1524
Test name
Test status
Simulation time 9978886365 ps
CPU time 184.94 seconds
Started Jul 14 06:05:16 PM PDT 24
Finished Jul 14 06:08:22 PM PDT 24
Peak memory 761184 kb
Host smart-3add8513-78d5-439a-8b5d-1d245644c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705674578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2705674578
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3073575180
Short name T648
Test name
Test status
Simulation time 204263692 ps
CPU time 1.06 seconds
Started Jul 14 06:05:16 PM PDT 24
Finished Jul 14 06:05:17 PM PDT 24
Peak memory 205228 kb
Host smart-a5c26199-a1ac-4d1c-b145-2cf92355f0d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073575180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3073575180
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.352361882
Short name T965
Test name
Test status
Simulation time 514211075 ps
CPU time 3.2 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:19 PM PDT 24
Peak memory 205456 kb
Host smart-749b3837-d057-4df0-aa52-65052102b1c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352361882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
352361882
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3176208424
Short name T874
Test name
Test status
Simulation time 13366774087 ps
CPU time 238.08 seconds
Started Jul 14 06:05:18 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 1041292 kb
Host smart-61305ad1-1245-46d1-a3e9-73d70fd0838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176208424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3176208424
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1042774348
Short name T242
Test name
Test status
Simulation time 1627633904 ps
CPU time 6 seconds
Started Jul 14 06:05:29 PM PDT 24
Finished Jul 14 06:05:35 PM PDT 24
Peak memory 205460 kb
Host smart-cbd69e8d-0bef-4f64-8417-c190900957d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042774348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1042774348
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.1167146515
Short name T132
Test name
Test status
Simulation time 131855294 ps
CPU time 0.68 seconds
Started Jul 14 06:05:16 PM PDT 24
Finished Jul 14 06:05:17 PM PDT 24
Peak memory 205080 kb
Host smart-0ef379b8-d1c5-44ca-8f84-2052f8a54d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167146515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1167146515
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3883847192
Short name T1362
Test name
Test status
Simulation time 514978832 ps
CPU time 1.86 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 221792 kb
Host smart-ee012e1c-5bd2-410f-8849-5a953e155e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883847192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3883847192
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.3853905448
Short name T994
Test name
Test status
Simulation time 1572449215 ps
CPU time 60.99 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:06:19 PM PDT 24
Peak memory 205464 kb
Host smart-8fb44ae5-0d08-43e2-a48a-fc636eea6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853905448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.3853905448
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3345934686
Short name T1174
Test name
Test status
Simulation time 4979812312 ps
CPU time 18.92 seconds
Started Jul 14 06:05:17 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 303684 kb
Host smart-f62cc305-09a2-443f-bf0f-9607a97cda89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345934686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3345934686
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3256326521
Short name T1347
Test name
Test status
Simulation time 13440898038 ps
CPU time 36.34 seconds
Started Jul 14 06:05:15 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 213764 kb
Host smart-532a8568-eacb-43bc-9b01-dc32ebe9b9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256326521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3256326521
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.924776735
Short name T1460
Test name
Test status
Simulation time 4270977437 ps
CPU time 5.34 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:30 PM PDT 24
Peak memory 211828 kb
Host smart-bf97d4ea-38f5-455a-9b88-0b420350ab4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924776735 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.924776735
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2534549057
Short name T609
Test name
Test status
Simulation time 695820807 ps
CPU time 1.02 seconds
Started Jul 14 06:05:26 PM PDT 24
Finished Jul 14 06:05:28 PM PDT 24
Peak memory 205416 kb
Host smart-9b78e79c-9ac8-4ad0-a950-7f1457e91ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534549057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2534549057
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3489874043
Short name T602
Test name
Test status
Simulation time 159632377 ps
CPU time 1.06 seconds
Started Jul 14 06:05:23 PM PDT 24
Finished Jul 14 06:05:24 PM PDT 24
Peak memory 205408 kb
Host smart-129b577e-ca28-41c4-8df7-53e6d04f85ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489874043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3489874043
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2449384759
Short name T662
Test name
Test status
Simulation time 348575415 ps
CPU time 2.1 seconds
Started Jul 14 06:05:33 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 205364 kb
Host smart-0cf61c08-373f-4e22-aac6-8cffb8d5eeaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449384759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2449384759
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.2011672574
Short name T463
Test name
Test status
Simulation time 160729569 ps
CPU time 1.28 seconds
Started Jul 14 06:05:33 PM PDT 24
Finished Jul 14 06:05:35 PM PDT 24
Peak memory 205344 kb
Host smart-d22609ff-e37b-4ec3-857e-4eefbcc8ee3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011672574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.2011672574
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2378194875
Short name T1587
Test name
Test status
Simulation time 961403600 ps
CPU time 1.94 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:27 PM PDT 24
Peak memory 213796 kb
Host smart-4b86a876-96e7-4aa8-b2d7-a8ca5ca89b71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378194875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2378194875
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1562909317
Short name T483
Test name
Test status
Simulation time 1873877979 ps
CPU time 8.37 seconds
Started Jul 14 06:05:27 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 221876 kb
Host smart-89120a7f-214f-4f7a-90e6-f51619343bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562909317 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1562909317
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2718161367
Short name T1293
Test name
Test status
Simulation time 16330720901 ps
CPU time 204.85 seconds
Started Jul 14 06:05:27 PM PDT 24
Finished Jul 14 06:08:52 PM PDT 24
Peak memory 2342552 kb
Host smart-a207556d-b820-44b6-946c-459ca9589d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718161367 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2718161367
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.147561129
Short name T599
Test name
Test status
Simulation time 1084460277 ps
CPU time 3.2 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:27 PM PDT 24
Peak memory 213876 kb
Host smart-a846137d-1f5b-4415-bd6b-9bf050e883bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147561129 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_nack_acqfull.147561129
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.2900890368
Short name T1338
Test name
Test status
Simulation time 3101100412 ps
CPU time 2.51 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:27 PM PDT 24
Peak memory 205616 kb
Host smart-c44d466f-be98-483b-ac63-c5473a49092c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900890368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.2900890368
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.1504050144
Short name T898
Test name
Test status
Simulation time 1653105041 ps
CPU time 4.22 seconds
Started Jul 14 06:05:31 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 214308 kb
Host smart-7e5125f9-bfdb-49e8-b7c6-a8a01d972416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504050144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.1504050144
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1438230433
Short name T1221
Test name
Test status
Simulation time 953050312 ps
CPU time 2.31 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:27 PM PDT 24
Peak memory 205312 kb
Host smart-19292231-8047-45a1-8ee5-5f60b6d047b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438230433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1438230433
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2922492357
Short name T120
Test name
Test status
Simulation time 3833442620 ps
CPU time 11.63 seconds
Started Jul 14 06:05:25 PM PDT 24
Finished Jul 14 06:05:37 PM PDT 24
Peak memory 217392 kb
Host smart-e5771ed0-c1e8-40cd-ac2f-e5bb662412e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922492357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2922492357
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.772746216
Short name T180
Test name
Test status
Simulation time 15091600202 ps
CPU time 113.66 seconds
Started Jul 14 06:05:27 PM PDT 24
Finished Jul 14 06:07:21 PM PDT 24
Peak memory 1228984 kb
Host smart-d56e37bc-30f3-4e71-a9a8-a704c1579ca0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772746216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_target_stress_all.772746216
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3017982906
Short name T978
Test name
Test status
Simulation time 3669727305 ps
CPU time 14.41 seconds
Started Jul 14 06:05:23 PM PDT 24
Finished Jul 14 06:05:38 PM PDT 24
Peak memory 223416 kb
Host smart-6ecfc448-03e6-404e-9b05-e40e5adc1830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017982906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3017982906
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4065244684
Short name T1249
Test name
Test status
Simulation time 8732788645 ps
CPU time 18.28 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:43 PM PDT 24
Peak memory 205572 kb
Host smart-29021888-415a-4e1d-88d9-b87f670851df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065244684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4065244684
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3378279531
Short name T351
Test name
Test status
Simulation time 1670798877 ps
CPU time 7.32 seconds
Started Jul 14 06:05:24 PM PDT 24
Finished Jul 14 06:05:31 PM PDT 24
Peak memory 222012 kb
Host smart-f13553c2-7ab7-440a-bc5a-e0c5cde2f458
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378279531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3378279531
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.364126947
Short name T768
Test name
Test status
Simulation time 390681288 ps
CPU time 5.08 seconds
Started Jul 14 06:05:28 PM PDT 24
Finished Jul 14 06:05:34 PM PDT 24
Peak memory 214632 kb
Host smart-5065bc5a-5c34-492c-8023-5acb091d65f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364126947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.364126947
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2105543161
Short name T429
Test name
Test status
Simulation time 32633589 ps
CPU time 0.67 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:39 PM PDT 24
Peak memory 204808 kb
Host smart-96c9c246-c6ef-495a-acea-488b31368799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105543161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2105543161
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2128102183
Short name T1702
Test name
Test status
Simulation time 746660171 ps
CPU time 6.06 seconds
Started Jul 14 06:05:32 PM PDT 24
Finished Jul 14 06:05:38 PM PDT 24
Peak memory 213712 kb
Host smart-f5223811-f7c7-4948-bf26-2b0b5428792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128102183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2128102183
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.4181587318
Short name T945
Test name
Test status
Simulation time 345238218 ps
CPU time 7.34 seconds
Started Jul 14 06:05:34 PM PDT 24
Finished Jul 14 06:05:42 PM PDT 24
Peak memory 266920 kb
Host smart-15d9d023-aca5-4700-899f-db04df4dd2f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181587318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.4181587318
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2257787838
Short name T1011
Test name
Test status
Simulation time 9493854349 ps
CPU time 68.97 seconds
Started Jul 14 06:05:30 PM PDT 24
Finished Jul 14 06:06:40 PM PDT 24
Peak memory 497080 kb
Host smart-a5829d0c-6311-41c7-90c1-b3e846477609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257787838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2257787838
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.985143216
Short name T442
Test name
Test status
Simulation time 7989617400 ps
CPU time 124.44 seconds
Started Jul 14 06:05:25 PM PDT 24
Finished Jul 14 06:07:30 PM PDT 24
Peak memory 615700 kb
Host smart-55cb3700-3d22-4916-8c3e-dad23a047877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985143216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.985143216
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2492146769
Short name T480
Test name
Test status
Simulation time 738694674 ps
CPU time 0.97 seconds
Started Jul 14 06:05:45 PM PDT 24
Finished Jul 14 06:05:47 PM PDT 24
Peak memory 205172 kb
Host smart-d356607e-a0a1-4390-be08-642c301c7770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492146769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2492146769
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2107717319
Short name T41
Test name
Test status
Simulation time 654816132 ps
CPU time 8.44 seconds
Started Jul 14 06:05:31 PM PDT 24
Finished Jul 14 06:05:40 PM PDT 24
Peak memory 205388 kb
Host smart-b03c450e-3930-4801-a75f-4de162e2c557
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107717319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2107717319
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.4007723572
Short name T43
Test name
Test status
Simulation time 8865952700 ps
CPU time 139.34 seconds
Started Jul 14 06:05:26 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 1310868 kb
Host smart-d4358a25-e6ca-4feb-89a5-e27dc62cf015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007723572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.4007723572
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2627731568
Short name T236
Test name
Test status
Simulation time 1229305974 ps
CPU time 9.75 seconds
Started Jul 14 06:05:39 PM PDT 24
Finished Jul 14 06:05:49 PM PDT 24
Peak memory 205472 kb
Host smart-234818d6-f46d-49f4-99d7-4f448c499ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627731568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2627731568
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.206187794
Short name T1705
Test name
Test status
Simulation time 19808527 ps
CPU time 0.65 seconds
Started Jul 14 06:05:22 PM PDT 24
Finished Jul 14 06:05:23 PM PDT 24
Peak memory 205180 kb
Host smart-c1cdb61b-bd43-423d-a4c3-92032e426280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206187794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.206187794
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3554256494
Short name T668
Test name
Test status
Simulation time 48689015643 ps
CPU time 181.35 seconds
Started Jul 14 06:05:45 PM PDT 24
Finished Jul 14 06:08:48 PM PDT 24
Peak memory 783712 kb
Host smart-d5a5f41d-699f-4a79-a485-acd4919bab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554256494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3554256494
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3636293327
Short name T1056
Test name
Test status
Simulation time 73854409 ps
CPU time 1.84 seconds
Started Jul 14 06:05:31 PM PDT 24
Finished Jul 14 06:05:34 PM PDT 24
Peak memory 213500 kb
Host smart-8dda8df9-430a-426f-a0d7-ae4bd834a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636293327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3636293327
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1664862771
Short name T1690
Test name
Test status
Simulation time 6479643797 ps
CPU time 27.18 seconds
Started Jul 14 06:05:26 PM PDT 24
Finished Jul 14 06:05:53 PM PDT 24
Peak memory 374284 kb
Host smart-916ee42e-f685-42d6-8773-6ea97663be64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664862771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1664862771
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1971549827
Short name T901
Test name
Test status
Simulation time 1525774033 ps
CPU time 14.99 seconds
Started Jul 14 06:05:47 PM PDT 24
Finished Jul 14 06:06:03 PM PDT 24
Peak memory 217916 kb
Host smart-1a130d04-4ce0-45c3-980e-0d04074610e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971549827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1971549827
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2852672986
Short name T524
Test name
Test status
Simulation time 4334594750 ps
CPU time 6.09 seconds
Started Jul 14 06:05:40 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 219552 kb
Host smart-36a5960f-9c3f-44b0-8484-8b93fea84295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852672986 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2852672986
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3863880942
Short name T1497
Test name
Test status
Simulation time 164164636 ps
CPU time 1.11 seconds
Started Jul 14 06:05:32 PM PDT 24
Finished Jul 14 06:05:33 PM PDT 24
Peak memory 205376 kb
Host smart-4a809c6c-7194-4a6f-966e-b98ac7380d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863880942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3863880942
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2388434335
Short name T1685
Test name
Test status
Simulation time 203585038 ps
CPU time 1.31 seconds
Started Jul 14 06:05:34 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 205596 kb
Host smart-41a87a03-ab9e-43c0-a652-e9539ba915b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388434335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2388434335
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3319286401
Short name T1051
Test name
Test status
Simulation time 412507988 ps
CPU time 1.96 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:41 PM PDT 24
Peak memory 205388 kb
Host smart-43129a66-37af-40df-8040-3de7d4a9f0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319286401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3319286401
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.4266444600
Short name T1546
Test name
Test status
Simulation time 381640663 ps
CPU time 1.27 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:40 PM PDT 24
Peak memory 205444 kb
Host smart-b7a5f812-e2fb-4a76-89bc-aae4822b2e9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266444600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.4266444600
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1045901890
Short name T1471
Test name
Test status
Simulation time 8585877588 ps
CPU time 6.07 seconds
Started Jul 14 06:05:29 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 213896 kb
Host smart-969f31d3-7887-4b53-803d-4c7bf90ee3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045901890 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1045901890
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2494898915
Short name T319
Test name
Test status
Simulation time 397810075 ps
CPU time 2.06 seconds
Started Jul 14 06:05:34 PM PDT 24
Finished Jul 14 06:05:36 PM PDT 24
Peak memory 205432 kb
Host smart-5caeff8c-d9d3-426e-82f5-c8f5265b7f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494898915 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2494898915
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3796897402
Short name T1121
Test name
Test status
Simulation time 2585952172 ps
CPU time 3.03 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:42 PM PDT 24
Peak memory 213888 kb
Host smart-aa870156-da3b-47da-9e0e-647356625740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796897402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3796897402
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.2070002203
Short name T990
Test name
Test status
Simulation time 593196324 ps
CPU time 2.99 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:42 PM PDT 24
Peak memory 206508 kb
Host smart-1fca739e-e61b-47ac-9e19-18d5a1b36b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070002203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.2070002203
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2742422996
Short name T546
Test name
Test status
Simulation time 583999285 ps
CPU time 4.54 seconds
Started Jul 14 06:05:32 PM PDT 24
Finished Jul 14 06:05:37 PM PDT 24
Peak memory 217008 kb
Host smart-584f6979-ac45-4816-93d2-685b4cd02fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742422996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2742422996
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.2908842441
Short name T331
Test name
Test status
Simulation time 1029179974 ps
CPU time 2.43 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:41 PM PDT 24
Peak memory 205300 kb
Host smart-3cddef47-f189-4c31-8f7d-6cd7e0931021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908842441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_smbus_maxlen.2908842441
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3470781670
Short name T66
Test name
Test status
Simulation time 902692293 ps
CPU time 15.2 seconds
Started Jul 14 06:05:31 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 213724 kb
Host smart-aa86e48e-fc33-42d8-9f10-dd4eab0ef888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470781670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3470781670
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.299912980
Short name T1566
Test name
Test status
Simulation time 76145916788 ps
CPU time 72.34 seconds
Started Jul 14 06:05:30 PM PDT 24
Finished Jul 14 06:06:43 PM PDT 24
Peak memory 850664 kb
Host smart-7a3cf0fe-a606-4749-8048-29e375fa4f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299912980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_target_stress_all.299912980
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3742715133
Short name T373
Test name
Test status
Simulation time 951709790 ps
CPU time 45.39 seconds
Started Jul 14 06:05:30 PM PDT 24
Finished Jul 14 06:06:16 PM PDT 24
Peak memory 213816 kb
Host smart-91e2b4e7-3062-49b9-a472-cb2006ac23ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742715133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3742715133
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3834023181
Short name T1085
Test name
Test status
Simulation time 29649865491 ps
CPU time 203.84 seconds
Started Jul 14 06:05:30 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 2427352 kb
Host smart-11484c7a-8d7e-4164-82b2-17e2e9342572
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834023181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3834023181
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.923043526
Short name T842
Test name
Test status
Simulation time 4849303907 ps
CPU time 13.13 seconds
Started Jul 14 06:05:29 PM PDT 24
Finished Jul 14 06:05:42 PM PDT 24
Peak memory 468204 kb
Host smart-bc8e6dba-7bdb-4c25-add4-e195f80106b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923043526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.923043526
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2722782192
Short name T1292
Test name
Test status
Simulation time 1244131870 ps
CPU time 6.79 seconds
Started Jul 14 06:05:30 PM PDT 24
Finished Jul 14 06:05:37 PM PDT 24
Peak memory 213780 kb
Host smart-e43d2722-3848-4f49-b25b-2653bebad7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722782192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2722782192
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.2199511891
Short name T1316
Test name
Test status
Simulation time 75480409 ps
CPU time 1.75 seconds
Started Jul 14 06:05:41 PM PDT 24
Finished Jul 14 06:05:43 PM PDT 24
Peak memory 205612 kb
Host smart-3f705885-8501-4ea2-9362-2e5e38202926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199511891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2199511891
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2575220500
Short name T1359
Test name
Test status
Simulation time 15864548 ps
CPU time 0.65 seconds
Started Jul 14 06:05:50 PM PDT 24
Finished Jul 14 06:05:51 PM PDT 24
Peak memory 204872 kb
Host smart-3e1942d7-ddd5-4df6-9d2b-131aa44738cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575220500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2575220500
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2656243056
Short name T458
Test name
Test status
Simulation time 143332172 ps
CPU time 4.49 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:05:48 PM PDT 24
Peak memory 221992 kb
Host smart-03eed640-0cf2-44d3-98ba-7298c99c3da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656243056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2656243056
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2438025385
Short name T750
Test name
Test status
Simulation time 8182801376 ps
CPU time 8.18 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:47 PM PDT 24
Peak memory 283080 kb
Host smart-e6f9d13a-0a45-4322-8efe-5a1f362f0d19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438025385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2438025385
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2163011643
Short name T386
Test name
Test status
Simulation time 9439238259 ps
CPU time 60.92 seconds
Started Jul 14 06:05:42 PM PDT 24
Finished Jul 14 06:06:44 PM PDT 24
Peak memory 517848 kb
Host smart-b3e14cd6-853f-4f51-8910-f5ef8a3f192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163011643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2163011643
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1908282794
Short name T1627
Test name
Test status
Simulation time 11092654968 ps
CPU time 90.08 seconds
Started Jul 14 06:05:41 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 870796 kb
Host smart-05886162-78a4-4c33-ad58-6e35f7353c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908282794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1908282794
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1955446130
Short name T232
Test name
Test status
Simulation time 98796776 ps
CPU time 1 seconds
Started Jul 14 06:05:39 PM PDT 24
Finished Jul 14 06:05:40 PM PDT 24
Peak memory 205468 kb
Host smart-bf3c21e9-fcaf-4d67-a990-5e385a4548aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955446130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1955446130
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2672186251
Short name T1081
Test name
Test status
Simulation time 1165035218 ps
CPU time 5.76 seconds
Started Jul 14 06:05:39 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 205508 kb
Host smart-d71e143d-3242-43ae-b7eb-0c8a8ed3b2b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672186251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2672186251
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.295847800
Short name T930
Test name
Test status
Simulation time 3772249451 ps
CPU time 93.42 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:07:17 PM PDT 24
Peak memory 972888 kb
Host smart-4dee8740-1e1e-454b-bd06-b73ecce687e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295847800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.295847800
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.914212559
Short name T767
Test name
Test status
Simulation time 328253461 ps
CPU time 4.85 seconds
Started Jul 14 06:05:45 PM PDT 24
Finished Jul 14 06:05:50 PM PDT 24
Peak memory 205392 kb
Host smart-7b68088d-3963-452f-bc9d-d4c86f216105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914212559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.914212559
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.3360382398
Short name T1000
Test name
Test status
Simulation time 18943430 ps
CPU time 0.66 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:05:44 PM PDT 24
Peak memory 205176 kb
Host smart-7c6a0816-051b-4161-bb40-d9102191dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360382398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3360382398
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3670451960
Short name T636
Test name
Test status
Simulation time 49739916025 ps
CPU time 128.34 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:07:47 PM PDT 24
Peak memory 213724 kb
Host smart-7d1bb388-190a-4d2c-ab21-f337d871e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670451960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3670451960
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.3440908166
Short name T182
Test name
Test status
Simulation time 32237774 ps
CPU time 1.3 seconds
Started Jul 14 06:05:38 PM PDT 24
Finished Jul 14 06:05:40 PM PDT 24
Peak memory 223512 kb
Host smart-3a063c00-df66-4010-880b-68a28b812616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440908166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.3440908166
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3057595484
Short name T790
Test name
Test status
Simulation time 23506906448 ps
CPU time 37.18 seconds
Started Jul 14 06:05:37 PM PDT 24
Finished Jul 14 06:06:15 PM PDT 24
Peak memory 426572 kb
Host smart-986ef210-1e92-458b-a3d8-366fb7203429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057595484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3057595484
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.517765092
Short name T1667
Test name
Test status
Simulation time 418994466 ps
CPU time 18.84 seconds
Started Jul 14 06:05:44 PM PDT 24
Finished Jul 14 06:06:03 PM PDT 24
Peak memory 213668 kb
Host smart-752b2dc7-23dd-4186-8863-b4302514872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517765092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.517765092
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3569001800
Short name T796
Test name
Test status
Simulation time 5548442234 ps
CPU time 6.87 seconds
Started Jul 14 06:05:48 PM PDT 24
Finished Jul 14 06:05:56 PM PDT 24
Peak memory 222056 kb
Host smart-024cdee6-6241-4540-84d3-4f59c9359e54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569001800 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3569001800
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3198866105
Short name T1261
Test name
Test status
Simulation time 340418140 ps
CPU time 1.4 seconds
Started Jul 14 06:05:42 PM PDT 24
Finished Jul 14 06:05:44 PM PDT 24
Peak memory 205536 kb
Host smart-ded09d96-3052-486c-a2a5-fd5d57a9787b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198866105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3198866105
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3389561973
Short name T1302
Test name
Test status
Simulation time 278331160 ps
CPU time 0.89 seconds
Started Jul 14 06:05:45 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 205480 kb
Host smart-d44dc996-dd92-4bf6-b6ff-5fb9e9547965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389561973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3389561973
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.2430432760
Short name T635
Test name
Test status
Simulation time 2389610332 ps
CPU time 3.18 seconds
Started Jul 14 06:05:48 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 205668 kb
Host smart-48c92ae0-1a97-4c3e-9645-97cfa9adf715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430432760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.2430432760
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.3467113419
Short name T318
Test name
Test status
Simulation time 813677277 ps
CPU time 1.32 seconds
Started Jul 14 06:05:44 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 205360 kb
Host smart-5ff6d5f5-5ff7-4f81-851f-92a94430b57f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467113419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.3467113419
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3371167402
Short name T515
Test name
Test status
Simulation time 984817558 ps
CPU time 2.02 seconds
Started Jul 14 06:05:48 PM PDT 24
Finished Jul 14 06:05:51 PM PDT 24
Peak memory 213828 kb
Host smart-796e313d-6dfa-4d08-9711-1ef586fe56af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371167402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3371167402
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3306202790
Short name T309
Test name
Test status
Simulation time 1187632212 ps
CPU time 6.37 seconds
Started Jul 14 06:05:49 PM PDT 24
Finished Jul 14 06:05:55 PM PDT 24
Peak memory 213772 kb
Host smart-2163951d-97c0-4e97-95e0-2e46107272f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306202790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3306202790
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2036156829
Short name T1562
Test name
Test status
Simulation time 3418800806 ps
CPU time 2.98 seconds
Started Jul 14 06:05:42 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 205708 kb
Host smart-3385cb10-de60-481a-974d-97c310df79ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036156829 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2036156829
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.218363213
Short name T1055
Test name
Test status
Simulation time 2004539979 ps
CPU time 2.83 seconds
Started Jul 14 06:05:48 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 213784 kb
Host smart-45bca6e8-218d-4fe4-b597-3a53cdd74372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218363213 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_nack_acqfull.218363213
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.3217201878
Short name T540
Test name
Test status
Simulation time 550845797 ps
CPU time 2.64 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:05:58 PM PDT 24
Peak memory 205788 kb
Host smart-055d5f68-5e83-4621-89ab-5781eeb2723d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217201878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3217201878
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.3934519598
Short name T820
Test name
Test status
Simulation time 721427347 ps
CPU time 1.39 seconds
Started Jul 14 06:05:53 PM PDT 24
Finished Jul 14 06:05:55 PM PDT 24
Peak memory 222140 kb
Host smart-8a6bfed3-ebfc-4401-895c-6aab02d5840f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934519598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.3934519598
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/25.i2c_target_perf.1414810133
Short name T1040
Test name
Test status
Simulation time 823512838 ps
CPU time 3.16 seconds
Started Jul 14 06:05:44 PM PDT 24
Finished Jul 14 06:05:48 PM PDT 24
Peak memory 213820 kb
Host smart-aa53bff5-2681-456b-b029-d2616b32a689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414810133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.1414810133
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.3374746404
Short name T1704
Test name
Test status
Simulation time 515292236 ps
CPU time 2.5 seconds
Started Jul 14 06:05:44 PM PDT 24
Finished Jul 14 06:05:47 PM PDT 24
Peak memory 205420 kb
Host smart-541d57e6-1ea2-4c54-bdac-26d785f23624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374746404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.3374746404
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2868498582
Short name T124
Test name
Test status
Simulation time 6022096983 ps
CPU time 10.93 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:05:55 PM PDT 24
Peak memory 213852 kb
Host smart-5a2a3182-423a-4a4c-835b-784a43032b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868498582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2868498582
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.3461126410
Short name T950
Test name
Test status
Simulation time 56193319398 ps
CPU time 90.98 seconds
Started Jul 14 06:05:47 PM PDT 24
Finished Jul 14 06:07:19 PM PDT 24
Peak memory 459268 kb
Host smart-391a82f3-93e5-4d67-877b-d5a15baa2bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461126410 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.3461126410
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1679353377
Short name T761
Test name
Test status
Simulation time 369354411 ps
CPU time 6.62 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:05:51 PM PDT 24
Peak memory 205624 kb
Host smart-89b157e9-b533-4f43-9711-4bd1434523f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679353377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1679353377
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3094846207
Short name T1643
Test name
Test status
Simulation time 8344614202 ps
CPU time 17.73 seconds
Started Jul 14 06:05:45 PM PDT 24
Finished Jul 14 06:06:04 PM PDT 24
Peak memory 205648 kb
Host smart-9d906dca-f4aa-416d-ac86-86e10b2bfd13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094846207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3094846207
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1884933991
Short name T806
Test name
Test status
Simulation time 2457269816 ps
CPU time 24.08 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 315408 kb
Host smart-27f28401-721b-4d28-9c8d-4b27c5bcd00b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884933991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1884933991
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.4228160556
Short name T586
Test name
Test status
Simulation time 7624608561 ps
CPU time 6.85 seconds
Started Jul 14 06:05:44 PM PDT 24
Finished Jul 14 06:05:52 PM PDT 24
Peak memory 213848 kb
Host smart-960eb90a-ccd5-4adc-b274-be51b9555b64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228160556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.4228160556
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2893482718
Short name T884
Test name
Test status
Simulation time 91403475 ps
CPU time 1.64 seconds
Started Jul 14 06:05:43 PM PDT 24
Finished Jul 14 06:05:45 PM PDT 24
Peak memory 205520 kb
Host smart-60a7e0de-c05a-49b3-a9cb-30876f146600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893482718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2893482718
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.592579576
Short name T666
Test name
Test status
Simulation time 18935229 ps
CPU time 0.64 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:05:55 PM PDT 24
Peak memory 204796 kb
Host smart-d60460de-29af-4236-9a2e-cc6b50858af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592579576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.592579576
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.711804547
Short name T1502
Test name
Test status
Simulation time 1384121683 ps
CPU time 7.65 seconds
Started Jul 14 06:05:52 PM PDT 24
Finished Jul 14 06:06:00 PM PDT 24
Peak memory 279672 kb
Host smart-bee943b3-9fcc-4907-ac97-a3ea56f01708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711804547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.711804547
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2637889767
Short name T19
Test name
Test status
Simulation time 4232539151 ps
CPU time 111.44 seconds
Started Jul 14 06:05:50 PM PDT 24
Finished Jul 14 06:07:42 PM PDT 24
Peak memory 343192 kb
Host smart-c526dd1f-9ee4-421e-b0eb-656f92add797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637889767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2637889767
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.6321812
Short name T1493
Test name
Test status
Simulation time 1827200662 ps
CPU time 113.48 seconds
Started Jul 14 06:05:50 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 611880 kb
Host smart-4dd2b0de-5226-4e1b-a7f6-f51c9c5c7a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6321812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.6321812
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1638274563
Short name T1602
Test name
Test status
Simulation time 276788660 ps
CPU time 0.86 seconds
Started Jul 14 06:05:49 PM PDT 24
Finished Jul 14 06:05:50 PM PDT 24
Peak memory 205464 kb
Host smart-1edc3c00-61c2-4b9c-99de-5670a6a4b2bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638274563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1638274563
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.193536053
Short name T1719
Test name
Test status
Simulation time 762554824 ps
CPU time 5.2 seconds
Started Jul 14 06:05:53 PM PDT 24
Finished Jul 14 06:05:58 PM PDT 24
Peak memory 242056 kb
Host smart-ad5cb5d1-3051-4c63-8e9b-95fde4ddd53d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193536053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
193536053
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2490692677
Short name T1199
Test name
Test status
Simulation time 8078273430 ps
CPU time 128.59 seconds
Started Jul 14 06:05:51 PM PDT 24
Finished Jul 14 06:08:00 PM PDT 24
Peak memory 1212108 kb
Host smart-5b6ff3b4-2690-4a4c-a06f-932ce7d65a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490692677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2490692677
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.2079092085
Short name T1315
Test name
Test status
Simulation time 1933652281 ps
CPU time 22.55 seconds
Started Jul 14 06:05:56 PM PDT 24
Finished Jul 14 06:06:19 PM PDT 24
Peak memory 205424 kb
Host smart-014a5622-7007-414e-893a-d2365322dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079092085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2079092085
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.1871017771
Short name T932
Test name
Test status
Simulation time 31514539 ps
CPU time 0.71 seconds
Started Jul 14 06:05:53 PM PDT 24
Finished Jul 14 06:05:54 PM PDT 24
Peak memory 205168 kb
Host smart-a2b23a7e-e578-41fb-8bb7-a84ef26ffbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871017771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1871017771
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.194544117
Short name T329
Test name
Test status
Simulation time 3218950760 ps
CPU time 46.42 seconds
Started Jul 14 06:05:49 PM PDT 24
Finished Jul 14 06:06:36 PM PDT 24
Peak memory 389132 kb
Host smart-94f84ea3-e36b-4872-89ac-d4f3ef8a4b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194544117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.194544117
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3873333322
Short name T1138
Test name
Test status
Simulation time 270122830 ps
CPU time 3.64 seconds
Started Jul 14 06:05:50 PM PDT 24
Finished Jul 14 06:05:54 PM PDT 24
Peak memory 229968 kb
Host smart-53d9a4f4-3f03-4ef2-b3f1-786f786fe11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873333322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3873333322
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.2861044927
Short name T33
Test name
Test status
Simulation time 5734941987 ps
CPU time 17.32 seconds
Started Jul 14 06:05:52 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 271504 kb
Host smart-98ed7a0f-c535-4bc2-8a32-3e96cce87ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861044927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2861044927
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2284811463
Short name T292
Test name
Test status
Simulation time 805676012 ps
CPU time 36.04 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:06:30 PM PDT 24
Peak memory 213704 kb
Host smart-1777e969-804f-43d2-b4ed-324954530707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284811463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2284811463
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4130741007
Short name T510
Test name
Test status
Simulation time 2450422065 ps
CPU time 4.07 seconds
Started Jul 14 06:05:57 PM PDT 24
Finished Jul 14 06:06:02 PM PDT 24
Peak memory 218164 kb
Host smart-e35a1b31-c0a3-4ac8-9103-35dbcaffb50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130741007 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4130741007
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.4270256695
Short name T850
Test name
Test status
Simulation time 195654898 ps
CPU time 1.37 seconds
Started Jul 14 06:05:57 PM PDT 24
Finished Jul 14 06:05:59 PM PDT 24
Peak memory 205592 kb
Host smart-43fb48eb-00ec-4979-b5ce-e7cac417a917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270256695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.4270256695
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3194801782
Short name T600
Test name
Test status
Simulation time 505690338 ps
CPU time 1.47 seconds
Started Jul 14 06:05:55 PM PDT 24
Finished Jul 14 06:05:57 PM PDT 24
Peak memory 205572 kb
Host smart-14f5ee72-beea-45d9-a402-e3f6bc6d459f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194801782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3194801782
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1328070680
Short name T560
Test name
Test status
Simulation time 379686194 ps
CPU time 2.42 seconds
Started Jul 14 06:05:55 PM PDT 24
Finished Jul 14 06:05:59 PM PDT 24
Peak memory 205620 kb
Host smart-ccd68a19-b3dc-4da8-9e86-042c811ed45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328070680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1328070680
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1578755429
Short name T1124
Test name
Test status
Simulation time 337757696 ps
CPU time 1.56 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:05:56 PM PDT 24
Peak memory 205416 kb
Host smart-2c7b5ad3-350c-42e0-b6aa-37aadad6370c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578755429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1578755429
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2247423938
Short name T724
Test name
Test status
Simulation time 830269893 ps
CPU time 4.57 seconds
Started Jul 14 06:05:58 PM PDT 24
Finished Jul 14 06:06:03 PM PDT 24
Peak memory 220408 kb
Host smart-28a39fed-99f5-4664-a989-a69f428bcaff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247423938 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2247423938
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2782674976
Short name T562
Test name
Test status
Simulation time 12513475902 ps
CPU time 230.26 seconds
Started Jul 14 06:05:56 PM PDT 24
Finished Jul 14 06:09:47 PM PDT 24
Peak memory 3166040 kb
Host smart-5f4d8012-da29-4522-ac57-d53bb3bb563d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782674976 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2782674976
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.667631813
Short name T1536
Test name
Test status
Simulation time 1747845081 ps
CPU time 2.61 seconds
Started Jul 14 06:05:56 PM PDT 24
Finished Jul 14 06:06:00 PM PDT 24
Peak memory 213844 kb
Host smart-95a68745-a527-4fdf-a57c-5a007d7c5961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667631813 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_nack_acqfull.667631813
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.1674808728
Short name T1576
Test name
Test status
Simulation time 480627184 ps
CPU time 2.46 seconds
Started Jul 14 06:05:57 PM PDT 24
Finished Jul 14 06:06:00 PM PDT 24
Peak memory 205540 kb
Host smart-95fb4bfa-44dc-47bc-b54b-58e06576bb04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674808728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.1674808728
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.2890890946
Short name T749
Test name
Test status
Simulation time 4660761222 ps
CPU time 5.3 seconds
Started Jul 14 06:05:55 PM PDT 24
Finished Jul 14 06:06:02 PM PDT 24
Peak memory 222016 kb
Host smart-79542fac-30a2-4d64-86bd-1d65f239c555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890890946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.2890890946
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.3825357454
Short name T1638
Test name
Test status
Simulation time 1634819296 ps
CPU time 2.14 seconds
Started Jul 14 06:05:58 PM PDT 24
Finished Jul 14 06:06:01 PM PDT 24
Peak memory 205356 kb
Host smart-35c32c6d-2514-4cd2-85ec-7a631bdbd5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825357454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.3825357454
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4190483892
Short name T1511
Test name
Test status
Simulation time 1224096661 ps
CPU time 13.33 seconds
Started Jul 14 06:05:53 PM PDT 24
Finished Jul 14 06:06:06 PM PDT 24
Peak memory 213788 kb
Host smart-4a115035-4890-49d5-8fda-443d4c8e92f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190483892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4190483892
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3205975139
Short name T1545
Test name
Test status
Simulation time 41317965782 ps
CPU time 58.33 seconds
Started Jul 14 06:05:55 PM PDT 24
Finished Jul 14 06:06:54 PM PDT 24
Peak memory 409556 kb
Host smart-0958295b-1f46-4223-aca1-78fbf3a19a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205975139 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3205975139
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1890120991
Short name T1373
Test name
Test status
Simulation time 532456624 ps
CPU time 5.38 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:06:00 PM PDT 24
Peak memory 205588 kb
Host smart-63d84770-e113-4d88-ba7b-8c126ca7dcbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890120991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1890120991
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2456992291
Short name T1636
Test name
Test status
Simulation time 23413820405 ps
CPU time 69.69 seconds
Started Jul 14 06:05:54 PM PDT 24
Finished Jul 14 06:07:05 PM PDT 24
Peak memory 889676 kb
Host smart-db9c201f-1079-4873-bec8-2ffdca2128b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456992291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2456992291
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3745435755
Short name T1165
Test name
Test status
Simulation time 2260530050 ps
CPU time 43.64 seconds
Started Jul 14 06:05:56 PM PDT 24
Finished Jul 14 06:06:40 PM PDT 24
Peak memory 705152 kb
Host smart-1106afc2-3a3e-41fd-b7c0-83f8007fd5e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745435755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3745435755
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3541066372
Short name T1167
Test name
Test status
Simulation time 5224717032 ps
CPU time 7 seconds
Started Jul 14 06:05:58 PM PDT 24
Finished Jul 14 06:06:06 PM PDT 24
Peak memory 213840 kb
Host smart-62597347-224e-424b-b420-ca62f4c80f5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541066372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3541066372
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1102166650
Short name T169
Test name
Test status
Simulation time 26767006 ps
CPU time 0.63 seconds
Started Jul 14 06:06:09 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 204840 kb
Host smart-ef2f7b98-c024-47c2-ac21-d60c31dfee1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102166650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1102166650
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.105746703
Short name T862
Test name
Test status
Simulation time 1531636791 ps
CPU time 6.58 seconds
Started Jul 14 06:06:00 PM PDT 24
Finished Jul 14 06:06:07 PM PDT 24
Peak memory 233352 kb
Host smart-61049438-34ed-4b28-b0b2-ed42e04424c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105746703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.105746703
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.4094114517
Short name T1014
Test name
Test status
Simulation time 1038823516 ps
CPU time 9.29 seconds
Started Jul 14 06:06:01 PM PDT 24
Finished Jul 14 06:06:11 PM PDT 24
Peak memory 317348 kb
Host smart-6fba8915-6967-483b-89f7-9ecdac3d6c8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094114517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.4094114517
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1525416169
Short name T1361
Test name
Test status
Simulation time 4492116320 ps
CPU time 92.84 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:07:40 PM PDT 24
Peak memory 385380 kb
Host smart-3d1fb865-3fc5-44e2-a164-090920073717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525416169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1525416169
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3935773389
Short name T1141
Test name
Test status
Simulation time 2366107192 ps
CPU time 169.82 seconds
Started Jul 14 06:05:56 PM PDT 24
Finished Jul 14 06:08:47 PM PDT 24
Peak memory 769896 kb
Host smart-fad30539-28f0-4a67-95cb-74c2b773de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935773389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3935773389
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.198126325
Short name T421
Test name
Test status
Simulation time 542865937 ps
CPU time 1.22 seconds
Started Jul 14 06:06:03 PM PDT 24
Finished Jul 14 06:06:05 PM PDT 24
Peak memory 205196 kb
Host smart-33cb1623-c8f0-4ea1-8295-a5095d84f48a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198126325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.198126325
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1320572980
Short name T441
Test name
Test status
Simulation time 643846034 ps
CPU time 3.76 seconds
Started Jul 14 06:06:01 PM PDT 24
Finished Jul 14 06:06:06 PM PDT 24
Peak memory 205472 kb
Host smart-ae204ab4-bac1-409c-8246-ac5e676a6436
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320572980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1320572980
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.508893220
Short name T112
Test name
Test status
Simulation time 22884440897 ps
CPU time 151.32 seconds
Started Jul 14 06:05:55 PM PDT 24
Finished Jul 14 06:08:27 PM PDT 24
Peak memory 1604940 kb
Host smart-ffcbbacc-58f0-4b21-9859-d7bece3745a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508893220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.508893220
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2232333556
Short name T252
Test name
Test status
Simulation time 1257205869 ps
CPU time 7.56 seconds
Started Jul 14 06:06:10 PM PDT 24
Finished Jul 14 06:06:18 PM PDT 24
Peak memory 205468 kb
Host smart-3e161da4-4747-4230-aa8b-2f9bfa3f7ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232333556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2232333556
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.3370633531
Short name T1307
Test name
Test status
Simulation time 18688922 ps
CPU time 0.69 seconds
Started Jul 14 06:06:01 PM PDT 24
Finished Jul 14 06:06:02 PM PDT 24
Peak memory 205164 kb
Host smart-a48168e7-dabe-4346-810e-e07d1ef2600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370633531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3370633531
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.4196431701
Short name T16
Test name
Test status
Simulation time 9252471443 ps
CPU time 10.17 seconds
Started Jul 14 06:06:02 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 205592 kb
Host smart-9b9e0aee-ec0a-4ba5-986d-a27929510cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196431701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.4196431701
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.3969482296
Short name T622
Test name
Test status
Simulation time 2384210398 ps
CPU time 19.25 seconds
Started Jul 14 06:06:02 PM PDT 24
Finished Jul 14 06:06:22 PM PDT 24
Peak memory 206604 kb
Host smart-cf513e5c-9727-4098-8c6b-c3269cd18d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969482296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.3969482296
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2230699201
Short name T1082
Test name
Test status
Simulation time 5131672473 ps
CPU time 19.33 seconds
Started Jul 14 06:06:00 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 294820 kb
Host smart-1c4175d2-f171-4bde-84b6-5f44bbff98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230699201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2230699201
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2602852376
Short name T424
Test name
Test status
Simulation time 2118048309 ps
CPU time 12 seconds
Started Jul 14 06:06:03 PM PDT 24
Finished Jul 14 06:06:16 PM PDT 24
Peak memory 213756 kb
Host smart-64aba4ef-4e4d-4f87-9347-2b3d9a4761e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602852376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2602852376
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1765822224
Short name T759
Test name
Test status
Simulation time 1505139949 ps
CPU time 4.33 seconds
Started Jul 14 06:06:03 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 213828 kb
Host smart-d9e3ca4d-e3fe-4e8f-8f07-f04b87474f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765822224 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1765822224
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3850003091
Short name T1093
Test name
Test status
Simulation time 268517162 ps
CPU time 1.79 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:06:09 PM PDT 24
Peak memory 205780 kb
Host smart-cf72638d-c96f-4279-9644-a1566b886523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850003091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3850003091
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.171496524
Short name T718
Test name
Test status
Simulation time 1654596089 ps
CPU time 1.63 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 213780 kb
Host smart-3ae14949-c62b-40aa-9952-5854a75fdf91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171496524 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.171496524
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2374723917
Short name T1219
Test name
Test status
Simulation time 1609162686 ps
CPU time 2.62 seconds
Started Jul 14 06:06:10 PM PDT 24
Finished Jul 14 06:06:14 PM PDT 24
Peak memory 205608 kb
Host smart-32d69fef-7cf0-4d3c-9b59-94dcaf37b4f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374723917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2374723917
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.282069212
Short name T1559
Test name
Test status
Simulation time 442428400 ps
CPU time 1.74 seconds
Started Jul 14 06:06:08 PM PDT 24
Finished Jul 14 06:06:11 PM PDT 24
Peak memory 205440 kb
Host smart-97e4fec3-e660-493b-a207-043c611c30cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282069212 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.282069212
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.605766188
Short name T1435
Test name
Test status
Simulation time 1589261390 ps
CPU time 8.43 seconds
Started Jul 14 06:06:04 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 230112 kb
Host smart-0a4f936c-d983-4835-838d-8bc956c306c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605766188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.605766188
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1812165871
Short name T1540
Test name
Test status
Simulation time 21009155084 ps
CPU time 516.56 seconds
Started Jul 14 06:06:15 PM PDT 24
Finished Jul 14 06:14:53 PM PDT 24
Peak memory 5175700 kb
Host smart-876b68d8-11e8-4d98-a07c-3ed4aeed3931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812165871 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1812165871
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.743760362
Short name T367
Test name
Test status
Simulation time 581923668 ps
CPU time 3.02 seconds
Started Jul 14 06:06:10 PM PDT 24
Finished Jul 14 06:06:14 PM PDT 24
Peak memory 213764 kb
Host smart-a34a11e3-cdd7-46be-a209-c26f6e56027c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743760362 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_nack_acqfull.743760362
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.426020118
Short name T1136
Test name
Test status
Simulation time 402882027 ps
CPU time 2.41 seconds
Started Jul 14 06:06:10 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 205592 kb
Host smart-2e8ccaa8-dd5b-4404-9ee9-2dbb6d3badfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426020118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.426020118
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.4232749998
Short name T1461
Test name
Test status
Simulation time 2433117050 ps
CPU time 1.52 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 222684 kb
Host smart-1f091e18-5680-4352-a5fa-d7fb1dc680bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232749998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_txstretch.4232749998
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.1307226858
Short name T1281
Test name
Test status
Simulation time 1216036118 ps
CPU time 4.78 seconds
Started Jul 14 06:06:10 PM PDT 24
Finished Jul 14 06:06:16 PM PDT 24
Peak memory 220444 kb
Host smart-5f5c4d9c-1fdd-4158-8796-202dc2b2c240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307226858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.1307226858
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.689595275
Short name T393
Test name
Test status
Simulation time 1861797689 ps
CPU time 2.23 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:06:10 PM PDT 24
Peak memory 205448 kb
Host smart-f6e00ea3-55f8-4bd5-b492-89c7d5c9a50a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689595275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_smbus_maxlen.689595275
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3316853780
Short name T687
Test name
Test status
Simulation time 611748573 ps
CPU time 8.11 seconds
Started Jul 14 06:06:04 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 217368 kb
Host smart-3f759aa8-ca39-4f16-9925-47dbc0c5bb07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316853780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3316853780
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.1977950375
Short name T849
Test name
Test status
Simulation time 40274073666 ps
CPU time 999.94 seconds
Started Jul 14 06:06:02 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 4610676 kb
Host smart-b398d238-219f-48f7-b41b-e182156552e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977950375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.1977950375
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3254556154
Short name T452
Test name
Test status
Simulation time 1582561265 ps
CPU time 28.16 seconds
Started Jul 14 06:06:06 PM PDT 24
Finished Jul 14 06:06:35 PM PDT 24
Peak memory 232744 kb
Host smart-370cfe15-43c5-44cd-a11c-3bbe798bbee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254556154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3254556154
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3850895772
Short name T5
Test name
Test status
Simulation time 40109312855 ps
CPU time 648.98 seconds
Started Jul 14 06:06:02 PM PDT 24
Finished Jul 14 06:16:52 PM PDT 24
Peak memory 5030336 kb
Host smart-1ef89e03-e46d-4498-ab60-40bae3ba494f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850895772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3850895772
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.1473185777
Short name T1538
Test name
Test status
Simulation time 2086322250 ps
CPU time 4.76 seconds
Started Jul 14 06:06:08 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 216068 kb
Host smart-235afd36-5e5a-4419-a443-120e2fc8d1bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473185777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.1473185777
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.638363127
Short name T548
Test name
Test status
Simulation time 1225692476 ps
CPU time 6.51 seconds
Started Jul 14 06:06:02 PM PDT 24
Finished Jul 14 06:06:09 PM PDT 24
Peak memory 213752 kb
Host smart-3d2fee8b-0113-4bc5-ae68-dd89acbeb443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638363127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.638363127
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1613693033
Short name T1431
Test name
Test status
Simulation time 548133021 ps
CPU time 7.36 seconds
Started Jul 14 06:06:11 PM PDT 24
Finished Jul 14 06:06:19 PM PDT 24
Peak memory 205584 kb
Host smart-bfd299c2-5954-4bb6-b8f9-a07127365188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613693033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1613693033
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2408654550
Short name T557
Test name
Test status
Simulation time 21166271 ps
CPU time 0.64 seconds
Started Jul 14 06:06:21 PM PDT 24
Finished Jul 14 06:06:22 PM PDT 24
Peak memory 204724 kb
Host smart-7df3bcd7-6a01-468e-8da3-b602555bdfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408654550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2408654550
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2308530366
Short name T655
Test name
Test status
Simulation time 169162398 ps
CPU time 2.43 seconds
Started Jul 14 06:06:16 PM PDT 24
Finished Jul 14 06:06:19 PM PDT 24
Peak memory 221288 kb
Host smart-4bc9c91a-da51-41a5-afaa-0d409ecaebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308530366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2308530366
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.547027159
Short name T1464
Test name
Test status
Simulation time 744079186 ps
CPU time 18.88 seconds
Started Jul 14 06:06:08 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 282876 kb
Host smart-d376c7ff-74df-47a0-8297-f36e78078037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547027159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.547027159
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2614980952
Short name T1490
Test name
Test status
Simulation time 1864523661 ps
CPU time 54.22 seconds
Started Jul 14 06:06:16 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 371516 kb
Host smart-3d474bb8-26ae-48a6-ad4d-70ea896bfa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614980952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2614980952
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3961808143
Short name T417
Test name
Test status
Simulation time 2748443399 ps
CPU time 86.63 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:07:34 PM PDT 24
Peak memory 883904 kb
Host smart-1f7ae156-daa2-4eff-87fb-c074bf1fabea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961808143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3961808143
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.602805213
Short name T1100
Test name
Test status
Simulation time 375134629 ps
CPU time 1.08 seconds
Started Jul 14 06:06:06 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 205212 kb
Host smart-5e778427-cd22-4427-b220-a95c2844b19b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602805213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.602805213
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2133817739
Short name T727
Test name
Test status
Simulation time 760785597 ps
CPU time 11.8 seconds
Started Jul 14 06:06:08 PM PDT 24
Finished Jul 14 06:06:20 PM PDT 24
Peak memory 245020 kb
Host smart-bcf1ed7e-0f22-4ecf-bbf0-22217f0b06f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133817739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2133817739
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2841576094
Short name T967
Test name
Test status
Simulation time 42145885701 ps
CPU time 275.5 seconds
Started Jul 14 06:06:09 PM PDT 24
Finished Jul 14 06:10:46 PM PDT 24
Peak memory 1151852 kb
Host smart-f8f0bb78-2cee-48e9-b7b4-a33f83c171f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841576094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2841576094
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.371843597
Short name T1201
Test name
Test status
Simulation time 2426430817 ps
CPU time 8.45 seconds
Started Jul 14 06:06:15 PM PDT 24
Finished Jul 14 06:06:24 PM PDT 24
Peak memory 205480 kb
Host smart-901d4977-3670-4096-b7d6-1db5cb45a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371843597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.371843597
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.1185231185
Short name T1086
Test name
Test status
Simulation time 41320542 ps
CPU time 0.67 seconds
Started Jul 14 06:06:07 PM PDT 24
Finished Jul 14 06:06:08 PM PDT 24
Peak memory 205188 kb
Host smart-c34d1f6b-1f0c-48e1-ada1-7af4811101fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185231185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1185231185
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2626966141
Short name T573
Test name
Test status
Simulation time 5071464745 ps
CPU time 144.12 seconds
Started Jul 14 06:06:13 PM PDT 24
Finished Jul 14 06:08:38 PM PDT 24
Peak memory 520724 kb
Host smart-a1cb942a-65be-4bf0-8b93-c42c9344c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626966141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2626966141
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.2311183139
Short name T580
Test name
Test status
Simulation time 322254942 ps
CPU time 1.3 seconds
Started Jul 14 06:06:12 PM PDT 24
Finished Jul 14 06:06:14 PM PDT 24
Peak memory 205344 kb
Host smart-39ddd0ff-7932-4c3a-9a9b-2e551fe7fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311183139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2311183139
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1648054934
Short name T321
Test name
Test status
Simulation time 2269330546 ps
CPU time 22.75 seconds
Started Jul 14 06:06:09 PM PDT 24
Finished Jul 14 06:06:33 PM PDT 24
Peak memory 340392 kb
Host smart-abbdf858-dbfd-4bdc-b001-5599956142ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648054934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1648054934
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1740146333
Short name T1548
Test name
Test status
Simulation time 54538784541 ps
CPU time 431.39 seconds
Started Jul 14 06:06:13 PM PDT 24
Finished Jul 14 06:13:25 PM PDT 24
Peak memory 1802536 kb
Host smart-24b4814d-33f7-4cf7-bbc7-e0a08e7794b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740146333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1740146333
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1758049426
Short name T347
Test name
Test status
Simulation time 2760190642 ps
CPU time 32.36 seconds
Started Jul 14 06:06:15 PM PDT 24
Finished Jul 14 06:06:48 PM PDT 24
Peak memory 213704 kb
Host smart-7bf50fe4-93a5-4357-865a-0e039df01ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758049426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1758049426
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2685606324
Short name T263
Test name
Test status
Simulation time 969499043 ps
CPU time 6.06 seconds
Started Jul 14 06:06:15 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 220124 kb
Host smart-df277a1c-3aaa-47e8-a2f4-932b17e709a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685606324 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2685606324
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2243149826
Short name T1418
Test name
Test status
Simulation time 2743260168 ps
CPU time 1.27 seconds
Started Jul 14 06:06:12 PM PDT 24
Finished Jul 14 06:06:13 PM PDT 24
Peak memory 205660 kb
Host smart-ad2409a9-4b96-472d-86fa-b3edc1cc0865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243149826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2243149826
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.872284288
Short name T1665
Test name
Test status
Simulation time 454442853 ps
CPU time 1.76 seconds
Started Jul 14 06:06:16 PM PDT 24
Finished Jul 14 06:06:19 PM PDT 24
Peak memory 205548 kb
Host smart-dffae033-dff5-45c0-89ba-3c3af9ba3930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872284288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.872284288
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.2094099233
Short name T860
Test name
Test status
Simulation time 188576792 ps
CPU time 1.43 seconds
Started Jul 14 06:06:13 PM PDT 24
Finished Jul 14 06:06:15 PM PDT 24
Peak memory 205360 kb
Host smart-ebff0841-1b7c-4747-8d38-05f856ddd9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094099233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.2094099233
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.591483147
Short name T1160
Test name
Test status
Simulation time 1509354593 ps
CPU time 1.07 seconds
Started Jul 14 06:06:23 PM PDT 24
Finished Jul 14 06:06:25 PM PDT 24
Peak memory 205380 kb
Host smart-ddaf351f-4490-4fd6-847e-34779a208669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591483147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.591483147
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3203010720
Short name T1681
Test name
Test status
Simulation time 2773235046 ps
CPU time 1.89 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:06:16 PM PDT 24
Peak memory 213908 kb
Host smart-62281a36-1362-4188-a9c3-1d415c10d724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203010720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3203010720
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.786802345
Short name T1639
Test name
Test status
Simulation time 713629180 ps
CPU time 4.68 seconds
Started Jul 14 06:06:17 PM PDT 24
Finished Jul 14 06:06:22 PM PDT 24
Peak memory 210144 kb
Host smart-196be17a-1e53-4f49-a20f-2c624f69e376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786802345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.786802345
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2454776223
Short name T422
Test name
Test status
Simulation time 13419175207 ps
CPU time 232.49 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:10:07 PM PDT 24
Peak memory 3207152 kb
Host smart-089e3146-f0cb-441f-9905-173023181fb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454776223 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2454776223
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.4050087219
Short name T871
Test name
Test status
Simulation time 442807326 ps
CPU time 2.49 seconds
Started Jul 14 06:06:23 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 213808 kb
Host smart-d1e12c1c-a6c6-4b69-a6a4-9ccac61d22c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050087219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.4050087219
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.4166869926
Short name T1351
Test name
Test status
Simulation time 2336331403 ps
CPU time 2.65 seconds
Started Jul 14 06:06:20 PM PDT 24
Finished Jul 14 06:06:23 PM PDT 24
Peak memory 205668 kb
Host smart-f4f2b12e-6d6a-448f-83ee-f70d63260cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166869926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.4166869926
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.3022486228
Short name T867
Test name
Test status
Simulation time 1533839262 ps
CPU time 6.07 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 212528 kb
Host smart-806e4219-b009-4636-be03-c3b48e6779a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022486228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.3022486228
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.4078495792
Short name T1008
Test name
Test status
Simulation time 642241743 ps
CPU time 2.06 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:27 PM PDT 24
Peak memory 205388 kb
Host smart-2373e82a-3dcb-4a12-b654-5ceec9ea2115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078495792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.4078495792
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1355854812
Short name T1409
Test name
Test status
Simulation time 3349633523 ps
CPU time 20.07 seconds
Started Jul 14 06:06:17 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 213896 kb
Host smart-a9d2516e-ea4e-4ef4-b94d-cad313e1d1d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355854812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1355854812
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3090025541
Short name T643
Test name
Test status
Simulation time 442917449 ps
CPU time 6.56 seconds
Started Jul 14 06:06:15 PM PDT 24
Finished Jul 14 06:06:22 PM PDT 24
Peak memory 214492 kb
Host smart-d17cf299-76a7-4125-8986-11200bbfcd64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090025541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3090025541
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1762458671
Short name T982
Test name
Test status
Simulation time 28945068454 ps
CPU time 32.47 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 651504 kb
Host smart-762582c3-c289-489d-a6a9-757baa4662a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762458671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1762458671
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3516405832
Short name T500
Test name
Test status
Simulation time 4439053392 ps
CPU time 6.87 seconds
Started Jul 14 06:06:14 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 269096 kb
Host smart-0d6fc130-8f21-446d-9b81-80b7e7e85bce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516405832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3516405832
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.4106416849
Short name T671
Test name
Test status
Simulation time 2771751527 ps
CPU time 7.13 seconds
Started Jul 14 06:06:13 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 222016 kb
Host smart-c52bb3a7-e101-4f04-8725-d137396f453e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106416849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.4106416849
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.2099980049
Short name T55
Test name
Test status
Simulation time 324413085 ps
CPU time 4.5 seconds
Started Jul 14 06:06:20 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 205516 kb
Host smart-298f12df-2e21-4e77-ad9f-82defe73b190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099980049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2099980049
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.815522201
Short name T848
Test name
Test status
Simulation time 16504492 ps
CPU time 0.65 seconds
Started Jul 14 06:06:28 PM PDT 24
Finished Jul 14 06:06:30 PM PDT 24
Peak memory 204748 kb
Host smart-08b7669b-50b0-4406-b938-e57641a206e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815522201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.815522201
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1453950139
Short name T893
Test name
Test status
Simulation time 762256243 ps
CPU time 2.82 seconds
Started Jul 14 06:06:20 PM PDT 24
Finished Jul 14 06:06:24 PM PDT 24
Peak memory 213756 kb
Host smart-8c915c40-ef9b-40ea-a238-51c922c4e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453950139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1453950139
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2289803422
Short name T1149
Test name
Test status
Simulation time 1036081776 ps
CPU time 14.07 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:40 PM PDT 24
Peak memory 263244 kb
Host smart-9cf521a2-8d8d-40b9-bb8c-112b0cdeedc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289803422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2289803422
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1004430518
Short name T1631
Test name
Test status
Simulation time 51426038779 ps
CPU time 98.72 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:08:04 PM PDT 24
Peak memory 762964 kb
Host smart-a5a4dc8a-9630-4b14-8d63-7a5638331676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004430518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1004430518
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1199788956
Short name T1333
Test name
Test status
Simulation time 1811238323 ps
CPU time 115.17 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:08:15 PM PDT 24
Peak memory 565744 kb
Host smart-53bc3632-2f5f-4742-9b36-d70993a11812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199788956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1199788956
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2354953156
Short name T1387
Test name
Test status
Simulation time 374247859 ps
CPU time 0.84 seconds
Started Jul 14 06:06:21 PM PDT 24
Finished Jul 14 06:06:22 PM PDT 24
Peak memory 205156 kb
Host smart-8d3e8243-fd07-45e8-b78f-e179b25d6b49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354953156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2354953156
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1849461593
Short name T672
Test name
Test status
Simulation time 815676824 ps
CPU time 5.58 seconds
Started Jul 14 06:06:18 PM PDT 24
Finished Jul 14 06:06:24 PM PDT 24
Peak memory 246776 kb
Host smart-85db4821-c6e1-4833-afe4-65fdd8f89afe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849461593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1849461593
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1701926179
Short name T858
Test name
Test status
Simulation time 5748906192 ps
CPU time 164.87 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 759316 kb
Host smart-f5bcc4e3-9a3f-4a06-a6b2-13a4c717562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701926179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1701926179
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3012496961
Short name T237
Test name
Test status
Simulation time 1468814656 ps
CPU time 4.69 seconds
Started Jul 14 06:06:28 PM PDT 24
Finished Jul 14 06:06:33 PM PDT 24
Peak memory 205460 kb
Host smart-52f6b182-ef48-43ca-8ccd-4e03ad9a75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012496961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3012496961
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.1919983635
Short name T1439
Test name
Test status
Simulation time 81911515 ps
CPU time 0.64 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:06:20 PM PDT 24
Peak memory 205184 kb
Host smart-b6c2da9b-b799-4b2e-ad54-9ff0a29efd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919983635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1919983635
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3786519515
Short name T392
Test name
Test status
Simulation time 13082172498 ps
CPU time 85.43 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:07:50 PM PDT 24
Peak memory 205568 kb
Host smart-1dde5245-8149-4829-b596-aae91ffc8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786519515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3786519515
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.4109263582
Short name T1079
Test name
Test status
Simulation time 762628033 ps
CPU time 16.6 seconds
Started Jul 14 06:06:22 PM PDT 24
Finished Jul 14 06:06:39 PM PDT 24
Peak memory 253412 kb
Host smart-7c797b9a-4c46-41fa-acbd-9add7ab8af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109263582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.4109263582
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.4236963589
Short name T1469
Test name
Test status
Simulation time 1876527357 ps
CPU time 36.66 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:06:56 PM PDT 24
Peak memory 361832 kb
Host smart-7746fe12-fdd7-4ce0-8630-2b94f4ec474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236963589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.4236963589
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.605729144
Short name T1020
Test name
Test status
Simulation time 882168512 ps
CPU time 10.71 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 216436 kb
Host smart-fb24ad80-4221-4984-ae5a-7f11dc402999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605729144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.605729144
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1673687412
Short name T1421
Test name
Test status
Simulation time 1771704874 ps
CPU time 6.16 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:30 PM PDT 24
Peak memory 221472 kb
Host smart-ab3cad44-cc1a-4a6c-9142-040ad5a69b57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673687412 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1673687412
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1185381784
Short name T891
Test name
Test status
Simulation time 288909504 ps
CPU time 1.07 seconds
Started Jul 14 06:06:27 PM PDT 24
Finished Jul 14 06:06:29 PM PDT 24
Peak memory 205468 kb
Host smart-fe9e9574-5f30-46e7-949c-a273f62ad972
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185381784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1185381784
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.373942066
Short name T585
Test name
Test status
Simulation time 148102957 ps
CPU time 0.97 seconds
Started Jul 14 06:06:22 PM PDT 24
Finished Jul 14 06:06:24 PM PDT 24
Peak memory 205424 kb
Host smart-23a55189-5baa-47ee-b79b-446d689fa807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373942066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.373942066
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3333439958
Short name T1537
Test name
Test status
Simulation time 362360692 ps
CPU time 2.24 seconds
Started Jul 14 06:06:26 PM PDT 24
Finished Jul 14 06:06:29 PM PDT 24
Peak memory 205520 kb
Host smart-e7a951cc-c044-41e7-8779-2c702af3e2f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333439958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3333439958
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.860769676
Short name T1185
Test name
Test status
Simulation time 407356365 ps
CPU time 1.1 seconds
Started Jul 14 06:06:26 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 205456 kb
Host smart-155f4eca-a888-4b6e-8db7-247481172400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860769676 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.860769676
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2450574582
Short name T1687
Test name
Test status
Simulation time 299013705 ps
CPU time 2.33 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 221896 kb
Host smart-4ccea87b-f1a7-4384-a382-49fba80502d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450574582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2450574582
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.979711532
Short name T547
Test name
Test status
Simulation time 3580370540 ps
CPU time 5.54 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:30 PM PDT 24
Peak memory 222016 kb
Host smart-8f53a113-bdaa-40d8-991c-2e56096f09cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979711532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.979711532
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3030106128
Short name T1117
Test name
Test status
Simulation time 21830099168 ps
CPU time 66.48 seconds
Started Jul 14 06:06:26 PM PDT 24
Finished Jul 14 06:07:33 PM PDT 24
Peak memory 850276 kb
Host smart-5a4f069c-b91c-4036-9a11-5b207f33b500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030106128 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3030106128
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.3158315589
Short name T63
Test name
Test status
Simulation time 2344285569 ps
CPU time 2.75 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 213808 kb
Host smart-4935d177-1617-4509-b16b-283dea893497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158315589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.3158315589
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.3433192234
Short name T1060
Test name
Test status
Simulation time 2041256694 ps
CPU time 2.63 seconds
Started Jul 14 06:06:27 PM PDT 24
Finished Jul 14 06:06:30 PM PDT 24
Peak memory 205604 kb
Host smart-21d57186-4b56-4c87-9789-67bad4551b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433192234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.3433192234
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_txstretch.1559414929
Short name T1154
Test name
Test status
Simulation time 576547503 ps
CPU time 1.43 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 222360 kb
Host smart-6bf354bb-d656-4a39-b501-6b5218340c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559414929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_nack_txstretch.1559414929
Directory /workspace/29.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_target_perf.890720095
Short name T444
Test name
Test status
Simulation time 432564689 ps
CPU time 3.19 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 213808 kb
Host smart-3de3c03b-f6fb-4a43-99f5-99e70c95117b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890720095 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_perf.890720095
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.3561238273
Short name T341
Test name
Test status
Simulation time 2027045384 ps
CPU time 2.47 seconds
Started Jul 14 06:06:26 PM PDT 24
Finished Jul 14 06:06:29 PM PDT 24
Peak memory 205356 kb
Host smart-1e0b1b5c-561a-4292-9315-e643d8e87dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561238273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.3561238273
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.893175140
Short name T660
Test name
Test status
Simulation time 11756316259 ps
CPU time 14.7 seconds
Started Jul 14 06:06:18 PM PDT 24
Finished Jul 14 06:06:33 PM PDT 24
Peak memory 213900 kb
Host smart-963a936f-3179-4a53-a1e7-5fe0d8800feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893175140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.893175140
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.1770253765
Short name T1233
Test name
Test status
Simulation time 69265873879 ps
CPU time 404.76 seconds
Started Jul 14 06:06:28 PM PDT 24
Finished Jul 14 06:13:14 PM PDT 24
Peak memory 1694644 kb
Host smart-7f470472-7e08-45ff-b0dd-7b7b9d2cf8f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770253765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.1770253765
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3368257007
Short name T355
Test name
Test status
Simulation time 1059870545 ps
CPU time 45.84 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:07:06 PM PDT 24
Peak memory 213788 kb
Host smart-f7caaf4d-a310-44e1-a720-3e002dd0c967
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368257007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3368257007
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2299290833
Short name T1406
Test name
Test status
Simulation time 52834515949 ps
CPU time 507.61 seconds
Started Jul 14 06:06:19 PM PDT 24
Finished Jul 14 06:14:48 PM PDT 24
Peak memory 4153384 kb
Host smart-ace839ff-4476-4b3d-a801-b0eae8f6604a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299290833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2299290833
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3797886610
Short name T1052
Test name
Test status
Simulation time 1361502802 ps
CPU time 7.62 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:34 PM PDT 24
Peak memory 221988 kb
Host smart-15a33528-2190-4db9-b38c-56abbd194b38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797886610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3797886610
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.2673743229
Short name T1717
Test name
Test status
Simulation time 204043039 ps
CPU time 2.88 seconds
Started Jul 14 06:06:27 PM PDT 24
Finished Jul 14 06:06:31 PM PDT 24
Peak memory 205592 kb
Host smart-1b0a1730-f782-4f12-82dd-63dda80fc7f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673743229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.2673743229
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1614280397
Short name T631
Test name
Test status
Simulation time 19279603 ps
CPU time 0.62 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:18 PM PDT 24
Peak memory 204696 kb
Host smart-978258b0-2b7e-4e99-b71b-e4bbaf8d8a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614280397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1614280397
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1443206174
Short name T17
Test name
Test status
Simulation time 651976770 ps
CPU time 4.62 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 254276 kb
Host smart-ad2824cc-ac7f-473a-ae9b-b4521bba2340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443206174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1443206174
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3619665117
Short name T1022
Test name
Test status
Simulation time 512516211 ps
CPU time 5.16 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:21 PM PDT 24
Peak memory 236280 kb
Host smart-db7b3eef-4941-4fbd-bd08-3e36d4c2fe6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619665117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3619665117
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2771327028
Short name T812
Test name
Test status
Simulation time 3716717696 ps
CPU time 93.23 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:02:47 PM PDT 24
Peak memory 560236 kb
Host smart-173d2846-b26c-4c9f-b882-c5f9d6c1d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771327028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2771327028
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1237286453
Short name T1323
Test name
Test status
Simulation time 2628430687 ps
CPU time 92.04 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:02:39 PM PDT 24
Peak memory 527228 kb
Host smart-a8a1f491-3904-4bdd-be61-5887c528a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237286453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1237286453
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1296942730
Short name T1516
Test name
Test status
Simulation time 199492959 ps
CPU time 1.16 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 205192 kb
Host smart-0985e0aa-e43b-456a-8aad-289cc125ecd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296942730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1296942730
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2002062514
Short name T1593
Test name
Test status
Simulation time 147602032 ps
CPU time 8.26 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:25 PM PDT 24
Peak memory 228760 kb
Host smart-e9562ed6-b258-4b4c-82fa-0a9aa417e75a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002062514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2002062514
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1502942736
Short name T1176
Test name
Test status
Simulation time 5521836720 ps
CPU time 351.91 seconds
Started Jul 14 06:01:06 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 1347744 kb
Host smart-571d850a-db17-440b-a7fe-6910f861cb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502942736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1502942736
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3213700293
Short name T1381
Test name
Test status
Simulation time 1530286642 ps
CPU time 11.44 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:27 PM PDT 24
Peak memory 205444 kb
Host smart-4e521b49-29cc-4654-b20e-d9b606843a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213700293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3213700293
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2468168060
Short name T12
Test name
Test status
Simulation time 81280704 ps
CPU time 1.43 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:16 PM PDT 24
Peak memory 205496 kb
Host smart-ff3b06ae-9071-4a1b-be68-830fe1c7300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468168060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2468168060
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.257739701
Short name T1357
Test name
Test status
Simulation time 33606079 ps
CPU time 0.68 seconds
Started Jul 14 06:01:07 PM PDT 24
Finished Jul 14 06:01:09 PM PDT 24
Peak memory 205240 kb
Host smart-20e9028b-c6f5-43c4-84bd-e9e4a0f83d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257739701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.257739701
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3001181078
Short name T44
Test name
Test status
Simulation time 29782537093 ps
CPU time 123.91 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:03:21 PM PDT 24
Peak memory 213768 kb
Host smart-3c1c95fc-8309-4921-b211-7a475ec54c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001181078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3001181078
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.1393623092
Short name T720
Test name
Test status
Simulation time 24368150064 ps
CPU time 303.87 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:06:21 PM PDT 24
Peak memory 205460 kb
Host smart-6ac03fdc-3f1c-45c8-ba17-2b9fbe0677ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393623092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.1393623092
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1432083718
Short name T888
Test name
Test status
Simulation time 12698670096 ps
CPU time 31.04 seconds
Started Jul 14 06:01:08 PM PDT 24
Finished Jul 14 06:01:40 PM PDT 24
Peak memory 331328 kb
Host smart-c7f652cb-7c7c-4656-ad77-521bde9884a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432083718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1432083718
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3241401520
Short name T520
Test name
Test status
Simulation time 1793969979 ps
CPU time 15.06 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:31 PM PDT 24
Peak memory 221036 kb
Host smart-885bb85d-651a-47d0-8b4a-953ac98fc7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241401520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3241401520
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.4171852260
Short name T174
Test name
Test status
Simulation time 402465349 ps
CPU time 0.86 seconds
Started Jul 14 06:01:17 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 223672 kb
Host smart-9904a91f-97b3-4a56-bef9-2342435aab0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171852260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.4171852260
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1717048459
Short name T590
Test name
Test status
Simulation time 5035617128 ps
CPU time 5.39 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:23 PM PDT 24
Peak memory 213812 kb
Host smart-f552c0b9-ca38-4a3d-842e-f87de67d9fb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717048459 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1717048459
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.549868701
Short name T952
Test name
Test status
Simulation time 360695190 ps
CPU time 1.33 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:16 PM PDT 24
Peak memory 205424 kb
Host smart-88e64713-ecb9-4e5c-af96-26a2c17c8996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549868701 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.549868701
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.446481464
Short name T877
Test name
Test status
Simulation time 268899441 ps
CPU time 1.24 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:18 PM PDT 24
Peak memory 205584 kb
Host smart-dbd824aa-a065-4e97-869b-716b1b53d533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446481464 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.446481464
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.3559271629
Short name T369
Test name
Test status
Simulation time 2321115393 ps
CPU time 2.85 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 205572 kb
Host smart-9911cc72-69af-4019-adfb-e3ecb1f0ff3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559271629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.3559271629
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.630049962
Short name T1291
Test name
Test status
Simulation time 124850768 ps
CPU time 1.22 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:18 PM PDT 24
Peak memory 205356 kb
Host smart-2bbac584-6eb2-4e14-9cdf-56daaea72b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630049962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.630049962
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3492776511
Short name T342
Test name
Test status
Simulation time 938149490 ps
CPU time 5.38 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:21 PM PDT 24
Peak memory 221952 kb
Host smart-a2d8dd8c-f20e-418d-a7a1-1d3be60f7f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492776511 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3492776511
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.4096294256
Short name T1508
Test name
Test status
Simulation time 19069635018 ps
CPU time 137.83 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:03:34 PM PDT 24
Peak memory 2304684 kb
Host smart-f488a88c-38ff-4d7f-b8ac-d12a7360cee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096294256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.4096294256
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.634698192
Short name T435
Test name
Test status
Simulation time 7479178484 ps
CPU time 2.75 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:17 PM PDT 24
Peak memory 214132 kb
Host smart-1cd45758-a5a6-4aeb-9deb-df7b19c91740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634698192 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_nack_acqfull.634698192
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.120510378
Short name T10
Test name
Test status
Simulation time 2075432985 ps
CPU time 2.75 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:20 PM PDT 24
Peak memory 205480 kb
Host smart-d9660f2b-7117-4a32-8086-2a9e08b50668
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120510378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.120510378
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_txstretch.92591162
Short name T831
Test name
Test status
Simulation time 265719488 ps
CPU time 1.39 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 222160 kb
Host smart-89fa6ec5-b5c4-49a6-9599-6ac3e0c542c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92591162 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_txstretch.92591162
Directory /workspace/3.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/3.i2c_target_perf.2329604128
Short name T805
Test name
Test status
Simulation time 963763891 ps
CPU time 4.26 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:22 PM PDT 24
Peak memory 219836 kb
Host smart-6b8e4f32-c982-496e-9329-3c0ccaafbf24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329604128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.2329604128
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.1634423417
Short name T178
Test name
Test status
Simulation time 1909253297 ps
CPU time 2.39 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:17 PM PDT 24
Peak memory 205400 kb
Host smart-40b7cd8e-233b-4b47-8191-3559c58fbf17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634423417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.1634423417
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2788064088
Short name T472
Test name
Test status
Simulation time 1510134014 ps
CPU time 7.15 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:24 PM PDT 24
Peak memory 213816 kb
Host smart-09f18f4f-d4e8-4b1e-a2a9-6c334849daf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788064088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2788064088
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1513250402
Short name T1211
Test name
Test status
Simulation time 49356943598 ps
CPU time 2066.97 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:35:45 PM PDT 24
Peak memory 7380524 kb
Host smart-187438a9-57b1-4124-b7af-a85e5df58239
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513250402 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1513250402
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3545583197
Short name T494
Test name
Test status
Simulation time 1740244049 ps
CPU time 27.78 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:01:44 PM PDT 24
Peak memory 233632 kb
Host smart-b5ba7d46-1502-4a38-a690-36829f65d287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545583197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3545583197
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3707614610
Short name T374
Test name
Test status
Simulation time 8022181831 ps
CPU time 8.98 seconds
Started Jul 14 06:01:17 PM PDT 24
Finished Jul 14 06:01:27 PM PDT 24
Peak memory 205648 kb
Host smart-719f80a4-4898-4465-8cdf-29dd292b1fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707614610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3707614610
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1409465698
Short name T1306
Test name
Test status
Simulation time 1014095099 ps
CPU time 6.53 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:22 PM PDT 24
Peak memory 218652 kb
Host smart-54b03bbe-01ad-4392-b972-d12d982a1166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409465698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1409465698
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.1887804339
Short name T1472
Test name
Test status
Simulation time 65260452 ps
CPU time 1.54 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 205480 kb
Host smart-80e57a2e-a93a-49a9-9be6-5074034036de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887804339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1887804339
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1279454192
Short name T816
Test name
Test status
Simulation time 22521337 ps
CPU time 0.64 seconds
Started Jul 14 06:06:41 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 204840 kb
Host smart-fce6bbd2-ed00-4423-82c9-8ed419b52813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279454192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1279454192
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.449959186
Short name T1013
Test name
Test status
Simulation time 549263199 ps
CPU time 4.29 seconds
Started Jul 14 06:06:30 PM PDT 24
Finished Jul 14 06:06:35 PM PDT 24
Peak memory 245960 kb
Host smart-33f66cc0-7399-41bf-8c11-f0dc735be1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449959186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.449959186
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2108047072
Short name T1018
Test name
Test status
Simulation time 1315932644 ps
CPU time 17.18 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:43 PM PDT 24
Peak memory 268828 kb
Host smart-0bd73180-2581-4d00-b862-37b7a4b536be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108047072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2108047072
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2970494730
Short name T1076
Test name
Test status
Simulation time 2478237663 ps
CPU time 86.33 seconds
Started Jul 14 06:06:33 PM PDT 24
Finished Jul 14 06:08:00 PM PDT 24
Peak memory 643544 kb
Host smart-66dd25dd-b6da-459f-99f8-d5f27ff698fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970494730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2970494730
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1964870642
Short name T576
Test name
Test status
Simulation time 10584650760 ps
CPU time 103.85 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:08:10 PM PDT 24
Peak memory 866608 kb
Host smart-3e288f00-a552-41a6-8654-d3d746ea6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964870642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1964870642
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.678647074
Short name T423
Test name
Test status
Simulation time 134425557 ps
CPU time 1.16 seconds
Started Jul 14 06:06:24 PM PDT 24
Finished Jul 14 06:06:26 PM PDT 24
Peak memory 205212 kb
Host smart-b625f8dc-fcb1-41a1-b1e5-a517356b073a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678647074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.678647074
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.213774174
Short name T696
Test name
Test status
Simulation time 129192935 ps
CPU time 6.77 seconds
Started Jul 14 06:06:35 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 223428 kb
Host smart-3a226e79-bde9-4d38-9048-1d926f65a069
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213774174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
213774174
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.4092109592
Short name T1509
Test name
Test status
Simulation time 3610680528 ps
CPU time 244.86 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:10:31 PM PDT 24
Peak memory 1046952 kb
Host smart-6c642edc-8c4a-46c5-96aa-460033eff381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092109592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.4092109592
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3697476940
Short name T493
Test name
Test status
Simulation time 153136181 ps
CPU time 1.51 seconds
Started Jul 14 06:06:40 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 216068 kb
Host smart-2e9d1e5f-d405-431b-99cf-fa9ec127969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697476940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3697476940
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.4144539637
Short name T462
Test name
Test status
Simulation time 23451561 ps
CPU time 0.66 seconds
Started Jul 14 06:06:27 PM PDT 24
Finished Jul 14 06:06:28 PM PDT 24
Peak memory 205176 kb
Host smart-ee48db37-77ce-419f-8d70-e092e39ae281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144539637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4144539637
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3592226916
Short name T1378
Test name
Test status
Simulation time 53446242396 ps
CPU time 706.12 seconds
Started Jul 14 06:06:32 PM PDT 24
Finished Jul 14 06:18:19 PM PDT 24
Peak memory 2106992 kb
Host smart-f89cee6b-1e29-47d6-bf67-85f728719983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592226916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3592226916
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.3074457938
Short name T1365
Test name
Test status
Simulation time 3015386802 ps
CPU time 2.98 seconds
Started Jul 14 06:06:34 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 205496 kb
Host smart-8ef274b7-f14a-4123-8e15-ae7911f508c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074457938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3074457938
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.20051911
Short name T1651
Test name
Test status
Simulation time 1306269408 ps
CPU time 24.47 seconds
Started Jul 14 06:06:25 PM PDT 24
Finished Jul 14 06:06:51 PM PDT 24
Peak memory 307676 kb
Host smart-877408dc-e44a-4c30-9681-433822b463ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20051911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.20051911
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2084087976
Short name T1047
Test name
Test status
Simulation time 1701916991 ps
CPU time 36.77 seconds
Started Jul 14 06:06:32 PM PDT 24
Finished Jul 14 06:07:09 PM PDT 24
Peak memory 213944 kb
Host smart-f4f5eb4a-4001-40fe-9ef6-71e5e3b2c7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084087976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2084087976
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.869117116
Short name T822
Test name
Test status
Simulation time 4467354835 ps
CPU time 5.12 seconds
Started Jul 14 06:06:33 PM PDT 24
Finished Jul 14 06:06:39 PM PDT 24
Peak memory 217876 kb
Host smart-74ee5574-ff65-426e-834a-0746d298c32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869117116 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.869117116
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2042042705
Short name T498
Test name
Test status
Simulation time 1085749575 ps
CPU time 1.21 seconds
Started Jul 14 06:06:31 PM PDT 24
Finished Jul 14 06:06:33 PM PDT 24
Peak memory 205344 kb
Host smart-8b76d0ab-6401-4e96-b3f2-f0c741744640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042042705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2042042705
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.4018378600
Short name T1517
Test name
Test status
Simulation time 245729371 ps
CPU time 1.52 seconds
Started Jul 14 06:06:34 PM PDT 24
Finished Jul 14 06:06:36 PM PDT 24
Peak memory 205560 kb
Host smart-769a4c15-ab65-48fa-be1c-8660603fc024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018378600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.4018378600
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.256315072
Short name T608
Test name
Test status
Simulation time 992156320 ps
CPU time 2.66 seconds
Started Jul 14 06:06:37 PM PDT 24
Finished Jul 14 06:06:41 PM PDT 24
Peak memory 205520 kb
Host smart-b93eeb93-15bd-4247-9361-43553bf20473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256315072 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.256315072
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.4122525366
Short name T352
Test name
Test status
Simulation time 51868791 ps
CPU time 0.8 seconds
Started Jul 14 06:06:39 PM PDT 24
Finished Jul 14 06:06:40 PM PDT 24
Peak memory 205412 kb
Host smart-690f7221-8874-4056-8bc8-065044029d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122525366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.4122525366
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1280106075
Short name T514
Test name
Test status
Simulation time 1255563818 ps
CPU time 6.97 seconds
Started Jul 14 06:06:31 PM PDT 24
Finished Jul 14 06:06:38 PM PDT 24
Peak memory 213872 kb
Host smart-4606ff34-c26e-4a0d-8fac-5eaa8b19dc39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280106075 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1280106075
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2912249584
Short name T1551
Test name
Test status
Simulation time 11296197736 ps
CPU time 10.42 seconds
Started Jul 14 06:06:29 PM PDT 24
Finished Jul 14 06:06:41 PM PDT 24
Peak memory 304856 kb
Host smart-9696ed62-790d-47c1-8386-f2643912f410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912249584 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2912249584
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.2456502716
Short name T681
Test name
Test status
Simulation time 3270024591 ps
CPU time 2.97 seconds
Started Jul 14 06:06:37 PM PDT 24
Finished Jul 14 06:06:41 PM PDT 24
Peak memory 213836 kb
Host smart-ed3fbe3d-f424-4c72-ab4f-98d69126b4a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456502716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.2456502716
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.3902494006
Short name T924
Test name
Test status
Simulation time 617463057 ps
CPU time 2.7 seconds
Started Jul 14 06:06:39 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 206740 kb
Host smart-0012fd85-9dfb-4758-8aca-ddcb270396c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902494006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.3902494006
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.475219114
Short name T1280
Test name
Test status
Simulation time 2752699489 ps
CPU time 5.23 seconds
Started Jul 14 06:06:31 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 213900 kb
Host smart-e5fbaa4e-fb0c-4451-b814-e6e6e25e3845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475219114 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.475219114
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.628303328
Short name T587
Test name
Test status
Simulation time 1628668622 ps
CPU time 2.22 seconds
Started Jul 14 06:06:39 PM PDT 24
Finished Jul 14 06:06:42 PM PDT 24
Peak memory 205352 kb
Host smart-1949762a-4741-4bfe-8f83-a1243aa9d3d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628303328 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_smbus_maxlen.628303328
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.4066139355
Short name T1300
Test name
Test status
Simulation time 1359361438 ps
CPU time 15.95 seconds
Started Jul 14 06:06:34 PM PDT 24
Finished Jul 14 06:06:50 PM PDT 24
Peak memory 213828 kb
Host smart-12f6790b-25e8-4202-ab1f-45fb35b4c0f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066139355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.4066139355
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.1392219563
Short name T742
Test name
Test status
Simulation time 61131899225 ps
CPU time 2454.43 seconds
Started Jul 14 06:06:30 PM PDT 24
Finished Jul 14 06:47:26 PM PDT 24
Peak memory 9710740 kb
Host smart-a1351df1-29cc-493d-9436-da45ae027ee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392219563 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.1392219563
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.224629273
Short name T303
Test name
Test status
Simulation time 2320203523 ps
CPU time 51.29 seconds
Started Jul 14 06:06:31 PM PDT 24
Finished Jul 14 06:07:22 PM PDT 24
Peak memory 216328 kb
Host smart-3bc7095c-e1a9-45b3-b5a7-e6f2b3363aad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224629273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.224629273
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1006535132
Short name T1608
Test name
Test status
Simulation time 25345090885 ps
CPU time 41.27 seconds
Started Jul 14 06:06:29 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 759064 kb
Host smart-39aede02-5cd5-4b4c-bebb-dfafc5b0c1b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006535132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1006535132
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1307864594
Short name T1246
Test name
Test status
Simulation time 607780333 ps
CPU time 5.2 seconds
Started Jul 14 06:06:32 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 216812 kb
Host smart-48769392-911e-4b70-aaa4-31716100ad48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307864594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1307864594
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2014527071
Short name T1164
Test name
Test status
Simulation time 13965288162 ps
CPU time 7.27 seconds
Started Jul 14 06:06:29 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 222024 kb
Host smart-e9a1c164-bc3e-4570-bbbb-561351ee997e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014527071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2014527071
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.3004281100
Short name T1427
Test name
Test status
Simulation time 237346922 ps
CPU time 3.43 seconds
Started Jul 14 06:06:35 PM PDT 24
Finished Jul 14 06:06:39 PM PDT 24
Peak memory 205520 kb
Host smart-d1d3d397-6d5a-4463-a777-12d746550560
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004281100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3004281100
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3104395536
Short name T1390
Test name
Test status
Simulation time 26919220 ps
CPU time 0.64 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:06:54 PM PDT 24
Peak memory 204760 kb
Host smart-e345a7f7-83be-4bf1-acdb-64b9d7defc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104395536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3104395536
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.4131920716
Short name T485
Test name
Test status
Simulation time 683795868 ps
CPU time 5.57 seconds
Started Jul 14 06:06:44 PM PDT 24
Finished Jul 14 06:06:50 PM PDT 24
Peak memory 279012 kb
Host smart-5782ee64-71a5-491e-921e-ef1708f4a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131920716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.4131920716
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.32318177
Short name T1083
Test name
Test status
Simulation time 1501956794 ps
CPU time 13.54 seconds
Started Jul 14 06:06:37 PM PDT 24
Finished Jul 14 06:06:51 PM PDT 24
Peak memory 257136 kb
Host smart-5f979c08-2a84-4d2e-bb16-1ec75da4c947
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty
.32318177
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2186723294
Short name T348
Test name
Test status
Simulation time 2912322882 ps
CPU time 200.83 seconds
Started Jul 14 06:06:41 PM PDT 24
Finished Jul 14 06:10:02 PM PDT 24
Peak memory 705964 kb
Host smart-b8855957-cf23-41cf-b1e1-b4b820393361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186723294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2186723294
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1268144815
Short name T1007
Test name
Test status
Simulation time 2225211427 ps
CPU time 164.43 seconds
Started Jul 14 06:06:38 PM PDT 24
Finished Jul 14 06:09:23 PM PDT 24
Peak memory 745800 kb
Host smart-db89b65c-f864-466f-8f33-2e0dbabcab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268144815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1268144815
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3096973373
Short name T231
Test name
Test status
Simulation time 596222589 ps
CPU time 1.11 seconds
Started Jul 14 06:06:38 PM PDT 24
Finished Jul 14 06:06:40 PM PDT 24
Peak memory 205156 kb
Host smart-460f61e9-d681-4abc-ad40-ed3820b064b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096973373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3096973373
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.967274388
Short name T1720
Test name
Test status
Simulation time 430828132 ps
CPU time 5.63 seconds
Started Jul 14 06:06:37 PM PDT 24
Finished Jul 14 06:06:43 PM PDT 24
Peak memory 205484 kb
Host smart-4431ab2c-baa5-4390-8397-25fd3751733b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967274388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
967274388
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2651298710
Short name T972
Test name
Test status
Simulation time 26813538598 ps
CPU time 91.59 seconds
Started Jul 14 06:06:39 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 1010392 kb
Host smart-2e0e5677-792e-4507-9a5a-b6984c2fc446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651298710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2651298710
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2778551418
Short name T1451
Test name
Test status
Simulation time 916157937 ps
CPU time 19.17 seconds
Started Jul 14 06:06:42 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 205404 kb
Host smart-21418091-c3fd-4920-9168-9ca54151b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778551418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2778551418
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2817412952
Short name T254
Test name
Test status
Simulation time 118440929 ps
CPU time 4.5 seconds
Started Jul 14 06:06:46 PM PDT 24
Finished Jul 14 06:06:52 PM PDT 24
Peak memory 205380 kb
Host smart-59a8871d-2cd1-44b7-ab65-aff016b3f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817412952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2817412952
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2092556354
Short name T959
Test name
Test status
Simulation time 28625044 ps
CPU time 0.68 seconds
Started Jul 14 06:06:37 PM PDT 24
Finished Jul 14 06:06:39 PM PDT 24
Peak memory 205168 kb
Host smart-2eb225c8-38db-4409-89b1-40c9e3245f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092556354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2092556354
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.360124746
Short name T1290
Test name
Test status
Simulation time 2544743918 ps
CPU time 36.59 seconds
Started Jul 14 06:06:39 PM PDT 24
Finished Jul 14 06:07:16 PM PDT 24
Peak memory 252744 kb
Host smart-fa25a292-c105-43db-a2fe-4edb1bd7c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360124746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.360124746
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.3215805293
Short name T801
Test name
Test status
Simulation time 140446631 ps
CPU time 2.88 seconds
Started Jul 14 06:06:43 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 228980 kb
Host smart-2b00df7f-e5f8-4bbd-9491-cdf1f202f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215805293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3215805293
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3252108670
Short name T1274
Test name
Test status
Simulation time 5807613972 ps
CPU time 74.5 seconds
Started Jul 14 06:06:38 PM PDT 24
Finished Jul 14 06:07:53 PM PDT 24
Peak memory 344328 kb
Host smart-8c455ba2-645f-4aa7-ab1b-867000d0351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252108670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3252108670
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.4183491544
Short name T453
Test name
Test status
Simulation time 2495419501 ps
CPU time 27.13 seconds
Started Jul 14 06:06:46 PM PDT 24
Finished Jul 14 06:07:13 PM PDT 24
Peak memory 213776 kb
Host smart-8ca74924-26dc-4244-a40e-521d524a8537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183491544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4183491544
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.537387034
Short name T1641
Test name
Test status
Simulation time 13725372863 ps
CPU time 5.16 seconds
Started Jul 14 06:06:43 PM PDT 24
Finished Jul 14 06:06:48 PM PDT 24
Peak memory 222032 kb
Host smart-cf8be5a5-e395-45cb-a786-2de5eab71ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537387034 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.537387034
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.4219852808
Short name T1279
Test name
Test status
Simulation time 2037849436 ps
CPU time 1.43 seconds
Started Jul 14 06:06:44 PM PDT 24
Finished Jul 14 06:06:46 PM PDT 24
Peak memory 205616 kb
Host smart-46ee705a-1a8a-437e-9e36-0a89f5f836ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219852808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.4219852808
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1435132916
Short name T958
Test name
Test status
Simulation time 802898658 ps
CPU time 1.75 seconds
Started Jul 14 06:06:44 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 205612 kb
Host smart-262aee37-36ce-4870-b2ab-3bc88c6227ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435132916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1435132916
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.422326600
Short name T669
Test name
Test status
Simulation time 712434690 ps
CPU time 1.36 seconds
Started Jul 14 06:06:42 PM PDT 24
Finished Jul 14 06:06:44 PM PDT 24
Peak memory 205408 kb
Host smart-6b8a7cc6-177b-4be5-b1e1-633290367ed8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422326600 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.422326600
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.3796025448
Short name T432
Test name
Test status
Simulation time 258956844 ps
CPU time 1.16 seconds
Started Jul 14 06:06:45 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 205252 kb
Host smart-72dc21ce-6166-4921-b8ca-324efae49602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796025448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.3796025448
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1640425745
Short name T474
Test name
Test status
Simulation time 2634556269 ps
CPU time 4.05 seconds
Started Jul 14 06:06:46 PM PDT 24
Finished Jul 14 06:06:50 PM PDT 24
Peak memory 213912 kb
Host smart-89e05a07-0cc0-4f13-a2eb-2f6ab79be0c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640425745 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1640425745
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2682438541
Short name T1031
Test name
Test status
Simulation time 28076745384 ps
CPU time 88.57 seconds
Started Jul 14 06:06:46 PM PDT 24
Finished Jul 14 06:08:15 PM PDT 24
Peak memory 1606056 kb
Host smart-ba5e5ef5-4919-4596-92e4-7760b1967361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682438541 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2682438541
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.3333304906
Short name T1407
Test name
Test status
Simulation time 552050997 ps
CPU time 2.72 seconds
Started Jul 14 06:06:46 PM PDT 24
Finished Jul 14 06:06:49 PM PDT 24
Peak memory 213720 kb
Host smart-1857e584-8ef0-4d5a-83be-1b6a1f76f0e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333304906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.3333304906
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.2686916439
Short name T1422
Test name
Test status
Simulation time 1772800311 ps
CPU time 2.7 seconds
Started Jul 14 06:06:43 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 205612 kb
Host smart-79043d30-6095-4ff5-803d-4343a7aa1747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686916439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.2686916439
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.3111963420
Short name T931
Test name
Test status
Simulation time 562502075 ps
CPU time 2.37 seconds
Started Jul 14 06:06:45 PM PDT 24
Finished Jul 14 06:06:48 PM PDT 24
Peak memory 205308 kb
Host smart-cdd1f9ff-c241-4f1c-bccd-e253209f65ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111963420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.3111963420
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.254573934
Short name T203
Test name
Test status
Simulation time 2697245196 ps
CPU time 17.81 seconds
Started Jul 14 06:06:44 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 213876 kb
Host smart-3fb8873b-cb9c-4169-b84f-56c14300b319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254573934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.254573934
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.3483336335
Short name T275
Test name
Test status
Simulation time 58207809013 ps
CPU time 190.45 seconds
Started Jul 14 06:06:45 PM PDT 24
Finished Jul 14 06:09:56 PM PDT 24
Peak memory 1186128 kb
Host smart-7e2c0ec7-86a8-4072-b991-98a9adc4d6eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483336335 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.3483336335
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.29414173
Short name T734
Test name
Test status
Simulation time 1431011452 ps
CPU time 63.81 seconds
Started Jul 14 06:06:45 PM PDT 24
Finished Jul 14 06:07:50 PM PDT 24
Peak memory 217056 kb
Host smart-9518e09a-c85c-4635-a15a-58a562d8e079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_rd.29414173
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2753964650
Short name T390
Test name
Test status
Simulation time 9273429623 ps
CPU time 3.82 seconds
Started Jul 14 06:06:43 PM PDT 24
Finished Jul 14 06:06:47 PM PDT 24
Peak memory 205656 kb
Host smart-9a1136df-fda4-4ad2-8f13-3468eea474c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753964650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2753964650
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.4033627481
Short name T464
Test name
Test status
Simulation time 2870879507 ps
CPU time 60.01 seconds
Started Jul 14 06:06:44 PM PDT 24
Finished Jul 14 06:07:45 PM PDT 24
Peak memory 504656 kb
Host smart-348d0d6f-5b46-46af-af46-0466717e42ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033627481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.4033627481
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4226035238
Short name T704
Test name
Test status
Simulation time 3918147980 ps
CPU time 7.03 seconds
Started Jul 14 06:06:43 PM PDT 24
Finished Jul 14 06:06:51 PM PDT 24
Peak memory 222080 kb
Host smart-ad42e4f6-8614-4326-b25d-6952d1cfd7d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226035238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.4226035238
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1177956858
Short name T504
Test name
Test status
Simulation time 91219393 ps
CPU time 1.71 seconds
Started Jul 14 06:06:42 PM PDT 24
Finished Jul 14 06:06:44 PM PDT 24
Peak memory 221664 kb
Host smart-9fcd7652-4ca6-49a7-a0b1-2d0d0b6bff7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177956858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1177956858
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2581601571
Short name T1462
Test name
Test status
Simulation time 26256348 ps
CPU time 0.65 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:07:00 PM PDT 24
Peak memory 204764 kb
Host smart-7ffda694-0ad3-4f7d-8cb0-990246142634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581601571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2581601571
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3437498049
Short name T916
Test name
Test status
Simulation time 200626118 ps
CPU time 1.62 seconds
Started Jul 14 06:06:54 PM PDT 24
Finished Jul 14 06:06:56 PM PDT 24
Peak memory 213744 kb
Host smart-5e388f28-ab68-44ed-b3fe-2c899fa06971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437498049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3437498049
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4015528433
Short name T1016
Test name
Test status
Simulation time 153805657 ps
CPU time 2.93 seconds
Started Jul 14 06:06:54 PM PDT 24
Finished Jul 14 06:06:58 PM PDT 24
Peak memory 233304 kb
Host smart-0cf9d175-23b9-44b5-a544-0f976aeb3ea5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015528433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4015528433
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3320302843
Short name T469
Test name
Test status
Simulation time 3097656205 ps
CPU time 119.34 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 769684 kb
Host smart-0774965d-ddb8-4f37-b132-ec7a10b56586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320302843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3320302843
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1942805440
Short name T1400
Test name
Test status
Simulation time 1541917397 ps
CPU time 98.55 seconds
Started Jul 14 06:06:51 PM PDT 24
Finished Jul 14 06:08:30 PM PDT 24
Peak memory 541196 kb
Host smart-ce24cd21-f766-4721-8559-f44e22bc48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942805440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1942805440
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2716057909
Short name T35
Test name
Test status
Simulation time 217564234 ps
CPU time 1.02 seconds
Started Jul 14 06:06:52 PM PDT 24
Finished Jul 14 06:06:54 PM PDT 24
Peak memory 205172 kb
Host smart-a2cc0879-3fb7-4707-a00b-a19424160443
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716057909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2716057909
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3502303888
Short name T865
Test name
Test status
Simulation time 1670088908 ps
CPU time 6.37 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:07:00 PM PDT 24
Peak memory 246672 kb
Host smart-e137d322-19ee-4fbd-9f82-e3bf65043c66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502303888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3502303888
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.451875227
Short name T106
Test name
Test status
Simulation time 6209605321 ps
CPU time 66.91 seconds
Started Jul 14 06:06:50 PM PDT 24
Finished Jul 14 06:07:57 PM PDT 24
Peak memory 917620 kb
Host smart-78369a88-8b02-4f68-840a-f3b10ea384f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451875227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.451875227
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3280446407
Short name T249
Test name
Test status
Simulation time 821520501 ps
CPU time 17.63 seconds
Started Jul 14 06:06:57 PM PDT 24
Finished Jul 14 06:07:16 PM PDT 24
Peak memory 205404 kb
Host smart-653785ae-1d23-4c7d-a5ad-f2ea06e1a310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280446407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3280446407
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.2767988983
Short name T701
Test name
Test status
Simulation time 49205846 ps
CPU time 0.69 seconds
Started Jul 14 06:06:58 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 205204 kb
Host smart-0fca6ecf-0de6-4b0a-9e80-10cc7b0914b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767988983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2767988983
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2311426594
Short name T414
Test name
Test status
Simulation time 2194046467 ps
CPU time 29.42 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 220324 kb
Host smart-624c2986-79dc-4c1d-a298-1e8249c18938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311426594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2311426594
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.1810875264
Short name T1397
Test name
Test status
Simulation time 606027810 ps
CPU time 7.67 seconds
Started Jul 14 06:06:50 PM PDT 24
Finished Jul 14 06:06:58 PM PDT 24
Peak memory 233960 kb
Host smart-2dd618e0-1087-47cb-bfc1-333fc74cdbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810875264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1810875264
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2621125481
Short name T1178
Test name
Test status
Simulation time 1778733760 ps
CPU time 29.99 seconds
Started Jul 14 06:06:54 PM PDT 24
Finished Jul 14 06:07:25 PM PDT 24
Peak memory 325480 kb
Host smart-90d2bea9-1f3e-485e-929a-83fe80792da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621125481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2621125481
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1828682220
Short name T306
Test name
Test status
Simulation time 1667095030 ps
CPU time 13.74 seconds
Started Jul 14 06:06:50 PM PDT 24
Finished Jul 14 06:07:05 PM PDT 24
Peak memory 229320 kb
Host smart-c54ac43c-aa8c-4270-93f4-a24d394464e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828682220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1828682220
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2102908566
Short name T961
Test name
Test status
Simulation time 6856145498 ps
CPU time 7.34 seconds
Started Jul 14 06:07:00 PM PDT 24
Finished Jul 14 06:07:08 PM PDT 24
Peak memory 216000 kb
Host smart-a06fa310-7315-4edf-bdb4-10a2f18b9972
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102908566 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2102908566
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1722283836
Short name T228
Test name
Test status
Simulation time 156420087 ps
CPU time 1.1 seconds
Started Jul 14 06:06:50 PM PDT 24
Finished Jul 14 06:06:52 PM PDT 24
Peak memory 205412 kb
Host smart-d055d121-29b6-429f-9e82-c90969382f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722283836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1722283836
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.698954196
Short name T1214
Test name
Test status
Simulation time 564032919 ps
CPU time 1.47 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:06:55 PM PDT 24
Peak memory 213788 kb
Host smart-ceb951f2-42eb-496f-a514-f4d607da924c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698954196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.698954196
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1480333200
Short name T1436
Test name
Test status
Simulation time 1955957664 ps
CPU time 2.59 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:07:03 PM PDT 24
Peak memory 205612 kb
Host smart-56a675b1-4c07-4f5f-be68-e1e4d6b888c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480333200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1480333200
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.2072951634
Short name T1268
Test name
Test status
Simulation time 1100602059 ps
CPU time 1.26 seconds
Started Jul 14 06:06:58 PM PDT 24
Finished Jul 14 06:07:00 PM PDT 24
Peak memory 205344 kb
Host smart-978bf3e8-2269-42be-8d64-2ab2c0068b9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072951634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.2072951634
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3383497068
Short name T377
Test name
Test status
Simulation time 2513229503 ps
CPU time 7.15 seconds
Started Jul 14 06:06:50 PM PDT 24
Finished Jul 14 06:06:57 PM PDT 24
Peak memory 221924 kb
Host smart-420bdbd2-baba-4d49-b398-50e6d3c2ceeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383497068 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3383497068
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3198308100
Short name T1095
Test name
Test status
Simulation time 12597378195 ps
CPU time 112.53 seconds
Started Jul 14 06:06:52 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 1916076 kb
Host smart-fa3610c8-f062-41dd-bb3f-06631fa1369e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198308100 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3198308100
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.295035181
Short name T864
Test name
Test status
Simulation time 1096393820 ps
CPU time 2.92 seconds
Started Jul 14 06:06:56 PM PDT 24
Finished Jul 14 06:07:00 PM PDT 24
Peak memory 213844 kb
Host smart-c01fb9f4-f159-4df5-956f-6e488bc2f03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295035181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_nack_acqfull.295035181
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.3207379108
Short name T1662
Test name
Test status
Simulation time 426034306 ps
CPU time 2.54 seconds
Started Jul 14 06:06:58 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 205572 kb
Host smart-468ccdec-2ee9-4842-b21a-6d15bc364e70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207379108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.3207379108
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_txstretch.3735701236
Short name T1012
Test name
Test status
Simulation time 539001789 ps
CPU time 1.52 seconds
Started Jul 14 06:06:57 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 222396 kb
Host smart-5ac8dc3b-5bf7-4133-a0a4-f96354213c23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735701236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_nack_txstretch.3735701236
Directory /workspace/32.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_target_perf.3901174361
Short name T561
Test name
Test status
Simulation time 1499307087 ps
CPU time 4.05 seconds
Started Jul 14 06:07:09 PM PDT 24
Finished Jul 14 06:07:14 PM PDT 24
Peak memory 213732 kb
Host smart-262e85a0-1db4-43d1-bffd-f00db58d7771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901174361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.3901174361
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.2983565746
Short name T259
Test name
Test status
Simulation time 1639374557 ps
CPU time 1.99 seconds
Started Jul 14 06:07:00 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 205404 kb
Host smart-dfcf4b3d-ca14-4f6c-96fb-367b33cdb1df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983565746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.2983565746
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3492758130
Short name T1706
Test name
Test status
Simulation time 698750144 ps
CPU time 8.29 seconds
Started Jul 14 06:06:54 PM PDT 24
Finished Jul 14 06:07:03 PM PDT 24
Peak memory 213756 kb
Host smart-859f7953-5466-408b-811f-0ceee2e868cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492758130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3492758130
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.3538192517
Short name T769
Test name
Test status
Simulation time 63319293991 ps
CPU time 70.9 seconds
Started Jul 14 06:06:56 PM PDT 24
Finished Jul 14 06:08:07 PM PDT 24
Peak memory 300856 kb
Host smart-473350bf-efcc-4823-a5be-944b222962c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538192517 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.3538192517
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.4126716212
Short name T1424
Test name
Test status
Simulation time 1094061847 ps
CPU time 24.62 seconds
Started Jul 14 06:06:51 PM PDT 24
Finished Jul 14 06:07:16 PM PDT 24
Peak memory 213824 kb
Host smart-aa3b99d9-662a-4292-a921-73d57925b1a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126716212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.4126716212
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.37559358
Short name T779
Test name
Test status
Simulation time 11604850148 ps
CPU time 24.36 seconds
Started Jul 14 06:06:49 PM PDT 24
Finished Jul 14 06:07:14 PM PDT 24
Peak memory 205692 kb
Host smart-1752615b-a9f9-4424-ab71-4a633461632d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stress_wr.37559358
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.235412503
Short name T921
Test name
Test status
Simulation time 1638184531 ps
CPU time 8.7 seconds
Started Jul 14 06:06:53 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 305004 kb
Host smart-495a29a6-8a8b-4eb0-8a4b-b3f3565341b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235412503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.235412503
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1141168720
Short name T1205
Test name
Test status
Simulation time 8217671778 ps
CPU time 7.34 seconds
Started Jul 14 06:06:51 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 222024 kb
Host smart-8b53e90b-58b8-433b-988c-d410bbad95e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141168720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1141168720
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.1633876693
Short name T451
Test name
Test status
Simulation time 119398324 ps
CPU time 2.62 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 205580 kb
Host smart-8456f29b-4db7-4f1f-8c54-29e89266c1f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633876693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1633876693
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.491585050
Short name T1678
Test name
Test status
Simulation time 23455311 ps
CPU time 0.6 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:07:02 PM PDT 24
Peak memory 204496 kb
Host smart-6ae44fe9-9b06-4f9d-88f1-3da08c3ed73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491585050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.491585050
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3836490326
Short name T88
Test name
Test status
Simulation time 1620787268 ps
CPU time 6.75 seconds
Started Jul 14 06:07:00 PM PDT 24
Finished Jul 14 06:07:08 PM PDT 24
Peak memory 242456 kb
Host smart-51d2e27d-8a9b-402e-8f91-da3b42f609f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836490326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3836490326
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2644293623
Short name T836
Test name
Test status
Simulation time 1188895960 ps
CPU time 16.24 seconds
Started Jul 14 06:07:06 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 268068 kb
Host smart-071429f5-5061-4cd5-9ab3-9fd2f7937eab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644293623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2644293623
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2306434184
Short name T81
Test name
Test status
Simulation time 7514056522 ps
CPU time 45.01 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:07:47 PM PDT 24
Peak memory 462904 kb
Host smart-d541deed-83cc-498a-9a64-b056a4432eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306434184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2306434184
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.134163959
Short name T706
Test name
Test status
Simulation time 4807938803 ps
CPU time 81.98 seconds
Started Jul 14 06:06:55 PM PDT 24
Finished Jul 14 06:08:17 PM PDT 24
Peak memory 805868 kb
Host smart-0d5084aa-b87e-4aeb-aff7-a40262358446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134163959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.134163959
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.163799189
Short name T1103
Test name
Test status
Simulation time 82541248 ps
CPU time 1 seconds
Started Jul 14 06:06:57 PM PDT 24
Finished Jul 14 06:06:58 PM PDT 24
Peak memory 205212 kb
Host smart-19691bb8-7dbc-468f-816f-237f1dd68b3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163799189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.163799189
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1952131480
Short name T881
Test name
Test status
Simulation time 282670314 ps
CPU time 3.48 seconds
Started Jul 14 06:06:57 PM PDT 24
Finished Jul 14 06:07:01 PM PDT 24
Peak memory 205464 kb
Host smart-8a403f44-4704-439f-82c9-a326c686b3b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952131480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1952131480
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3864604161
Short name T919
Test name
Test status
Simulation time 19529440566 ps
CPU time 358.94 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:13:00 PM PDT 24
Peak memory 1397556 kb
Host smart-fd5d2d61-9b96-4e35-afbc-927198e5d468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864604161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3864604161
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2596327385
Short name T995
Test name
Test status
Simulation time 884860325 ps
CPU time 4.49 seconds
Started Jul 14 06:07:04 PM PDT 24
Finished Jul 14 06:07:09 PM PDT 24
Peak memory 205404 kb
Host smart-e4f479b1-5b06-429d-99d8-5ada1198d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596327385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2596327385
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.3984602405
Short name T895
Test name
Test status
Simulation time 49039844 ps
CPU time 0.71 seconds
Started Jul 14 06:06:58 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 205204 kb
Host smart-5b8c56b1-2a2b-4828-987d-1a0e335e5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984602405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3984602405
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2128153289
Short name T627
Test name
Test status
Simulation time 26552359279 ps
CPU time 122.84 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 205436 kb
Host smart-309f4066-4935-4f90-a79b-6f4fb209fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128153289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2128153289
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.494984212
Short name T1438
Test name
Test status
Simulation time 5963041892 ps
CPU time 17.28 seconds
Started Jul 14 06:06:58 PM PDT 24
Finished Jul 14 06:07:16 PM PDT 24
Peak memory 213600 kb
Host smart-31a86107-8956-44c7-983a-e532e0bb3a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494984212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.494984212
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.268097796
Short name T794
Test name
Test status
Simulation time 7601938160 ps
CPU time 30.45 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:07:30 PM PDT 24
Peak memory 359960 kb
Host smart-2d1f7b6e-823b-48e2-9384-7f99c5beea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268097796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.268097796
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.4098283754
Short name T1126
Test name
Test status
Simulation time 64486664644 ps
CPU time 808.61 seconds
Started Jul 14 06:06:56 PM PDT 24
Finished Jul 14 06:20:26 PM PDT 24
Peak memory 3077948 kb
Host smart-47eff261-6610-4164-af43-f83e83fde339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098283754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.4098283754
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2610749513
Short name T305
Test name
Test status
Simulation time 2504926931 ps
CPU time 25.04 seconds
Started Jul 14 06:06:56 PM PDT 24
Finished Jul 14 06:07:22 PM PDT 24
Peak memory 213712 kb
Host smart-ff9508d5-8cf6-4d44-8fd0-b30294720d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610749513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2610749513
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2552003635
Short name T126
Test name
Test status
Simulation time 1218360347 ps
CPU time 3.94 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:07:06 PM PDT 24
Peak memory 213796 kb
Host smart-2f3fd2a5-78ec-4ee3-ac80-740f480a4742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552003635 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2552003635
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.4232133758
Short name T1630
Test name
Test status
Simulation time 173031056 ps
CPU time 1.2 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:04 PM PDT 24
Peak memory 205348 kb
Host smart-84d3acfc-dab6-456d-b3e9-0fe1e70187c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232133758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.4232133758
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3050408107
Short name T394
Test name
Test status
Simulation time 185290564 ps
CPU time 1.21 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:04 PM PDT 24
Peak memory 205444 kb
Host smart-a6dceb6e-a96e-4a94-9c1f-f944ceaf0d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050408107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3050408107
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3782144675
Short name T851
Test name
Test status
Simulation time 502247301 ps
CPU time 2.46 seconds
Started Jul 14 06:07:07 PM PDT 24
Finished Jul 14 06:07:10 PM PDT 24
Peak memory 205560 kb
Host smart-da4bd131-e2a9-4452-a4d3-f94907176084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782144675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3782144675
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2793623471
Short name T350
Test name
Test status
Simulation time 146304030 ps
CPU time 0.83 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:04 PM PDT 24
Peak memory 205464 kb
Host smart-73e13e4e-f114-49d1-a4cc-e05d74095de2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793623471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2793623471
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.231366427
Short name T137
Test name
Test status
Simulation time 297506186 ps
CPU time 2.09 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:05 PM PDT 24
Peak memory 213784 kb
Host smart-c28589e7-d5c4-41f4-ac1c-f26fa6ef2ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231366427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.231366427
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3927696718
Short name T276
Test name
Test status
Simulation time 773734945 ps
CPU time 5.31 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:07:07 PM PDT 24
Peak memory 219312 kb
Host smart-56724f67-d90a-41b3-af08-389c8729cce0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927696718 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3927696718
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3988094042
Short name T784
Test name
Test status
Simulation time 9216091909 ps
CPU time 4.25 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:07 PM PDT 24
Peak memory 205732 kb
Host smart-4d161e11-08c7-4727-bbf5-b0bb1afb28c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988094042 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3988094042
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2905947049
Short name T827
Test name
Test status
Simulation time 2028325652 ps
CPU time 2.78 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:06 PM PDT 24
Peak memory 213816 kb
Host smart-d357240b-6cc1-424e-a48a-7dee01d07947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905947049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2905947049
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.3953374890
Short name T677
Test name
Test status
Simulation time 466862339 ps
CPU time 2.71 seconds
Started Jul 14 06:07:05 PM PDT 24
Finished Jul 14 06:07:08 PM PDT 24
Peak memory 205520 kb
Host smart-2551ae86-e36b-4090-b3f5-19f03e9cbc19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953374890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.3953374890
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3270888970
Short name T659
Test name
Test status
Simulation time 2530002264 ps
CPU time 5.01 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:08 PM PDT 24
Peak memory 216036 kb
Host smart-dd96a901-48a8-4743-9ff7-27733ee24886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270888970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3270888970
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.926252326
Short name T605
Test name
Test status
Simulation time 928399751 ps
CPU time 2.62 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:06 PM PDT 24
Peak memory 205376 kb
Host smart-ec9aa84e-bf13-4947-8dd9-1360e355d058
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926252326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_smbus_maxlen.926252326
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.756677627
Short name T1003
Test name
Test status
Simulation time 3692196389 ps
CPU time 10.75 seconds
Started Jul 14 06:07:01 PM PDT 24
Finished Jul 14 06:07:12 PM PDT 24
Peak memory 213448 kb
Host smart-3b0cad9e-1ba6-4e1e-ab08-c735b6d18cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756677627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.756677627
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.1503546639
Short name T1486
Test name
Test status
Simulation time 25012998241 ps
CPU time 792.96 seconds
Started Jul 14 06:07:06 PM PDT 24
Finished Jul 14 06:20:19 PM PDT 24
Peak memory 5042232 kb
Host smart-967b1416-cea8-44ab-af64-ab0714621450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503546639 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.1503546639
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3770645727
Short name T1434
Test name
Test status
Simulation time 5465587776 ps
CPU time 28.32 seconds
Started Jul 14 06:07:02 PM PDT 24
Finished Jul 14 06:07:31 PM PDT 24
Peak memory 232988 kb
Host smart-377c0266-478e-450e-b1a8-3522187edc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770645727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3770645727
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2442078780
Short name T791
Test name
Test status
Simulation time 25879239915 ps
CPU time 46.84 seconds
Started Jul 14 06:06:59 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 782404 kb
Host smart-6b678214-fb2c-4741-9563-b5b28d7fea63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442078780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2442078780
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1435524249
Short name T302
Test name
Test status
Simulation time 9827652746 ps
CPU time 6.2 seconds
Started Jul 14 06:07:04 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 222084 kb
Host smart-902fda0e-9260-4317-9e61-6fffe8cfe044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435524249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1435524249
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.3701711238
Short name T311
Test name
Test status
Simulation time 55685047 ps
CPU time 1.38 seconds
Started Jul 14 06:07:04 PM PDT 24
Finished Jul 14 06:07:06 PM PDT 24
Peak memory 205484 kb
Host smart-cd2e828a-07b4-46e3-836f-8f5bd1f0a425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701711238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3701711238
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2145243023
Short name T1311
Test name
Test status
Simulation time 142440054 ps
CPU time 0.63 seconds
Started Jul 14 06:07:17 PM PDT 24
Finished Jul 14 06:07:18 PM PDT 24
Peak memory 204764 kb
Host smart-60a2ce04-454a-499b-baed-a63287e6748f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145243023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2145243023
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3760076031
Short name T1353
Test name
Test status
Simulation time 96714128 ps
CPU time 2.01 seconds
Started Jul 14 06:07:12 PM PDT 24
Finished Jul 14 06:07:14 PM PDT 24
Peak memory 214812 kb
Host smart-8ab162c7-0649-4750-a2ca-9ee1c745f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760076031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3760076031
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.419040068
Short name T814
Test name
Test status
Simulation time 566181662 ps
CPU time 12.36 seconds
Started Jul 14 06:07:09 PM PDT 24
Finished Jul 14 06:07:22 PM PDT 24
Peak memory 327400 kb
Host smart-dafbbed4-ccd0-4add-87cf-00691d5795c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419040068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.419040068
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1114716753
Short name T25
Test name
Test status
Simulation time 12187146206 ps
CPU time 88.48 seconds
Started Jul 14 06:07:09 PM PDT 24
Finished Jul 14 06:08:38 PM PDT 24
Peak memory 514316 kb
Host smart-a4a66bd1-611b-4462-9a65-94a6ce8efdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114716753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1114716753
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2493057814
Short name T92
Test name
Test status
Simulation time 1966280881 ps
CPU time 58.84 seconds
Started Jul 14 06:07:10 PM PDT 24
Finished Jul 14 06:08:09 PM PDT 24
Peak memory 688584 kb
Host smart-a213cfce-cfe8-4055-866f-4b47ebe5491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493057814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2493057814
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3173869156
Short name T1120
Test name
Test status
Simulation time 99627058 ps
CPU time 1.05 seconds
Started Jul 14 06:07:14 PM PDT 24
Finished Jul 14 06:07:15 PM PDT 24
Peak memory 205136 kb
Host smart-ff87f64b-775d-4ff6-a2e2-611919b56002
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173869156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3173869156
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2449662451
Short name T468
Test name
Test status
Simulation time 206942312 ps
CPU time 2.89 seconds
Started Jul 14 06:07:11 PM PDT 24
Finished Jul 14 06:07:15 PM PDT 24
Peak memory 220116 kb
Host smart-1d950590-8b13-4867-8735-eb0ae7a92923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449662451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2449662451
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2203620060
Short name T1308
Test name
Test status
Simulation time 8019271761 ps
CPU time 115.73 seconds
Started Jul 14 06:07:08 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 1155204 kb
Host smart-a68d21e0-ebd5-401e-a698-ba4999854877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203620060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2203620060
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.998421677
Short name T238
Test name
Test status
Simulation time 1142036605 ps
CPU time 5.03 seconds
Started Jul 14 06:07:17 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 205404 kb
Host smart-f27d0458-85fd-474e-b137-cd6e5d1f3f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998421677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.998421677
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.245944716
Short name T1494
Test name
Test status
Simulation time 16895228 ps
CPU time 0.69 seconds
Started Jul 14 06:07:08 PM PDT 24
Finished Jul 14 06:07:09 PM PDT 24
Peak memory 205240 kb
Host smart-5ff42bae-50af-446d-a276-2e978203f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245944716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.245944716
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.633423986
Short name T1403
Test name
Test status
Simulation time 326520491 ps
CPU time 2.54 seconds
Started Jul 14 06:07:09 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 205920 kb
Host smart-c8feff98-ead8-4535-b130-d42a1e0283cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633423986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.633423986
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.2057112564
Short name T80
Test name
Test status
Simulation time 2689450628 ps
CPU time 19.2 seconds
Started Jul 14 06:07:08 PM PDT 24
Finished Jul 14 06:07:28 PM PDT 24
Peak memory 205828 kb
Host smart-bb6c6dc0-933c-4d29-8fd5-1567296fc816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057112564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.2057112564
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2579230741
Short name T1252
Test name
Test status
Simulation time 4413823355 ps
CPU time 40.21 seconds
Started Jul 14 06:07:05 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 408928 kb
Host smart-837e0062-aea7-43cd-a193-143aeef90432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579230741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2579230741
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2663818067
Short name T389
Test name
Test status
Simulation time 781951917 ps
CPU time 35.15 seconds
Started Jul 14 06:07:10 PM PDT 24
Finished Jul 14 06:07:45 PM PDT 24
Peak memory 213716 kb
Host smart-95b7399c-449c-42f2-86c5-b2aaed143a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663818067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2663818067
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2880777329
Short name T1230
Test name
Test status
Simulation time 631342170 ps
CPU time 3.3 seconds
Started Jul 14 06:07:18 PM PDT 24
Finished Jul 14 06:07:21 PM PDT 24
Peak memory 213952 kb
Host smart-53d37bfe-8d95-4788-9f3b-af196dfd1a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880777329 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2880777329
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1015810772
Short name T1169
Test name
Test status
Simulation time 442637387 ps
CPU time 0.84 seconds
Started Jul 14 06:07:10 PM PDT 24
Finished Jul 14 06:07:11 PM PDT 24
Peak memory 213668 kb
Host smart-5ea3066f-1abd-4524-ba11-cc676dc3cbc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015810772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1015810772
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2967251565
Short name T1458
Test name
Test status
Simulation time 208381142 ps
CPU time 1.57 seconds
Started Jul 14 06:07:21 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 205588 kb
Host smart-55d642a9-0d2a-412b-ae26-031e2578178a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967251565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2967251565
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3681259619
Short name T1560
Test name
Test status
Simulation time 192466011 ps
CPU time 1.4 seconds
Started Jul 14 06:07:15 PM PDT 24
Finished Jul 14 06:07:17 PM PDT 24
Peak memory 205384 kb
Host smart-cd691054-4a05-4c84-ab09-95600634a77c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681259619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3681259619
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.824144144
Short name T1143
Test name
Test status
Simulation time 125737501 ps
CPU time 1.14 seconds
Started Jul 14 06:07:14 PM PDT 24
Finished Jul 14 06:07:15 PM PDT 24
Peak memory 205384 kb
Host smart-6d02bca9-02f9-4a07-8b49-de7b758ed4cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824144144 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.824144144
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1385534283
Short name T1635
Test name
Test status
Simulation time 914410411 ps
CPU time 5.4 seconds
Started Jul 14 06:07:11 PM PDT 24
Finished Jul 14 06:07:17 PM PDT 24
Peak memory 220140 kb
Host smart-e5d0945d-3e1d-487a-bbb5-702c6ca22f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385534283 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1385534283
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.4218686995
Short name T529
Test name
Test status
Simulation time 21606325817 ps
CPU time 557.59 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:16:35 PM PDT 24
Peak memory 5095992 kb
Host smart-35d4baf1-0125-4dc3-80ee-d450a91b2b61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218686995 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.4218686995
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.2568925165
Short name T454
Test name
Test status
Simulation time 522234163 ps
CPU time 2.83 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:07:19 PM PDT 24
Peak memory 213816 kb
Host smart-7f469b31-429f-47a0-bf99-6ed6a8abe908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568925165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.2568925165
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.428269559
Short name T140
Test name
Test status
Simulation time 456170468 ps
CPU time 2.48 seconds
Started Jul 14 06:07:23 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 205588 kb
Host smart-b00d118e-93cf-40f9-8587-348271157966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428269559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.428269559
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.1555213392
Short name T67
Test name
Test status
Simulation time 4237904465 ps
CPU time 4.79 seconds
Started Jul 14 06:07:17 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 220196 kb
Host smart-955134e9-a281-44ce-8eaa-1478b57a3a75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555213392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.1555213392
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.2011323462
Short name T1654
Test name
Test status
Simulation time 1625882545 ps
CPU time 2.2 seconds
Started Jul 14 06:07:21 PM PDT 24
Finished Jul 14 06:07:23 PM PDT 24
Peak memory 205400 kb
Host smart-f42eb787-93e7-4111-b72a-3e7bb5394ecd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011323462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.2011323462
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3365059710
Short name T418
Test name
Test status
Simulation time 7201300104 ps
CPU time 32.99 seconds
Started Jul 14 06:07:10 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 213864 kb
Host smart-3d32fd3a-a49f-4fe1-9b7f-2d6e726fe17b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365059710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3365059710
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.1417915695
Short name T1109
Test name
Test status
Simulation time 21087291279 ps
CPU time 29.12 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 254800 kb
Host smart-f9f9161a-e777-4ad5-aa15-2a273778c308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417915695 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.1417915695
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3455790446
Short name T1612
Test name
Test status
Simulation time 2251907688 ps
CPU time 24.17 seconds
Started Jul 14 06:07:14 PM PDT 24
Finished Jul 14 06:07:39 PM PDT 24
Peak memory 213912 kb
Host smart-1870efce-9f2b-4a54-8074-d68f1a125d1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455790446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3455790446
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2241555721
Short name T385
Test name
Test status
Simulation time 50188964061 ps
CPU time 1672.56 seconds
Started Jul 14 06:07:12 PM PDT 24
Finished Jul 14 06:35:05 PM PDT 24
Peak memory 7825536 kb
Host smart-2e95555f-1641-48cc-be5e-c5f2c10a6e12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241555721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2241555721
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.2374362147
Short name T667
Test name
Test status
Simulation time 3743946996 ps
CPU time 7.78 seconds
Started Jul 14 06:07:12 PM PDT 24
Finished Jul 14 06:07:20 PM PDT 24
Peak memory 295884 kb
Host smart-1a1301f5-1963-49f9-ae0c-16fc6e8aedcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374362147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.2374362147
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.4187516093
Short name T1196
Test name
Test status
Simulation time 1322052793 ps
CPU time 6.66 seconds
Started Jul 14 06:07:14 PM PDT 24
Finished Jul 14 06:07:21 PM PDT 24
Peak memory 221836 kb
Host smart-f3569d69-845d-4810-8a05-b5600665a3c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187516093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.4187516093
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.2461383099
Short name T428
Test name
Test status
Simulation time 286276678 ps
CPU time 5.08 seconds
Started Jul 14 06:07:15 PM PDT 24
Finished Jul 14 06:07:20 PM PDT 24
Peak memory 206824 kb
Host smart-30c72654-a3c3-4bfb-b5b7-ac5f6a5197bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461383099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.2461383099
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1050355168
Short name T1599
Test name
Test status
Simulation time 18561338 ps
CPU time 0.72 seconds
Started Jul 14 06:07:27 PM PDT 24
Finished Jul 14 06:07:28 PM PDT 24
Peak memory 204656 kb
Host smart-dcb68597-33a4-4420-86df-0695e4600119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050355168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1050355168
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1279168272
Short name T1579
Test name
Test status
Simulation time 569691060 ps
CPU time 1.36 seconds
Started Jul 14 06:07:14 PM PDT 24
Finished Jul 14 06:07:16 PM PDT 24
Peak memory 213716 kb
Host smart-77a2e094-89a0-4787-a1ce-c4c32f270a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279168272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1279168272
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.235986851
Short name T1348
Test name
Test status
Simulation time 981936434 ps
CPU time 8.66 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 284144 kb
Host smart-04b6b777-e396-44cc-9240-01708b23ea6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235986851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.235986851
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3639567895
Short name T1328
Test name
Test status
Simulation time 13093428671 ps
CPU time 151.53 seconds
Started Jul 14 06:07:21 PM PDT 24
Finished Jul 14 06:09:53 PM PDT 24
Peak memory 400280 kb
Host smart-ba591004-5e59-443e-857c-cd247a23ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639567895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3639567895
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2443055966
Short name T948
Test name
Test status
Simulation time 11625638277 ps
CPU time 124.27 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:09:21 PM PDT 24
Peak memory 640080 kb
Host smart-c740839c-4416-49e5-8f8c-d783514b3d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443055966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2443055966
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4010833192
Short name T721
Test name
Test status
Simulation time 376591904 ps
CPU time 1.1 seconds
Started Jul 14 06:07:18 PM PDT 24
Finished Jul 14 06:07:20 PM PDT 24
Peak memory 205168 kb
Host smart-a9b45404-739f-407b-841f-1408466cbef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010833192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4010833192
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1595748338
Short name T717
Test name
Test status
Simulation time 3346850797 ps
CPU time 6.38 seconds
Started Jul 14 06:07:15 PM PDT 24
Finished Jul 14 06:07:22 PM PDT 24
Peak memory 253100 kb
Host smart-9e1d9751-b5b9-41c2-8eab-b3224deebac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595748338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1595748338
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2218950336
Short name T32
Test name
Test status
Simulation time 15826578381 ps
CPU time 118.58 seconds
Started Jul 14 06:07:21 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 1262640 kb
Host smart-ef5e6058-085e-4aab-8dbb-80ef23b4833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218950336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2218950336
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.879432322
Short name T955
Test name
Test status
Simulation time 350605290 ps
CPU time 14.94 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:40 PM PDT 24
Peak memory 205468 kb
Host smart-9d18a20b-4046-40d6-8866-f78ea7f520b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879432322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.879432322
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.3754927765
Short name T90
Test name
Test status
Simulation time 93934286 ps
CPU time 0.68 seconds
Started Jul 14 06:07:19 PM PDT 24
Finished Jul 14 06:07:20 PM PDT 24
Peak memory 205160 kb
Host smart-7e129769-3236-48b3-be0a-19d66a0f3590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754927765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3754927765
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1665310275
Short name T1202
Test name
Test status
Simulation time 12503031636 ps
CPU time 123.93 seconds
Started Jul 14 06:07:17 PM PDT 24
Finished Jul 14 06:09:22 PM PDT 24
Peak memory 217084 kb
Host smart-3224217c-296c-4870-9e88-54f84a873086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665310275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1665310275
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.241379637
Short name T711
Test name
Test status
Simulation time 74754230 ps
CPU time 1.69 seconds
Started Jul 14 06:07:15 PM PDT 24
Finished Jul 14 06:07:17 PM PDT 24
Peak memory 220824 kb
Host smart-e08ea743-e967-4eec-aeb4-109ff54abd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241379637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.241379637
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1515768557
Short name T370
Test name
Test status
Simulation time 7229637652 ps
CPU time 83.53 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:08:40 PM PDT 24
Peak memory 294484 kb
Host smart-30e08c3f-acee-4afe-8241-bfbb3d4d3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515768557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1515768557
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2711764496
Short name T1525
Test name
Test status
Simulation time 1306181065 ps
CPU time 10.33 seconds
Started Jul 14 06:07:22 PM PDT 24
Finished Jul 14 06:07:32 PM PDT 24
Peak memory 221072 kb
Host smart-c082824d-339b-470e-a0cf-056aa398b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711764496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2711764496
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.592200793
Short name T892
Test name
Test status
Simulation time 842659531 ps
CPU time 4.63 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:29 PM PDT 24
Peak memory 213872 kb
Host smart-bbefcac9-a7d6-44e7-81e8-0bca6154db09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592200793 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.592200793
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3093224135
Short name T592
Test name
Test status
Simulation time 213079492 ps
CPU time 1.49 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 205416 kb
Host smart-1e85284a-b0e9-4c79-be41-966048b101da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093224135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3093224135
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2419703821
Short name T457
Test name
Test status
Simulation time 731250444 ps
CPU time 1.63 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 205576 kb
Host smart-2f7c6eb9-a298-412e-9103-080f5626d01b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419703821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2419703821
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.3917551734
Short name T426
Test name
Test status
Simulation time 2157556898 ps
CPU time 2.92 seconds
Started Jul 14 06:07:25 PM PDT 24
Finished Jul 14 06:07:29 PM PDT 24
Peak memory 205620 kb
Host smart-ffd978a0-e7c3-4417-a629-10b57bc9e326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917551734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.3917551734
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.964263666
Short name T410
Test name
Test status
Simulation time 378509754 ps
CPU time 1.21 seconds
Started Jul 14 06:07:25 PM PDT 24
Finished Jul 14 06:07:27 PM PDT 24
Peak memory 205452 kb
Host smart-3976aac2-71f9-494b-93e1-59c9fd1b1e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964263666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.964263666
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3177605163
Short name T1237
Test name
Test status
Simulation time 205651949 ps
CPU time 1.56 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 206004 kb
Host smart-e1060c87-fb88-48cf-9212-dc121e422b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177605163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3177605163
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2631529761
Short name T1384
Test name
Test status
Simulation time 5697972820 ps
CPU time 4.14 seconds
Started Jul 14 06:07:25 PM PDT 24
Finished Jul 14 06:07:29 PM PDT 24
Peak memory 221864 kb
Host smart-15e731fb-77c6-456c-8c75-362a5b1e742e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631529761 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2631529761
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.336007493
Short name T938
Test name
Test status
Simulation time 9670418760 ps
CPU time 19.6 seconds
Started Jul 14 06:07:25 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 698164 kb
Host smart-73a10b4b-8ada-4950-a2e5-950f2b455d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336007493 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.336007493
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.2967046462
Short name T1158
Test name
Test status
Simulation time 503170356 ps
CPU time 3.07 seconds
Started Jul 14 06:07:27 PM PDT 24
Finished Jul 14 06:07:31 PM PDT 24
Peak memory 213800 kb
Host smart-d92c937d-9fe8-42ad-9a4c-ac1cfb8bbdcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967046462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.2967046462
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.1946444282
Short name T1531
Test name
Test status
Simulation time 1155423784 ps
CPU time 2.76 seconds
Started Jul 14 06:07:25 PM PDT 24
Finished Jul 14 06:07:29 PM PDT 24
Peak memory 205540 kb
Host smart-b1beb9b2-affc-4a3d-aa17-8afa0c6c503d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946444282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.1946444282
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.3684895250
Short name T1610
Test name
Test status
Simulation time 542356969 ps
CPU time 1.6 seconds
Started Jul 14 06:07:26 PM PDT 24
Finished Jul 14 06:07:28 PM PDT 24
Peak memory 222044 kb
Host smart-3cd0e125-c25e-4970-91b3-12ef842fde79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684895250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.3684895250
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.2075448183
Short name T739
Test name
Test status
Simulation time 1661442495 ps
CPU time 5.68 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 221984 kb
Host smart-0da128ee-acef-45f2-9375-1085be18096d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075448183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.2075448183
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.2282720059
Short name T620
Test name
Test status
Simulation time 1003798763 ps
CPU time 2.32 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:27 PM PDT 24
Peak memory 205408 kb
Host smart-35dbe7c2-13bb-4253-a1f1-d894083d9c89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282720059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.2282720059
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1235350622
Short name T1111
Test name
Test status
Simulation time 2950938066 ps
CPU time 23.04 seconds
Started Jul 14 06:07:22 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 217516 kb
Host smart-ad969cd5-293c-4788-8964-740e68c9497d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235350622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1235350622
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.3051043910
Short name T653
Test name
Test status
Simulation time 225309549012 ps
CPU time 116.55 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:09:21 PM PDT 24
Peak memory 714644 kb
Host smart-feab6a21-d6b7-44d2-82f5-652cb5b8a0cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051043910 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.3051043910
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2061044434
Short name T1445
Test name
Test status
Simulation time 2806019535 ps
CPU time 25.22 seconds
Started Jul 14 06:07:22 PM PDT 24
Finished Jul 14 06:07:48 PM PDT 24
Peak memory 230084 kb
Host smart-17c87646-4ab2-4ef9-924d-7856b38fc378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061044434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2061044434
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1454262526
Short name T1528
Test name
Test status
Simulation time 52901993174 ps
CPU time 88.14 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 1316400 kb
Host smart-bd4f3f05-3069-4ac4-bdbe-f35ff62f0b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454262526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1454262526
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1318684574
Short name T1733
Test name
Test status
Simulation time 2266804349 ps
CPU time 11.2 seconds
Started Jul 14 06:07:16 PM PDT 24
Finished Jul 14 06:07:27 PM PDT 24
Peak memory 323496 kb
Host smart-f77af04d-3475-4323-a106-3a64c5fa8781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318684574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1318684574
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2238510078
Short name T344
Test name
Test status
Simulation time 1526993398 ps
CPU time 8.32 seconds
Started Jul 14 06:07:23 PM PDT 24
Finished Jul 14 06:07:32 PM PDT 24
Peak memory 221928 kb
Host smart-845ce8d8-87cf-41f8-b045-4a1844c698c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238510078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2238510078
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.1781820536
Short name T1247
Test name
Test status
Simulation time 473687041 ps
CPU time 6.32 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:07:40 PM PDT 24
Peak memory 205560 kb
Host smart-9ef09590-f636-4d92-be31-f96aaa854f80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781820536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.1781820536
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2620679848
Short name T1734
Test name
Test status
Simulation time 17922009 ps
CPU time 0.65 seconds
Started Jul 14 06:07:39 PM PDT 24
Finished Jul 14 06:07:40 PM PDT 24
Peak memory 204752 kb
Host smart-791a64be-7b4f-41e7-8fa0-12a1776cfc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620679848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2620679848
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2976385385
Short name T1262
Test name
Test status
Simulation time 576180186 ps
CPU time 11.41 seconds
Started Jul 14 06:07:32 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 221692 kb
Host smart-e7e03a5c-ed6b-4ef5-b4a3-56ad1c081fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976385385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2976385385
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1156023744
Short name T1166
Test name
Test status
Simulation time 226324452 ps
CPU time 4.16 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:07:37 PM PDT 24
Peak memory 247028 kb
Host smart-8bd2ad96-5c1d-4493-94cf-a875cbca0fa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156023744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1156023744
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2044850080
Short name T905
Test name
Test status
Simulation time 7507918028 ps
CPU time 143.95 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:09:56 PM PDT 24
Peak memory 799328 kb
Host smart-cd12941d-5577-492c-b588-d41928924b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044850080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2044850080
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3478665931
Short name T1713
Test name
Test status
Simulation time 18679271380 ps
CPU time 43.26 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:08:14 PM PDT 24
Peak memory 533784 kb
Host smart-32100b2e-d366-45c2-8a9f-56b9cba3a529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478665931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3478665931
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3684546072
Short name T1660
Test name
Test status
Simulation time 920144707 ps
CPU time 12.52 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 249496 kb
Host smart-baa6e22d-dc92-4b5d-a3ad-c2a71507f7e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684546072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3684546072
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.4191053560
Short name T1376
Test name
Test status
Simulation time 15410375777 ps
CPU time 238.7 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:11:33 PM PDT 24
Peak memory 1028788 kb
Host smart-a402d4ab-fed5-4feb-be52-e9cb1b490137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191053560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.4191053560
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1423465123
Short name T1203
Test name
Test status
Simulation time 352718117 ps
CPU time 4.27 seconds
Started Jul 14 06:07:41 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 205500 kb
Host smart-c823666e-1945-49e2-a720-39b9c420dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423465123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1423465123
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.2324799388
Short name T1604
Test name
Test status
Simulation time 82724013 ps
CPU time 0.68 seconds
Started Jul 14 06:07:24 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 205108 kb
Host smart-3646c505-64e0-4f8d-8223-05ffe8db9022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324799388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2324799388
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2161331951
Short name T1382
Test name
Test status
Simulation time 4323796599 ps
CPU time 44.91 seconds
Started Jul 14 06:07:29 PM PDT 24
Finished Jul 14 06:08:14 PM PDT 24
Peak memory 348108 kb
Host smart-fdaf0723-4b54-4685-aac7-665cff588eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161331951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2161331951
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.4030843356
Short name T700
Test name
Test status
Simulation time 146310520 ps
CPU time 1.11 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:33 PM PDT 24
Peak memory 213444 kb
Host smart-e21328f8-75cd-487e-9599-22a56dee4df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030843356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.4030843356
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2638396599
Short name T1442
Test name
Test status
Simulation time 1879440460 ps
CPU time 87.06 seconds
Started Jul 14 06:07:27 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 366600 kb
Host smart-54576d41-de02-4f8b-9174-ecc266462330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638396599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2638396599
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2146416437
Short name T267
Test name
Test status
Simulation time 8384844963 ps
CPU time 685.36 seconds
Started Jul 14 06:07:30 PM PDT 24
Finished Jul 14 06:18:56 PM PDT 24
Peak memory 1495412 kb
Host smart-4dfc39f2-643c-4a23-85c8-40a24541c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146416437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2146416437
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3617221912
Short name T1500
Test name
Test status
Simulation time 742783379 ps
CPU time 35.04 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 213680 kb
Host smart-6852d8eb-d643-43a6-bd4b-4e52a52bc2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617221912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3617221912
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1570225343
Short name T8
Test name
Test status
Simulation time 2032241878 ps
CPU time 5.44 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 213800 kb
Host smart-a07361a2-012b-4d92-8460-1b5c5c846cff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570225343 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1570225343
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.736061727
Short name T1241
Test name
Test status
Simulation time 193639431 ps
CPU time 0.87 seconds
Started Jul 14 06:07:37 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 205432 kb
Host smart-c73294d2-56e7-4391-8d9e-f7946bf0246a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736061727 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.736061727
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.4162911355
Short name T1618
Test name
Test status
Simulation time 443709697 ps
CPU time 2.84 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 205560 kb
Host smart-ddd68e34-f139-43fb-9375-ae027e58f069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162911355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.4162911355
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.216333360
Short name T345
Test name
Test status
Simulation time 592407858 ps
CPU time 1.55 seconds
Started Jul 14 06:07:36 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 205468 kb
Host smart-35845349-89b4-484d-a3e6-d236f74b8765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216333360 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.216333360
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3016328196
Short name T1603
Test name
Test status
Simulation time 580348429 ps
CPU time 2.42 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 213768 kb
Host smart-145c1af9-9bfb-40da-8d69-1e527e9b9e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016328196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3016328196
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.285348519
Short name T68
Test name
Test status
Simulation time 3144687201 ps
CPU time 5.24 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 221924 kb
Host smart-0d176da0-1b7a-493d-aeda-e6bf97ccb9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285348519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.285348519
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.356829109
Short name T783
Test name
Test status
Simulation time 8383034030 ps
CPU time 36.17 seconds
Started Jul 14 06:07:34 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 1111512 kb
Host smart-21397623-d0d8-4c31-a3cf-e11ae81f2843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356829109 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.356829109
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.3866725620
Short name T832
Test name
Test status
Simulation time 2183966091 ps
CPU time 3.15 seconds
Started Jul 14 06:07:36 PM PDT 24
Finished Jul 14 06:07:39 PM PDT 24
Peak memory 213856 kb
Host smart-67a814d6-d808-4961-98b9-0527f0f0595d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866725620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.3866725620
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.475221419
Short name T633
Test name
Test status
Simulation time 2321691067 ps
CPU time 2.78 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 205692 kb
Host smart-50b384e0-2218-47e1-83d7-05c5c6d0334a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475221419 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.475221419
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.4201408898
Short name T797
Test name
Test status
Simulation time 1581014010 ps
CPU time 1.4 seconds
Started Jul 14 06:07:37 PM PDT 24
Finished Jul 14 06:07:39 PM PDT 24
Peak memory 222444 kb
Host smart-7adb2a5c-bec9-4d2a-857e-92640cd12b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201408898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_txstretch.4201408898
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.1785836737
Short name T482
Test name
Test status
Simulation time 635389222 ps
CPU time 5.11 seconds
Started Jul 14 06:07:38 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 213768 kb
Host smart-4870dbaa-9563-4037-badf-a49e3b28e3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785836737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.1785836737
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.2553451291
Short name T582
Test name
Test status
Simulation time 658998857 ps
CPU time 2.45 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 205308 kb
Host smart-d4eb68d5-6023-407f-903b-ec614486d38b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553451291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.2553451291
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2881499797
Short name T290
Test name
Test status
Simulation time 745366710 ps
CPU time 10.12 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:42 PM PDT 24
Peak memory 213816 kb
Host smart-6ce372fa-186d-4d56-a471-e48cc4a35695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881499797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2881499797
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3525210019
Short name T1155
Test name
Test status
Simulation time 114714523006 ps
CPU time 110.9 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:09:36 PM PDT 24
Peak memory 624928 kb
Host smart-a487e1e7-d0d6-440e-afec-a398eeda7956
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525210019 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3525210019
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3638732523
Short name T539
Test name
Test status
Simulation time 4402385527 ps
CPU time 20.78 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:07:53 PM PDT 24
Peak memory 221932 kb
Host smart-fb471f61-31ab-45e8-b152-4cc95d01b309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638732523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3638732523
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2100372433
Short name T299
Test name
Test status
Simulation time 33146938321 ps
CPU time 49.36 seconds
Started Jul 14 06:07:33 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 885640 kb
Host smart-04dfe7cf-464c-4264-ba88-ef7163a3c928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100372433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2100372433
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3496045228
Short name T499
Test name
Test status
Simulation time 1845827817 ps
CPU time 27.8 seconds
Started Jul 14 06:07:31 PM PDT 24
Finished Jul 14 06:08:00 PM PDT 24
Peak memory 606496 kb
Host smart-fe7b1461-4856-49fd-b345-de5a485f2789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496045228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3496045228
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2100623188
Short name T1673
Test name
Test status
Simulation time 7486111265 ps
CPU time 8.05 seconds
Started Jul 14 06:07:32 PM PDT 24
Finished Jul 14 06:07:41 PM PDT 24
Peak memory 233160 kb
Host smart-9a3acf90-ee1e-4a17-beaa-33664c565c72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100623188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2100623188
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.866587052
Short name T1402
Test name
Test status
Simulation time 142658989 ps
CPU time 3.55 seconds
Started Jul 14 06:07:38 PM PDT 24
Finished Jul 14 06:07:42 PM PDT 24
Peak memory 206424 kb
Host smart-a0d19fbb-2ce8-4c7f-bf47-b6597477b945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866587052 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.866587052
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1093410377
Short name T496
Test name
Test status
Simulation time 17212351 ps
CPU time 0.65 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:07:48 PM PDT 24
Peak memory 204844 kb
Host smart-73fd1114-0155-417b-98ad-33157e673e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093410377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1093410377
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4065569130
Short name T980
Test name
Test status
Simulation time 374272326 ps
CPU time 2.35 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:07:47 PM PDT 24
Peak memory 213820 kb
Host smart-600e9bb4-2d3d-4ade-b4dc-8e7ff97a5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065569130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4065569130
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1865260053
Short name T1552
Test name
Test status
Simulation time 1286963680 ps
CPU time 6.1 seconds
Started Jul 14 06:07:38 PM PDT 24
Finished Jul 14 06:07:44 PM PDT 24
Peak memory 273936 kb
Host smart-4be6302c-fac5-4ee6-90cf-ea941b5a0495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865260053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1865260053
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1270555779
Short name T556
Test name
Test status
Simulation time 2403378639 ps
CPU time 77.34 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 554852 kb
Host smart-ffd63fe0-e6ca-407a-8313-db0f58514d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270555779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1270555779
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.111461161
Short name T1224
Test name
Test status
Simulation time 13723450141 ps
CPU time 38.74 seconds
Started Jul 14 06:07:38 PM PDT 24
Finished Jul 14 06:08:17 PM PDT 24
Peak memory 547464 kb
Host smart-24e5d188-0d78-4553-91b3-c1129bd65ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111461161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.111461161
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3504107704
Short name T235
Test name
Test status
Simulation time 541938290 ps
CPU time 1.11 seconds
Started Jul 14 06:07:37 PM PDT 24
Finished Jul 14 06:07:39 PM PDT 24
Peak memory 205240 kb
Host smart-5a01f64b-934e-4f8c-b875-64336708cc17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504107704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3504107704
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2334069047
Short name T985
Test name
Test status
Simulation time 731717353 ps
CPU time 4.86 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:07:49 PM PDT 24
Peak memory 243408 kb
Host smart-4f1f22e3-3a70-42fb-8bd2-e318e9a54dd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334069047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2334069047
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.542488311
Short name T1647
Test name
Test status
Simulation time 12006669030 ps
CPU time 146.9 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:10:08 PM PDT 24
Peak memory 724188 kb
Host smart-b680751f-444c-4c29-8370-80d4be9bf260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542488311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.542488311
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3507720470
Short name T702
Test name
Test status
Simulation time 806180762 ps
CPU time 6.5 seconds
Started Jul 14 06:07:48 PM PDT 24
Finished Jul 14 06:07:55 PM PDT 24
Peak memory 205480 kb
Host smart-c294442c-d786-43f3-99b7-d9ae173c6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507720470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3507720470
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1810957289
Short name T1144
Test name
Test status
Simulation time 558412863 ps
CPU time 4.84 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:52 PM PDT 24
Peak memory 214792 kb
Host smart-5a36e3ff-72c5-4b96-85fe-0fbda8a9769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810957289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1810957289
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2574710763
Short name T320
Test name
Test status
Simulation time 66482196 ps
CPU time 0.7 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:07:45 PM PDT 24
Peak memory 205208 kb
Host smart-31fb36c8-2aed-4611-b44f-aa428339d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574710763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2574710763
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3083821605
Short name T1522
Test name
Test status
Simulation time 73950548821 ps
CPU time 54.44 seconds
Started Jul 14 06:07:39 PM PDT 24
Finished Jul 14 06:08:34 PM PDT 24
Peak memory 213748 kb
Host smart-947fbe18-6586-454a-bfa6-761a25b6b73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083821605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3083821605
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.3383278978
Short name T287
Test name
Test status
Simulation time 139054989 ps
CPU time 1.64 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 213612 kb
Host smart-3afe49e8-a123-4d78-a593-841928aa7515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383278978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.3383278978
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3908484382
Short name T1229
Test name
Test status
Simulation time 6511300962 ps
CPU time 74.94 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 401568 kb
Host smart-529cda69-aa1d-4933-8485-d1df1001221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908484382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3908484382
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3891127251
Short name T340
Test name
Test status
Simulation time 986994637 ps
CPU time 22.95 seconds
Started Jul 14 06:07:41 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 213688 kb
Host smart-03bd10a9-d9ab-46d4-bc4d-3100f25e455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891127251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3891127251
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3386833131
Short name T663
Test name
Test status
Simulation time 3375056724 ps
CPU time 5.15 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:07:52 PM PDT 24
Peak memory 213860 kb
Host smart-8e7efe78-4829-457f-a521-cb2c9e3cf552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386833131 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3386833131
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.4238835118
Short name T688
Test name
Test status
Simulation time 679697897 ps
CPU time 1.46 seconds
Started Jul 14 06:07:43 PM PDT 24
Finished Jul 14 06:07:45 PM PDT 24
Peak memory 205576 kb
Host smart-cf2a3cdf-f844-4c22-85d9-f2563dba61f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238835118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.4238835118
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3828921016
Short name T909
Test name
Test status
Simulation time 200287811 ps
CPU time 1.32 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:07:48 PM PDT 24
Peak memory 205580 kb
Host smart-6a57d157-669b-44b4-a68d-7757a2a5f04b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828921016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3828921016
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.2063309421
Short name T1664
Test name
Test status
Simulation time 1384081694 ps
CPU time 2.41 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:50 PM PDT 24
Peak memory 205560 kb
Host smart-bc518883-64e0-4bbf-a12e-9539bb8a9294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063309421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.2063309421
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2729624243
Short name T1272
Test name
Test status
Simulation time 380134023 ps
CPU time 0.95 seconds
Started Jul 14 06:07:48 PM PDT 24
Finished Jul 14 06:07:50 PM PDT 24
Peak memory 205364 kb
Host smart-6cb39fa1-8106-4715-9cba-0bbf2dd0e259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729624243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2729624243
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1587569397
Short name T1190
Test name
Test status
Simulation time 1090303954 ps
CPU time 6.02 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:46 PM PDT 24
Peak memory 221012 kb
Host smart-14a17488-f21e-4cb2-a928-918ac6ba4eb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587569397 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1587569397
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1223294803
Short name T1033
Test name
Test status
Simulation time 12492648966 ps
CPU time 17.87 seconds
Started Jul 14 06:07:44 PM PDT 24
Finished Jul 14 06:08:03 PM PDT 24
Peak memory 431988 kb
Host smart-f5539e18-3eb3-40b7-b016-0815b7d62f44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223294803 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1223294803
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.2705326324
Short name T384
Test name
Test status
Simulation time 1000035703 ps
CPU time 2.86 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:51 PM PDT 24
Peak memory 213732 kb
Host smart-bb57d1e7-068d-400f-8167-f96078f39e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705326324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.2705326324
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.2422530144
Short name T1106
Test name
Test status
Simulation time 2349576066 ps
CPU time 2.94 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:51 PM PDT 24
Peak memory 205904 kb
Host smart-6e3ca2cc-de52-43c2-96c2-7e01134afb82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422530144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.2422530144
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.926251708
Short name T792
Test name
Test status
Simulation time 1350475953 ps
CPU time 4.88 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:53 PM PDT 24
Peak memory 221984 kb
Host smart-9bce3d86-3329-4697-9924-010f2975f09d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926251708 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_perf.926251708
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.989282430
Short name T1182
Test name
Test status
Simulation time 886982512 ps
CPU time 2.2 seconds
Started Jul 14 06:07:45 PM PDT 24
Finished Jul 14 06:07:48 PM PDT 24
Peak memory 205392 kb
Host smart-1099c8a0-bb47-4d76-ab1c-0d1147a02f5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989282430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_smbus_maxlen.989282430
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2507237115
Short name T920
Test name
Test status
Simulation time 1186489881 ps
CPU time 41.43 seconds
Started Jul 14 06:07:39 PM PDT 24
Finished Jul 14 06:08:21 PM PDT 24
Peak memory 213800 kb
Host smart-c6db1070-672e-4806-9e30-4ae729894dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507237115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2507237115
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.75935395
Short name T973
Test name
Test status
Simulation time 48851415956 ps
CPU time 51 seconds
Started Jul 14 06:07:50 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 287440 kb
Host smart-b2f84efb-7888-4203-86a1-c91ae750750c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75935395 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.i2c_target_stress_all.75935395
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1503448086
Short name T616
Test name
Test status
Simulation time 1250455189 ps
CPU time 22.13 seconds
Started Jul 14 06:07:41 PM PDT 24
Finished Jul 14 06:08:03 PM PDT 24
Peak memory 229996 kb
Host smart-cd009c71-3e14-4dc4-81b9-66da4cc1617f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503448086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1503448086
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3741662899
Short name T526
Test name
Test status
Simulation time 8860902322 ps
CPU time 2.56 seconds
Started Jul 14 06:07:40 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 205648 kb
Host smart-135e4d95-16d3-4b9f-820f-ed3905bf9ef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741662899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3741662899
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3294867873
Short name T1554
Test name
Test status
Simulation time 2232731951 ps
CPU time 40.59 seconds
Started Jul 14 06:07:39 PM PDT 24
Finished Jul 14 06:08:20 PM PDT 24
Peak memory 696184 kb
Host smart-e5af0998-9003-40f8-8c54-93fd8dea0093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294867873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3294867873
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.859378659
Short name T1295
Test name
Test status
Simulation time 1198425710 ps
CPU time 7.1 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:07:54 PM PDT 24
Peak memory 230148 kb
Host smart-8cb9f752-4110-4678-9ab3-721fb27a30ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859378659 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.859378659
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.3178022003
Short name T401
Test name
Test status
Simulation time 122985351 ps
CPU time 1.9 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:07:50 PM PDT 24
Peak memory 205504 kb
Host smart-72fd2c33-82bc-40e7-8fac-b7ca5056f64f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178022003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3178022003
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1423300575
Short name T844
Test name
Test status
Simulation time 19505874 ps
CPU time 0.63 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:04 PM PDT 24
Peak memory 204736 kb
Host smart-144b1f82-85d0-49c5-9433-e8842b0a021d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423300575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1423300575
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.973675623
Short name T1266
Test name
Test status
Simulation time 400913252 ps
CPU time 8.22 seconds
Started Jul 14 06:07:55 PM PDT 24
Finished Jul 14 06:08:04 PM PDT 24
Peak memory 237560 kb
Host smart-ec99d363-369d-40cb-ad82-71d42b739192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973675623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.973675623
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1081732857
Short name T406
Test name
Test status
Simulation time 426940136 ps
CPU time 21.66 seconds
Started Jul 14 06:07:47 PM PDT 24
Finished Jul 14 06:08:09 PM PDT 24
Peak memory 290820 kb
Host smart-4e14ee8e-f037-4dd0-bb3d-8c5cd2a076e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081732857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1081732857
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4124182154
Short name T400
Test name
Test status
Simulation time 10544093596 ps
CPU time 171.33 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:10:38 PM PDT 24
Peak memory 574132 kb
Host smart-b776c684-9704-4f59-abd4-0f2b24eff438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124182154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4124182154
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3230281539
Short name T1067
Test name
Test status
Simulation time 13798567678 ps
CPU time 134.3 seconds
Started Jul 14 06:07:48 PM PDT 24
Finished Jul 14 06:10:03 PM PDT 24
Peak memory 626656 kb
Host smart-60e2f0ca-9444-4eaf-878d-d1fb675d0d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230281539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3230281539
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1372264949
Short name T975
Test name
Test status
Simulation time 277943071 ps
CPU time 1.17 seconds
Started Jul 14 06:07:46 PM PDT 24
Finished Jul 14 06:07:48 PM PDT 24
Peak memory 205204 kb
Host smart-3dd5f48f-2826-4ebd-9486-c2d18cd296ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372264949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1372264949
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3822315977
Short name T1547
Test name
Test status
Simulation time 235198587 ps
CPU time 6.78 seconds
Started Jul 14 06:07:50 PM PDT 24
Finished Jul 14 06:07:58 PM PDT 24
Peak memory 205392 kb
Host smart-7b1cf5ad-20d6-466c-9c40-4f0bbdd37c42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822315977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3822315977
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1389287984
Short name T1068
Test name
Test status
Simulation time 2664809224 ps
CPU time 58.55 seconds
Started Jul 14 06:07:45 PM PDT 24
Finished Jul 14 06:08:44 PM PDT 24
Peak memory 867064 kb
Host smart-bdd83ede-437a-4df7-87ac-a2b8cd8ff582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389287984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1389287984
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.881278131
Short name T21
Test name
Test status
Simulation time 1501318094 ps
CPU time 4.42 seconds
Started Jul 14 06:07:53 PM PDT 24
Finished Jul 14 06:07:58 PM PDT 24
Peak memory 205492 kb
Host smart-e6ca0c7c-7ba6-466a-931a-19aaa0326372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881278131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.881278131
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.1263318648
Short name T1606
Test name
Test status
Simulation time 263991681 ps
CPU time 0.69 seconds
Started Jul 14 06:07:51 PM PDT 24
Finished Jul 14 06:07:52 PM PDT 24
Peak memory 205128 kb
Host smart-71677da0-4289-4ec6-ae71-7ea66ac95c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263318648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1263318648
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2476987173
Short name T391
Test name
Test status
Simulation time 7444151599 ps
CPU time 34.06 seconds
Started Jul 14 06:07:57 PM PDT 24
Finished Jul 14 06:08:32 PM PDT 24
Peak memory 346228 kb
Host smart-d6c50f06-38f8-4e97-9099-c797e5a83651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476987173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2476987173
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2656976216
Short name T1452
Test name
Test status
Simulation time 518440247 ps
CPU time 13.83 seconds
Started Jul 14 06:07:51 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 244768 kb
Host smart-423d9a09-991e-4b06-95cd-3ec70188e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656976216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2656976216
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3329496758
Short name T42
Test name
Test status
Simulation time 7131740073 ps
CPU time 35.34 seconds
Started Jul 14 06:07:51 PM PDT 24
Finished Jul 14 06:08:27 PM PDT 24
Peak memory 344340 kb
Host smart-e69e5fc0-68f9-4f6d-bfbd-6fdeec845828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329496758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3329496758
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1679526713
Short name T607
Test name
Test status
Simulation time 458249376 ps
CPU time 9.29 seconds
Started Jul 14 06:07:53 PM PDT 24
Finished Jul 14 06:08:03 PM PDT 24
Peak memory 213688 kb
Host smart-29a01daa-d194-48ea-919a-8dbc0551450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679526713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1679526713
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3788097455
Short name T455
Test name
Test status
Simulation time 2352047379 ps
CPU time 3.87 seconds
Started Jul 14 06:07:55 PM PDT 24
Finished Jul 14 06:07:59 PM PDT 24
Peak memory 220244 kb
Host smart-acebc4d2-735d-4342-800b-bd85c5371781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788097455 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3788097455
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1711259168
Short name T1191
Test name
Test status
Simulation time 150399427 ps
CPU time 1.02 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:08:00 PM PDT 24
Peak memory 205376 kb
Host smart-4cddcca8-58e2-4e7a-8a06-813ea9d3ab7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711259168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1711259168
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1110673680
Short name T437
Test name
Test status
Simulation time 1069869925 ps
CPU time 1.44 seconds
Started Jul 14 06:07:57 PM PDT 24
Finished Jul 14 06:07:58 PM PDT 24
Peak memory 213740 kb
Host smart-45456fa3-a086-4ae9-ad6e-368b84e7c662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110673680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1110673680
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1251683700
Short name T1642
Test name
Test status
Simulation time 277652877 ps
CPU time 2.05 seconds
Started Jul 14 06:07:57 PM PDT 24
Finished Jul 14 06:07:59 PM PDT 24
Peak memory 205308 kb
Host smart-7e9e896c-425c-421c-be47-f4243dcb4312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251683700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1251683700
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.4135282935
Short name T1492
Test name
Test status
Simulation time 232751330 ps
CPU time 0.9 seconds
Started Jul 14 06:07:54 PM PDT 24
Finished Jul 14 06:07:56 PM PDT 24
Peak memory 205388 kb
Host smart-b1e45bd5-093d-4d57-8f95-daead59c6d62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135282935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.4135282935
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3402757230
Short name T799
Test name
Test status
Simulation time 1523292755 ps
CPU time 2.26 seconds
Started Jul 14 06:07:55 PM PDT 24
Finished Jul 14 06:07:58 PM PDT 24
Peak memory 214068 kb
Host smart-00a0231b-b051-4373-ad53-ae83ff1bafa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402757230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3402757230
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1309308729
Short name T443
Test name
Test status
Simulation time 5296933487 ps
CPU time 8.39 seconds
Started Jul 14 06:07:53 PM PDT 24
Finished Jul 14 06:08:02 PM PDT 24
Peak memory 222040 kb
Host smart-6b2c3c06-ca33-4d7d-b862-63cf2fcd1379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309308729 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1309308729
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1947229412
Short name T617
Test name
Test status
Simulation time 15605651509 ps
CPU time 384.09 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:14:23 PM PDT 24
Peak memory 3901752 kb
Host smart-a0aef89d-7eea-430e-9a12-c85be6cc3410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947229412 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1947229412
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.1362781738
Short name T62
Test name
Test status
Simulation time 4448550753 ps
CPU time 2.75 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:08:02 PM PDT 24
Peak memory 213840 kb
Host smart-c6d447c4-f226-44bb-a6b8-ee6e1da6984e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362781738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.1362781738
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.1171387871
Short name T1339
Test name
Test status
Simulation time 989338518 ps
CPU time 2.71 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:06 PM PDT 24
Peak memory 205532 kb
Host smart-6c878b2f-d050-4e1e-89be-32eccd2324bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171387871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.1171387871
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.3383284387
Short name T902
Test name
Test status
Simulation time 574919482 ps
CPU time 1.54 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:08:01 PM PDT 24
Peak memory 222204 kb
Host smart-2972ea1a-38b0-46b5-9378-13f869a31456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383284387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_nack_txstretch.3383284387
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.971446269
Short name T1208
Test name
Test status
Simulation time 2752253715 ps
CPU time 4.77 seconds
Started Jul 14 06:07:57 PM PDT 24
Finished Jul 14 06:08:02 PM PDT 24
Peak memory 221956 kb
Host smart-a81dfadf-7c05-4987-b3df-46574639f53b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971446269 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_perf.971446269
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.955572497
Short name T304
Test name
Test status
Simulation time 2597243122 ps
CPU time 2.27 seconds
Started Jul 14 06:07:53 PM PDT 24
Finished Jul 14 06:07:55 PM PDT 24
Peak memory 205388 kb
Host smart-cc116fbb-083e-44fb-b4aa-a3345904837c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955572497 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_smbus_maxlen.955572497
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.751889212
Short name T1513
Test name
Test status
Simulation time 3389709069 ps
CPU time 12.94 seconds
Started Jul 14 06:07:57 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 213792 kb
Host smart-e393b37e-2f75-42f9-8a5b-7616a6b75010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751889212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.751889212
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.177031558
Short name T837
Test name
Test status
Simulation time 49011930821 ps
CPU time 128.5 seconds
Started Jul 14 06:07:55 PM PDT 24
Finished Jul 14 06:10:04 PM PDT 24
Peak memory 1047272 kb
Host smart-3b2886c9-a902-479c-aca9-3359960551ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177031558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.177031558
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.274108341
Short name T503
Test name
Test status
Simulation time 1266679320 ps
CPU time 7.76 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:08:06 PM PDT 24
Peak memory 215832 kb
Host smart-d822c4cf-189b-435c-bfb5-9a692376b273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274108341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.274108341
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3127039534
Short name T1416
Test name
Test status
Simulation time 12980278901 ps
CPU time 27.58 seconds
Started Jul 14 06:07:52 PM PDT 24
Finished Jul 14 06:08:20 PM PDT 24
Peak memory 205628 kb
Host smart-7e6b1cfb-75ed-49e7-859b-a1e2a17f6357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127039534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3127039534
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3342863569
Short name T613
Test name
Test status
Simulation time 3011816656 ps
CPU time 14.47 seconds
Started Jul 14 06:07:55 PM PDT 24
Finished Jul 14 06:08:10 PM PDT 24
Peak memory 252984 kb
Host smart-8624788f-c1d7-4053-be49-6e861377eb40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342863569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3342863569
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1851349615
Short name T261
Test name
Test status
Simulation time 2747213875 ps
CPU time 7.3 seconds
Started Jul 14 06:07:54 PM PDT 24
Finished Jul 14 06:08:03 PM PDT 24
Peak memory 235916 kb
Host smart-d086b611-1081-48ac-9e08-e3c722e56c15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851349615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1851349615
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.1164348455
Short name T356
Test name
Test status
Simulation time 472986327 ps
CPU time 6.43 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 205544 kb
Host smart-a33b27f5-cc80-41f9-8015-3cd0d5c86e67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164348455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.1164348455
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3491780293
Short name T813
Test name
Test status
Simulation time 29086926 ps
CPU time 0.67 seconds
Started Jul 14 06:08:07 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 204824 kb
Host smart-6b653003-001f-415a-8614-ab982c4a5d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491780293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3491780293
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1282230803
Short name T1432
Test name
Test status
Simulation time 310338106 ps
CPU time 1.53 seconds
Started Jul 14 06:08:03 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 213776 kb
Host smart-898a1153-a6d1-4aac-98d0-11694a8f2365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282230803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1282230803
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.456735224
Short name T854
Test name
Test status
Simulation time 2099092967 ps
CPU time 8.75 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 291160 kb
Host smart-39e80aa1-0c5f-44ea-aee6-48e120ad8ee9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456735224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.456735224
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2031329565
Short name T1129
Test name
Test status
Simulation time 3575503692 ps
CPU time 185.35 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:11:09 PM PDT 24
Peak memory 376872 kb
Host smart-db744ac2-7c63-4869-83b2-de10eeeb4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031329565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2031329565
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.53463697
Short name T1130
Test name
Test status
Simulation time 3684018850 ps
CPU time 111 seconds
Started Jul 14 06:08:05 PM PDT 24
Finished Jul 14 06:09:56 PM PDT 24
Peak memory 591784 kb
Host smart-88746bdf-ef10-4203-bc17-587b47e77f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53463697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.53463697
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1129781854
Short name T906
Test name
Test status
Simulation time 522039207 ps
CPU time 1.08 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:08:01 PM PDT 24
Peak memory 205192 kb
Host smart-168fb4a3-d620-4808-8753-d275af8a2457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129781854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1129781854
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3188430475
Short name T1200
Test name
Test status
Simulation time 539012268 ps
CPU time 5.72 seconds
Started Jul 14 06:08:06 PM PDT 24
Finished Jul 14 06:08:12 PM PDT 24
Peak memory 205484 kb
Host smart-a3734445-8750-4991-9738-10980d0f3b10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188430475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3188430475
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.752403096
Short name T954
Test name
Test status
Simulation time 5149908637 ps
CPU time 157.27 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:10:41 PM PDT 24
Peak memory 833788 kb
Host smart-34f19e82-bb90-42fe-ab65-013864ee29fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752403096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.752403096
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1983785338
Short name T1600
Test name
Test status
Simulation time 2178476971 ps
CPU time 5.59 seconds
Started Jul 14 06:08:00 PM PDT 24
Finished Jul 14 06:08:06 PM PDT 24
Peak memory 205556 kb
Host smart-12ec8ccf-4f99-4b61-b873-3365ea7c7eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983785338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1983785338
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.479020011
Short name T781
Test name
Test status
Simulation time 50491912 ps
CPU time 0.68 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:07:59 PM PDT 24
Peak memory 205172 kb
Host smart-925eda38-390b-4b00-bb9f-8ae7092d528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479020011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.479020011
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2813009645
Short name T1556
Test name
Test status
Simulation time 2408757071 ps
CPU time 96.37 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:09:36 PM PDT 24
Peak memory 230024 kb
Host smart-a0216b5f-fddc-4b32-9cd4-48891bd81f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813009645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2813009645
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.1803810914
Short name T1691
Test name
Test status
Simulation time 605536730 ps
CPU time 2.31 seconds
Started Jul 14 06:08:01 PM PDT 24
Finished Jul 14 06:08:04 PM PDT 24
Peak memory 213596 kb
Host smart-cd209278-5edc-42ec-ba6c-bacea971ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803810914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1803810914
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2081915330
Short name T1534
Test name
Test status
Simulation time 4085622016 ps
CPU time 24.88 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:28 PM PDT 24
Peak memory 334664 kb
Host smart-426c9912-b45f-4d4b-ab57-b445f54528a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081915330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2081915330
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3452566412
Short name T6
Test name
Test status
Simulation time 515218649 ps
CPU time 8.05 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 213672 kb
Host smart-260a274f-6bbb-4c9a-b041-db54c673c513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452566412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3452566412
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2861039394
Short name T433
Test name
Test status
Simulation time 200609971 ps
CPU time 1.31 seconds
Started Jul 14 06:08:01 PM PDT 24
Finished Jul 14 06:08:03 PM PDT 24
Peak memory 205448 kb
Host smart-959c8e5e-c3d2-476f-8f25-9cdaa299efac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861039394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2861039394
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3266410252
Short name T1299
Test name
Test status
Simulation time 372062234 ps
CPU time 1.14 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:05 PM PDT 24
Peak memory 205552 kb
Host smart-b5eda10f-00a1-4632-bc0a-f73bde2742c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266410252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3266410252
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.1821618132
Short name T446
Test name
Test status
Simulation time 667506999 ps
CPU time 1.07 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:08:01 PM PDT 24
Peak memory 205400 kb
Host smart-c9e720f5-0e6c-483d-b130-faa1852308ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821618132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.1821618132
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1825187134
Short name T149
Test name
Test status
Simulation time 743548051 ps
CPU time 1.63 seconds
Started Jul 14 06:08:09 PM PDT 24
Finished Jul 14 06:08:12 PM PDT 24
Peak memory 205432 kb
Host smart-c21a60c0-b21e-400c-a5aa-d9d8ba79002a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825187134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1825187134
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1665016496
Short name T1034
Test name
Test status
Simulation time 2030376099 ps
CPU time 3.77 seconds
Started Jul 14 06:08:03 PM PDT 24
Finished Jul 14 06:08:07 PM PDT 24
Peak memory 213736 kb
Host smart-635fa83b-e2ce-46aa-83bd-80bf6d9f82e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665016496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1665016496
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3851588474
Short name T1648
Test name
Test status
Simulation time 1284207635 ps
CPU time 6.86 seconds
Started Jul 14 06:08:06 PM PDT 24
Finished Jul 14 06:08:13 PM PDT 24
Peak memory 222000 kb
Host smart-80ddf479-30a6-43a5-9094-3ac526df9a6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851588474 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3851588474
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2304994708
Short name T872
Test name
Test status
Simulation time 22882495726 ps
CPU time 65.39 seconds
Started Jul 14 06:07:59 PM PDT 24
Finished Jul 14 06:09:05 PM PDT 24
Peak memory 1244200 kb
Host smart-3324a852-4f80-46c5-9002-fd9c006673a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304994708 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2304994708
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.1615403266
Short name T139
Test name
Test status
Simulation time 1386505338 ps
CPU time 2.78 seconds
Started Jul 14 06:08:08 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 213808 kb
Host smart-0644e0bd-611e-4802-a5de-6e864c990832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615403266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.1615403266
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.3206771164
Short name T857
Test name
Test status
Simulation time 553169915 ps
CPU time 2.74 seconds
Started Jul 14 06:08:10 PM PDT 24
Finished Jul 14 06:08:14 PM PDT 24
Peak memory 205632 kb
Host smart-494e2ec0-5f0e-417f-ad92-96afe8a19217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206771164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.3206771164
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.3100294918
Short name T1226
Test name
Test status
Simulation time 4047446947 ps
CPU time 7.05 seconds
Started Jul 14 06:08:00 PM PDT 24
Finished Jul 14 06:08:07 PM PDT 24
Peak memory 232944 kb
Host smart-6645cc50-a853-4c02-a57a-e3e6d8a27271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100294918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.3100294918
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3515922508
Short name T1652
Test name
Test status
Simulation time 1141735548 ps
CPU time 2.71 seconds
Started Jul 14 06:08:10 PM PDT 24
Finished Jul 14 06:08:14 PM PDT 24
Peak memory 205268 kb
Host smart-dcfecf7c-3f43-4457-bed8-eb91a9583215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515922508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3515922508
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1499338924
Short name T179
Test name
Test status
Simulation time 3654807227 ps
CPU time 29.66 seconds
Started Jul 14 06:08:04 PM PDT 24
Finished Jul 14 06:08:34 PM PDT 24
Peak memory 213840 kb
Host smart-40ac5673-87d0-4725-82b6-d6982aa083b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499338924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1499338924
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.624193093
Short name T1042
Test name
Test status
Simulation time 33292929195 ps
CPU time 149.09 seconds
Started Jul 14 06:07:58 PM PDT 24
Finished Jul 14 06:10:27 PM PDT 24
Peak memory 1386920 kb
Host smart-dc62efef-a9b9-447b-913f-dbd066e2d4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624193093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_stress_all.624193093
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4220143484
Short name T682
Test name
Test status
Simulation time 1071930816 ps
CPU time 16.96 seconds
Started Jul 14 06:08:01 PM PDT 24
Finished Jul 14 06:08:18 PM PDT 24
Peak memory 233248 kb
Host smart-2b5c87af-6b5e-47f6-beb6-7c362590dc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220143484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4220143484
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.888708198
Short name T1459
Test name
Test status
Simulation time 59703243614 ps
CPU time 2342.82 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:47:07 PM PDT 24
Peak memory 10187012 kb
Host smart-26624cc7-739b-42ec-b48a-83730a4a644d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888708198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.888708198
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3549216613
Short name T1474
Test name
Test status
Simulation time 376945755 ps
CPU time 4.42 seconds
Started Jul 14 06:08:02 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 212652 kb
Host smart-c1b6c53c-af8c-4eb4-90e4-d68cab3856cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549216613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3549216613
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.412555651
Short name T1550
Test name
Test status
Simulation time 1203707969 ps
CPU time 6.9 seconds
Started Jul 14 06:08:01 PM PDT 24
Finished Jul 14 06:08:08 PM PDT 24
Peak memory 230076 kb
Host smart-4412d736-6080-46ed-af6a-5e30c11e61b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412555651 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.412555651
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.2171899598
Short name T1283
Test name
Test status
Simulation time 111234809 ps
CPU time 2.71 seconds
Started Jul 14 06:08:06 PM PDT 24
Finished Jul 14 06:08:10 PM PDT 24
Peak memory 205712 kb
Host smart-2b797149-1472-4e77-9180-80a5fb9c2366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171899598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2171899598
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3945272388
Short name T588
Test name
Test status
Simulation time 46738515 ps
CPU time 0.6 seconds
Started Jul 14 06:01:28 PM PDT 24
Finished Jul 14 06:01:29 PM PDT 24
Peak memory 204780 kb
Host smart-94eeed65-c8f0-4030-90d8-c83abe5d6ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945272388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3945272388
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2058874038
Short name T986
Test name
Test status
Simulation time 68127478 ps
CPU time 2.2 seconds
Started Jul 14 06:01:25 PM PDT 24
Finished Jul 14 06:01:28 PM PDT 24
Peak memory 213800 kb
Host smart-73f809e6-afb6-4d3f-8f28-dc7c6180fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058874038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2058874038
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.4203232102
Short name T962
Test name
Test status
Simulation time 815259270 ps
CPU time 21.54 seconds
Started Jul 14 06:01:17 PM PDT 24
Finished Jul 14 06:01:40 PM PDT 24
Peak memory 294232 kb
Host smart-271efe58-a43d-430b-8896-f26a8088445f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203232102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.4203232102
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.434569712
Short name T824
Test name
Test status
Simulation time 3794395415 ps
CPU time 46.95 seconds
Started Jul 14 06:01:24 PM PDT 24
Finished Jul 14 06:02:11 PM PDT 24
Peak memory 386364 kb
Host smart-fd690444-cdc4-46f5-9d2a-adc1d6b38443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434569712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.434569712
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3823324466
Short name T762
Test name
Test status
Simulation time 9034121829 ps
CPU time 166.47 seconds
Started Jul 14 06:01:15 PM PDT 24
Finished Jul 14 06:04:02 PM PDT 24
Peak memory 736856 kb
Host smart-ece21fba-2e12-4819-802d-9462b07e3ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823324466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3823324466
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2204306136
Short name T787
Test name
Test status
Simulation time 1194965956 ps
CPU time 1.05 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:01:19 PM PDT 24
Peak memory 205216 kb
Host smart-afa47211-bd22-4f38-bf7b-88b4ea25c70f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204306136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2204306136
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.4044865746
Short name T1417
Test name
Test status
Simulation time 758204651 ps
CPU time 5.68 seconds
Started Jul 14 06:01:23 PM PDT 24
Finished Jul 14 06:01:29 PM PDT 24
Peak memory 239424 kb
Host smart-5aecdc64-720b-4dca-8d60-0af79250a862
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044865746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
4044865746
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2117705729
Short name T736
Test name
Test status
Simulation time 4589997383 ps
CPU time 221.2 seconds
Started Jul 14 06:01:17 PM PDT 24
Finished Jul 14 06:04:59 PM PDT 24
Peak memory 967432 kb
Host smart-6b7859c5-8b3d-4507-b528-1a1aa0a69656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117705729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2117705729
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3822700615
Short name T1210
Test name
Test status
Simulation time 867168602 ps
CPU time 4.05 seconds
Started Jul 14 06:01:33 PM PDT 24
Finished Jul 14 06:01:37 PM PDT 24
Peak memory 205492 kb
Host smart-a8f80ba3-75d0-4226-bddc-f4e0a75f8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822700615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3822700615
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2646218649
Short name T492
Test name
Test status
Simulation time 149409464 ps
CPU time 2.11 seconds
Started Jul 14 06:01:23 PM PDT 24
Finished Jul 14 06:01:25 PM PDT 24
Peak memory 213620 kb
Host smart-c4d1bfe0-ec03-4d46-86be-2bdf1cd8ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646218649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2646218649
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.133703953
Short name T135
Test name
Test status
Simulation time 36351489 ps
CPU time 0.67 seconds
Started Jul 14 06:01:14 PM PDT 24
Finished Jul 14 06:01:15 PM PDT 24
Peak memory 205208 kb
Host smart-ac863511-fc81-4728-85c2-a0cb832781f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133703953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.133703953
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3298931498
Short name T1286
Test name
Test status
Simulation time 49839326290 ps
CPU time 530.09 seconds
Started Jul 14 06:01:24 PM PDT 24
Finished Jul 14 06:10:15 PM PDT 24
Peak memory 205492 kb
Host smart-a7d86c90-dba2-46d9-b070-5c816387ca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298931498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3298931498
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.3269109985
Short name T855
Test name
Test status
Simulation time 307876031 ps
CPU time 1.29 seconds
Started Jul 14 06:01:21 PM PDT 24
Finished Jul 14 06:01:23 PM PDT 24
Peak memory 205464 kb
Host smart-24de19cc-8348-4e31-aff4-0997e06a95fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269109985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3269109985
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1987117904
Short name T1259
Test name
Test status
Simulation time 4005282096 ps
CPU time 98.58 seconds
Started Jul 14 06:01:16 PM PDT 24
Finished Jul 14 06:02:56 PM PDT 24
Peak memory 382204 kb
Host smart-ade0e2b6-2f85-49c8-8f72-ca7eb03ee413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987117904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1987117904
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.948699145
Short name T743
Test name
Test status
Simulation time 3568669087 ps
CPU time 43.67 seconds
Started Jul 14 06:01:22 PM PDT 24
Finished Jul 14 06:02:06 PM PDT 24
Peak memory 213708 kb
Host smart-07d5d0b8-6987-4fa6-9c6d-0a6468588f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948699145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.948699145
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2132521465
Short name T176
Test name
Test status
Simulation time 68016890 ps
CPU time 0.94 seconds
Started Jul 14 06:01:29 PM PDT 24
Finished Jul 14 06:01:31 PM PDT 24
Peak memory 223892 kb
Host smart-7ca7b3a3-974e-44c0-88ea-256c3d5042b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132521465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2132521465
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1405672622
Short name T907
Test name
Test status
Simulation time 679047011 ps
CPU time 3.59 seconds
Started Jul 14 06:01:21 PM PDT 24
Finished Jul 14 06:01:25 PM PDT 24
Peak memory 213796 kb
Host smart-9ee80ff4-4114-4e46-adb0-bc9042cbb836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405672622 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1405672622
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2705649540
Short name T811
Test name
Test status
Simulation time 374423507 ps
CPU time 1.54 seconds
Started Jul 14 06:01:22 PM PDT 24
Finished Jul 14 06:01:24 PM PDT 24
Peak memory 213796 kb
Host smart-cee37d3b-b1fc-4531-9dd4-0fecb4bfc841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705649540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2705649540
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2419420125
Short name T1005
Test name
Test status
Simulation time 238994749 ps
CPU time 1.53 seconds
Started Jul 14 06:01:26 PM PDT 24
Finished Jul 14 06:01:28 PM PDT 24
Peak memory 208144 kb
Host smart-7e58a197-f00b-4565-b848-c992a7fd8e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419420125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2419420125
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.1200163606
Short name T382
Test name
Test status
Simulation time 863541303 ps
CPU time 2.47 seconds
Started Jul 14 06:01:28 PM PDT 24
Finished Jul 14 06:01:32 PM PDT 24
Peak memory 205632 kb
Host smart-92c393ca-036a-4efd-961a-f5d659a30e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200163606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.1200163606
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.3157141446
Short name T1133
Test name
Test status
Simulation time 569547336 ps
CPU time 1.49 seconds
Started Jul 14 06:01:30 PM PDT 24
Finished Jul 14 06:01:32 PM PDT 24
Peak memory 205424 kb
Host smart-2d32615a-6521-4f3f-a461-49660563ad21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157141446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.3157141446
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1676280917
Short name T1181
Test name
Test status
Simulation time 384735473 ps
CPU time 2.38 seconds
Started Jul 14 06:01:22 PM PDT 24
Finished Jul 14 06:01:25 PM PDT 24
Peak memory 213768 kb
Host smart-039f47b3-d632-460a-80a6-f44ecc166a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676280917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1676280917
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2938551640
Short name T544
Test name
Test status
Simulation time 1434328250 ps
CPU time 8.02 seconds
Started Jul 14 06:01:26 PM PDT 24
Finished Jul 14 06:01:35 PM PDT 24
Peak memory 221996 kb
Host smart-6586f4ee-fea9-4510-b100-9d9768c1f55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938551640 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2938551640
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1676222648
Short name T285
Test name
Test status
Simulation time 29907641153 ps
CPU time 49.06 seconds
Started Jul 14 06:01:20 PM PDT 24
Finished Jul 14 06:02:10 PM PDT 24
Peak memory 920004 kb
Host smart-bd9f0745-e856-4a46-a7b5-6b43e1aba517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676222648 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1676222648
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.4042312855
Short name T936
Test name
Test status
Simulation time 2139472148 ps
CPU time 2.96 seconds
Started Jul 14 06:01:31 PM PDT 24
Finished Jul 14 06:01:34 PM PDT 24
Peak memory 213796 kb
Host smart-474b27da-a3ce-4565-a61f-046f086aef23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042312855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.4042312855
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.1591243952
Short name T1689
Test name
Test status
Simulation time 2033005453 ps
CPU time 2.63 seconds
Started Jul 14 06:01:29 PM PDT 24
Finished Jul 14 06:01:32 PM PDT 24
Peak memory 205616 kb
Host smart-8f66877a-f634-4190-9bb9-7e7cb7195b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591243952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.1591243952
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.1558968055
Short name T818
Test name
Test status
Simulation time 138699879 ps
CPU time 1.35 seconds
Started Jul 14 06:01:32 PM PDT 24
Finished Jul 14 06:01:34 PM PDT 24
Peak memory 222400 kb
Host smart-d327f2b8-6c94-4165-86d5-f18694a07ad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558968055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_txstretch.1558968055
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.3378604127
Short name T1139
Test name
Test status
Simulation time 11063610921 ps
CPU time 4.19 seconds
Started Jul 14 06:01:22 PM PDT 24
Finished Jul 14 06:01:27 PM PDT 24
Peak memory 219124 kb
Host smart-2b4a048a-2684-4c9b-a92b-43642c557053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378604127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.3378604127
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.956908473
Short name T1092
Test name
Test status
Simulation time 1846194068 ps
CPU time 2.27 seconds
Started Jul 14 06:01:32 PM PDT 24
Finished Jul 14 06:01:35 PM PDT 24
Peak memory 205424 kb
Host smart-07377fe7-0483-45f5-9084-b1e2bec47d85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956908473 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_smbus_maxlen.956908473
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3957294266
Short name T1326
Test name
Test status
Simulation time 5222448445 ps
CPU time 19.42 seconds
Started Jul 14 06:01:23 PM PDT 24
Finished Jul 14 06:01:43 PM PDT 24
Peak memory 213820 kb
Host smart-951b4403-77f2-4bdd-80ec-e53d2dd53aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957294266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3957294266
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2912327754
Short name T486
Test name
Test status
Simulation time 33494764083 ps
CPU time 233.5 seconds
Started Jul 14 06:01:26 PM PDT 24
Finished Jul 14 06:05:20 PM PDT 24
Peak memory 1862480 kb
Host smart-1acf9af6-73d8-49d5-91d5-4e3689d01d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912327754 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2912327754
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.4064417307
Short name T440
Test name
Test status
Simulation time 5266141396 ps
CPU time 62.11 seconds
Started Jul 14 06:01:27 PM PDT 24
Finished Jul 14 06:02:29 PM PDT 24
Peak memory 216216 kb
Host smart-a3aa46a8-f761-4add-b6b0-d5d58b5f4a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064417307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.4064417307
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1089132769
Short name T315
Test name
Test status
Simulation time 14997895682 ps
CPU time 24.41 seconds
Started Jul 14 06:01:24 PM PDT 24
Finished Jul 14 06:01:49 PM PDT 24
Peak memory 205644 kb
Host smart-ce8666d4-f749-4cc4-b51d-cf784478a7d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089132769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1089132769
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.953814202
Short name T1343
Test name
Test status
Simulation time 3801798921 ps
CPU time 156.86 seconds
Started Jul 14 06:01:23 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 877064 kb
Host smart-25d61e5d-dc70-4937-968b-bd8dc07e15f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953814202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.953814202
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1048994460
Short name T489
Test name
Test status
Simulation time 1210978716 ps
CPU time 6.45 seconds
Started Jul 14 06:01:24 PM PDT 24
Finished Jul 14 06:01:31 PM PDT 24
Peak memory 213780 kb
Host smart-86ed47d6-4356-4d77-abb7-137579501a8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048994460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1048994460
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.2705031661
Short name T54
Test name
Test status
Simulation time 198404965 ps
CPU time 2.83 seconds
Started Jul 14 06:01:29 PM PDT 24
Finished Jul 14 06:01:32 PM PDT 24
Peak memory 205516 kb
Host smart-4a61c533-34c7-41c0-aba1-5ed7c6d3036b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705031661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2705031661
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1637226860
Short name T168
Test name
Test status
Simulation time 18661941 ps
CPU time 0.65 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:08:15 PM PDT 24
Peak memory 204888 kb
Host smart-17bb5894-5951-480f-8722-b5eba5b7ebfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637226860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1637226860
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2102439889
Short name T1414
Test name
Test status
Simulation time 49671276 ps
CPU time 1.82 seconds
Started Jul 14 06:08:11 PM PDT 24
Finished Jul 14 06:08:14 PM PDT 24
Peak memory 213788 kb
Host smart-f1dfbea6-b97f-4d9f-8a59-60fb651075e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102439889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2102439889
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2117973256
Short name T551
Test name
Test status
Simulation time 248767470 ps
CPU time 12.24 seconds
Started Jul 14 06:08:09 PM PDT 24
Finished Jul 14 06:08:22 PM PDT 24
Peak memory 239704 kb
Host smart-4f3e1f59-b698-4258-b860-6074336ac0ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117973256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2117973256
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2782191667
Short name T122
Test name
Test status
Simulation time 6716133321 ps
CPU time 113.3 seconds
Started Jul 14 06:08:12 PM PDT 24
Finished Jul 14 06:10:06 PM PDT 24
Peak memory 663660 kb
Host smart-9dc130ef-f6a0-4b9c-b1d3-1c64b0f810ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782191667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2782191667
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.4062890941
Short name T378
Test name
Test status
Simulation time 4438935640 ps
CPU time 155.97 seconds
Started Jul 14 06:08:10 PM PDT 24
Finished Jul 14 06:10:47 PM PDT 24
Peak memory 684532 kb
Host smart-75d45781-910d-436d-aec4-f79ada6fbf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062890941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.4062890941
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3568637150
Short name T1473
Test name
Test status
Simulation time 295703103 ps
CPU time 1.02 seconds
Started Jul 14 06:08:11 PM PDT 24
Finished Jul 14 06:08:13 PM PDT 24
Peak memory 205224 kb
Host smart-a633b60d-daec-468a-8962-b9e8eda2dd78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568637150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3568637150
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2292987759
Short name T1173
Test name
Test status
Simulation time 396371942 ps
CPU time 2.89 seconds
Started Jul 14 06:08:07 PM PDT 24
Finished Jul 14 06:08:11 PM PDT 24
Peak memory 205396 kb
Host smart-ab1485c6-fd19-411d-a9d3-c735af1b6615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292987759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2292987759
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.4079232893
Short name T1096
Test name
Test status
Simulation time 21336061242 ps
CPU time 158.54 seconds
Started Jul 14 06:08:06 PM PDT 24
Finished Jul 14 06:10:45 PM PDT 24
Peak memory 1491812 kb
Host smart-5943b9e9-fb51-4fa3-8ac6-08afba1cc146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079232893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4079232893
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.4197720975
Short name T243
Test name
Test status
Simulation time 534899262 ps
CPU time 21.86 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:38 PM PDT 24
Peak memory 205520 kb
Host smart-66a4a1ab-cc59-4b16-ad1b-79b2b169fb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197720975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.4197720975
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.3564581121
Short name T1441
Test name
Test status
Simulation time 47175643 ps
CPU time 0.7 seconds
Started Jul 14 06:08:10 PM PDT 24
Finished Jul 14 06:08:12 PM PDT 24
Peak memory 205160 kb
Host smart-f2b94cf1-d34f-45ac-9b0c-3ce6050c360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564581121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3564581121
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3246301679
Short name T1312
Test name
Test status
Simulation time 13178334127 ps
CPU time 595.55 seconds
Started Jul 14 06:08:09 PM PDT 24
Finished Jul 14 06:18:05 PM PDT 24
Peak memory 2520420 kb
Host smart-1a4d1138-ec7a-4202-95b5-4d13620f06ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246301679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3246301679
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1511997650
Short name T475
Test name
Test status
Simulation time 221700851 ps
CPU time 4.72 seconds
Started Jul 14 06:08:08 PM PDT 24
Finished Jul 14 06:08:13 PM PDT 24
Peak memory 239096 kb
Host smart-c0fc4d43-231d-44ec-8198-50c712ed0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511997650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1511997650
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.4217597971
Short name T312
Test name
Test status
Simulation time 2623094675 ps
CPU time 66.1 seconds
Started Jul 14 06:08:10 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 297920 kb
Host smart-a2c7a427-c4cb-4d56-81fc-53c656fda2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217597971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.4217597971
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.645032979
Short name T1367
Test name
Test status
Simulation time 7401570055 ps
CPU time 15.59 seconds
Started Jul 14 06:08:11 PM PDT 24
Finished Jul 14 06:08:28 PM PDT 24
Peak memory 215492 kb
Host smart-68574031-16e4-4479-ab58-4d53b0de6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645032979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.645032979
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3269425816
Short name T1298
Test name
Test status
Simulation time 2170834247 ps
CPU time 6.21 seconds
Started Jul 14 06:08:16 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 221984 kb
Host smart-83684a48-ab23-4d66-8d1b-f8a9b13c3f4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269425816 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3269425816
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.456142332
Short name T278
Test name
Test status
Simulation time 246260433 ps
CPU time 1.66 seconds
Started Jul 14 06:08:18 PM PDT 24
Finished Jul 14 06:08:21 PM PDT 24
Peak memory 205616 kb
Host smart-a1045fa1-8bcc-438a-82c3-91924a5ab949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456142332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.456142332
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3236432414
Short name T710
Test name
Test status
Simulation time 673185944 ps
CPU time 1.38 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:08:15 PM PDT 24
Peak memory 205464 kb
Host smart-0eee71a4-0b3e-4dfc-b81f-727f831165a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236432414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3236432414
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.468437832
Short name T1724
Test name
Test status
Simulation time 2962688307 ps
CPU time 2.87 seconds
Started Jul 14 06:08:14 PM PDT 24
Finished Jul 14 06:08:18 PM PDT 24
Peak memory 205660 kb
Host smart-b1041a1a-2259-4f81-99af-142b5c0c77a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468437832 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.468437832
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.2129399663
Short name T658
Test name
Test status
Simulation time 132097741 ps
CPU time 1.55 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:08:16 PM PDT 24
Peak memory 205416 kb
Host smart-4883d14d-d8a8-4f9a-9fa2-80307f1ed207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129399663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.2129399663
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.4254712623
Short name T1476
Test name
Test status
Simulation time 599151124 ps
CPU time 3.82 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:08:19 PM PDT 24
Peak memory 213828 kb
Host smart-2fa50c5a-d363-494c-9584-9848f35401ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254712623 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.4254712623
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4081159350
Short name T1004
Test name
Test status
Simulation time 21931350217 ps
CPU time 450.41 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:15:44 PM PDT 24
Peak memory 3867112 kb
Host smart-05012e59-d71f-46ea-8844-9cdd02457ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081159350 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4081159350
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.2460907987
Short name T144
Test name
Test status
Simulation time 1136079528 ps
CPU time 2.97 seconds
Started Jul 14 06:08:18 PM PDT 24
Finished Jul 14 06:08:22 PM PDT 24
Peak memory 213848 kb
Host smart-9f8bb370-80f6-4595-8bb5-71c25e2612ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460907987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.2460907987
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.4200876420
Short name T579
Test name
Test status
Simulation time 1062377827 ps
CPU time 2.73 seconds
Started Jul 14 06:08:14 PM PDT 24
Finished Jul 14 06:08:18 PM PDT 24
Peak memory 205616 kb
Host smart-2c4c7125-59b1-43eb-8873-d223f86d38be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200876420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.4200876420
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_txstretch.3454997867
Short name T731
Test name
Test status
Simulation time 268015924 ps
CPU time 1.4 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:17 PM PDT 24
Peak memory 222392 kb
Host smart-c9ffe513-de0b-478c-8796-20db7b1c5ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454997867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_nack_txstretch.3454997867
Directory /workspace/40.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/40.i2c_target_perf.1554318400
Short name T1443
Test name
Test status
Simulation time 514155118 ps
CPU time 3.63 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:19 PM PDT 24
Peak memory 213900 kb
Host smart-e3f28b1e-d224-4943-9440-26b3e238d5a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554318400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.1554318400
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.4130490617
Short name T1218
Test name
Test status
Simulation time 600205387 ps
CPU time 1.95 seconds
Started Jul 14 06:08:17 PM PDT 24
Finished Jul 14 06:08:20 PM PDT 24
Peak memory 205364 kb
Host smart-8bbe195b-4696-41c1-b510-0a61b7b792b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130490617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.4130490617
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.880504219
Short name T1228
Test name
Test status
Simulation time 856030048 ps
CPU time 12.83 seconds
Started Jul 14 06:08:11 PM PDT 24
Finished Jul 14 06:08:25 PM PDT 24
Peak memory 213752 kb
Host smart-84bdf134-e2fd-4013-8b83-29fee8904b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880504219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.880504219
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.911251911
Short name T542
Test name
Test status
Simulation time 33923752336 ps
CPU time 667.31 seconds
Started Jul 14 06:08:12 PM PDT 24
Finished Jul 14 06:19:21 PM PDT 24
Peak memory 3602824 kb
Host smart-087db45a-baaf-4e9d-ab35-9985a1a08e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911251911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_stress_all.911251911
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3711453530
Short name T1112
Test name
Test status
Simulation time 980620727 ps
CPU time 9 seconds
Started Jul 14 06:08:14 PM PDT 24
Finished Jul 14 06:08:24 PM PDT 24
Peak memory 214080 kb
Host smart-4497bce8-7b90-4c83-bd9a-4c2a3e42199b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711453530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3711453530
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.635434032
Short name T970
Test name
Test status
Simulation time 36776662439 ps
CPU time 484.31 seconds
Started Jul 14 06:08:17 PM PDT 24
Finished Jul 14 06:16:23 PM PDT 24
Peak memory 4378800 kb
Host smart-744edb93-38d0-4dd7-8cfe-6185bc50d679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635434032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.635434032
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1017110386
Short name T705
Test name
Test status
Simulation time 2371789618 ps
CPU time 8.6 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:25 PM PDT 24
Peak memory 304172 kb
Host smart-681ce61c-9581-4018-a094-42dab9515945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017110386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1017110386
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1703486812
Short name T310
Test name
Test status
Simulation time 5624996461 ps
CPU time 7.14 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 221992 kb
Host smart-d489b914-e5d2-4e89-ad5d-f33205afb238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703486812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1703486812
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.987222167
Short name T383
Test name
Test status
Simulation time 121254433 ps
CPU time 2.67 seconds
Started Jul 14 06:08:15 PM PDT 24
Finished Jul 14 06:08:18 PM PDT 24
Peak memory 205564 kb
Host smart-19838ad4-d238-4621-8643-f1f50130d032
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987222167 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.987222167
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.686465298
Short name T1510
Test name
Test status
Simulation time 32367792 ps
CPU time 0.63 seconds
Started Jul 14 06:08:28 PM PDT 24
Finished Jul 14 06:08:30 PM PDT 24
Peak memory 204716 kb
Host smart-7994a4a4-ef77-423c-b438-11d4d0fcbb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686465298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.686465298
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3064362264
Short name T612
Test name
Test status
Simulation time 119945042 ps
CPU time 2.68 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:24 PM PDT 24
Peak memory 213720 kb
Host smart-c64ab11a-609f-4676-b1b0-a9219d24e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064362264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3064362264
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.81280355
Short name T1132
Test name
Test status
Simulation time 1882754324 ps
CPU time 6.12 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:27 PM PDT 24
Peak memory 259088 kb
Host smart-05c9083b-4fab-457a-b189-ece1d0c3278b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81280355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty
.81280355
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2914321722
Short name T889
Test name
Test status
Simulation time 15701427266 ps
CPU time 144.31 seconds
Started Jul 14 06:08:19 PM PDT 24
Finished Jul 14 06:10:44 PM PDT 24
Peak memory 365664 kb
Host smart-754f1db2-126f-4c26-b908-b93951e71157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914321722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2914321722
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1131299359
Short name T1450
Test name
Test status
Simulation time 1329920915 ps
CPU time 87.56 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:09:49 PM PDT 24
Peak memory 523220 kb
Host smart-f5bbb6e6-d06a-4350-a395-4ad535fce6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131299359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1131299359
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.47188988
Short name T83
Test name
Test status
Simulation time 264391886 ps
CPU time 1.12 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 205252 kb
Host smart-d0e4786b-8519-477d-935f-3b330a3d2bef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47188988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt
.47188988
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.550302427
Short name T642
Test name
Test status
Simulation time 219468307 ps
CPU time 2.53 seconds
Started Jul 14 06:08:18 PM PDT 24
Finished Jul 14 06:08:21 PM PDT 24
Peak memory 205420 kb
Host smart-f2b915a9-ca4c-4ab0-b884-b31d88711851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550302427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
550302427
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.4004919925
Short name T160
Test name
Test status
Simulation time 5628196364 ps
CPU time 183.09 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:11:25 PM PDT 24
Peak memory 894472 kb
Host smart-ff39b312-d2b2-4b84-9359-87e19fd8da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004919925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.4004919925
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3811230189
Short name T1225
Test name
Test status
Simulation time 137665494 ps
CPU time 2.2 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:08:33 PM PDT 24
Peak memory 205456 kb
Host smart-27f73ae7-0460-4b07-ae3b-2d5cd865164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811230189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3811230189
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.3762774327
Short name T379
Test name
Test status
Simulation time 97678301 ps
CPU time 0.72 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:08:22 PM PDT 24
Peak memory 205196 kb
Host smart-fa16a2a5-e991-423f-96aa-ff2c2f98736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762774327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3762774327
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3820735952
Short name T38
Test name
Test status
Simulation time 18399579284 ps
CPU time 479.29 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:16:29 PM PDT 24
Peak memory 667552 kb
Host smart-3a7166a2-fc4a-4466-ab1d-c138129a8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820735952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3820735952
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3978868004
Short name T1232
Test name
Test status
Simulation time 5953997734 ps
CPU time 124.14 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:10:26 PM PDT 24
Peak memory 205248 kb
Host smart-6a3fdd1d-1df5-4858-a45c-5d62db4402cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978868004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3978868004
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.108420411
Short name T466
Test name
Test status
Simulation time 3652662927 ps
CPU time 83.6 seconds
Started Jul 14 06:08:13 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 327276 kb
Host smart-2ec5f0fb-aca2-4aae-9568-fdcb5aef0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108420411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.108420411
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.164583139
Short name T1646
Test name
Test status
Simulation time 1276427036 ps
CPU time 9.07 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:08:39 PM PDT 24
Peak memory 220960 kb
Host smart-d8957e9f-9dbb-42cb-b4b3-c8cd5ff2714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164583139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.164583139
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3186726769
Short name T61
Test name
Test status
Simulation time 2876948147 ps
CPU time 4.01 seconds
Started Jul 14 06:08:30 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 213864 kb
Host smart-48a5170f-a8f8-4945-b53c-74095b633917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186726769 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3186726769
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.361466160
Short name T148
Test name
Test status
Simulation time 275396273 ps
CPU time 1.51 seconds
Started Jul 14 06:08:19 PM PDT 24
Finished Jul 14 06:08:21 PM PDT 24
Peak memory 205820 kb
Host smart-bcf186cc-1da3-4afb-8ba5-e4d8aa475711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361466160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.361466160
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3899665021
Short name T1721
Test name
Test status
Simulation time 325779383 ps
CPU time 1.33 seconds
Started Jul 14 06:08:22 PM PDT 24
Finished Jul 14 06:08:24 PM PDT 24
Peak memory 205640 kb
Host smart-692ad55f-2409-42e4-b698-8a8e6fea31ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899665021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3899665021
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1902464181
Short name T447
Test name
Test status
Simulation time 502540289 ps
CPU time 2.82 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:08:33 PM PDT 24
Peak memory 205616 kb
Host smart-cbd885d3-22a1-4471-9eec-917597417851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902464181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1902464181
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3911120766
Short name T989
Test name
Test status
Simulation time 252453474 ps
CPU time 1.44 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 205444 kb
Host smart-f8e90636-f34a-4d7b-8abc-41e5422ac6f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911120766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3911120766
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1263580296
Short name T361
Test name
Test status
Simulation time 5641010699 ps
CPU time 8.6 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:08:30 PM PDT 24
Peak memory 231952 kb
Host smart-01446cac-605e-4652-a572-bc89f2cec33a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263580296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1263580296
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3555414242
Short name T1570
Test name
Test status
Simulation time 3746661463 ps
CPU time 31.16 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:52 PM PDT 24
Peak memory 1029088 kb
Host smart-c3bd26ee-f02b-4d79-aee7-b2d4a82270ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555414242 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3555414242
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.2822954109
Short name T1244
Test name
Test status
Simulation time 520876429 ps
CPU time 2.71 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 213824 kb
Host smart-a88efab6-ddb7-484d-8f9a-2c5909efb55f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822954109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.2822954109
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.4034550136
Short name T1358
Test name
Test status
Simulation time 1889145812 ps
CPU time 2.26 seconds
Started Jul 14 06:08:25 PM PDT 24
Finished Jul 14 06:08:27 PM PDT 24
Peak memory 205620 kb
Host smart-dccd05c7-6c7a-45b6-867a-66ef97bd8c8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034550136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.4034550136
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_txstretch.4172981527
Short name T150
Test name
Test status
Simulation time 548110840 ps
CPU time 1.37 seconds
Started Jul 14 06:08:26 PM PDT 24
Finished Jul 14 06:08:28 PM PDT 24
Peak memory 222352 kb
Host smart-fadc9560-6fb3-4da7-9dd9-6dff64bad2fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172981527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_txstretch.4172981527
Directory /workspace/41.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/41.i2c_target_perf.2355385686
Short name T913
Test name
Test status
Simulation time 907224813 ps
CPU time 5.68 seconds
Started Jul 14 06:08:23 PM PDT 24
Finished Jul 14 06:08:29 PM PDT 24
Peak memory 221080 kb
Host smart-16f6d31e-f364-4bea-a338-8842b326f4cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355385686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.2355385686
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.3461901005
Short name T845
Test name
Test status
Simulation time 514564267 ps
CPU time 2.36 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 205356 kb
Host smart-ff9386eb-758c-4d74-bad9-2a05ebb75509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461901005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.3461901005
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1597363035
Short name T284
Test name
Test status
Simulation time 3216874546 ps
CPU time 10.52 seconds
Started Jul 14 06:08:23 PM PDT 24
Finished Jul 14 06:08:34 PM PDT 24
Peak memory 213852 kb
Host smart-b709ddd9-15c4-44ff-a8d7-f066657e296b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597363035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1597363035
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.1190304587
Short name T364
Test name
Test status
Simulation time 9723541575 ps
CPU time 63.32 seconds
Started Jul 14 06:08:18 PM PDT 24
Finished Jul 14 06:09:22 PM PDT 24
Peak memory 295464 kb
Host smart-af8a79b6-6f67-47ee-b54c-30cf3747c6d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190304587 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.1190304587
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.924013999
Short name T518
Test name
Test status
Simulation time 935288723 ps
CPU time 37.32 seconds
Started Jul 14 06:08:20 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 213848 kb
Host smart-9bf19938-0b17-46ee-8808-3bb077889b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924013999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.924013999
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3845899110
Short name T1159
Test name
Test status
Simulation time 53967495036 ps
CPU time 159.49 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:11:02 PM PDT 24
Peak memory 1812944 kb
Host smart-9f9c1acb-e0eb-4788-aa83-394ffc8ecb23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845899110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3845899110
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.4019395961
Short name T764
Test name
Test status
Simulation time 1824734767 ps
CPU time 16.97 seconds
Started Jul 14 06:08:21 PM PDT 24
Finished Jul 14 06:08:39 PM PDT 24
Peak memory 285576 kb
Host smart-39ab2417-393f-489d-b953-3c1ac6ab7962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019395961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.4019395961
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1956771225
Short name T866
Test name
Test status
Simulation time 5940139338 ps
CPU time 8.3 seconds
Started Jul 14 06:08:19 PM PDT 24
Finished Jul 14 06:08:28 PM PDT 24
Peak memory 230116 kb
Host smart-957e0a20-5b96-4048-abce-b08ad07903ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956771225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1956771225
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.3542652708
Short name T450
Test name
Test status
Simulation time 115514984 ps
CPU time 2.6 seconds
Started Jul 14 06:08:22 PM PDT 24
Finished Jul 14 06:08:26 PM PDT 24
Peak memory 205540 kb
Host smart-0e1a6797-20ef-40fb-ac91-b430965e2671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542652708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.3542652708
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.896082321
Short name T1104
Test name
Test status
Simulation time 38050570 ps
CPU time 0.62 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:34 PM PDT 24
Peak memory 204736 kb
Host smart-5859363c-58e7-4020-bba2-6d3059def51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896082321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.896082321
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2601103244
Short name T957
Test name
Test status
Simulation time 326665939 ps
CPU time 1.44 seconds
Started Jul 14 06:08:28 PM PDT 24
Finished Jul 14 06:08:30 PM PDT 24
Peak memory 213736 kb
Host smart-eb0c4353-9079-4059-9eb4-719ffc25314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601103244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2601103244
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1097281661
Short name T744
Test name
Test status
Simulation time 353621387 ps
CPU time 17.88 seconds
Started Jul 14 06:08:27 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 279728 kb
Host smart-0c2ff7ad-ff52-4747-98ca-a80d3b914fcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097281661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1097281661
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.30444723
Short name T1597
Test name
Test status
Simulation time 24420393440 ps
CPU time 196.9 seconds
Started Jul 14 06:08:31 PM PDT 24
Finished Jul 14 06:11:48 PM PDT 24
Peak memory 400728 kb
Host smart-ae69b322-131b-43ce-a248-095d0c1d1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30444723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.30444723
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3397967967
Short name T1683
Test name
Test status
Simulation time 1831434902 ps
CPU time 60.97 seconds
Started Jul 14 06:08:27 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 648588 kb
Host smart-15a769b6-a3bd-457b-8700-2ebc8e293cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397967967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3397967967
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3082940955
Short name T1332
Test name
Test status
Simulation time 233105379 ps
CPU time 1.02 seconds
Started Jul 14 06:08:28 PM PDT 24
Finished Jul 14 06:08:29 PM PDT 24
Peak memory 205216 kb
Host smart-31004726-dbcf-4932-9395-7ade94bf849b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082940955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3082940955
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1085824968
Short name T900
Test name
Test status
Simulation time 173748744 ps
CPU time 9.22 seconds
Started Jul 14 06:08:26 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 234428 kb
Host smart-e42c385d-33d7-4599-9b00-b76875f41b5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085824968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1085824968
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3358135933
Short name T625
Test name
Test status
Simulation time 12904750824 ps
CPU time 190.36 seconds
Started Jul 14 06:08:27 PM PDT 24
Finished Jul 14 06:11:38 PM PDT 24
Peak memory 912092 kb
Host smart-6586c676-2f4e-4173-892a-7f996ae683cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358135933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3358135933
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.304672988
Short name T1467
Test name
Test status
Simulation time 953101670 ps
CPU time 18.94 seconds
Started Jul 14 06:08:35 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 205496 kb
Host smart-72a68225-1a78-41fc-a881-b54364db6b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304672988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.304672988
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.3387053484
Short name T1271
Test name
Test status
Simulation time 85776348 ps
CPU time 0.67 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:08:31 PM PDT 24
Peak memory 205172 kb
Host smart-a456fe80-d0d7-41ee-a4d4-a661b40318bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387053484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3387053484
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.735049753
Short name T785
Test name
Test status
Simulation time 5057460177 ps
CPU time 28.99 seconds
Started Jul 14 06:08:26 PM PDT 24
Finished Jul 14 06:08:55 PM PDT 24
Peak memory 366420 kb
Host smart-be426582-2dfc-4a3c-a019-324175d0cc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735049753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.735049753
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.740427163
Short name T1175
Test name
Test status
Simulation time 47138369 ps
CPU time 1.27 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:08:32 PM PDT 24
Peak memory 223796 kb
Host smart-a9827c0f-f124-4f87-a096-2c5d17134310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740427163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.740427163
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2838511919
Short name T204
Test name
Test status
Simulation time 1270993893 ps
CPU time 58.04 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 300120 kb
Host smart-16e1515d-f15d-4cd3-bf50-b3c3f2e18b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838511919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2838511919
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1757843281
Short name T298
Test name
Test status
Simulation time 1021713633 ps
CPU time 16.59 seconds
Started Jul 14 06:08:25 PM PDT 24
Finished Jul 14 06:08:42 PM PDT 24
Peak memory 229644 kb
Host smart-665d1d11-edb4-4f2a-a497-544be551af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757843281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1757843281
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.650405789
Short name T630
Test name
Test status
Simulation time 4019570705 ps
CPU time 5.51 seconds
Started Jul 14 06:08:35 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 213804 kb
Host smart-9a8df30e-a2c0-4f58-89cf-4c8c43553d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650405789 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.650405789
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3520530602
Short name T1035
Test name
Test status
Simulation time 316586973 ps
CPU time 0.86 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 205416 kb
Host smart-69339bdd-dd07-4f86-bbc5-d48319680ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520530602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3520530602
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.4147044685
Short name T330
Test name
Test status
Simulation time 706644015 ps
CPU time 1.35 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 205628 kb
Host smart-d89b3fb9-7a98-433d-9050-1967e2ccc402
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147044685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.4147044685
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.3361733579
Short name T1519
Test name
Test status
Simulation time 67993617 ps
CPU time 0.87 seconds
Started Jul 14 06:08:34 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 205336 kb
Host smart-5f3340dc-78ba-4193-8cf9-80d4d56026fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361733579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.3361733579
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3615703746
Short name T654
Test name
Test status
Simulation time 126410692 ps
CPU time 0.86 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 205432 kb
Host smart-4dd3247c-fcf8-4679-9bcc-349d5e15f78c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615703746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3615703746
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1195700860
Short name T674
Test name
Test status
Simulation time 800768084 ps
CPU time 4.22 seconds
Started Jul 14 06:08:25 PM PDT 24
Finished Jul 14 06:08:30 PM PDT 24
Peak memory 221908 kb
Host smart-1c4dd839-a171-4dbf-aadf-333ff35a69b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195700860 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1195700860
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1559666632
Short name T58
Test name
Test status
Simulation time 13710851864 ps
CPU time 142.33 seconds
Started Jul 14 06:08:28 PM PDT 24
Finished Jul 14 06:10:51 PM PDT 24
Peak memory 1803136 kb
Host smart-6e1fdb71-a96e-4a4b-9b41-8a3e8df17c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559666632 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1559666632
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.1287773539
Short name T747
Test name
Test status
Simulation time 3441538531 ps
CPU time 3.09 seconds
Started Jul 14 06:08:32 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 213800 kb
Host smart-7158776b-4faf-4c70-855b-f4a5807fab1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287773539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.1287773539
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.3473094363
Short name T1385
Test name
Test status
Simulation time 2072870148 ps
CPU time 2.56 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:37 PM PDT 24
Peak memory 205596 kb
Host smart-9bbb35ab-b2c1-4a10-918f-b57bc15117e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473094363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.3473094363
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.3323394646
Short name T1496
Test name
Test status
Simulation time 876747342 ps
CPU time 6.89 seconds
Started Jul 14 06:08:35 PM PDT 24
Finished Jul 14 06:08:43 PM PDT 24
Peak memory 220816 kb
Host smart-dc06cedc-3765-4df9-b1e5-eb4bcd85479f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323394646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.3323394646
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.3642055159
Short name T833
Test name
Test status
Simulation time 441198589 ps
CPU time 2.14 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 205380 kb
Host smart-1683b937-a52b-4500-bd77-6ac5231fe435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642055159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_smbus_maxlen.3642055159
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.937741845
Short name T1294
Test name
Test status
Simulation time 2054475104 ps
CPU time 33.34 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 213728 kb
Host smart-f77807f1-9ad6-4512-8d14-a6262d69e45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937741845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.937741845
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.3551189208
Short name T778
Test name
Test status
Simulation time 27916547665 ps
CPU time 631.45 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:19:05 PM PDT 24
Peak memory 4020916 kb
Host smart-bbd44556-953e-4bc5-9dc2-9bc6f610222f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551189208 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.3551189208
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3348878929
Short name T808
Test name
Test status
Simulation time 1543229005 ps
CPU time 28.49 seconds
Started Jul 14 06:08:28 PM PDT 24
Finished Jul 14 06:08:58 PM PDT 24
Peak memory 230092 kb
Host smart-c0b32517-890a-4bd2-b126-471d3f8e6766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348878929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3348878929
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.159910068
Short name T528
Test name
Test status
Simulation time 28715714108 ps
CPU time 163.73 seconds
Started Jul 14 06:08:27 PM PDT 24
Finished Jul 14 06:11:12 PM PDT 24
Peak memory 2237040 kb
Host smart-6a55c00b-9b6e-4ba9-af87-5af216be56d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159910068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.159910068
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.319189910
Short name T508
Test name
Test status
Simulation time 1950610154 ps
CPU time 31.91 seconds
Started Jul 14 06:08:29 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 408928 kb
Host smart-52756c39-2ec3-49b0-bcc8-ea8b28d974bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319189910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.319189910
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.4212831724
Short name T1581
Test name
Test status
Simulation time 9139637767 ps
CPU time 7.2 seconds
Started Jul 14 06:08:27 PM PDT 24
Finished Jul 14 06:08:35 PM PDT 24
Peak memory 222032 kb
Host smart-45756dde-f3eb-4c1c-bbe9-c724860fa5ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212831724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.4212831724
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.846266995
Short name T637
Test name
Test status
Simulation time 266566222 ps
CPU time 4.11 seconds
Started Jul 14 06:08:34 PM PDT 24
Finished Jul 14 06:08:40 PM PDT 24
Peak memory 205604 kb
Host smart-85070ecb-8580-4dcd-ae9a-1717c8334364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846266995 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.846266995
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1154576727
Short name T1574
Test name
Test status
Simulation time 38464665 ps
CPU time 0.64 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 204708 kb
Host smart-dcbd821f-83ca-4ee4-b7c6-99cf982dcb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154576727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1154576727
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1519482766
Short name T1535
Test name
Test status
Simulation time 212562430 ps
CPU time 1.61 seconds
Started Jul 14 06:08:41 PM PDT 24
Finished Jul 14 06:08:43 PM PDT 24
Peak memory 213720 kb
Host smart-81475257-eb79-45b9-b2a2-39ba1b7d179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519482766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1519482766
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3369437638
Short name T1565
Test name
Test status
Simulation time 2528184349 ps
CPU time 32.85 seconds
Started Jul 14 06:08:40 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 339132 kb
Host smart-cabf6c22-91a7-417b-947e-88ddfdf3c0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369437638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3369437638
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.4051709167
Short name T651
Test name
Test status
Simulation time 27628911899 ps
CPU time 130.79 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:10:54 PM PDT 24
Peak memory 631676 kb
Host smart-5667ee2e-4524-446e-b0ff-fc5d3a04b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051709167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4051709167
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.700843336
Short name T1041
Test name
Test status
Simulation time 1598425819 ps
CPU time 107.07 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:10:21 PM PDT 24
Peak memory 580828 kb
Host smart-12ec3029-5e7c-4e9a-adb2-e6e9eb4d01c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700843336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.700843336
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.905833606
Short name T513
Test name
Test status
Simulation time 94516315 ps
CPU time 0.92 seconds
Started Jul 14 06:08:34 PM PDT 24
Finished Jul 14 06:08:36 PM PDT 24
Peak memory 205248 kb
Host smart-24a6d6b9-a6e0-48db-ba14-fb51adc528eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905833606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.905833606
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1966475247
Short name T1273
Test name
Test status
Simulation time 180752157 ps
CPU time 4.22 seconds
Started Jul 14 06:08:36 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 205444 kb
Host smart-a7bf0ad1-90c3-4bfc-a219-039b55ec827d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966475247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1966475247
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1823082769
Short name T1065
Test name
Test status
Simulation time 10214516447 ps
CPU time 354 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:14:27 PM PDT 24
Peak memory 1371736 kb
Host smart-9c1857a5-cd79-40be-ab02-dc341b4897c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823082769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1823082769
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3391818469
Short name T1637
Test name
Test status
Simulation time 572172072 ps
CPU time 7.37 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:08:50 PM PDT 24
Peak memory 205468 kb
Host smart-3d857d4c-4c1f-4dd9-8b78-1b201a80d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391818469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3391818469
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.2347072739
Short name T152
Test name
Test status
Simulation time 86993151 ps
CPU time 0.71 seconds
Started Jul 14 06:08:34 PM PDT 24
Finished Jul 14 06:08:36 PM PDT 24
Peak memory 205192 kb
Host smart-c352f914-de37-4684-b9f8-6e4b86b405af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347072739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2347072739
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.649148927
Short name T14
Test name
Test status
Simulation time 25635437734 ps
CPU time 205.94 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:12:09 PM PDT 24
Peak memory 234892 kb
Host smart-9d86c00c-d523-4763-926d-e6ed8de84dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649148927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.649148927
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3332183885
Short name T896
Test name
Test status
Simulation time 381279329 ps
CPU time 1.87 seconds
Started Jul 14 06:08:41 PM PDT 24
Finished Jul 14 06:08:43 PM PDT 24
Peak memory 223080 kb
Host smart-536a103c-b7ab-4edf-a37a-be241ca4791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332183885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3332183885
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2192395036
Short name T676
Test name
Test status
Simulation time 4866187086 ps
CPU time 22.76 seconds
Started Jul 14 06:08:33 PM PDT 24
Finished Jul 14 06:08:56 PM PDT 24
Peak memory 298524 kb
Host smart-072176a3-3cfa-4dc9-ab0a-ae48567af5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192395036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2192395036
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3458776051
Short name T115
Test name
Test status
Simulation time 14310940185 ps
CPU time 698.51 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:20:21 PM PDT 24
Peak memory 3031064 kb
Host smart-f37e65f1-cb10-4e9f-966d-011b1e7d8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458776051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3458776051
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1862021658
Short name T624
Test name
Test status
Simulation time 1105545895 ps
CPU time 10.03 seconds
Started Jul 14 06:08:39 PM PDT 24
Finished Jul 14 06:08:50 PM PDT 24
Peak memory 216088 kb
Host smart-1a877780-5d49-4932-96cb-4f62098b1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862021658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1862021658
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.537341672
Short name T712
Test name
Test status
Simulation time 2211436088 ps
CPU time 5.37 seconds
Started Jul 14 06:08:38 PM PDT 24
Finished Jul 14 06:08:44 PM PDT 24
Peak memory 213892 kb
Host smart-3d70c70a-7736-42d3-8f4b-c52af0e2a4fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537341672 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.537341672
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3201457801
Short name T1609
Test name
Test status
Simulation time 707001222 ps
CPU time 1.37 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:08:44 PM PDT 24
Peak memory 208736 kb
Host smart-cb53394b-08c5-471a-a25d-4c80842fce58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201457801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3201457801
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2228028274
Short name T326
Test name
Test status
Simulation time 454060924 ps
CPU time 1.15 seconds
Started Jul 14 06:08:38 PM PDT 24
Finished Jul 14 06:08:40 PM PDT 24
Peak memory 205448 kb
Host smart-f0ce0269-e564-4903-aadf-079d422298c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228028274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2228028274
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2002318390
Short name T821
Test name
Test status
Simulation time 1140642720 ps
CPU time 3.3 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:47 PM PDT 24
Peak memory 205528 kb
Host smart-2c80124f-b7bd-4659-8466-d86138478eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002318390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2002318390
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3353023715
Short name T324
Test name
Test status
Simulation time 3039249883 ps
CPU time 4.23 seconds
Started Jul 14 06:08:40 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 221192 kb
Host smart-cb295fc9-4024-413a-bf2f-7c2b04f5efbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353023715 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3353023715
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3665782680
Short name T809
Test name
Test status
Simulation time 4293462158 ps
CPU time 9.24 seconds
Started Jul 14 06:08:39 PM PDT 24
Finished Jul 14 06:08:49 PM PDT 24
Peak memory 205708 kb
Host smart-190aca84-06ed-40bb-87a7-82b45bf0560b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665782680 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3665782680
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.1710791507
Short name T1296
Test name
Test status
Simulation time 583362473 ps
CPU time 3.2 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 213812 kb
Host smart-e4cb40eb-2a87-445a-96d1-50903e6f7683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710791507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.1710791507
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.1726231689
Short name T1563
Test name
Test status
Simulation time 2199611738 ps
CPU time 2.74 seconds
Started Jul 14 06:08:41 PM PDT 24
Finished Jul 14 06:08:44 PM PDT 24
Peak memory 205540 kb
Host smart-2b99b3b8-0ab6-4bf7-a619-cbeeecc2d019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726231689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.1726231689
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.53855877
Short name T775
Test name
Test status
Simulation time 186635742 ps
CPU time 1.57 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:45 PM PDT 24
Peak memory 222172 kb
Host smart-766c71fc-617e-4389-b9ef-54c5b91746d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53855877 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_txstretch.53855877
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.2696288986
Short name T511
Test name
Test status
Simulation time 505862506 ps
CPU time 3.06 seconds
Started Jul 14 06:08:40 PM PDT 24
Finished Jul 14 06:08:44 PM PDT 24
Peak memory 213856 kb
Host smart-f7f6b814-549f-42cd-ba9a-48f0303a3ed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696288986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.2696288986
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.1558973458
Short name T1616
Test name
Test status
Simulation time 2698626606 ps
CPU time 2.49 seconds
Started Jul 14 06:08:38 PM PDT 24
Finished Jul 14 06:08:41 PM PDT 24
Peak memory 205464 kb
Host smart-30263f24-3614-4a8e-9c7b-09b7e7e2e479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558973458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.1558973458
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1239380978
Short name T1029
Test name
Test status
Simulation time 3707733906 ps
CPU time 13.44 seconds
Started Jul 14 06:08:40 PM PDT 24
Finished Jul 14 06:08:54 PM PDT 24
Peak memory 213844 kb
Host smart-ec8093f4-9b0d-41cd-b8dd-3144a998c5a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239380978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1239380978
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.398866379
Short name T1215
Test name
Test status
Simulation time 46360561202 ps
CPU time 91.08 seconds
Started Jul 14 06:08:37 PM PDT 24
Finished Jul 14 06:10:09 PM PDT 24
Peak memory 585880 kb
Host smart-10af9471-e5e9-4dc9-865b-c2027dbcba0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398866379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.398866379
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2840952416
Short name T1735
Test name
Test status
Simulation time 1236609883 ps
CPU time 53.88 seconds
Started Jul 14 06:08:38 PM PDT 24
Finished Jul 14 06:09:33 PM PDT 24
Peak memory 213784 kb
Host smart-0769466c-b212-4e50-8fe1-76813b123e7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840952416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2840952416
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1730674595
Short name T1429
Test name
Test status
Simulation time 30363825876 ps
CPU time 78.72 seconds
Started Jul 14 06:08:38 PM PDT 24
Finished Jul 14 06:09:57 PM PDT 24
Peak memory 1306908 kb
Host smart-5d620270-d4ba-4f6e-b8ec-ea89fec5aa4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730674595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1730674595
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3868439758
Short name T70
Test name
Test status
Simulation time 6953903758 ps
CPU time 7.26 seconds
Started Jul 14 06:08:40 PM PDT 24
Finished Jul 14 06:08:48 PM PDT 24
Peak memory 222036 kb
Host smart-8efd46a7-8596-4fbb-870e-c48c70c84975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868439758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3868439758
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.3077601688
Short name T317
Test name
Test status
Simulation time 145278451 ps
CPU time 3.37 seconds
Started Jul 14 06:08:39 PM PDT 24
Finished Jul 14 06:08:43 PM PDT 24
Peak memory 205612 kb
Host smart-15799886-424e-46e4-8025-f6969751f073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077601688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3077601688
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2150892144
Short name T610
Test name
Test status
Simulation time 63929738 ps
CPU time 0.61 seconds
Started Jul 14 06:08:55 PM PDT 24
Finished Jul 14 06:08:56 PM PDT 24
Peak memory 204780 kb
Host smart-209ee157-8204-4e10-a566-f29b956cf9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150892144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2150892144
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1419891067
Short name T1487
Test name
Test status
Simulation time 84094545 ps
CPU time 1.46 seconds
Started Jul 14 06:08:48 PM PDT 24
Finished Jul 14 06:08:50 PM PDT 24
Peak memory 213692 kb
Host smart-57e4f4bc-d34b-4a81-acf3-0797d6bcb9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419891067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1419891067
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1941299061
Short name T273
Test name
Test status
Simulation time 665907254 ps
CPU time 13.53 seconds
Started Jul 14 06:08:46 PM PDT 24
Finished Jul 14 06:09:00 PM PDT 24
Peak memory 258060 kb
Host smart-9a8ba229-5665-4b56-a058-b5f0ca404145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941299061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1941299061
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2639166438
Short name T1495
Test name
Test status
Simulation time 15778981290 ps
CPU time 44.27 seconds
Started Jul 14 06:08:44 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 271128 kb
Host smart-1f70f230-cda3-4973-88c1-7e3e17b77dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639166438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2639166438
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.989797767
Short name T1284
Test name
Test status
Simulation time 1500430984 ps
CPU time 49.73 seconds
Started Jul 14 06:08:44 PM PDT 24
Finished Jul 14 06:09:34 PM PDT 24
Peak memory 576020 kb
Host smart-38791d70-fd37-4868-be7f-8b673eb11658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989797767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.989797767
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1123905878
Short name T940
Test name
Test status
Simulation time 119232379 ps
CPU time 1.2 seconds
Started Jul 14 06:08:55 PM PDT 24
Finished Jul 14 06:08:57 PM PDT 24
Peak memory 205424 kb
Host smart-9503ed86-bcf9-4da4-8cab-1b82320c5744
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123905878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1123905878
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2302270736
Short name T1658
Test name
Test status
Simulation time 179254907 ps
CPU time 8.61 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 205512 kb
Host smart-213579c3-b7af-49f1-8c83-b076db3d875a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302270736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2302270736
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.182360045
Short name T1457
Test name
Test status
Simulation time 28436777367 ps
CPU time 117.34 seconds
Started Jul 14 06:08:44 PM PDT 24
Finished Jul 14 06:10:42 PM PDT 24
Peak memory 1342660 kb
Host smart-50569b96-e5b2-450f-9acf-67c2fa1a29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182360045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.182360045
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2156019377
Short name T774
Test name
Test status
Simulation time 4405987612 ps
CPU time 9.28 seconds
Started Jul 14 06:08:49 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 205528 kb
Host smart-bc8610f4-447f-4957-ba8d-338e6edc56bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156019377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2156019377
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_override.838873071
Short name T770
Test name
Test status
Simulation time 31135143 ps
CPU time 0.7 seconds
Started Jul 14 06:08:47 PM PDT 24
Finished Jul 14 06:08:48 PM PDT 24
Peak memory 205228 kb
Host smart-230f2081-b11c-448e-9aef-ed9759848ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838873071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.838873071
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1305012172
Short name T623
Test name
Test status
Simulation time 5735885089 ps
CPU time 17.1 seconds
Started Jul 14 06:08:45 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 226980 kb
Host smart-0fea9b94-93a1-4c40-87e7-99dff9bf4172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305012172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1305012172
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.2966300891
Short name T632
Test name
Test status
Simulation time 75149358 ps
CPU time 1.36 seconds
Started Jul 14 06:08:44 PM PDT 24
Finished Jul 14 06:08:46 PM PDT 24
Peak memory 205436 kb
Host smart-1bbf336c-c94e-47fb-a342-eaa24d3bc9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966300891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2966300891
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3481561922
Short name T621
Test name
Test status
Simulation time 5669691459 ps
CPU time 50.52 seconds
Started Jul 14 06:08:42 PM PDT 24
Finished Jul 14 06:09:33 PM PDT 24
Peak memory 263524 kb
Host smart-f3b53b2d-72af-4b87-a47e-3c85777518d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481561922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3481561922
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.505519702
Short name T969
Test name
Test status
Simulation time 1840235619 ps
CPU time 15.83 seconds
Started Jul 14 06:08:46 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 230000 kb
Host smart-6820f9f4-dc23-40c8-8c02-3ebce8536135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505519702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.505519702
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1210631885
Short name T619
Test name
Test status
Simulation time 4970727031 ps
CPU time 5.05 seconds
Started Jul 14 06:08:53 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 218252 kb
Host smart-9bf69389-5e8a-45db-92f4-6b4ff7397923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210631885 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1210631885
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2938501213
Short name T846
Test name
Test status
Simulation time 534180726 ps
CPU time 1.43 seconds
Started Jul 14 06:08:52 PM PDT 24
Finished Jul 14 06:08:54 PM PDT 24
Peak memory 205592 kb
Host smart-25825df1-a069-467c-950d-8bab25012d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938501213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2938501213
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2287632545
Short name T95
Test name
Test status
Simulation time 789757510 ps
CPU time 1.8 seconds
Started Jul 14 06:08:49 PM PDT 24
Finished Jul 14 06:08:51 PM PDT 24
Peak memory 206292 kb
Host smart-665cea09-a4f8-45d9-bb16-c39f0da6257e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287632545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2287632545
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.786173813
Short name T1498
Test name
Test status
Simulation time 473570770 ps
CPU time 1.86 seconds
Started Jul 14 06:08:50 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 205416 kb
Host smart-b8959cb6-5da0-445f-be87-ca0a9c453ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786173813 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.786173813
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.3574220674
Short name T923
Test name
Test status
Simulation time 240464445 ps
CPU time 0.92 seconds
Started Jul 14 06:08:52 PM PDT 24
Finished Jul 14 06:08:54 PM PDT 24
Peak memory 205396 kb
Host smart-1eadeb73-5c46-470c-b393-9371e957891f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574220674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.3574220674
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1563276758
Short name T165
Test name
Test status
Simulation time 366079089 ps
CPU time 3.11 seconds
Started Jul 14 06:08:55 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 213832 kb
Host smart-40a69158-5254-4c89-8ea4-df50e78b67e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563276758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1563276758
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3578659667
Short name T807
Test name
Test status
Simulation time 1633230180 ps
CPU time 4.67 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:48 PM PDT 24
Peak memory 221908 kb
Host smart-6e1c4949-408b-4a8d-82df-ba018314aa92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578659667 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3578659667
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.539783558
Short name T293
Test name
Test status
Simulation time 12731599897 ps
CPU time 30.7 seconds
Started Jul 14 06:08:45 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 788524 kb
Host smart-9a2bbcc7-531f-4813-a875-9a33457624ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539783558 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.539783558
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.3581416913
Short name T1446
Test name
Test status
Simulation time 2163459201 ps
CPU time 2.75 seconds
Started Jul 14 06:08:50 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 213764 kb
Host smart-a1e0aad8-5a4a-460d-9805-2f4f9e67b800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581416913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.3581416913
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.1345193736
Short name T1186
Test name
Test status
Simulation time 491375879 ps
CPU time 2.45 seconds
Started Jul 14 06:08:48 PM PDT 24
Finished Jul 14 06:08:51 PM PDT 24
Peak memory 205572 kb
Host smart-f2a6745f-9055-4723-bf1a-526b14c765ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345193736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1345193736
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.4222768111
Short name T828
Test name
Test status
Simulation time 4952727827 ps
CPU time 5.45 seconds
Started Jul 14 06:08:54 PM PDT 24
Finished Jul 14 06:09:00 PM PDT 24
Peak memory 219204 kb
Host smart-eb77dd41-33dd-462b-a138-8eab9d7d996a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222768111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.4222768111
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.983847919
Short name T571
Test name
Test status
Simulation time 528860619 ps
CPU time 2.35 seconds
Started Jul 14 06:08:50 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 205324 kb
Host smart-a482f1b8-1009-4ced-aaf7-f4205c0a1629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983847919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_smbus_maxlen.983847919
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.4031454212
Short name T291
Test name
Test status
Simulation time 18600887494 ps
CPU time 17.62 seconds
Started Jul 14 06:08:46 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 213748 kb
Host smart-fd91976a-20b4-42dc-b14e-f091c8505629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031454212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.4031454212
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.995659920
Short name T697
Test name
Test status
Simulation time 980758725 ps
CPU time 6.65 seconds
Started Jul 14 06:08:46 PM PDT 24
Finished Jul 14 06:08:53 PM PDT 24
Peak memory 216612 kb
Host smart-937a7035-6414-40d7-8b95-592ed293a80f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995659920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.995659920
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.724205303
Short name T1645
Test name
Test status
Simulation time 11160432775 ps
CPU time 22.16 seconds
Started Jul 14 06:08:48 PM PDT 24
Finished Jul 14 06:09:10 PM PDT 24
Peak memory 205600 kb
Host smart-94a8e337-8318-4b55-ab54-f84099fafef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724205303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.724205303
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1697158529
Short name T1394
Test name
Test status
Simulation time 433157743 ps
CPU time 1.17 seconds
Started Jul 14 06:08:44 PM PDT 24
Finished Jul 14 06:08:46 PM PDT 24
Peak memory 205436 kb
Host smart-e2555044-f08f-49d8-b98c-ce7b0e596067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697158529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1697158529
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1850009892
Short name T307
Test name
Test status
Simulation time 1285655831 ps
CPU time 6.53 seconds
Started Jul 14 06:08:43 PM PDT 24
Finished Jul 14 06:08:51 PM PDT 24
Peak memory 213820 kb
Host smart-72828222-c88b-482b-99a6-d7e64cd02367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850009892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1850009892
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3013721067
Short name T1577
Test name
Test status
Simulation time 368397408 ps
CPU time 5.25 seconds
Started Jul 14 06:08:52 PM PDT 24
Finished Jul 14 06:08:57 PM PDT 24
Peak memory 205584 kb
Host smart-d8c67a9f-1f04-4772-87fc-af115bb32db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013721067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3013721067
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.746116177
Short name T1278
Test name
Test status
Simulation time 21575965 ps
CPU time 0.66 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:08:59 PM PDT 24
Peak memory 204756 kb
Host smart-2af51a29-8255-4993-ba8f-b56824989a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746116177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.746116177
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3527425862
Short name T30
Test name
Test status
Simulation time 512310403 ps
CPU time 9.88 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:08 PM PDT 24
Peak memory 246028 kb
Host smart-92a7f444-4b30-4252-b56e-dbaf6c9fabcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527425862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3527425862
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3116054285
Short name T1731
Test name
Test status
Simulation time 542422785 ps
CPU time 14.88 seconds
Started Jul 14 06:08:50 PM PDT 24
Finished Jul 14 06:09:05 PM PDT 24
Peak memory 264248 kb
Host smart-fdf7a962-bf3b-46b9-bff1-7bee98cf08c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116054285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3116054285
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.346139925
Short name T657
Test name
Test status
Simulation time 12928313877 ps
CPU time 238.27 seconds
Started Jul 14 06:08:54 PM PDT 24
Finished Jul 14 06:12:53 PM PDT 24
Peak memory 816476 kb
Host smart-dac7c2b6-c19d-4414-b507-fab91e2c0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346139925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.346139925
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.88508063
Short name T1575
Test name
Test status
Simulation time 2538624394 ps
CPU time 80.74 seconds
Started Jul 14 06:08:52 PM PDT 24
Finished Jul 14 06:10:13 PM PDT 24
Peak memory 821112 kb
Host smart-0ea5d010-98da-45a5-b01f-3ea46561481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88508063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.88508063
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1746519484
Short name T234
Test name
Test status
Simulation time 1007183750 ps
CPU time 0.95 seconds
Started Jul 14 06:08:51 PM PDT 24
Finished Jul 14 06:08:52 PM PDT 24
Peak memory 205188 kb
Host smart-0f19f1fc-6a0c-4fa8-b6ca-95262d5359a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746519484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1746519484
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1808901431
Short name T434
Test name
Test status
Simulation time 206858085 ps
CPU time 12.18 seconds
Started Jul 14 06:08:56 PM PDT 24
Finished Jul 14 06:09:08 PM PDT 24
Peak memory 246612 kb
Host smart-9b1ba9f8-518d-43e3-aac8-dbd1799f3ccb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808901431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1808901431
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.4083106044
Short name T353
Test name
Test status
Simulation time 11384745097 ps
CPU time 318.3 seconds
Started Jul 14 06:08:53 PM PDT 24
Finished Jul 14 06:14:12 PM PDT 24
Peak memory 1247076 kb
Host smart-86641e06-fe34-4b28-b5af-356ba434ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083106044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.4083106044
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1508264630
Short name T26
Test name
Test status
Simulation time 432099151 ps
CPU time 5.62 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 205408 kb
Host smart-f3e4f47f-a93e-4442-981c-087ed6a5cbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508264630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1508264630
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.994277941
Short name T130
Test name
Test status
Simulation time 49557057 ps
CPU time 0.72 seconds
Started Jul 14 06:08:51 PM PDT 24
Finished Jul 14 06:08:52 PM PDT 24
Peak memory 205200 kb
Host smart-baec72b7-4268-4cad-8d0f-20d7079c7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994277941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.994277941
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.554937113
Short name T1341
Test name
Test status
Simulation time 28527471370 ps
CPU time 101.08 seconds
Started Jul 14 06:08:51 PM PDT 24
Finished Jul 14 06:10:32 PM PDT 24
Peak memory 205556 kb
Host smart-412ebbd1-d630-4db3-bc23-271295f068a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554937113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.554937113
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1691090278
Short name T490
Test name
Test status
Simulation time 2457124094 ps
CPU time 13.79 seconds
Started Jul 14 06:08:54 PM PDT 24
Finished Jul 14 06:09:08 PM PDT 24
Peak memory 206016 kb
Host smart-d7fd97ec-7f98-4421-b7d1-69e515713581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691090278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1691090278
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.4267407280
Short name T1518
Test name
Test status
Simulation time 2034525487 ps
CPU time 47.09 seconds
Started Jul 14 06:08:51 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 481552 kb
Host smart-edd1bb31-ada4-4f33-be9c-b515226424a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267407280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.4267407280
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.998865917
Short name T110
Test name
Test status
Simulation time 138513303206 ps
CPU time 1120.12 seconds
Started Jul 14 06:08:59 PM PDT 24
Finished Jul 14 06:27:40 PM PDT 24
Peak memory 2744700 kb
Host smart-72a800ac-a4fd-4f1d-91c0-8a2ad5a22d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998865917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.998865917
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.728832727
Short name T286
Test name
Test status
Simulation time 493440636 ps
CPU time 22.53 seconds
Started Jul 14 06:08:53 PM PDT 24
Finished Jul 14 06:09:16 PM PDT 24
Peak memory 213672 kb
Host smart-f7b90277-7434-4485-8ffb-02d6e0a946ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728832727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.728832727
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.724283703
Short name T357
Test name
Test status
Simulation time 1298986679 ps
CPU time 6.47 seconds
Started Jul 14 06:09:00 PM PDT 24
Finished Jul 14 06:09:07 PM PDT 24
Peak memory 221980 kb
Host smart-abc5ac7f-4821-4b7d-afed-4e45d118db61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724283703 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.724283703
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2621397541
Short name T1594
Test name
Test status
Simulation time 257838488 ps
CPU time 1.62 seconds
Started Jul 14 06:08:58 PM PDT 24
Finished Jul 14 06:09:01 PM PDT 24
Peak memory 205788 kb
Host smart-6a43c190-87d4-4b4b-965d-664d7263eed0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621397541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2621397541
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2271616265
Short name T79
Test name
Test status
Simulation time 432644012 ps
CPU time 1.18 seconds
Started Jul 14 06:08:58 PM PDT 24
Finished Jul 14 06:09:00 PM PDT 24
Peak memory 205604 kb
Host smart-73c72c48-6cce-4a83-ab45-7056e7148ac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271616265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2271616265
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.3426263045
Short name T1726
Test name
Test status
Simulation time 661086536 ps
CPU time 3.47 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 205600 kb
Host smart-c4215fac-f1da-437b-a0c5-19219a35385a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426263045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.3426263045
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.1247760053
Short name T1099
Test name
Test status
Simulation time 266746277 ps
CPU time 0.72 seconds
Started Jul 14 06:08:59 PM PDT 24
Finished Jul 14 06:09:00 PM PDT 24
Peak memory 205380 kb
Host smart-a1dd7d10-3aa1-4211-81a7-c6e937763674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247760053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1247760053
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1627770563
Short name T1666
Test name
Test status
Simulation time 1123030937 ps
CPU time 3.8 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 213876 kb
Host smart-3153db88-a690-4070-ae35-444b1ef39364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627770563 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1627770563
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2902856413
Short name T1370
Test name
Test status
Simulation time 5440784422 ps
CPU time 53.31 seconds
Started Jul 14 06:09:00 PM PDT 24
Finished Jul 14 06:09:54 PM PDT 24
Peak memory 1406864 kb
Host smart-83526cd6-4d06-45ab-b406-a8af6f47b1bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902856413 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2902856413
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.575901788
Short name T142
Test name
Test status
Simulation time 1136698849 ps
CPU time 3.09 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:02 PM PDT 24
Peak memory 213784 kb
Host smart-85fee84b-1c85-4dea-b6df-a28730b5526b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575901788 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_nack_acqfull.575901788
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.583677172
Short name T1583
Test name
Test status
Simulation time 1683230333 ps
CPU time 2.47 seconds
Started Jul 14 06:09:00 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 205572 kb
Host smart-98f51ebf-5430-4f47-8f1b-85cb3ef47e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583677172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.583677172
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_txstretch.536333211
Short name T1732
Test name
Test status
Simulation time 340735374 ps
CPU time 1.38 seconds
Started Jul 14 06:08:58 PM PDT 24
Finished Jul 14 06:09:01 PM PDT 24
Peak memory 222228 kb
Host smart-61cfdd29-5612-4b36-ba17-a97708d24311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536333211 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_nack_txstretch.536333211
Directory /workspace/45.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/45.i2c_target_perf.1418589050
Short name T1363
Test name
Test status
Simulation time 1179818927 ps
CPU time 4.51 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:03 PM PDT 24
Peak memory 222052 kb
Host smart-7cc77718-c9db-48c5-b7eb-4bf3bcca41e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418589050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.1418589050
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.255074085
Short name T1324
Test name
Test status
Simulation time 467174127 ps
CPU time 2.1 seconds
Started Jul 14 06:08:57 PM PDT 24
Finished Jul 14 06:09:00 PM PDT 24
Peak memory 205352 kb
Host smart-d5c9bb4a-67ca-47b0-9b2a-2d2cf9793e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255074085 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_smbus_maxlen.255074085
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1173741124
Short name T976
Test name
Test status
Simulation time 9266467668 ps
CPU time 12.04 seconds
Started Jul 14 06:08:56 PM PDT 24
Finished Jul 14 06:09:08 PM PDT 24
Peak memory 213940 kb
Host smart-d034d270-a8ba-46e3-a0fe-3e09c6f34133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173741124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1173741124
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.3262266421
Short name T325
Test name
Test status
Simulation time 26442260204 ps
CPU time 201.05 seconds
Started Jul 14 06:08:59 PM PDT 24
Finished Jul 14 06:12:21 PM PDT 24
Peak memory 1456792 kb
Host smart-35c47d48-025c-4c4c-91ef-c381a6f29196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262266421 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.3262266421
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.648965980
Short name T1254
Test name
Test status
Simulation time 6749243829 ps
CPU time 71.37 seconds
Started Jul 14 06:08:58 PM PDT 24
Finished Jul 14 06:10:10 PM PDT 24
Peak memory 217536 kb
Host smart-5d3cea76-e9cc-4124-a902-4d89d9062bc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648965980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.648965980
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3885911703
Short name T841
Test name
Test status
Simulation time 13650188059 ps
CPU time 26.81 seconds
Started Jul 14 06:08:53 PM PDT 24
Finished Jul 14 06:09:21 PM PDT 24
Peak memory 205672 kb
Host smart-7b77506a-18fb-4ba1-b61c-ada6da92ab6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885911703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3885911703
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1768211064
Short name T1151
Test name
Test status
Simulation time 4376909635 ps
CPU time 6.07 seconds
Started Jul 14 06:08:58 PM PDT 24
Finished Jul 14 06:09:05 PM PDT 24
Peak memory 213956 kb
Host smart-4cce78d2-bf64-464b-ac03-9837d0dc062c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768211064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1768211064
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.437499773
Short name T1346
Test name
Test status
Simulation time 412255176 ps
CPU time 6.7 seconds
Started Jul 14 06:08:59 PM PDT 24
Finished Jul 14 06:09:06 PM PDT 24
Peak memory 207680 kb
Host smart-75042438-b1d0-4ff6-98ba-aa2b85336543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437499773 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.437499773
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.897990267
Short name T1396
Test name
Test status
Simulation time 23150564 ps
CPU time 0.64 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:14 PM PDT 24
Peak memory 204688 kb
Host smart-36f358a9-e4d1-4306-b630-cef852fa533e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897990267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.897990267
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.810846116
Short name T559
Test name
Test status
Simulation time 264572951 ps
CPU time 2.29 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:09:05 PM PDT 24
Peak memory 221896 kb
Host smart-7b188385-665a-4378-bab4-be6a8991a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810846116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.810846116
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2746088045
Short name T1064
Test name
Test status
Simulation time 476246611 ps
CPU time 12.45 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:09:16 PM PDT 24
Peak memory 252880 kb
Host smart-838e50d8-d339-4c9f-9018-34209b530199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746088045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2746088045
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1436032848
Short name T577
Test name
Test status
Simulation time 4209340904 ps
CPU time 136.89 seconds
Started Jul 14 06:09:04 PM PDT 24
Finished Jul 14 06:11:22 PM PDT 24
Peak memory 508584 kb
Host smart-c2364124-accb-418f-9135-d2bb05864f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436032848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1436032848
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2277217443
Short name T649
Test name
Test status
Simulation time 9086685197 ps
CPU time 77.66 seconds
Started Jul 14 06:09:03 PM PDT 24
Finished Jul 14 06:10:21 PM PDT 24
Peak memory 750144 kb
Host smart-83e3991a-b021-4aa8-bbdf-160662f32668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277217443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2277217443
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2272599680
Short name T1708
Test name
Test status
Simulation time 124318390 ps
CPU time 1.1 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:09:04 PM PDT 24
Peak memory 205172 kb
Host smart-dff46a8d-fee3-459a-9919-99bf80511fbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272599680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2272599680
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.647840703
Short name T1488
Test name
Test status
Simulation time 254104288 ps
CPU time 3.75 seconds
Started Jul 14 06:09:05 PM PDT 24
Finished Jul 14 06:09:09 PM PDT 24
Peak memory 227280 kb
Host smart-abf46b52-140e-441d-b595-46da6f29a5ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647840703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
647840703
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2251811420
Short name T111
Test name
Test status
Simulation time 19073933032 ps
CPU time 134.99 seconds
Started Jul 14 06:09:10 PM PDT 24
Finished Jul 14 06:11:26 PM PDT 24
Peak memory 1473728 kb
Host smart-f083c6ff-adc4-4d79-94a7-daefffdfd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251811420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2251811420
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3178910537
Short name T246
Test name
Test status
Simulation time 1233452301 ps
CPU time 14.12 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:28 PM PDT 24
Peak memory 205452 kb
Host smart-17dec23d-a1ce-4ee5-9120-b9e016e68f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178910537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3178910537
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.670233097
Short name T1401
Test name
Test status
Simulation time 97004464 ps
CPU time 3.28 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 215316 kb
Host smart-30d545c9-395d-4ca7-9fbb-901edf263e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670233097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.670233097
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.421015937
Short name T1553
Test name
Test status
Simulation time 314756262 ps
CPU time 13.19 seconds
Started Jul 14 06:09:03 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 205392 kb
Host smart-91a01966-fbb4-4e71-85d5-7ba8fa2bd44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421015937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.421015937
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.4112749447
Short name T1715
Test name
Test status
Simulation time 1855703810 ps
CPU time 38.26 seconds
Started Jul 14 06:09:03 PM PDT 24
Finished Jul 14 06:09:43 PM PDT 24
Peak memory 398456 kb
Host smart-6afff2b5-05a8-4b42-a7ef-3af2e3701d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112749447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.4112749447
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3082497121
Short name T773
Test name
Test status
Simulation time 40377776945 ps
CPU time 1215.47 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:29:19 PM PDT 24
Peak memory 2703672 kb
Host smart-6d7b4f8a-2eed-46d0-9e97-0090fe1ad11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082497121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3082497121
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1801461461
Short name T1288
Test name
Test status
Simulation time 2025569964 ps
CPU time 16.61 seconds
Started Jul 14 06:09:04 PM PDT 24
Finished Jul 14 06:09:22 PM PDT 24
Peak memory 230052 kb
Host smart-d3e7b4a7-c380-42fe-982c-011e63c0b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801461461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1801461461
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2101073820
Short name T1655
Test name
Test status
Simulation time 769249459 ps
CPU time 4.21 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 214864 kb
Host smart-79237e67-9664-4344-9513-d267d8d2dd20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101073820 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2101073820
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.975387417
Short name T998
Test name
Test status
Simulation time 114349015 ps
CPU time 0.85 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 205424 kb
Host smart-ad413f64-03f4-47dd-948b-c65934465fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975387417 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.975387417
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3649151397
Short name T997
Test name
Test status
Simulation time 204210707 ps
CPU time 1.18 seconds
Started Jul 14 06:09:07 PM PDT 24
Finished Jul 14 06:09:09 PM PDT 24
Peak memory 205420 kb
Host smart-a3e027d5-6c19-4af8-b2eb-0d8242145225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649151397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3649151397
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.2569007644
Short name T776
Test name
Test status
Simulation time 873727591 ps
CPU time 1.84 seconds
Started Jul 14 06:09:08 PM PDT 24
Finished Jul 14 06:09:10 PM PDT 24
Peak memory 205420 kb
Host smart-ddaca60a-69a9-4ffd-90c7-729fd4436931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569007644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.2569007644
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.4006682150
Short name T756
Test name
Test status
Simulation time 255217481 ps
CPU time 1.17 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 205372 kb
Host smart-272a12e0-2e1d-4b68-8645-ee1e4c73da6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006682150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.4006682150
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3648012258
Short name T729
Test name
Test status
Simulation time 1347176338 ps
CPU time 2.46 seconds
Started Jul 14 06:09:09 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 215144 kb
Host smart-f2fd5247-acf6-4d7d-b8cf-3f7a3014c157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648012258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3648012258
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.901658332
Short name T1287
Test name
Test status
Simulation time 1206072167 ps
CPU time 8 seconds
Started Jul 14 06:09:03 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 214076 kb
Host smart-915bb2ce-d8dd-4a18-9d17-497f6b300b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901658332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.901658332
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.716118854
Short name T879
Test name
Test status
Simulation time 21991184881 ps
CPU time 461.25 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:16:44 PM PDT 24
Peak memory 3697088 kb
Host smart-c2c202be-82eb-40fa-b357-f172123e2821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716118854 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.716118854
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.3662831294
Short name T1468
Test name
Test status
Simulation time 2095403301 ps
CPU time 2.94 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:09:15 PM PDT 24
Peak memory 213848 kb
Host smart-55ba49c5-5447-40c3-b035-d398b427f3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662831294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.3662831294
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.92733082
Short name T1265
Test name
Test status
Simulation time 1530328919 ps
CPU time 2.9 seconds
Started Jul 14 06:09:09 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 205604 kb
Host smart-037948ee-8317-49f7-9781-7b3d300a2387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92733082 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_nack_acqfull_addr.92733082
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.167253887
Short name T839
Test name
Test status
Simulation time 131280983 ps
CPU time 1.53 seconds
Started Jul 14 06:09:10 PM PDT 24
Finished Jul 14 06:09:12 PM PDT 24
Peak memory 222476 kb
Host smart-5ccea6f8-96cb-43c0-8e86-a51c297faef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167253887 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_nack_txstretch.167253887
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.1254105195
Short name T281
Test name
Test status
Simulation time 478230043 ps
CPU time 3.51 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 221896 kb
Host smart-a5b3ce8b-60a3-4657-95b8-90e74deeffa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254105195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.1254105195
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.229803123
Short name T375
Test name
Test status
Simulation time 1860026821 ps
CPU time 2.35 seconds
Started Jul 14 06:09:09 PM PDT 24
Finished Jul 14 06:09:12 PM PDT 24
Peak memory 205288 kb
Host smart-11ebe0dc-4e87-4e86-a771-3eb2a3b2b0e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229803123 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_smbus_maxlen.229803123
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2453332152
Short name T76
Test name
Test status
Simulation time 3298837345 ps
CPU time 26.87 seconds
Started Jul 14 06:09:01 PM PDT 24
Finished Jul 14 06:09:28 PM PDT 24
Peak memory 213824 kb
Host smart-489cf08d-6afb-4ad4-ba3a-5f8469e3f9a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453332152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2453332152
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.3038791203
Short name T1595
Test name
Test status
Simulation time 40736849716 ps
CPU time 984.06 seconds
Started Jul 14 06:09:10 PM PDT 24
Finished Jul 14 06:25:35 PM PDT 24
Peak memory 4255076 kb
Host smart-8cec64cd-ff52-475c-85fb-a2e87ce0f2b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038791203 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.3038791203
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.4256826611
Short name T1024
Test name
Test status
Simulation time 1640339656 ps
CPU time 7.48 seconds
Started Jul 14 06:09:04 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 205508 kb
Host smart-d8164a5d-2bb3-4459-904b-35d2c5ac3b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256826611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.4256826611
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3561293117
Short name T904
Test name
Test status
Simulation time 15367949367 ps
CPU time 7.85 seconds
Started Jul 14 06:09:05 PM PDT 24
Finished Jul 14 06:09:14 PM PDT 24
Peak memory 205588 kb
Host smart-772db493-0e1f-450c-9373-5f3c19ceb241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561293117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3561293117
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2101495840
Short name T334
Test name
Test status
Simulation time 4337449591 ps
CPU time 11.21 seconds
Started Jul 14 06:09:02 PM PDT 24
Finished Jul 14 06:09:14 PM PDT 24
Peak memory 280884 kb
Host smart-a6283ace-6e77-4426-bbb4-2ffbdec6b65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101495840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2101495840
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1003008678
Short name T1250
Test name
Test status
Simulation time 1287712855 ps
CPU time 7.06 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 230076 kb
Host smart-4b089657-bfe4-479b-b7b7-0994a652209a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003008678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1003008678
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.3126629382
Short name T568
Test name
Test status
Simulation time 90285575 ps
CPU time 2.1 seconds
Started Jul 14 06:09:09 PM PDT 24
Finished Jul 14 06:09:12 PM PDT 24
Peak memory 205584 kb
Host smart-e955e024-123f-4434-b6c9-2daa8096479e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126629382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3126629382
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.987754145
Short name T1605
Test name
Test status
Simulation time 45326056 ps
CPU time 0.63 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 204684 kb
Host smart-3565a24b-345f-4cfd-a31d-eef2b871b5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987754145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.987754145
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1144621283
Short name T863
Test name
Test status
Simulation time 216355721 ps
CPU time 1.37 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 213772 kb
Host smart-35085421-c7a2-4156-99ba-ba8ba4e8f8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144621283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1144621283
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3740008070
Short name T1137
Test name
Test status
Simulation time 248616628 ps
CPU time 12.54 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:09:24 PM PDT 24
Peak memory 253044 kb
Host smart-8d799b43-c968-4800-9ab4-7798bbff6f47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740008070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3740008070
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.145356109
Short name T1598
Test name
Test status
Simulation time 7186160196 ps
CPU time 100.88 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:10:52 PM PDT 24
Peak memory 238064 kb
Host smart-360805bb-7c77-4f19-ab0a-a0887857fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145356109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.145356109
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1767828192
Short name T1310
Test name
Test status
Simulation time 29763662837 ps
CPU time 89.03 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:10:41 PM PDT 24
Peak memory 875184 kb
Host smart-b6bd8156-7253-444e-8330-c4cf1680c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767828192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1767828192
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1803640039
Short name T738
Test name
Test status
Simulation time 649141024 ps
CPU time 1.06 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:09:13 PM PDT 24
Peak memory 205212 kb
Host smart-5934a9f6-9cd4-4137-9a7b-32f8bd9d8af0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803640039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1803640039
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1102925155
Short name T1066
Test name
Test status
Simulation time 348764474 ps
CPU time 4.23 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:09:19 PM PDT 24
Peak memory 232936 kb
Host smart-e1552db2-b147-489a-97b8-e64682795d9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102925155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1102925155
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.216573274
Short name T1626
Test name
Test status
Simulation time 4552287637 ps
CPU time 128.37 seconds
Started Jul 14 06:09:11 PM PDT 24
Finished Jul 14 06:11:20 PM PDT 24
Peak memory 1259744 kb
Host smart-30978981-f4f9-4c51-b8f9-51f080291b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216573274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.216573274
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.764350947
Short name T181
Test name
Test status
Simulation time 1618562317 ps
CPU time 6.85 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 205524 kb
Host smart-7a893ee2-2ebe-44a1-a5f0-389711812236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764350947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.764350947
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.3342803672
Short name T1624
Test name
Test status
Simulation time 20125699 ps
CPU time 0.69 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:09:15 PM PDT 24
Peak memory 205108 kb
Host smart-4d62ff3c-4c51-4d7d-b34f-057d0f7ea280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342803672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3342803672
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.31621116
Short name T593
Test name
Test status
Simulation time 13031263331 ps
CPU time 18.94 seconds
Started Jul 14 06:09:10 PM PDT 24
Finished Jul 14 06:09:30 PM PDT 24
Peak memory 216684 kb
Host smart-745e7a57-52d1-44c3-88f4-a76372716814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31621116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.31621116
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.492392426
Short name T491
Test name
Test status
Simulation time 172120017 ps
CPU time 1.44 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 223156 kb
Host smart-e611d458-fa39-4d6c-a301-8e86257719a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492392426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.492392426
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3778492689
Short name T640
Test name
Test status
Simulation time 1326374414 ps
CPU time 58.97 seconds
Started Jul 14 06:09:09 PM PDT 24
Finished Jul 14 06:10:09 PM PDT 24
Peak memory 311120 kb
Host smart-dbfea1a0-ddaa-4f4a-b969-90a7691d39c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778492689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3778492689
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2665764778
Short name T746
Test name
Test status
Simulation time 731634240 ps
CPU time 33.09 seconds
Started Jul 14 06:09:18 PM PDT 24
Finished Jul 14 06:09:52 PM PDT 24
Peak memory 213684 kb
Host smart-760afda1-3b4a-4429-90c0-927ca6d3db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665764778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2665764778
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2026762414
Short name T430
Test name
Test status
Simulation time 1385138450 ps
CPU time 7.03 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:24 PM PDT 24
Peak memory 219712 kb
Host smart-a767012c-d2fe-4300-b5a2-1174d1ff2fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026762414 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2026762414
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3783740801
Short name T918
Test name
Test status
Simulation time 226194032 ps
CPU time 0.87 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 205448 kb
Host smart-36f021c6-3a59-4613-b6db-507eb3ee25c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783740801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3783740801
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.441143238
Short name T757
Test name
Test status
Simulation time 251146535 ps
CPU time 0.78 seconds
Started Jul 14 06:09:17 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 205448 kb
Host smart-129cd5ee-7984-4075-b9a9-74d7496483fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441143238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.441143238
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.4291683291
Short name T1419
Test name
Test status
Simulation time 619552815 ps
CPU time 3.13 seconds
Started Jul 14 06:09:18 PM PDT 24
Finished Jul 14 06:09:22 PM PDT 24
Peak memory 205604 kb
Host smart-bf87fb7d-1361-4141-a03f-0c17ae2e98d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291683291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.4291683291
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.25855694
Short name T1404
Test name
Test status
Simulation time 641000420 ps
CPU time 1.27 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 205412 kb
Host smart-2adc1eab-dd61-42cc-9bd3-4b125afd7db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25855694 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.25855694
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3221703607
Short name T1718
Test name
Test status
Simulation time 2331847960 ps
CPU time 7.09 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:23 PM PDT 24
Peak memory 222040 kb
Host smart-9b0a12a0-7c9b-4099-8b41-95e8c498fa02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221703607 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3221703607
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2420644929
Short name T802
Test name
Test status
Simulation time 10378469218 ps
CPU time 153.53 seconds
Started Jul 14 06:09:18 PM PDT 24
Finished Jul 14 06:11:52 PM PDT 24
Peak memory 2496484 kb
Host smart-0250dec4-1de2-4616-a0e2-753dff10185d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420644929 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2420644929
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.1092451528
Short name T597
Test name
Test status
Simulation time 589270220 ps
CPU time 2.58 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:09:17 PM PDT 24
Peak memory 213776 kb
Host smart-c2260d6b-1001-4b68-bc70-3775c422b027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092451528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.1092451528
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.464298847
Short name T60
Test name
Test status
Simulation time 434393633 ps
CPU time 2.41 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:19 PM PDT 24
Peak memory 206216 kb
Host smart-016601c3-b124-4212-b1e6-3a714880d107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464298847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.464298847
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3642571363
Short name T680
Test name
Test status
Simulation time 152315643 ps
CPU time 1.55 seconds
Started Jul 14 06:09:17 PM PDT 24
Finished Jul 14 06:09:19 PM PDT 24
Peak memory 222480 kb
Host smart-6f6de977-0667-4662-8d54-5d401a6fb963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642571363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3642571363
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.3211425966
Short name T155
Test name
Test status
Simulation time 3700170766 ps
CPU time 6.65 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:24 PM PDT 24
Peak memory 213844 kb
Host smart-2fa33a5b-03fa-4b3a-a815-f744226030f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211425966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.3211425966
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.2706447803
Short name T1561
Test name
Test status
Simulation time 2430149654 ps
CPU time 2.56 seconds
Started Jul 14 06:09:16 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 205492 kb
Host smart-48265158-0f58-4254-8592-cdea2bfb7afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706447803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.2706447803
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2595263665
Short name T72
Test name
Test status
Simulation time 5296113805 ps
CPU time 41.08 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:57 PM PDT 24
Peak memory 213812 kb
Host smart-9f0c1673-63b2-4160-b12f-9af32b2441d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595263665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2595263665
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.104941264
Short name T1657
Test name
Test status
Simulation time 66592371402 ps
CPU time 547.89 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:18:23 PM PDT 24
Peak memory 3359280 kb
Host smart-b6df1746-5795-47b9-acd4-fa93130f7f6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104941264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_target_stress_all.104941264
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1357267713
Short name T570
Test name
Test status
Simulation time 256709154 ps
CPU time 4.02 seconds
Started Jul 14 06:09:15 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 205540 kb
Host smart-9b552041-ed07-42d6-8658-4178db5e3279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357267713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1357267713
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.89566770
Short name T1006
Test name
Test status
Simulation time 71097892184 ps
CPU time 404.3 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:15:59 PM PDT 24
Peak memory 3169944 kb
Host smart-ed2fd270-b4d0-4c55-a751-aa16c8c50957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89566770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stress_wr.89566770
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2039666117
Short name T381
Test name
Test status
Simulation time 2820709479 ps
CPU time 10.99 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:09:26 PM PDT 24
Peak memory 354348 kb
Host smart-dd17859d-7ea8-45cc-84db-b76009b179d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039666117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2039666117
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2358583963
Short name T1483
Test name
Test status
Simulation time 5100594283 ps
CPU time 7.48 seconds
Started Jul 14 06:09:14 PM PDT 24
Finished Jul 14 06:09:23 PM PDT 24
Peak memory 230200 kb
Host smart-c9b8ed26-1a42-4181-b8b3-fdffbc6f1817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358583963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2358583963
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.986496317
Short name T449
Test name
Test status
Simulation time 62476151 ps
CPU time 1.51 seconds
Started Jul 14 06:09:18 PM PDT 24
Finished Jul 14 06:09:20 PM PDT 24
Peak memory 205584 kb
Host smart-7a908d63-e698-4112-bb00-935946c51425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986496317 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.986496317
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2752133382
Short name T567
Test name
Test status
Simulation time 53680482 ps
CPU time 0.63 seconds
Started Jul 14 06:09:28 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 204776 kb
Host smart-ec5ab5ca-c81b-483e-8e6f-5a63fd296de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752133382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2752133382
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1743151995
Short name T1318
Test name
Test status
Simulation time 391451384 ps
CPU time 2.34 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:25 PM PDT 24
Peak memory 213764 kb
Host smart-cbc97e74-754d-47a5-afb6-c1a6e6465fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743151995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1743151995
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.833564273
Short name T1398
Test name
Test status
Simulation time 799564807 ps
CPU time 9.65 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 297956 kb
Host smart-8c534c6d-c6c1-400c-823a-26bb1ad4dca2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833564273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.833564273
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3339205975
Short name T39
Test name
Test status
Simulation time 16206280253 ps
CPU time 278.29 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:14:01 PM PDT 24
Peak memory 843956 kb
Host smart-d63a2ba5-c6d9-45d2-ad0c-afa3da35c913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339205975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3339205975
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3829753103
Short name T1267
Test name
Test status
Simulation time 16124338402 ps
CPU time 41.85 seconds
Started Jul 14 06:09:25 PM PDT 24
Finished Jul 14 06:10:07 PM PDT 24
Peak memory 505192 kb
Host smart-b2c37b22-7078-4045-898a-6e56ea45cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829753103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3829753103
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1082199952
Short name T1342
Test name
Test status
Simulation time 179888300 ps
CPU time 1.24 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:09:24 PM PDT 24
Peak memory 205140 kb
Host smart-43b4e112-8bc8-4acd-9c81-2cf389c0e501
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082199952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1082199952
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3022583104
Short name T1207
Test name
Test status
Simulation time 905302124 ps
CPU time 13.77 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:35 PM PDT 24
Peak memory 253380 kb
Host smart-fb09e1a7-337e-429f-85b4-d130062add1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022583104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3022583104
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.879735790
Short name T992
Test name
Test status
Simulation time 2940228540 ps
CPU time 62.87 seconds
Started Jul 14 06:09:18 PM PDT 24
Finished Jul 14 06:10:21 PM PDT 24
Peak memory 906920 kb
Host smart-2b87a15c-947f-4c1a-b5f5-b9cda5ab66bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879735790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.879735790
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.4010389287
Short name T876
Test name
Test status
Simulation time 2030501116 ps
CPU time 8.28 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 205376 kb
Host smart-7f595a79-3dfc-48d0-a3d2-b1c18dd73c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010389287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.4010389287
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3957285257
Short name T258
Test name
Test status
Simulation time 78803603 ps
CPU time 1.24 seconds
Started Jul 14 06:09:23 PM PDT 24
Finished Jul 14 06:09:25 PM PDT 24
Peak memory 213668 kb
Host smart-6d87839a-cef6-44a0-b2f5-7375de28846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957285257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3957285257
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.551066215
Short name T993
Test name
Test status
Simulation time 26541183 ps
CPU time 0.69 seconds
Started Jul 14 06:09:17 PM PDT 24
Finished Jul 14 06:09:18 PM PDT 24
Peak memory 205100 kb
Host smart-5553c6df-5554-4a96-94c0-c772a6e778fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551066215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.551066215
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.782676994
Short name T37
Test name
Test status
Simulation time 640870385 ps
CPU time 26.54 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:49 PM PDT 24
Peak memory 206088 kb
Host smart-cc496dfc-3d38-494b-b3bb-4dfe3ac0287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782676994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.782676994
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1255919665
Short name T1063
Test name
Test status
Simulation time 142637364 ps
CPU time 1.8 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:09:25 PM PDT 24
Peak memory 223056 kb
Host smart-3514e4f1-e279-43e6-b71c-9449f665c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255919665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1255919665
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2467802244
Short name T487
Test name
Test status
Simulation time 12337180872 ps
CPU time 74.46 seconds
Started Jul 14 06:09:13 PM PDT 24
Finished Jul 14 06:10:28 PM PDT 24
Peak memory 303636 kb
Host smart-29c73472-4f05-4cda-96e5-f8553d726d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467802244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2467802244
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1380058831
Short name T1113
Test name
Test status
Simulation time 2724228649 ps
CPU time 30.47 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:52 PM PDT 24
Peak memory 213788 kb
Host smart-1d6fe2ee-2240-4cd6-8422-d323235a9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380058831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1380058831
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.4223641553
Short name T956
Test name
Test status
Simulation time 12421707699 ps
CPU time 5.37 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:09:28 PM PDT 24
Peak memory 213900 kb
Host smart-b1517b0c-6a1f-4dfb-9639-c717fe42df2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223641553 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.4223641553
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3348570300
Short name T74
Test name
Test status
Simulation time 605179656 ps
CPU time 1.62 seconds
Started Jul 14 06:09:24 PM PDT 24
Finished Jul 14 06:09:26 PM PDT 24
Peak memory 205608 kb
Host smart-de4a8bc8-6f17-49df-a8ce-6ee83a0f3f9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348570300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3348570300
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2425987459
Short name T53
Test name
Test status
Simulation time 330028440 ps
CPU time 1.59 seconds
Started Jul 14 06:09:24 PM PDT 24
Finished Jul 14 06:09:26 PM PDT 24
Peak memory 205364 kb
Host smart-910c0464-2b36-4696-928d-7b02f649eb42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425987459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2425987459
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.3363667361
Short name T634
Test name
Test status
Simulation time 88568490 ps
CPU time 0.99 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 205372 kb
Host smart-8c34d9af-8460-4fdf-8ff3-3afbdeb88d1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363667361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.3363667361
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.4002845405
Short name T371
Test name
Test status
Simulation time 424117466 ps
CPU time 1.06 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 205424 kb
Host smart-3fd7f9e1-b85f-4fba-9d94-c65a39738507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002845405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.4002845405
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3271001124
Short name T1223
Test name
Test status
Simulation time 1143843163 ps
CPU time 6.07 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:09:29 PM PDT 24
Peak memory 213856 kb
Host smart-96341bce-843a-4566-b823-c13c336afb60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271001124 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3271001124
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2246580465
Short name T1558
Test name
Test status
Simulation time 22070966991 ps
CPU time 181.98 seconds
Started Jul 14 06:09:20 PM PDT 24
Finished Jul 14 06:12:23 PM PDT 24
Peak memory 2064168 kb
Host smart-1ab630f0-7399-4b0b-b089-035a719e8ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246580465 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2246580465
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.3235581565
Short name T52
Test name
Test status
Simulation time 2520190508 ps
CPU time 3.1 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:33 PM PDT 24
Peak memory 213828 kb
Host smart-ea0f28cb-86cb-4b40-8890-d532716f0ed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235581565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.3235581565
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.3724378473
Short name T484
Test name
Test status
Simulation time 952723656 ps
CPU time 2.65 seconds
Started Jul 14 06:09:28 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 205544 kb
Host smart-e417ac67-4b24-41c4-b82e-005ffb11954b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724378473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.3724378473
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_txstretch.1192873820
Short name T664
Test name
Test status
Simulation time 138139686 ps
CPU time 1.43 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 222432 kb
Host smart-ae0e928a-7bb6-41f8-b0dd-c46cca85e0fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192873820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_nack_txstretch.1192873820
Directory /workspace/48.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/48.i2c_target_perf.3234621680
Short name T1680
Test name
Test status
Simulation time 2671943720 ps
CPU time 4.26 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:27 PM PDT 24
Peak memory 210236 kb
Host smart-9237c9b7-2e11-4b8b-bfaf-c75841c45b2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234621680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.3234621680
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.3342138568
Short name T527
Test name
Test status
Simulation time 453484570 ps
CPU time 2.19 seconds
Started Jul 14 06:09:33 PM PDT 24
Finished Jul 14 06:09:36 PM PDT 24
Peak memory 205316 kb
Host smart-17eb8b4d-170e-4f82-853f-ae868b74d6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342138568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.3342138568
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.378763028
Short name T1053
Test name
Test status
Simulation time 6252007397 ps
CPU time 11.09 seconds
Started Jul 14 06:09:20 PM PDT 24
Finished Jul 14 06:09:32 PM PDT 24
Peak memory 213880 kb
Host smart-41bf7cb7-d46e-4530-8ef8-7aa92b549ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378763028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.378763028
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.3332698052
Short name T262
Test name
Test status
Simulation time 76872621577 ps
CPU time 112.49 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:11:16 PM PDT 24
Peak memory 591500 kb
Host smart-e47977c2-d430-4be0-ac29-e4dc07362a49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332698052 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.3332698052
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1836196829
Short name T949
Test name
Test status
Simulation time 2154295176 ps
CPU time 37.07 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:09:59 PM PDT 24
Peak memory 232932 kb
Host smart-d7a41e79-fd51-4bfb-b6fc-d70213cca375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836196829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1836196829
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.557601630
Short name T830
Test name
Test status
Simulation time 37122125936 ps
CPU time 326.75 seconds
Started Jul 14 06:09:21 PM PDT 24
Finished Jul 14 06:14:48 PM PDT 24
Peak memory 3561144 kb
Host smart-4fc750af-ea70-4d91-b06c-916aaf00dbb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557601630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.557601630
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.4207433378
Short name T280
Test name
Test status
Simulation time 1683958418 ps
CPU time 9.85 seconds
Started Jul 14 06:09:20 PM PDT 24
Finished Jul 14 06:09:30 PM PDT 24
Peak memory 295620 kb
Host smart-c0e5a7e1-e07b-4b40-bf83-58d9450505ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207433378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.4207433378
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.380450895
Short name T1027
Test name
Test status
Simulation time 26136208371 ps
CPU time 6.85 seconds
Started Jul 14 06:09:22 PM PDT 24
Finished Jul 14 06:09:30 PM PDT 24
Peak memory 218568 kb
Host smart-5da6aae7-133c-42f6-9425-d5282b509597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380450895 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.380450895
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2507108066
Short name T1231
Test name
Test status
Simulation time 77448334 ps
CPU time 1.59 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 205564 kb
Host smart-31bdf635-43b7-4911-b9eb-93f495c914de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507108066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2507108066
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.595031545
Short name T1386
Test name
Test status
Simulation time 37924637 ps
CPU time 0.63 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 204684 kb
Host smart-5c1b5c44-66d5-46b5-8cf6-3dacc8cab54f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595031545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.595031545
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3235491523
Short name T1395
Test name
Test status
Simulation time 193296921 ps
CPU time 1.48 seconds
Started Jul 14 06:09:28 PM PDT 24
Finished Jul 14 06:09:30 PM PDT 24
Peak memory 213640 kb
Host smart-5bbde997-ce6c-404e-8b2f-61e53520caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235491523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3235491523
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1396350391
Short name T699
Test name
Test status
Simulation time 996939152 ps
CPU time 26.36 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:56 PM PDT 24
Peak memory 313308 kb
Host smart-f98fd1c0-86ea-4c3f-af84-67d1ce8edc7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396350391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1396350391
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1041563959
Short name T501
Test name
Test status
Simulation time 29965926455 ps
CPU time 90.97 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:10:59 PM PDT 24
Peak memory 526812 kb
Host smart-73420673-cfab-44e6-b755-efa931032ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041563959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1041563959
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2379979231
Short name T1303
Test name
Test status
Simulation time 7078881077 ps
CPU time 50.2 seconds
Started Jul 14 06:09:28 PM PDT 24
Finished Jul 14 06:10:19 PM PDT 24
Peak memory 629136 kb
Host smart-0b5c972e-e79c-4513-aadf-e2c01fff38f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379979231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2379979231
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3758277507
Short name T611
Test name
Test status
Simulation time 366373318 ps
CPU time 1.04 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:09:28 PM PDT 24
Peak memory 205200 kb
Host smart-95853fa8-4fff-4855-a977-379973c9477a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758277507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3758277507
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.560868470
Short name T359
Test name
Test status
Simulation time 215619510 ps
CPU time 5.27 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:09:33 PM PDT 24
Peak memory 205448 kb
Host smart-8ac47a31-ed92-4d70-8d90-300bef505934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560868470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
560868470
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1017103110
Short name T1555
Test name
Test status
Simulation time 21008607664 ps
CPU time 123.17 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:11:33 PM PDT 24
Peak memory 1309048 kb
Host smart-bb6e3fa9-d874-41f8-95dc-0d6eb4143667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017103110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1017103110
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3325682943
Short name T766
Test name
Test status
Simulation time 382767231 ps
CPU time 16.11 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:09:55 PM PDT 24
Peak memory 205464 kb
Host smart-a2efe23e-6fbd-4e91-9eaa-dac5e24a02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325682943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3325682943
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_override.1176094657
Short name T890
Test name
Test status
Simulation time 48368519 ps
CPU time 0.67 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:09:31 PM PDT 24
Peak memory 205196 kb
Host smart-1773aaff-4fda-4b7a-9bf1-7ae986070dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176094657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1176094657
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3404174774
Short name T1466
Test name
Test status
Simulation time 27769279220 ps
CPU time 1434.17 seconds
Started Jul 14 06:09:33 PM PDT 24
Finished Jul 14 06:33:28 PM PDT 24
Peak memory 523724 kb
Host smart-46d3fe6e-67ab-4cad-a6ed-d0faada4d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404174774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3404174774
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.3323033421
Short name T1709
Test name
Test status
Simulation time 6050131704 ps
CPU time 189.34 seconds
Started Jul 14 06:09:31 PM PDT 24
Finished Jul 14 06:12:40 PM PDT 24
Peak memory 1566336 kb
Host smart-a830296c-548c-45c9-95fa-6d156cadb45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323033421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3323033421
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4081547849
Short name T1710
Test name
Test status
Simulation time 9560065074 ps
CPU time 44.92 seconds
Started Jul 14 06:09:29 PM PDT 24
Finished Jul 14 06:10:15 PM PDT 24
Peak memory 455244 kb
Host smart-f55b2b2d-20e1-4c2e-92d8-6ed1bbf93f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081547849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4081547849
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.252043899
Short name T1275
Test name
Test status
Simulation time 587586147 ps
CPU time 9.33 seconds
Started Jul 14 06:09:30 PM PDT 24
Finished Jul 14 06:09:40 PM PDT 24
Peak memory 221732 kb
Host smart-524ef4b8-99b7-4f30-abf0-bb3dc08e230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252043899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.252043899
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1352275550
Short name T1698
Test name
Test status
Simulation time 530065830 ps
CPU time 2.91 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:40 PM PDT 24
Peak memory 216540 kb
Host smart-0f87a62e-a3a0-417a-becb-df320f3df358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352275550 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1352275550
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2744602852
Short name T535
Test name
Test status
Simulation time 607898829 ps
CPU time 1.15 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 205344 kb
Host smart-58682e41-671b-4425-88f6-e6e6ddaf82fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744602852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2744602852
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.441935509
Short name T147
Test name
Test status
Simulation time 362590744 ps
CPU time 1.13 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 213560 kb
Host smart-718b032f-d233-460e-a575-7f2c39fbf9d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441935509 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.441935509
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.787307982
Short name T265
Test name
Test status
Simulation time 2253463396 ps
CPU time 2.88 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 205660 kb
Host smart-3b4b842f-b68c-40e1-b340-c2549676a046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787307982 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.787307982
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2648708906
Short name T316
Test name
Test status
Simulation time 175586408 ps
CPU time 0.97 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:39 PM PDT 24
Peak memory 205436 kb
Host smart-3b0dacb8-0816-466e-bf76-ec8595c8cb76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648708906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2648708906
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1628579694
Short name T1217
Test name
Test status
Simulation time 1051085841 ps
CPU time 4.67 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:09:44 PM PDT 24
Peak memory 213964 kb
Host smart-f2439fa0-f810-46df-8cbf-db2f90b63059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628579694 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1628579694
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2225418608
Short name T162
Test name
Test status
Simulation time 4697031650 ps
CPU time 3.03 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 205572 kb
Host smart-fe46fdd6-dbf1-435d-a321-b920eb46398e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225418608 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2225418608
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.1013932310
Short name T966
Test name
Test status
Simulation time 1461477634 ps
CPU time 3.05 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:09:39 PM PDT 24
Peak memory 213780 kb
Host smart-4bb206b0-8e2e-46f6-883e-accb51411ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013932310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.1013932310
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.611070351
Short name T714
Test name
Test status
Simulation time 1012386427 ps
CPU time 2.45 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:40 PM PDT 24
Peak memory 205564 kb
Host smart-0896944f-20c0-4b7d-9799-a1c5daec98c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611070351 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.611070351
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.1621138148
Short name T1684
Test name
Test status
Simulation time 150754348 ps
CPU time 1.63 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:09:38 PM PDT 24
Peak memory 222256 kb
Host smart-50619736-0603-49e6-a700-82572d03d6cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621138148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.1621138148
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.2021180064
Short name T1213
Test name
Test status
Simulation time 620036649 ps
CPU time 5.09 seconds
Started Jul 14 06:09:35 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 219224 kb
Host smart-ee1eab29-9893-44e4-9826-767226c9c1b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021180064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.2021180064
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.1488165487
Short name T875
Test name
Test status
Simulation time 613943552 ps
CPU time 2.53 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 205380 kb
Host smart-e4555be4-eb40-406b-8cd1-7405fd63f9ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488165487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.1488165487
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.692477021
Short name T476
Test name
Test status
Simulation time 773901795 ps
CPU time 9.73 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:09:37 PM PDT 24
Peak memory 213768 kb
Host smart-9631512a-5f5b-47d7-8a44-6f60b876f077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692477021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.692477021
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.2106820935
Short name T661
Test name
Test status
Simulation time 10346529770 ps
CPU time 29.9 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:10:07 PM PDT 24
Peak memory 254572 kb
Host smart-0b226dc9-85a9-42cb-a638-b988b89aaaee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106820935 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.2106820935
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1994744832
Short name T629
Test name
Test status
Simulation time 3285356846 ps
CPU time 71.9 seconds
Started Jul 14 06:09:30 PM PDT 24
Finished Jul 14 06:10:42 PM PDT 24
Peak memory 218472 kb
Host smart-b8c33584-e359-49e0-aab5-c8e21b39f789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994744832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1994744832
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.432784924
Short name T1712
Test name
Test status
Simulation time 47732786795 ps
CPU time 1059.74 seconds
Started Jul 14 06:09:27 PM PDT 24
Finished Jul 14 06:27:08 PM PDT 24
Peak memory 6948800 kb
Host smart-1d38c615-66b1-4bde-94b4-35cd30b32f34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432784924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.432784924
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1408943169
Short name T771
Test name
Test status
Simulation time 4065633961 ps
CPU time 8.82 seconds
Started Jul 14 06:09:30 PM PDT 24
Finished Jul 14 06:09:39 PM PDT 24
Peak memory 286268 kb
Host smart-93d07143-0bf9-4007-ac9d-969d1c380c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408943169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1408943169
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.4053641620
Short name T1037
Test name
Test status
Simulation time 1417955328 ps
CPU time 7.72 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:09:47 PM PDT 24
Peak memory 221980 kb
Host smart-ab3253cf-2735-49ed-840f-af699ebd4e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053641620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.4053641620
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.4124336843
Short name T1263
Test name
Test status
Simulation time 247367554 ps
CPU time 3.69 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:09:41 PM PDT 24
Peak memory 205600 kb
Host smart-0d14fe3d-6239-445a-8da7-40c19c916530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124336843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.4124336843
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3171388531
Short name T1412
Test name
Test status
Simulation time 16755295 ps
CPU time 0.66 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:02 PM PDT 24
Peak memory 204852 kb
Host smart-53801e61-ae39-42dd-b107-1e4defb3f16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171388531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3171388531
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3881403487
Short name T1153
Test name
Test status
Simulation time 151355161 ps
CPU time 3.08 seconds
Started Jul 14 06:01:46 PM PDT 24
Finished Jul 14 06:01:50 PM PDT 24
Peak memory 213688 kb
Host smart-a9a540f9-5e08-430f-966b-036b2aaa1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881403487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3881403487
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.570244476
Short name T1227
Test name
Test status
Simulation time 354173622 ps
CPU time 16.09 seconds
Started Jul 14 06:01:41 PM PDT 24
Finished Jul 14 06:01:58 PM PDT 24
Peak memory 250032 kb
Host smart-3cc1ec53-58e9-4990-86bc-82c6fbe94da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570244476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.570244476
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3312236224
Short name T565
Test name
Test status
Simulation time 2916840254 ps
CPU time 190.96 seconds
Started Jul 14 06:01:42 PM PDT 24
Finished Jul 14 06:04:54 PM PDT 24
Peak memory 620636 kb
Host smart-ebd86651-4990-4885-a218-f9b9050233f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312236224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3312236224
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3391613801
Short name T409
Test name
Test status
Simulation time 1412933388 ps
CPU time 44.8 seconds
Started Jul 14 06:01:36 PM PDT 24
Finished Jul 14 06:02:21 PM PDT 24
Peak memory 519308 kb
Host smart-8d2944f3-253c-4ac2-903f-09c36e131134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391613801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3391613801
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.862029822
Short name T1568
Test name
Test status
Simulation time 104065515 ps
CPU time 1.09 seconds
Started Jul 14 06:01:41 PM PDT 24
Finished Jul 14 06:01:43 PM PDT 24
Peak memory 205228 kb
Host smart-cbee8215-0d56-4b41-b3b0-c08b089d6f40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862029822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.862029822
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.4243451979
Short name T1669
Test name
Test status
Simulation time 658954028 ps
CPU time 4.21 seconds
Started Jul 14 06:01:41 PM PDT 24
Finished Jul 14 06:01:46 PM PDT 24
Peak memory 205388 kb
Host smart-5dc7b729-89a5-4776-abf5-bf14335fdee7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243451979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
4243451979
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.37022480
Short name T521
Test name
Test status
Simulation time 21281886472 ps
CPU time 405.69 seconds
Started Jul 14 06:01:35 PM PDT 24
Finished Jul 14 06:08:22 PM PDT 24
Peak memory 1508924 kb
Host smart-d9de4dcb-2e5d-4df7-a14c-f2481d89fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37022480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.37022480
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1137051384
Short name T1426
Test name
Test status
Simulation time 2529664290 ps
CPU time 29.9 seconds
Started Jul 14 06:01:52 PM PDT 24
Finished Jul 14 06:02:22 PM PDT 24
Peak memory 205564 kb
Host smart-038f59b4-6be5-47cc-89c9-041627a5416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137051384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1137051384
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1823569448
Short name T1701
Test name
Test status
Simulation time 94443145 ps
CPU time 1.45 seconds
Started Jul 14 06:01:43 PM PDT 24
Finished Jul 14 06:01:46 PM PDT 24
Peak memory 221592 kb
Host smart-8fe68589-60f4-4654-9044-4f07d7f3427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823569448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1823569448
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2764751160
Short name T133
Test name
Test status
Simulation time 48728388 ps
CPU time 0.69 seconds
Started Jul 14 06:01:41 PM PDT 24
Finished Jul 14 06:01:43 PM PDT 24
Peak memory 205220 kb
Host smart-b9da2547-c85a-41ff-9849-c8574c38039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764751160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2764751160
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.97431081
Short name T716
Test name
Test status
Simulation time 7227201426 ps
CPU time 119.83 seconds
Started Jul 14 06:01:45 PM PDT 24
Finished Jul 14 06:03:46 PM PDT 24
Peak memory 584500 kb
Host smart-440e0754-07e3-4d60-9870-c7a01b74269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97431081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.97431081
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.1730978260
Short name T1557
Test name
Test status
Simulation time 6177975677 ps
CPU time 20.38 seconds
Started Jul 14 06:01:43 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 205492 kb
Host smart-00db0728-16cc-4b66-9d1a-1233389d8c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730978260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.1730978260
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.664742424
Short name T1668
Test name
Test status
Simulation time 9492057342 ps
CPU time 21.75 seconds
Started Jul 14 06:01:33 PM PDT 24
Finished Jul 14 06:01:55 PM PDT 24
Peak memory 314544 kb
Host smart-ce0b8f93-01bb-4166-9448-9ae996521b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664742424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.664742424
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1072071808
Short name T1620
Test name
Test status
Simulation time 653853759 ps
CPU time 29.81 seconds
Started Jul 14 06:01:45 PM PDT 24
Finished Jul 14 06:02:16 PM PDT 24
Peak memory 213628 kb
Host smart-2480befc-3b49-4de6-ab5d-aeae7a6864d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072071808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1072071808
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1035970013
Short name T1119
Test name
Test status
Simulation time 7575205944 ps
CPU time 4.72 seconds
Started Jul 14 06:01:44 PM PDT 24
Finished Jul 14 06:01:49 PM PDT 24
Peak memory 213892 kb
Host smart-abde050b-c61c-4f05-ad32-769c4f10380a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035970013 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1035970013
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1306276831
Short name T798
Test name
Test status
Simulation time 481722604 ps
CPU time 1.21 seconds
Started Jul 14 06:01:49 PM PDT 24
Finished Jul 14 06:01:51 PM PDT 24
Peak memory 205552 kb
Host smart-02e7424a-e49b-4c3a-b781-7a11f4a61ded
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306276831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1306276831
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.894375836
Short name T1723
Test name
Test status
Simulation time 626805504 ps
CPU time 1.5 seconds
Started Jul 14 06:01:45 PM PDT 24
Finished Jul 14 06:01:48 PM PDT 24
Peak memory 205608 kb
Host smart-84920b91-65c4-499b-ba83-4ee77de78955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894375836 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.894375836
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.468250254
Short name T1480
Test name
Test status
Simulation time 697081939 ps
CPU time 2.47 seconds
Started Jul 14 06:01:53 PM PDT 24
Finished Jul 14 06:01:56 PM PDT 24
Peak memory 205556 kb
Host smart-1c81fdb1-b650-4794-88fc-9b5613489087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468250254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.468250254
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.799971390
Short name T748
Test name
Test status
Simulation time 135843424 ps
CPU time 1.17 seconds
Started Jul 14 06:01:50 PM PDT 24
Finished Jul 14 06:01:52 PM PDT 24
Peak memory 205388 kb
Host smart-eef92099-572a-4525-8291-6e28916adbeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799971390 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.799971390
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3420649093
Short name T1619
Test name
Test status
Simulation time 3090395309 ps
CPU time 4.76 seconds
Started Jul 14 06:01:46 PM PDT 24
Finished Jul 14 06:01:51 PM PDT 24
Peak memory 222008 kb
Host smart-443374d5-dc7d-4038-803b-a68555e9cc42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420649093 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3420649093
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3305212725
Short name T1649
Test name
Test status
Simulation time 18664008238 ps
CPU time 21.97 seconds
Started Jul 14 06:01:47 PM PDT 24
Finished Jul 14 06:02:09 PM PDT 24
Peak memory 566888 kb
Host smart-c4a8f414-7587-4a8b-8f38-5c01a6b8dde6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305212725 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3305212725
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.4285625466
Short name T128
Test name
Test status
Simulation time 1033045664 ps
CPU time 2.77 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:02:03 PM PDT 24
Peak memory 213804 kb
Host smart-145a6491-bf43-40ae-aeac-7cf360340d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285625466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.4285625466
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.2700944762
Short name T1567
Test name
Test status
Simulation time 1874473009 ps
CPU time 2.35 seconds
Started Jul 14 06:01:56 PM PDT 24
Finished Jul 14 06:01:58 PM PDT 24
Peak memory 205660 kb
Host smart-fb28f548-5382-4764-98cf-c96613d481db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700944762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.2700944762
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_txstretch.1404377193
Short name T943
Test name
Test status
Simulation time 236040301 ps
CPU time 1.34 seconds
Started Jul 14 06:01:49 PM PDT 24
Finished Jul 14 06:01:51 PM PDT 24
Peak memory 222376 kb
Host smart-81e9663f-52df-4768-a380-b658bea5b2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404377193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_nack_txstretch.1404377193
Directory /workspace/5.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/5.i2c_target_perf.1713857962
Short name T1276
Test name
Test status
Simulation time 3563353891 ps
CPU time 5.33 seconds
Started Jul 14 06:01:47 PM PDT 24
Finished Jul 14 06:01:53 PM PDT 24
Peak memory 217568 kb
Host smart-768fd56c-3acd-40ba-a683-c5604271352f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713857962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.1713857962
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.3534539945
Short name T1331
Test name
Test status
Simulation time 1666640116 ps
CPU time 2.27 seconds
Started Jul 14 06:01:52 PM PDT 24
Finished Jul 14 06:01:55 PM PDT 24
Peak memory 205428 kb
Host smart-f499b7e4-05ab-49c3-b9af-837e68959166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534539945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_smbus_maxlen.3534539945
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2164346663
Short name T650
Test name
Test status
Simulation time 3315403455 ps
CPU time 21.77 seconds
Started Jul 14 06:01:44 PM PDT 24
Finished Jul 14 06:02:06 PM PDT 24
Peak memory 213860 kb
Host smart-4ea1f419-fd1b-4d77-9fc8-0aa39ec2d8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164346663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2164346663
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.3632967240
Short name T1084
Test name
Test status
Simulation time 28914546823 ps
CPU time 488.14 seconds
Started Jul 14 06:01:45 PM PDT 24
Finished Jul 14 06:09:55 PM PDT 24
Peak memory 3486768 kb
Host smart-d1628ebd-2dbd-430c-aa2d-1f92130d74cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632967240 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.3632967240
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3967883680
Short name T772
Test name
Test status
Simulation time 2036926158 ps
CPU time 22.57 seconds
Started Jul 14 06:01:44 PM PDT 24
Finished Jul 14 06:02:07 PM PDT 24
Peak memory 231424 kb
Host smart-3ca5c5ec-9a1d-4c11-bd7e-8ac5829ef830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967883680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3967883680
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3946106788
Short name T1430
Test name
Test status
Simulation time 32495798990 ps
CPU time 90.56 seconds
Started Jul 14 06:01:44 PM PDT 24
Finished Jul 14 06:03:16 PM PDT 24
Peak memory 1522544 kb
Host smart-32bceaf7-244d-4477-af9b-593519022488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946106788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3946106788
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2211061494
Short name T1062
Test name
Test status
Simulation time 2201390112 ps
CPU time 5.76 seconds
Started Jul 14 06:01:43 PM PDT 24
Finished Jul 14 06:01:50 PM PDT 24
Peak memory 221036 kb
Host smart-02923f7c-010f-4455-9845-2453654fc3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211061494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2211061494
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1721172798
Short name T713
Test name
Test status
Simulation time 1189000290 ps
CPU time 6.94 seconds
Started Jul 14 06:01:45 PM PDT 24
Finished Jul 14 06:01:53 PM PDT 24
Peak memory 219540 kb
Host smart-75df06f1-8374-49cb-83f3-ac2f34b2ed0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721172798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1721172798
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.4068042169
Short name T1046
Test name
Test status
Simulation time 511474400 ps
CPU time 7.11 seconds
Started Jul 14 06:01:48 PM PDT 24
Finished Jul 14 06:01:56 PM PDT 24
Peak memory 205472 kb
Host smart-6826d764-fac3-4a38-8538-a488145b9b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068042169 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.4068042169
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2664715842
Short name T760
Test name
Test status
Simulation time 17518123 ps
CPU time 0.65 seconds
Started Jul 14 06:02:03 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 204828 kb
Host smart-69be85e2-e74b-4688-928a-ee23e457927e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664715842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2664715842
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3720290784
Short name T723
Test name
Test status
Simulation time 98800680 ps
CPU time 1.84 seconds
Started Jul 14 06:01:53 PM PDT 24
Finished Jul 14 06:01:56 PM PDT 24
Peak memory 213652 kb
Host smart-22d545b8-44ee-4af7-814e-286634dbdaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720290784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3720290784
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3208623128
Short name T939
Test name
Test status
Simulation time 1619441694 ps
CPU time 23.85 seconds
Started Jul 14 06:01:50 PM PDT 24
Finished Jul 14 06:02:14 PM PDT 24
Peak memory 301536 kb
Host smart-bf790170-58de-417f-b777-73ff36a578db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208623128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3208623128
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2754978499
Short name T1057
Test name
Test status
Simulation time 3219923773 ps
CPU time 231.09 seconds
Started Jul 14 06:01:50 PM PDT 24
Finished Jul 14 06:05:41 PM PDT 24
Peak memory 741068 kb
Host smart-9362ec8c-bddd-4de8-bfea-74e97337d2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754978499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2754978499
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3650967170
Short name T1405
Test name
Test status
Simulation time 1375373387 ps
CPU time 87.96 seconds
Started Jul 14 06:01:51 PM PDT 24
Finished Jul 14 06:03:20 PM PDT 24
Peak memory 454792 kb
Host smart-e8ec1b4c-7e19-44c3-902b-f34e5fefca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650967170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3650967170
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2369832902
Short name T942
Test name
Test status
Simulation time 73111385 ps
CPU time 0.98 seconds
Started Jul 14 06:01:50 PM PDT 24
Finished Jul 14 06:01:51 PM PDT 24
Peak memory 205200 kb
Host smart-4a0b4c99-95f7-459d-9f25-dce7e6ebfb0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369832902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2369832902
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3495441078
Short name T1329
Test name
Test status
Simulation time 343276668 ps
CPU time 3.88 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:05 PM PDT 24
Peak memory 205496 kb
Host smart-4ac9f3ec-1d3a-4dbf-baf4-796819998a7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495441078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3495441078
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.124183011
Short name T626
Test name
Test status
Simulation time 12947347423 ps
CPU time 220.53 seconds
Started Jul 14 06:01:53 PM PDT 24
Finished Jul 14 06:05:34 PM PDT 24
Peak memory 1009096 kb
Host smart-32a16f88-c22a-4fe4-8599-45acdb98135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124183011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.124183011
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3009979126
Short name T244
Test name
Test status
Simulation time 503061558 ps
CPU time 6.49 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:08 PM PDT 24
Peak memory 205440 kb
Host smart-b71a2bf3-7895-4783-8bd6-557cea1695a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009979126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3009979126
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_override.2869143624
Short name T395
Test name
Test status
Simulation time 127452450 ps
CPU time 0.67 seconds
Started Jul 14 06:01:51 PM PDT 24
Finished Jul 14 06:01:52 PM PDT 24
Peak memory 205184 kb
Host smart-2cea0b58-7118-4154-b233-8bbc55773a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869143624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2869143624
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.485163546
Short name T754
Test name
Test status
Simulation time 1223774822 ps
CPU time 49.16 seconds
Started Jul 14 06:01:53 PM PDT 24
Finished Jul 14 06:02:43 PM PDT 24
Peak memory 229908 kb
Host smart-ebeec10c-2485-48e0-963f-2d0b4d0179e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485163546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.485163546
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.511435262
Short name T928
Test name
Test status
Simulation time 242567684 ps
CPU time 6.39 seconds
Started Jul 14 06:01:51 PM PDT 24
Finished Jul 14 06:01:58 PM PDT 24
Peak memory 221648 kb
Host smart-017b175a-7c4c-4cb2-972a-d2000d0c6ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511435262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.511435262
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3744094188
Short name T1444
Test name
Test status
Simulation time 4795086456 ps
CPU time 18.65 seconds
Started Jul 14 06:01:49 PM PDT 24
Finished Jul 14 06:02:09 PM PDT 24
Peak memory 301820 kb
Host smart-c14527ee-d45e-468a-aaa8-80c6fb21bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744094188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3744094188
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2152846778
Short name T786
Test name
Test status
Simulation time 1659413473 ps
CPU time 13.97 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:15 PM PDT 24
Peak memory 230024 kb
Host smart-755ce4df-fca3-41ac-8ba1-78b398b54f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152846778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2152846778
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.727119682
Short name T279
Test name
Test status
Simulation time 1334847832 ps
CPU time 7 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:08 PM PDT 24
Peak memory 219168 kb
Host smart-843f4ad1-7559-4cdb-a41d-a1b24ebcaeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727119682 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.727119682
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2443616511
Short name T332
Test name
Test status
Simulation time 1419956585 ps
CPU time 1.12 seconds
Started Jul 14 06:02:01 PM PDT 24
Finished Jul 14 06:02:03 PM PDT 24
Peak memory 205412 kb
Host smart-74294164-cabe-4543-a19e-e84c28fee357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443616511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2443616511
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.648452930
Short name T823
Test name
Test status
Simulation time 184194629 ps
CPU time 0.78 seconds
Started Jul 14 06:01:58 PM PDT 24
Finished Jul 14 06:02:00 PM PDT 24
Peak memory 205448 kb
Host smart-8f98e662-0386-4f62-a8ef-0c1aa6278306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648452930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.648452930
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.3920605381
Short name T926
Test name
Test status
Simulation time 2557708637 ps
CPU time 3.42 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 205684 kb
Host smart-8640bd05-f42c-4911-8341-16c9ae36d48f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920605381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3920605381
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.408467941
Short name T1140
Test name
Test status
Simulation time 167196737 ps
CPU time 1.74 seconds
Started Jul 14 06:02:01 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 205444 kb
Host smart-3e19727c-c157-40e9-b17f-dfb9445956a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408467941 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.408467941
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.662940510
Short name T1465
Test name
Test status
Simulation time 2019416426 ps
CPU time 5.53 seconds
Started Jul 14 06:01:56 PM PDT 24
Finished Jul 14 06:02:02 PM PDT 24
Peak memory 221968 kb
Host smart-2f24271f-b0fc-4aa3-96d1-a3a30ebd951d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662940510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.662940510
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1145455259
Short name T553
Test name
Test status
Simulation time 7387126313 ps
CPU time 8.32 seconds
Started Jul 14 06:01:51 PM PDT 24
Finished Jul 14 06:02:00 PM PDT 24
Peak memory 205684 kb
Host smart-35c07871-6567-4223-9e96-e90a2ece9f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145455259 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1145455259
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.3786592029
Short name T1220
Test name
Test status
Simulation time 574320527 ps
CPU time 3.29 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 213844 kb
Host smart-a18c8fd3-3254-4e07-8902-0ccf5a3c937a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786592029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.3786592029
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.615798155
Short name T65
Test name
Test status
Simulation time 4222169403 ps
CPU time 2.42 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 205600 kb
Host smart-100ee6ac-62cc-494c-b979-b0b78c221387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615798155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.615798155
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.981576540
Short name T1142
Test name
Test status
Simulation time 121599975 ps
CPU time 1.66 seconds
Started Jul 14 06:02:01 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 222404 kb
Host smart-2b9d3639-dd3f-45c0-83f7-3a5d90aea051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981576540 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_nack_txstretch.981576540
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.2893134812
Short name T1679
Test name
Test status
Simulation time 737327164 ps
CPU time 2.89 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 219884 kb
Host smart-f28bc50a-3dee-4f4a-9722-1c45a08962ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893134812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.2893134812
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.2551938087
Short name T594
Test name
Test status
Simulation time 758512099 ps
CPU time 2.02 seconds
Started Jul 14 06:02:02 PM PDT 24
Finished Jul 14 06:02:05 PM PDT 24
Peak memory 205336 kb
Host smart-dcace643-2829-4a41-879a-94e451354ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551938087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.2551938087
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2698689420
Short name T75
Test name
Test status
Simulation time 2408929224 ps
CPU time 36.86 seconds
Started Jul 14 06:01:52 PM PDT 24
Finished Jul 14 06:02:29 PM PDT 24
Peak memory 213780 kb
Host smart-a0299fd7-7b80-4476-8cec-4f367e55c8e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698689420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2698689420
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.72891752
Short name T1234
Test name
Test status
Simulation time 47965942050 ps
CPU time 116.69 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:03:56 PM PDT 24
Peak memory 1204496 kb
Host smart-ef2dc322-37df-48bd-9001-0a21ad6af6c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72891752 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.i2c_target_stress_all.72891752
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2026535129
Short name T596
Test name
Test status
Simulation time 11410894863 ps
CPU time 31.23 seconds
Started Jul 14 06:01:56 PM PDT 24
Finished Jul 14 06:02:28 PM PDT 24
Peak memory 230208 kb
Host smart-ba651482-ff86-4de5-9d25-5e1e28d3a1ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026535129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2026535129
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1518334909
Short name T505
Test name
Test status
Simulation time 11574694852 ps
CPU time 12.75 seconds
Started Jul 14 06:01:50 PM PDT 24
Finished Jul 14 06:02:03 PM PDT 24
Peak memory 205648 kb
Host smart-486c2242-4a24-4f3e-b2da-5c3e451fa364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518334909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1518334909
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.159969256
Short name T264
Test name
Test status
Simulation time 1103147587 ps
CPU time 6.86 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:02:07 PM PDT 24
Peak memory 213848 kb
Host smart-98a2f79e-ff9f-489c-b97b-99e64158a0a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159969256 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.159969256
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.336110354
Short name T868
Test name
Test status
Simulation time 157563882 ps
CPU time 3.49 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:05 PM PDT 24
Peak memory 205584 kb
Host smart-74ebbef0-0121-474f-b030-a60ddf8017cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336110354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.336110354
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2563052960
Short name T9
Test name
Test status
Simulation time 19673912 ps
CPU time 0.62 seconds
Started Jul 14 06:02:14 PM PDT 24
Finished Jul 14 06:02:15 PM PDT 24
Peak memory 204788 kb
Host smart-ccbe7c82-6d67-4990-9df6-3b6c67d60eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563052960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2563052960
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.681751489
Short name T698
Test name
Test status
Simulation time 253381915 ps
CPU time 2.24 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:12 PM PDT 24
Peak memory 217496 kb
Host smart-303349f9-7995-4ab6-951d-33fc0915ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681751489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.681751489
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.21049506
Short name T1573
Test name
Test status
Simulation time 282920420 ps
CPU time 5.11 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:02:06 PM PDT 24
Peak memory 249052 kb
Host smart-d3518ed8-a9ea-4d1d-a328-ed0ef0f2f85f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21049506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.21049506
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.395525635
Short name T40
Test name
Test status
Simulation time 2533842248 ps
CPU time 62.79 seconds
Started Jul 14 06:02:01 PM PDT 24
Finished Jul 14 06:03:05 PM PDT 24
Peak memory 433704 kb
Host smart-127c8142-00fd-4f5e-9c6b-edebf2c59421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395525635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.395525635
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2391527579
Short name T479
Test name
Test status
Simulation time 1262328465 ps
CPU time 88.31 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:03:30 PM PDT 24
Peak memory 518764 kb
Host smart-55b6859b-1bda-47a6-b006-267a08cae119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391527579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2391527579
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2414970935
Short name T230
Test name
Test status
Simulation time 170604301 ps
CPU time 1.37 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:02:01 PM PDT 24
Peak memory 205208 kb
Host smart-d3df15c3-0fba-42be-bfe6-d46b6f56e404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414970935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2414970935
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1176711646
Short name T1391
Test name
Test status
Simulation time 2053698520 ps
CPU time 3.96 seconds
Started Jul 14 06:02:03 PM PDT 24
Finished Jul 14 06:02:08 PM PDT 24
Peak memory 230060 kb
Host smart-b17639b9-bde0-4338-923f-4b6c7e7fc2de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176711646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1176711646
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.249559800
Short name T1696
Test name
Test status
Simulation time 11665003719 ps
CPU time 76.61 seconds
Started Jul 14 06:02:00 PM PDT 24
Finished Jul 14 06:03:17 PM PDT 24
Peak memory 990504 kb
Host smart-76923c2e-23d8-4653-a05c-9adf660483a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249559800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.249559800
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1040521349
Short name T897
Test name
Test status
Simulation time 1242895730 ps
CPU time 9.38 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 205448 kb
Host smart-3c3e2832-7a78-4fac-9a0a-5b93f2e02564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040521349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1040521349
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.769145268
Short name T1257
Test name
Test status
Simulation time 22975388 ps
CPU time 0.72 seconds
Started Jul 14 06:02:03 PM PDT 24
Finished Jul 14 06:02:04 PM PDT 24
Peak memory 205156 kb
Host smart-67d9856b-7aba-4e9e-8357-3c8626448540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769145268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.769145268
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1626401011
Short name T859
Test name
Test status
Simulation time 48003627532 ps
CPU time 571 seconds
Started Jul 14 06:01:59 PM PDT 24
Finished Jul 14 06:11:31 PM PDT 24
Peak memory 1786080 kb
Host smart-2935f29e-7f63-4796-9612-4b9340cf5379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626401011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1626401011
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.596718869
Short name T366
Test name
Test status
Simulation time 6227593589 ps
CPU time 20.28 seconds
Started Jul 14 06:01:58 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 205544 kb
Host smart-4329396d-42fc-4168-b0bc-f2c212d08151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596718869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.596718869
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.342784447
Short name T829
Test name
Test status
Simulation time 1192704992 ps
CPU time 53.01 seconds
Started Jul 14 06:01:58 PM PDT 24
Finished Jul 14 06:02:52 PM PDT 24
Peak memory 274496 kb
Host smart-10aa8d7e-e961-4e49-8075-fe3a4fe698be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342784447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.342784447
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1425644791
Short name T1036
Test name
Test status
Simulation time 2894063412 ps
CPU time 11.65 seconds
Started Jul 14 06:02:10 PM PDT 24
Finished Jul 14 06:02:22 PM PDT 24
Peak memory 216272 kb
Host smart-2aba98af-d1a1-47ce-87ef-bd08a50e5ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425644791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1425644791
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2529461159
Short name T456
Test name
Test status
Simulation time 1176367475 ps
CPU time 6.74 seconds
Started Jul 14 06:02:08 PM PDT 24
Finished Jul 14 06:02:15 PM PDT 24
Peak memory 219140 kb
Host smart-345967ca-b345-400d-952a-ac60e65994fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529461159 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2529461159
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.658715910
Short name T1091
Test name
Test status
Simulation time 261027577 ps
CPU time 1.05 seconds
Started Jul 14 06:02:08 PM PDT 24
Finished Jul 14 06:02:11 PM PDT 24
Peak memory 205372 kb
Host smart-d4dc0ff4-6357-4b18-ae48-5cc8b1bf0380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658715910 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.658715910
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1840882474
Short name T1320
Test name
Test status
Simulation time 584972313 ps
CPU time 1.29 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:12 PM PDT 24
Peak memory 213780 kb
Host smart-3358892a-00bc-4c02-8e68-b14b2298f04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840882474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1840882474
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2915016606
Short name T569
Test name
Test status
Simulation time 447576719 ps
CPU time 2.52 seconds
Started Jul 14 06:02:07 PM PDT 24
Finished Jul 14 06:02:10 PM PDT 24
Peak memory 205568 kb
Host smart-67061ac9-0613-45bb-89c7-e84adcb2c8c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915016606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2915016606
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.1543399235
Short name T365
Test name
Test status
Simulation time 495488581 ps
CPU time 1.41 seconds
Started Jul 14 06:02:06 PM PDT 24
Finished Jul 14 06:02:08 PM PDT 24
Peak memory 205428 kb
Host smart-04b1996c-fe6d-49bf-8495-0a7618b81589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543399235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.1543399235
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1710897516
Short name T1677
Test name
Test status
Simulation time 1302635401 ps
CPU time 7 seconds
Started Jul 14 06:02:06 PM PDT 24
Finished Jul 14 06:02:14 PM PDT 24
Peak memory 220892 kb
Host smart-67be6cf5-ec17-4f5d-86ef-07a46fe4b30f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710897516 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1710897516
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1282376757
Short name T1499
Test name
Test status
Simulation time 11305263757 ps
CPU time 25.22 seconds
Started Jul 14 06:02:06 PM PDT 24
Finished Jul 14 06:02:31 PM PDT 24
Peak memory 622440 kb
Host smart-9775b36a-6a52-4d2e-a35d-4652996ae0a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282376757 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1282376757
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.3190836705
Short name T1440
Test name
Test status
Simulation time 554600134 ps
CPU time 2.95 seconds
Started Jul 14 06:02:07 PM PDT 24
Finished Jul 14 06:02:11 PM PDT 24
Peak memory 214084 kb
Host smart-18d9a865-f0e6-43bf-bd17-f50c9403ac4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190836705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.3190836705
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.1041151367
Short name T1529
Test name
Test status
Simulation time 983031976 ps
CPU time 2.59 seconds
Started Jul 14 06:02:07 PM PDT 24
Finished Jul 14 06:02:09 PM PDT 24
Peak memory 205504 kb
Host smart-0dbbe8fe-89dd-4737-9392-b982b94aeedb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041151367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.1041151367
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.3832513558
Short name T1504
Test name
Test status
Simulation time 896950549 ps
CPU time 6.65 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:16 PM PDT 24
Peak memory 230108 kb
Host smart-fd557363-57eb-48a3-ad68-1f5b576cc1e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832513558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.3832513558
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.4138617919
Short name T815
Test name
Test status
Simulation time 3567460365 ps
CPU time 2.64 seconds
Started Jul 14 06:02:07 PM PDT 24
Finished Jul 14 06:02:11 PM PDT 24
Peak memory 205464 kb
Host smart-e0eb998e-ef31-4ea1-b546-9e039f7beadc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138617919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.4138617919
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2418002139
Short name T1527
Test name
Test status
Simulation time 316619590 ps
CPU time 10.24 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:20 PM PDT 24
Peak memory 213728 kb
Host smart-9608bd46-7806-4681-b48e-b098903dd17c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418002139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2418002139
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.740546902
Short name T1533
Test name
Test status
Simulation time 74606345869 ps
CPU time 56.47 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:03:07 PM PDT 24
Peak memory 306488 kb
Host smart-9d2445dd-e473-4475-81e1-22b232738ac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740546902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_target_stress_all.740546902
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3217540689
Short name T1725
Test name
Test status
Simulation time 1606436853 ps
CPU time 25.79 seconds
Started Jul 14 06:02:08 PM PDT 24
Finished Jul 14 06:02:35 PM PDT 24
Peak memory 233912 kb
Host smart-ecb3d159-6b6c-43df-9ded-d3ba96d68ba5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217540689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3217540689
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2792637477
Short name T1686
Test name
Test status
Simulation time 29117407664 ps
CPU time 176.18 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:05:06 PM PDT 24
Peak memory 2407832 kb
Host smart-6c4afbbe-954f-4f65-a055-952bd6faf60c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792637477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2792637477
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3515850410
Short name T86
Test name
Test status
Simulation time 4629453588 ps
CPU time 10.93 seconds
Started Jul 14 06:02:08 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 335120 kb
Host smart-0371c8cc-514c-4a33-ad8d-60550d374aef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515850410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3515850410
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1912237044
Short name T803
Test name
Test status
Simulation time 2596812440 ps
CPU time 7.22 seconds
Started Jul 14 06:02:14 PM PDT 24
Finished Jul 14 06:02:21 PM PDT 24
Peak memory 213836 kb
Host smart-03313a97-a5c3-4fcc-9bfb-33102c6ce1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912237044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1912237044
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.1676104434
Short name T1105
Test name
Test status
Simulation time 68361904 ps
CPU time 1.69 seconds
Started Jul 14 06:02:09 PM PDT 24
Finished Jul 14 06:02:12 PM PDT 24
Peak memory 205480 kb
Host smart-d701b9fe-8b3a-4666-8cad-93baee014357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676104434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.1676104434
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3928627226
Short name T591
Test name
Test status
Simulation time 26129724 ps
CPU time 0.66 seconds
Started Jul 14 06:02:31 PM PDT 24
Finished Jul 14 06:02:33 PM PDT 24
Peak memory 204752 kb
Host smart-fde7678c-9601-4e4a-8452-1ea34c6e0056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928627226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3928627226
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2608040915
Short name T552
Test name
Test status
Simulation time 448402658 ps
CPU time 1.87 seconds
Started Jul 14 06:02:31 PM PDT 24
Finished Jul 14 06:02:33 PM PDT 24
Peak memory 213744 kb
Host smart-4775f72b-9026-42ac-890d-7bc6e10a8205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608040915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2608040915
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2806581799
Short name T1501
Test name
Test status
Simulation time 703539753 ps
CPU time 9.2 seconds
Started Jul 14 06:02:16 PM PDT 24
Finished Jul 14 06:02:26 PM PDT 24
Peak memory 232796 kb
Host smart-0d3a3de1-e363-4847-b622-4b1e667e0c08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806581799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2806581799
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.237946208
Short name T645
Test name
Test status
Simulation time 12627224358 ps
CPU time 98.08 seconds
Started Jul 14 06:02:16 PM PDT 24
Finished Jul 14 06:03:55 PM PDT 24
Peak memory 680460 kb
Host smart-fd67efdb-666c-497f-b40e-0af329878e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237946208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.237946208
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2780984429
Short name T789
Test name
Test status
Simulation time 9762717355 ps
CPU time 83.06 seconds
Started Jul 14 06:02:22 PM PDT 24
Finished Jul 14 06:03:46 PM PDT 24
Peak memory 501716 kb
Host smart-01a20649-45d1-450c-8671-2f668ef62293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780984429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2780984429
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.467823389
Short name T1515
Test name
Test status
Simulation time 226031290 ps
CPU time 1.03 seconds
Started Jul 14 06:02:17 PM PDT 24
Finished Jul 14 06:02:18 PM PDT 24
Peak memory 205212 kb
Host smart-448f0085-f6eb-4292-82f8-6d191bfc1dab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467823389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.467823389
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1502885946
Short name T388
Test name
Test status
Simulation time 198936220 ps
CPU time 5.04 seconds
Started Jul 14 06:02:21 PM PDT 24
Finished Jul 14 06:02:27 PM PDT 24
Peak memory 242176 kb
Host smart-16cc7f46-3524-4e0b-9700-2bd77d923eed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502885946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1502885946
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1554869982
Short name T856
Test name
Test status
Simulation time 17048169305 ps
CPU time 104.13 seconds
Started Jul 14 06:02:16 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 1100648 kb
Host smart-cd6dd993-7d2a-446c-b557-128844b96a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554869982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1554869982
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2471578869
Short name T1389
Test name
Test status
Simulation time 3785300352 ps
CPU time 7.79 seconds
Started Jul 14 06:02:33 PM PDT 24
Finished Jul 14 06:02:41 PM PDT 24
Peak memory 205568 kb
Host smart-0a6d6711-7512-4782-a278-00fc8ef5db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471578869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2471578869
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.3213299391
Short name T947
Test name
Test status
Simulation time 101458237 ps
CPU time 0.67 seconds
Started Jul 14 06:02:18 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 205204 kb
Host smart-84b40d28-1f20-43c8-abb1-c892f9f38455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213299391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3213299391
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1131488616
Short name T157
Test name
Test status
Simulation time 1884067039 ps
CPU time 16.22 seconds
Started Jul 14 06:02:16 PM PDT 24
Finished Jul 14 06:02:33 PM PDT 24
Peak memory 284724 kb
Host smart-6645216b-9f0a-4be6-b091-cbe508b3794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131488616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1131488616
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.302713222
Short name T1090
Test name
Test status
Simulation time 828128777 ps
CPU time 3.78 seconds
Started Jul 14 06:02:15 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 233256 kb
Host smart-a713bdbc-5bbc-4f4f-8be0-0058874d2c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302713222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.302713222
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3043357451
Short name T951
Test name
Test status
Simulation time 1795799239 ps
CPU time 39.36 seconds
Started Jul 14 06:02:16 PM PDT 24
Finished Jul 14 06:02:56 PM PDT 24
Peak memory 441716 kb
Host smart-85e0dddc-369b-4e93-9816-967bd4c97872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043357451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3043357451
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1647283377
Short name T960
Test name
Test status
Simulation time 4459230393 ps
CPU time 21.29 seconds
Started Jul 14 06:02:17 PM PDT 24
Finished Jul 14 06:02:39 PM PDT 24
Peak memory 221936 kb
Host smart-e71fdd8c-9218-41a9-9c57-13d3433926fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647283377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1647283377
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2589239409
Short name T1168
Test name
Test status
Simulation time 899314194 ps
CPU time 4.45 seconds
Started Jul 14 06:02:29 PM PDT 24
Finished Jul 14 06:02:34 PM PDT 24
Peak memory 210076 kb
Host smart-a901929b-2b4f-4929-b06d-878c3ce4a4b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589239409 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2589239409
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3968946470
Short name T1640
Test name
Test status
Simulation time 163713486 ps
CPU time 1.14 seconds
Started Jul 14 06:02:28 PM PDT 24
Finished Jul 14 06:02:30 PM PDT 24
Peak memory 205556 kb
Host smart-c0c9cb74-3b03-42d1-9027-ec3f3485c9d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968946470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3968946470
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2875830176
Short name T574
Test name
Test status
Simulation time 107043850 ps
CPU time 0.91 seconds
Started Jul 14 06:02:30 PM PDT 24
Finished Jul 14 06:02:31 PM PDT 24
Peak memory 205448 kb
Host smart-32c44cb2-963f-43e8-b42a-faa0e6cde6d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875830176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2875830176
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2782243760
Short name T398
Test name
Test status
Simulation time 4459025556 ps
CPU time 3.12 seconds
Started Jul 14 06:02:32 PM PDT 24
Finished Jul 14 06:02:36 PM PDT 24
Peak memory 205668 kb
Host smart-8a20dda5-1be8-4f4d-90d1-752b1df5e222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782243760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2782243760
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.263948556
Short name T628
Test name
Test status
Simulation time 182170533 ps
CPU time 1.43 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 205408 kb
Host smart-61221cf5-cfdd-4621-af7e-c4dca588f1c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263948556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.263948556
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1745433908
Short name T127
Test name
Test status
Simulation time 1037214214 ps
CPU time 2.92 seconds
Started Jul 14 06:02:32 PM PDT 24
Finished Jul 14 06:02:36 PM PDT 24
Peak memory 213724 kb
Host smart-3fca63a0-6f62-4244-8c32-4ddea91075a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745433908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1745433908
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.86249580
Short name T1114
Test name
Test status
Simulation time 3792976944 ps
CPU time 6.18 seconds
Started Jul 14 06:02:28 PM PDT 24
Finished Jul 14 06:02:35 PM PDT 24
Peak memory 219100 kb
Host smart-c9c0833c-cf04-46f5-af12-e220ff6a36f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86249580 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.86249580
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2006342017
Short name T296
Test name
Test status
Simulation time 27662266003 ps
CPU time 296.6 seconds
Started Jul 14 06:02:29 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 3265992 kb
Host smart-0eb4bb71-d997-4758-80eb-0294f61bf7a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006342017 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2006342017
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.4236908274
Short name T1108
Test name
Test status
Simulation time 1462696947 ps
CPU time 2.83 seconds
Started Jul 14 06:02:31 PM PDT 24
Finished Jul 14 06:02:35 PM PDT 24
Peak memory 213856 kb
Host smart-8233c668-c4b7-4961-9120-374f363d5df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236908274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.4236908274
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.1800577788
Short name T826
Test name
Test status
Simulation time 530761671 ps
CPU time 2.5 seconds
Started Jul 14 06:02:30 PM PDT 24
Finished Jul 14 06:02:33 PM PDT 24
Peak memory 205568 kb
Host smart-8568842f-a882-4ec0-a85f-40b82a3a5f48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800577788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1800577788
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_txstretch.3963026950
Short name T533
Test name
Test status
Simulation time 282480895 ps
CPU time 1.59 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 222412 kb
Host smart-cb7e579a-1270-4187-9ce2-7c1a44f13739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963026950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_nack_txstretch.3963026950
Directory /workspace/8.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/8.i2c_target_perf.1876387124
Short name T1170
Test name
Test status
Simulation time 1226795291 ps
CPU time 7.04 seconds
Started Jul 14 06:02:27 PM PDT 24
Finished Jul 14 06:02:34 PM PDT 24
Peak memory 230216 kb
Host smart-36626ce9-56de-40cb-9171-d31fa91d9fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876387124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.1876387124
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.1038299855
Short name T737
Test name
Test status
Simulation time 465539036 ps
CPU time 2.12 seconds
Started Jul 14 06:02:31 PM PDT 24
Finished Jul 14 06:02:34 PM PDT 24
Peak memory 205356 kb
Host smart-550f1098-835c-4194-b86b-140591052696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038299855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.1038299855
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1622668663
Short name T1256
Test name
Test status
Simulation time 9792614475 ps
CPU time 28.66 seconds
Started Jul 14 06:02:26 PM PDT 24
Finished Jul 14 06:02:55 PM PDT 24
Peak memory 213820 kb
Host smart-2a29e518-0cdb-4f79-99ab-e5236d34caeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622668663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1622668663
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.3183248773
Short name T1069
Test name
Test status
Simulation time 59974499859 ps
CPU time 553.4 seconds
Started Jul 14 06:02:27 PM PDT 24
Finished Jul 14 06:11:41 PM PDT 24
Peak memory 2777764 kb
Host smart-3505572c-adc6-461a-8a53-fb7025082ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183248773 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.3183248773
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2921412680
Short name T878
Test name
Test status
Simulation time 1299761248 ps
CPU time 61.47 seconds
Started Jul 14 06:02:28 PM PDT 24
Finished Jul 14 06:03:30 PM PDT 24
Peak memory 215996 kb
Host smart-147578d5-48fb-4bdc-9f27-88282d7eed38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921412680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2921412680
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3657391169
Short name T301
Test name
Test status
Simulation time 32227623502 ps
CPU time 219.54 seconds
Started Jul 14 06:02:27 PM PDT 24
Finished Jul 14 06:06:07 PM PDT 24
Peak memory 2691328 kb
Host smart-17f6a7d3-fedd-4214-85be-d6d8f1afe802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657391169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3657391169
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1402289993
Short name T1349
Test name
Test status
Simulation time 2389825039 ps
CPU time 15.56 seconds
Started Jul 14 06:02:29 PM PDT 24
Finished Jul 14 06:02:45 PM PDT 24
Peak memory 399296 kb
Host smart-c0d1146e-a2b1-456c-a307-3fab771553c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402289993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1402289993
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1260846578
Short name T683
Test name
Test status
Simulation time 1186200994 ps
CPU time 6.84 seconds
Started Jul 14 06:02:28 PM PDT 24
Finished Jul 14 06:02:35 PM PDT 24
Peak memory 219076 kb
Host smart-99df155f-fe75-4e4f-9ff2-70cb684e6ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260846578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1260846578
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.2805898691
Short name T1481
Test name
Test status
Simulation time 366820038 ps
CPU time 5.2 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:02:42 PM PDT 24
Peak memory 205496 kb
Host smart-48cf4703-0a28-4225-8b8e-eb0604821347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805898691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.2805898691
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.868695296
Short name T733
Test name
Test status
Simulation time 24704695 ps
CPU time 0.63 seconds
Started Jul 14 06:02:48 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 204764 kb
Host smart-a92a4598-dd60-4c75-ac71-72effbc38dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868695296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.868695296
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.598418082
Short name T1087
Test name
Test status
Simulation time 596544122 ps
CPU time 3.18 seconds
Started Jul 14 06:02:41 PM PDT 24
Finished Jul 14 06:02:44 PM PDT 24
Peak memory 221496 kb
Host smart-69af537c-e01e-421c-be4b-12a87436411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598418082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.598418082
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3039892395
Short name T1369
Test name
Test status
Simulation time 163740995 ps
CPU time 3.39 seconds
Started Jul 14 06:02:32 PM PDT 24
Finished Jul 14 06:02:36 PM PDT 24
Peak memory 231432 kb
Host smart-2b700ebe-a71a-46c7-9843-5e1f49421b14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039892395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3039892395
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3503925852
Short name T1162
Test name
Test status
Simulation time 8298340974 ps
CPU time 154.42 seconds
Started Jul 14 06:02:43 PM PDT 24
Finished Jul 14 06:05:18 PM PDT 24
Peak memory 466328 kb
Host smart-896fd0f0-5dd6-4ef1-97b3-436a5fec815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503925852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3503925852
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.948947182
Short name T1682
Test name
Test status
Simulation time 5693819434 ps
CPU time 87.73 seconds
Started Jul 14 06:02:33 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 856348 kb
Host smart-70e18acd-b0e9-459c-ae8e-7424819d0d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948947182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.948947182
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2407201786
Short name T1410
Test name
Test status
Simulation time 135919734 ps
CPU time 1.05 seconds
Started Jul 14 06:02:29 PM PDT 24
Finished Jul 14 06:02:30 PM PDT 24
Peak memory 205236 kb
Host smart-6625abe7-e2a3-4773-90ed-0e6b79350562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407201786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2407201786
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1652298062
Short name T512
Test name
Test status
Simulation time 404942941 ps
CPU time 2.71 seconds
Started Jul 14 06:02:40 PM PDT 24
Finished Jul 14 06:02:43 PM PDT 24
Peak memory 221224 kb
Host smart-b65858aa-bd4e-4a85-9f90-e17807d7205e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652298062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1652298062
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.421722480
Short name T108
Test name
Test status
Simulation time 5728146028 ps
CPU time 148.63 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:05:05 PM PDT 24
Peak memory 1593176 kb
Host smart-39f2770c-b929-4b47-a267-bb3eb3ab084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421722480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.421722480
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3207557500
Short name T248
Test name
Test status
Simulation time 2225316650 ps
CPU time 6.45 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:02:53 PM PDT 24
Peak memory 205532 kb
Host smart-52377ffc-7d52-4fd0-aaa3-d4cd94d11df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207557500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3207557500
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.798626928
Short name T1477
Test name
Test status
Simulation time 16909978 ps
CPU time 0.67 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:02:37 PM PDT 24
Peak memory 205140 kb
Host smart-20b3b0ba-27ef-4ae8-ad20-ccb805cec334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798626928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.798626928
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.4076490235
Short name T461
Test name
Test status
Simulation time 7723482678 ps
CPU time 72.62 seconds
Started Jul 14 06:02:40 PM PDT 24
Finished Jul 14 06:03:53 PM PDT 24
Peak memory 533376 kb
Host smart-2898f7fc-3408-4eee-8855-bc7c25ac508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076490235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.4076490235
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.3413252136
Short name T1074
Test name
Test status
Simulation time 94857938 ps
CPU time 1.09 seconds
Started Jul 14 06:02:37 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 205524 kb
Host smart-e405b62f-a7e4-437f-b5db-116230cd281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413252136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.3413252136
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3301468076
Short name T1601
Test name
Test status
Simulation time 1507993201 ps
CPU time 28.52 seconds
Started Jul 14 06:02:30 PM PDT 24
Finished Jul 14 06:02:59 PM PDT 24
Peak memory 312644 kb
Host smart-c9eab46d-cdbb-4f3f-9ec4-7dc61f35cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301468076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3301468076
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.663997685
Short name T24
Test name
Test status
Simulation time 21005935501 ps
CPU time 349.74 seconds
Started Jul 14 06:02:39 PM PDT 24
Finished Jul 14 06:08:29 PM PDT 24
Peak memory 581836 kb
Host smart-f26c367e-a4a6-4939-aa62-79b275e02c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663997685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.663997685
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1276544910
Short name T1589
Test name
Test status
Simulation time 918175040 ps
CPU time 7.74 seconds
Started Jul 14 06:02:41 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 213664 kb
Host smart-eaf20b56-17be-40d6-93b9-ca71362e2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276544910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1276544910
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2342142244
Short name T1380
Test name
Test status
Simulation time 1011688838 ps
CPU time 5.77 seconds
Started Jul 14 06:02:45 PM PDT 24
Finished Jul 14 06:02:51 PM PDT 24
Peak memory 221940 kb
Host smart-71774ad8-d29b-4194-929b-046dda7603ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342142244 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2342142244
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3890264092
Short name T1711
Test name
Test status
Simulation time 342312253 ps
CPU time 0.86 seconds
Started Jul 14 06:02:38 PM PDT 24
Finished Jul 14 06:02:39 PM PDT 24
Peak memory 205408 kb
Host smart-b81775cb-bae4-48b8-898f-402310047910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890264092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3890264092
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.531041581
Short name T725
Test name
Test status
Simulation time 728300603 ps
CPU time 1.27 seconds
Started Jul 14 06:02:37 PM PDT 24
Finished Jul 14 06:02:38 PM PDT 24
Peak memory 213644 kb
Host smart-9dbfa251-90b0-41b7-81d0-900d16ad77e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531041581 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.531041581
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1197209253
Short name T1345
Test name
Test status
Simulation time 169689703 ps
CPU time 1.51 seconds
Started Jul 14 06:02:45 PM PDT 24
Finished Jul 14 06:02:47 PM PDT 24
Peak memory 205376 kb
Host smart-a23c9331-1f9c-4ce0-9533-dc8a5cc185a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197209253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1197209253
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3597682662
Short name T915
Test name
Test status
Simulation time 253317236 ps
CPU time 1.18 seconds
Started Jul 14 06:02:47 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 205412 kb
Host smart-7ed13f42-dc1f-48aa-97d1-efb4286eaa61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597682662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3597682662
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2454383078
Short name T870
Test name
Test status
Simulation time 2880980524 ps
CPU time 2.54 seconds
Started Jul 14 06:02:48 PM PDT 24
Finished Jul 14 06:02:51 PM PDT 24
Peak memory 213788 kb
Host smart-b1450099-a2e1-4a11-b6f6-72dfd8ade363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454383078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2454383078
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2328580676
Short name T1629
Test name
Test status
Simulation time 3121115690 ps
CPU time 5.14 seconds
Started Jul 14 06:02:39 PM PDT 24
Finished Jul 14 06:02:44 PM PDT 24
Peak memory 222016 kb
Host smart-5db63c90-7915-40f4-9861-8d1f29ae9eb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328580676 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2328580676
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3229384257
Short name T1245
Test name
Test status
Simulation time 7893660494 ps
CPU time 16.64 seconds
Started Jul 14 06:02:40 PM PDT 24
Finished Jul 14 06:02:57 PM PDT 24
Peak memory 571836 kb
Host smart-9b61f99f-1eac-46bc-aada-b2f9921d78ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229384257 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3229384257
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.2792575569
Short name T1539
Test name
Test status
Simulation time 448026687 ps
CPU time 2.8 seconds
Started Jul 14 06:02:49 PM PDT 24
Finished Jul 14 06:02:52 PM PDT 24
Peak memory 213812 kb
Host smart-635920f5-ec18-456e-9972-4214dc3485c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792575569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.2792575569
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.3739511876
Short name T525
Test name
Test status
Simulation time 468537352 ps
CPU time 2.62 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 205560 kb
Host smart-4c456ef2-8cd5-4191-bbf4-8f4b5da6b8fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739511876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3739511876
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3997088899
Short name T1633
Test name
Test status
Simulation time 600025162 ps
CPU time 4.36 seconds
Started Jul 14 06:02:36 PM PDT 24
Finished Jul 14 06:02:41 PM PDT 24
Peak memory 213768 kb
Host smart-f9adb54e-b813-46da-bc03-dd2b5dcca7cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997088899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3997088899
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.3128126337
Short name T549
Test name
Test status
Simulation time 7169558746 ps
CPU time 2.3 seconds
Started Jul 14 06:02:46 PM PDT 24
Finished Jul 14 06:02:48 PM PDT 24
Peak memory 205476 kb
Host smart-6090bd08-f0d5-486e-9dc8-21a7b541a394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128126337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.3128126337
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.902087369
Short name T1044
Test name
Test status
Simulation time 889390147 ps
CPU time 11.78 seconds
Started Jul 14 06:02:38 PM PDT 24
Finished Jul 14 06:02:51 PM PDT 24
Peak memory 209580 kb
Host smart-8d94a8d8-c403-435f-ac73-d35f779d4bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902087369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.902087369
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.691232261
Short name T354
Test name
Test status
Simulation time 29189258752 ps
CPU time 177.6 seconds
Started Jul 14 06:02:52 PM PDT 24
Finished Jul 14 06:05:50 PM PDT 24
Peak memory 1205820 kb
Host smart-47110b89-a6cf-4083-9675-47751269594a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691232261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_stress_all.691232261
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.831841731
Short name T257
Test name
Test status
Simulation time 847292759 ps
CPU time 16.16 seconds
Started Jul 14 06:02:39 PM PDT 24
Finished Jul 14 06:02:56 PM PDT 24
Peak memory 221840 kb
Host smart-e5e3667d-e328-490f-b5a8-fd0d6734ee9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831841731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.831841731
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3835442730
Short name T448
Test name
Test status
Simulation time 49969929146 ps
CPU time 474.97 seconds
Started Jul 14 06:02:44 PM PDT 24
Finished Jul 14 06:10:39 PM PDT 24
Peak memory 3864996 kb
Host smart-ca4a5668-e0a8-4d44-b235-1979681df2ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835442730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3835442730
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.871810919
Short name T372
Test name
Test status
Simulation time 3294419611 ps
CPU time 11.22 seconds
Started Jul 14 06:02:40 PM PDT 24
Finished Jul 14 06:02:51 PM PDT 24
Peak memory 322512 kb
Host smart-49b5420f-1226-4520-b63d-5f1b511d6fea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871810919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.871810919
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1678873266
Short name T1592
Test name
Test status
Simulation time 7224792002 ps
CPU time 6.22 seconds
Started Jul 14 06:02:38 PM PDT 24
Finished Jul 14 06:02:44 PM PDT 24
Peak memory 220384 kb
Host smart-3ac2e8e1-9eb9-4abe-9e53-9e2e9e08068c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678873266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1678873266
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.1805511064
Short name T1425
Test name
Test status
Simulation time 506587115 ps
CPU time 7.5 seconds
Started Jul 14 06:02:52 PM PDT 24
Finished Jul 14 06:03:00 PM PDT 24
Peak memory 205848 kb
Host smart-d6b5d15e-ba45-462d-9ded-7c09f71aa9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805511064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.1805511064
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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