Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	730633	1			T1	4		T2	2		T3	2
all_values[1]	730633	1			T1	4		T2	2		T3	2
all_values[2]	730633	1			T1	4		T2	2		T3	2
all_values[3]	730633	1			T1	4		T2	2		T3	2
all_values[4]	730633	1			T1	4		T2	2		T3	2
all_values[5]	730633	1			T1	4		T2	2		T3	2
all_values[6]	730633	1			T1	4		T2	2		T3	2
all_values[7]	730633	1			T1	4		T2	2		T3	2
all_values[8]	730633	1			T1	4		T2	2		T3	2
all_values[9]	730633	1			T1	4		T2	2		T3	2
all_values[10]	730633	1			T1	4		T2	2		T3	2
all_values[11]	730633	1			T1	4		T2	2		T3	2
all_values[12]	730633	1			T1	4		T2	2		T3	2
all_values[13]	730633	1			T1	4		T2	2		T3	2
all_values[14]	730633	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9016541

1

T1

51

T2

26

T3

26

auto[1]

1942954

1

T1

9

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9575303

1

T1

60

T2

30

T3

30

auto[1]

1384192

1

T17

43604

T129

11975

T189

182611

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	93352	1			T8	8		T9	2		T14	1
all_values[0]	auto[0]	auto[1]	17250	1			T17	745		T129	370		T245	1052
all_values[0]	auto[1]	auto[0]	556052	1			T1	4		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	63979	1			T17	2162		T129	429		T245	210
all_values[1]	auto[0]	auto[0]	641306	1			T1	4		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	88709	1			T17	2897		T129	795		T189	14047
all_values[1]	auto[1]	auto[0]	439	1			T41	2		T50	3		T156	5
all_values[1]	auto[1]	auto[1]	179	1			T17	9		T129	4		T189	1
all_values[2]	auto[0]	auto[0]	636362	1			T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	93913	1			T17	2896		T129	795		T189	14045
all_values[2]	auto[1]	auto[0]	184	1			T7	2		T54	1		T176	2
all_values[2]	auto[1]	auto[1]	174	1			T17	11		T129	4		T189	2
all_values[3]	auto[0]	auto[0]	640858	1			T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	89555	1			T17	2893		T129	794		T189	14045
all_values[3]	auto[1]	auto[1]	220	1			T17	13		T129	5		T189	3
all_values[4]	auto[0]	auto[0]	635356	1			T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	95077	1			T17	2894		T129	796		T189	14045
all_values[4]	auto[1]	auto[0]	17	1			T47	1		T261	2		T272	1
all_values[4]	auto[1]	auto[1]	183	1			T17	13		T129	3		T189	1
all_values[5]	auto[0]	auto[0]	635345	1			T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	95071	1			T17	2896		T129	794		T189	14046
all_values[5]	auto[1]	auto[1]	217	1			T17	11		T129	3		T189	2
all_values[6]	auto[0]	auto[0]	636616	1			T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	93787	1			T17	2891		T129	793		T189	14044
all_values[6]	auto[1]	auto[1]	230	1			T17	16		T129	5		T189	2
all_values[7]	auto[0]	auto[0]	610207	1			T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	90179	1			T17	2623		T129	508		T189	13582
all_values[7]	auto[1]	auto[0]	25366	1			T8	107		T14	1		T16	178
all_values[7]	auto[1]	auto[1]	4881	1			T17	285		T129	289		T189	466
all_values[8]	auto[0]	auto[0]	635363	1			T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	95039	1			T17	2893		T129	792		T189	14044
all_values[8]	auto[1]	auto[1]	231	1			T17	15		T129	6		T189	3
all_values[9]	auto[0]	auto[0]	141626	1			T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	27068	1			T17	2850		T129	766		T189	515
all_values[9]	auto[1]	auto[0]	493732	1			T1	1		T7	1		T8	11640
all_values[9]	auto[1]	auto[1]	68207	1			T17	58		T129	32		T189	13533
all_values[10]	auto[0]	auto[0]	635585	1			T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	94883	1			T17	2894		T129	796		T189	14045
all_values[10]	auto[1]	auto[1]	165	1			T17	11		T129	3		T189	1
all_values[11]	auto[0]	auto[0]	2327	1			T8	9		T9	2		T14	1
all_values[11]	auto[0]	auto[1]	466	1			T17	30		T129	9		T189	15
all_values[11]	auto[1]	auto[0]	635107	1			T1	4		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	92733	1			T17	2878		T129	789		T189	14032
all_values[12]	auto[0]	auto[0]	649335	1			T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	81052	1			T17	2889		T129	793		T245	1256
all_values[12]	auto[1]	auto[0]	64	1			T54	1		T60	1		T61	1
all_values[12]	auto[1]	auto[1]	182	1			T17	15		T129	4		T245	6
all_values[13]	auto[0]	auto[0]	635348	1			T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	95050	1			T17	2890		T129	797		T189	14044
all_values[13]	auto[1]	auto[1]	235	1			T17	18		T129	2		T189	2
all_values[14]	auto[0]	auto[0]	635356	1			T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	95100	1			T17	2888		T129	793		T189	14044
all_values[14]	auto[1]	auto[1]	177	1			T17	20		T129	6		T189	2