Summary for Variable cp_acq_overflow
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_acq_overflow
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3599 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_acq_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_acq_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3597 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
2 |
1 |
|
|
T247 |
1 |
|
T248 |
1 |
|
- |
- |
Summary for Variable cp_acqrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_acqrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
814 |
1 |
|
|
T9 |
12 |
|
T15 |
2 |
|
T53 |
1 |
auto[1] |
2785 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_fmt_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_fmt_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2944 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
655 |
1 |
|
|
T15 |
2 |
|
T53 |
2 |
|
T64 |
9 |
Summary for Variable cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_fmtrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
601 |
1 |
|
|
T9 |
6 |
|
T15 |
2 |
|
T53 |
2 |
auto[1] |
2998 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rx_overflow
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_rx_overflow
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3599 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rx_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_rx_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3580 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
19 |
1 |
|
|
T15 |
1 |
|
T184 |
1 |
|
T249 |
1 |
Summary for Variable cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_rxrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
945 |
1 |
|
|
T9 |
12 |
|
T15 |
1 |
|
T53 |
2 |
auto[1] |
2654 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_tx_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_tx_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2977 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
622 |
1 |
|
|
T15 |
2 |
|
T53 |
1 |
|
T64 |
9 |
Summary for Variable cp_txrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_txrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
814 |
1 |
|
|
T9 |
12 |
|
T15 |
2 |
|
T42 |
14 |
auto[1] |
2785 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_fmt_threshold_cross
Samples crossed: cp_fmt_threshold cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_fmt_threshold_cross
Bins
cp_fmt_threshold | cp_fmtrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
365 |
1 |
|
|
T9 |
6 |
|
T42 |
7 |
|
T43 |
5 |
auto[0] |
auto[1] |
2579 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
236 |
1 |
|
|
T15 |
2 |
|
T53 |
2 |
|
T79 |
2 |
auto[1] |
auto[1] |
419 |
1 |
|
|
T64 |
9 |
|
T17 |
1 |
|
T65 |
10 |
Summary for Cross cp_rx_threshold_cross
Samples crossed: cp_rx_threshold cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cp_rx_threshold_cross
Uncovered bins
cp_rx_threshold | cp_rxrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_rx_threshold | cp_rxrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
945 |
1 |
|
|
T9 |
12 |
|
T15 |
1 |
|
T53 |
2 |
auto[0] |
auto[1] |
2635 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[1] |
19 |
1 |
|
|
T15 |
1 |
|
T184 |
1 |
|
T249 |
1 |
Summary for Cross cp_acq_threshold_cross
Samples crossed: cp_acq_threshold cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cp_acq_threshold_cross
Uncovered bins
cp_acq_threshold | cp_fmtrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_acq_threshold | cp_fmtrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
599 |
1 |
|
|
T9 |
6 |
|
T15 |
2 |
|
T53 |
2 |
auto[0] |
auto[1] |
2998 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
2 |
1 |
|
|
T247 |
1 |
|
T248 |
1 |
|
- |
- |
Summary for Cross cp_rx_overflow_cross
Samples crossed: cp_rx_overflow cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cp_rx_overflow_cross
Element holes
cp_rx_overflow | cp_rxrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_rx_overflow | cp_rxrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
945 |
1 |
|
|
T9 |
12 |
|
T15 |
1 |
|
T53 |
2 |
auto[0] |
auto[1] |
2654 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_acq_overflow_cross
Samples crossed: cp_acq_overflow cp_acqrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cp_acq_overflow_cross
Element holes
cp_acq_overflow | cp_acqrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_acq_overflow | cp_acqrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
814 |
1 |
|
|
T9 |
12 |
|
T15 |
2 |
|
T53 |
1 |
auto[0] |
auto[1] |
2785 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_tx_threshold_cross
Samples crossed: cp_tx_threshold cp_txrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_tx_threshold_cross
Bins
cp_tx_threshold | cp_txrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
737 |
1 |
|
|
T9 |
12 |
|
T42 |
14 |
|
T43 |
10 |
auto[0] |
auto[1] |
2240 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
77 |
1 |
|
|
T15 |
2 |
|
T153 |
1 |
|
T95 |
1 |
auto[1] |
auto[1] |
545 |
1 |
|
|
T53 |
1 |
|
T64 |
9 |
|
T17 |
1 |