Summary for Variable cp_acq_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_acq_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
118310957 |
1 |
|
|
T1 |
48 |
|
T2 |
118901 |
|
T3 |
148825 |
empty |
65328912 |
1 |
|
|
T2 |
122754 |
|
T4 |
47 |
|
T6 |
19 |
Summary for Variable cp_host_mode_stretch
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_host_mode_stretch
Excluded/Illegal bins
NAME | COUNT | STATUS |
unused |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
stretch |
44239116 |
1 |
|
|
T8 |
1123 |
|
T14 |
20284 |
|
T16 |
3858 |
Summary for Variable cp_target_scl_stretch_addr_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_target_scl_stretch_addr_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
addr_write_byte_stretch |
514205 |
1 |
|
|
T3 |
10418 |
|
T10 |
29 |
|
T54 |
35 |
Summary for Variable cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_tx_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
4964212 |
1 |
|
|
T1 |
48 |
|
T4 |
77 |
|
T5 |
3245 |
empty |
178736358 |
1 |
|
|
T2 |
131176 |
|
T3 |
148825 |
|
T5 |
1276 |
Summary for Cross cp_target_scl_stretch_read
Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
User Defined Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for cp_target_scl_stretch_read
Bins
cp_acq_fifo_size | cp_tx_fifo_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
empty |
not_empty |
1870 |
1 |
|
|
T4 |
47 |
|
T6 |
19 |
|
T290 |
18 |
empty |
empty |
355451 |
1 |
|
|
T53 |
613 |
|
T17 |
61 |
|
T79 |
1546 |
User Defined Cross Bins for cp_target_scl_stretch_read
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_byte_stretch |
296630 |
1 |
|
|
T5 |
543 |
|
T53 |
609 |
|
T62 |
130 |
scl_stretch_read_request |
5258493 |
1 |
|
|
T1 |
48 |
|
T4 |
30 |
|
T5 |
3788 |