Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	730633	1			T1	4		T2	2		T3	2
all_pins[1]	730633	1			T1	4		T2	2		T3	2
all_pins[2]	730633	1			T1	4		T2	2		T3	2
all_pins[3]	730633	1			T1	4		T2	2		T3	2
all_pins[4]	730633	1			T1	4		T2	2		T3	2
all_pins[5]	730633	1			T1	4		T2	2		T3	2
all_pins[6]	730633	1			T1	4		T2	2		T3	2
all_pins[7]	730633	1			T1	4		T2	2		T3	2
all_pins[8]	730633	1			T1	4		T2	2		T3	2
all_pins[9]	730633	1			T1	4		T2	2		T3	2
all_pins[10]	730633	1			T1	4		T2	2		T3	2
all_pins[11]	730633	1			T1	4		T2	2		T3	2
all_pins[12]	730633	1			T1	4		T2	2		T3	2
all_pins[13]	730633	1			T1	4		T2	2		T3	2
all_pins[14]	730633	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9021965	1			T1	51		T2	26		T3	26
values[0x1]	1937530	1			T1	9		T2	4		T3	4
transitions[0x0=>0x1]	1936583	1			T1	9		T2	4		T3	4
transitions[0x1=>0x0]	1935279	1			T1	8		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	113988	1			T8	8		T9	2		T10	1
all_pins[0]	values[0x1]	616645	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	616068	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	76	1			T17	3		T129	2		T245	2
all_pins[1]	values[0x0]	729980	1			T1	4		T2	2		T3	2
all_pins[1]	values[0x1]	653	1			T17	3		T41	3		T50	3
all_pins[1]	transitions[0x0=>0x1]	639	1			T17	2		T41	3		T50	3
all_pins[1]	transitions[0x1=>0x0]	115	1			T17	4		T279	1		T171	1
all_pins[2]	values[0x0]	730504	1			T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	129	1			T17	5		T279	1		T171	1
all_pins[2]	transitions[0x0=>0x1]	114	1			T17	5		T279	1		T171	1
all_pins[2]	transitions[0x1=>0x0]	91	1			T17	7		T129	2		T189	2
all_pins[3]	values[0x0]	730527	1			T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	106	1			T17	7		T129	3		T189	3
all_pins[3]	transitions[0x0=>0x1]	87	1			T17	7		T129	3		T189	3
all_pins[3]	transitions[0x1=>0x0]	91	1			T17	4		T47	1		T261	3
all_pins[4]	values[0x0]	730523	1			T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	110	1			T17	4		T47	1		T261	3
all_pins[4]	transitions[0x0=>0x1]	73	1			T17	2		T47	1		T261	3
all_pins[4]	transitions[0x1=>0x0]	81	1			T17	3		T129	1		T245	3
all_pins[5]	values[0x0]	730515	1			T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	118	1			T17	5		T129	2		T245	5
all_pins[5]	transitions[0x0=>0x1]	78	1			T17	3		T129	1		T245	5
all_pins[5]	transitions[0x1=>0x0]	74	1			T17	6		T129	2		T189	2
all_pins[6]	values[0x0]	730519	1			T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	114	1			T17	8		T129	3		T189	2
all_pins[6]	transitions[0x0=>0x1]	77	1			T17	6		T33	3		T131	2
all_pins[6]	transitions[0x1=>0x0]	33175	1			T8	133		T14	1		T16	193
all_pins[7]	values[0x0]	697421	1			T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	33212	1			T8	133		T14	1		T16	193
all_pins[7]	transitions[0x0=>0x1]	33180	1			T8	133		T14	1		T16	193
all_pins[7]	transitions[0x1=>0x0]	81	1			T17	5		T129	1		T189	1
all_pins[8]	values[0x0]	730520	1			T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	113	1			T17	7		T129	3		T189	1
all_pins[8]	transitions[0x0=>0x1]	92	1			T17	6		T129	3		T189	1
all_pins[8]	transitions[0x1=>0x0]	561831	1			T1	1		T7	1		T8	11640
all_pins[9]	values[0x0]	168781	1			T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	561852	1			T1	1		T7	1		T8	11640
all_pins[9]	transitions[0x0=>0x1]	561834	1			T1	1		T7	1		T8	11640
all_pins[9]	transitions[0x1=>0x0]	61	1			T17	5		T129	1		T280	2
all_pins[10]	values[0x0]	730554	1			T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	79	1			T17	5		T129	1		T280	2
all_pins[10]	transitions[0x0=>0x1]	58	1			T17	3		T129	1		T280	2
all_pins[10]	transitions[0x1=>0x0]	724017	1			T1	4		T2	2		T3	2
all_pins[11]	values[0x0]	6595	1			T7	2		T8	9		T9	2
all_pins[11]	values[0x1]	724038	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	724001	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	128	1			T54	1		T17	5		T60	1
all_pins[12]	values[0x0]	730468	1			T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	165	1			T54	1		T17	6		T60	1
all_pins[12]	transitions[0x0=>0x1]	144	1			T54	1		T17	4		T60	1
all_pins[12]	transitions[0x1=>0x0]	86	1			T17	8		T245	2		T130	2
all_pins[13]	values[0x0]	730526	1			T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	107	1			T17	10		T129	1		T245	2
all_pins[13]	transitions[0x0=>0x1]	84	1			T17	8		T245	2		T130	1
all_pins[13]	transitions[0x1=>0x0]	66	1			T17	5		T129	4		T189	2
all_pins[14]	values[0x0]	730544	1			T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	89	1			T17	7		T129	5		T189	2
all_pins[14]	transitions[0x0=>0x1]	54	1			T17	3		T129	2		T189	2
all_pins[14]	transitions[0x1=>0x0]	615306	1			T1	3		T2	1		T3	1