Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	437	1			T17	29		T129	7		T189	4
all_values[1]	437	1			T17	29		T129	7		T189	4
all_values[2]	437	1			T17	29		T129	7		T189	4
all_values[3]	437	1			T17	29		T129	7		T189	4
all_values[4]	437	1			T17	29		T129	7		T189	4
all_values[5]	437	1			T17	29		T129	7		T189	4
all_values[6]	437	1			T17	29		T129	7		T189	4
all_values[7]	437	1			T17	29		T129	7		T189	4
all_values[8]	437	1			T17	29		T129	7		T189	4
all_values[9]	437	1			T17	29		T129	7		T189	4
all_values[10]	437	1			T17	29		T129	7		T189	4
all_values[11]	437	1			T17	29		T129	7		T189	4
all_values[12]	437	1			T17	29		T129	7		T189	4
all_values[13]	437	1			T17	29		T129	7		T189	4
all_values[14]	437	1			T17	29		T129	7		T189	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3418

1

T17

243

T129

43

T189

30

auto[1]

3137

1

T17

192

T129

62

T189

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T17

16

T129

10

T189

21

auto[1]

5584

1

T17

419

T129

95

T189

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3853

1

T17

242

T129

54

T189

40

auto[1]

2702

1

T17

193

T129

51

T189

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1			T17	1		T189	3		T33	1
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T17	6		T129	1		T245	2
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T189	1		T131	1		T281	2
all_values[0]	auto[0]	auto[1]	auto[1]	101	1			T17	8		T129	2		T245	4
all_values[0]	auto[1]	auto[0]	auto[1]	92	1			T17	4		T280	2		T130	4
all_values[0]	auto[1]	auto[1]	auto[1]	98	1			T17	10		T129	4		T245	5
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T17	1		T245	1		T131	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T17	10		T245	4		T280	6
all_values[1]	auto[0]	auto[1]	auto[0]	36	1			T17	1		T282	4		T283	2
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T17	8		T129	3		T189	3
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T17	5		T189	1		T245	1
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T17	4		T129	4		T245	4
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T17	1		T280	3		T284	4
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T17	8		T245	1		T130	2
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T189	1		T280	4		T282	1
all_values[2]	auto[0]	auto[1]	auto[1]	103	1			T17	9		T129	3		T189	1
all_values[2]	auto[1]	auto[0]	auto[1]	106	1			T17	5		T129	3		T189	1
all_values[2]	auto[1]	auto[1]	auto[1]	68	1			T17	6		T129	1		T189	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1			T17	2		T245	1		T280	1
all_values[3]	auto[0]	auto[0]	auto[1]	112	1			T17	9		T129	1		T245	4
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T245	1		T280	3		T282	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T17	8		T129	3		T189	2
all_values[3]	auto[1]	auto[0]	auto[1]	109	1			T17	8		T129	2		T189	1
all_values[3]	auto[1]	auto[1]	auto[1]	75	1			T17	2		T129	1		T189	1
all_values[4]	auto[0]	auto[0]	auto[0]	42	1			T17	1		T189	2		T245	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T17	9		T129	2		T189	1
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T245	1		T282	1		T283	2
all_values[4]	auto[0]	auto[1]	auto[1]	90	1			T17	6		T129	2		T245	1
all_values[4]	auto[1]	auto[0]	auto[1]	92	1			T17	9		T129	2		T189	1
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T17	4		T129	1		T245	3
all_values[5]	auto[0]	auto[0]	auto[0]	25	1			T17	1		T33	1		T281	1
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T17	10		T129	2		T189	1
all_values[5]	auto[0]	auto[1]	auto[0]	23	1			T129	2		T280	1		T285	4
all_values[5]	auto[0]	auto[1]	auto[1]	122	1			T17	6		T189	1		T245	4
all_values[5]	auto[1]	auto[0]	auto[1]	93	1			T17	6		T189	1		T245	1
all_values[5]	auto[1]	auto[1]	auto[1]	96	1			T17	6		T129	3		T189	1
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T17	1		T129	1		T189	2
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T17	7		T280	3		T130	1
all_values[6]	auto[0]	auto[1]	auto[0]	36	1			T245	3		T280	3		T130	1
all_values[6]	auto[0]	auto[1]	auto[1]	100	1			T17	7		T129	3		T189	1
all_values[6]	auto[1]	auto[0]	auto[1]	85	1			T17	6		T129	1		T245	2
all_values[6]	auto[1]	auto[1]	auto[1]	92	1			T17	8		T129	2		T189	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T129	2		T33	4		T132	3
all_values[7]	auto[0]	auto[0]	auto[1]	101	1			T17	12		T245	3		T280	3
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T280	1		T33	1		T283	2
all_values[7]	auto[0]	auto[1]	auto[1]	97	1			T17	6		T129	2		T189	2
all_values[7]	auto[1]	auto[0]	auto[1]	88	1			T17	4		T189	1		T245	1
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T17	7		T129	3		T189	1
all_values[8]	auto[0]	auto[0]	auto[0]	44	1			T129	1		T189	1		T280	2
all_values[8]	auto[0]	auto[0]	auto[1]	82	1			T17	4		T129	1		T189	1
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T280	1		T130	3		T286	1
all_values[8]	auto[0]	auto[1]	auto[1]	96	1			T17	11		T280	2		T130	1
all_values[8]	auto[1]	auto[0]	auto[1]	109	1			T17	11		T129	2		T189	1
all_values[8]	auto[1]	auto[1]	auto[1]	83	1			T17	3		T129	3		T189	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T129	1		T130	1		T33	1
all_values[9]	auto[0]	auto[0]	auto[1]	104	1			T17	9		T129	3		T245	3
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T280	1		T131	1		T284	2
all_values[9]	auto[0]	auto[1]	auto[1]	96	1			T17	4		T189	2		T245	3
all_values[9]	auto[1]	auto[0]	auto[1]	102	1			T17	11		T129	3		T189	1
all_values[9]	auto[1]	auto[1]	auto[1]	74	1			T17	5		T189	1		T245	5
all_values[10]	auto[0]	auto[0]	auto[0]	41	1			T17	3		T189	1		T33	4
all_values[10]	auto[0]	auto[0]	auto[1]	112	1			T17	9		T129	3		T189	1
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T189	1		T280	2		T283	1
all_values[10]	auto[0]	auto[1]	auto[1]	87	1			T17	6		T129	1		T280	2
all_values[10]	auto[1]	auto[0]	auto[1]	89	1			T17	7		T129	3		T189	1
all_values[10]	auto[1]	auto[1]	auto[1]	76	1			T17	4		T280	2		T130	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T130	1		T282	1		T281	1
all_values[11]	auto[0]	auto[0]	auto[1]	96	1			T17	6		T129	1		T189	1
all_values[11]	auto[0]	auto[1]	auto[0]	34	1			T129	1		T189	1		T280	1
all_values[11]	auto[0]	auto[1]	auto[1]	93	1			T17	10		T129	2		T280	1
all_values[11]	auto[1]	auto[0]	auto[1]	91	1			T17	6		T129	1		T189	1
all_values[11]	auto[1]	auto[1]	auto[1]	81	1			T17	7		T129	2		T189	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T17	1		T189	3		T33	1
all_values[12]	auto[0]	auto[0]	auto[1]	84	1			T17	4		T245	4		T280	4
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T17	3		T129	2		T189	1
all_values[12]	auto[0]	auto[1]	auto[1]	111	1			T17	6		T129	1		T245	1
all_values[12]	auto[1]	auto[0]	auto[1]	82	1			T17	9		T129	1		T245	1
all_values[12]	auto[1]	auto[1]	auto[1]	100	1			T17	6		T129	3		T245	5
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T189	1		T280	2		T281	1
all_values[13]	auto[0]	auto[0]	auto[1]	101	1			T17	7		T129	3		T189	1
all_values[13]	auto[0]	auto[1]	auto[0]	21	1			T189	1		T280	2		T130	1
all_values[13]	auto[0]	auto[1]	auto[1]	91	1			T17	7		T129	2		T245	3
all_values[13]	auto[1]	auto[0]	auto[1]	112	1			T17	8		T129	1		T189	1
all_values[13]	auto[1]	auto[1]	auto[1]	80	1			T17	7		T129	1		T130	1
all_values[14]	auto[0]	auto[0]	auto[0]	34	1			T130	1		T33	1		T281	1
all_values[14]	auto[0]	auto[0]	auto[1]	126	1			T17	12		T129	1		T245	4
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T189	2		T33	1		T286	1
all_values[14]	auto[0]	auto[1]	auto[1]	75	1			T17	2		T129	2		T189	1
all_values[14]	auto[1]	auto[0]	auto[1]	99	1			T17	10		T129	1		T245	2
all_values[14]	auto[1]	auto[1]	auto[1]	75	1			T17	5		T129	3		T189	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal