Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.38 97.30 89.65 97.22 72.62 94.40 98.44 90.00


Total test records in report: 1847
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T1762 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3430070993 Jul 15 05:25:51 PM PDT 24 Jul 15 05:25:53 PM PDT 24 34334812 ps
T1763 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3353514961 Jul 15 05:25:42 PM PDT 24 Jul 15 05:25:44 PM PDT 24 51905683 ps
T1764 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2445270593 Jul 15 05:26:37 PM PDT 24 Jul 15 05:26:38 PM PDT 24 16345584 ps
T1765 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1247158961 Jul 15 05:25:26 PM PDT 24 Jul 15 05:25:29 PM PDT 24 186421862 ps
T1766 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.560853783 Jul 15 05:26:14 PM PDT 24 Jul 15 05:26:17 PM PDT 24 152862424 ps
T1767 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.683169567 Jul 15 05:25:04 PM PDT 24 Jul 15 05:25:05 PM PDT 24 115398770 ps
T1768 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2120609993 Jul 15 05:25:41 PM PDT 24 Jul 15 05:25:43 PM PDT 24 22887224 ps
T1769 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1660859888 Jul 15 05:26:06 PM PDT 24 Jul 15 05:26:07 PM PDT 24 57266845 ps
T1770 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2688221187 Jul 15 05:26:32 PM PDT 24 Jul 15 05:26:34 PM PDT 24 23824652 ps
T1771 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3678365185 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:14 PM PDT 24 48292150 ps
T1772 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1888082180 Jul 15 05:25:58 PM PDT 24 Jul 15 05:25:59 PM PDT 24 21960146 ps
T1773 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2169055400 Jul 15 05:25:43 PM PDT 24 Jul 15 05:25:44 PM PDT 24 23984688 ps
T1774 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3173079469 Jul 15 05:25:49 PM PDT 24 Jul 15 05:25:51 PM PDT 24 62292639 ps
T1775 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3519427025 Jul 15 05:26:15 PM PDT 24 Jul 15 05:26:17 PM PDT 24 56987857 ps
T1776 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1706572699 Jul 15 05:26:05 PM PDT 24 Jul 15 05:26:06 PM PDT 24 24982920 ps
T1777 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1936330312 Jul 15 05:25:51 PM PDT 24 Jul 15 05:25:54 PM PDT 24 66230838 ps
T1778 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3904179770 Jul 15 05:25:33 PM PDT 24 Jul 15 05:25:35 PM PDT 24 34097480 ps
T1779 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1446970209 Jul 15 05:25:12 PM PDT 24 Jul 15 05:25:14 PM PDT 24 47651592 ps
T1780 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2674028991 Jul 15 05:25:41 PM PDT 24 Jul 15 05:25:43 PM PDT 24 49370923 ps
T1781 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2337422458 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:33 PM PDT 24 17078529 ps
T237 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1212034306 Jul 15 05:25:41 PM PDT 24 Jul 15 05:25:44 PM PDT 24 66600469 ps
T1782 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3151205529 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:32 PM PDT 24 54942173 ps
T1783 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2305156560 Jul 15 05:26:22 PM PDT 24 Jul 15 05:26:23 PM PDT 24 42642427 ps
T218 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1072813294 Jul 15 05:25:58 PM PDT 24 Jul 15 05:26:01 PM PDT 24 167009214 ps
T1784 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2046353344 Jul 15 05:26:14 PM PDT 24 Jul 15 05:26:16 PM PDT 24 18483374 ps
T1785 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2926651888 Jul 15 05:25:26 PM PDT 24 Jul 15 05:25:27 PM PDT 24 68649926 ps
T1786 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3220871419 Jul 15 05:26:12 PM PDT 24 Jul 15 05:26:14 PM PDT 24 391484856 ps
T1787 /workspace/coverage/cover_reg_top/39.i2c_intr_test.4228149394 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:33 PM PDT 24 17110426 ps
T227 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4119261421 Jul 15 05:25:40 PM PDT 24 Jul 15 05:25:43 PM PDT 24 88988501 ps
T1788 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3639124053 Jul 15 05:25:53 PM PDT 24 Jul 15 05:25:56 PM PDT 24 100346500 ps
T214 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2275804879 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:15 PM PDT 24 308370160 ps
T1789 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3634052596 Jul 15 05:26:22 PM PDT 24 Jul 15 05:26:23 PM PDT 24 80497879 ps
T1790 /workspace/coverage/cover_reg_top/12.i2c_intr_test.491628496 Jul 15 05:25:56 PM PDT 24 Jul 15 05:25:57 PM PDT 24 60285404 ps
T1791 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2933110504 Jul 15 05:26:04 PM PDT 24 Jul 15 05:26:05 PM PDT 24 52590244 ps
T1792 /workspace/coverage/cover_reg_top/2.i2c_intr_test.2927770147 Jul 15 05:25:21 PM PDT 24 Jul 15 05:25:22 PM PDT 24 18625151 ps
T235 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.143849558 Jul 15 05:25:51 PM PDT 24 Jul 15 05:25:53 PM PDT 24 51102167 ps
T1793 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1647851497 Jul 15 05:25:52 PM PDT 24 Jul 15 05:25:55 PM PDT 24 30632530 ps
T1794 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.875939966 Jul 15 05:25:56 PM PDT 24 Jul 15 05:25:58 PM PDT 24 55065845 ps
T1795 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2602044527 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:14 PM PDT 24 34670861 ps
T1796 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2191564929 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:14 PM PDT 24 29218636 ps
T1797 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3197043456 Jul 15 05:24:57 PM PDT 24 Jul 15 05:25:00 PM PDT 24 656370877 ps
T1798 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2048480560 Jul 15 05:25:51 PM PDT 24 Jul 15 05:25:54 PM PDT 24 226305415 ps
T1799 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3371092054 Jul 15 05:26:05 PM PDT 24 Jul 15 05:26:08 PM PDT 24 127687356 ps
T238 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1354743835 Jul 15 05:25:05 PM PDT 24 Jul 15 05:25:07 PM PDT 24 99283491 ps
T1800 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4123955196 Jul 15 05:26:20 PM PDT 24 Jul 15 05:26:21 PM PDT 24 16668647 ps
T1801 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2697906270 Jul 15 05:26:15 PM PDT 24 Jul 15 05:26:16 PM PDT 24 29254162 ps
T1802 /workspace/coverage/cover_reg_top/46.i2c_intr_test.4250206635 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:33 PM PDT 24 148596595 ps
T1803 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3913281147 Jul 15 05:25:34 PM PDT 24 Jul 15 05:25:37 PM PDT 24 276184494 ps
T1804 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3614843769 Jul 15 05:26:04 PM PDT 24 Jul 15 05:26:05 PM PDT 24 27639994 ps
T1805 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1910126695 Jul 15 05:26:21 PM PDT 24 Jul 15 05:26:22 PM PDT 24 56734366 ps
T1806 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1253862144 Jul 15 05:25:57 PM PDT 24 Jul 15 05:25:59 PM PDT 24 23662676 ps
T1807 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1541224574 Jul 15 05:26:06 PM PDT 24 Jul 15 05:26:08 PM PDT 24 226996386 ps
T239 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2243425300 Jul 15 05:25:17 PM PDT 24 Jul 15 05:25:18 PM PDT 24 54510249 ps
T1808 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1505380842 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:15 PM PDT 24 30496110 ps
T215 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3380199547 Jul 15 05:25:21 PM PDT 24 Jul 15 05:25:23 PM PDT 24 483094874 ps
T1809 /workspace/coverage/cover_reg_top/20.i2c_intr_test.977821254 Jul 15 05:26:21 PM PDT 24 Jul 15 05:26:22 PM PDT 24 52232098 ps
T1810 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2480984398 Jul 15 05:25:52 PM PDT 24 Jul 15 05:25:54 PM PDT 24 20862112 ps
T1811 /workspace/coverage/cover_reg_top/16.i2c_intr_test.4193342884 Jul 15 05:26:12 PM PDT 24 Jul 15 05:26:13 PM PDT 24 46397386 ps
T1812 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3995834801 Jul 15 05:26:13 PM PDT 24 Jul 15 05:26:15 PM PDT 24 40307203 ps
T1813 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2850887801 Jul 15 05:25:05 PM PDT 24 Jul 15 05:25:06 PM PDT 24 42411806 ps
T1814 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1651453498 Jul 15 05:25:42 PM PDT 24 Jul 15 05:25:44 PM PDT 24 61625881 ps
T1815 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3747136368 Jul 15 05:26:07 PM PDT 24 Jul 15 05:26:10 PM PDT 24 203955747 ps
T1816 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.463638858 Jul 15 05:25:57 PM PDT 24 Jul 15 05:26:00 PM PDT 24 74795030 ps
T1817 /workspace/coverage/cover_reg_top/32.i2c_intr_test.983739651 Jul 15 05:26:22 PM PDT 24 Jul 15 05:26:23 PM PDT 24 55433153 ps
T1818 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3658546811 Jul 15 05:25:27 PM PDT 24 Jul 15 05:25:30 PM PDT 24 291542029 ps
T1819 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2224162626 Jul 15 05:25:06 PM PDT 24 Jul 15 05:25:07 PM PDT 24 44490194 ps
T1820 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3604192692 Jul 15 05:26:21 PM PDT 24 Jul 15 05:26:22 PM PDT 24 21251952 ps
T240 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1719062354 Jul 15 05:25:34 PM PDT 24 Jul 15 05:25:35 PM PDT 24 43627925 ps
T1821 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3649883753 Jul 15 05:26:04 PM PDT 24 Jul 15 05:26:06 PM PDT 24 66155865 ps
T1822 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2051572542 Jul 15 05:26:37 PM PDT 24 Jul 15 05:26:38 PM PDT 24 31038251 ps
T1823 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.278173 Jul 15 05:26:04 PM PDT 24 Jul 15 05:26:06 PM PDT 24 152117391 ps
T1824 /workspace/coverage/cover_reg_top/27.i2c_intr_test.4139562671 Jul 15 05:26:21 PM PDT 24 Jul 15 05:26:23 PM PDT 24 47125533 ps
T1825 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2055651865 Jul 15 05:25:04 PM PDT 24 Jul 15 05:25:05 PM PDT 24 27200382 ps
T1826 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3774340472 Jul 15 05:25:35 PM PDT 24 Jul 15 05:25:38 PM PDT 24 1092499662 ps
T1827 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3470495198 Jul 15 05:26:06 PM PDT 24 Jul 15 05:26:09 PM PDT 24 167418291 ps
T1828 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1855458249 Jul 15 05:25:41 PM PDT 24 Jul 15 05:25:42 PM PDT 24 104082580 ps
T1829 /workspace/coverage/cover_reg_top/45.i2c_intr_test.684769418 Jul 15 05:26:35 PM PDT 24 Jul 15 05:26:36 PM PDT 24 43718834 ps
T1830 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1311097519 Jul 15 05:25:06 PM PDT 24 Jul 15 05:25:08 PM PDT 24 50445395 ps
T1831 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1469624135 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:32 PM PDT 24 16437619 ps
T1832 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1724114868 Jul 15 05:25:11 PM PDT 24 Jul 15 05:25:13 PM PDT 24 43134399 ps
T1833 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1974842242 Jul 15 05:25:53 PM PDT 24 Jul 15 05:25:55 PM PDT 24 244169779 ps
T1834 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2112473339 Jul 15 05:25:42 PM PDT 24 Jul 15 05:25:46 PM PDT 24 132967804 ps
T1835 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2235388808 Jul 15 05:25:33 PM PDT 24 Jul 15 05:25:34 PM PDT 24 32025003 ps
T1836 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.4243512888 Jul 15 05:25:06 PM PDT 24 Jul 15 05:25:09 PM PDT 24 251207206 ps
T1837 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.561191046 Jul 15 05:25:57 PM PDT 24 Jul 15 05:25:58 PM PDT 24 24638396 ps
T1838 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3574149414 Jul 15 05:25:50 PM PDT 24 Jul 15 05:25:53 PM PDT 24 41007408 ps
T1839 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4038457182 Jul 15 05:25:10 PM PDT 24 Jul 15 05:25:13 PM PDT 24 126171337 ps
T1840 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1696229057 Jul 15 05:25:42 PM PDT 24 Jul 15 05:25:43 PM PDT 24 46810596 ps
T1841 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.684236270 Jul 15 05:25:12 PM PDT 24 Jul 15 05:25:15 PM PDT 24 110949373 ps
T1842 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2677164079 Jul 15 05:25:42 PM PDT 24 Jul 15 05:25:45 PM PDT 24 37166517 ps
T1843 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1195416960 Jul 15 05:26:14 PM PDT 24 Jul 15 05:26:17 PM PDT 24 130544156 ps
T273 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2090810596 Jul 15 05:26:14 PM PDT 24 Jul 15 05:26:17 PM PDT 24 130135208 ps
T1844 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3687764946 Jul 15 05:26:31 PM PDT 24 Jul 15 05:26:33 PM PDT 24 22832934 ps
T1845 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3067703179 Jul 15 05:25:58 PM PDT 24 Jul 15 05:26:00 PM PDT 24 39646633 ps
T223 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2801374962 Jul 15 05:25:26 PM PDT 24 Jul 15 05:25:29 PM PDT 24 123716254 ps
T1846 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1925405200 Jul 15 05:25:31 PM PDT 24 Jul 15 05:25:32 PM PDT 24 24580971 ps
T1847 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2823904455 Jul 15 05:25:41 PM PDT 24 Jul 15 05:25:42 PM PDT 24 337804120 ps

Test location /workspace/coverage/default/34.i2c_target_perf.449620535
Short name T5
Test name
Test status
Simulation time 797140711 ps
CPU time 5.41 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:22 PM PDT 24
Peak memory 217172 kb
Host smart-c501cf3e-0521-4897-9be6-fa4b0239d1e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449620535 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_perf.449620535
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.4111943126
Short name T17
Test name
Test status
Simulation time 82104449096 ps
CPU time 1398.93 seconds
Started Jul 15 06:52:03 PM PDT 24
Finished Jul 15 07:15:23 PM PDT 24
Peak memory 1537408 kb
Host smart-aa5492a6-2065-4a5b-a3c8-6f5f67bb10a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111943126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.4111943126
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.926315499
Short name T59
Test name
Test status
Simulation time 4714267055 ps
CPU time 10.01 seconds
Started Jul 15 06:51:14 PM PDT 24
Finished Jul 15 06:51:24 PM PDT 24
Peak memory 214212 kb
Host smart-ee4ccafd-9cee-4f83-af29-797c0c668ae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926315499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.926315499
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.135435878
Short name T102
Test name
Test status
Simulation time 135544049 ps
CPU time 2.67 seconds
Started Jul 15 05:26:12 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204612 kb
Host smart-90fb4c08-9648-46a2-9c71-5a4d505d077c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135435878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.135435878
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.4150352591
Short name T16
Test name
Test status
Simulation time 9545053043 ps
CPU time 13.64 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:58 PM PDT 24
Peak memory 221272 kb
Host smart-7d15d927-7108-4722-820b-e3ead3a1e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150352591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4150352591
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.2601558892
Short name T60
Test name
Test status
Simulation time 4195114116 ps
CPU time 2.82 seconds
Started Jul 15 06:57:14 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 205644 kb
Host smart-8a377eeb-810e-4361-abb3-e2c921b955c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601558892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.2601558892
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3389699321
Short name T34
Test name
Test status
Simulation time 15080981601 ps
CPU time 670.95 seconds
Started Jul 15 06:56:00 PM PDT 24
Finished Jul 15 07:07:13 PM PDT 24
Peak memory 1751968 kb
Host smart-71c63821-c20c-4f09-915d-54d3d23f5e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389699321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3389699321
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.544053377
Short name T64
Test name
Test status
Simulation time 65933927597 ps
CPU time 207.17 seconds
Started Jul 15 06:57:01 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 971028 kb
Host smart-42415d29-eccf-4be8-9766-b65cfbc5dadd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544053377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_target_stress_all.544053377
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_override.2461363036
Short name T143
Test name
Test status
Simulation time 26590559 ps
CPU time 0.67 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:54:36 PM PDT 24
Peak memory 205156 kb
Host smart-1f3aeaec-9f40-454b-b30d-b2cb923cb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461363036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2461363036
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.1667220981
Short name T55
Test name
Test status
Simulation time 988550725 ps
CPU time 1.56 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:53 PM PDT 24
Peak memory 222704 kb
Host smart-d57643c2-d731-4e38-a230-4608ab60254e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667220981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.1667220981
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1761142333
Short name T33
Test name
Test status
Simulation time 8448317370 ps
CPU time 282.97 seconds
Started Jul 15 06:56:24 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 1753156 kb
Host smart-673b0d6b-8e67-421e-86c1-f6a0f6c1e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761142333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1761142333
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2804156777
Short name T27
Test name
Test status
Simulation time 495330297 ps
CPU time 18.89 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:54:09 PM PDT 24
Peak memory 205428 kb
Host smart-4c889b23-3461-476b-a66f-b6b61a0f65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804156777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2804156777
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2466721630
Short name T250
Test name
Test status
Simulation time 160757226 ps
CPU time 1.27 seconds
Started Jul 15 06:55:24 PM PDT 24
Finished Jul 15 06:55:26 PM PDT 24
Peak memory 205260 kb
Host smart-d8fabcb5-5182-4532-95c3-57eb7e7272a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466721630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2466721630
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2668877532
Short name T157
Test name
Test status
Simulation time 14576736 ps
CPU time 0.6 seconds
Started Jul 15 06:54:16 PM PDT 24
Finished Jul 15 06:54:17 PM PDT 24
Peak memory 204696 kb
Host smart-fac78c83-15ab-4624-958f-91ac762766c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668877532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2668877532
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2563647065
Short name T208
Test name
Test status
Simulation time 374526204 ps
CPU time 2.13 seconds
Started Jul 15 05:25:56 PM PDT 24
Finished Jul 15 05:25:58 PM PDT 24
Peak memory 204632 kb
Host smart-f4665bdc-54e8-4757-bdee-fb8b8003aa50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563647065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2563647065
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2049731121
Short name T225
Test name
Test status
Simulation time 76192784 ps
CPU time 0.75 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:51 PM PDT 24
Peak memory 204448 kb
Host smart-2c4a2b46-09c0-4d34-af3f-c103a302f755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049731121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2049731121
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.328393822
Short name T280
Test name
Test status
Simulation time 40817617937 ps
CPU time 545.35 seconds
Started Jul 15 06:57:03 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 1139128 kb
Host smart-ed40911f-8b05-4e10-b2fe-820956acb34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328393822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.328393822
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.525324125
Short name T54
Test name
Test status
Simulation time 2174653158 ps
CPU time 2.51 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:07 PM PDT 24
Peak memory 205684 kb
Host smart-c6f39b25-a12f-4e41-ba4c-f6d9d16d9829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525324125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.525324125
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.3374444477
Short name T72
Test name
Test status
Simulation time 447542103 ps
CPU time 2.84 seconds
Started Jul 15 06:51:33 PM PDT 24
Finished Jul 15 06:51:36 PM PDT 24
Peak memory 213864 kb
Host smart-28bfc0bb-e5cb-47c8-ae09-42ba2ac785bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374444477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.3374444477
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1101500540
Short name T347
Test name
Test status
Simulation time 1906512243 ps
CPU time 5.05 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:54:03 PM PDT 24
Peak memory 213992 kb
Host smart-f031e17a-5697-4d4d-b1f3-ed5cc4e2434b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101500540 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1101500540
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.860297091
Short name T195
Test name
Test status
Simulation time 69764437 ps
CPU time 0.81 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:20 PM PDT 24
Peak memory 223796 kb
Host smart-13ba9b31-c699-497b-beb1-179dd92dfabb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860297091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.860297091
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.474598418
Short name T15
Test name
Test status
Simulation time 486132284 ps
CPU time 3.33 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:06 PM PDT 24
Peak memory 205492 kb
Host smart-bc80ecc0-1fec-4ce7-91e5-9e3ab5066c93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474598418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.474598418
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1468888369
Short name T41
Test name
Test status
Simulation time 1030642345 ps
CPU time 20.59 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:54:22 PM PDT 24
Peak memory 220388 kb
Host smart-2c5d4180-32a9-43d2-811b-64110e080574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468888369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1468888369
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.634815446
Short name T131
Test name
Test status
Simulation time 41646252171 ps
CPU time 1142.88 seconds
Started Jul 15 06:57:07 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 2013576 kb
Host smart-bfbe9a60-a2c6-4f5c-ac19-8dc8835d50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634815446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.634815446
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.3184508124
Short name T28
Test name
Test status
Simulation time 829886530 ps
CPU time 8.51 seconds
Started Jul 15 06:53:17 PM PDT 24
Finished Jul 15 06:53:26 PM PDT 24
Peak memory 205444 kb
Host smart-af4626fa-3f65-428b-8ee0-30fad70d3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184508124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3184508124
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2069307277
Short name T87
Test name
Test status
Simulation time 2151018693 ps
CPU time 7.14 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 06:58:51 PM PDT 24
Peak memory 213900 kb
Host smart-38808893-7d01-4d31-b780-d50392d163d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069307277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2069307277
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.1228983352
Short name T172
Test name
Test status
Simulation time 23259920033 ps
CPU time 607.66 seconds
Started Jul 15 06:51:33 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 4147928 kb
Host smart-31740b76-807e-4a03-85ed-6bc345529d43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228983352 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.1228983352
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2381141708
Short name T221
Test name
Test status
Simulation time 83908835 ps
CPU time 2.19 seconds
Started Jul 15 05:26:12 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204552 kb
Host smart-70e701ee-8595-4d23-82ec-192f343f39c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381141708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2381141708
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1164145990
Short name T271
Test name
Test status
Simulation time 129390241 ps
CPU time 0.99 seconds
Started Jul 15 06:56:15 PM PDT 24
Finished Jul 15 06:56:17 PM PDT 24
Peak memory 205280 kb
Host smart-c06ac98c-9527-4974-b551-e653281732e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164145990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1164145990
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.428893397
Short name T47
Test name
Test status
Simulation time 1852864129 ps
CPU time 7.49 seconds
Started Jul 15 06:52:31 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 205492 kb
Host smart-0dea7b95-e1ad-4ba3-9137-6e75f0593b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428893397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.428893397
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1938233995
Short name T118
Test name
Test status
Simulation time 3595932521 ps
CPU time 84.01 seconds
Started Jul 15 06:53:09 PM PDT 24
Finished Jul 15 06:54:34 PM PDT 24
Peak memory 1082636 kb
Host smart-c4f7b92f-82ec-4242-ad8d-4253a3f34d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938233995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1938233995
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3583544453
Short name T282
Test name
Test status
Simulation time 13430118607 ps
CPU time 652.37 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 915684 kb
Host smart-606a33e9-8f3e-4473-902a-269fdf610422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583544453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3583544453
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3351316585
Short name T253
Test name
Test status
Simulation time 132067934 ps
CPU time 1.43 seconds
Started Jul 15 06:51:25 PM PDT 24
Finished Jul 15 06:51:27 PM PDT 24
Peak memory 205468 kb
Host smart-de1af161-80f3-4c55-a769-fa9296076fc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351316585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3351316585
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.326533381
Short name T276
Test name
Test status
Simulation time 19820126234 ps
CPU time 405.49 seconds
Started Jul 15 06:54:49 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 2726580 kb
Host smart-fafed4b4-a943-477c-a372-28b3a88371e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326533381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_target_stress_all.326533381
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1322670992
Short name T1542
Test name
Test status
Simulation time 1172499116 ps
CPU time 7.32 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:21 PM PDT 24
Peak memory 205456 kb
Host smart-9b10b0b7-5d0d-4e96-8cc2-e0d73f69ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322670992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1322670992
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3199073788
Short name T247
Test name
Test status
Simulation time 151933962 ps
CPU time 0.99 seconds
Started Jul 15 06:56:08 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 205420 kb
Host smart-bd0ae3f1-83ae-4928-990a-1d5cdba50560
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199073788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3199073788
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_host_override.3944168238
Short name T268
Test name
Test status
Simulation time 96300051 ps
CPU time 0.67 seconds
Started Jul 15 06:56:30 PM PDT 24
Finished Jul 15 06:56:31 PM PDT 24
Peak memory 205236 kb
Host smart-111cf3d0-5567-43a9-8e59-fb738b8a219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944168238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3944168238
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2587161754
Short name T265
Test name
Test status
Simulation time 786187428 ps
CPU time 6.7 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:25 PM PDT 24
Peak memory 205540 kb
Host smart-7230b711-aa1b-44f3-b4d6-85c59b0e746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587161754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2587161754
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.2755981809
Short name T378
Test name
Test status
Simulation time 296594973 ps
CPU time 3.93 seconds
Started Jul 15 06:51:20 PM PDT 24
Finished Jul 15 06:51:25 PM PDT 24
Peak memory 205624 kb
Host smart-9b48bc78-a992-40da-a63a-49563dd4e9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755981809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2755981809
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3761536076
Short name T503
Test name
Test status
Simulation time 6911697457 ps
CPU time 34.75 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:54:11 PM PDT 24
Peak memory 233216 kb
Host smart-5623e46a-f055-42c6-89c7-e908ad70bfa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761536076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3761536076
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1337430237
Short name T178
Test name
Test status
Simulation time 1035109509 ps
CPU time 1.72 seconds
Started Jul 15 06:55:10 PM PDT 24
Finished Jul 15 06:55:12 PM PDT 24
Peak memory 205732 kb
Host smart-eb0b2c01-2685-489c-9aa6-79bf43da8ac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337430237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1337430237
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2390414529
Short name T255
Test name
Test status
Simulation time 1752720384 ps
CPU time 19.24 seconds
Started Jul 15 06:58:18 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 205456 kb
Host smart-f73f4527-6a92-4a89-af8b-0f9ddc3270f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390414529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2390414529
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3380199547
Short name T215
Test name
Test status
Simulation time 483094874 ps
CPU time 2.1 seconds
Started Jul 15 05:25:21 PM PDT 24
Finished Jul 15 05:25:23 PM PDT 24
Peak memory 204440 kb
Host smart-7e17c739-e2bc-4b70-971a-c9342a30aa4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380199547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3380199547
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2801374962
Short name T223
Test name
Test status
Simulation time 123716254 ps
CPU time 2.15 seconds
Started Jul 15 05:25:26 PM PDT 24
Finished Jul 15 05:25:29 PM PDT 24
Peak memory 204508 kb
Host smart-496183af-c748-46e3-b28c-6b42c8413ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801374962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2801374962
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3600189329
Short name T942
Test name
Test status
Simulation time 534070055 ps
CPU time 3.02 seconds
Started Jul 15 06:51:23 PM PDT 24
Finished Jul 15 06:51:27 PM PDT 24
Peak memory 228252 kb
Host smart-08091195-badf-4849-b761-c5e9fe1ab021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600189329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3600189329
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1633598908
Short name T212
Test name
Test status
Simulation time 89467685 ps
CPU time 1.38 seconds
Started Jul 15 05:24:57 PM PDT 24
Finished Jul 15 05:24:59 PM PDT 24
Peak memory 204584 kb
Host smart-ff3bab0d-1da7-4db6-a87a-9d8ac0764d55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633598908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1633598908
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1072813294
Short name T218
Test name
Test status
Simulation time 167009214 ps
CPU time 2.04 seconds
Started Jul 15 05:25:58 PM PDT 24
Finished Jul 15 05:26:01 PM PDT 24
Peak memory 204528 kb
Host smart-1e6577f9-31db-4bf2-ac82-26a000b780d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072813294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1072813294
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1754069101
Short name T1024
Test name
Test status
Simulation time 156056269 ps
CPU time 5.56 seconds
Started Jul 15 06:51:34 PM PDT 24
Finished Jul 15 06:51:40 PM PDT 24
Peak memory 220868 kb
Host smart-8eb2a51a-5945-486c-b314-a87ad3cde008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754069101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1754069101
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.796477307
Short name T616
Test name
Test status
Simulation time 1526234313 ps
CPU time 2.64 seconds
Started Jul 15 06:53:40 PM PDT 24
Finished Jul 15 06:53:43 PM PDT 24
Peak memory 213804 kb
Host smart-4aab791f-65e7-47fb-b588-e8cdb73782ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796477307 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.796477307
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1231349341
Short name T39
Test name
Test status
Simulation time 7562322784 ps
CPU time 345.4 seconds
Started Jul 15 06:55:07 PM PDT 24
Finished Jul 15 07:00:53 PM PDT 24
Peak memory 1177292 kb
Host smart-32a86acc-d604-4a35-8add-717cbc575996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231349341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1231349341
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1354743835
Short name T238
Test name
Test status
Simulation time 99283491 ps
CPU time 1.97 seconds
Started Jul 15 05:25:05 PM PDT 24
Finished Jul 15 05:25:07 PM PDT 24
Peak memory 204560 kb
Host smart-c82e3428-d939-42c0-8353-0888f1360f0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354743835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1354743835
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4038457182
Short name T1839
Test name
Test status
Simulation time 126171337 ps
CPU time 2.59 seconds
Started Jul 15 05:25:10 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 204444 kb
Host smart-abec6c8b-9349-489e-8879-1e68386bb197
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038457182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4038457182
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2224162626
Short name T1819
Test name
Test status
Simulation time 44490194 ps
CPU time 0.79 seconds
Started Jul 15 05:25:06 PM PDT 24
Finished Jul 15 05:25:07 PM PDT 24
Peak memory 204312 kb
Host smart-122a59a9-6469-45eb-a1b0-04d7b364df85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224162626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2224162626
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2850887801
Short name T1813
Test name
Test status
Simulation time 42411806 ps
CPU time 1.02 seconds
Started Jul 15 05:25:05 PM PDT 24
Finished Jul 15 05:25:06 PM PDT 24
Peak memory 204364 kb
Host smart-079ba48d-ce03-4e24-84f4-312cb67aa47e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850887801 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2850887801
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2055651865
Short name T1825
Test name
Test status
Simulation time 27200382 ps
CPU time 0.69 seconds
Started Jul 15 05:25:04 PM PDT 24
Finished Jul 15 05:25:05 PM PDT 24
Peak memory 204340 kb
Host smart-40059136-4234-4234-b277-29338bdcf2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055651865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2055651865
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1311097519
Short name T1830
Test name
Test status
Simulation time 50445395 ps
CPU time 0.65 seconds
Started Jul 15 05:25:06 PM PDT 24
Finished Jul 15 05:25:08 PM PDT 24
Peak memory 204276 kb
Host smart-fb62a21e-a133-4639-8c48-d2ac7590ca1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311097519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1311097519
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.683169567
Short name T1767
Test name
Test status
Simulation time 115398770 ps
CPU time 1.18 seconds
Started Jul 15 05:25:04 PM PDT 24
Finished Jul 15 05:25:05 PM PDT 24
Peak memory 204568 kb
Host smart-c7ec23b2-99ca-4dc5-b936-23bd9a4a18b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683169567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out
standing.683169567
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3197043456
Short name T1797
Test name
Test status
Simulation time 656370877 ps
CPU time 2.09 seconds
Started Jul 15 05:24:57 PM PDT 24
Finished Jul 15 05:25:00 PM PDT 24
Peak memory 204444 kb
Host smart-70259190-5643-4057-a260-00b4ad08b9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197043456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3197043456
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1446970209
Short name T1779
Test name
Test status
Simulation time 47651592 ps
CPU time 1.21 seconds
Started Jul 15 05:25:12 PM PDT 24
Finished Jul 15 05:25:14 PM PDT 24
Peak memory 204612 kb
Host smart-b9f7b91f-da15-4ed9-9f3b-d50796cb14f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446970209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1446970209
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2393598001
Short name T226
Test name
Test status
Simulation time 449661983 ps
CPU time 4.63 seconds
Started Jul 15 05:25:12 PM PDT 24
Finished Jul 15 05:25:17 PM PDT 24
Peak memory 204524 kb
Host smart-00b7a1a6-848e-4986-941c-8b0704e3a8f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393598001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2393598001
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2181986838
Short name T110
Test name
Test status
Simulation time 25527855 ps
CPU time 0.77 seconds
Started Jul 15 05:25:11 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 204440 kb
Host smart-188f0acb-dfc5-410c-80fb-b20bd589b7ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181986838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2181986838
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1724114868
Short name T1832
Test name
Test status
Simulation time 43134399 ps
CPU time 0.82 seconds
Started Jul 15 05:25:11 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 204508 kb
Host smart-25ee4af9-8beb-493d-8c9c-91f6519e375a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724114868 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1724114868
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2094593386
Short name T231
Test name
Test status
Simulation time 174943973 ps
CPU time 0.68 seconds
Started Jul 15 05:25:12 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 204396 kb
Host smart-4661d95d-961a-4f6f-a553-c330f8e49050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094593386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2094593386
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2623401819
Short name T134
Test name
Test status
Simulation time 54791934 ps
CPU time 0.7 seconds
Started Jul 15 05:25:11 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 204196 kb
Host smart-d072e641-a02e-45c2-86bb-8e94f9c9661c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623401819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2623401819
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2112683200
Short name T1754
Test name
Test status
Simulation time 53571992 ps
CPU time 1.09 seconds
Started Jul 15 05:25:10 PM PDT 24
Finished Jul 15 05:25:12 PM PDT 24
Peak memory 204624 kb
Host smart-459326f1-043a-4185-a877-96a9d33f1a30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112683200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2112683200
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.4243512888
Short name T1836
Test name
Test status
Simulation time 251207206 ps
CPU time 1.51 seconds
Started Jul 15 05:25:06 PM PDT 24
Finished Jul 15 05:25:09 PM PDT 24
Peak memory 204676 kb
Host smart-95caf2db-41d9-428c-a9a1-5adfacf30cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243512888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.4243512888
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3278490512
Short name T229
Test name
Test status
Simulation time 80011969 ps
CPU time 2.15 seconds
Started Jul 15 05:25:07 PM PDT 24
Finished Jul 15 05:25:10 PM PDT 24
Peak memory 204644 kb
Host smart-fbc12d45-78ed-4572-8b47-ef9aa44f2b10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278490512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3278490512
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2480984398
Short name T1810
Test name
Test status
Simulation time 20862112 ps
CPU time 0.89 seconds
Started Jul 15 05:25:52 PM PDT 24
Finished Jul 15 05:25:54 PM PDT 24
Peak memory 204300 kb
Host smart-b9a3ab0c-9c64-49b9-aa31-5603ec220d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480984398 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2480984398
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3574149414
Short name T1838
Test name
Test status
Simulation time 41007408 ps
CPU time 0.68 seconds
Started Jul 15 05:25:50 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204336 kb
Host smart-57eb23a0-7279-4d97-b58f-aff42526b79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574149414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3574149414
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4138017085
Short name T1755
Test name
Test status
Simulation time 125241152 ps
CPU time 1.13 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204468 kb
Host smart-e881bde4-f3b2-401b-8353-9f53cb1bbb07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138017085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.4138017085
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1647851497
Short name T1793
Test name
Test status
Simulation time 30632530 ps
CPU time 1.5 seconds
Started Jul 15 05:25:52 PM PDT 24
Finished Jul 15 05:25:55 PM PDT 24
Peak memory 204412 kb
Host smart-d94e1a4a-afd4-4a5f-adcf-f05015d909e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647851497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1647851497
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.31487524
Short name T224
Test name
Test status
Simulation time 84626371 ps
CPU time 2.15 seconds
Started Jul 15 05:25:50 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204492 kb
Host smart-5119e404-5371-47f5-9289-8eeb8b8f0572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31487524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.31487524
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.561191046
Short name T1837
Test name
Test status
Simulation time 24638396 ps
CPU time 1.02 seconds
Started Jul 15 05:25:57 PM PDT 24
Finished Jul 15 05:25:58 PM PDT 24
Peak memory 204428 kb
Host smart-551679c0-020d-45b5-a162-d58e8bfc6264
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561191046 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.561191046
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1253862144
Short name T1806
Test name
Test status
Simulation time 23662676 ps
CPU time 0.81 seconds
Started Jul 15 05:25:57 PM PDT 24
Finished Jul 15 05:25:59 PM PDT 24
Peak memory 204392 kb
Host smart-ddb9875e-4832-464a-8805-2838e410ee57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253862144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1253862144
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3067703179
Short name T1845
Test name
Test status
Simulation time 39646633 ps
CPU time 0.67 seconds
Started Jul 15 05:25:58 PM PDT 24
Finished Jul 15 05:26:00 PM PDT 24
Peak memory 204236 kb
Host smart-2d6c9301-a389-406f-970a-d4e90265c67f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067703179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3067703179
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.875939966
Short name T1794
Test name
Test status
Simulation time 55065845 ps
CPU time 0.83 seconds
Started Jul 15 05:25:56 PM PDT 24
Finished Jul 15 05:25:58 PM PDT 24
Peak memory 204476 kb
Host smart-5474ff70-c28b-4733-b582-ef26a310b521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875939966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.875939966
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.225981992
Short name T217
Test name
Test status
Simulation time 194035255 ps
CPU time 1.38 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:52 PM PDT 24
Peak memory 204608 kb
Host smart-52c170e7-5d41-47cb-8c3f-e659da66ec3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225981992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.225981992
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.629585788
Short name T209
Test name
Test status
Simulation time 54125626 ps
CPU time 1.47 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:50 PM PDT 24
Peak memory 204560 kb
Host smart-7141e9f5-6aa8-45ab-8105-0f6f40b49575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629585788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.629585788
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2283387122
Short name T109
Test name
Test status
Simulation time 81235691 ps
CPU time 0.77 seconds
Started Jul 15 05:25:56 PM PDT 24
Finished Jul 15 05:25:58 PM PDT 24
Peak memory 204392 kb
Host smart-c12488a7-8948-4177-bc7a-a7c3fda8cee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283387122 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2283387122
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2653683371
Short name T243
Test name
Test status
Simulation time 20139263 ps
CPU time 0.69 seconds
Started Jul 15 05:25:56 PM PDT 24
Finished Jul 15 05:25:58 PM PDT 24
Peak memory 204420 kb
Host smart-6491894d-c111-4acd-a514-b9875be2b8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653683371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2653683371
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.491628496
Short name T1790
Test name
Test status
Simulation time 60285404 ps
CPU time 0.66 seconds
Started Jul 15 05:25:56 PM PDT 24
Finished Jul 15 05:25:57 PM PDT 24
Peak memory 204300 kb
Host smart-629ec266-055f-4918-b65c-b076446789f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491628496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.491628496
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3355501129
Short name T244
Test name
Test status
Simulation time 34905701 ps
CPU time 0.9 seconds
Started Jul 15 05:25:58 PM PDT 24
Finished Jul 15 05:25:59 PM PDT 24
Peak memory 204404 kb
Host smart-ab4d6a68-4a39-4bfa-b10e-104d9b3f92aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355501129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3355501129
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.463638858
Short name T1816
Test name
Test status
Simulation time 74795030 ps
CPU time 2.04 seconds
Started Jul 15 05:25:57 PM PDT 24
Finished Jul 15 05:26:00 PM PDT 24
Peak memory 204492 kb
Host smart-1dcb6f40-111d-4bff-853e-20c1d384a4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463638858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.463638858
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3470495198
Short name T1827
Test name
Test status
Simulation time 167418291 ps
CPU time 1.78 seconds
Started Jul 15 05:26:06 PM PDT 24
Finished Jul 15 05:26:09 PM PDT 24
Peak memory 212788 kb
Host smart-53e985b7-29ed-435f-8054-dfda59b591ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470495198 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3470495198
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1888082180
Short name T1772
Test name
Test status
Simulation time 21960146 ps
CPU time 0.72 seconds
Started Jul 15 05:25:58 PM PDT 24
Finished Jul 15 05:25:59 PM PDT 24
Peak memory 204632 kb
Host smart-d24af4a9-f6ad-4a91-a872-160802a4dda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888082180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1888082180
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.168251881
Short name T1744
Test name
Test status
Simulation time 40544346 ps
CPU time 0.69 seconds
Started Jul 15 05:25:57 PM PDT 24
Finished Jul 15 05:25:59 PM PDT 24
Peak memory 204328 kb
Host smart-77b489e4-6b74-4d3f-9976-dd495a6c1beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168251881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.168251881
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1541224574
Short name T1807
Test name
Test status
Simulation time 226996386 ps
CPU time 1.25 seconds
Started Jul 15 05:26:06 PM PDT 24
Finished Jul 15 05:26:08 PM PDT 24
Peak memory 204580 kb
Host smart-23096152-3379-4203-8168-57dd519864f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541224574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1541224574
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2129263092
Short name T210
Test name
Test status
Simulation time 31569331 ps
CPU time 1.45 seconds
Started Jul 15 05:25:57 PM PDT 24
Finished Jul 15 05:25:59 PM PDT 24
Peak memory 204560 kb
Host smart-804f332b-1ea5-4565-a5ca-6cbb25f7ae64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129263092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2129263092
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3649883753
Short name T1821
Test name
Test status
Simulation time 66155865 ps
CPU time 0.91 seconds
Started Jul 15 05:26:04 PM PDT 24
Finished Jul 15 05:26:06 PM PDT 24
Peak memory 204500 kb
Host smart-be26ebb3-a8a4-45a3-9b18-f783cfdd99d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649883753 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3649883753
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1706572699
Short name T1776
Test name
Test status
Simulation time 24982920 ps
CPU time 0.78 seconds
Started Jul 15 05:26:05 PM PDT 24
Finished Jul 15 05:26:06 PM PDT 24
Peak memory 204340 kb
Host smart-36d87fbe-2175-407e-abd1-bc40a9827640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706572699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1706572699
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3473163482
Short name T1758
Test name
Test status
Simulation time 242746423 ps
CPU time 0.71 seconds
Started Jul 15 05:26:06 PM PDT 24
Finished Jul 15 05:26:07 PM PDT 24
Peak memory 204344 kb
Host smart-69c0be3e-ea1e-45bf-905b-d2365ebc6f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473163482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3473163482
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3371092054
Short name T1799
Test name
Test status
Simulation time 127687356 ps
CPU time 1.96 seconds
Started Jul 15 05:26:05 PM PDT 24
Finished Jul 15 05:26:08 PM PDT 24
Peak memory 204568 kb
Host smart-8109b0e2-e9ac-43f3-a0e8-bbc295d43705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371092054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3371092054
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2575761448
Short name T222
Test name
Test status
Simulation time 91066975 ps
CPU time 1.43 seconds
Started Jul 15 05:26:07 PM PDT 24
Finished Jul 15 05:26:09 PM PDT 24
Peak memory 204436 kb
Host smart-267817f4-ed02-4da9-ba1c-edd8e129b565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575761448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2575761448
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1660859888
Short name T1769
Test name
Test status
Simulation time 57266845 ps
CPU time 0.98 seconds
Started Jul 15 05:26:06 PM PDT 24
Finished Jul 15 05:26:07 PM PDT 24
Peak memory 204532 kb
Host smart-bf3f855f-49a3-4973-ac6e-1fd68d988b32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660859888 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1660859888
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2933110504
Short name T1791
Test name
Test status
Simulation time 52590244 ps
CPU time 0.73 seconds
Started Jul 15 05:26:04 PM PDT 24
Finished Jul 15 05:26:05 PM PDT 24
Peak memory 204372 kb
Host smart-8c91a413-0cc2-42db-864c-aa72314596fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933110504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2933110504
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3614843769
Short name T1804
Test name
Test status
Simulation time 27639994 ps
CPU time 0.69 seconds
Started Jul 15 05:26:04 PM PDT 24
Finished Jul 15 05:26:05 PM PDT 24
Peak memory 204360 kb
Host smart-ca5107fa-d82f-4e49-9706-d76ac3ef808b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614843769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3614843769
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.278173
Short name T1823
Test name
Test status
Simulation time 152117391 ps
CPU time 0.97 seconds
Started Jul 15 05:26:04 PM PDT 24
Finished Jul 15 05:26:06 PM PDT 24
Peak memory 204476 kb
Host smart-b8a0a6a4-9cd1-4807-8094-764580669bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outst
anding.278173
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3747136368
Short name T1815
Test name
Test status
Simulation time 203955747 ps
CPU time 2.52 seconds
Started Jul 15 05:26:07 PM PDT 24
Finished Jul 15 05:26:10 PM PDT 24
Peak memory 204620 kb
Host smart-a2c2156e-efcb-4291-8263-7b114494394e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747136368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3747136368
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2448066414
Short name T213
Test name
Test status
Simulation time 48392211 ps
CPU time 1.4 seconds
Started Jul 15 05:26:53 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 204584 kb
Host smart-40f84170-c9d0-438b-9511-dc3ebca4e615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448066414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2448066414
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.757345057
Short name T191
Test name
Test status
Simulation time 114140381 ps
CPU time 1.03 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:16 PM PDT 24
Peak memory 204492 kb
Host smart-64a67888-8800-4af3-abb9-51edb06e09d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757345057 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.757345057
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2528740425
Short name T232
Test name
Test status
Simulation time 15597928 ps
CPU time 0.7 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204308 kb
Host smart-07abe196-2361-4096-9e4e-9141409f51a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528740425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2528740425
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.4193342884
Short name T1811
Test name
Test status
Simulation time 46397386 ps
CPU time 0.68 seconds
Started Jul 15 05:26:12 PM PDT 24
Finished Jul 15 05:26:13 PM PDT 24
Peak memory 204252 kb
Host smart-500fad58-8211-45d2-80e0-c8adec39e47b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193342884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4193342884
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2916321558
Short name T241
Test name
Test status
Simulation time 50315739 ps
CPU time 0.9 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204336 kb
Host smart-5098a071-f4fc-4dda-b3b2-2e6ada2d4d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916321558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2916321558
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2090810596
Short name T273
Test name
Test status
Simulation time 130135208 ps
CPU time 2.28 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:17 PM PDT 24
Peak memory 204464 kb
Host smart-55056f4b-e5e8-434d-945b-87a035793785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090810596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2090810596
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3295684273
Short name T108
Test name
Test status
Simulation time 37828325 ps
CPU time 1 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204480 kb
Host smart-51727341-466e-4db2-be31-1c973a518fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295684273 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3295684273
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1170590538
Short name T111
Test name
Test status
Simulation time 46582264 ps
CPU time 0.77 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:16 PM PDT 24
Peak memory 204376 kb
Host smart-cd2dba22-d383-4942-8603-3b51d1946cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170590538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1170590538
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2602044527
Short name T1795
Test name
Test status
Simulation time 34670861 ps
CPU time 0.66 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204284 kb
Host smart-eb599c61-b0b1-483a-a887-d2c3aa65c344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602044527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2602044527
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3519427025
Short name T1775
Test name
Test status
Simulation time 56987857 ps
CPU time 0.88 seconds
Started Jul 15 05:26:15 PM PDT 24
Finished Jul 15 05:26:17 PM PDT 24
Peak memory 204308 kb
Host smart-98d8f96f-bd3f-4dd6-8bd0-624dd12ffd51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519427025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3519427025
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3220871419
Short name T1786
Test name
Test status
Simulation time 391484856 ps
CPU time 2.01 seconds
Started Jul 15 05:26:12 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204668 kb
Host smart-d3794e04-107e-487f-95cb-668ba307a82d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220871419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3220871419
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2275804879
Short name T214
Test name
Test status
Simulation time 308370160 ps
CPU time 1.49 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204624 kb
Host smart-19d7f898-abb7-41ee-b934-c12682f9f24c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275804879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2275804879
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2191564929
Short name T1796
Test name
Test status
Simulation time 29218636 ps
CPU time 1.33 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204636 kb
Host smart-165d534f-995d-4318-af19-ccf1897b58f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191564929 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2191564929
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2046353344
Short name T1784
Test name
Test status
Simulation time 18483374 ps
CPU time 0.71 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:16 PM PDT 24
Peak memory 204308 kb
Host smart-21a9878e-28b7-40ed-afb3-d122b811474e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046353344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2046353344
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3995834801
Short name T1812
Test name
Test status
Simulation time 40307203 ps
CPU time 0.7 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204340 kb
Host smart-9e57cf95-8833-4b30-ad5d-55ca88c45e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995834801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3995834801
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2180237656
Short name T242
Test name
Test status
Simulation time 107405538 ps
CPU time 1.12 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:16 PM PDT 24
Peak memory 204592 kb
Host smart-bccdc335-c4de-4388-97e6-eae273fe61c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180237656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2180237656
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.560853783
Short name T1766
Test name
Test status
Simulation time 152862424 ps
CPU time 1.73 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:17 PM PDT 24
Peak memory 204664 kb
Host smart-cd467e06-db83-4f18-b97e-dfb0194a1eee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560853783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.560853783
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3895286492
Short name T103
Test name
Test status
Simulation time 30341068 ps
CPU time 0.81 seconds
Started Jul 15 05:26:23 PM PDT 24
Finished Jul 15 05:26:24 PM PDT 24
Peak memory 204488 kb
Host smart-87389d28-a920-46f1-89d8-dd2a0d8dc172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895286492 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3895286492
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2697906270
Short name T1801
Test name
Test status
Simulation time 29254162 ps
CPU time 0.79 seconds
Started Jul 15 05:26:15 PM PDT 24
Finished Jul 15 05:26:16 PM PDT 24
Peak memory 204280 kb
Host smart-37eaf6f5-7670-4aae-b32c-176d56b44ae3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697906270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2697906270
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3678365185
Short name T1771
Test name
Test status
Simulation time 48292150 ps
CPU time 0.69 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:14 PM PDT 24
Peak memory 204340 kb
Host smart-e332b6d9-1ae8-4b6f-84e8-7c14190421d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678365185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3678365185
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1505380842
Short name T1808
Test name
Test status
Simulation time 30496110 ps
CPU time 0.84 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204268 kb
Host smart-f6c46bd4-2327-4eda-8ac5-278c675b6dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505380842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1505380842
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1195416960
Short name T1843
Test name
Test status
Simulation time 130544156 ps
CPU time 2.04 seconds
Started Jul 15 05:26:14 PM PDT 24
Finished Jul 15 05:26:17 PM PDT 24
Peak memory 204604 kb
Host smart-79ac225d-90cd-4360-9bbe-2cd599e722e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195416960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1195416960
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.704535266
Short name T105
Test name
Test status
Simulation time 338937675 ps
CPU time 1.44 seconds
Started Jul 15 05:26:13 PM PDT 24
Finished Jul 15 05:26:15 PM PDT 24
Peak memory 204564 kb
Host smart-28422924-bd13-41eb-85e0-3e467ee9d8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704535266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.704535266
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2212029761
Short name T1752
Test name
Test status
Simulation time 45424779 ps
CPU time 1.23 seconds
Started Jul 15 05:25:27 PM PDT 24
Finished Jul 15 05:25:29 PM PDT 24
Peak memory 204504 kb
Host smart-c2dbe075-3453-49de-bc40-ac73836c95ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212029761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2212029761
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3658546811
Short name T1818
Test name
Test status
Simulation time 291542029 ps
CPU time 2.91 seconds
Started Jul 15 05:25:27 PM PDT 24
Finished Jul 15 05:25:30 PM PDT 24
Peak memory 204580 kb
Host smart-35019005-c88b-4fa3-a696-92a5c7644a38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658546811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3658546811
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2243425300
Short name T239
Test name
Test status
Simulation time 54510249 ps
CPU time 0.7 seconds
Started Jul 15 05:25:17 PM PDT 24
Finished Jul 15 05:25:18 PM PDT 24
Peak memory 204396 kb
Host smart-d4eb1328-c9c7-45e3-93d4-c6b2a9385d97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243425300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2243425300
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3946371107
Short name T107
Test name
Test status
Simulation time 103967229 ps
CPU time 0.82 seconds
Started Jul 15 05:25:26 PM PDT 24
Finished Jul 15 05:25:27 PM PDT 24
Peak memory 204380 kb
Host smart-e100596c-2054-4661-9c8f-4a6b0d6f6ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946371107 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3946371107
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.975157225
Short name T104
Test name
Test status
Simulation time 49917538 ps
CPU time 0.72 seconds
Started Jul 15 05:25:21 PM PDT 24
Finished Jul 15 05:25:22 PM PDT 24
Peak memory 204452 kb
Host smart-5bfed807-9761-41b6-85e5-22e736b8a08f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975157225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.975157225
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2927770147
Short name T1792
Test name
Test status
Simulation time 18625151 ps
CPU time 0.69 seconds
Started Jul 15 05:25:21 PM PDT 24
Finished Jul 15 05:25:22 PM PDT 24
Peak memory 204252 kb
Host smart-144f95b0-760c-45f1-bc2d-e6ddd61a77af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927770147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2927770147
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2926651888
Short name T1785
Test name
Test status
Simulation time 68649926 ps
CPU time 0.85 seconds
Started Jul 15 05:25:26 PM PDT 24
Finished Jul 15 05:25:27 PM PDT 24
Peak memory 204392 kb
Host smart-d3e4af0e-f9b5-446d-88ca-56a235f4a5df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926651888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2926651888
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.684236270
Short name T1841
Test name
Test status
Simulation time 110949373 ps
CPU time 2.26 seconds
Started Jul 15 05:25:12 PM PDT 24
Finished Jul 15 05:25:15 PM PDT 24
Peak memory 212752 kb
Host smart-4fa8464e-a3cc-43cb-a160-8a8e391dafe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684236270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.684236270
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.977821254
Short name T1809
Test name
Test status
Simulation time 52232098 ps
CPU time 0.7 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:22 PM PDT 24
Peak memory 204220 kb
Host smart-52f8f2c4-ac74-4906-9942-463cf97a098d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977821254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.977821254
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4123955196
Short name T1800
Test name
Test status
Simulation time 16668647 ps
CPU time 0.69 seconds
Started Jul 15 05:26:20 PM PDT 24
Finished Jul 15 05:26:21 PM PDT 24
Peak memory 204368 kb
Host smart-3cfed494-8ae7-4046-8c0d-b271d2fe018d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123955196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4123955196
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1098524092
Short name T1740
Test name
Test status
Simulation time 20846831 ps
CPU time 0.66 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:22 PM PDT 24
Peak memory 204244 kb
Host smart-ca9e25fa-28cf-44e1-bc62-dadf5a06725e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098524092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1098524092
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2305156560
Short name T1783
Test name
Test status
Simulation time 42642427 ps
CPU time 0.72 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204320 kb
Host smart-933ac112-1e44-496a-8455-d6f0df225425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305156560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2305156560
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.888016051
Short name T1742
Test name
Test status
Simulation time 16694027 ps
CPU time 0.68 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:22 PM PDT 24
Peak memory 204332 kb
Host smart-9433c24f-d8b2-47d6-94d3-e41ff88dc9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888016051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.888016051
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1910126695
Short name T1805
Test name
Test status
Simulation time 56734366 ps
CPU time 0.62 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:22 PM PDT 24
Peak memory 204308 kb
Host smart-1904e733-bf72-4fba-82a6-f88eb68e94de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910126695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1910126695
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.611480434
Short name T1743
Test name
Test status
Simulation time 49916324 ps
CPU time 0.7 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:24 PM PDT 24
Peak memory 204300 kb
Host smart-8874fb2e-57ab-45c1-b72e-ed2abb401825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611480434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.611480434
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.4139562671
Short name T1824
Test name
Test status
Simulation time 47125533 ps
CPU time 0.7 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204284 kb
Host smart-c6f4bbb4-e645-47c4-aa11-172a0644e669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139562671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.4139562671
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.938830558
Short name T1745
Test name
Test status
Simulation time 116462521 ps
CPU time 0.66 seconds
Started Jul 15 05:26:24 PM PDT 24
Finished Jul 15 05:26:25 PM PDT 24
Peak memory 204236 kb
Host smart-3fd4ecf7-d85b-410c-b7df-5256e20d8447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938830558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.938830558
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3684898964
Short name T1749
Test name
Test status
Simulation time 14590648 ps
CPU time 0.68 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:24 PM PDT 24
Peak memory 204392 kb
Host smart-687d6dc8-6260-4b1e-959e-8de71d87fb4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684898964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3684898964
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.315781793
Short name T233
Test name
Test status
Simulation time 342166224 ps
CPU time 1.94 seconds
Started Jul 15 05:25:34 PM PDT 24
Finished Jul 15 05:25:36 PM PDT 24
Peak memory 204496 kb
Host smart-3df78e23-897f-42da-886b-5d39789bf023
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315781793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.315781793
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3774340472
Short name T1826
Test name
Test status
Simulation time 1092499662 ps
CPU time 2.97 seconds
Started Jul 15 05:25:35 PM PDT 24
Finished Jul 15 05:25:38 PM PDT 24
Peak memory 204588 kb
Host smart-51412c94-5a2f-4f6e-8e24-1965ba896201
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774340472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3774340472
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2235388808
Short name T1835
Test name
Test status
Simulation time 32025003 ps
CPU time 0.74 seconds
Started Jul 15 05:25:33 PM PDT 24
Finished Jul 15 05:25:34 PM PDT 24
Peak memory 204452 kb
Host smart-3c0c7f52-ee7f-4891-a679-a9221d3481ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235388808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2235388808
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4030059849
Short name T220
Test name
Test status
Simulation time 98444634 ps
CPU time 1.32 seconds
Started Jul 15 05:25:33 PM PDT 24
Finished Jul 15 05:25:35 PM PDT 24
Peak memory 204560 kb
Host smart-bdf81c80-5fd8-483b-bcb3-fff323c32ee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030059849 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.4030059849
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1719062354
Short name T240
Test name
Test status
Simulation time 43627925 ps
CPU time 0.79 seconds
Started Jul 15 05:25:34 PM PDT 24
Finished Jul 15 05:25:35 PM PDT 24
Peak memory 204332 kb
Host smart-5890b7dc-2414-4743-ab56-0f5af69fd291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719062354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1719062354
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1925405200
Short name T1846
Test name
Test status
Simulation time 24580971 ps
CPU time 0.64 seconds
Started Jul 15 05:25:31 PM PDT 24
Finished Jul 15 05:25:32 PM PDT 24
Peak memory 204252 kb
Host smart-d3fda214-5b39-419d-a72a-be7911fd04fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925405200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1925405200
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3904179770
Short name T1778
Test name
Test status
Simulation time 34097480 ps
CPU time 0.86 seconds
Started Jul 15 05:25:33 PM PDT 24
Finished Jul 15 05:25:35 PM PDT 24
Peak memory 204380 kb
Host smart-13f1d952-340f-419b-bd1a-4043c69e264e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904179770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3904179770
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1247158961
Short name T1765
Test name
Test status
Simulation time 186421862 ps
CPU time 2.56 seconds
Started Jul 15 05:25:26 PM PDT 24
Finished Jul 15 05:25:29 PM PDT 24
Peak memory 204588 kb
Host smart-83327263-49e2-4bdb-b3cd-5ea5d6b95607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247158961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1247158961
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3429248248
Short name T284
Test name
Test status
Simulation time 43178460 ps
CPU time 0.69 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:24 PM PDT 24
Peak memory 204312 kb
Host smart-d46a543b-63a3-4ae8-b575-6277729dfbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429248248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3429248248
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3634052596
Short name T1789
Test name
Test status
Simulation time 80497879 ps
CPU time 0.66 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204396 kb
Host smart-cdc695eb-d69a-4f4d-8c11-d83d44fd1206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634052596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3634052596
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.983739651
Short name T1817
Test name
Test status
Simulation time 55433153 ps
CPU time 0.68 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204284 kb
Host smart-ef22815d-7520-4bd4-8376-8b4d91cb442e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983739651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.983739651
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2980819416
Short name T1756
Test name
Test status
Simulation time 18551228 ps
CPU time 0.67 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204328 kb
Host smart-9b361f7b-f529-4eed-84e3-481714ce9475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980819416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2980819416
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3816115006
Short name T1759
Test name
Test status
Simulation time 44635437 ps
CPU time 0.68 seconds
Started Jul 15 05:26:19 PM PDT 24
Finished Jul 15 05:26:20 PM PDT 24
Peak memory 204332 kb
Host smart-4297b7e4-1aeb-436d-bbd8-d21db4543332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816115006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3816115006
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3604192692
Short name T1820
Test name
Test status
Simulation time 21251952 ps
CPU time 0.73 seconds
Started Jul 15 05:26:21 PM PDT 24
Finished Jul 15 05:26:22 PM PDT 24
Peak memory 204316 kb
Host smart-332b8379-abcc-4290-a4b4-85739899a856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604192692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3604192692
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3294755411
Short name T1751
Test name
Test status
Simulation time 47893152 ps
CPU time 0.68 seconds
Started Jul 15 05:26:22 PM PDT 24
Finished Jul 15 05:26:23 PM PDT 24
Peak memory 204252 kb
Host smart-7239dfa5-7f19-4d6f-9b5f-89c1120ac36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294755411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3294755411
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3687764946
Short name T1844
Test name
Test status
Simulation time 22832934 ps
CPU time 0.69 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:33 PM PDT 24
Peak memory 204344 kb
Host smart-1fbe84f8-3602-49d3-9d0c-386536cad354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687764946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3687764946
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3195366584
Short name T1753
Test name
Test status
Simulation time 21578749 ps
CPU time 0.72 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:34 PM PDT 24
Peak memory 204216 kb
Host smart-15e61201-bd1e-4823-870a-3a3259d90e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195366584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3195366584
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.4228149394
Short name T1787
Test name
Test status
Simulation time 17110426 ps
CPU time 0.7 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:33 PM PDT 24
Peak memory 204356 kb
Host smart-953631a3-18c0-4a8f-9339-89d04e330824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228149394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4228149394
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2665886461
Short name T1750
Test name
Test status
Simulation time 99963503 ps
CPU time 1.16 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204464 kb
Host smart-337e44f6-abc8-4091-a226-7a5e607a3971
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665886461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2665886461
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1212034306
Short name T237
Test name
Test status
Simulation time 66600469 ps
CPU time 2.6 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204596 kb
Host smart-07edee00-bf57-459a-8972-33406e815908
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212034306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1212034306
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2169055400
Short name T1773
Test name
Test status
Simulation time 23984688 ps
CPU time 0.72 seconds
Started Jul 15 05:25:43 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204416 kb
Host smart-e641ed07-a4ca-456b-b842-3a38e94b8deb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169055400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2169055400
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2120609993
Short name T1768
Test name
Test status
Simulation time 22887224 ps
CPU time 1.12 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204480 kb
Host smart-55450940-c25a-4dde-960e-c04bdb12671b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120609993 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2120609993
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.451946299
Short name T236
Test name
Test status
Simulation time 41252780 ps
CPU time 0.68 seconds
Started Jul 15 05:25:45 PM PDT 24
Finished Jul 15 05:25:46 PM PDT 24
Peak memory 204376 kb
Host smart-a0f07ebf-74d0-4adf-bb05-a3566e49b838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451946299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.451946299
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1545877307
Short name T1761
Test name
Test status
Simulation time 33124883 ps
CPU time 0.72 seconds
Started Jul 15 05:26:28 PM PDT 24
Finished Jul 15 05:26:29 PM PDT 24
Peak memory 204352 kb
Host smart-86264336-ee0f-44eb-a213-940ea296d799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545877307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1545877307
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3145799558
Short name T128
Test name
Test status
Simulation time 133200571 ps
CPU time 0.9 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204416 kb
Host smart-5350845a-d7a3-46c1-a225-96f878468b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145799558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3145799558
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3913281147
Short name T1803
Test name
Test status
Simulation time 276184494 ps
CPU time 2.75 seconds
Started Jul 15 05:25:34 PM PDT 24
Finished Jul 15 05:25:37 PM PDT 24
Peak memory 204568 kb
Host smart-52571ada-76df-4211-ae3d-11a7289c709a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913281147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3913281147
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4119261421
Short name T227
Test name
Test status
Simulation time 88988501 ps
CPU time 2.17 seconds
Started Jul 15 05:25:40 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204608 kb
Host smart-f56b9cee-1f58-45df-a789-7c9bedebf03c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119261421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4119261421
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2013995430
Short name T133
Test name
Test status
Simulation time 27064803 ps
CPU time 0.7 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:34 PM PDT 24
Peak memory 204320 kb
Host smart-77cc1da6-5cbe-4c4c-9538-a5f7ce59bfbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013995430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2013995430
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2337422458
Short name T1781
Test name
Test status
Simulation time 17078529 ps
CPU time 0.72 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:33 PM PDT 24
Peak memory 204392 kb
Host smart-76e115a1-014b-4a64-a77e-69174d19b207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337422458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2337422458
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3151205529
Short name T1782
Test name
Test status
Simulation time 54942173 ps
CPU time 0.71 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:32 PM PDT 24
Peak memory 204348 kb
Host smart-aa4a8dcf-eefc-4fb9-b5f4-3120a5cb2e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151205529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3151205529
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1924378472
Short name T1741
Test name
Test status
Simulation time 54887561 ps
CPU time 0.7 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:34 PM PDT 24
Peak memory 204232 kb
Host smart-cf9bae37-3f7a-4bb9-afb7-be37c71f89ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924378472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1924378472
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1469624135
Short name T1831
Test name
Test status
Simulation time 16437619 ps
CPU time 0.68 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:32 PM PDT 24
Peak memory 204268 kb
Host smart-63393a53-b7fc-4f6c-96ff-e13911e0c747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469624135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1469624135
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.684769418
Short name T1829
Test name
Test status
Simulation time 43718834 ps
CPU time 0.68 seconds
Started Jul 15 05:26:35 PM PDT 24
Finished Jul 15 05:26:36 PM PDT 24
Peak memory 204236 kb
Host smart-4f2ed950-115f-49e6-b8d3-786285953f6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684769418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.684769418
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.4250206635
Short name T1802
Test name
Test status
Simulation time 148596595 ps
CPU time 0.7 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:33 PM PDT 24
Peak memory 204284 kb
Host smart-f31e3fdf-ca7e-4087-921d-5579055dee03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250206635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.4250206635
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2051572542
Short name T1822
Test name
Test status
Simulation time 31038251 ps
CPU time 0.7 seconds
Started Jul 15 05:26:37 PM PDT 24
Finished Jul 15 05:26:38 PM PDT 24
Peak memory 204148 kb
Host smart-d9603bb6-7d8a-4727-b09e-75158207c6cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051572542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2051572542
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2445270593
Short name T1764
Test name
Test status
Simulation time 16345584 ps
CPU time 0.69 seconds
Started Jul 15 05:26:37 PM PDT 24
Finished Jul 15 05:26:38 PM PDT 24
Peak memory 204196 kb
Host smart-dd87b491-45a4-4027-9d65-dcffba884554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445270593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2445270593
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2688221187
Short name T1770
Test name
Test status
Simulation time 23824652 ps
CPU time 0.69 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:34 PM PDT 24
Peak memory 204248 kb
Host smart-d31eb741-cf13-40ae-9dcb-fb1f01b4b3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688221187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2688221187
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1204395971
Short name T1760
Test name
Test status
Simulation time 20506231 ps
CPU time 0.86 seconds
Started Jul 15 05:25:43 PM PDT 24
Finished Jul 15 05:25:45 PM PDT 24
Peak memory 204516 kb
Host smart-c1b4310e-1a44-4aad-8ad4-bdbe4e771adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204395971 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1204395971
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4055861335
Short name T230
Test name
Test status
Simulation time 41271076 ps
CPU time 0.69 seconds
Started Jul 15 05:25:43 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204292 kb
Host smart-d3e17a3b-9b15-411f-a384-962de89feda6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055861335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4055861335
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3353514961
Short name T1763
Test name
Test status
Simulation time 51905683 ps
CPU time 0.67 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204300 kb
Host smart-c6b3419a-893b-4a90-aebc-4d4226264c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353514961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3353514961
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1696229057
Short name T1840
Test name
Test status
Simulation time 46810596 ps
CPU time 1.08 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204636 kb
Host smart-b65f977c-5478-448f-995e-fc78bfbcdf1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696229057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1696229057
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2823904455
Short name T1847
Test name
Test status
Simulation time 337804120 ps
CPU time 1.19 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:42 PM PDT 24
Peak memory 204656 kb
Host smart-12ab8d93-edd1-4e51-a855-9bb868fe3755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823904455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2823904455
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2562528759
Short name T219
Test name
Test status
Simulation time 635324622 ps
CPU time 1.42 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204464 kb
Host smart-6a092bf7-ed20-4d15-9f86-495c434ce14e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562528759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2562528759
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1855458249
Short name T1828
Test name
Test status
Simulation time 104082580 ps
CPU time 0.98 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:42 PM PDT 24
Peak memory 204480 kb
Host smart-b52d8a46-13c7-4ee6-9fe6-1da6b9e71b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855458249 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1855458249
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.555404261
Short name T106
Test name
Test status
Simulation time 214442241 ps
CPU time 0.78 seconds
Started Jul 15 05:25:43 PM PDT 24
Finished Jul 15 05:25:45 PM PDT 24
Peak memory 204360 kb
Host smart-2e9fb12d-3835-4b9a-8c13-e73970071d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555404261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.555404261
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2674028991
Short name T1780
Test name
Test status
Simulation time 49370923 ps
CPU time 0.68 seconds
Started Jul 15 05:25:41 PM PDT 24
Finished Jul 15 05:25:43 PM PDT 24
Peak memory 204288 kb
Host smart-d03169e4-9cc8-4403-83a6-b76ac4ea4521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674028991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2674028991
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3173079469
Short name T1774
Test name
Test status
Simulation time 62292639 ps
CPU time 0.8 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:51 PM PDT 24
Peak memory 204392 kb
Host smart-75873e2d-982f-4f00-b68e-48d029d02de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173079469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3173079469
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2112473339
Short name T1834
Test name
Test status
Simulation time 132967804 ps
CPU time 2.67 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:46 PM PDT 24
Peak memory 212724 kb
Host smart-42b720d3-1b3c-424e-ab4e-031c24b3cac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112473339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2112473339
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1651453498
Short name T1814
Test name
Test status
Simulation time 61625881 ps
CPU time 1.45 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:44 PM PDT 24
Peak memory 204540 kb
Host smart-c61f4448-ecc5-4c74-9639-9463b2daf56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651453498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1651453498
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3562841386
Short name T216
Test name
Test status
Simulation time 59164541 ps
CPU time 0.82 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204372 kb
Host smart-b96320cf-9cc4-42b5-9f97-c63fcda2acd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562841386 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3562841386
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.143849558
Short name T235
Test name
Test status
Simulation time 51102167 ps
CPU time 0.77 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204292 kb
Host smart-247fa406-6939-4342-abd6-df5b897912bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143849558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.143849558
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3491194617
Short name T1748
Test name
Test status
Simulation time 18546922 ps
CPU time 0.69 seconds
Started Jul 15 05:25:50 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204316 kb
Host smart-2b4b8f7d-a429-4c2c-afa9-8e43feac1589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491194617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3491194617
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3430070993
Short name T1762
Test name
Test status
Simulation time 34334812 ps
CPU time 0.85 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204344 kb
Host smart-469ede5e-fd4e-4234-aeaf-a1822924ba92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430070993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3430070993
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2677164079
Short name T1842
Test name
Test status
Simulation time 37166517 ps
CPU time 1.96 seconds
Started Jul 15 05:25:42 PM PDT 24
Finished Jul 15 05:25:45 PM PDT 24
Peak memory 204676 kb
Host smart-0169ffe3-4ec6-44b7-85e0-698f2b884884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677164079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2677164079
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1618464399
Short name T206
Test name
Test status
Simulation time 88757684 ps
CPU time 2.18 seconds
Started Jul 15 05:25:53 PM PDT 24
Finished Jul 15 05:25:56 PM PDT 24
Peak memory 204432 kb
Host smart-b5b8ca02-6a14-4d4d-8306-1d212614545a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618464399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1618464399
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1536475391
Short name T159
Test name
Test status
Simulation time 39918875 ps
CPU time 1.04 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:51 PM PDT 24
Peak memory 204384 kb
Host smart-2c15b016-8caf-4164-b23f-5681eb89d0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536475391 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1536475391
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.33660699
Short name T234
Test name
Test status
Simulation time 27926232 ps
CPU time 0.82 seconds
Started Jul 15 05:25:52 PM PDT 24
Finished Jul 15 05:25:54 PM PDT 24
Peak memory 204468 kb
Host smart-f6a68253-44aa-4dcf-a754-49220a4d7ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33660699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.33660699
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1661615200
Short name T1746
Test name
Test status
Simulation time 16107764 ps
CPU time 0.72 seconds
Started Jul 15 05:25:50 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204320 kb
Host smart-a815b6e5-a527-40e2-82fa-963e2bd0407b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661615200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1661615200
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2048480560
Short name T1798
Test name
Test status
Simulation time 226305415 ps
CPU time 1.15 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:54 PM PDT 24
Peak memory 204432 kb
Host smart-4ebec492-d497-4b8d-a041-270c533fdffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048480560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2048480560
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1936330312
Short name T1777
Test name
Test status
Simulation time 66230838 ps
CPU time 1.84 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:54 PM PDT 24
Peak memory 204560 kb
Host smart-4469283e-fb78-47c5-b6e8-f3759d4d8a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936330312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1936330312
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3332087091
Short name T1757
Test name
Test status
Simulation time 1390400606 ps
CPU time 2.22 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:55 PM PDT 24
Peak memory 204488 kb
Host smart-714bf9bb-6d3a-431d-ad69-58267fb35897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332087091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3332087091
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.663623902
Short name T211
Test name
Test status
Simulation time 42968797 ps
CPU time 1.19 seconds
Started Jul 15 05:25:50 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 212944 kb
Host smart-4fc1c4c1-d70d-406b-92ac-e99093e8fcc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663623902 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.663623902
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4268853725
Short name T1747
Test name
Test status
Simulation time 32231409 ps
CPU time 0.71 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:51 PM PDT 24
Peak memory 204444 kb
Host smart-370b29dc-60ce-4f4f-ac1b-3137b318fdd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268853725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4268853725
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2696321063
Short name T285
Test name
Test status
Simulation time 56327788 ps
CPU time 0.69 seconds
Started Jul 15 05:25:51 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 204280 kb
Host smart-dfdfa44b-9200-4ce9-8c94-8347d1771dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696321063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2696321063
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1974842242
Short name T1833
Test name
Test status
Simulation time 244169779 ps
CPU time 1.19 seconds
Started Jul 15 05:25:53 PM PDT 24
Finished Jul 15 05:25:55 PM PDT 24
Peak memory 204524 kb
Host smart-3088dcd1-8ec5-4168-8c9f-d563d46c4d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974842242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1974842242
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3639124053
Short name T1788
Test name
Test status
Simulation time 100346500 ps
CPU time 1.96 seconds
Started Jul 15 05:25:53 PM PDT 24
Finished Jul 15 05:25:56 PM PDT 24
Peak memory 204524 kb
Host smart-33476e59-a91a-4028-876f-b5358de2ee75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639124053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3639124053
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1485682339
Short name T207
Test name
Test status
Simulation time 338181204 ps
CPU time 1.55 seconds
Started Jul 15 05:25:49 PM PDT 24
Finished Jul 15 05:25:51 PM PDT 24
Peak memory 204600 kb
Host smart-d557c59b-d705-47bd-9b67-31db340fff25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485682339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1485682339
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1408040021
Short name T987
Test name
Test status
Simulation time 48496754 ps
CPU time 0.63 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:21 PM PDT 24
Peak memory 204780 kb
Host smart-f2f9429d-1513-42b0-bfc7-533b6dca2b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408040021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1408040021
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3360013855
Short name T1403
Test name
Test status
Simulation time 183483482 ps
CPU time 1.67 seconds
Started Jul 15 06:51:12 PM PDT 24
Finished Jul 15 06:51:14 PM PDT 24
Peak memory 213740 kb
Host smart-14cc0084-2327-4a03-818a-5af852cd2412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360013855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3360013855
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3055839492
Short name T561
Test name
Test status
Simulation time 348052161 ps
CPU time 8.16 seconds
Started Jul 15 06:51:15 PM PDT 24
Finished Jul 15 06:51:23 PM PDT 24
Peak memory 282248 kb
Host smart-b1d7c2b9-0ca7-4d8b-a463-82fc2f1f6a15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055839492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3055839492
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3456673514
Short name T1527
Test name
Test status
Simulation time 7250488464 ps
CPU time 209.11 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:54:42 PM PDT 24
Peak memory 621888 kb
Host smart-f167e8b2-2457-4a3a-b512-7f9f0931228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456673514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3456673514
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.544123329
Short name T830
Test name
Test status
Simulation time 4692871223 ps
CPU time 84.43 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:52:38 PM PDT 24
Peak memory 758420 kb
Host smart-74665f40-8715-4e0c-b82b-66d86180b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544123329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.544123329
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1196425561
Short name T1151
Test name
Test status
Simulation time 864484265 ps
CPU time 0.91 seconds
Started Jul 15 06:51:15 PM PDT 24
Finished Jul 15 06:51:16 PM PDT 24
Peak memory 205248 kb
Host smart-d699b965-cf3c-4727-b253-1c97f054eb38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196425561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1196425561
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2338127070
Short name T1641
Test name
Test status
Simulation time 483434491 ps
CPU time 7.44 seconds
Started Jul 15 06:51:12 PM PDT 24
Finished Jul 15 06:51:20 PM PDT 24
Peak memory 227392 kb
Host smart-eae15b7e-e092-4a7f-a73a-b7333331085f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338127070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2338127070
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2456800919
Short name T822
Test name
Test status
Simulation time 13322468481 ps
CPU time 94.39 seconds
Started Jul 15 06:51:16 PM PDT 24
Finished Jul 15 06:52:51 PM PDT 24
Peak memory 1007168 kb
Host smart-d12a78e4-ed75-4ee6-a37d-a2adc13b7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456800919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2456800919
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.122351563
Short name T1686
Test name
Test status
Simulation time 113170599 ps
CPU time 2.01 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:22 PM PDT 24
Peak memory 205524 kb
Host smart-50bc06d5-7304-4556-a718-2ea8876df5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122351563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.122351563
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.517548723
Short name T316
Test name
Test status
Simulation time 30476274 ps
CPU time 0.7 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:51:14 PM PDT 24
Peak memory 205248 kb
Host smart-f2c69b4f-48f3-46ed-b859-d93a68c4095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517548723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.517548723
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3434259326
Short name T1102
Test name
Test status
Simulation time 5629405324 ps
CPU time 119.11 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:53:13 PM PDT 24
Peak memory 486696 kb
Host smart-56b0f354-f35d-48bb-a374-37a6ffcd7336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434259326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3434259326
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.2276706616
Short name T1066
Test name
Test status
Simulation time 222202738 ps
CPU time 7.89 seconds
Started Jul 15 06:51:15 PM PDT 24
Finished Jul 15 06:51:23 PM PDT 24
Peak memory 229576 kb
Host smart-60cb7d79-ceea-464e-bf32-048a0f477f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276706616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2276706616
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.924505452
Short name T1181
Test name
Test status
Simulation time 8127415479 ps
CPU time 40.1 seconds
Started Jul 15 06:51:14 PM PDT 24
Finished Jul 15 06:51:55 PM PDT 24
Peak memory 463604 kb
Host smart-2bcbc7d3-03d3-4549-8a94-4ee0673bd44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924505452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.924505452
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2012973153
Short name T132
Test name
Test status
Simulation time 96777620911 ps
CPU time 879.35 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 2196332 kb
Host smart-bada38e6-70c3-4957-a36b-1f366910e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012973153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2012973153
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.39252150
Short name T1016
Test name
Test status
Simulation time 5026840118 ps
CPU time 12.07 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:32 PM PDT 24
Peak memory 219244 kb
Host smart-9403f114-a3e9-4786-98d5-9ca80ec19604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39252150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.39252150
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.4241321057
Short name T536
Test name
Test status
Simulation time 2110479397 ps
CPU time 5.7 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:25 PM PDT 24
Peak memory 219376 kb
Host smart-3683e87f-4cea-4e8e-9e2c-e2f2f10ce3c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241321057 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.4241321057
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2229876314
Short name T1276
Test name
Test status
Simulation time 184507278 ps
CPU time 0.87 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:19 PM PDT 24
Peak memory 205424 kb
Host smart-c33ff2ce-3111-4f3c-9211-9a5c593a8546
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229876314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2229876314
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1380187210
Short name T317
Test name
Test status
Simulation time 352064652 ps
CPU time 1.27 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:21 PM PDT 24
Peak memory 205428 kb
Host smart-9001810d-1ef7-4d6d-900f-ffad30b2a3d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380187210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1380187210
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1903080845
Short name T1669
Test name
Test status
Simulation time 495625730 ps
CPU time 2.93 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:23 PM PDT 24
Peak memory 205696 kb
Host smart-cbad8352-e8fd-4bae-ad13-12571c183b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903080845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1903080845
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.3852992149
Short name T1184
Test name
Test status
Simulation time 201449039 ps
CPU time 1.24 seconds
Started Jul 15 06:51:17 PM PDT 24
Finished Jul 15 06:51:19 PM PDT 24
Peak memory 205416 kb
Host smart-c74363f8-bd49-45a3-8adf-f12e3b2472cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852992149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.3852992149
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2351401193
Short name T707
Test name
Test status
Simulation time 704539058 ps
CPU time 3.76 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:51:17 PM PDT 24
Peak memory 213840 kb
Host smart-ef5a151e-ea49-49db-bdef-762c77a71400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351401193 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2351401193
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.933413346
Short name T443
Test name
Test status
Simulation time 19762663209 ps
CPU time 57.74 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:52:16 PM PDT 24
Peak memory 887636 kb
Host smart-46ac8447-9ec2-4370-818f-8131ed8c160b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933413346 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.933413346
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.984215849
Short name T961
Test name
Test status
Simulation time 923400322 ps
CPU time 2.83 seconds
Started Jul 15 06:51:16 PM PDT 24
Finished Jul 15 06:51:19 PM PDT 24
Peak memory 213812 kb
Host smart-b84fa557-c4d3-4f53-95b3-c6d2cac60af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984215849 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_nack_acqfull.984215849
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.2294250141
Short name T580
Test name
Test status
Simulation time 547701822 ps
CPU time 2.6 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:21 PM PDT 24
Peak memory 205984 kb
Host smart-34d81684-7b47-4217-acb7-be5e8c527a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294250141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2294250141
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.2421013145
Short name T499
Test name
Test status
Simulation time 138450829 ps
CPU time 1.38 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:21 PM PDT 24
Peak memory 222100 kb
Host smart-2ede72ee-42e3-465f-a098-0774d425d66d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421013145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.2421013145
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2879712701
Short name T1682
Test name
Test status
Simulation time 619797116 ps
CPU time 5.08 seconds
Started Jul 15 06:51:12 PM PDT 24
Finished Jul 15 06:51:18 PM PDT 24
Peak memory 219628 kb
Host smart-2c918678-e05e-4ef8-b991-70a1596a6149
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879712701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2879712701
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.3668161688
Short name T979
Test name
Test status
Simulation time 2039771618 ps
CPU time 2.37 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:23 PM PDT 24
Peak memory 205428 kb
Host smart-eb5ebf3c-f959-4c1e-9fc3-c8a871d98be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668161688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_smbus_maxlen.3668161688
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.841456429
Short name T893
Test name
Test status
Simulation time 1866260103 ps
CPU time 29.16 seconds
Started Jul 15 06:51:11 PM PDT 24
Finished Jul 15 06:51:40 PM PDT 24
Peak memory 213828 kb
Host smart-a7ad3552-d19f-4582-a3d9-d65ff1543c18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841456429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.841456429
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.1187110834
Short name T1327
Test name
Test status
Simulation time 48643288827 ps
CPU time 2150.55 seconds
Started Jul 15 06:51:22 PM PDT 24
Finished Jul 15 07:27:13 PM PDT 24
Peak memory 5851956 kb
Host smart-f0dec6fe-749c-41ab-8401-a0a99eab5af2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187110834 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.1187110834
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3073687083
Short name T1606
Test name
Test status
Simulation time 6397220271 ps
CPU time 72.13 seconds
Started Jul 15 06:51:13 PM PDT 24
Finished Jul 15 06:52:26 PM PDT 24
Peak memory 218708 kb
Host smart-968eaf6d-d22c-4263-8c89-f40a1a2efb15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073687083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3073687083
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2686951146
Short name T1519
Test name
Test status
Simulation time 35600558813 ps
CPU time 61.76 seconds
Started Jul 15 06:51:14 PM PDT 24
Finished Jul 15 06:52:16 PM PDT 24
Peak memory 1094204 kb
Host smart-065d1182-5444-4f12-9a04-69bac5f3d87d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686951146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2686951146
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3780614362
Short name T1440
Test name
Test status
Simulation time 4547744665 ps
CPU time 5.46 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:25 PM PDT 24
Peak memory 267848 kb
Host smart-4704dfb8-9fc1-4ec9-bb1d-5dc4c5d45911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780614362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3780614362
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3076017029
Short name T309
Test name
Test status
Simulation time 1435932036 ps
CPU time 6.72 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:51:26 PM PDT 24
Peak memory 213904 kb
Host smart-ab16bc3a-1d37-400a-a4d2-d20bc6db83a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076017029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3076017029
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.122593140
Short name T483
Test name
Test status
Simulation time 15416486 ps
CPU time 0.64 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:34 PM PDT 24
Peak memory 204772 kb
Host smart-6ad95a60-cb79-4b54-930d-673af1997d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122593140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.122593140
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.480278392
Short name T1434
Test name
Test status
Simulation time 407563879 ps
CPU time 9.07 seconds
Started Jul 15 06:51:25 PM PDT 24
Finished Jul 15 06:51:34 PM PDT 24
Peak memory 289720 kb
Host smart-87af9370-8252-4d1e-a4b4-10879cf1bfa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480278392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.480278392
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2934387841
Short name T162
Test name
Test status
Simulation time 16933126670 ps
CPU time 54.81 seconds
Started Jul 15 06:51:26 PM PDT 24
Finished Jul 15 06:52:21 PM PDT 24
Peak memory 371972 kb
Host smart-ba7e9142-b84e-4351-933e-5614e99e44c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934387841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2934387841
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.496463853
Short name T1118
Test name
Test status
Simulation time 2382440375 ps
CPU time 104.28 seconds
Started Jul 15 06:51:18 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 574312 kb
Host smart-3f81a1c3-8d55-4bbd-98bd-88f52706f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496463853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.496463853
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3805557219
Short name T249
Test name
Test status
Simulation time 505725234 ps
CPU time 3.41 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:35 PM PDT 24
Peak memory 205416 kb
Host smart-b3d0f5ec-5c58-4543-8ae3-6a0d72c446be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805557219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3805557219
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2101013668
Short name T982
Test name
Test status
Simulation time 10912164325 ps
CPU time 172.23 seconds
Started Jul 15 06:51:21 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 1538576 kb
Host smart-40cafd79-cbc6-4b86-b352-c91e0e39d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101013668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2101013668
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1555210522
Short name T657
Test name
Test status
Simulation time 1634893370 ps
CPU time 6.66 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:39 PM PDT 24
Peak memory 205500 kb
Host smart-e4f1468b-46ee-41bb-ba3d-2fceca8ffbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555210522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1555210522
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.4116139936
Short name T1126
Test name
Test status
Simulation time 96945299 ps
CPU time 0.69 seconds
Started Jul 15 06:51:19 PM PDT 24
Finished Jul 15 06:51:20 PM PDT 24
Peak memory 205228 kb
Host smart-5c64de87-31de-4635-9c49-9a56e91c1012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116139936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.4116139936
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.269809984
Short name T19
Test name
Test status
Simulation time 30161643705 ps
CPU time 406.42 seconds
Started Jul 15 06:51:26 PM PDT 24
Finished Jul 15 06:58:12 PM PDT 24
Peak memory 205480 kb
Host smart-36db8230-7a3f-4a6e-8915-edf13c6f3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269809984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.269809984
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.3377579512
Short name T246
Test name
Test status
Simulation time 23173762779 ps
CPU time 117.35 seconds
Started Jul 15 06:51:24 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 213736 kb
Host smart-0f2009f9-06e7-49e0-a805-537e16645c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377579512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3377579512
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.16270589
Short name T682
Test name
Test status
Simulation time 1596557633 ps
CPU time 25.66 seconds
Started Jul 15 06:51:22 PM PDT 24
Finished Jul 15 06:51:48 PM PDT 24
Peak memory 387580 kb
Host smart-853a96c7-25bf-43a1-b521-eb9203d1aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16270589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.16270589
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3959100310
Short name T1277
Test name
Test status
Simulation time 2673636733 ps
CPU time 11.89 seconds
Started Jul 15 06:51:26 PM PDT 24
Finished Jul 15 06:51:39 PM PDT 24
Peak memory 214808 kb
Host smart-6740b588-8995-44bd-a1db-2a36b16dc962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959100310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3959100310
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1404454138
Short name T193
Test name
Test status
Simulation time 164025940 ps
CPU time 0.84 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:33 PM PDT 24
Peak memory 223832 kb
Host smart-8eba4d12-2592-4ec2-899f-f00221d9e727
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404454138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1404454138
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1403378507
Short name T889
Test name
Test status
Simulation time 1847164183 ps
CPU time 5.08 seconds
Started Jul 15 06:51:34 PM PDT 24
Finished Jul 15 06:51:39 PM PDT 24
Peak memory 222076 kb
Host smart-256fbe5b-f747-42bc-b1f0-fe945f0fa174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403378507 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1403378507
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3031193452
Short name T1104
Test name
Test status
Simulation time 178735541 ps
CPU time 1.12 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:34 PM PDT 24
Peak memory 205456 kb
Host smart-bdbd3617-714f-42d5-bd45-cac0a02ec883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031193452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3031193452
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2498611294
Short name T674
Test name
Test status
Simulation time 157253855 ps
CPU time 1.05 seconds
Started Jul 15 06:51:27 PM PDT 24
Finished Jul 15 06:51:29 PM PDT 24
Peak memory 205492 kb
Host smart-101e694d-e8ee-4095-8d43-af7da3cc5c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498611294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2498611294
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.4139411377
Short name T311
Test name
Test status
Simulation time 971597042 ps
CPU time 2.78 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:35 PM PDT 24
Peak memory 205628 kb
Host smart-1660e4db-bfd1-4c39-8f02-46d2c2abdcf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139411377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.4139411377
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.3711008727
Short name T957
Test name
Test status
Simulation time 662684574 ps
CPU time 1.58 seconds
Started Jul 15 06:51:34 PM PDT 24
Finished Jul 15 06:51:36 PM PDT 24
Peak memory 205616 kb
Host smart-f9133977-5266-4ca3-b0b2-fc91a2bff4ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711008727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.3711008727
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.786603748
Short name T58
Test name
Test status
Simulation time 9519725258 ps
CPU time 12.12 seconds
Started Jul 15 06:51:24 PM PDT 24
Finished Jul 15 06:51:36 PM PDT 24
Peak memory 214180 kb
Host smart-5b037c2b-6a6a-4796-a2a7-365a34433fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786603748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.786603748
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3219256673
Short name T1278
Test name
Test status
Simulation time 966694925 ps
CPU time 6.18 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:38 PM PDT 24
Peak memory 222044 kb
Host smart-64d3670a-079c-42ca-a47a-5ff2ddaa3f42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219256673 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3219256673
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2905663035
Short name T691
Test name
Test status
Simulation time 9723344562 ps
CPU time 15.6 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:47 PM PDT 24
Peak memory 582844 kb
Host smart-b5f6b22a-8d79-4f61-930f-7831b0b74ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905663035 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2905663035
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.1526385390
Short name T1549
Test name
Test status
Simulation time 373612653 ps
CPU time 2.23 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:35 PM PDT 24
Peak memory 205656 kb
Host smart-22ec5d39-ae41-48e3-a003-78aaabbb3420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526385390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1526385390
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_txstretch.357024315
Short name T894
Test name
Test status
Simulation time 186355624 ps
CPU time 1.56 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:33 PM PDT 24
Peak memory 222080 kb
Host smart-7e6776c6-f9bc-4ab1-b076-a9b525c0845c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357024315 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_nack_txstretch.357024315
Directory /workspace/1.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/1.i2c_target_perf.4010408840
Short name T1169
Test name
Test status
Simulation time 804050206 ps
CPU time 5.22 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:38 PM PDT 24
Peak memory 217684 kb
Host smart-6ba11da1-c5f7-4d17-9f5b-a61dbabfe4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010408840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.4010408840
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.882765814
Short name T352
Test name
Test status
Simulation time 541853712 ps
CPU time 2.49 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:35 PM PDT 24
Peak memory 205432 kb
Host smart-617109de-8e9d-4c74-a7c3-1c407b158635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882765814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_smbus_maxlen.882765814
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2857714597
Short name T337
Test name
Test status
Simulation time 3394678670 ps
CPU time 26.86 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:58 PM PDT 24
Peak memory 213844 kb
Host smart-7a512d83-7ef4-4ae5-a74c-2eb0ab667d78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857714597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2857714597
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1561555718
Short name T1001
Test name
Test status
Simulation time 647529171 ps
CPU time 12.49 seconds
Started Jul 15 06:51:24 PM PDT 24
Finished Jul 15 06:51:37 PM PDT 24
Peak memory 218056 kb
Host smart-ab30ea95-ecad-4c97-a0a6-9c58fd21d93c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561555718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1561555718
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3904033228
Short name T1594
Test name
Test status
Simulation time 78158441974 ps
CPU time 200.37 seconds
Started Jul 15 06:51:25 PM PDT 24
Finished Jul 15 06:54:46 PM PDT 24
Peak memory 1709540 kb
Host smart-2efbfea5-0d09-42ef-bd21-fdb1bdd38760
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904033228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3904033228
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3955758626
Short name T1529
Test name
Test status
Simulation time 2014096057 ps
CPU time 24.67 seconds
Started Jul 15 06:51:25 PM PDT 24
Finished Jul 15 06:51:51 PM PDT 24
Peak memory 423568 kb
Host smart-9644ab8c-cb85-431f-84e4-bc9c608ecfb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955758626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3955758626
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1191761064
Short name T795
Test name
Test status
Simulation time 1351705030 ps
CPU time 7.52 seconds
Started Jul 15 06:51:25 PM PDT 24
Finished Jul 15 06:51:33 PM PDT 24
Peak memory 230088 kb
Host smart-c446332c-1b9a-4cbb-b5b9-eb7ac29af158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191761064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1191761064
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2233591289
Short name T1453
Test name
Test status
Simulation time 50717723 ps
CPU time 0.62 seconds
Started Jul 15 06:53:18 PM PDT 24
Finished Jul 15 06:53:19 PM PDT 24
Peak memory 204828 kb
Host smart-8dc4a62d-24b3-448a-a985-1c13aeb26f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233591289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2233591289
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3068915634
Short name T1362
Test name
Test status
Simulation time 441614446 ps
CPU time 4.13 seconds
Started Jul 15 06:53:12 PM PDT 24
Finished Jul 15 06:53:17 PM PDT 24
Peak memory 235556 kb
Host smart-3099de11-cb21-4dff-8ece-b9348aad741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068915634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3068915634
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2595849396
Short name T686
Test name
Test status
Simulation time 1067566310 ps
CPU time 13.19 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 06:53:29 PM PDT 24
Peak memory 252932 kb
Host smart-006489cc-18ba-4225-85f4-e4d699545e73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595849396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2595849396
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3021827726
Short name T1616
Test name
Test status
Simulation time 16460629983 ps
CPU time 236.89 seconds
Started Jul 15 06:53:20 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 640032 kb
Host smart-256af551-a0c1-440b-af7b-a463f208d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021827726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3021827726
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.77884029
Short name T1307
Test name
Test status
Simulation time 6944919218 ps
CPU time 31.73 seconds
Started Jul 15 06:53:13 PM PDT 24
Finished Jul 15 06:53:45 PM PDT 24
Peak memory 411608 kb
Host smart-101de77f-1d9e-4d31-a7b2-c5ef122c459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77884029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.77884029
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1834568214
Short name T1306
Test name
Test status
Simulation time 192134132 ps
CPU time 1.12 seconds
Started Jul 15 06:53:13 PM PDT 24
Finished Jul 15 06:53:15 PM PDT 24
Peak memory 205392 kb
Host smart-e7a6d895-b5af-425f-933e-fa93fe702f5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834568214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1834568214
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1141758754
Short name T864
Test name
Test status
Simulation time 278679985 ps
CPU time 8.24 seconds
Started Jul 15 06:53:16 PM PDT 24
Finished Jul 15 06:53:25 PM PDT 24
Peak memory 229776 kb
Host smart-25d3a9a1-9570-49c6-a2a9-812775a25457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141758754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1141758754
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_override.3502807859
Short name T1232
Test name
Test status
Simulation time 17515596 ps
CPU time 0.67 seconds
Started Jul 15 06:53:09 PM PDT 24
Finished Jul 15 06:53:10 PM PDT 24
Peak memory 205108 kb
Host smart-aa63bc16-4d9a-407b-9983-096f7399ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502807859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3502807859
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1116196318
Short name T45
Test name
Test status
Simulation time 1346697932 ps
CPU time 5.94 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 244916 kb
Host smart-6ed822bb-b5a0-4d4a-8622-0494f85353ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116196318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1116196318
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.3831486043
Short name T794
Test name
Test status
Simulation time 5908966552 ps
CPU time 62.71 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 06:54:19 PM PDT 24
Peak memory 205440 kb
Host smart-883de939-8091-4efd-875f-8987f7d9f0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831486043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3831486043
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2890030129
Short name T1037
Test name
Test status
Simulation time 2376087906 ps
CPU time 57.2 seconds
Started Jul 15 06:53:10 PM PDT 24
Finished Jul 15 06:54:08 PM PDT 24
Peak memory 292992 kb
Host smart-43c704d6-5142-44c7-862e-5a11351a8a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890030129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2890030129
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1640588155
Short name T509
Test name
Test status
Simulation time 821375651 ps
CPU time 36.52 seconds
Started Jul 15 06:53:14 PM PDT 24
Finished Jul 15 06:53:51 PM PDT 24
Peak memory 213708 kb
Host smart-e97d0e97-5191-470e-9ce2-0895962674f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640588155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1640588155
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.333091692
Short name T456
Test name
Test status
Simulation time 1233512830 ps
CPU time 5.66 seconds
Started Jul 15 06:53:14 PM PDT 24
Finished Jul 15 06:53:21 PM PDT 24
Peak memory 214872 kb
Host smart-86384a97-313b-48fd-8787-9488a7e6d5a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333091692 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.333091692
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.425043400
Short name T1059
Test name
Test status
Simulation time 700435541 ps
CPU time 1.41 seconds
Started Jul 15 06:53:12 PM PDT 24
Finished Jul 15 06:53:14 PM PDT 24
Peak memory 213996 kb
Host smart-f253afef-60e8-4a6d-9dc3-f5c709bc7918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425043400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.425043400
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2512525573
Short name T549
Test name
Test status
Simulation time 1086984478 ps
CPU time 1.3 seconds
Started Jul 15 06:53:14 PM PDT 24
Finished Jul 15 06:53:16 PM PDT 24
Peak memory 205360 kb
Host smart-a733bd64-1af2-4792-b90c-91e7f04623f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512525573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2512525573
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3080668691
Short name T1564
Test name
Test status
Simulation time 2162718996 ps
CPU time 2.66 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:53:28 PM PDT 24
Peak memory 205692 kb
Host smart-4d2e5066-77d7-4f74-8490-33e046a1553f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080668691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3080668691
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2911247485
Short name T539
Test name
Test status
Simulation time 630537232 ps
CPU time 1.16 seconds
Started Jul 15 06:53:18 PM PDT 24
Finished Jul 15 06:53:20 PM PDT 24
Peak memory 205520 kb
Host smart-ddb57b67-8524-4a2e-800a-6ae624730d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911247485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2911247485
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1809088681
Short name T1558
Test name
Test status
Simulation time 1406131542 ps
CPU time 4.86 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 06:53:21 PM PDT 24
Peak memory 214036 kb
Host smart-e15a5b3a-ac26-46d2-b9f2-129c65a813fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809088681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1809088681
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.360744883
Short name T996
Test name
Test status
Simulation time 36578478853 ps
CPU time 88.24 seconds
Started Jul 15 06:53:20 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 1592976 kb
Host smart-bf6f6f5b-86a8-430a-8fe5-b3e25ff34f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360744883 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.360744883
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.2898773240
Short name T629
Test name
Test status
Simulation time 1751455950 ps
CPU time 2.69 seconds
Started Jul 15 06:53:19 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 213864 kb
Host smart-57e36a95-ee6c-4717-914d-08640f2ea012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898773240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.2898773240
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.3105754107
Short name T1298
Test name
Test status
Simulation time 747678297 ps
CPU time 2.61 seconds
Started Jul 15 06:53:19 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 205628 kb
Host smart-d128e3e3-e6a4-45b1-a21c-0d0a5690d236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105754107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.3105754107
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.935988201
Short name T696
Test name
Test status
Simulation time 144463836 ps
CPU time 1.4 seconds
Started Jul 15 06:53:18 PM PDT 24
Finished Jul 15 06:53:20 PM PDT 24
Peak memory 222184 kb
Host smart-e152cdef-c2a7-41cc-a457-18c2e16b9aef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935988201 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_nack_txstretch.935988201
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.3334154605
Short name T1513
Test name
Test status
Simulation time 1888469034 ps
CPU time 7.09 seconds
Started Jul 15 06:53:16 PM PDT 24
Finished Jul 15 06:53:23 PM PDT 24
Peak memory 230208 kb
Host smart-881ba626-aaa5-4f17-b628-5147316d59e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334154605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.3334154605
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.3444109073
Short name T515
Test name
Test status
Simulation time 656310193 ps
CPU time 2.29 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 06:53:18 PM PDT 24
Peak memory 205416 kb
Host smart-11a28fa5-906e-41de-9d3a-a8c5f2ac8763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444109073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.3444109073
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3483622256
Short name T1450
Test name
Test status
Simulation time 7164356148 ps
CPU time 11.08 seconds
Started Jul 15 06:53:20 PM PDT 24
Finished Jul 15 06:53:31 PM PDT 24
Peak memory 216504 kb
Host smart-e3f26331-de88-4080-bf30-50a87cd6dbd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483622256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3483622256
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.1417406181
Short name T873
Test name
Test status
Simulation time 36179420034 ps
CPU time 25.9 seconds
Started Jul 15 06:53:13 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 263236 kb
Host smart-9b207422-4a68-41c7-b4d6-34a06b4020ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417406181 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.1417406181
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3576199022
Short name T1366
Test name
Test status
Simulation time 1813399301 ps
CPU time 76.28 seconds
Started Jul 15 06:53:14 PM PDT 24
Finished Jul 15 06:54:31 PM PDT 24
Peak memory 221976 kb
Host smart-5a8662b5-e436-4580-ae3f-be2913c29c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576199022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3576199022
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3745856659
Short name T413
Test name
Test status
Simulation time 60647859237 ps
CPU time 2583.95 seconds
Started Jul 15 06:53:15 PM PDT 24
Finished Jul 15 07:36:20 PM PDT 24
Peak memory 9991664 kb
Host smart-1c4e1ef6-47d4-40d3-9a45-e54ab9065044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745856659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3745856659
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.121504708
Short name T1583
Test name
Test status
Simulation time 1315697277 ps
CPU time 5.47 seconds
Started Jul 15 06:53:12 PM PDT 24
Finished Jul 15 06:53:18 PM PDT 24
Peak memory 253768 kb
Host smart-1aece083-05f0-408a-8ccd-db303291d2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121504708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.121504708
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3664330944
Short name T613
Test name
Test status
Simulation time 1546673785 ps
CPU time 7.61 seconds
Started Jul 15 06:53:14 PM PDT 24
Finished Jul 15 06:53:23 PM PDT 24
Peak memory 213836 kb
Host smart-50644e15-54f9-4bc8-83c1-8031876553e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664330944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3664330944
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2527906618
Short name T331
Test name
Test status
Simulation time 274230863 ps
CPU time 4.51 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:53:30 PM PDT 24
Peak memory 205956 kb
Host smart-7248b63d-3c95-4df7-99c1-8e73efde2d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527906618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2527906618
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.760188541
Short name T1280
Test name
Test status
Simulation time 28849946 ps
CPU time 0.63 seconds
Started Jul 15 06:53:27 PM PDT 24
Finished Jul 15 06:53:28 PM PDT 24
Peak memory 204764 kb
Host smart-9a566939-8444-4005-9028-ddefb40fb7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760188541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.760188541
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3630074296
Short name T36
Test name
Test status
Simulation time 425250736 ps
CPU time 6.66 seconds
Started Jul 15 06:53:27 PM PDT 24
Finished Jul 15 06:53:34 PM PDT 24
Peak memory 232860 kb
Host smart-bed63f17-f88c-43a1-b687-7edd56a90078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630074296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3630074296
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1106888039
Short name T718
Test name
Test status
Simulation time 371175361 ps
CPU time 7.69 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 280164 kb
Host smart-25ec725e-7b21-4387-88f5-b1c453b668f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106888039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1106888039
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2559775659
Short name T1299
Test name
Test status
Simulation time 2670446319 ps
CPU time 148.27 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:55:53 PM PDT 24
Peak memory 388100 kb
Host smart-1bb82d42-17b8-471c-8201-486ae54c26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559775659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2559775659
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1990161887
Short name T187
Test name
Test status
Simulation time 2763105776 ps
CPU time 87.64 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:54:53 PM PDT 24
Peak memory 441416 kb
Host smart-5938edab-6dbc-472e-81d5-a504481ee70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990161887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1990161887
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1419545659
Short name T670
Test name
Test status
Simulation time 326995024 ps
CPU time 0.92 seconds
Started Jul 15 06:53:26 PM PDT 24
Finished Jul 15 06:53:28 PM PDT 24
Peak memory 205244 kb
Host smart-80c03516-929a-4d01-b058-65deab6ec1dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419545659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1419545659
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1140421330
Short name T1575
Test name
Test status
Simulation time 130925175 ps
CPU time 3.13 seconds
Started Jul 15 06:53:23 PM PDT 24
Finished Jul 15 06:53:26 PM PDT 24
Peak memory 205492 kb
Host smart-2ad212c6-2b69-4bb7-a10e-cabe3258203a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140421330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1140421330
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.166717520
Short name T120
Test name
Test status
Simulation time 15667493878 ps
CPU time 96.38 seconds
Started Jul 15 06:53:23 PM PDT 24
Finished Jul 15 06:55:00 PM PDT 24
Peak memory 1071848 kb
Host smart-96ab9e3a-dd6e-404e-959c-6af171e6858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166717520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.166717520
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3085179895
Short name T266
Test name
Test status
Simulation time 1681897914 ps
CPU time 17.1 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:53:47 PM PDT 24
Peak memory 205468 kb
Host smart-0aed17d5-aa22-4d29-9640-5a4f203ba53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085179895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3085179895
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.117093805
Short name T737
Test name
Test status
Simulation time 348289087 ps
CPU time 1.53 seconds
Started Jul 15 06:53:33 PM PDT 24
Finished Jul 15 06:53:35 PM PDT 24
Peak memory 205556 kb
Host smart-8ee99424-5cf6-4017-aef2-a45508e1da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117093805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.117093805
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.293302073
Short name T1454
Test name
Test status
Simulation time 109980073 ps
CPU time 0.65 seconds
Started Jul 15 06:53:18 PM PDT 24
Finished Jul 15 06:53:19 PM PDT 24
Peak memory 205236 kb
Host smart-08a6ff77-5c1c-40f3-872c-35b6d843fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293302073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.293302073
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1235657942
Short name T1612
Test name
Test status
Simulation time 7311414979 ps
CPU time 80.3 seconds
Started Jul 15 06:53:29 PM PDT 24
Finished Jul 15 06:54:49 PM PDT 24
Peak memory 785616 kb
Host smart-5d2d2fa6-a096-4396-9e61-794ef0509a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235657942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1235657942
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.607723912
Short name T201
Test name
Test status
Simulation time 508879206 ps
CPU time 9.96 seconds
Started Jul 15 06:53:24 PM PDT 24
Finished Jul 15 06:53:35 PM PDT 24
Peak memory 205440 kb
Host smart-f521ed80-041f-40cd-bf9a-941819ddc80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607723912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.607723912
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2011263139
Short name T1733
Test name
Test status
Simulation time 5949310078 ps
CPU time 71.25 seconds
Started Jul 15 06:53:19 PM PDT 24
Finished Jul 15 06:54:31 PM PDT 24
Peak memory 336380 kb
Host smart-8dc3dcce-4888-4e05-9d87-61105a85c421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011263139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2011263139
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1654869500
Short name T1630
Test name
Test status
Simulation time 2896282720 ps
CPU time 13.76 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:53:40 PM PDT 24
Peak memory 217976 kb
Host smart-d5de8273-12b7-4bcc-8d05-fd1e00097b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654869500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1654869500
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.317894118
Short name T333
Test name
Test status
Simulation time 960702226 ps
CPU time 1.67 seconds
Started Jul 15 06:53:26 PM PDT 24
Finished Jul 15 06:53:28 PM PDT 24
Peak memory 213828 kb
Host smart-5cb5f101-681f-4c68-941f-4bb6b175580e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317894118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.317894118
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.788735793
Short name T1094
Test name
Test status
Simulation time 361257323 ps
CPU time 1 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:53:31 PM PDT 24
Peak memory 205452 kb
Host smart-54c277e0-dc47-44b7-9f06-64af99b2a8bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788735793 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.788735793
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.3006315925
Short name T305
Test name
Test status
Simulation time 869980914 ps
CPU time 2.71 seconds
Started Jul 15 06:53:33 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 205668 kb
Host smart-4b867ba5-e8ce-4bc2-942e-26a8014af83c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006315925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.3006315925
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.758106467
Short name T1343
Test name
Test status
Simulation time 884223759 ps
CPU time 1.41 seconds
Started Jul 15 06:53:34 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 205464 kb
Host smart-fff7f12e-0ad3-4772-9493-782c5599d940
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758106467 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.758106467
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2795252404
Short name T1706
Test name
Test status
Simulation time 3642179946 ps
CPU time 2.79 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:53:35 PM PDT 24
Peak memory 214008 kb
Host smart-c592cf21-1bb5-472b-ab93-bbe278f93a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795252404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2795252404
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.385492085
Short name T1056
Test name
Test status
Simulation time 4981489353 ps
CPU time 8.13 seconds
Started Jul 15 06:53:27 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 222032 kb
Host smart-71418481-2b07-4eb9-be95-2b77c3a1e59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385492085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.385492085
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2569477015
Short name T1445
Test name
Test status
Simulation time 9498414432 ps
CPU time 6.78 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:53:32 PM PDT 24
Peak memory 205760 kb
Host smart-01e16d4f-56cb-4001-846f-27b0b5a1f4de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569477015 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2569477015
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.2430268850
Short name T579
Test name
Test status
Simulation time 4670203702 ps
CPU time 2.81 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:53:34 PM PDT 24
Peak memory 213920 kb
Host smart-1b40cf3a-16a0-4dad-8124-6fc316c521b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430268850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.2430268850
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.1321853355
Short name T1086
Test name
Test status
Simulation time 929266461 ps
CPU time 2.53 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:53:33 PM PDT 24
Peak memory 205640 kb
Host smart-b124311c-c3ac-4ffe-b54c-be9b5757f090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321853355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.1321853355
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.2876792095
Short name T1198
Test name
Test status
Simulation time 141965037 ps
CPU time 1.4 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:53:33 PM PDT 24
Peak memory 222424 kb
Host smart-890fae97-9362-4eed-b197-5b16ab990ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876792095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.2876792095
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_perf.2739117119
Short name T1283
Test name
Test status
Simulation time 7159722141 ps
CPU time 6.15 seconds
Started Jul 15 06:53:29 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 214028 kb
Host smart-f0c34c12-c5d2-4c7c-b409-be37a9bebdff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739117119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.2739117119
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.985235822
Short name T955
Test name
Test status
Simulation time 1488371410 ps
CPU time 2 seconds
Started Jul 15 06:53:33 PM PDT 24
Finished Jul 15 06:53:35 PM PDT 24
Peak memory 205372 kb
Host smart-7fb47248-8089-4855-ab2b-defc0fe54052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985235822 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_smbus_maxlen.985235822
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.340134937
Short name T78
Test name
Test status
Simulation time 1247714122 ps
CPU time 25.59 seconds
Started Jul 15 06:53:23 PM PDT 24
Finished Jul 15 06:53:48 PM PDT 24
Peak memory 213816 kb
Host smart-3ff9a8eb-c2b5-4f59-a3af-af8c48a1016b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340134937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.340134937
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.1422339947
Short name T1714
Test name
Test status
Simulation time 40297490201 ps
CPU time 44.5 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 335944 kb
Host smart-fe98176a-c150-4cb3-b97b-06eeeb2bcad9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422339947 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.1422339947
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1505185875
Short name T1496
Test name
Test status
Simulation time 583206337 ps
CPU time 26.15 seconds
Started Jul 15 06:53:26 PM PDT 24
Finished Jul 15 06:53:53 PM PDT 24
Peak memory 213840 kb
Host smart-07ca4207-8987-4345-9e29-82708f9e40d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505185875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1505185875
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1432952559
Short name T457
Test name
Test status
Simulation time 7980251377 ps
CPU time 15.48 seconds
Started Jul 15 06:53:24 PM PDT 24
Finished Jul 15 06:53:40 PM PDT 24
Peak memory 205620 kb
Host smart-11674c39-bbc4-4b4e-809e-bf57d22a897a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432952559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1432952559
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1167559055
Short name T1463
Test name
Test status
Simulation time 1605007489 ps
CPU time 1.61 seconds
Started Jul 15 06:53:24 PM PDT 24
Finished Jul 15 06:53:26 PM PDT 24
Peak memory 213792 kb
Host smart-6fc9f976-b557-44e5-8240-13a74ded085c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167559055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1167559055
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2729980509
Short name T1021
Test name
Test status
Simulation time 7342139640 ps
CPU time 6.66 seconds
Started Jul 15 06:53:25 PM PDT 24
Finished Jul 15 06:53:33 PM PDT 24
Peak memory 213888 kb
Host smart-01e8d526-16f4-4abd-81bb-5fcc06364e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729980509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2729980509
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3682178729
Short name T1351
Test name
Test status
Simulation time 96382001 ps
CPU time 2.06 seconds
Started Jul 15 06:53:29 PM PDT 24
Finished Jul 15 06:53:31 PM PDT 24
Peak memory 205572 kb
Host smart-55282f9b-bb43-411b-855c-9c3ce258c8ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682178729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3682178729
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.4195771593
Short name T1645
Test name
Test status
Simulation time 41191424 ps
CPU time 0.66 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:53:45 PM PDT 24
Peak memory 204820 kb
Host smart-bdd605d7-b3f2-495b-90a6-0a1497ffc509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195771593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.4195771593
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2130484640
Short name T840
Test name
Test status
Simulation time 153105327 ps
CPU time 1.28 seconds
Started Jul 15 06:53:35 PM PDT 24
Finished Jul 15 06:53:37 PM PDT 24
Peak memory 213788 kb
Host smart-6d4415f9-a9a8-45cf-b08b-f4ff6051c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130484640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2130484640
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2403530831
Short name T1422
Test name
Test status
Simulation time 938418248 ps
CPU time 4.43 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 248488 kb
Host smart-35a473f2-3269-4361-960c-03a883c00c3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403530831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2403530831
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2309955315
Short name T1353
Test name
Test status
Simulation time 10845456599 ps
CPU time 177.27 seconds
Started Jul 15 06:53:35 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 565044 kb
Host smart-ed003484-9a75-4766-922f-c93a580c3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309955315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2309955315
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2165874126
Short name T1320
Test name
Test status
Simulation time 2628694282 ps
CPU time 95.66 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:55:06 PM PDT 24
Peak memory 840336 kb
Host smart-eaded617-ee07-466c-a1b7-8c685d18b457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165874126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2165874126
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2719407241
Short name T932
Test name
Test status
Simulation time 207828962 ps
CPU time 1.1 seconds
Started Jul 15 06:53:32 PM PDT 24
Finished Jul 15 06:53:33 PM PDT 24
Peak memory 205252 kb
Host smart-eedf1f55-3158-438f-ad7e-52b5eed1b308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719407241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2719407241
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3784482248
Short name T1220
Test name
Test status
Simulation time 382313125 ps
CPU time 10.66 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:47 PM PDT 24
Peak memory 240240 kb
Host smart-5eebd457-c3ee-43e2-986f-77e711231916
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784482248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3784482248
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2622284100
Short name T1621
Test name
Test status
Simulation time 14928777341 ps
CPU time 99.07 seconds
Started Jul 15 06:53:31 PM PDT 24
Finished Jul 15 06:55:11 PM PDT 24
Peak memory 999568 kb
Host smart-78dea4f2-4104-4f5f-9ab8-3ec671e8a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622284100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2622284100
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3120328659
Short name T990
Test name
Test status
Simulation time 1562510622 ps
CPU time 6.52 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:43 PM PDT 24
Peak memory 205488 kb
Host smart-b691568e-8e7e-43e1-a560-ba1a1e4f780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120328659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3120328659
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.2711412568
Short name T1295
Test name
Test status
Simulation time 44696009 ps
CPU time 0.7 seconds
Started Jul 15 06:53:32 PM PDT 24
Finished Jul 15 06:53:33 PM PDT 24
Peak memory 205208 kb
Host smart-387787fc-3136-4491-8003-d9eaa88200fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711412568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2711412568
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.306335270
Short name T842
Test name
Test status
Simulation time 55600449624 ps
CPU time 537.61 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 1045504 kb
Host smart-8c5479da-8d4f-408e-9582-44a17ffbce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306335270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.306335270
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.66853232
Short name T364
Test name
Test status
Simulation time 335661463 ps
CPU time 3.14 seconds
Started Jul 15 06:53:35 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 223064 kb
Host smart-1a074dec-2eb5-45fe-ab5d-1249d155ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66853232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.66853232
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2943295179
Short name T1294
Test name
Test status
Simulation time 18153487238 ps
CPU time 100.27 seconds
Started Jul 15 06:53:30 PM PDT 24
Finished Jul 15 06:55:11 PM PDT 24
Peak memory 357444 kb
Host smart-7e177c20-8434-4e04-82c8-d8617b6de674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943295179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2943295179
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.1887306279
Short name T32
Test name
Test status
Simulation time 14455672078 ps
CPU time 106.19 seconds
Started Jul 15 06:53:41 PM PDT 24
Finished Jul 15 06:55:27 PM PDT 24
Peak memory 686264 kb
Host smart-99184138-d743-43c6-8fbc-7fd9f6241e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887306279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1887306279
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1413136772
Short name T811
Test name
Test status
Simulation time 699063694 ps
CPU time 31.75 seconds
Started Jul 15 06:53:35 PM PDT 24
Finished Jul 15 06:54:07 PM PDT 24
Peak memory 213672 kb
Host smart-55e32de4-9077-4ece-b068-569701d30f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413136772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1413136772
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3398425286
Short name T1235
Test name
Test status
Simulation time 3715809775 ps
CPU time 5.91 seconds
Started Jul 15 06:53:38 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 213960 kb
Host smart-a0e7dbc7-d736-4e9f-b79e-bf078d0a9cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398425286 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3398425286
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1368357165
Short name T833
Test name
Test status
Simulation time 143990390 ps
CPU time 0.95 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:38 PM PDT 24
Peak memory 205452 kb
Host smart-c2e92a7e-59a3-472a-aaea-5517526df016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368357165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1368357165
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1175917859
Short name T398
Test name
Test status
Simulation time 175019187 ps
CPU time 1.09 seconds
Started Jul 15 06:53:37 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 213668 kb
Host smart-88d5035d-1143-41e2-9fbb-afeb9ec312a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175917859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1175917859
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.4035093412
Short name T1678
Test name
Test status
Simulation time 2009653616 ps
CPU time 3.02 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 205608 kb
Host smart-3d0d3482-03af-47a1-81bb-d826d4e4ed14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035093412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.4035093412
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3809029675
Short name T704
Test name
Test status
Simulation time 1937874438 ps
CPU time 6.46 seconds
Started Jul 15 06:53:37 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 222048 kb
Host smart-acf6c51b-ed53-4702-a60d-c087ada81447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809029675 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3809029675
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3993474889
Short name T3
Test name
Test status
Simulation time 22379997015 ps
CPU time 538.52 seconds
Started Jul 15 06:53:38 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 3957892 kb
Host smart-3cea2712-f7e5-4729-99b0-433ed3d949ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993474889 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3993474889
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.4137061698
Short name T1285
Test name
Test status
Simulation time 532337518 ps
CPU time 2.82 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:53:47 PM PDT 24
Peak memory 213816 kb
Host smart-713700d6-2c2d-4b05-abb4-5abbf94df4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137061698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.4137061698
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.2162456265
Short name T1354
Test name
Test status
Simulation time 1886655058 ps
CPU time 2.59 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:53:47 PM PDT 24
Peak memory 205560 kb
Host smart-c035d180-be6e-43e1-aaf0-12c3595adbc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162456265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.2162456265
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3782573969
Short name T1411
Test name
Test status
Simulation time 1910242040 ps
CPU time 3.36 seconds
Started Jul 15 06:53:39 PM PDT 24
Finished Jul 15 06:53:43 PM PDT 24
Peak memory 217336 kb
Host smart-6066139b-f8de-4fb7-838b-0b45d9f081a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782573969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3782573969
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.3503494415
Short name T1203
Test name
Test status
Simulation time 2555003132 ps
CPU time 2.09 seconds
Started Jul 15 06:53:41 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 205432 kb
Host smart-86acad15-3c1a-4d2b-b2e9-1e0856880e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503494415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.3503494415
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.4134992352
Short name T776
Test name
Test status
Simulation time 1541310884 ps
CPU time 12.58 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:49 PM PDT 24
Peak memory 213792 kb
Host smart-01534ec8-47ff-485f-82e9-ff4f297d7115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134992352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.4134992352
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2163200047
Short name T452
Test name
Test status
Simulation time 22244153411 ps
CPU time 39.48 seconds
Started Jul 15 06:53:40 PM PDT 24
Finished Jul 15 06:54:20 PM PDT 24
Peak memory 540364 kb
Host smart-78cee6d6-ca51-4fb1-8477-de0ee74d176c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163200047 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2163200047
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3183462276
Short name T1556
Test name
Test status
Simulation time 33147686547 ps
CPU time 209.48 seconds
Started Jul 15 06:53:42 PM PDT 24
Finished Jul 15 06:57:12 PM PDT 24
Peak memory 2602236 kb
Host smart-2040c6de-e78e-4509-86fc-8fbc538f3efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183462276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3183462276
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.603567362
Short name T300
Test name
Test status
Simulation time 3641690417 ps
CPU time 18.53 seconds
Started Jul 15 06:53:39 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 407436 kb
Host smart-e5260d55-533a-4b3a-b7f1-fd241d975a25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603567362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.603567362
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1393853284
Short name T1228
Test name
Test status
Simulation time 1506765182 ps
CPU time 6.7 seconds
Started Jul 15 06:53:36 PM PDT 24
Finished Jul 15 06:53:43 PM PDT 24
Peak memory 221996 kb
Host smart-8e207e78-5fe3-4629-9f07-af8af2756734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393853284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1393853284
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2465483460
Short name T1561
Test name
Test status
Simulation time 466937992 ps
CPU time 6.45 seconds
Started Jul 15 06:53:39 PM PDT 24
Finished Jul 15 06:53:46 PM PDT 24
Peak memory 205616 kb
Host smart-37c8d5c8-bdbe-4985-80bc-28706b296cf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465483460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2465483460
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2795824870
Short name T675
Test name
Test status
Simulation time 45367696 ps
CPU time 0.63 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:53:51 PM PDT 24
Peak memory 204748 kb
Host smart-8b9e84eb-55b1-46ca-a1e1-985e69b7d24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795824870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2795824870
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1401464048
Short name T37
Test name
Test status
Simulation time 208947429 ps
CPU time 1.65 seconds
Started Jul 15 06:53:51 PM PDT 24
Finished Jul 15 06:53:53 PM PDT 24
Peak memory 213820 kb
Host smart-d63a21f4-3303-4021-b2ce-ac9824bf4250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401464048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1401464048
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.305701377
Short name T1045
Test name
Test status
Simulation time 534777340 ps
CPU time 13.78 seconds
Started Jul 15 06:53:43 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 245452 kb
Host smart-15800190-238b-49ca-9022-370333fc9566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305701377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.305701377
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1221615682
Short name T876
Test name
Test status
Simulation time 16972757167 ps
CPU time 55.58 seconds
Started Jul 15 06:53:43 PM PDT 24
Finished Jul 15 06:54:39 PM PDT 24
Peak memory 288484 kb
Host smart-1c47fcfc-87b6-4cea-a306-9faaea2ee8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221615682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1221615682
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1369686361
Short name T1326
Test name
Test status
Simulation time 2662642938 ps
CPU time 36.89 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:54:21 PM PDT 24
Peak memory 531384 kb
Host smart-4715aba5-b458-4c01-b1b9-9546d46e40fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369686361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1369686361
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3636057468
Short name T1673
Test name
Test status
Simulation time 480791737 ps
CPU time 1.09 seconds
Started Jul 15 06:53:42 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 205240 kb
Host smart-53575585-d7e0-4d94-a912-76a096e364b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636057468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3636057468
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1618856282
Short name T1579
Test name
Test status
Simulation time 220491474 ps
CPU time 5.46 seconds
Started Jul 15 06:53:43 PM PDT 24
Finished Jul 15 06:53:49 PM PDT 24
Peak memory 245540 kb
Host smart-87e95261-9a9c-4eb3-8305-d0fe7b5344da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618856282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1618856282
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.58138740
Short name T518
Test name
Test status
Simulation time 3298293376 ps
CPU time 223.85 seconds
Started Jul 15 06:53:42 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 994408 kb
Host smart-b263bcee-c8d0-4ea5-bc8b-5387d2ac5d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58138740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.58138740
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_override.1239161268
Short name T148
Test name
Test status
Simulation time 30508307 ps
CPU time 0.71 seconds
Started Jul 15 06:53:45 PM PDT 24
Finished Jul 15 06:53:46 PM PDT 24
Peak memory 205156 kb
Host smart-91173833-306f-4fd1-819c-f3bfee4c541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239161268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1239161268
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3102437381
Short name T470
Test name
Test status
Simulation time 12345553195 ps
CPU time 87.93 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:55:13 PM PDT 24
Peak memory 205544 kb
Host smart-c517d051-3427-4450-a5f9-9d3f2e8d46b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102437381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3102437381
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.2592605263
Short name T363
Test name
Test status
Simulation time 103946974 ps
CPU time 1.18 seconds
Started Jul 15 06:53:44 PM PDT 24
Finished Jul 15 06:53:46 PM PDT 24
Peak memory 223136 kb
Host smart-88e6e21e-4947-45c4-8f80-3ca75af21899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592605263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.2592605263
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1753724466
Short name T1724
Test name
Test status
Simulation time 5614919890 ps
CPU time 65.04 seconds
Started Jul 15 06:53:41 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 333232 kb
Host smart-b4de2695-0ef0-4fb1-a7ed-816872b473fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753724466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1753724466
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3478046447
Short name T1093
Test name
Test status
Simulation time 3426175357 ps
CPU time 33.53 seconds
Started Jul 15 06:53:43 PM PDT 24
Finished Jul 15 06:54:17 PM PDT 24
Peak memory 213788 kb
Host smart-1016e15e-dea1-451d-8dd3-507783d6065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478046447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3478046447
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.464080479
Short name T369
Test name
Test status
Simulation time 138993999 ps
CPU time 0.93 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:53:51 PM PDT 24
Peak memory 205448 kb
Host smart-af9e515e-a0bb-433d-8382-a60828cb6c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464080479 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.464080479
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3999999701
Short name T442
Test name
Test status
Simulation time 279265775 ps
CPU time 1.69 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 06:53:57 PM PDT 24
Peak memory 213812 kb
Host smart-46373e99-caae-4a33-8e13-85d17fb9239c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999999701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3999999701
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.552993062
Short name T203
Test name
Test status
Simulation time 372815526 ps
CPU time 2.34 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:53:52 PM PDT 24
Peak memory 205508 kb
Host smart-756516a8-00a3-4566-9e9b-6c12edad55d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552993062 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.552993062
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3939634540
Short name T1121
Test name
Test status
Simulation time 120431625 ps
CPU time 1.23 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 205504 kb
Host smart-ea94c71a-6420-446d-94f5-d5eb0745009d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939634540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3939634540
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.378439728
Short name T913
Test name
Test status
Simulation time 795975521 ps
CPU time 1.6 seconds
Started Jul 15 06:53:50 PM PDT 24
Finished Jul 15 06:53:52 PM PDT 24
Peak memory 213828 kb
Host smart-69232faa-e503-41c6-bb5a-535729fefc6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378439728 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.378439728
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2855267016
Short name T1540
Test name
Test status
Simulation time 5770369502 ps
CPU time 7.03 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 06:54:02 PM PDT 24
Peak memory 222068 kb
Host smart-69abb697-7b6b-457e-aa32-e0628888e576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855267016 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2855267016
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2067609649
Short name T947
Test name
Test status
Simulation time 1435311829 ps
CPU time 2.18 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:53:52 PM PDT 24
Peak memory 213832 kb
Host smart-4884b53c-3ada-4933-b319-3574b6a4fd4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067609649 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2067609649
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.3787340017
Short name T1538
Test name
Test status
Simulation time 465914359 ps
CPU time 2.52 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:53:59 PM PDT 24
Peak memory 213836 kb
Host smart-44703d52-005e-4e5b-a655-6cedd03f3ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787340017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.3787340017
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.484048491
Short name T810
Test name
Test status
Simulation time 538641142 ps
CPU time 2.79 seconds
Started Jul 15 06:53:48 PM PDT 24
Finished Jul 15 06:53:52 PM PDT 24
Peak memory 205616 kb
Host smart-b896fa84-0b14-479f-b316-ae488d472f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484048491 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.484048491
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.1745052934
Short name T1658
Test name
Test status
Simulation time 254963959 ps
CPU time 1.46 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 222464 kb
Host smart-e0d29a65-d762-47a9-9bd5-04f4fd740457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745052934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_txstretch.1745052934
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.2923911566
Short name T877
Test name
Test status
Simulation time 439552149 ps
CPU time 3.09 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:53:53 PM PDT 24
Peak memory 213792 kb
Host smart-32d5efcf-fca5-4ced-b3e6-fe1a7c235110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923911566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.2923911566
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.4052060126
Short name T572
Test name
Test status
Simulation time 1811048977 ps
CPU time 2.26 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 205448 kb
Host smart-bf35c970-c06d-4286-bd47-6a09e5cea7fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052060126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.4052060126
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1045036486
Short name T1435
Test name
Test status
Simulation time 2696233584 ps
CPU time 22.52 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:54:20 PM PDT 24
Peak memory 213932 kb
Host smart-1c5ebcf0-12e0-4dbb-b02d-dd5406f01117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045036486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1045036486
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.2566531989
Short name T768
Test name
Test status
Simulation time 24451351034 ps
CPU time 599.86 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 07:03:56 PM PDT 24
Peak memory 4431136 kb
Host smart-220f9fd1-de4c-4ca3-a26b-3aa5cd7a108f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566531989 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.2566531989
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.4194567603
Short name T1210
Test name
Test status
Simulation time 2642493992 ps
CPU time 10.2 seconds
Started Jul 15 06:53:49 PM PDT 24
Finished Jul 15 06:54:00 PM PDT 24
Peak memory 205724 kb
Host smart-c15654f8-4870-4505-949b-c0e7531db43d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194567603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.4194567603
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.421732672
Short name T1272
Test name
Test status
Simulation time 35241019628 ps
CPU time 304.26 seconds
Started Jul 15 06:53:51 PM PDT 24
Finished Jul 15 06:58:56 PM PDT 24
Peak memory 3223272 kb
Host smart-59242828-df67-4c38-8775-3b4cf060fe16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421732672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.421732672
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2867231392
Short name T1465
Test name
Test status
Simulation time 4682703210 ps
CPU time 27.66 seconds
Started Jul 15 06:53:48 PM PDT 24
Finished Jul 15 06:54:17 PM PDT 24
Peak memory 506400 kb
Host smart-d92fd388-e51d-4ccb-a92b-7860f76de701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867231392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2867231392
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3290460498
Short name T1429
Test name
Test status
Simulation time 5677622616 ps
CPU time 7.63 seconds
Started Jul 15 06:53:48 PM PDT 24
Finished Jul 15 06:53:56 PM PDT 24
Peak memory 213956 kb
Host smart-717319c5-bf5c-453e-82ff-7019f681efe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290460498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3290460498
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2603194134
Short name T1140
Test name
Test status
Simulation time 26046692 ps
CPU time 0.62 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:01 PM PDT 24
Peak memory 204708 kb
Host smart-1043d09d-0e5a-4a04-b1f7-594c607cc5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603194134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2603194134
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.93430684
Short name T1270
Test name
Test status
Simulation time 1242570769 ps
CPU time 12.58 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 06:54:09 PM PDT 24
Peak memory 213772 kb
Host smart-2cf1ed96-44f4-45a7-bfb7-54e9132cf2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93430684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.93430684
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.445329715
Short name T1032
Test name
Test status
Simulation time 362826330 ps
CPU time 5.33 seconds
Started Jul 15 06:53:59 PM PDT 24
Finished Jul 15 06:54:04 PM PDT 24
Peak memory 263740 kb
Host smart-825a474a-6e17-4ffd-aeb5-fd34f19d5abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445329715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.445329715
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.157034976
Short name T609
Test name
Test status
Simulation time 2468214410 ps
CPU time 154.13 seconds
Started Jul 15 06:53:58 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 495564 kb
Host smart-fc4ac5fc-8199-4ee1-bf0a-697bdb7d33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157034976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.157034976
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2067175759
Short name T1135
Test name
Test status
Simulation time 3611981753 ps
CPU time 128.51 seconds
Started Jul 15 06:53:59 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 644760 kb
Host smart-3c2d08b9-9f5d-44fd-a48e-2ca9ec31a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067175759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2067175759
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3327923713
Short name T565
Test name
Test status
Simulation time 181399959 ps
CPU time 1.09 seconds
Started Jul 15 06:53:58 PM PDT 24
Finished Jul 15 06:53:59 PM PDT 24
Peak memory 205160 kb
Host smart-c35082d1-7916-4828-be7c-6603346f6960
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327923713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3327923713
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1608954725
Short name T1696
Test name
Test status
Simulation time 1159581547 ps
CPU time 7.49 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:54:04 PM PDT 24
Peak memory 205536 kb
Host smart-49595fee-dc04-409d-b796-2df4104e9de0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608954725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1608954725
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1638930163
Short name T113
Test name
Test status
Simulation time 11935832087 ps
CPU time 59.62 seconds
Started Jul 15 06:53:59 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 843200 kb
Host smart-0b8d1cb6-d510-44a7-acc7-f82104432832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638930163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1638930163
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.104213666
Short name T1637
Test name
Test status
Simulation time 317266481 ps
CPU time 5.2 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:54:07 PM PDT 24
Peak memory 205484 kb
Host smart-2084ebfc-739d-4b9f-9121-496a639072e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104213666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.104213666
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.3235998758
Short name T1544
Test name
Test status
Simulation time 27202921 ps
CPU time 0.68 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 205248 kb
Host smart-5b2fefe3-bae4-4383-bdde-a702478bfa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235998758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3235998758
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.946379784
Short name T24
Test name
Test status
Simulation time 7635677363 ps
CPU time 130.25 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:56:07 PM PDT 24
Peak memory 798696 kb
Host smart-4ad46892-7a13-4fe5-87c3-aa4801d2a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946379784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.946379784
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.4231508288
Short name T91
Test name
Test status
Simulation time 222981281 ps
CPU time 9.82 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:54:07 PM PDT 24
Peak memory 221680 kb
Host smart-2f9a9d1f-c3a8-4a23-bd7b-34a2f2a75daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231508288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.4231508288
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.29699209
Short name T1269
Test name
Test status
Simulation time 1864721906 ps
CPU time 88.83 seconds
Started Jul 15 06:53:58 PM PDT 24
Finished Jul 15 06:55:28 PM PDT 24
Peak memory 356832 kb
Host smart-1804d2db-0eed-4dc1-9fc7-ea62b2d7fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29699209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.29699209
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3252656133
Short name T621
Test name
Test status
Simulation time 1375534590 ps
CPU time 6.64 seconds
Started Jul 15 06:53:59 PM PDT 24
Finished Jul 15 06:54:06 PM PDT 24
Peak memory 213884 kb
Host smart-be62b9f5-7815-454c-b444-996ada723e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252656133 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3252656133
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2214222564
Short name T153
Test name
Test status
Simulation time 139108287 ps
CPU time 1.02 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:53:59 PM PDT 24
Peak memory 205424 kb
Host smart-3c1efcb0-879e-434e-8832-4ddccd0e636e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214222564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2214222564
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3643649315
Short name T356
Test name
Test status
Simulation time 1002736442 ps
CPU time 1.65 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:53:58 PM PDT 24
Peak memory 210848 kb
Host smart-f614bd45-91fc-4692-b779-2a4bdc8fa902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643649315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3643649315
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.472522576
Short name T1367
Test name
Test status
Simulation time 412194277 ps
CPU time 2.36 seconds
Started Jul 15 06:54:02 PM PDT 24
Finished Jul 15 06:54:05 PM PDT 24
Peak memory 205504 kb
Host smart-ffc46094-115e-4a79-9273-0767487797db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472522576 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.472522576
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3835504447
Short name T1592
Test name
Test status
Simulation time 165707795 ps
CPU time 1.25 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:54:03 PM PDT 24
Peak memory 205424 kb
Host smart-f5793953-66cc-4e25-818b-3af9f0210bc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835504447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3835504447
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3909389648
Short name T323
Test name
Test status
Simulation time 848925398 ps
CPU time 5.09 seconds
Started Jul 15 06:53:58 PM PDT 24
Finished Jul 15 06:54:04 PM PDT 24
Peak memory 213792 kb
Host smart-18632239-cf66-450f-bb30-aad346caea50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909389648 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3909389648
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.936840783
Short name T1346
Test name
Test status
Simulation time 4458456617 ps
CPU time 9.31 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:54:07 PM PDT 24
Peak memory 205724 kb
Host smart-48af2069-4e3b-44fe-af0f-1ba63e76f52d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936840783 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.936840783
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.645596668
Short name T1414
Test name
Test status
Simulation time 668646833 ps
CPU time 3.06 seconds
Started Jul 15 06:54:02 PM PDT 24
Finished Jul 15 06:54:05 PM PDT 24
Peak memory 213876 kb
Host smart-25b3fba7-a8d1-4c99-8bc8-298bdfcd1046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645596668 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_nack_acqfull.645596668
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.1635267344
Short name T1720
Test name
Test status
Simulation time 1155037221 ps
CPU time 2.8 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:04 PM PDT 24
Peak memory 205584 kb
Host smart-69f4c68d-7ad0-49d3-8479-c4113ede8b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635267344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.1635267344
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.409869128
Short name T1117
Test name
Test status
Simulation time 272381980 ps
CPU time 1.54 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:01 PM PDT 24
Peak memory 222252 kb
Host smart-5f66c606-1542-4e8e-8f11-eea22d95435d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409869128 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_nack_txstretch.409869128
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_perf.2660417322
Short name T755
Test name
Test status
Simulation time 3895861743 ps
CPU time 6.6 seconds
Started Jul 15 06:53:57 PM PDT 24
Finished Jul 15 06:54:05 PM PDT 24
Peak memory 221988 kb
Host smart-8c0cf123-caa7-443d-a119-c277a3af58e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660417322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.2660417322
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.1010805509
Short name T1473
Test name
Test status
Simulation time 900002603 ps
CPU time 2.15 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:03 PM PDT 24
Peak memory 205424 kb
Host smart-333b67ba-581a-4c13-af39-13493140ce6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010805509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.1010805509
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2632412676
Short name T1555
Test name
Test status
Simulation time 794315423 ps
CPU time 25.21 seconds
Started Jul 15 06:53:58 PM PDT 24
Finished Jul 15 06:54:24 PM PDT 24
Peak memory 213808 kb
Host smart-0301d96e-752a-4166-bca3-8c766a036010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632412676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2632412676
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.3387188195
Short name T1084
Test name
Test status
Simulation time 32955119675 ps
CPU time 60.99 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:55:03 PM PDT 24
Peak memory 648256 kb
Host smart-c21c4cd5-41d0-4a1e-b0ed-68b85e402e28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387188195 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.3387188195
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.4252609446
Short name T155
Test name
Test status
Simulation time 334671055 ps
CPU time 14.34 seconds
Started Jul 15 06:53:56 PM PDT 24
Finished Jul 15 06:54:11 PM PDT 24
Peak memory 205652 kb
Host smart-05efbe36-5117-49c9-9b67-1dcb23f67d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252609446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.4252609446
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1882920519
Short name T1261
Test name
Test status
Simulation time 49382850724 ps
CPU time 1174.41 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 07:13:36 PM PDT 24
Peak memory 7222628 kb
Host smart-7d54f00f-cd8e-45d9-a2fa-ddab21a20bf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882920519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1882920519
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.4070942627
Short name T377
Test name
Test status
Simulation time 4828822115 ps
CPU time 120.4 seconds
Started Jul 15 06:53:59 PM PDT 24
Finished Jul 15 06:56:00 PM PDT 24
Peak memory 733076 kb
Host smart-82736a90-bf9f-4151-9894-da4ca013b21c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070942627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.4070942627
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.523775154
Short name T1322
Test name
Test status
Simulation time 4340586982 ps
CPU time 5.97 seconds
Started Jul 15 06:53:55 PM PDT 24
Finished Jul 15 06:54:01 PM PDT 24
Peak memory 213864 kb
Host smart-09d15fea-e4e0-4165-a9f4-6563c5743bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523775154 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.523775154
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.3313781871
Short name T1379
Test name
Test status
Simulation time 190551568 ps
CPU time 2.52 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:03 PM PDT 24
Peak memory 205620 kb
Host smart-00061cfc-1a90-46c3-b35f-5fd26a18ba88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313781871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.3313781871
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3648074363
Short name T1393
Test name
Test status
Simulation time 205983605 ps
CPU time 2.66 seconds
Started Jul 15 06:54:08 PM PDT 24
Finished Jul 15 06:54:11 PM PDT 24
Peak memory 213748 kb
Host smart-b4eef786-7f95-4bf8-a246-bde91c6e2f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648074363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3648074363
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2514895541
Short name T1092
Test name
Test status
Simulation time 340422937 ps
CPU time 18.38 seconds
Started Jul 15 06:54:06 PM PDT 24
Finished Jul 15 06:54:26 PM PDT 24
Peak memory 277100 kb
Host smart-8eef0c04-fd77-4ff2-92f6-8d54a62fad72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514895541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2514895541
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.943274466
Short name T1030
Test name
Test status
Simulation time 10376012832 ps
CPU time 169.15 seconds
Started Jul 15 06:54:04 PM PDT 24
Finished Jul 15 06:56:54 PM PDT 24
Peak memory 617648 kb
Host smart-faa97c8d-1c8f-41bd-b52f-e94d14bd8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943274466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.943274466
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.943613946
Short name T1584
Test name
Test status
Simulation time 6886561293 ps
CPU time 117.99 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:56:00 PM PDT 24
Peak memory 616288 kb
Host smart-2440c16e-65fe-4db3-a2ab-2bfd7a9401c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943613946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.943613946
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.964831561
Short name T973
Test name
Test status
Simulation time 82060085 ps
CPU time 1.09 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:02 PM PDT 24
Peak memory 205276 kb
Host smart-fa7a0af1-6e74-47b7-9eba-3da889c0d33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964831561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.964831561
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.269495138
Short name T749
Test name
Test status
Simulation time 709531179 ps
CPU time 4.88 seconds
Started Jul 15 06:54:09 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 236780 kb
Host smart-ddff0e0e-6cb3-4a04-bf2c-1ce5b8f14737
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269495138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
269495138
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1673652761
Short name T844
Test name
Test status
Simulation time 10267758617 ps
CPU time 162.69 seconds
Started Jul 15 06:54:03 PM PDT 24
Finished Jul 15 06:56:46 PM PDT 24
Peak memory 819304 kb
Host smart-14906186-f485-438e-93e5-0cbb86891eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673652761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1673652761
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2515322108
Short name T607
Test name
Test status
Simulation time 480848976 ps
CPU time 6 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:19 PM PDT 24
Peak memory 205488 kb
Host smart-d25ed689-afe9-43c6-9eb3-d3ba17c28796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515322108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2515322108
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3994216189
Short name T975
Test name
Test status
Simulation time 429867756 ps
CPU time 1.76 seconds
Started Jul 15 06:54:15 PM PDT 24
Finished Jul 15 06:54:17 PM PDT 24
Peak memory 213744 kb
Host smart-23dcb81c-c0c5-47f8-8c46-411214841ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994216189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3994216189
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3809445347
Short name T149
Test name
Test status
Simulation time 92461512 ps
CPU time 0.71 seconds
Started Jul 15 06:54:01 PM PDT 24
Finished Jul 15 06:54:03 PM PDT 24
Peak memory 205272 kb
Host smart-91d5a297-7b36-4991-9227-97423b5317c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809445347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3809445347
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3981320747
Short name T142
Test name
Test status
Simulation time 6352205433 ps
CPU time 24.51 seconds
Started Jul 15 06:54:08 PM PDT 24
Finished Jul 15 06:54:33 PM PDT 24
Peak memory 466452 kb
Host smart-a30b15e9-69c3-42d6-b3d7-047ec064d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981320747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3981320747
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.4109121327
Short name T1617
Test name
Test status
Simulation time 2440181489 ps
CPU time 6.6 seconds
Started Jul 15 06:54:05 PM PDT 24
Finished Jul 15 06:54:13 PM PDT 24
Peak memory 205528 kb
Host smart-0a5db17b-13ab-4aeb-ad72-491ddb421963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109121327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.4109121327
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2563447281
Short name T35
Test name
Test status
Simulation time 5252496332 ps
CPU time 17.9 seconds
Started Jul 15 06:54:00 PM PDT 24
Finished Jul 15 06:54:18 PM PDT 24
Peak memory 262424 kb
Host smart-be9f9806-9c86-4d39-9af6-cde4aab6abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563447281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2563447281
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1340140663
Short name T121
Test name
Test status
Simulation time 72211541970 ps
CPU time 695.47 seconds
Started Jul 15 06:54:06 PM PDT 24
Finished Jul 15 07:05:43 PM PDT 24
Peak memory 2611696 kb
Host smart-7023d6f3-1373-43de-8b12-97b539f89521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340140663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1340140663
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1155900926
Short name T542
Test name
Test status
Simulation time 3763018417 ps
CPU time 40.4 seconds
Started Jul 15 06:54:05 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 213756 kb
Host smart-b815b580-2102-4d28-ac5f-f9451ed85e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155900926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1155900926
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2825120719
Short name T1328
Test name
Test status
Simulation time 2611510337 ps
CPU time 3.77 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:18 PM PDT 24
Peak memory 218320 kb
Host smart-7963d1ad-b260-4e0c-9635-00783d2e8257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825120719 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2825120719
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.966422401
Short name T1264
Test name
Test status
Simulation time 469159639 ps
CPU time 1.01 seconds
Started Jul 15 06:54:06 PM PDT 24
Finished Jul 15 06:54:08 PM PDT 24
Peak memory 205468 kb
Host smart-e807c3ad-3472-4832-9f5d-6bf89a47851d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966422401 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.966422401
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.1100956637
Short name T735
Test name
Test status
Simulation time 148374805 ps
CPU time 0.99 seconds
Started Jul 15 06:54:06 PM PDT 24
Finished Jul 15 06:54:08 PM PDT 24
Peak memory 205496 kb
Host smart-12a6e0ee-d6bf-4088-bfa1-f5124e456e3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100956637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.1100956637
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.536846058
Short name T472
Test name
Test status
Simulation time 1943167595 ps
CPU time 2.49 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:16 PM PDT 24
Peak memory 205652 kb
Host smart-4270a131-b596-436f-9397-31c352cc19a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536846058 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.536846058
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3533793782
Short name T1474
Test name
Test status
Simulation time 172483623 ps
CPU time 1.05 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 205420 kb
Host smart-ced45ec6-c2d2-44d2-b6a7-a36fb014ad93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533793782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3533793782
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.153684915
Short name T371
Test name
Test status
Simulation time 2979306109 ps
CPU time 6.29 seconds
Started Jul 15 06:54:07 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 218152 kb
Host smart-c212eee7-edc4-4462-b6e2-45edf2f31439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153684915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.153684915
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3421062693
Short name T339
Test name
Test status
Simulation time 18917920306 ps
CPU time 464.47 seconds
Started Jul 15 06:54:05 PM PDT 24
Finished Jul 15 07:01:51 PM PDT 24
Peak memory 4571788 kb
Host smart-041bf826-cfce-4721-91ce-a30d3bed0fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421062693 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3421062693
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.2199546806
Short name T406
Test name
Test status
Simulation time 1752261619 ps
CPU time 2.68 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:16 PM PDT 24
Peak memory 213732 kb
Host smart-a34a0300-a9a2-4515-a957-6afdd821149a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199546806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.2199546806
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.1708911517
Short name T1318
Test name
Test status
Simulation time 894876973 ps
CPU time 2.5 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 205588 kb
Host smart-7698e616-05db-4174-b47b-5f6a28be2507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708911517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.1708911517
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.1203138617
Short name T1494
Test name
Test status
Simulation time 144517270 ps
CPU time 1.44 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 222400 kb
Host smart-8b36ab8a-447a-435a-b04f-9930d232c8e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203138617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.1203138617
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/15.i2c_target_perf.3786425930
Short name T1271
Test name
Test status
Simulation time 644544656 ps
CPU time 4.66 seconds
Started Jul 15 06:54:08 PM PDT 24
Finished Jul 15 06:54:13 PM PDT 24
Peak memory 216516 kb
Host smart-1396d2e7-f061-4677-bf1d-daa2280e87f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786425930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.3786425930
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.1370564815
Short name T1231
Test name
Test status
Simulation time 1991900638 ps
CPU time 2.32 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 205432 kb
Host smart-2b32e27e-17ed-4fbb-beef-e464660e71f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370564815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.1370564815
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1164822940
Short name T1289
Test name
Test status
Simulation time 3896340137 ps
CPU time 10.3 seconds
Started Jul 15 06:54:08 PM PDT 24
Finished Jul 15 06:54:18 PM PDT 24
Peak memory 213836 kb
Host smart-dea52bcf-45e3-4af9-b04f-fc1fd63ba476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164822940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1164822940
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1110400884
Short name T1176
Test name
Test status
Simulation time 54349074310 ps
CPU time 155.51 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 1941912 kb
Host smart-221e8596-2e36-4e8d-a83d-5687ad0bb4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110400884 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1110400884
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.633410698
Short name T1257
Test name
Test status
Simulation time 4331762068 ps
CPU time 20.38 seconds
Started Jul 15 06:54:07 PM PDT 24
Finished Jul 15 06:54:28 PM PDT 24
Peak memory 230248 kb
Host smart-fe678b3e-f45a-4f12-b945-f281428b665a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633410698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.633410698
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1318338001
Short name T880
Test name
Test status
Simulation time 17792227941 ps
CPU time 33.41 seconds
Started Jul 15 06:54:05 PM PDT 24
Finished Jul 15 06:54:39 PM PDT 24
Peak memory 206748 kb
Host smart-57f1e3f8-2ebd-4a95-8857-5a2f92e43801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318338001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1318338001
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.468835724
Short name T1551
Test name
Test status
Simulation time 1819999982 ps
CPU time 13 seconds
Started Jul 15 06:54:06 PM PDT 24
Finished Jul 15 06:54:20 PM PDT 24
Peak memory 376088 kb
Host smart-5d2aef78-f9a6-467c-8582-8b1e6803bf3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468835724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.468835724
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2072139664
Short name T1459
Test name
Test status
Simulation time 1159013440 ps
CPU time 6.3 seconds
Started Jul 15 06:54:05 PM PDT 24
Finished Jul 15 06:54:12 PM PDT 24
Peak memory 222064 kb
Host smart-52805880-fb72-47a0-ac72-340bbce91600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072139664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2072139664
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.3790588020
Short name T1725
Test name
Test status
Simulation time 111808351 ps
CPU time 2.53 seconds
Started Jul 15 06:54:11 PM PDT 24
Finished Jul 15 06:54:14 PM PDT 24
Peak memory 205552 kb
Host smart-52498178-beb6-4034-bf20-52dd6db63b98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790588020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.3790588020
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3600669377
Short name T618
Test name
Test status
Simulation time 26543046 ps
CPU time 0.66 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:54:26 PM PDT 24
Peak memory 204736 kb
Host smart-1b76388e-43c3-4ed4-9fbc-76f0a6572c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600669377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3600669377
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3088177568
Short name T729
Test name
Test status
Simulation time 288595106 ps
CPU time 1.35 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:22 PM PDT 24
Peak memory 213840 kb
Host smart-c2ac4dd0-48df-4b68-967a-6e42648ca883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088177568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3088177568
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3006488427
Short name T983
Test name
Test status
Simulation time 261025537 ps
CPU time 4.8 seconds
Started Jul 15 06:54:10 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 256876 kb
Host smart-863080fc-4328-46b8-94fc-39362e36c0ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006488427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3006488427
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2623016585
Short name T25
Test name
Test status
Simulation time 3248452418 ps
CPU time 256.65 seconds
Started Jul 15 06:54:17 PM PDT 24
Finished Jul 15 06:58:34 PM PDT 24
Peak memory 869952 kb
Host smart-55cf0a1e-e298-4d33-baf9-e87aee2cc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623016585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2623016585
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2089017832
Short name T905
Test name
Test status
Simulation time 2583059950 ps
CPU time 36.55 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 528156 kb
Host smart-3729c130-fd14-4316-a099-87e70ffb9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089017832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2089017832
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2298081839
Short name T254
Test name
Test status
Simulation time 880634162 ps
CPU time 1.07 seconds
Started Jul 15 06:54:14 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 205260 kb
Host smart-8c9882b9-6b84-4727-b99b-d2ac36b84661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298081839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2298081839
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.4218438216
Short name T1602
Test name
Test status
Simulation time 551385749 ps
CPU time 15.9 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:29 PM PDT 24
Peak memory 261256 kb
Host smart-3f2cdfb3-ad64-4306-aa0f-624dfaff4909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218438216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.4218438216
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.633580171
Short name T914
Test name
Test status
Simulation time 25497931180 ps
CPU time 140.46 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:56:34 PM PDT 24
Peak memory 1353480 kb
Host smart-9902c176-ef8f-4216-9133-0d38ed8c3bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633580171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.633580171
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.742900970
Short name T259
Test name
Test status
Simulation time 518458778 ps
CPU time 8.55 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:30 PM PDT 24
Peak memory 205512 kb
Host smart-afafd70f-f8dd-4a60-9a91-12829c5fe12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742900970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.742900970
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.1482058785
Short name T1031
Test name
Test status
Simulation time 49120396 ps
CPU time 0.66 seconds
Started Jul 15 06:54:15 PM PDT 24
Finished Jul 15 06:54:17 PM PDT 24
Peak memory 205200 kb
Host smart-bc5cbf98-c9e1-4bec-94ca-f1a17c6c315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482058785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1482058785
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.864550341
Short name T748
Test name
Test status
Simulation time 5362170696 ps
CPU time 194.03 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 223748 kb
Host smart-67cb2011-b3ef-4bfc-83c8-eff55b556f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864550341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.864550341
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3359354779
Short name T1420
Test name
Test status
Simulation time 245254231 ps
CPU time 1.72 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 205444 kb
Host smart-74853837-a3c3-411e-9fc3-ca33ec2bb8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359354779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3359354779
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.331122896
Short name T1660
Test name
Test status
Simulation time 2636361623 ps
CPU time 62.9 seconds
Started Jul 15 06:54:13 PM PDT 24
Finished Jul 15 06:55:16 PM PDT 24
Peak memory 312472 kb
Host smart-4664efff-2e32-4753-ac3f-83cfb343ffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331122896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.331122896
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.221474125
Short name T1311
Test name
Test status
Simulation time 839460559 ps
CPU time 16.4 seconds
Started Jul 15 06:54:12 PM PDT 24
Finished Jul 15 06:54:29 PM PDT 24
Peak memory 217532 kb
Host smart-9afe0d8e-d706-42b1-b04d-dab00c868f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221474125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.221474125
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1966250855
Short name T575
Test name
Test status
Simulation time 983097015 ps
CPU time 5.02 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:26 PM PDT 24
Peak memory 213956 kb
Host smart-acd00d8a-b6cc-4fcf-bbcf-b4b8a342fbf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966250855 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1966250855
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1532934657
Short name T1415
Test name
Test status
Simulation time 821401320 ps
CPU time 0.83 seconds
Started Jul 15 06:54:19 PM PDT 24
Finished Jul 15 06:54:21 PM PDT 24
Peak memory 205400 kb
Host smart-f72f13ee-b1e3-4d69-99c0-8fbc77e7d5d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532934657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1532934657
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.234754592
Short name T1166
Test name
Test status
Simulation time 232134907 ps
CPU time 0.83 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:22 PM PDT 24
Peak memory 213684 kb
Host smart-82b45ff0-d1a3-42c1-83e5-4003af746f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234754592 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.234754592
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3786938212
Short name T370
Test name
Test status
Simulation time 1537839869 ps
CPU time 2.41 seconds
Started Jul 15 06:54:21 PM PDT 24
Finished Jul 15 06:54:24 PM PDT 24
Peak memory 205696 kb
Host smart-5d887fdc-6c53-47ec-9b6f-c69612cf9106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786938212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3786938212
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.4288658
Short name T1076
Test name
Test status
Simulation time 454760438 ps
CPU time 1.26 seconds
Started Jul 15 06:54:19 PM PDT 24
Finished Jul 15 06:54:21 PM PDT 24
Peak memory 205468 kb
Host smart-bf0af6a3-ef3d-48a6-bd2e-280daa09bba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288658 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.4288658
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2995646071
Short name T62
Test name
Test status
Simulation time 1570802375 ps
CPU time 1.78 seconds
Started Jul 15 06:54:17 PM PDT 24
Finished Jul 15 06:54:20 PM PDT 24
Peak memory 213824 kb
Host smart-29822204-8578-498f-b0b0-ce432778682e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995646071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2995646071
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.4125498550
Short name T1262
Test name
Test status
Simulation time 5294152186 ps
CPU time 7.27 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:28 PM PDT 24
Peak memory 223472 kb
Host smart-045a6ed1-b94a-4e51-9e90-a852de019bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125498550 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.4125498550
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3270808608
Short name T936
Test name
Test status
Simulation time 6835919649 ps
CPU time 5.05 seconds
Started Jul 15 06:54:18 PM PDT 24
Finished Jul 15 06:54:23 PM PDT 24
Peak memory 205732 kb
Host smart-5764e2e3-3ec7-4080-b63b-ba82cda1bccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270808608 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3270808608
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.577113483
Short name T919
Test name
Test status
Simulation time 2685211569 ps
CPU time 2.52 seconds
Started Jul 15 06:54:24 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 213896 kb
Host smart-42d219aa-5b5d-46f7-9411-2b96738f617e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577113483 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_nack_acqfull.577113483
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.3671697118
Short name T61
Test name
Test status
Simulation time 594911049 ps
CPU time 2.92 seconds
Started Jul 15 06:54:23 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 205624 kb
Host smart-c8752384-06b7-425c-bb3d-4810bfaa081a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671697118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.3671697118
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.2813858057
Short name T1058
Test name
Test status
Simulation time 2973498515 ps
CPU time 5.25 seconds
Started Jul 15 06:54:18 PM PDT 24
Finished Jul 15 06:54:24 PM PDT 24
Peak memory 221168 kb
Host smart-4ec9b822-398a-4cb8-a953-159acc412353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813858057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.2813858057
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.1939199105
Short name T665
Test name
Test status
Simulation time 483259460 ps
CPU time 2.69 seconds
Started Jul 15 06:54:16 PM PDT 24
Finished Jul 15 06:54:19 PM PDT 24
Peak memory 205396 kb
Host smart-13c56382-b039-466b-8703-b14049d88c61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939199105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.1939199105
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2447552789
Short name T1443
Test name
Test status
Simulation time 3379699368 ps
CPU time 23.82 seconds
Started Jul 15 06:54:19 PM PDT 24
Finished Jul 15 06:54:44 PM PDT 24
Peak memory 213896 kb
Host smart-3aa46bcd-6607-4012-9df4-5f2424821490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447552789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2447552789
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.2222237701
Short name T170
Test name
Test status
Simulation time 31536230981 ps
CPU time 316.67 seconds
Started Jul 15 06:54:19 PM PDT 24
Finished Jul 15 06:59:36 PM PDT 24
Peak memory 2862936 kb
Host smart-de456c40-c342-40f3-8007-6af2f01c7f6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222237701 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.2222237701
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.4088851337
Short name T127
Test name
Test status
Simulation time 341140179 ps
CPU time 5.46 seconds
Started Jul 15 06:54:17 PM PDT 24
Finished Jul 15 06:54:23 PM PDT 24
Peak memory 205640 kb
Host smart-54313e03-b27a-4254-8f1f-6cbceaf4d873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088851337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.4088851337
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.58212317
Short name T888
Test name
Test status
Simulation time 15043496281 ps
CPU time 5.23 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:26 PM PDT 24
Peak memory 205676 kb
Host smart-187da380-4343-47c6-a2c5-005b9a84c838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58212317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stress_wr.58212317
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.245806016
Short name T1545
Test name
Test status
Simulation time 230318983 ps
CPU time 1.12 seconds
Started Jul 15 06:54:20 PM PDT 24
Finished Jul 15 06:54:22 PM PDT 24
Peak memory 205604 kb
Host smart-7e66281a-ec71-4a7a-84b4-90b52c03d65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245806016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.245806016
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.955775737
Short name T1652
Test name
Test status
Simulation time 5010152082 ps
CPU time 7.33 seconds
Started Jul 15 06:54:21 PM PDT 24
Finished Jul 15 06:54:29 PM PDT 24
Peak memory 213912 kb
Host smart-502e08cf-533f-40fa-b998-db9a36d4b906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955775737 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.955775737
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.1665697578
Short name T937
Test name
Test status
Simulation time 150231033 ps
CPU time 3.19 seconds
Started Jul 15 06:54:19 PM PDT 24
Finished Jul 15 06:54:23 PM PDT 24
Peak memory 205624 kb
Host smart-ef6010aa-449f-4912-a7db-c22acc72e0c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665697578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1665697578
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.854946768
Short name T813
Test name
Test status
Simulation time 22044083 ps
CPU time 0.64 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:54:36 PM PDT 24
Peak memory 204792 kb
Host smart-05aa663d-1813-4d0f-985e-5de628b25fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854946768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.854946768
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.517576145
Short name T669
Test name
Test status
Simulation time 497924540 ps
CPU time 9.13 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:54:34 PM PDT 24
Peak memory 213656 kb
Host smart-360e89ef-76a8-40d1-a1c5-97e8d66146f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517576145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.517576145
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2479138346
Short name T355
Test name
Test status
Simulation time 1708130884 ps
CPU time 4.63 seconds
Started Jul 15 06:54:24 PM PDT 24
Finished Jul 15 06:54:29 PM PDT 24
Peak memory 256828 kb
Host smart-0f522a18-9df2-4d55-bb1c-da5a798b6cec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479138346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2479138346
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3597564751
Short name T137
Test name
Test status
Simulation time 15313556830 ps
CPU time 252.69 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 714044 kb
Host smart-57b63fe0-392f-4f59-b4d0-c94e7b5180a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597564751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3597564751
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1953108378
Short name T474
Test name
Test status
Simulation time 2270401972 ps
CPU time 159.54 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 745824 kb
Host smart-63c0d3d0-fd90-436f-8f65-1f0a0a405ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953108378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1953108378
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2824145625
Short name T1553
Test name
Test status
Simulation time 261982089 ps
CPU time 1.2 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 205248 kb
Host smart-78473476-8178-49c8-add8-28ef8f90eeb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824145625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2824145625
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2893142755
Short name T1629
Test name
Test status
Simulation time 138113500 ps
CPU time 2.84 seconds
Started Jul 15 06:54:23 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 205508 kb
Host smart-33364c21-5907-4860-9985-2f48391a7dae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893142755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2893142755
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3609324916
Short name T622
Test name
Test status
Simulation time 11964645086 ps
CPU time 203.61 seconds
Started Jul 15 06:54:23 PM PDT 24
Finished Jul 15 06:57:48 PM PDT 24
Peak memory 870892 kb
Host smart-be410b28-fcd9-434b-8b93-a91c29e36753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609324916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3609324916
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1440172872
Short name T699
Test name
Test status
Simulation time 1916513099 ps
CPU time 6.02 seconds
Started Jul 15 06:54:36 PM PDT 24
Finished Jul 15 06:54:42 PM PDT 24
Peak memory 205492 kb
Host smart-3e110e49-4733-4988-815b-e4b9568063d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440172872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1440172872
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.2371836053
Short name T99
Test name
Test status
Simulation time 47611203 ps
CPU time 0.67 seconds
Started Jul 15 06:54:23 PM PDT 24
Finished Jul 15 06:54:24 PM PDT 24
Peak memory 205220 kb
Host smart-e18443d5-1ac4-4340-b2be-873b0ceb21ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371836053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2371836053
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3046976859
Short name T527
Test name
Test status
Simulation time 75427108661 ps
CPU time 43.84 seconds
Started Jul 15 06:54:25 PM PDT 24
Finished Jul 15 06:55:09 PM PDT 24
Peak memory 205544 kb
Host smart-6e90bd2f-1f32-47fe-8a63-4b758c7084ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046976859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3046976859
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.269562072
Short name T1255
Test name
Test status
Simulation time 43216467 ps
CPU time 1.28 seconds
Started Jul 15 06:54:24 PM PDT 24
Finished Jul 15 06:54:26 PM PDT 24
Peak memory 224024 kb
Host smart-1da8e345-761e-45a4-ac40-4a1bc56b6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269562072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.269562072
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1766065520
Short name T1677
Test name
Test status
Simulation time 6502662737 ps
CPU time 83.31 seconds
Started Jul 15 06:54:24 PM PDT 24
Finished Jul 15 06:55:48 PM PDT 24
Peak memory 378548 kb
Host smart-57840c80-1b5f-4998-8856-7cedb2d140ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766065520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1766065520
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.345313187
Short name T130
Test name
Test status
Simulation time 22822511081 ps
CPU time 219.84 seconds
Started Jul 15 06:54:22 PM PDT 24
Finished Jul 15 06:58:02 PM PDT 24
Peak memory 1409620 kb
Host smart-ce5d4ef9-ae8b-4d2e-9bcc-33d1d4dbcacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345313187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.345313187
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3296859202
Short name T1268
Test name
Test status
Simulation time 2686750130 ps
CPU time 11.83 seconds
Started Jul 15 06:54:23 PM PDT 24
Finished Jul 15 06:54:36 PM PDT 24
Peak memory 221724 kb
Host smart-28f53645-5f65-41a1-99b6-306215885542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296859202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3296859202
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1764812831
Short name T1200
Test name
Test status
Simulation time 1330127786 ps
CPU time 3.95 seconds
Started Jul 15 06:54:38 PM PDT 24
Finished Jul 15 06:54:42 PM PDT 24
Peak memory 217108 kb
Host smart-b1fd4381-4ea6-4a27-a342-c6bdac1e567a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764812831 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1764812831
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3053382629
Short name T1499
Test name
Test status
Simulation time 1953075825 ps
CPU time 1.12 seconds
Started Jul 15 06:54:36 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 205424 kb
Host smart-c4782097-88f4-4288-87ce-3b79103e67d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053382629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3053382629
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3506251981
Short name T531
Test name
Test status
Simulation time 220737035 ps
CPU time 1.46 seconds
Started Jul 15 06:54:30 PM PDT 24
Finished Jul 15 06:54:32 PM PDT 24
Peak memory 205752 kb
Host smart-fd7f117a-2502-48b2-958f-c34902cb2b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506251981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3506251981
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.3274368282
Short name T1052
Test name
Test status
Simulation time 2930164926 ps
CPU time 3.34 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 205712 kb
Host smart-dec868be-07ad-4392-b985-76d827df30d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274368282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.3274368282
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2042976341
Short name T1552
Test name
Test status
Simulation time 649665146 ps
CPU time 1.62 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 205436 kb
Host smart-90aa5b7f-9510-4ebb-bfe0-850ea7ec65e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042976341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2042976341
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3637897080
Short name T313
Test name
Test status
Simulation time 2231076561 ps
CPU time 8.21 seconds
Started Jul 15 06:54:37 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 213864 kb
Host smart-48b15c92-325c-4c0e-a8e2-e3a365d6cd15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637897080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3637897080
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1077425255
Short name T746
Test name
Test status
Simulation time 15586617412 ps
CPU time 340.06 seconds
Started Jul 15 06:54:33 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 3765004 kb
Host smart-1fc6f34c-0b7b-4be6-8f20-e23503980bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077425255 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1077425255
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.4242429617
Short name T571
Test name
Test status
Simulation time 1874400268 ps
CPU time 2.87 seconds
Started Jul 15 06:54:34 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 213884 kb
Host smart-16cee43f-9e5c-431a-8517-1315de263382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242429617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.4242429617
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.2494987709
Short name T1186
Test name
Test status
Simulation time 2011973651 ps
CPU time 2.8 seconds
Started Jul 15 06:54:33 PM PDT 24
Finished Jul 15 06:54:36 PM PDT 24
Peak memory 205620 kb
Host smart-dfee220f-d079-487f-8914-501acc15fe0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494987709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.2494987709
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_txstretch.1363441792
Short name T661
Test name
Test status
Simulation time 132292119 ps
CPU time 1.47 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 222504 kb
Host smart-1ecb9812-1b35-4387-b934-7d63f4a2506a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363441792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_nack_txstretch.1363441792
Directory /workspace/17.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3103869476
Short name T1596
Test name
Test status
Simulation time 1850423275 ps
CPU time 7.31 seconds
Started Jul 15 06:54:29 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 213880 kb
Host smart-4073305d-1884-4e92-aa1d-485c790413c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103869476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3103869476
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.2533045638
Short name T1236
Test name
Test status
Simulation time 2049523112 ps
CPU time 2.39 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:54:38 PM PDT 24
Peak memory 205448 kb
Host smart-5a5e7c68-a39c-4914-9e51-3f5a5bce541e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533045638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.2533045638
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2925336963
Short name T1319
Test name
Test status
Simulation time 5921716348 ps
CPU time 19.68 seconds
Started Jul 15 06:54:29 PM PDT 24
Finished Jul 15 06:54:49 PM PDT 24
Peak memory 213904 kb
Host smart-e22c9178-890b-447a-956b-edaef3de236d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925336963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2925336963
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.3086475697
Short name T1312
Test name
Test status
Simulation time 27292324013 ps
CPU time 46.01 seconds
Started Jul 15 06:54:28 PM PDT 24
Finished Jul 15 06:55:14 PM PDT 24
Peak memory 647872 kb
Host smart-299e777f-8903-4d45-9fa4-a5c96542a7e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086475697 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.3086475697
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2912907672
Short name T611
Test name
Test status
Simulation time 3392393494 ps
CPU time 31.41 seconds
Started Jul 15 06:54:29 PM PDT 24
Finished Jul 15 06:55:01 PM PDT 24
Peak memory 213904 kb
Host smart-b94507ff-6088-4ef8-b26b-c552931e36a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912907672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2912907672
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.527053203
Short name T1502
Test name
Test status
Simulation time 23956955716 ps
CPU time 7.12 seconds
Started Jul 15 06:54:27 PM PDT 24
Finished Jul 15 06:54:35 PM PDT 24
Peak memory 213916 kb
Host smart-1adaa24d-8f7a-47d5-9320-b7b038109af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527053203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.527053203
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2595077113
Short name T1381
Test name
Test status
Simulation time 1788167135 ps
CPU time 15.99 seconds
Started Jul 15 06:54:27 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 281300 kb
Host smart-daf74de1-8832-40e6-8a29-0bdeae8ae84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595077113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2595077113
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3016017164
Short name T1466
Test name
Test status
Simulation time 943413586 ps
CPU time 5.92 seconds
Started Jul 15 06:54:27 PM PDT 24
Finished Jul 15 06:54:34 PM PDT 24
Peak memory 221984 kb
Host smart-a1f3f7ef-717c-4d69-81f2-0cb988a29fcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016017164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3016017164
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.720956381
Short name T546
Test name
Test status
Simulation time 582475346 ps
CPU time 6.22 seconds
Started Jul 15 06:54:37 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 221060 kb
Host smart-a6a85ff4-5462-486e-ab42-807d6042f9ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720956381 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.720956381
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2240637289
Short name T1179
Test name
Test status
Simulation time 19953877 ps
CPU time 0.65 seconds
Started Jul 15 06:54:45 PM PDT 24
Finished Jul 15 06:54:46 PM PDT 24
Peak memory 204808 kb
Host smart-e2d200eb-daf9-495d-877f-823f48e32c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240637289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2240637289
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.4292854390
Short name T1226
Test name
Test status
Simulation time 121535973 ps
CPU time 1.85 seconds
Started Jul 15 06:54:42 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 213788 kb
Host smart-cebffa1f-3312-4865-b712-7a3f41887b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292854390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.4292854390
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1756417723
Short name T789
Test name
Test status
Simulation time 851098377 ps
CPU time 9.28 seconds
Started Jul 15 06:54:33 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 288756 kb
Host smart-d13b93a9-0630-451a-898f-bbd9b1ec4257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756417723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1756417723
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3707579400
Short name T1178
Test name
Test status
Simulation time 12390306698 ps
CPU time 112.33 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:56:28 PM PDT 24
Peak memory 480592 kb
Host smart-4fa7db7b-7dcd-4735-b7e3-9479844c22ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707579400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3707579400
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2267905210
Short name T1622
Test name
Test status
Simulation time 2035574269 ps
CPU time 144.79 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:57:00 PM PDT 24
Peak memory 673644 kb
Host smart-fcc49b6d-50e0-4e5b-b316-d78e5221748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267905210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2267905210
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.908878078
Short name T252
Test name
Test status
Simulation time 92346449 ps
CPU time 1.01 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 205264 kb
Host smart-c740e222-bb4f-4aae-b2c1-b7192a5de5dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908878078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.908878078
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2547216317
Short name T1241
Test name
Test status
Simulation time 180178674 ps
CPU time 3.76 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 205496 kb
Host smart-259a843e-a910-4e2a-9dd9-a774f0074399
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547216317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2547216317
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3626244599
Short name T839
Test name
Test status
Simulation time 8833410610 ps
CPU time 336.44 seconds
Started Jul 15 06:54:35 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 1300264 kb
Host smart-c7ec93b0-4cd8-4a9d-9c3e-4a8291d3296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626244599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3626244599
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3962620992
Short name T1589
Test name
Test status
Simulation time 488798303 ps
CPU time 7.41 seconds
Started Jul 15 06:54:41 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 205508 kb
Host smart-ecca3f51-3339-467e-ac1f-bd77d89dc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962620992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3962620992
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_perf.264438535
Short name T46
Test name
Test status
Simulation time 29576627034 ps
CPU time 64.08 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:55:48 PM PDT 24
Peak memory 733888 kb
Host smart-2572f58b-2981-4cd8-8f75-453bfd6442e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264438535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.264438535
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.3325170765
Short name T122
Test name
Test status
Simulation time 160019754 ps
CPU time 1.46 seconds
Started Jul 15 06:54:41 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 213592 kb
Host smart-7bcd3262-ff3e-445b-8249-2092b1f41e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325170765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.3325170765
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3429044462
Short name T1185
Test name
Test status
Simulation time 11256013214 ps
CPU time 37.77 seconds
Started Jul 15 06:54:37 PM PDT 24
Finished Jul 15 06:55:15 PM PDT 24
Peak memory 464236 kb
Host smart-fc8fa0a6-3f6c-487b-97e6-4761d0afdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429044462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3429044462
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2909633111
Short name T286
Test name
Test status
Simulation time 14468898197 ps
CPU time 416.06 seconds
Started Jul 15 06:54:41 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 1722220 kb
Host smart-1b953bad-3d69-4cf7-b9ab-d37e51fbe96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909633111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2909633111
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.905533403
Short name T898
Test name
Test status
Simulation time 511971505 ps
CPU time 21.71 seconds
Started Jul 15 06:54:42 PM PDT 24
Finished Jul 15 06:55:04 PM PDT 24
Peak memory 213752 kb
Host smart-a5598fbd-4c30-463a-952b-de9e611c7b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905533403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.905533403
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3833092587
Short name T69
Test name
Test status
Simulation time 1136387972 ps
CPU time 5.86 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 219652 kb
Host smart-b72c876d-102b-4c40-a0a8-791b06f07ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833092587 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3833092587
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.685003346
Short name T524
Test name
Test status
Simulation time 267687584 ps
CPU time 1.05 seconds
Started Jul 15 06:54:42 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 205388 kb
Host smart-d56111b1-2441-4cef-b11f-d47fe0ee1a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685003346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.685003346
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.4008441664
Short name T1377
Test name
Test status
Simulation time 284124930 ps
CPU time 1.94 seconds
Started Jul 15 06:54:41 PM PDT 24
Finished Jul 15 06:54:43 PM PDT 24
Peak memory 208468 kb
Host smart-76541101-af95-459c-8aa0-df11f6803afd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008441664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.4008441664
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.3022452295
Short name T1698
Test name
Test status
Simulation time 1729816651 ps
CPU time 2.23 seconds
Started Jul 15 06:54:42 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 205588 kb
Host smart-b6c10afb-71b8-449f-b0df-4474bd466d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022452295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.3022452295
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.301481666
Short name T1704
Test name
Test status
Simulation time 328695552 ps
CPU time 1.26 seconds
Started Jul 15 06:54:44 PM PDT 24
Finished Jul 15 06:54:46 PM PDT 24
Peak memory 205440 kb
Host smart-ae9155d9-cd5c-41ec-83d7-334109516f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301481666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.301481666
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.4031916909
Short name T784
Test name
Test status
Simulation time 409750563 ps
CPU time 2.83 seconds
Started Jul 15 06:54:42 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 213820 kb
Host smart-434cf96d-6479-446d-87ad-ec84e15ed763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031916909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.4031916909
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.521880322
Short name T762
Test name
Test status
Simulation time 4741927762 ps
CPU time 5.13 seconds
Started Jul 15 06:54:40 PM PDT 24
Finished Jul 15 06:54:45 PM PDT 24
Peak memory 222088 kb
Host smart-50883233-6ba1-4445-bbb3-bb98ec865bd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521880322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.521880322
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.369144732
Short name T1064
Test name
Test status
Simulation time 14936679220 ps
CPU time 32.68 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:55:16 PM PDT 24
Peak memory 865084 kb
Host smart-ea5273b6-ad38-4ae1-88fa-4b4ef7f2767e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369144732 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.369144732
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.2223074176
Short name T1258
Test name
Test status
Simulation time 2346336697 ps
CPU time 2.69 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 213904 kb
Host smart-58d20297-5795-4143-86f1-0dc16d977bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223074176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.2223074176
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.3314602790
Short name T66
Test name
Test status
Simulation time 530752635 ps
CPU time 2.38 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 205584 kb
Host smart-4ef78606-cda6-4e4e-8d6c-5be90e938eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314602790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.3314602790
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3989682852
Short name T77
Test name
Test status
Simulation time 1874774916 ps
CPU time 6.87 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 217068 kb
Host smart-0dd8d39c-b958-481b-abc2-a55c5bcc217c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989682852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3989682852
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.1524608954
Short name T328
Test name
Test status
Simulation time 2226094126 ps
CPU time 2.43 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 205444 kb
Host smart-140dea6d-8548-4edd-a99e-284d4ef30875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524608954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.1524608954
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.927633294
Short name T1570
Test name
Test status
Simulation time 4909338319 ps
CPU time 15.02 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 213696 kb
Host smart-21bf16b5-d365-4e77-ae8a-4c3cb1b1cd81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927633294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.927633294
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.4114653111
Short name T440
Test name
Test status
Simulation time 19316116680 ps
CPU time 213.69 seconds
Started Jul 15 06:54:41 PM PDT 24
Finished Jul 15 06:58:15 PM PDT 24
Peak memory 1246436 kb
Host smart-b3933b2c-b9dc-4057-afef-ccbb06c3a24a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114653111 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.4114653111
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.1477008595
Short name T1639
Test name
Test status
Simulation time 2023965536 ps
CPU time 85.16 seconds
Started Jul 15 06:54:43 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 218868 kb
Host smart-b329a523-1297-4a7e-9518-4c168aa03cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477008595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.1477008595
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1070970488
Short name T1119
Test name
Test status
Simulation time 36479756122 ps
CPU time 158.65 seconds
Started Jul 15 06:54:39 PM PDT 24
Finished Jul 15 06:57:18 PM PDT 24
Peak memory 2130568 kb
Host smart-58781725-26e1-4ad5-b22f-fd710062b36a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070970488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1070970488
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.102443802
Short name T342
Test name
Test status
Simulation time 409449851 ps
CPU time 2.84 seconds
Started Jul 15 06:54:44 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 218608 kb
Host smart-0269b383-6be8-4c05-8126-f50a09d11a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102443802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t
arget_stretch.102443802
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2388615264
Short name T1040
Test name
Test status
Simulation time 4489378659 ps
CPU time 6.6 seconds
Started Jul 15 06:54:40 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 213828 kb
Host smart-7051dbfe-3eac-443d-b9be-b486e05568a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388615264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2388615264
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2225822969
Short name T1259
Test name
Test status
Simulation time 24958743 ps
CPU time 0.64 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:52 PM PDT 24
Peak memory 204828 kb
Host smart-eb2e76e1-18de-4f50-9e02-601835e96ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225822969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2225822969
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.456858134
Short name T1539
Test name
Test status
Simulation time 649595631 ps
CPU time 2.41 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:54:50 PM PDT 24
Peak memory 205524 kb
Host smart-3f744f9e-8aee-4dec-b2b3-d969cf836def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456858134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.456858134
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.672345005
Short name T846
Test name
Test status
Simulation time 843596028 ps
CPU time 6.85 seconds
Started Jul 15 06:54:44 PM PDT 24
Finished Jul 15 06:54:51 PM PDT 24
Peak memory 257212 kb
Host smart-9b2d773c-4f56-456c-a759-606325d184bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672345005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.672345005
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.570483286
Short name T31
Test name
Test status
Simulation time 6457207769 ps
CPU time 253.45 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:59:01 PM PDT 24
Peak memory 911788 kb
Host smart-dcd5be67-775e-4c0f-a19a-33f6d0a721bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570483286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.570483286
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.4909084
Short name T1308
Test name
Test status
Simulation time 1323943629 ps
CPU time 35.69 seconds
Started Jul 15 06:54:47 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 499328 kb
Host smart-229b16fc-1bb9-4bd5-b789-277105264bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4909084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.4909084
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2336444193
Short name T1175
Test name
Test status
Simulation time 128424404 ps
CPU time 1.17 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 205232 kb
Host smart-4a024f01-df93-47b2-ab61-d153dd41764a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336444193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2336444193
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3107059802
Short name T573
Test name
Test status
Simulation time 1369730917 ps
CPU time 11.98 seconds
Started Jul 15 06:54:48 PM PDT 24
Finished Jul 15 06:55:01 PM PDT 24
Peak memory 205564 kb
Host smart-8ec230a6-9fe6-4154-b479-d34ff8fb17fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107059802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3107059802
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2485681126
Short name T1149
Test name
Test status
Simulation time 2568749859 ps
CPU time 154.8 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 845912 kb
Host smart-7c86a0ba-38af-438d-b249-413358a1e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485681126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2485681126
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3802323106
Short name T261
Test name
Test status
Simulation time 516709296 ps
CPU time 6.77 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 205504 kb
Host smart-819d6970-9685-478c-9593-71e4885f42f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802323106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3802323106
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.311955468
Short name T12
Test name
Test status
Simulation time 165500003 ps
CPU time 1.24 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:54:53 PM PDT 24
Peak memory 213708 kb
Host smart-55e61af4-9afa-4b06-b275-0ff8e09c628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311955468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.311955468
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.741670606
Short name T702
Test name
Test status
Simulation time 47837911 ps
CPU time 0.68 seconds
Started Jul 15 06:54:47 PM PDT 24
Finished Jul 15 06:54:49 PM PDT 24
Peak memory 205212 kb
Host smart-09410306-dce1-4ede-98fe-ccf9450cda71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741670606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.741670606
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1187517553
Short name T596
Test name
Test status
Simulation time 12725371745 ps
CPU time 150.41 seconds
Started Jul 15 06:54:48 PM PDT 24
Finished Jul 15 06:57:19 PM PDT 24
Peak memory 577540 kb
Host smart-0253d054-a4e7-492a-8862-c00f6aced814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187517553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1187517553
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.3373525737
Short name T954
Test name
Test status
Simulation time 2340922550 ps
CPU time 140.41 seconds
Started Jul 15 06:54:45 PM PDT 24
Finished Jul 15 06:57:06 PM PDT 24
Peak memory 748128 kb
Host smart-166f1091-e1e7-48f6-be9b-d5efae5603db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373525737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3373525737
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3366175993
Short name T396
Test name
Test status
Simulation time 1873403083 ps
CPU time 34.1 seconds
Started Jul 15 06:54:46 PM PDT 24
Finished Jul 15 06:55:21 PM PDT 24
Peak memory 426468 kb
Host smart-b23f3052-261e-4633-998c-6f77d093f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366175993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3366175993
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1456635581
Short name T1475
Test name
Test status
Simulation time 34158891354 ps
CPU time 274.64 seconds
Started Jul 15 06:54:47 PM PDT 24
Finished Jul 15 06:59:22 PM PDT 24
Peak memory 1056124 kb
Host smart-d8dc9455-0fbb-4e50-ab28-dc9167962fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456635581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1456635581
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2684631132
Short name T564
Test name
Test status
Simulation time 882880790 ps
CPU time 13.57 seconds
Started Jul 15 06:54:45 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 221924 kb
Host smart-c064f3aa-3281-4425-a711-687c80582290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684631132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2684631132
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3972081939
Short name T625
Test name
Test status
Simulation time 7954957327 ps
CPU time 3.25 seconds
Started Jul 15 06:54:50 PM PDT 24
Finished Jul 15 06:54:54 PM PDT 24
Peak memory 214020 kb
Host smart-bf523c10-c89c-4685-8d41-ec118cd6c3d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972081939 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3972081939
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.442858710
Short name T992
Test name
Test status
Simulation time 152693839 ps
CPU time 0.98 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:53 PM PDT 24
Peak memory 205444 kb
Host smart-f8755a97-b24b-43ca-8615-8008ca2e6d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442858710 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.442858710
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1957569224
Short name T668
Test name
Test status
Simulation time 189435582 ps
CPU time 1.21 seconds
Started Jul 15 06:54:50 PM PDT 24
Finished Jul 15 06:54:51 PM PDT 24
Peak memory 205644 kb
Host smart-ce908de2-4465-4010-bb03-65e74f6214f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957569224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1957569224
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.2038923835
Short name T1559
Test name
Test status
Simulation time 1659884841 ps
CPU time 2.15 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:54:54 PM PDT 24
Peak memory 205480 kb
Host smart-468d01f2-2335-42af-a83e-1fc77ac21b6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038923835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.2038923835
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1237912660
Short name T182
Test name
Test status
Simulation time 259346955 ps
CPU time 1.42 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:54 PM PDT 24
Peak memory 205388 kb
Host smart-15dad86c-3fef-4fe2-93e7-2022962c24aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237912660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1237912660
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.851111636
Short name T861
Test name
Test status
Simulation time 1463158720 ps
CPU time 2.85 seconds
Started Jul 15 06:54:54 PM PDT 24
Finished Jul 15 06:54:57 PM PDT 24
Peak memory 213880 kb
Host smart-43c5d40a-9206-494f-b785-82c264931273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851111636 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.851111636
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.709121972
Short name T490
Test name
Test status
Simulation time 20286107828 ps
CPU time 6.57 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:58 PM PDT 24
Peak memory 231136 kb
Host smart-5002d139-ab7d-464a-85f8-047308e69592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709121972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.709121972
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.4188650375
Short name T1599
Test name
Test status
Simulation time 479313881 ps
CPU time 2.58 seconds
Started Jul 15 06:54:53 PM PDT 24
Finished Jul 15 06:54:56 PM PDT 24
Peak memory 205604 kb
Host smart-e8331054-5a60-44ba-8cef-840592ba075c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188650375 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.4188650375
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.2648964771
Short name T808
Test name
Test status
Simulation time 524773562 ps
CPU time 2.92 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:54:56 PM PDT 24
Peak memory 213880 kb
Host smart-b75ed2c5-cf20-4040-a2ee-8084c29792c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648964771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.2648964771
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.2922289287
Short name T1290
Test name
Test status
Simulation time 1191945386 ps
CPU time 2.47 seconds
Started Jul 15 06:54:56 PM PDT 24
Finished Jul 15 06:54:58 PM PDT 24
Peak memory 205580 kb
Host smart-331eb045-83f1-4f1f-9c25-d764d78b2b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922289287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.2922289287
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.2859566195
Short name T1457
Test name
Test status
Simulation time 821942175 ps
CPU time 3.3 seconds
Started Jul 15 06:54:50 PM PDT 24
Finished Jul 15 06:54:54 PM PDT 24
Peak memory 214312 kb
Host smart-68770063-2dcc-4883-a4a8-d767340f006f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859566195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.2859566195
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.3949412591
Short name T1389
Test name
Test status
Simulation time 726048667 ps
CPU time 2.17 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:54:55 PM PDT 24
Peak memory 205476 kb
Host smart-e279f83c-5d60-4cba-ad2c-08390b66111f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949412591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.3949412591
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.21054729
Short name T1418
Test name
Test status
Simulation time 2642610830 ps
CPU time 7.66 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 213912 kb
Host smart-cd63fd09-ea4f-4634-92e8-1a0ef1844c76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21054729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_targ
et_smoke.21054729
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2857585572
Short name T766
Test name
Test status
Simulation time 1028364835 ps
CPU time 10.24 seconds
Started Jul 15 06:54:50 PM PDT 24
Finished Jul 15 06:55:01 PM PDT 24
Peak memory 205664 kb
Host smart-06103c0a-0c40-4b35-ab85-2758d780a524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857585572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2857585572
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2151232286
Short name T1489
Test name
Test status
Simulation time 15635902240 ps
CPU time 28.34 seconds
Started Jul 15 06:54:52 PM PDT 24
Finished Jul 15 06:55:21 PM PDT 24
Peak memory 205672 kb
Host smart-820fe312-1e35-4c27-982e-818916ff310c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151232286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2151232286
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2615074584
Short name T374
Test name
Test status
Simulation time 1601128150 ps
CPU time 73.74 seconds
Started Jul 15 06:54:53 PM PDT 24
Finished Jul 15 06:56:07 PM PDT 24
Peak memory 549656 kb
Host smart-11411b77-da68-4cc9-bee3-8a23b9b3b057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615074584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2615074584
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2160192233
Short name T277
Test name
Test status
Simulation time 6881955257 ps
CPU time 7.31 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 213892 kb
Host smart-4144252a-6fa6-4305-afaa-4772dd8680b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160192233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2160192233
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.1912675395
Short name T804
Test name
Test status
Simulation time 213360238 ps
CPU time 3.08 seconds
Started Jul 15 06:54:51 PM PDT 24
Finished Jul 15 06:54:55 PM PDT 24
Peak memory 205592 kb
Host smart-ffd031e8-3c0b-4186-ad30-edcb3da7a04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912675395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1912675395
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.959229902
Short name T560
Test name
Test status
Simulation time 48055351 ps
CPU time 0.64 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:51:53 PM PDT 24
Peak memory 204872 kb
Host smart-4288d88c-e3f1-4146-b73f-a098145f4cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959229902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.959229902
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.541129618
Short name T566
Test name
Test status
Simulation time 993814883 ps
CPU time 5.81 seconds
Started Jul 15 06:51:34 PM PDT 24
Finished Jul 15 06:51:41 PM PDT 24
Peak memory 213696 kb
Host smart-13328808-2f74-4da1-aba5-37fd7a841c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541129618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.541129618
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2655823002
Short name T783
Test name
Test status
Simulation time 1378736788 ps
CPU time 15.78 seconds
Started Jul 15 06:51:30 PM PDT 24
Finished Jul 15 06:51:46 PM PDT 24
Peak memory 256080 kb
Host smart-f25cd0cb-85e4-461c-b7a7-4cb3ea6d708a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655823002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2655823002
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2598837179
Short name T1222
Test name
Test status
Simulation time 3443685170 ps
CPU time 105.01 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:53:17 PM PDT 24
Peak memory 536116 kb
Host smart-7801d3d1-57fe-4a9d-808a-2a575d628921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598837179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2598837179
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1116122231
Short name T1265
Test name
Test status
Simulation time 4945919794 ps
CPU time 179.66 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:54:33 PM PDT 24
Peak memory 795948 kb
Host smart-1cb32235-ccac-4142-8498-46181ff40c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116122231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1116122231
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.152217381
Short name T1386
Test name
Test status
Simulation time 188723380 ps
CPU time 0.98 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:33 PM PDT 24
Peak memory 205260 kb
Host smart-95cd073c-6b83-4836-b15d-247639d15daa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152217381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.152217381
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1720150387
Short name T605
Test name
Test status
Simulation time 521977768 ps
CPU time 7.18 seconds
Started Jul 15 06:51:30 PM PDT 24
Finished Jul 15 06:51:38 PM PDT 24
Peak memory 226476 kb
Host smart-c1422496-973d-441e-b638-de9d4ddf09ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720150387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1720150387
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3321854379
Short name T115
Test name
Test status
Simulation time 5415500900 ps
CPU time 61.25 seconds
Started Jul 15 06:51:29 PM PDT 24
Finished Jul 15 06:52:30 PM PDT 24
Peak memory 830444 kb
Host smart-6cff1228-f5b4-4eb7-97ac-1417492e5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321854379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3321854379
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2020277127
Short name T257
Test name
Test status
Simulation time 2052422341 ps
CPU time 6.12 seconds
Started Jul 15 06:51:43 PM PDT 24
Finished Jul 15 06:51:49 PM PDT 24
Peak memory 205484 kb
Host smart-d841d7cf-0ed1-4495-b9a6-10ff49eae4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020277127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2020277127
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.1105187736
Short name T966
Test name
Test status
Simulation time 17790566 ps
CPU time 0.67 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:33 PM PDT 24
Peak memory 205244 kb
Host smart-db212669-88da-4e38-9719-26aa07081c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105187736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1105187736
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.231320685
Short name T886
Test name
Test status
Simulation time 600303394 ps
CPU time 7.5 seconds
Started Jul 15 06:51:31 PM PDT 24
Finished Jul 15 06:51:39 PM PDT 24
Peak memory 205460 kb
Host smart-1e86221b-9d02-4dde-bfcc-dea3dd9a2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231320685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.231320685
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4057567051
Short name T538
Test name
Test status
Simulation time 1131169727 ps
CPU time 19.22 seconds
Started Jul 15 06:51:32 PM PDT 24
Finished Jul 15 06:51:52 PM PDT 24
Peak memory 233824 kb
Host smart-306002fb-6ff5-4776-b6cf-1475d2a026b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057567051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4057567051
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3664305253
Short name T1408
Test name
Test status
Simulation time 4755279703 ps
CPU time 9.85 seconds
Started Jul 15 06:51:30 PM PDT 24
Finished Jul 15 06:51:40 PM PDT 24
Peak memory 213784 kb
Host smart-a5104453-c9dd-4285-a24e-d8be974b0fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664305253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3664305253
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2315673199
Short name T192
Test name
Test status
Simulation time 56267151 ps
CPU time 0.89 seconds
Started Jul 15 06:51:50 PM PDT 24
Finished Jul 15 06:51:51 PM PDT 24
Peak memory 223820 kb
Host smart-d23b24a2-6d77-4f75-925f-b4402a55274c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315673199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2315673199
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.659720352
Short name T1129
Test name
Test status
Simulation time 2061990500 ps
CPU time 5.22 seconds
Started Jul 15 06:51:46 PM PDT 24
Finished Jul 15 06:51:52 PM PDT 24
Peak memory 219852 kb
Host smart-ab581fa3-23a2-428d-a20f-e9a7b2816254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659720352 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.659720352
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3802900764
Short name T1533
Test name
Test status
Simulation time 806955139 ps
CPU time 1.15 seconds
Started Jul 15 06:51:39 PM PDT 24
Finished Jul 15 06:51:41 PM PDT 24
Peak memory 205392 kb
Host smart-8d1bc5d2-9093-450f-a8c7-db8761db4537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802900764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3802900764
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3117626102
Short name T926
Test name
Test status
Simulation time 272511608 ps
CPU time 1.67 seconds
Started Jul 15 06:51:40 PM PDT 24
Finished Jul 15 06:51:42 PM PDT 24
Peak memory 207748 kb
Host smart-eb593994-2a2e-45fa-a799-fd1c08154605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117626102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3117626102
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2337251881
Short name T1578
Test name
Test status
Simulation time 1585149096 ps
CPU time 2.78 seconds
Started Jul 15 06:51:44 PM PDT 24
Finished Jul 15 06:51:47 PM PDT 24
Peak memory 205608 kb
Host smart-751abfa5-3caf-4852-8464-42ce82a2fe52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337251881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2337251881
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3700741183
Short name T397
Test name
Test status
Simulation time 349399749 ps
CPU time 1.09 seconds
Started Jul 15 06:51:46 PM PDT 24
Finished Jul 15 06:51:47 PM PDT 24
Peak memory 205444 kb
Host smart-85fd91ab-15a3-46d7-b39b-ffb4b844825d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700741183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3700741183
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.341674290
Short name T438
Test name
Test status
Simulation time 5808373541 ps
CPU time 4.01 seconds
Started Jul 15 06:51:38 PM PDT 24
Finished Jul 15 06:51:43 PM PDT 24
Peak memory 222068 kb
Host smart-59de829d-f70b-4a07-9771-d728adedd036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341674290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.341674290
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.282096535
Short name T1061
Test name
Test status
Simulation time 2747328063 ps
CPU time 9.04 seconds
Started Jul 15 06:51:39 PM PDT 24
Finished Jul 15 06:51:48 PM PDT 24
Peak memory 468556 kb
Host smart-5624b54b-3b5f-4095-960c-fe881a82ec39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282096535 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.282096535
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.3958121970
Short name T448
Test name
Test status
Simulation time 954783508 ps
CPU time 2.81 seconds
Started Jul 15 06:51:43 PM PDT 24
Finished Jul 15 06:51:47 PM PDT 24
Peak memory 213840 kb
Host smart-5bef8ca2-0854-416f-ae02-e146098b6077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958121970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.3958121970
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.1840183094
Short name T660
Test name
Test status
Simulation time 504355474 ps
CPU time 2.64 seconds
Started Jul 15 06:51:45 PM PDT 24
Finished Jul 15 06:51:48 PM PDT 24
Peak memory 207068 kb
Host smart-f8139081-38d4-4ed0-b759-2a94f672ddf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840183094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.1840183094
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.4154578941
Short name T874
Test name
Test status
Simulation time 428456418 ps
CPU time 1.42 seconds
Started Jul 15 06:51:44 PM PDT 24
Finished Jul 15 06:51:45 PM PDT 24
Peak memory 222900 kb
Host smart-198a28f3-ab48-439b-ac27-96e6791a6f08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154578941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.4154578941
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2358506147
Short name T525
Test name
Test status
Simulation time 4069632807 ps
CPU time 5.2 seconds
Started Jul 15 06:51:39 PM PDT 24
Finished Jul 15 06:51:45 PM PDT 24
Peak memory 221964 kb
Host smart-502bd471-ba3c-4776-b72c-c665fbc786ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358506147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2358506147
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.2058106047
Short name T402
Test name
Test status
Simulation time 5074649297 ps
CPU time 2.17 seconds
Started Jul 15 06:51:45 PM PDT 24
Finished Jul 15 06:51:48 PM PDT 24
Peak memory 205516 kb
Host smart-bb0aee7e-f823-440c-82b7-3e93325d44f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058106047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.2058106047
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1484061370
Short name T643
Test name
Test status
Simulation time 7968977977 ps
CPU time 12.52 seconds
Started Jul 15 06:51:38 PM PDT 24
Finished Jul 15 06:51:51 PM PDT 24
Peak memory 213880 kb
Host smart-2099a6fd-e8e0-4042-b573-8764d8606c3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484061370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1484061370
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3960748839
Short name T1144
Test name
Test status
Simulation time 61292479979 ps
CPU time 193.89 seconds
Started Jul 15 06:51:43 PM PDT 24
Finished Jul 15 06:54:58 PM PDT 24
Peak memory 1574556 kb
Host smart-b403e276-4220-4547-a9be-06cecf4c329c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960748839 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3960748839
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.485847826
Short name T1446
Test name
Test status
Simulation time 1502968128 ps
CPU time 16.44 seconds
Started Jul 15 06:51:42 PM PDT 24
Finished Jul 15 06:51:59 PM PDT 24
Peak memory 205684 kb
Host smart-9aea4e89-d414-44f3-9b87-75a826ec19fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485847826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.485847826
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.79643302
Short name T1424
Test name
Test status
Simulation time 57391677980 ps
CPU time 120.43 seconds
Started Jul 15 06:51:38 PM PDT 24
Finished Jul 15 06:53:39 PM PDT 24
Peak memory 1365588 kb
Host smart-a3e2d9ce-6328-4071-930c-cf35ca8ef4d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79643302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stress_wr.79643302
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1423738735
Short name T1625
Test name
Test status
Simulation time 1123761401 ps
CPU time 15.23 seconds
Started Jul 15 06:51:37 PM PDT 24
Finished Jul 15 06:51:52 PM PDT 24
Peak memory 428972 kb
Host smart-a0cfdbd2-f820-4639-9f64-19cdd6a52221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423738735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1423738735
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1416854602
Short name T1524
Test name
Test status
Simulation time 10877629576 ps
CPU time 6.83 seconds
Started Jul 15 06:51:37 PM PDT 24
Finished Jul 15 06:51:45 PM PDT 24
Peak memory 221908 kb
Host smart-9862ecaa-e9f5-4d18-980f-4c4e77c9c8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416854602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1416854602
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.1660539676
Short name T786
Test name
Test status
Simulation time 942584814 ps
CPU time 10.81 seconds
Started Jul 15 06:51:45 PM PDT 24
Finished Jul 15 06:51:56 PM PDT 24
Peak memory 205592 kb
Host smart-eaa1999f-99c6-4901-80fb-d7461c60b6ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660539676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.1660539676
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.513674278
Short name T1348
Test name
Test status
Simulation time 30878036 ps
CPU time 0.61 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:55:03 PM PDT 24
Peak memory 204780 kb
Host smart-5f963c2f-759b-441d-bd16-4b357f55b4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513674278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.513674278
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.116018169
Short name T1215
Test name
Test status
Simulation time 285081186 ps
CPU time 2.02 seconds
Started Jul 15 06:54:57 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 213740 kb
Host smart-0385a904-85c1-400c-a8f9-4b4495ce187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116018169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.116018169
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2251393935
Short name T348
Test name
Test status
Simulation time 438388015 ps
CPU time 22.03 seconds
Started Jul 15 06:54:59 PM PDT 24
Finished Jul 15 06:55:22 PM PDT 24
Peak memory 291176 kb
Host smart-3ff3b7fa-4529-485f-a51b-5e5daf7ca007
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251393935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2251393935
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2674732527
Short name T341
Test name
Test status
Simulation time 13871285818 ps
CPU time 110.76 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:56:50 PM PDT 24
Peak memory 565752 kb
Host smart-ebf66df2-9554-467e-8efb-83fa3b199200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674732527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2674732527
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1453064915
Short name T40
Test name
Test status
Simulation time 2062912944 ps
CPU time 66.18 seconds
Started Jul 15 06:54:56 PM PDT 24
Finished Jul 15 06:56:03 PM PDT 24
Peak memory 644352 kb
Host smart-8e520e6f-b157-4d9b-8324-8a45614acb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453064915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1453064915
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3488401600
Short name T949
Test name
Test status
Simulation time 293330888 ps
CPU time 1.02 seconds
Started Jul 15 06:54:57 PM PDT 24
Finished Jul 15 06:54:59 PM PDT 24
Peak memory 205260 kb
Host smart-bdea79a0-0052-4f0d-a765-7211a7024582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488401600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3488401600
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2388255221
Short name T1196
Test name
Test status
Simulation time 1078087150 ps
CPU time 12.27 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:55:12 PM PDT 24
Peak memory 205532 kb
Host smart-13c628cd-ee69-40d7-be91-8317226d9f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388255221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2388255221
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.127373407
Short name T1363
Test name
Test status
Simulation time 2625931437 ps
CPU time 68.74 seconds
Started Jul 15 06:54:57 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 833412 kb
Host smart-60e3262b-e15f-4126-96f5-eb4940838dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127373407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.127373407
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3623402808
Short name T200
Test name
Test status
Simulation time 1689021684 ps
CPU time 7.09 seconds
Started Jul 15 06:55:00 PM PDT 24
Finished Jul 15 06:55:08 PM PDT 24
Peak memory 205544 kb
Host smart-aef6c6e7-4815-4867-8e2f-108f8f41098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623402808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3623402808
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_override.1353000760
Short name T1655
Test name
Test status
Simulation time 27116001 ps
CPU time 0.68 seconds
Started Jul 15 06:55:00 PM PDT 24
Finished Jul 15 06:55:01 PM PDT 24
Peak memory 205240 kb
Host smart-1922f1e9-2cba-4821-8479-57682a7141b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353000760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1353000760
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2503736663
Short name T1593
Test name
Test status
Simulation time 13405910896 ps
CPU time 153.07 seconds
Started Jul 15 06:54:59 PM PDT 24
Finished Jul 15 06:57:32 PM PDT 24
Peak memory 534020 kb
Host smart-6aa5fa09-aac9-4203-8e0b-00ddaad5775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503736663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2503736663
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.1546024397
Short name T1168
Test name
Test status
Simulation time 140700595 ps
CPU time 1.67 seconds
Started Jul 15 06:55:00 PM PDT 24
Finished Jul 15 06:55:02 PM PDT 24
Peak memory 225584 kb
Host smart-77396752-e6ac-4eba-8ce3-c970bfaea90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546024397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.1546024397
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.274419581
Short name T434
Test name
Test status
Simulation time 2611680616 ps
CPU time 23.6 seconds
Started Jul 15 06:54:50 PM PDT 24
Finished Jul 15 06:55:14 PM PDT 24
Peak memory 339592 kb
Host smart-5e8026a7-6f47-4c6a-a3fd-4c755eae5ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274419581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.274419581
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3282965107
Short name T1130
Test name
Test status
Simulation time 1494966397 ps
CPU time 12.14 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:55:11 PM PDT 24
Peak memory 230032 kb
Host smart-97aaa3d7-35a4-4026-8576-2cece9eec31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282965107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3282965107
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.501045360
Short name T760
Test name
Test status
Simulation time 3204156020 ps
CPU time 4.22 seconds
Started Jul 15 06:55:10 PM PDT 24
Finished Jul 15 06:55:15 PM PDT 24
Peak memory 214048 kb
Host smart-e51f7636-4946-4606-9748-dc68aa11155b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501045360 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.501045360
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3332253856
Short name T375
Test name
Test status
Simulation time 252060518 ps
CPU time 0.88 seconds
Started Jul 15 06:55:01 PM PDT 24
Finished Jul 15 06:55:02 PM PDT 24
Peak memory 205424 kb
Host smart-33cb34f2-9849-400a-a7d6-50614b103ec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332253856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3332253856
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2935346718
Short name T1487
Test name
Test status
Simulation time 178746432 ps
CPU time 0.92 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:55:00 PM PDT 24
Peak memory 205416 kb
Host smart-7f612499-086f-4c48-bb1f-95acc447e687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935346718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2935346718
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.1745053194
Short name T598
Test name
Test status
Simulation time 2797478800 ps
CPU time 3.49 seconds
Started Jul 15 06:55:03 PM PDT 24
Finished Jul 15 06:55:07 PM PDT 24
Peak memory 205680 kb
Host smart-a72b920b-27ab-4755-af83-493ef94f0bb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745053194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.1745053194
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3318819213
Short name T125
Test name
Test status
Simulation time 286231789 ps
CPU time 1.22 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:55:04 PM PDT 24
Peak memory 205432 kb
Host smart-b4305628-83db-42a9-8e45-f09f4350c818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318819213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3318819213
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2791710466
Short name T1480
Test name
Test status
Simulation time 777189661 ps
CPU time 1.09 seconds
Started Jul 15 06:55:06 PM PDT 24
Finished Jul 15 06:55:08 PM PDT 24
Peak memory 205508 kb
Host smart-0736553d-f5dd-4d19-a4cc-22e7e9179fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791710466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2791710466
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2806151759
Short name T1335
Test name
Test status
Simulation time 10109281448 ps
CPU time 7.85 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:55:06 PM PDT 24
Peak memory 222124 kb
Host smart-61519048-870e-4599-9311-a34cac4bcada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806151759 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2806151759
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3936659684
Short name T444
Test name
Test status
Simulation time 15567508822 ps
CPU time 328.91 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 3881732 kb
Host smart-3a7f3ff6-b5d4-4263-9fec-0adfa40313a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936659684 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3936659684
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.3898855987
Short name T543
Test name
Test status
Simulation time 1703533992 ps
CPU time 2.65 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:55:06 PM PDT 24
Peak memory 213848 kb
Host smart-f03f9709-048e-4a75-9b33-c1c1d5fd0525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898855987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.3898855987
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.2709992391
Short name T1000
Test name
Test status
Simulation time 558536163 ps
CPU time 2.78 seconds
Started Jul 15 06:55:06 PM PDT 24
Finished Jul 15 06:55:10 PM PDT 24
Peak memory 205680 kb
Host smart-816f80b9-c04d-4f46-8406-02895a9604b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709992391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.2709992391
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.4229202407
Short name T180
Test name
Test status
Simulation time 141102121 ps
CPU time 1.67 seconds
Started Jul 15 06:55:00 PM PDT 24
Finished Jul 15 06:55:02 PM PDT 24
Peak memory 222212 kb
Host smart-070670cc-6750-4630-ad6d-f62e37b60cf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229202407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.4229202407
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.963471715
Short name T1385
Test name
Test status
Simulation time 5073784372 ps
CPU time 8.45 seconds
Started Jul 15 06:54:57 PM PDT 24
Finished Jul 15 06:55:05 PM PDT 24
Peak memory 230104 kb
Host smart-c79e443f-fd38-43cf-bf18-2f12e4702557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963471715 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_perf.963471715
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.4163461454
Short name T1567
Test name
Test status
Simulation time 1890866948 ps
CPU time 2.37 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:55:05 PM PDT 24
Peak memory 205400 kb
Host smart-660d5655-3065-4fbe-9026-bb44f7e73727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163461454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.4163461454
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.868681847
Short name T855
Test name
Test status
Simulation time 858943508 ps
CPU time 25.17 seconds
Started Jul 15 06:54:58 PM PDT 24
Finished Jul 15 06:55:24 PM PDT 24
Peak memory 213908 kb
Host smart-8657657d-a6b4-40d2-819a-88ec6cce35dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868681847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.868681847
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.2081069096
Short name T1510
Test name
Test status
Simulation time 33078980749 ps
CPU time 321.3 seconds
Started Jul 15 06:55:01 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 1469304 kb
Host smart-712105a4-32b5-4db7-a32a-a875d9bd05d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081069096 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.2081069096
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1830206416
Short name T511
Test name
Test status
Simulation time 1040222279 ps
CPU time 17.12 seconds
Started Jul 15 06:54:57 PM PDT 24
Finished Jul 15 06:55:14 PM PDT 24
Peak memory 221796 kb
Host smart-fc270281-36a5-40c7-9526-8efd44be2a88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830206416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1830206416
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.496218884
Short name T1148
Test name
Test status
Simulation time 13658121922 ps
CPU time 6.73 seconds
Started Jul 15 06:54:59 PM PDT 24
Finished Jul 15 06:55:06 PM PDT 24
Peak memory 205636 kb
Host smart-3e94b6a6-8fc3-46d4-9f4d-9ff42b33c47a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496218884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.496218884
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2605294012
Short name T1497
Test name
Test status
Simulation time 5212385825 ps
CPU time 23.2 seconds
Started Jul 15 06:54:59 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 345148 kb
Host smart-702f296b-64be-4855-bfee-ae56b1ad47a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605294012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2605294012
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2851016550
Short name T412
Test name
Test status
Simulation time 1427373530 ps
CPU time 7.4 seconds
Started Jul 15 06:55:00 PM PDT 24
Finished Jul 15 06:55:07 PM PDT 24
Peak memory 222060 kb
Host smart-b12a2908-9ff8-4cc1-9d04-5987d9f4fe75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851016550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2851016550
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1639550450
Short name T1101
Test name
Test status
Simulation time 1167848972 ps
CPU time 13.49 seconds
Started Jul 15 06:55:06 PM PDT 24
Finished Jul 15 06:55:21 PM PDT 24
Peak memory 205656 kb
Host smart-5c4add72-a105-4507-a84b-82afed3341fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639550450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1639550450
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2576977002
Short name T460
Test name
Test status
Simulation time 18038383 ps
CPU time 0.58 seconds
Started Jul 15 06:55:11 PM PDT 24
Finished Jul 15 06:55:12 PM PDT 24
Peak memory 204520 kb
Host smart-e99af093-4021-472a-88c8-3f49ca4d0fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576977002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2576977002
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1866122001
Short name T426
Test name
Test status
Simulation time 1039505461 ps
CPU time 1.69 seconds
Started Jul 15 06:55:08 PM PDT 24
Finished Jul 15 06:55:10 PM PDT 24
Peak memory 213804 kb
Host smart-efcb37b3-3822-4872-b975-253fa6a159ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866122001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1866122001
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2546991363
Short name T1156
Test name
Test status
Simulation time 686404443 ps
CPU time 10.07 seconds
Started Jul 15 06:55:06 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 243284 kb
Host smart-76e291ce-2dda-4999-878e-1c01a30f3d62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546991363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2546991363
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1265364201
Short name T1685
Test name
Test status
Simulation time 7771418633 ps
CPU time 72.63 seconds
Started Jul 15 06:55:04 PM PDT 24
Finished Jul 15 06:56:17 PM PDT 24
Peak memory 629392 kb
Host smart-17a550fc-fc03-422c-8125-dc60cc02dca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265364201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1265364201
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.4115181964
Short name T1728
Test name
Test status
Simulation time 2623093339 ps
CPU time 91.91 seconds
Started Jul 15 06:55:01 PM PDT 24
Finished Jul 15 06:56:34 PM PDT 24
Peak memory 507360 kb
Host smart-606ff5b5-e69c-4465-bb2f-8db3cd44f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115181964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4115181964
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2327832609
Short name T985
Test name
Test status
Simulation time 712732953 ps
CPU time 1.28 seconds
Started Jul 15 06:55:10 PM PDT 24
Finished Jul 15 06:55:12 PM PDT 24
Peak memory 205236 kb
Host smart-25af5503-b5f6-4e50-94cd-be681eda9c6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327832609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2327832609
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.303092745
Short name T583
Test name
Test status
Simulation time 235365106 ps
CPU time 4.67 seconds
Started Jul 15 06:55:04 PM PDT 24
Finished Jul 15 06:55:09 PM PDT 24
Peak memory 205528 kb
Host smart-e91b35d4-2620-4036-abd3-0c866dd98f93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303092745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
303092745
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2612859241
Short name T1464
Test name
Test status
Simulation time 5081361293 ps
CPU time 383.31 seconds
Started Jul 15 06:55:05 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 1358700 kb
Host smart-66bc785b-29cc-4cc0-98e3-6a6861973b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612859241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2612859241
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_override.1175988765
Short name T147
Test name
Test status
Simulation time 30302823 ps
CPU time 0.7 seconds
Started Jul 15 06:55:03 PM PDT 24
Finished Jul 15 06:55:04 PM PDT 24
Peak memory 205176 kb
Host smart-9552eceb-dfaa-4f99-88c4-8a640ded34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175988765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1175988765
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2156169605
Short name T1286
Test name
Test status
Simulation time 49544046632 ps
CPU time 469.36 seconds
Started Jul 15 06:55:03 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 2058384 kb
Host smart-4db77f0d-392e-4661-a5d1-b410dc362bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156169605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2156169605
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.2463740431
Short name T769
Test name
Test status
Simulation time 77413320 ps
CPU time 1.63 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:55:04 PM PDT 24
Peak memory 205604 kb
Host smart-8c81ddd5-81e3-4254-b13a-73a26fed6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463740431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.2463740431
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2047574043
Short name T1455
Test name
Test status
Simulation time 2536596684 ps
CPU time 68.21 seconds
Started Jul 15 06:55:02 PM PDT 24
Finished Jul 15 06:56:11 PM PDT 24
Peak memory 331276 kb
Host smart-cccb62be-b2cb-4cbd-b91f-8950992e0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047574043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2047574043
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2293779447
Short name T287
Test name
Test status
Simulation time 2648396585 ps
CPU time 30.76 seconds
Started Jul 15 06:55:10 PM PDT 24
Finished Jul 15 06:55:41 PM PDT 24
Peak memory 213760 kb
Host smart-162e73c0-1890-4dee-886e-6e6d016d6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293779447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2293779447
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2119611139
Short name T553
Test name
Test status
Simulation time 1115916716 ps
CPU time 3.52 seconds
Started Jul 15 06:55:09 PM PDT 24
Finished Jul 15 06:55:13 PM PDT 24
Peak memory 216880 kb
Host smart-ec2612ad-8f79-4376-8cba-0a325c2e83a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119611139 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2119611139
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.407663645
Short name T792
Test name
Test status
Simulation time 207217873 ps
CPU time 1.37 seconds
Started Jul 15 06:55:07 PM PDT 24
Finished Jul 15 06:55:09 PM PDT 24
Peak memory 205568 kb
Host smart-304abec4-6879-4563-8990-bb882b60e56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407663645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.407663645
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.114617815
Short name T512
Test name
Test status
Simulation time 1822648075 ps
CPU time 2.7 seconds
Started Jul 15 06:55:15 PM PDT 24
Finished Jul 15 06:55:18 PM PDT 24
Peak memory 205600 kb
Host smart-3adc150c-90cf-4505-b874-1f34342338fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114617815 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.114617815
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1379116833
Short name T968
Test name
Test status
Simulation time 358593986 ps
CPU time 1.54 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:15 PM PDT 24
Peak memory 205460 kb
Host smart-2b91ed5d-4a06-402a-b593-a3b0b68ae7df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379116833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1379116833
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2422814393
Short name T866
Test name
Test status
Simulation time 299041978 ps
CPU time 2.52 seconds
Started Jul 15 06:55:11 PM PDT 24
Finished Jul 15 06:55:14 PM PDT 24
Peak memory 207292 kb
Host smart-4695d12d-8eb2-49d1-a746-95d07a91d406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422814393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2422814393
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1137722964
Short name T1668
Test name
Test status
Simulation time 1644036880 ps
CPU time 4.91 seconds
Started Jul 15 06:55:07 PM PDT 24
Finished Jul 15 06:55:12 PM PDT 24
Peak memory 221956 kb
Host smart-d47a641f-1768-4f85-aafe-994db3610fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137722964 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1137722964
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3996330676
Short name T1218
Test name
Test status
Simulation time 19752051272 ps
CPU time 142.49 seconds
Started Jul 15 06:55:08 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 1707952 kb
Host smart-ce2baab4-5187-41eb-8e7b-39af959a6d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996330676 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3996330676
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.2480948212
Short name T409
Test name
Test status
Simulation time 2334147846 ps
CPU time 2.99 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 213936 kb
Host smart-e78d5314-9e4a-446a-aeef-dd7f6f6167e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480948212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.2480948212
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.1668648583
Short name T429
Test name
Test status
Simulation time 520530984 ps
CPU time 2.92 seconds
Started Jul 15 06:55:12 PM PDT 24
Finished Jul 15 06:55:16 PM PDT 24
Peak memory 205640 kb
Host smart-84ed9c0e-b3f1-49ee-99e6-3123204cf607
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668648583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.1668648583
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.2344410681
Short name T1143
Test name
Test status
Simulation time 281612849 ps
CPU time 1.42 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:15 PM PDT 24
Peak memory 222344 kb
Host smart-af991129-524f-4ad5-a50e-e42b7f9d2c9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344410681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_nack_txstretch.2344410681
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.2342471611
Short name T756
Test name
Test status
Simulation time 2767625206 ps
CPU time 5.53 seconds
Started Jul 15 06:55:07 PM PDT 24
Finished Jul 15 06:55:13 PM PDT 24
Peak memory 222044 kb
Host smart-7424c704-7ad7-49de-894e-7c975b028e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342471611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.2342471611
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.3977957788
Short name T1103
Test name
Test status
Simulation time 1764873567 ps
CPU time 2.26 seconds
Started Jul 15 06:55:14 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 205444 kb
Host smart-ec57c40f-d1e2-44d1-99f7-a3417db22a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977957788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.3977957788
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.883352945
Short name T1028
Test name
Test status
Simulation time 831099622 ps
CPU time 10.53 seconds
Started Jul 15 06:55:07 PM PDT 24
Finished Jul 15 06:55:19 PM PDT 24
Peak memory 207744 kb
Host smart-5ddf1744-a6db-4b1c-bc37-6203f79ad22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883352945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.883352945
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.2163258485
Short name T1528
Test name
Test status
Simulation time 9822833353 ps
CPU time 52.97 seconds
Started Jul 15 06:55:09 PM PDT 24
Finished Jul 15 06:56:03 PM PDT 24
Peak memory 238500 kb
Host smart-704e563f-2b51-45b4-8392-d0b85e918994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163258485 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.2163258485
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.47515239
Short name T1072
Test name
Test status
Simulation time 3952226530 ps
CPU time 22.55 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:36 PM PDT 24
Peak memory 221964 kb
Host smart-89642cd9-c173-45d4-80ec-1fbcee67c494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47515239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_rd.47515239
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3185261627
Short name T1495
Test name
Test status
Simulation time 14724714738 ps
CPU time 21.57 seconds
Started Jul 15 06:55:10 PM PDT 24
Finished Jul 15 06:55:32 PM PDT 24
Peak memory 205736 kb
Host smart-b13ac731-5a2a-43b7-8b66-ce905cb9afde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185261627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3185261627
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1953584929
Short name T198
Test name
Test status
Simulation time 5867527080 ps
CPU time 9.96 seconds
Started Jul 15 06:55:06 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 305376 kb
Host smart-3becdfdb-f159-4260-8286-0660e18e778b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953584929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1953584929
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2853170945
Short name T764
Test name
Test status
Simulation time 1225015346 ps
CPU time 6.45 seconds
Started Jul 15 06:55:12 PM PDT 24
Finished Jul 15 06:55:19 PM PDT 24
Peak memory 221956 kb
Host smart-428ac5cb-3a2f-44f7-8384-cd9d7573282c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853170945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2853170945
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.925861621
Short name T1428
Test name
Test status
Simulation time 120833048 ps
CPU time 2.75 seconds
Started Jul 15 06:55:12 PM PDT 24
Finished Jul 15 06:55:15 PM PDT 24
Peak memory 205556 kb
Host smart-1349ddb0-ad51-4261-a10a-e18636b95d3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925861621 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.925861621
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1489838335
Short name T1703
Test name
Test status
Simulation time 17964351 ps
CPU time 0.65 seconds
Started Jul 15 06:55:22 PM PDT 24
Finished Jul 15 06:55:24 PM PDT 24
Peak memory 204768 kb
Host smart-581bdc50-6aae-43c4-9753-8830c9ee056b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489838335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1489838335
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3999069459
Short name T1452
Test name
Test status
Simulation time 64118029 ps
CPU time 1.48 seconds
Started Jul 15 06:55:28 PM PDT 24
Finished Jul 15 06:55:30 PM PDT 24
Peak memory 213772 kb
Host smart-a0254657-e4bb-4dbb-940a-18c26699df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999069459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3999069459
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.222914377
Short name T1563
Test name
Test status
Simulation time 2175870035 ps
CPU time 19.13 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:37 PM PDT 24
Peak memory 283988 kb
Host smart-5a7d67e3-3a6b-43c2-a625-ce575a303b53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222914377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.222914377
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2968507701
Short name T1419
Test name
Test status
Simulation time 5104397909 ps
CPU time 74.21 seconds
Started Jul 15 06:55:20 PM PDT 24
Finished Jul 15 06:56:35 PM PDT 24
Peak memory 486776 kb
Host smart-b35d57bc-7bc4-4db3-84f9-d05e2a102108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968507701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2968507701
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1598447344
Short name T1532
Test name
Test status
Simulation time 8327155385 ps
CPU time 64.53 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:56:18 PM PDT 24
Peak memory 728048 kb
Host smart-f8822c3d-406b-4c50-9e70-8340b500f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598447344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1598447344
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2541829487
Short name T1522
Test name
Test status
Simulation time 177746030 ps
CPU time 0.98 seconds
Started Jul 15 06:55:12 PM PDT 24
Finished Jul 15 06:55:13 PM PDT 24
Peak memory 205256 kb
Host smart-2c66b2cc-5703-472b-b678-5c95a8fc4ea3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541829487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2541829487
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1050432226
Short name T14
Test name
Test status
Simulation time 219130989 ps
CPU time 5.75 seconds
Started Jul 15 06:55:15 PM PDT 24
Finished Jul 15 06:55:21 PM PDT 24
Peak memory 248472 kb
Host smart-c5ba70ce-7ef9-4b2a-9f60-5eddd6431b7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050432226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1050432226
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3050231259
Short name T493
Test name
Test status
Simulation time 5385032769 ps
CPU time 172.62 seconds
Started Jul 15 06:55:15 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 878712 kb
Host smart-ac8d57a1-5883-4022-b725-6de5bf57a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050231259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3050231259
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.130582067
Short name T587
Test name
Test status
Simulation time 1154856415 ps
CPU time 6.83 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:55:37 PM PDT 24
Peak memory 205452 kb
Host smart-3ba4eada-0ce6-4564-a0c3-cc901bb2956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130582067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.130582067
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.928774529
Short name T1402
Test name
Test status
Simulation time 134638198 ps
CPU time 1.17 seconds
Started Jul 15 06:55:31 PM PDT 24
Finished Jul 15 06:55:33 PM PDT 24
Peak memory 213664 kb
Host smart-036a4965-8aa3-470c-8218-97fd47594b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928774529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.928774529
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.129887753
Short name T1191
Test name
Test status
Simulation time 56653990 ps
CPU time 0.7 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:14 PM PDT 24
Peak memory 205208 kb
Host smart-389a7597-1ebf-42a6-894b-0778fc02a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129887753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.129887753
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2020755243
Short name T1331
Test name
Test status
Simulation time 8696216572 ps
CPU time 42.44 seconds
Started Jul 15 06:55:19 PM PDT 24
Finished Jul 15 06:56:02 PM PDT 24
Peak memory 254884 kb
Host smart-247af651-9130-4ce2-9ee0-b8e5b14352bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020755243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2020755243
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.2956957307
Short name T1608
Test name
Test status
Simulation time 50974273 ps
CPU time 1.89 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:20 PM PDT 24
Peak memory 227212 kb
Host smart-4c77ec35-f221-44ad-bda7-2a43e1d5eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956957307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.2956957307
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2219635372
Short name T123
Test name
Test status
Simulation time 4917020569 ps
CPU time 25.15 seconds
Started Jul 15 06:55:13 PM PDT 24
Finished Jul 15 06:55:38 PM PDT 24
Peak memory 359360 kb
Host smart-687bcd9d-ff02-44f6-8fd2-496f387913c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219635372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2219635372
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2685085956
Short name T129
Test name
Test status
Simulation time 5935290053 ps
CPU time 155.06 seconds
Started Jul 15 06:55:21 PM PDT 24
Finished Jul 15 06:57:56 PM PDT 24
Peak memory 766860 kb
Host smart-c44e1363-45a7-4263-9259-bc5e84030da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685085956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2685085956
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2083785125
Short name T1136
Test name
Test status
Simulation time 3236560874 ps
CPU time 35.04 seconds
Started Jul 15 06:55:18 PM PDT 24
Finished Jul 15 06:55:53 PM PDT 24
Peak memory 213948 kb
Host smart-f2d2eb77-a5f9-497e-bfd6-4a58cf6a5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083785125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2083785125
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1919523601
Short name T459
Test name
Test status
Simulation time 3893134319 ps
CPU time 5.48 seconds
Started Jul 15 06:55:23 PM PDT 24
Finished Jul 15 06:55:29 PM PDT 24
Peak memory 222044 kb
Host smart-d8e08a17-e740-4ff0-8d5d-edbbddd745ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919523601 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1919523601
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2099452861
Short name T291
Test name
Test status
Simulation time 558055843 ps
CPU time 1.2 seconds
Started Jul 15 06:55:26 PM PDT 24
Finished Jul 15 06:55:28 PM PDT 24
Peak memory 205600 kb
Host smart-5d081045-d8ab-4857-9af7-d92024224f29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099452861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2099452861
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.923418967
Short name T994
Test name
Test status
Simulation time 157765419 ps
CPU time 0.93 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:55:27 PM PDT 24
Peak memory 205384 kb
Host smart-2aec6b63-e479-461d-ae3f-568c0e0773e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923418967 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.923418967
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.3748214459
Short name T1315
Test name
Test status
Simulation time 378613680 ps
CPU time 2.35 seconds
Started Jul 15 06:55:20 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 205532 kb
Host smart-83877c3b-a258-4c26-b794-b87cea24faf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748214459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.3748214459
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.486107511
Short name T489
Test name
Test status
Simulation time 1727813500 ps
CPU time 1.09 seconds
Started Jul 15 06:55:21 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 205468 kb
Host smart-fa4e29a1-aa43-4f47-828f-46bfbfd1e8db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486107511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.486107511
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3685577906
Short name T567
Test name
Test status
Simulation time 571528614 ps
CPU time 2.01 seconds
Started Jul 15 06:55:20 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 213764 kb
Host smart-a4702fe3-339b-41ce-949f-53e81c8283cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685577906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3685577906
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3121898765
Short name T630
Test name
Test status
Simulation time 3746583909 ps
CPU time 4.5 seconds
Started Jul 15 06:55:20 PM PDT 24
Finished Jul 15 06:55:24 PM PDT 24
Peak memory 213972 kb
Host smart-ab488a2f-70cc-4395-b1f6-f7be5442458d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121898765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3121898765
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.4048319692
Short name T1662
Test name
Test status
Simulation time 21902540325 ps
CPU time 58.93 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:56:17 PM PDT 24
Peak memory 1148852 kb
Host smart-97c8877f-79a3-46c9-9122-1d1466d5fadf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048319692 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.4048319692
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.3266301534
Short name T1467
Test name
Test status
Simulation time 2145216181 ps
CPU time 3.09 seconds
Started Jul 15 06:55:23 PM PDT 24
Finished Jul 15 06:55:26 PM PDT 24
Peak memory 213768 kb
Host smart-df63c75a-dc5b-4d7a-8c48-937c94c83882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266301534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.3266301534
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.1911792110
Short name T458
Test name
Test status
Simulation time 1884617079 ps
CPU time 2.35 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:55:28 PM PDT 24
Peak memory 205628 kb
Host smart-0810199b-4240-4d24-a1e4-6169d2ee11bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911792110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.1911792110
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.177982506
Short name T554
Test name
Test status
Simulation time 2783365600 ps
CPU time 5.25 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:36 PM PDT 24
Peak memory 222112 kb
Host smart-cb212705-9d48-4bfe-b4e6-c01a37cd44ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177982506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_perf.177982506
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.4068635971
Short name T1560
Test name
Test status
Simulation time 2508853350 ps
CPU time 2.37 seconds
Started Jul 15 06:55:22 PM PDT 24
Finished Jul 15 06:55:25 PM PDT 24
Peak memory 205496 kb
Host smart-60585302-76ac-4d6f-bad6-9461ef70f5db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068635971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.4068635971
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2610155707
Short name T361
Test name
Test status
Simulation time 9923005959 ps
CPU time 20.48 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:38 PM PDT 24
Peak memory 213856 kb
Host smart-966aa1d2-130a-47a2-9aab-96a6eedc72e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610155707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2610155707
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.1117499492
Short name T1664
Test name
Test status
Simulation time 29896710880 ps
CPU time 516.96 seconds
Started Jul 15 06:55:26 PM PDT 24
Finished Jul 15 07:04:04 PM PDT 24
Peak memory 3560324 kb
Host smart-6a3adf96-b350-436b-83af-3e54f6409dcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117499492 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.1117499492
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1300900566
Short name T1618
Test name
Test status
Simulation time 2992633023 ps
CPU time 31.26 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:49 PM PDT 24
Peak memory 213904 kb
Host smart-12adfab1-e9a1-4b8d-a2fd-b3e5930cf491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300900566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1300900566
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.550198069
Short name T1566
Test name
Test status
Simulation time 17312561507 ps
CPU time 31.68 seconds
Started Jul 15 06:55:18 PM PDT 24
Finished Jul 15 06:55:50 PM PDT 24
Peak memory 205744 kb
Host smart-e36e46e7-fcd5-4ff4-925c-d06304639e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550198069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.550198069
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3167560402
Short name T924
Test name
Test status
Simulation time 3163902248 ps
CPU time 4.6 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:22 PM PDT 24
Peak memory 264156 kb
Host smart-272bfadc-91ae-4eed-ba56-f3b64998455e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167560402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3167560402
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.634438196
Short name T556
Test name
Test status
Simulation time 1251122079 ps
CPU time 7.08 seconds
Started Jul 15 06:55:17 PM PDT 24
Finished Jul 15 06:55:25 PM PDT 24
Peak memory 230368 kb
Host smart-9306ae76-5bc3-4209-a369-c759dbcd8c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634438196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.634438196
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.4088597397
Short name T548
Test name
Test status
Simulation time 172877198 ps
CPU time 3.37 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:55:29 PM PDT 24
Peak memory 205596 kb
Host smart-f5a80f4a-6119-431e-9d27-962b7e919655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088597397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.4088597397
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2790565405
Short name T376
Test name
Test status
Simulation time 18491108 ps
CPU time 0.65 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:55:30 PM PDT 24
Peak memory 204800 kb
Host smart-14bb4bd7-131a-4688-ae3d-e41fa95517d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790565405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2790565405
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1216048406
Short name T1193
Test name
Test status
Simulation time 106745539 ps
CPU time 1.5 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:55:27 PM PDT 24
Peak memory 221996 kb
Host smart-32947e1c-cb13-4713-98ff-8fe4657f8177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216048406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1216048406
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.942798464
Short name T577
Test name
Test status
Simulation time 367370956 ps
CPU time 9.73 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:40 PM PDT 24
Peak memory 238764 kb
Host smart-4778dad8-3311-44a7-a4f6-37511188d2ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942798464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.942798464
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2521348074
Short name T1002
Test name
Test status
Simulation time 4460001399 ps
CPU time 137.68 seconds
Started Jul 15 06:55:26 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 544384 kb
Host smart-09c332fc-68ea-4a97-af0e-f591852c7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521348074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2521348074
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1385391571
Short name T1230
Test name
Test status
Simulation time 2674479051 ps
CPU time 91.23 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:56:57 PM PDT 24
Peak memory 843324 kb
Host smart-4dcb2aca-ec14-4306-8477-ab5a2c92a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385391571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1385391571
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1988065224
Short name T730
Test name
Test status
Simulation time 660968574 ps
CPU time 9.98 seconds
Started Jul 15 06:55:26 PM PDT 24
Finished Jul 15 06:55:36 PM PDT 24
Peak memory 236288 kb
Host smart-5c0053fc-b378-4709-bba2-35e2b8574be8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988065224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1988065224
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1877907466
Short name T1042
Test name
Test status
Simulation time 3498160617 ps
CPU time 238.32 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:59:24 PM PDT 24
Peak memory 1043172 kb
Host smart-d1168490-340d-4bd3-ac29-8e9f9265eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877907466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1877907466
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.540789659
Short name T938
Test name
Test status
Simulation time 260253238 ps
CPU time 4.22 seconds
Started Jul 15 06:55:28 PM PDT 24
Finished Jul 15 06:55:33 PM PDT 24
Peak memory 205464 kb
Host smart-809faa79-64d8-45ef-988c-17af46719a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540789659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.540789659
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.3786167810
Short name T1116
Test name
Test status
Simulation time 45940759 ps
CPU time 0.69 seconds
Started Jul 15 06:55:31 PM PDT 24
Finished Jul 15 06:55:33 PM PDT 24
Peak memory 205172 kb
Host smart-719ab714-bde4-497c-99b1-38f3237fe944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786167810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3786167810
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1603937220
Short name T1293
Test name
Test status
Simulation time 13012167030 ps
CPU time 56.72 seconds
Started Jul 15 06:55:25 PM PDT 24
Finished Jul 15 06:56:23 PM PDT 24
Peak memory 615216 kb
Host smart-30b902d7-413d-4f55-afba-4e7175f1b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603937220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1603937220
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.3265672938
Short name T1063
Test name
Test status
Simulation time 2151270168 ps
CPU time 20.79 seconds
Started Jul 15 06:55:23 PM PDT 24
Finished Jul 15 06:55:45 PM PDT 24
Peak memory 205536 kb
Host smart-d1589205-15c2-4ae1-ad14-a5136a966cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265672938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.3265672938
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.238490360
Short name T1111
Test name
Test status
Simulation time 1485707865 ps
CPU time 72.53 seconds
Started Jul 15 06:55:22 PM PDT 24
Finished Jul 15 06:56:36 PM PDT 24
Peak memory 314580 kb
Host smart-dbf4ae47-2d73-4866-9195-7e92e63adb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238490360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.238490360
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.4163060400
Short name T199
Test name
Test status
Simulation time 1115612853 ps
CPU time 11.23 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:42 PM PDT 24
Peak memory 221340 kb
Host smart-72523d50-c185-40aa-80dd-0fe49594d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163060400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.4163060400
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.580862645
Short name T1437
Test name
Test status
Simulation time 2055754760 ps
CPU time 5.6 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:55:35 PM PDT 24
Peak memory 218384 kb
Host smart-26cd1c82-4563-481c-aae9-719a9b477393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580862645 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.580862645
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2767363582
Short name T796
Test name
Test status
Simulation time 222944720 ps
CPU time 1.41 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:32 PM PDT 24
Peak memory 205616 kb
Host smart-f8451a0d-8f15-4f97-85bb-1a8279972989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767363582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2767363582
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2756628393
Short name T1717
Test name
Test status
Simulation time 192685037 ps
CPU time 1.12 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:32 PM PDT 24
Peak memory 205488 kb
Host smart-ebf251fe-948f-4791-9a68-28d0209da69f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756628393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2756628393
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.156148387
Short name T1347
Test name
Test status
Simulation time 382681587 ps
CPU time 1.34 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:55:31 PM PDT 24
Peak memory 205420 kb
Host smart-5f2b6d47-94eb-4948-9125-9f6a0eea3574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156148387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.156148387
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1435603667
Short name T1369
Test name
Test status
Simulation time 230856542 ps
CPU time 1.14 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:32 PM PDT 24
Peak memory 205440 kb
Host smart-5a84f74b-e2f4-4b19-809b-768c4bfb3726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435603667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1435603667
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3063151517
Short name T502
Test name
Test status
Simulation time 3594315761 ps
CPU time 5.24 seconds
Started Jul 15 06:55:26 PM PDT 24
Finished Jul 15 06:55:31 PM PDT 24
Peak memory 213920 kb
Host smart-a1dc86a5-62b4-4695-b66d-2952e3edb04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063151517 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3063151517
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3415645408
Short name T173
Test name
Test status
Simulation time 9445907546 ps
CPU time 130.96 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:57:40 PM PDT 24
Peak memory 2434156 kb
Host smart-6082ed82-af24-4681-994c-2aeb8826e72e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415645408 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3415645408
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.2010649052
Short name T1106
Test name
Test status
Simulation time 3744189719 ps
CPU time 2.8 seconds
Started Jul 15 06:55:29 PM PDT 24
Finished Jul 15 06:55:33 PM PDT 24
Peak memory 213804 kb
Host smart-cfb10dae-b3f9-4ffb-bf52-973aaf3b12a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010649052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.2010649052
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.523748699
Short name T1060
Test name
Test status
Simulation time 488172253 ps
CPU time 2.6 seconds
Started Jul 15 06:55:31 PM PDT 24
Finished Jul 15 06:55:34 PM PDT 24
Peak memory 205608 kb
Host smart-649abd72-d8f3-4234-90ff-21ed5da0b68c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523748699 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.523748699
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.2290906321
Short name T1376
Test name
Test status
Simulation time 689336648 ps
CPU time 4.98 seconds
Started Jul 15 06:55:31 PM PDT 24
Finished Jul 15 06:55:36 PM PDT 24
Peak memory 221872 kb
Host smart-40449aca-eda0-4a80-8802-cbaa0a50c269
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290906321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.2290906321
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1199437124
Short name T1027
Test name
Test status
Simulation time 390828901 ps
CPU time 2.04 seconds
Started Jul 15 06:55:31 PM PDT 24
Finished Jul 15 06:55:34 PM PDT 24
Peak memory 205372 kb
Host smart-252f7716-5db8-4561-9f65-0359b3056750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199437124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1199437124
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.4162621001
Short name T89
Test name
Test status
Simulation time 2976844788 ps
CPU time 30.12 seconds
Started Jul 15 06:55:28 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 213848 kb
Host smart-748ed4c3-51fe-4e71-a3bb-8c90d0eddf6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162621001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.4162621001
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.1335156836
Short name T1080
Test name
Test status
Simulation time 75042890069 ps
CPU time 316.4 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 2203520 kb
Host smart-15978cf1-4f70-464a-ab65-318fc1374340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335156836 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.1335156836
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.4097109701
Short name T1722
Test name
Test status
Simulation time 8070741419 ps
CPU time 33.68 seconds
Started Jul 15 06:55:24 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 246508 kb
Host smart-ee0e5ff2-cf35-4f8d-9178-37ed0d7b2297
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097109701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.4097109701
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2877207628
Short name T1359
Test name
Test status
Simulation time 58371486762 ps
CPU time 680.96 seconds
Started Jul 15 06:55:22 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 4907060 kb
Host smart-03bfb4d0-a8d4-4610-ae21-09de6acdf789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877207628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2877207628
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3273879109
Short name T1721
Test name
Test status
Simulation time 1289940884 ps
CPU time 7.35 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:38 PM PDT 24
Peak memory 230196 kb
Host smart-7f92c07e-4392-47ec-8a8a-ac96cd276376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273879109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3273879109
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.4243094975
Short name T673
Test name
Test status
Simulation time 152994661 ps
CPU time 3.34 seconds
Started Jul 15 06:55:30 PM PDT 24
Finished Jul 15 06:55:34 PM PDT 24
Peak memory 205604 kb
Host smart-41016e75-0f05-4487-a40c-9caf67d5a99b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243094975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.4243094975
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.874395062
Short name T1609
Test name
Test status
Simulation time 15388175 ps
CPU time 0.67 seconds
Started Jul 15 06:55:40 PM PDT 24
Finished Jul 15 06:55:41 PM PDT 24
Peak memory 204872 kb
Host smart-6600e042-beb0-40b4-a7b0-d4865911e1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874395062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.874395062
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.129661167
Short name T1413
Test name
Test status
Simulation time 828386222 ps
CPU time 2.35 seconds
Started Jul 15 06:55:38 PM PDT 24
Finished Jul 15 06:55:40 PM PDT 24
Peak memory 216320 kb
Host smart-809a6fcf-fa44-4a7e-97a5-3c7e83540d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129661167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.129661167
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3979803290
Short name T1303
Test name
Test status
Simulation time 1449187114 ps
CPU time 19.61 seconds
Started Jul 15 06:55:35 PM PDT 24
Finished Jul 15 06:55:55 PM PDT 24
Peak memory 283836 kb
Host smart-ce57baf1-eb1c-496d-a886-2d3b41a911de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979803290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3979803290
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.4275053564
Short name T383
Test name
Test status
Simulation time 2394134263 ps
CPU time 61.44 seconds
Started Jul 15 06:55:34 PM PDT 24
Finished Jul 15 06:56:36 PM PDT 24
Peak memory 384840 kb
Host smart-55ba00f6-037c-403e-9aef-aa90c9b4d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275053564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.4275053564
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2172593846
Short name T419
Test name
Test status
Simulation time 1767158883 ps
CPU time 111.56 seconds
Started Jul 15 06:55:36 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 512004 kb
Host smart-e13e6e7d-e3df-4231-821a-227ada7344a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172593846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2172593846
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2769712026
Short name T9
Test name
Test status
Simulation time 477723808 ps
CPU time 1.03 seconds
Started Jul 15 06:55:36 PM PDT 24
Finished Jul 15 06:55:38 PM PDT 24
Peak memory 205248 kb
Host smart-0c6ba486-0798-4336-a70e-13dbdb531c45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769712026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2769712026
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.112340879
Short name T671
Test name
Test status
Simulation time 741890691 ps
CPU time 10.22 seconds
Started Jul 15 06:55:32 PM PDT 24
Finished Jul 15 06:55:42 PM PDT 24
Peak memory 239644 kb
Host smart-1d4b898d-30ea-429c-95b7-40465dfa77fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112340879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
112340879
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1076532561
Short name T119
Test name
Test status
Simulation time 3470128120 ps
CPU time 76.07 seconds
Started Jul 15 06:55:34 PM PDT 24
Finished Jul 15 06:56:51 PM PDT 24
Peak memory 1019380 kb
Host smart-3676ce1d-d1d9-4cc5-b2ed-2a4dafccf0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076532561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1076532561
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2981885947
Short name T258
Test name
Test status
Simulation time 2696670061 ps
CPU time 10.53 seconds
Started Jul 15 06:55:43 PM PDT 24
Finished Jul 15 06:55:54 PM PDT 24
Peak memory 205552 kb
Host smart-70193c2e-41ee-46c8-8fca-c5bb4e4dccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981885947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2981885947
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.2111631016
Short name T146
Test name
Test status
Simulation time 29761375 ps
CPU time 0.72 seconds
Started Jul 15 06:55:36 PM PDT 24
Finished Jul 15 06:55:37 PM PDT 24
Peak memory 205244 kb
Host smart-8eea9799-8da7-4709-9438-4eab4d3b9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111631016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2111631016
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.579168075
Short name T928
Test name
Test status
Simulation time 47233360676 ps
CPU time 691.05 seconds
Started Jul 15 06:55:35 PM PDT 24
Finished Jul 15 07:07:07 PM PDT 24
Peak memory 2843284 kb
Host smart-7a140c5a-a2eb-4776-a4d3-aa80caeebce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579168075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.579168075
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3207397288
Short name T441
Test name
Test status
Simulation time 6081020120 ps
CPU time 217.26 seconds
Started Jul 15 06:55:37 PM PDT 24
Finished Jul 15 06:59:15 PM PDT 24
Peak memory 205236 kb
Host smart-e4d93f3f-e331-415e-aa19-426f3a8b4e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207397288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3207397288
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.767568658
Short name T1383
Test name
Test status
Simulation time 1702473790 ps
CPU time 32.96 seconds
Started Jul 15 06:55:28 PM PDT 24
Finished Jul 15 06:56:01 PM PDT 24
Peak memory 324532 kb
Host smart-fce5fef7-d28a-40cb-94c3-bc663e9f52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767568658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.767568658
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3181138892
Short name T1680
Test name
Test status
Simulation time 488930475 ps
CPU time 7.79 seconds
Started Jul 15 06:55:35 PM PDT 24
Finished Jul 15 06:55:43 PM PDT 24
Peak memory 213688 kb
Host smart-80af446b-27a7-44d1-a2ac-213f384ac5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181138892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3181138892
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3311966287
Short name T1194
Test name
Test status
Simulation time 1043183738 ps
CPU time 5.57 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:47 PM PDT 24
Peak memory 214012 kb
Host smart-a7872a42-1b0d-4eaf-9442-796bc2fddc4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311966287 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3311966287
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.620923032
Short name T1711
Test name
Test status
Simulation time 264402469 ps
CPU time 1.14 seconds
Started Jul 15 06:55:37 PM PDT 24
Finished Jul 15 06:55:39 PM PDT 24
Peak memory 205444 kb
Host smart-e0be1925-9cf5-4c21-9b00-5911f7e4b117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620923032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.620923032
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.626115652
Short name T588
Test name
Test status
Simulation time 251039873 ps
CPU time 1.08 seconds
Started Jul 15 06:55:38 PM PDT 24
Finished Jul 15 06:55:39 PM PDT 24
Peak memory 205476 kb
Host smart-fb5767cc-27b5-4bde-896e-5fc6a0e49400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626115652 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.626115652
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.1609349688
Short name T1344
Test name
Test status
Simulation time 1275305786 ps
CPU time 1.79 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:44 PM PDT 24
Peak memory 205452 kb
Host smart-aeffde97-9e5a-4e55-84e1-80660ae59d9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609349688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.1609349688
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.348151666
Short name T1392
Test name
Test status
Simulation time 435520356 ps
CPU time 1.11 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:42 PM PDT 24
Peak memory 205456 kb
Host smart-04a8f5e9-adf9-4096-aaa6-2d136bef6246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348151666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.348151666
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.458190878
Short name T400
Test name
Test status
Simulation time 461780824 ps
CPU time 1.87 seconds
Started Jul 15 06:55:43 PM PDT 24
Finished Jul 15 06:55:45 PM PDT 24
Peak memory 214624 kb
Host smart-2133a4ce-fc09-4a3a-864b-8058ddd73dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458190878 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.458190878
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2233848460
Short name T1325
Test name
Test status
Simulation time 886555002 ps
CPU time 5.07 seconds
Started Jul 15 06:55:39 PM PDT 24
Finished Jul 15 06:55:45 PM PDT 24
Peak memory 222056 kb
Host smart-aa77cd02-bda8-48c7-85b0-58240b58de51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233848460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2233848460
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.348314547
Short name T597
Test name
Test status
Simulation time 6229309268 ps
CPU time 4.54 seconds
Started Jul 15 06:55:35 PM PDT 24
Finished Jul 15 06:55:40 PM PDT 24
Peak memory 205756 kb
Host smart-7e886dce-1615-4dc7-8fb5-973e220e6b80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348314547 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.348314547
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3143277256
Short name T411
Test name
Test status
Simulation time 5938449679 ps
CPU time 2.55 seconds
Started Jul 15 06:55:39 PM PDT 24
Finished Jul 15 06:55:42 PM PDT 24
Peak memory 213956 kb
Host smart-f0a415d4-a221-4414-98e0-a76256bce028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143277256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3143277256
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.3625623766
Short name T1492
Test name
Test status
Simulation time 5299720973 ps
CPU time 2.67 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:44 PM PDT 24
Peak memory 205720 kb
Host smart-a90e802b-dbc9-4eb2-848b-08af41640901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625623766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3625623766
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.3325427724
Short name T1049
Test name
Test status
Simulation time 1494210278 ps
CPU time 3.18 seconds
Started Jul 15 06:55:34 PM PDT 24
Finished Jul 15 06:55:38 PM PDT 24
Peak memory 213816 kb
Host smart-5eae5ab0-72d3-4668-9e5d-7dbb73a1a891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325427724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.3325427724
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.112654371
Short name T956
Test name
Test status
Simulation time 2027599576 ps
CPU time 2.71 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:44 PM PDT 24
Peak memory 205448 kb
Host smart-83b9d607-e3a8-42de-8478-91b3371ec90f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112654371 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.112654371
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.255749277
Short name T1314
Test name
Test status
Simulation time 6065324741 ps
CPU time 39.49 seconds
Started Jul 15 06:55:39 PM PDT 24
Finished Jul 15 06:56:19 PM PDT 24
Peak memory 213876 kb
Host smart-2f904386-2ee1-4f85-9d4a-52bf6356e111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255749277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.255749277
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.2834120335
Short name T1388
Test name
Test status
Simulation time 52483903543 ps
CPU time 74.13 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 763248 kb
Host smart-7d74491e-8113-462a-b883-b7b5cf9b8e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834120335 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.2834120335
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1406899008
Short name T1581
Test name
Test status
Simulation time 1565939066 ps
CPU time 28.1 seconds
Started Jul 15 06:55:40 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 234592 kb
Host smart-617bdcd7-92e0-443e-8911-e4ced45f453e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406899008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1406899008
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3680875464
Short name T809
Test name
Test status
Simulation time 19325380800 ps
CPU time 33.76 seconds
Started Jul 15 06:55:34 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 205732 kb
Host smart-33214767-573b-4407-b335-9fae047b17f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680875464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3680875464
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1050137787
Short name T529
Test name
Test status
Simulation time 1778754859 ps
CPU time 23.84 seconds
Started Jul 15 06:55:36 PM PDT 24
Finished Jul 15 06:56:00 PM PDT 24
Peak memory 473252 kb
Host smart-0a37b647-329b-4a49-8b60-8e332ded537b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050137787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1050137787
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.168997020
Short name T725
Test name
Test status
Simulation time 1060738008 ps
CPU time 6.41 seconds
Started Jul 15 06:55:37 PM PDT 24
Finished Jul 15 06:55:44 PM PDT 24
Peak memory 213888 kb
Host smart-8a1c3abc-4ad7-4e92-ab20-f9b56e1afce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168997020 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.168997020
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.2264024843
Short name T635
Test name
Test status
Simulation time 141740953 ps
CPU time 2.42 seconds
Started Jul 15 06:55:40 PM PDT 24
Finished Jul 15 06:55:43 PM PDT 24
Peak memory 205600 kb
Host smart-dc275555-fdac-42f8-bfb3-a8c37dfc48d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264024843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2264024843
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3115318649
Short name T1238
Test name
Test status
Simulation time 23541666 ps
CPU time 0.65 seconds
Started Jul 15 06:55:54 PM PDT 24
Finished Jul 15 06:55:55 PM PDT 24
Peak memory 204692 kb
Host smart-0dce0c53-e2ad-4eb6-bde3-c5f10024fc46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115318649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3115318649
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1058905755
Short name T927
Test name
Test status
Simulation time 588295194 ps
CPU time 2.96 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:55:52 PM PDT 24
Peak memory 233244 kb
Host smart-ab422b2c-cfea-47c4-9c33-dc32c65a23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058905755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1058905755
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2541239931
Short name T450
Test name
Test status
Simulation time 746561353 ps
CPU time 9.26 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:55:57 PM PDT 24
Peak memory 239532 kb
Host smart-5363ca92-c67a-4e44-8c7d-c26a2120a1cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541239931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2541239931
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.63113223
Short name T1404
Test name
Test status
Simulation time 8936333396 ps
CPU time 182.36 seconds
Started Jul 15 06:55:47 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 548900 kb
Host smart-d1771ce9-3d46-4b6d-93d5-31c3bee0a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63113223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.63113223
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.22068593
Short name T586
Test name
Test status
Simulation time 2219180985 ps
CPU time 171.38 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:58:33 PM PDT 24
Peak memory 755696 kb
Host smart-18c9db10-fa3a-408e-827e-e493b4ec9534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22068593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.22068593
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2751678662
Short name T386
Test name
Test status
Simulation time 914512039 ps
CPU time 1.16 seconds
Started Jul 15 06:55:41 PM PDT 24
Finished Jul 15 06:55:43 PM PDT 24
Peak memory 205240 kb
Host smart-0aa9ed74-c053-42c7-9cf0-977d82780332
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751678662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2751678662
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3984744011
Short name T1712
Test name
Test status
Simulation time 150997605 ps
CPU time 2.86 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:55:52 PM PDT 24
Peak memory 205528 kb
Host smart-b30373ad-cce3-4da0-9653-81d0bd9499ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984744011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3984744011
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2431168111
Short name T1615
Test name
Test status
Simulation time 17969416167 ps
CPU time 171.06 seconds
Started Jul 15 06:55:42 PM PDT 24
Finished Jul 15 06:58:34 PM PDT 24
Peak memory 885024 kb
Host smart-0d30593d-6b1f-4316-bc7b-70206a7e9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431168111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2431168111
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.4165822995
Short name T853
Test name
Test status
Simulation time 1278473617 ps
CPU time 2.97 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:53 PM PDT 24
Peak memory 205532 kb
Host smart-30cfd2b1-0f4c-4ca5-9694-b2da7e83ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165822995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.4165822995
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1480716832
Short name T1357
Test name
Test status
Simulation time 114957876 ps
CPU time 2.33 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:52 PM PDT 24
Peak memory 221652 kb
Host smart-7e471634-6df5-4f9e-aaf8-d107d0685054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480716832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1480716832
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1003525175
Short name T151
Test name
Test status
Simulation time 33099792 ps
CPU time 0.68 seconds
Started Jul 15 06:55:42 PM PDT 24
Finished Jul 15 06:55:43 PM PDT 24
Peak memory 205332 kb
Host smart-418116fc-5843-4f80-abf7-04056ab63a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003525175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1003525175
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.345026840
Short name T1047
Test name
Test status
Simulation time 8029397955 ps
CPU time 74.26 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:57:03 PM PDT 24
Peak memory 519956 kb
Host smart-0d3ad42e-2b21-4f6f-81e3-dbab0aa7fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345026840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.345026840
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1078332778
Short name T1012
Test name
Test status
Simulation time 63246655 ps
CPU time 2.84 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:55:53 PM PDT 24
Peak memory 205492 kb
Host smart-71948b2f-44f3-4e81-8f21-af2efb28c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078332778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1078332778
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1936034403
Short name T881
Test name
Test status
Simulation time 6947998970 ps
CPU time 83.97 seconds
Started Jul 15 06:55:40 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 359852 kb
Host smart-53375931-7358-4b64-87de-f4062d108d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936034403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1936034403
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1021940065
Short name T8
Test name
Test status
Simulation time 1864284045 ps
CPU time 24.67 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:56:15 PM PDT 24
Peak memory 213728 kb
Host smart-09fdf477-4a07-4eec-959f-9e1839e1c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021940065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1021940065
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.391749665
Short name T826
Test name
Test status
Simulation time 1078416930 ps
CPU time 4.95 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:55:54 PM PDT 24
Peak memory 213888 kb
Host smart-44dce754-c2b9-467f-bcfa-c84f297decc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391749665 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.391749665
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1519130886
Short name T744
Test name
Test status
Simulation time 431887640 ps
CPU time 0.87 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:51 PM PDT 24
Peak memory 213652 kb
Host smart-5e9b9c4f-04fd-4840-8d2f-ce66266e0ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519130886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1519130886
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.335514086
Short name T504
Test name
Test status
Simulation time 244758672 ps
CPU time 0.94 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:55:49 PM PDT 24
Peak memory 213628 kb
Host smart-ad5bca08-5f5c-4c5b-acac-e9d847958032
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335514086 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_tx.335514086
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.1540587386
Short name T279
Test name
Test status
Simulation time 374945993 ps
CPU time 2.26 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:52 PM PDT 24
Peak memory 205612 kb
Host smart-aaac9dfa-68f3-4518-9fe2-b2a55af2adcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540587386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.1540587386
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.1557956285
Short name T923
Test name
Test status
Simulation time 991561404 ps
CPU time 1.02 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:51 PM PDT 24
Peak memory 205432 kb
Host smart-57422d48-461d-4eea-9085-82be19d17c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557956285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.1557956285
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2490040207
Short name T1738
Test name
Test status
Simulation time 325360160 ps
CPU time 2.57 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:55:52 PM PDT 24
Peak memory 213892 kb
Host smart-aaf03647-7bc1-4e78-83ae-cf9d8c033d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490040207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2490040207
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1346962976
Short name T995
Test name
Test status
Simulation time 2497729176 ps
CPU time 4.69 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:55:55 PM PDT 24
Peak memory 217884 kb
Host smart-364019b9-bd2c-4f55-81ef-76bf7224310c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346962976 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1346962976
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3756840505
Short name T890
Test name
Test status
Simulation time 3635671313 ps
CPU time 2.76 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:55:53 PM PDT 24
Peak memory 205656 kb
Host smart-a7f2dda2-6cd8-46c9-b375-3a32445ab512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756840505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3756840505
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.2478961392
Short name T819
Test name
Test status
Simulation time 598407076 ps
CPU time 3.14 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:56:00 PM PDT 24
Peak memory 213844 kb
Host smart-0e1fc43d-141a-4974-a5aa-ac012fa1954a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478961392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.2478961392
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.2666206866
Short name T856
Test name
Test status
Simulation time 1793110139 ps
CPU time 2.32 seconds
Started Jul 15 06:55:58 PM PDT 24
Finished Jul 15 06:56:02 PM PDT 24
Peak memory 205612 kb
Host smart-de65c8a4-d6db-47fd-82c4-af131030ce9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666206866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.2666206866
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.3153920786
Short name T836
Test name
Test status
Simulation time 3182608817 ps
CPU time 6.66 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:55:57 PM PDT 24
Peak memory 222004 kb
Host smart-9a54412d-519b-4076-8951-770ddf632625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153920786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.3153920786
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.10710812
Short name T7
Test name
Test status
Simulation time 4429664805 ps
CPU time 2.53 seconds
Started Jul 15 06:55:58 PM PDT 24
Finished Jul 15 06:56:02 PM PDT 24
Peak memory 205432 kb
Host smart-bfcb7e14-bed9-42db-9005-6d2161ef3fea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10710812 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.i2c_target_smbus_maxlen.10710812
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.727603532
Short name T288
Test name
Test status
Simulation time 2756177167 ps
CPU time 19.56 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 213876 kb
Host smart-95db25c3-c55f-494f-becf-763cdf24f2cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727603532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.727603532
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.1354431035
Short name T1170
Test name
Test status
Simulation time 40453104264 ps
CPU time 191.93 seconds
Started Jul 15 06:55:49 PM PDT 24
Finished Jul 15 06:59:01 PM PDT 24
Peak memory 1645100 kb
Host smart-9084fc64-854d-45c2-84f8-a5a26e9f6dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354431035 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.1354431035
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2970953495
Short name T904
Test name
Test status
Simulation time 389593507 ps
CPU time 17.11 seconds
Started Jul 15 06:55:48 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 205672 kb
Host smart-fc6df28f-12de-4391-9ee1-4c3e535e936d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970953495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2970953495
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3292385501
Short name T1387
Test name
Test status
Simulation time 43607944721 ps
CPU time 907.38 seconds
Started Jul 15 06:55:51 PM PDT 24
Finished Jul 15 07:10:59 PM PDT 24
Peak memory 6155700 kb
Host smart-cb713359-31cd-40b1-a6a9-21732eaabccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292385501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3292385501
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.671784112
Short name T360
Test name
Test status
Simulation time 2780467192 ps
CPU time 7.24 seconds
Started Jul 15 06:55:50 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 222052 kb
Host smart-4fa0de81-916a-4444-8aee-93bf9a390462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671784112 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.671784112
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.1789017189
Short name T1082
Test name
Test status
Simulation time 515137424 ps
CPU time 6.99 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:56:05 PM PDT 24
Peak memory 214780 kb
Host smart-aff0cbf7-eaf1-4fa4-a3ed-a61e6d82b55c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789017189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.1789017189
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3201691120
Short name T427
Test name
Test status
Simulation time 71509726 ps
CPU time 0.62 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:03 PM PDT 24
Peak memory 204860 kb
Host smart-19e9f738-0ba7-4aee-89e9-aff2dc88243a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201691120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3201691120
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1934723735
Short name T23
Test name
Test status
Simulation time 83844068 ps
CPU time 1.54 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 213704 kb
Host smart-67c3f292-4bce-495e-afcb-58d595f730ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934723735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1934723735
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.4240705286
Short name T350
Test name
Test status
Simulation time 324639167 ps
CPU time 6.21 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:56:05 PM PDT 24
Peak memory 274016 kb
Host smart-96d379ff-f3c3-4795-b764-149bb2df41ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240705286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.4240705286
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2005903704
Short name T447
Test name
Test status
Simulation time 12895182112 ps
CPU time 82.88 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 478944 kb
Host smart-9f3e5d11-be8c-4e41-b122-6882bde1a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005903704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2005903704
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.4056176255
Short name T1124
Test name
Test status
Simulation time 1998894327 ps
CPU time 63.04 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:57:00 PM PDT 24
Peak memory 649256 kb
Host smart-a88c70a5-e849-47e3-a16e-7f5c12ce10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056176255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.4056176255
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.4176080078
Short name T592
Test name
Test status
Simulation time 240901999 ps
CPU time 0.96 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 205256 kb
Host smart-e66ef24e-bf0f-451c-8a4c-3aeb9c773e50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176080078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.4176080078
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1379260754
Short name T1586
Test name
Test status
Simulation time 628409645 ps
CPU time 4.01 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:56:01 PM PDT 24
Peak memory 233180 kb
Host smart-cb035afc-c2e3-40c5-8fdc-3559a4ee4434
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379260754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1379260754
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2494805184
Short name T85
Test name
Test status
Simulation time 4579327808 ps
CPU time 321.32 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 07:01:23 PM PDT 24
Peak memory 1227808 kb
Host smart-e6904a39-02f4-435a-8f3b-e7772e839e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494805184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2494805184
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.4283306418
Short name T1207
Test name
Test status
Simulation time 655597621 ps
CPU time 4.43 seconds
Started Jul 15 06:56:00 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 205496 kb
Host smart-7fefaf4b-68c8-43a9-bc89-7f2f15a7e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283306418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.4283306418
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.2743388155
Short name T1650
Test name
Test status
Simulation time 79241438 ps
CPU time 0.66 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 205176 kb
Host smart-f4284424-9cec-4481-9d61-133c4dfa2241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743388155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2743388155
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.420663672
Short name T852
Test name
Test status
Simulation time 2722698134 ps
CPU time 64.22 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 829564 kb
Host smart-31095142-dabf-4e4f-95ef-ceb4e9083191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420663672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.420663672
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.2878479379
Short name T1610
Test name
Test status
Simulation time 112235885 ps
CPU time 4.94 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:56:03 PM PDT 24
Peak memory 213628 kb
Host smart-555c61db-0a96-471f-b98a-7adca17726a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878479379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.2878479379
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1868078517
Short name T1165
Test name
Test status
Simulation time 3256048523 ps
CPU time 35.63 seconds
Started Jul 15 06:55:54 PM PDT 24
Finished Jul 15 06:56:32 PM PDT 24
Peak memory 362044 kb
Host smart-63efd00d-a053-4c87-82c0-398e965de44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868078517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1868078517
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3014074599
Short name T1195
Test name
Test status
Simulation time 919768078 ps
CPU time 34.35 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 213752 kb
Host smart-1482407f-094f-4733-9a81-f1328bf24ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014074599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3014074599
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3904687430
Short name T832
Test name
Test status
Simulation time 948370233 ps
CPU time 5.21 seconds
Started Jul 15 06:55:58 PM PDT 24
Finished Jul 15 06:56:05 PM PDT 24
Peak memory 209816 kb
Host smart-b6b1f01e-bf3a-4b12-bb1f-6bfdb54b7fbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904687430 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3904687430
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3684187828
Short name T1267
Test name
Test status
Simulation time 321569684 ps
CPU time 1.14 seconds
Started Jul 15 06:55:58 PM PDT 24
Finished Jul 15 06:56:01 PM PDT 24
Peak memory 205444 kb
Host smart-b6befd5a-42c9-4827-b552-8a6ece951d74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684187828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3684187828
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3023505061
Short name T1321
Test name
Test status
Simulation time 152555166 ps
CPU time 0.96 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:55:58 PM PDT 24
Peak memory 205440 kb
Host smart-caea5176-de41-4346-90bb-27cfabcaf0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023505061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3023505061
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.3752770468
Short name T380
Test name
Test status
Simulation time 1748029436 ps
CPU time 3.26 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 205680 kb
Host smart-da357f0a-1ef7-4f37-8785-27e5f3b79954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752770468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.3752770468
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1105622190
Short name T297
Test name
Test status
Simulation time 276174715 ps
CPU time 1 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:03 PM PDT 24
Peak memory 205408 kb
Host smart-74084cfb-5ba5-4119-8295-d63cd677da73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105622190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1105622190
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1852971564
Short name T659
Test name
Test status
Simulation time 1366560536 ps
CPU time 4.74 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:56:02 PM PDT 24
Peak memory 221996 kb
Host smart-bccc1e76-e8da-4c8f-9554-bdc6086728bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852971564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1852971564
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2137378207
Short name T351
Test name
Test status
Simulation time 19431081743 ps
CPU time 108.98 seconds
Started Jul 15 06:55:57 PM PDT 24
Finished Jul 15 06:57:48 PM PDT 24
Peak memory 1367816 kb
Host smart-97715021-b0c1-444f-8da2-5a24410caec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137378207 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2137378207
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.3404810538
Short name T578
Test name
Test status
Simulation time 874216414 ps
CPU time 2.71 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 213828 kb
Host smart-8d87dbec-3e85-425f-94b8-63e2664b0281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404810538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_nack_acqfull.3404810538
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.281566982
Short name T497
Test name
Test status
Simulation time 1073998842 ps
CPU time 2.72 seconds
Started Jul 15 06:56:02 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 205588 kb
Host smart-ebae9b6c-f56f-4c66-9e38-cc4af40ff1ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281566982 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.281566982
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.3320310547
Short name T392
Test name
Test status
Simulation time 2976369945 ps
CPU time 5.58 seconds
Started Jul 15 06:56:00 PM PDT 24
Finished Jul 15 06:56:07 PM PDT 24
Peak memory 213876 kb
Host smart-e7df4d08-28d6-4c05-a6a3-b3b93b86c42d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320310547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.3320310547
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.1521856025
Short name T1007
Test name
Test status
Simulation time 1545313640 ps
CPU time 2.03 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 205372 kb
Host smart-723e2a04-49be-4577-ae0a-acb95d769497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521856025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.1521856025
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4127425958
Short name T843
Test name
Test status
Simulation time 809462816 ps
CPU time 10.12 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:12 PM PDT 24
Peak memory 213788 kb
Host smart-d3cd26df-cb2c-4524-9aff-fbbee20eac1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127425958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4127425958
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.775127389
Short name T1150
Test name
Test status
Simulation time 45981262880 ps
CPU time 620.32 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 07:06:24 PM PDT 24
Peak memory 3311952 kb
Host smart-74b4a759-784d-42ae-9949-e89a727cd516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775127389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_target_stress_all.775127389
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2329041531
Short name T728
Test name
Test status
Simulation time 422342728 ps
CPU time 7.17 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 06:56:04 PM PDT 24
Peak memory 206684 kb
Host smart-3e51008d-bd1f-4535-b6db-7bce8558eda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329041531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2329041531
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1983380980
Short name T800
Test name
Test status
Simulation time 39772407591 ps
CPU time 486.65 seconds
Started Jul 15 06:55:55 PM PDT 24
Finished Jul 15 07:04:04 PM PDT 24
Peak memory 4175648 kb
Host smart-0c1f3da2-dfd8-42cb-91d0-647c1a65d2ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983380980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1983380980
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1696115031
Short name T1548
Test name
Test status
Simulation time 5203554300 ps
CPU time 21 seconds
Started Jul 15 06:55:56 PM PDT 24
Finished Jul 15 06:56:19 PM PDT 24
Peak memory 471192 kb
Host smart-6414b542-4a3e-4cb4-83ec-d90ad40a2748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696115031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1696115031
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2825709556
Short name T1670
Test name
Test status
Simulation time 5035216049 ps
CPU time 7.08 seconds
Started Jul 15 06:55:57 PM PDT 24
Finished Jul 15 06:56:06 PM PDT 24
Peak memory 230236 kb
Host smart-40d380be-2198-4a60-ab71-63009d385f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825709556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2825709556
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.3751226312
Short name T4
Test name
Test status
Simulation time 155147915 ps
CPU time 3.39 seconds
Started Jul 15 06:56:04 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 205584 kb
Host smart-a4e6b9fa-aec0-4eca-9aee-9df6920154d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751226312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3751226312
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.719601888
Short name T1304
Test name
Test status
Simulation time 17003144 ps
CPU time 0.65 seconds
Started Jul 15 06:56:21 PM PDT 24
Finished Jul 15 06:56:22 PM PDT 24
Peak memory 204844 kb
Host smart-1a552f53-7128-4570-a2ff-0d02a7465d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719601888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.719601888
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1803190648
Short name T21
Test name
Test status
Simulation time 436516551 ps
CPU time 4.14 seconds
Started Jul 15 06:56:02 PM PDT 24
Finished Jul 15 06:56:07 PM PDT 24
Peak memory 246196 kb
Host smart-754cb113-16df-4d52-87c9-3effc4144749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803190648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1803190648
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1418746839
Short name T892
Test name
Test status
Simulation time 1287179181 ps
CPU time 22.3 seconds
Started Jul 15 06:56:00 PM PDT 24
Finished Jul 15 06:56:24 PM PDT 24
Peak memory 294220 kb
Host smart-e995e81f-e011-4c58-8b2f-c7adc01435cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418746839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1418746839
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2059389961
Short name T1316
Test name
Test status
Simulation time 6766482038 ps
CPU time 184 seconds
Started Jul 15 06:55:59 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 361836 kb
Host smart-8c4c00a5-3835-47da-a104-eb2f66c15172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059389961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2059389961
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1586346596
Short name T471
Test name
Test status
Simulation time 7058957323 ps
CPU time 101.47 seconds
Started Jul 15 06:56:02 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 824780 kb
Host smart-0918ba92-d6b1-41fd-887e-3d6b3cddb548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586346596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1586346596
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1649891101
Short name T647
Test name
Test status
Simulation time 188979447 ps
CPU time 1.05 seconds
Started Jul 15 06:56:06 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 205372 kb
Host smart-657eb7cf-9210-418f-a16f-6e5cf339dbcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649891101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1649891101
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3936571572
Short name T1488
Test name
Test status
Simulation time 225989852 ps
CPU time 11.69 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 244864 kb
Host smart-be005e1a-b621-4586-a0d1-f7724ef10e7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936571572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3936571572
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3199677874
Short name T1062
Test name
Test status
Simulation time 5386309493 ps
CPU time 420.1 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 1402724 kb
Host smart-8dcb6e7f-2764-4e81-9a29-0410de4a78c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199677874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3199677874
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3113512373
Short name T627
Test name
Test status
Simulation time 2610775859 ps
CPU time 20.13 seconds
Started Jul 15 06:56:08 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 205572 kb
Host smart-dc9d084b-acd2-4e6e-b5ed-763d099bf893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113512373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3113512373
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.2962905487
Short name T83
Test name
Test status
Simulation time 29720476 ps
CPU time 0.72 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:04 PM PDT 24
Peak memory 205240 kb
Host smart-6d3e7058-f73e-42a0-864a-b55e0c82e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962905487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2962905487
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3912358590
Short name T1288
Test name
Test status
Simulation time 5235107036 ps
CPU time 108.65 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:57:57 PM PDT 24
Peak memory 217964 kb
Host smart-220dc58d-426d-4030-8587-be1394254a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912358590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3912358590
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2951590778
Short name T467
Test name
Test status
Simulation time 242438239 ps
CPU time 10.29 seconds
Started Jul 15 06:56:00 PM PDT 24
Finished Jul 15 06:56:11 PM PDT 24
Peak memory 248448 kb
Host smart-a8eda313-c1cf-4d42-a2d0-3353f2054daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951590778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2951590778
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3638459759
Short name T307
Test name
Test status
Simulation time 5002522367 ps
CPU time 30.6 seconds
Started Jul 15 06:56:01 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 304264 kb
Host smart-e6312772-83d7-4a6c-98ba-1054ae9b14f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638459759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3638459759
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.217136129
Short name T1543
Test name
Test status
Simulation time 3338585463 ps
CPU time 36.98 seconds
Started Jul 15 06:56:02 PM PDT 24
Finished Jul 15 06:56:40 PM PDT 24
Peak memory 213712 kb
Host smart-92b9ae94-a3bd-4d8a-9f17-6c34db7a762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217136129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.217136129
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.172558984
Short name T68
Test name
Test status
Simulation time 809427384 ps
CPU time 4.78 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:13 PM PDT 24
Peak memory 213812 kb
Host smart-fa9ab6c5-a84a-4c6a-b6e7-05eba14c06af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172558984 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.172558984
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.813226492
Short name T154
Test name
Test status
Simulation time 230795322 ps
CPU time 1.51 seconds
Started Jul 15 06:56:05 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 205516 kb
Host smart-a0b190c2-464c-4165-8398-bc0ca5409c8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813226492 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.813226492
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.813056663
Short name T712
Test name
Test status
Simulation time 543806294 ps
CPU time 2.89 seconds
Started Jul 15 06:56:05 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 205624 kb
Host smart-fb3f70a7-5b19-4986-ae95-f4ef270f5021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813056663 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.813056663
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.2391367644
Short name T1245
Test name
Test status
Simulation time 647208172 ps
CPU time 1.34 seconds
Started Jul 15 06:56:05 PM PDT 24
Finished Jul 15 06:56:08 PM PDT 24
Peak memory 205360 kb
Host smart-f073282b-0d50-4fcc-b012-1c98a55d1c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391367644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.2391367644
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1726277065
Short name T152
Test name
Test status
Simulation time 229673135 ps
CPU time 1.73 seconds
Started Jul 15 06:56:06 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 206300 kb
Host smart-b5ac115c-6c86-4738-b4d0-aebfd3530d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726277065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1726277065
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.329033268
Short name T407
Test name
Test status
Simulation time 1244161589 ps
CPU time 9.42 seconds
Started Jul 15 06:56:04 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 238332 kb
Host smart-01b2e8e7-2e25-4d2f-a3ba-56872c82aa36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329033268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.329033268
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1601231561
Short name T1107
Test name
Test status
Simulation time 10328388338 ps
CPU time 20.77 seconds
Started Jul 15 06:56:05 PM PDT 24
Finished Jul 15 06:56:26 PM PDT 24
Peak memory 706980 kb
Host smart-1b81abec-4b0f-46ac-9bad-0ede4c995e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601231561 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1601231561
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.2583441731
Short name T662
Test name
Test status
Simulation time 465399472 ps
CPU time 2.7 seconds
Started Jul 15 06:56:06 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 213812 kb
Host smart-7bd4f444-270d-4987-ad97-4ad997b18425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583441731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.2583441731
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.3743194880
Short name T1274
Test name
Test status
Simulation time 1086254734 ps
CPU time 2.95 seconds
Started Jul 15 06:56:12 PM PDT 24
Finished Jul 15 06:56:16 PM PDT 24
Peak memory 205604 kb
Host smart-f0b946ae-0b06-4b36-ae3c-165986fe9559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743194880 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.3743194880
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.1127914099
Short name T878
Test name
Test status
Simulation time 131849912 ps
CPU time 1.36 seconds
Started Jul 15 06:56:11 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 222136 kb
Host smart-285ce073-fe35-47d0-9a72-b179a7a28441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127914099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_txstretch.1127914099
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.2455545691
Short name T476
Test name
Test status
Simulation time 2844534974 ps
CPU time 5.41 seconds
Started Jul 15 06:56:04 PM PDT 24
Finished Jul 15 06:56:10 PM PDT 24
Peak memory 221020 kb
Host smart-6a9ac6a9-7b88-43d3-b30b-ec5ac8c66d91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455545691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.2455545691
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.3040211091
Short name T1736
Test name
Test status
Simulation time 474434246 ps
CPU time 2.16 seconds
Started Jul 15 06:56:06 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 205392 kb
Host smart-df9c2690-08f9-44a4-b5a9-16db6def5af1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040211091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.3040211091
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.49837866
Short name T1219
Test name
Test status
Simulation time 3618537302 ps
CPU time 26.81 seconds
Started Jul 15 06:56:08 PM PDT 24
Finished Jul 15 06:56:35 PM PDT 24
Peak memory 213840 kb
Host smart-0e49a104-9393-4500-b588-3be38960f361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49837866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_targ
et_smoke.49837866
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.1146616858
Short name T294
Test name
Test status
Simulation time 20101395962 ps
CPU time 183.13 seconds
Started Jul 15 06:56:08 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 2552712 kb
Host smart-af2943cf-c2d2-4cb4-8780-c800a6696d68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146616858 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.1146616858
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2061224023
Short name T1302
Test name
Test status
Simulation time 4950708022 ps
CPU time 26.11 seconds
Started Jul 15 06:56:06 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 213892 kb
Host smart-a9c484e1-5c0e-4891-90ab-7c9ba0d4263a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061224023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2061224023
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1304273093
Short name T358
Test name
Test status
Simulation time 7817526261 ps
CPU time 5.16 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 205656 kb
Host smart-b348dc7a-790c-4dd5-992e-96abfcaea9f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304273093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1304273093
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3738899160
Short name T934
Test name
Test status
Simulation time 2304120901 ps
CPU time 9.14 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:17 PM PDT 24
Peak memory 309956 kb
Host smart-e6ec4ec4-658d-4164-9a00-c20b90e061e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738899160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3738899160
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2928806361
Short name T971
Test name
Test status
Simulation time 1573922589 ps
CPU time 7.53 seconds
Started Jul 15 06:56:07 PM PDT 24
Finished Jul 15 06:56:16 PM PDT 24
Peak memory 230228 kb
Host smart-1669fb62-3f39-4337-8e34-7abb323f44b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928806361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2928806361
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.830828261
Short name T401
Test name
Test status
Simulation time 120894734 ps
CPU time 1.99 seconds
Started Jul 15 06:56:05 PM PDT 24
Finished Jul 15 06:56:09 PM PDT 24
Peak memory 205632 kb
Host smart-131dfc11-c470-4cc3-8010-de07f5e8291f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830828261 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.830828261
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1715433283
Short name T1503
Test name
Test status
Simulation time 53223025 ps
CPU time 0.63 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:19 PM PDT 24
Peak memory 204940 kb
Host smart-00034aa9-d3dd-4609-bd4e-e7ba2f970feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715433283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1715433283
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2376391238
Short name T1099
Test name
Test status
Simulation time 64011365 ps
CPU time 1.84 seconds
Started Jul 15 06:56:11 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 213764 kb
Host smart-124e0acb-985f-4bd5-abe2-78d36484f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376391238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2376391238
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3351545663
Short name T140
Test name
Test status
Simulation time 1354629508 ps
CPU time 8.42 seconds
Started Jul 15 06:56:13 PM PDT 24
Finished Jul 15 06:56:22 PM PDT 24
Peak memory 275104 kb
Host smart-3cce3914-02a3-478f-8dba-4dd5773281bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351545663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3351545663
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.66517274
Short name T747
Test name
Test status
Simulation time 11209426449 ps
CPU time 106.58 seconds
Started Jul 15 06:56:13 PM PDT 24
Finished Jul 15 06:58:00 PM PDT 24
Peak memory 476660 kb
Host smart-8512d86d-7565-4a0d-bd39-1386e3410048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66517274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.66517274
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1370360400
Short name T803
Test name
Test status
Simulation time 4977504335 ps
CPU time 74.89 seconds
Started Jul 15 06:56:12 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 744700 kb
Host smart-5fd9fb21-282c-4d1a-9b48-2ce64ed679b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370360400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1370360400
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2796584582
Short name T693
Test name
Test status
Simulation time 96478022 ps
CPU time 1.01 seconds
Started Jul 15 06:56:14 PM PDT 24
Finished Jul 15 06:56:16 PM PDT 24
Peak memory 205248 kb
Host smart-a12d6a64-e8fc-4e3d-97a9-3f8bd207841f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796584582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2796584582
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1961914371
Short name T488
Test name
Test status
Simulation time 528910833 ps
CPU time 5.02 seconds
Started Jul 15 06:56:14 PM PDT 24
Finished Jul 15 06:56:20 PM PDT 24
Peak memory 235632 kb
Host smart-0663ec9a-66fa-4c80-98ae-9b5ad2b55859
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961914371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1961914371
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1940433091
Short name T1206
Test name
Test status
Simulation time 39777085976 ps
CPU time 413.48 seconds
Started Jul 15 06:56:11 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 1525096 kb
Host smart-4848dd4b-4218-451a-91a0-5beb32ceaa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940433091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1940433091
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3465651501
Short name T1588
Test name
Test status
Simulation time 493431716 ps
CPU time 9.73 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 205500 kb
Host smart-6b5f4b60-0191-49ff-92d6-bb3d2e034ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465651501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3465651501
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.1440168804
Short name T1365
Test name
Test status
Simulation time 80734912 ps
CPU time 0.66 seconds
Started Jul 15 06:56:13 PM PDT 24
Finished Jul 15 06:56:14 PM PDT 24
Peak memory 205224 kb
Host smart-bdee31ab-aeca-498d-9343-84813f3bcbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440168804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1440168804
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.877420614
Short name T658
Test name
Test status
Simulation time 6710588419 ps
CPU time 66.02 seconds
Started Jul 15 06:56:21 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 223528 kb
Host smart-04caca76-b411-47a6-a00f-9405d3223077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877420614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.877420614
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3524621504
Short name T475
Test name
Test status
Simulation time 783960177 ps
CPU time 4.63 seconds
Started Jul 15 06:56:13 PM PDT 24
Finished Jul 15 06:56:18 PM PDT 24
Peak memory 205436 kb
Host smart-0abf1cf8-80f3-450c-bd23-16f1a357deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524621504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3524621504
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.4186899156
Short name T324
Test name
Test status
Simulation time 2155807900 ps
CPU time 102.22 seconds
Started Jul 15 06:56:12 PM PDT 24
Finished Jul 15 06:57:55 PM PDT 24
Peak memory 439700 kb
Host smart-b360a960-11f4-4b97-b84f-6f872b9d630f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186899156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4186899156
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3165354986
Short name T639
Test name
Test status
Simulation time 2470772818 ps
CPU time 11.13 seconds
Started Jul 15 06:56:21 PM PDT 24
Finished Jul 15 06:56:32 PM PDT 24
Peak memory 213804 kb
Host smart-3d3fad68-502b-481e-9a97-212eed26102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165354986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3165354986
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3518128412
Short name T466
Test name
Test status
Simulation time 5007387169 ps
CPU time 5.27 seconds
Started Jul 15 06:56:20 PM PDT 24
Finished Jul 15 06:56:26 PM PDT 24
Peak memory 213956 kb
Host smart-aa124515-2a2b-4928-8a49-7cd53eb2e412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518128412 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3518128412
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.528035100
Short name T95
Test name
Test status
Simulation time 1964055248 ps
CPU time 1.77 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:20 PM PDT 24
Peak memory 212256 kb
Host smart-dee22d07-bbfa-4362-af5a-68dcbccbd351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528035100 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.528035100
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.955233549
Short name T993
Test name
Test status
Simulation time 285326179 ps
CPU time 1.55 seconds
Started Jul 15 06:56:19 PM PDT 24
Finished Jul 15 06:56:21 PM PDT 24
Peak memory 209040 kb
Host smart-efd44cf7-27c2-4ad3-bfa6-ca178b2a0b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955233549 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.955233549
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.3362673062
Short name T785
Test name
Test status
Simulation time 3735706176 ps
CPU time 2.96 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:21 PM PDT 24
Peak memory 205668 kb
Host smart-fce25c3c-4bc6-47d9-8cac-7a39eb703d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362673062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3362673062
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.1774622959
Short name T431
Test name
Test status
Simulation time 721358248 ps
CPU time 1.45 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:20 PM PDT 24
Peak memory 205360 kb
Host smart-18b4ca0d-c8c7-48be-aaf0-2c995c59e8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774622959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1774622959
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1743453046
Short name T1600
Test name
Test status
Simulation time 3848459732 ps
CPU time 5.71 seconds
Started Jul 15 06:56:21 PM PDT 24
Finished Jul 15 06:56:27 PM PDT 24
Peak memory 219360 kb
Host smart-0efe6149-a050-48ab-a58a-f9e68f326955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743453046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1743453046
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.82444609
Short name T1705
Test name
Test status
Simulation time 19503431762 ps
CPU time 451.67 seconds
Started Jul 15 06:56:19 PM PDT 24
Finished Jul 15 07:03:52 PM PDT 24
Peak memory 4618204 kb
Host smart-88b1db67-77df-4311-adc5-4d396cf64436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82444609 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.82444609
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.2845778236
Short name T1425
Test name
Test status
Simulation time 1931798927 ps
CPU time 2.72 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:21 PM PDT 24
Peak memory 213908 kb
Host smart-ccb42be2-c064-49ce-950c-31872658057b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845778236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.2845778236
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.852729574
Short name T530
Test name
Test status
Simulation time 2143472772 ps
CPU time 2.52 seconds
Started Jul 15 06:56:19 PM PDT 24
Finished Jul 15 06:56:22 PM PDT 24
Peak memory 205652 kb
Host smart-eab36cea-d44a-42bd-a394-d100099e0b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852729574 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.852729574
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.1336827503
Short name T1142
Test name
Test status
Simulation time 2144061439 ps
CPU time 4.56 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:23 PM PDT 24
Peak memory 210232 kb
Host smart-0247aee0-4217-4f34-bfb0-5180f7a82840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336827503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.1336827503
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.3706259852
Short name T498
Test name
Test status
Simulation time 496574376 ps
CPU time 2.31 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:20 PM PDT 24
Peak memory 205472 kb
Host smart-42bba7ec-f728-4737-9c98-2b2f102c273c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706259852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.3706259852
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1769636450
Short name T761
Test name
Test status
Simulation time 1408210793 ps
CPU time 23.14 seconds
Started Jul 15 06:56:12 PM PDT 24
Finished Jul 15 06:56:35 PM PDT 24
Peak memory 213840 kb
Host smart-7daae438-c082-484a-af04-e661bcf22491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769636450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1769636450
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.599445627
Short name T1412
Test name
Test status
Simulation time 84362511658 ps
CPU time 89.17 seconds
Started Jul 15 06:56:20 PM PDT 24
Finished Jul 15 06:57:49 PM PDT 24
Peak memory 416392 kb
Host smart-8bdd6471-dba5-4045-a263-8df6645d8e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599445627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.599445627
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3942136043
Short name T600
Test name
Test status
Simulation time 5257177146 ps
CPU time 24.6 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:43 PM PDT 24
Peak memory 230244 kb
Host smart-f32a3a2a-0335-4a88-bdf7-139d2ff2c3d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942136043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3942136043
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3031921406
Short name T646
Test name
Test status
Simulation time 49079178646 ps
CPU time 142.82 seconds
Started Jul 15 06:56:13 PM PDT 24
Finished Jul 15 06:58:36 PM PDT 24
Peak memory 1824284 kb
Host smart-0c333816-4cda-42f0-bc64-c75ec917eec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031921406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3031921406
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3442106232
Short name T1134
Test name
Test status
Simulation time 2701266747 ps
CPU time 7.77 seconds
Started Jul 15 06:56:20 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 231680 kb
Host smart-4e5f31e9-816d-4637-899a-69c1ebaf61c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442106232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3442106232
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.2201461912
Short name T290
Test name
Test status
Simulation time 109432399 ps
CPU time 2.42 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:19 PM PDT 24
Peak memory 205664 kb
Host smart-c906a81e-4e2a-4172-b2aa-9ce5b4a0606f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201461912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2201461912
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3879635157
Short name T1632
Test name
Test status
Simulation time 37065685 ps
CPU time 0.62 seconds
Started Jul 15 06:56:31 PM PDT 24
Finished Jul 15 06:56:32 PM PDT 24
Peak memory 204740 kb
Host smart-01c5ce15-abd4-46bb-b72f-d31f8f2655fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879635157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3879635157
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.842698013
Short name T22
Test name
Test status
Simulation time 166860686 ps
CPU time 3.26 seconds
Started Jul 15 06:56:22 PM PDT 24
Finished Jul 15 06:56:25 PM PDT 24
Peak memory 213700 kb
Host smart-40cf2f26-7e34-4099-ae2e-419fad7a994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842698013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.842698013
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2619615687
Short name T1208
Test name
Test status
Simulation time 6049094093 ps
CPU time 12.33 seconds
Started Jul 15 06:56:24 PM PDT 24
Finished Jul 15 06:56:37 PM PDT 24
Peak memory 312992 kb
Host smart-d83c60eb-0786-40ba-aeab-cdcb2f439ea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619615687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2619615687
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2469634410
Short name T486
Test name
Test status
Simulation time 3514401718 ps
CPU time 200.55 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:59:39 PM PDT 24
Peak memory 411728 kb
Host smart-a0981f39-00ef-4990-85fd-89489c39ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469634410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2469634410
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1270993524
Short name T818
Test name
Test status
Simulation time 15094221897 ps
CPU time 77.85 seconds
Started Jul 15 06:56:20 PM PDT 24
Finished Jul 15 06:57:38 PM PDT 24
Peak memory 683228 kb
Host smart-cd8acaaa-cb29-4db2-b743-b5ec8855ccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270993524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1270993524
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1621699352
Short name T1324
Test name
Test status
Simulation time 941071129 ps
CPU time 0.95 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:56:20 PM PDT 24
Peak memory 205160 kb
Host smart-bb6d771d-332b-4f9d-b5bb-24842e32fb48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621699352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1621699352
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1635483962
Short name T184
Test name
Test status
Simulation time 220587845 ps
CPU time 4.49 seconds
Started Jul 15 06:56:24 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 239652 kb
Host smart-e633edeb-b736-47da-a2f6-109c12afe86e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635483962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1635483962
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3133384438
Short name T787
Test name
Test status
Simulation time 65424804394 ps
CPU time 86.28 seconds
Started Jul 15 06:56:25 PM PDT 24
Finished Jul 15 06:57:52 PM PDT 24
Peak memory 921944 kb
Host smart-0340ea4a-8bbf-4e27-a525-8bc9a47c2a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133384438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3133384438
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3276179104
Short name T1081
Test name
Test status
Simulation time 942198270 ps
CPU time 6.44 seconds
Started Jul 15 06:56:31 PM PDT 24
Finished Jul 15 06:56:38 PM PDT 24
Peak memory 205460 kb
Host smart-bdad092c-d0e8-4e8f-8845-9ec507b60112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276179104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3276179104
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.644304611
Short name T770
Test name
Test status
Simulation time 27947464 ps
CPU time 0.67 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:18 PM PDT 24
Peak memory 205252 kb
Host smart-09ae9dcd-8603-42e2-98a3-0f68773cad6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644304611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.644304611
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1559365428
Short name T44
Test name
Test status
Simulation time 7573529290 ps
CPU time 459.06 seconds
Started Jul 15 06:56:20 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 1389644 kb
Host smart-511e3dde-7d23-41e9-b1ed-9b2e07182054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559365428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1559365428
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.2435843032
Short name T436
Test name
Test status
Simulation time 1188208478 ps
CPU time 5.93 seconds
Started Jul 15 06:56:17 PM PDT 24
Finished Jul 15 06:56:24 PM PDT 24
Peak memory 254540 kb
Host smart-6e8255f7-2903-4423-849e-b09b393e5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435843032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.2435843032
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3327775196
Short name T1554
Test name
Test status
Simulation time 6714507160 ps
CPU time 65.74 seconds
Started Jul 15 06:56:18 PM PDT 24
Finished Jul 15 06:57:25 PM PDT 24
Peak memory 339652 kb
Host smart-f4965664-1986-4c17-ba2f-894d309955cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327775196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3327775196
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2648642708
Short name T1479
Test name
Test status
Simulation time 539487424 ps
CPU time 10.54 seconds
Started Jul 15 06:56:22 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 213708 kb
Host smart-310e050e-c379-482c-a082-3969d431de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648642708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2648642708
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.708389664
Short name T757
Test name
Test status
Simulation time 2405283893 ps
CPU time 6.16 seconds
Started Jul 15 06:56:30 PM PDT 24
Finished Jul 15 06:56:37 PM PDT 24
Peak memory 213916 kb
Host smart-53dd5fa2-a53b-4f68-9fdc-01d93af534af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708389664 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.708389664
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2259761309
Short name T319
Test name
Test status
Simulation time 906547673 ps
CPU time 1.31 seconds
Started Jul 15 06:56:31 PM PDT 24
Finished Jul 15 06:56:32 PM PDT 24
Peak memory 208332 kb
Host smart-30ed7026-7ea5-4a05-a70a-998373e2ad2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259761309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2259761309
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1054427257
Short name T304
Test name
Test status
Simulation time 160776640 ps
CPU time 0.94 seconds
Started Jul 15 06:56:33 PM PDT 24
Finished Jul 15 06:56:35 PM PDT 24
Peak memory 205464 kb
Host smart-7748e39a-a843-4a2a-b7d8-0d1823472553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054427257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1054427257
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.218978427
Short name T1689
Test name
Test status
Simulation time 519329084 ps
CPU time 2.76 seconds
Started Jul 15 06:56:33 PM PDT 24
Finished Jul 15 06:56:36 PM PDT 24
Peak memory 205616 kb
Host smart-f72bfba2-6410-4800-bfcd-680b4f3f5b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218978427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.218978427
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.3481622865
Short name T963
Test name
Test status
Simulation time 123491310 ps
CPU time 0.84 seconds
Started Jul 15 06:56:32 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 205504 kb
Host smart-28b44cba-2a2f-4d8f-a433-12a70b8eb229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481622865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.3481622865
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.4153618471
Short name T520
Test name
Test status
Simulation time 1556080922 ps
CPU time 2.41 seconds
Started Jul 15 06:56:32 PM PDT 24
Finished Jul 15 06:56:34 PM PDT 24
Peak memory 213860 kb
Host smart-d6b9c575-89f9-4422-9c7b-7aff9256b5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153618471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.4153618471
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1350436718
Short name T637
Test name
Test status
Simulation time 12492222775 ps
CPU time 5.48 seconds
Started Jul 15 06:56:23 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 216016 kb
Host smart-c05ba92a-6bdc-48be-95ad-39512416ff0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350436718 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1350436718
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3740450335
Short name T2
Test name
Test status
Simulation time 14014548965 ps
CPU time 308.9 seconds
Started Jul 15 06:56:24 PM PDT 24
Finished Jul 15 07:01:33 PM PDT 24
Peak memory 3514708 kb
Host smart-b1f7ab05-485b-46c4-86e5-c20986fb5bcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740450335 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3740450335
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.2717289146
Short name T1512
Test name
Test status
Simulation time 415387491 ps
CPU time 2.43 seconds
Started Jul 15 06:56:30 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 213892 kb
Host smart-8c8cb2eb-b048-44f7-95e1-004b3809e95a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717289146 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.2717289146
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.2338583739
Short name T1361
Test name
Test status
Simulation time 1983411034 ps
CPU time 2.35 seconds
Started Jul 15 06:56:30 PM PDT 24
Finished Jul 15 06:56:33 PM PDT 24
Peak memory 205580 kb
Host smart-1defca84-9fdd-4377-8fef-3a79a5611354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338583739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2338583739
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.798652386
Short name T1158
Test name
Test status
Simulation time 8829457052 ps
CPU time 4.65 seconds
Started Jul 15 06:56:31 PM PDT 24
Finished Jul 15 06:56:36 PM PDT 24
Peak memory 222040 kb
Host smart-f688eccc-a8ac-4393-a9db-605837ee94d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798652386 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_perf.798652386
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.2394138022
Short name T293
Test name
Test status
Simulation time 4406381183 ps
CPU time 2.02 seconds
Started Jul 15 06:56:28 PM PDT 24
Finished Jul 15 06:56:31 PM PDT 24
Peak memory 205524 kb
Host smart-e87a303e-a912-4d1f-91f8-73e9f439aa32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394138022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.2394138022
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.834547108
Short name T969
Test name
Test status
Simulation time 3441375056 ps
CPU time 26.66 seconds
Started Jul 15 06:56:25 PM PDT 24
Finished Jul 15 06:56:52 PM PDT 24
Peak memory 213924 kb
Host smart-a923804f-8138-43f3-96e8-2d5848990588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834547108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.834547108
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.2206097408
Short name T1568
Test name
Test status
Simulation time 47967561507 ps
CPU time 121.81 seconds
Started Jul 15 06:56:33 PM PDT 24
Finished Jul 15 06:58:36 PM PDT 24
Peak memory 971056 kb
Host smart-744aa223-77e7-4a2a-9c9d-62ccf359899b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206097408 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.2206097408
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.396069437
Short name T931
Test name
Test status
Simulation time 660496101 ps
CPU time 15.75 seconds
Started Jul 15 06:56:26 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 205764 kb
Host smart-5a32213c-6f89-4ec1-988f-18ec9102e8ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396069437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.396069437
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.902989225
Short name T464
Test name
Test status
Simulation time 16035976410 ps
CPU time 15.68 seconds
Started Jul 15 06:56:23 PM PDT 24
Finished Jul 15 06:56:39 PM PDT 24
Peak memory 205656 kb
Host smart-de23ca2d-be3a-47ee-93f2-5a5f6c0fd0b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902989225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.902989225
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3198374900
Short name T943
Test name
Test status
Simulation time 1603564303 ps
CPU time 22.1 seconds
Started Jul 15 06:56:23 PM PDT 24
Finished Jul 15 06:56:46 PM PDT 24
Peak memory 304756 kb
Host smart-05831593-2d9e-4224-a0c9-5957a69dfdeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198374900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3198374900
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3098208990
Short name T1702
Test name
Test status
Simulation time 3552024753 ps
CPU time 6.75 seconds
Started Jul 15 06:56:21 PM PDT 24
Finished Jul 15 06:56:28 PM PDT 24
Peak memory 222112 kb
Host smart-e46ad20b-b7a3-4d8b-814e-3e690bcebe7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098208990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3098208990
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.2180806956
Short name T738
Test name
Test status
Simulation time 362224266 ps
CPU time 5.27 seconds
Started Jul 15 06:56:30 PM PDT 24
Finished Jul 15 06:56:35 PM PDT 24
Peak memory 206112 kb
Host smart-112cd4aa-f65f-4d07-8192-897e926349e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180806956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.2180806956
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1849511898
Short name T654
Test name
Test status
Simulation time 59979541 ps
CPU time 0.63 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:04 PM PDT 24
Peak memory 204804 kb
Host smart-270ffc7b-13fd-461c-8d86-8891fc543ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849511898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1849511898
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3469743339
Short name T501
Test name
Test status
Simulation time 119820119 ps
CPU time 1.54 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:51:54 PM PDT 24
Peak memory 213792 kb
Host smart-117fe22a-58b2-4293-8b93-b30f98cde2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469743339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3469743339
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2103086464
Short name T835
Test name
Test status
Simulation time 545988686 ps
CPU time 6.7 seconds
Started Jul 15 06:51:52 PM PDT 24
Finished Jul 15 06:52:00 PM PDT 24
Peak memory 263588 kb
Host smart-d5d3519f-c4c1-4994-9406-8443616ba30f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103086464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2103086464
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.4119842156
Short name T1011
Test name
Test status
Simulation time 47641997285 ps
CPU time 67.26 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:52:59 PM PDT 24
Peak memory 326908 kb
Host smart-d073fa4e-b4e2-42c7-8575-2871ab34e9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119842156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.4119842156
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.430810874
Short name T731
Test name
Test status
Simulation time 1313976838 ps
CPU time 37.49 seconds
Started Jul 15 06:51:52 PM PDT 24
Finished Jul 15 06:52:30 PM PDT 24
Peak memory 453100 kb
Host smart-a2bde1d3-84bb-4d5d-a31c-cbf23b32e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430810874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.430810874
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3923435492
Short name T1177
Test name
Test status
Simulation time 250952932 ps
CPU time 1.11 seconds
Started Jul 15 06:51:49 PM PDT 24
Finished Jul 15 06:51:51 PM PDT 24
Peak memory 205244 kb
Host smart-7e6d69b0-2883-4c83-aea1-a8d338334666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923435492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3923435492
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3335895224
Short name T865
Test name
Test status
Simulation time 403755442 ps
CPU time 9.57 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:52:02 PM PDT 24
Peak memory 205576 kb
Host smart-0acf3f83-cb20-4d43-8733-57d294f7b04f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335895224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3335895224
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1570587374
Short name T428
Test name
Test status
Simulation time 6479766735 ps
CPU time 206.62 seconds
Started Jul 15 06:51:49 PM PDT 24
Finished Jul 15 06:55:16 PM PDT 24
Peak memory 980068 kb
Host smart-f38efb10-0ad9-411b-baae-3253b4e121a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570587374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1570587374
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2406608700
Short name T260
Test name
Test status
Simulation time 1394748842 ps
CPU time 13.81 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 205504 kb
Host smart-be132df6-089d-48bc-a3db-7ae20cd1ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406608700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2406608700
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.2580253875
Short name T144
Test name
Test status
Simulation time 29932320 ps
CPU time 0.68 seconds
Started Jul 15 06:51:53 PM PDT 24
Finished Jul 15 06:51:55 PM PDT 24
Peak memory 205232 kb
Host smart-5bbffff5-bca0-44e4-988d-bc00770ec084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580253875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2580253875
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3544122728
Short name T390
Test name
Test status
Simulation time 2667667123 ps
CPU time 144.12 seconds
Started Jul 15 06:51:50 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 787220 kb
Host smart-e7d906ea-fe05-4eda-9b96-1475f6517417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544122728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3544122728
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.2186658311
Short name T451
Test name
Test status
Simulation time 1078418165 ps
CPU time 15.61 seconds
Started Jul 15 06:51:52 PM PDT 24
Finished Jul 15 06:52:08 PM PDT 24
Peak memory 205612 kb
Host smart-4ccc2fa4-39a7-4ecf-ba1c-ca092ebc1fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186658311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2186658311
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2273302091
Short name T797
Test name
Test status
Simulation time 7190154411 ps
CPU time 90.21 seconds
Started Jul 15 06:51:52 PM PDT 24
Finished Jul 15 06:53:23 PM PDT 24
Peak memory 401352 kb
Host smart-4332ee21-eb93-46d9-a6d7-860608aec4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273302091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2273302091
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3866791184
Short name T332
Test name
Test status
Simulation time 1413998250 ps
CPU time 15.46 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:52:08 PM PDT 24
Peak memory 213608 kb
Host smart-3df9bf20-7c25-466e-bdbb-47186e3d5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866791184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3866791184
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3556525063
Short name T196
Test name
Test status
Simulation time 75335184 ps
CPU time 0.95 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:05 PM PDT 24
Peak memory 223796 kb
Host smart-9e54a608-4bd6-47ae-a104-b6a0e1b00a8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556525063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3556525063
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.360510522
Short name T1470
Test name
Test status
Simulation time 1154473439 ps
CPU time 6.91 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:09 PM PDT 24
Peak memory 222020 kb
Host smart-9c25d142-367f-419f-b0c0-7efa72c89e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360510522 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.360510522
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3916803385
Short name T484
Test name
Test status
Simulation time 213288047 ps
CPU time 1.36 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:03 PM PDT 24
Peak memory 205564 kb
Host smart-a1cbc3f5-6b22-4363-b71f-b41c0f395a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916803385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3916803385
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3010001670
Short name T604
Test name
Test status
Simulation time 121956798 ps
CPU time 0.99 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:06 PM PDT 24
Peak memory 205472 kb
Host smart-67526d13-f4db-4db2-8a80-2e2edc2675a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010001670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3010001670
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.674314931
Short name T1447
Test name
Test status
Simulation time 343291962 ps
CPU time 2.28 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:07 PM PDT 24
Peak memory 205644 kb
Host smart-8cefa988-59ba-45ee-a001-43b91f8cd261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674314931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.674314931
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.2736733491
Short name T972
Test name
Test status
Simulation time 277676232 ps
CPU time 1.22 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:02 PM PDT 24
Peak memory 205608 kb
Host smart-52b31bb6-9f4a-4bbe-ae40-1c0e65a1d641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736733491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.2736733491
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3962092759
Short name T977
Test name
Test status
Simulation time 26644131462 ps
CPU time 8.52 seconds
Started Jul 15 06:51:50 PM PDT 24
Finished Jul 15 06:51:59 PM PDT 24
Peak memory 230304 kb
Host smart-0317e2b7-c736-430a-b163-9d7f2909ca0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962092759 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3962092759
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2325426573
Short name T1671
Test name
Test status
Simulation time 5905226245 ps
CPU time 12.74 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:16 PM PDT 24
Peak memory 205772 kb
Host smart-8d207da0-9bc9-488d-bd51-49b1feca53fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325426573 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2325426573
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.3807014525
Short name T1627
Test name
Test status
Simulation time 561278529 ps
CPU time 2.99 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:06 PM PDT 24
Peak memory 213840 kb
Host smart-f5284fc8-22a8-45f9-888d-309aeaa69782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807014525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.3807014525
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.75823538
Short name T1716
Test name
Test status
Simulation time 535979170 ps
CPU time 2.77 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:04 PM PDT 24
Peak memory 205600 kb
Host smart-aa7b0336-7e5e-4c54-b1bb-8aa078a96ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75823538 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_nack_acqfull_addr.75823538
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.1878625688
Short name T1225
Test name
Test status
Simulation time 813748731 ps
CPU time 3.03 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:05 PM PDT 24
Peak memory 213896 kb
Host smart-ec95f6bb-ee71-4fd1-927d-b570c928f5b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878625688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.1878625688
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.3874457806
Short name T1224
Test name
Test status
Simulation time 455334615 ps
CPU time 2.21 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:07 PM PDT 24
Peak memory 205412 kb
Host smart-a61f8488-ebb0-4f4d-8f5e-eb47ad3a5235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874457806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.3874457806
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3987698000
Short name T88
Test name
Test status
Simulation time 4288973618 ps
CPU time 32.12 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:52:25 PM PDT 24
Peak memory 213924 kb
Host smart-98d69c1a-f1da-4633-b2e4-76f766f7516a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987698000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3987698000
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1152013385
Short name T1023
Test name
Test status
Simulation time 53735785301 ps
CPU time 744.21 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 07:04:29 PM PDT 24
Peak memory 4449852 kb
Host smart-a65c9172-1088-4f5e-999e-c45ddd65e883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152013385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1152013385
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.937875153
Short name T1409
Test name
Test status
Simulation time 4469607071 ps
CPU time 21.47 seconds
Started Jul 15 06:51:48 PM PDT 24
Finished Jul 15 06:52:10 PM PDT 24
Peak memory 229296 kb
Host smart-33a7ac77-775c-4f43-9285-5a75349a8432
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937875153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.937875153
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1657107856
Short name T825
Test name
Test status
Simulation time 13908821485 ps
CPU time 26.71 seconds
Started Jul 15 06:51:50 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 205728 kb
Host smart-f7f2079f-4de0-4ff5-add7-fcf1eecae005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657107856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1657107856
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3464908043
Short name T1173
Test name
Test status
Simulation time 1267291364 ps
CPU time 1.98 seconds
Started Jul 15 06:51:51 PM PDT 24
Finished Jul 15 06:51:54 PM PDT 24
Peak memory 213756 kb
Host smart-228526af-05ca-4311-9339-67e6aac3538f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464908043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3464908043
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3986363436
Short name T935
Test name
Test status
Simulation time 2227419319 ps
CPU time 6.61 seconds
Started Jul 15 06:52:00 PM PDT 24
Finished Jul 15 06:52:07 PM PDT 24
Peak memory 219024 kb
Host smart-116ad693-da4d-4069-92ef-f2bb2b23463e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986363436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3986363436
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.2711370300
Short name T63
Test name
Test status
Simulation time 170907041 ps
CPU time 2.41 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:06 PM PDT 24
Peak memory 205620 kb
Host smart-4ed3c991-b0ee-43e3-98e1-a66b7f08075a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711370300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2711370300
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1079609979
Short name T644
Test name
Test status
Simulation time 16221375 ps
CPU time 0.61 seconds
Started Jul 15 06:56:46 PM PDT 24
Finished Jul 15 06:56:47 PM PDT 24
Peak memory 204716 kb
Host smart-f654182c-fcbc-4ac3-b066-25d7174e5b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079609979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1079609979
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2056496841
Short name T1665
Test name
Test status
Simulation time 499159447 ps
CPU time 4.74 seconds
Started Jul 15 06:56:38 PM PDT 24
Finished Jul 15 06:56:43 PM PDT 24
Peak memory 243716 kb
Host smart-44011661-9785-443c-8e59-f0d90cae470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056496841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2056496841
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3320529925
Short name T314
Test name
Test status
Simulation time 107181803 ps
CPU time 2.5 seconds
Started Jul 15 06:56:38 PM PDT 24
Finished Jul 15 06:56:41 PM PDT 24
Peak memory 219316 kb
Host smart-ef18a2ca-6205-424e-b8b1-f4f660333d21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320529925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3320529925
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.4044255816
Short name T1511
Test name
Test status
Simulation time 10388689662 ps
CPU time 159.09 seconds
Started Jul 15 06:56:37 PM PDT 24
Finished Jul 15 06:59:17 PM PDT 24
Peak memory 530108 kb
Host smart-ba5e69ba-b213-4992-9308-0d5fbd2356ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044255816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4044255816
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3839318910
Short name T416
Test name
Test status
Simulation time 3727443706 ps
CPU time 95.06 seconds
Started Jul 15 06:56:34 PM PDT 24
Finished Jul 15 06:58:09 PM PDT 24
Peak memory 809924 kb
Host smart-6210533f-0b96-4e3b-9b6b-a868c5e2626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839318910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3839318910
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1515766959
Short name T93
Test name
Test status
Simulation time 833815665 ps
CPU time 1.35 seconds
Started Jul 15 06:56:32 PM PDT 24
Finished Jul 15 06:56:34 PM PDT 24
Peak memory 205340 kb
Host smart-b3c422c6-3502-42b8-a24e-547b32d59495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515766959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1515766959
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2406238953
Short name T827
Test name
Test status
Simulation time 326458888 ps
CPU time 8.83 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:49 PM PDT 24
Peak memory 232268 kb
Host smart-c27fad02-d104-404a-8991-78ffa0e9c8e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406238953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2406238953
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.4084936995
Short name T116
Test name
Test status
Simulation time 5271772539 ps
CPU time 129.29 seconds
Started Jul 15 06:56:34 PM PDT 24
Finished Jul 15 06:58:44 PM PDT 24
Peak memory 1397536 kb
Host smart-b4a61177-d46f-4e46-8284-cf4e92976ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084936995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.4084936995
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3604302880
Short name T1146
Test name
Test status
Simulation time 252691749 ps
CPU time 8.39 seconds
Started Jul 15 06:56:40 PM PDT 24
Finished Jul 15 06:56:49 PM PDT 24
Peak memory 205556 kb
Host smart-777fedfb-2509-478f-9e8e-e35b3ed78c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604302880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3604302880
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3956497513
Short name T461
Test name
Test status
Simulation time 7268017279 ps
CPU time 7.93 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 213828 kb
Host smart-f4c94012-3360-414c-b164-e4f1ced34d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956497513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3956497513
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1577673998
Short name T1098
Test name
Test status
Simulation time 134695179 ps
CPU time 1.79 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 205672 kb
Host smart-af88e45d-9805-4ba4-b3f5-4f5f17e2deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577673998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1577673998
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1977067135
Short name T50
Test name
Test status
Simulation time 1668007062 ps
CPU time 28.7 seconds
Started Jul 15 06:56:29 PM PDT 24
Finished Jul 15 06:56:59 PM PDT 24
Peak memory 346328 kb
Host smart-e4194c5b-d724-4927-9c04-6735142679e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977067135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1977067135
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2376041244
Short name T51
Test name
Test status
Simulation time 486981057 ps
CPU time 9.09 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:49 PM PDT 24
Peak memory 213656 kb
Host smart-6a06187b-e06a-4e77-bf6c-27beb6aeea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376041244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2376041244
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1987678455
Short name T393
Test name
Test status
Simulation time 555856331 ps
CPU time 2.87 seconds
Started Jul 15 06:56:38 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 213852 kb
Host smart-8e1667c5-9071-404d-a71b-62f1554424af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987678455 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1987678455
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1772004883
Short name T1646
Test name
Test status
Simulation time 178059522 ps
CPU time 1.07 seconds
Started Jul 15 06:56:36 PM PDT 24
Finished Jul 15 06:56:37 PM PDT 24
Peak memory 205396 kb
Host smart-aecdfb0f-3991-4448-9884-b24ba4bd97a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772004883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1772004883
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2554283040
Short name T373
Test name
Test status
Simulation time 3369349524 ps
CPU time 1.69 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:41 PM PDT 24
Peak memory 206740 kb
Host smart-9606523b-a3ae-4ad3-9fce-a631b1c8de2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554283040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2554283040
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.2295620006
Short name T751
Test name
Test status
Simulation time 946776958 ps
CPU time 2.66 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 205596 kb
Host smart-a9e4fd9f-802f-4f68-8434-eee579abb1ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295620006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.2295620006
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.1000167305
Short name T777
Test name
Test status
Simulation time 65098918 ps
CPU time 0.89 seconds
Started Jul 15 06:56:40 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 205372 kb
Host smart-e1ce8130-4c00-4d87-9320-a8070b236679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000167305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1000167305
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2725398478
Short name T920
Test name
Test status
Simulation time 1127850485 ps
CPU time 6.29 seconds
Started Jul 15 06:56:40 PM PDT 24
Finished Jul 15 06:56:47 PM PDT 24
Peak memory 219060 kb
Host smart-d553ca2c-2c58-4ccb-ab86-86399086c3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725398478 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2725398478
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2810402868
Short name T964
Test name
Test status
Simulation time 22746953045 ps
CPU time 68.95 seconds
Started Jul 15 06:56:38 PM PDT 24
Finished Jul 15 06:57:48 PM PDT 24
Peak memory 985316 kb
Host smart-eb68aa04-71c6-4913-9f9d-b0515c054321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810402868 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2810402868
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.1054354035
Short name T872
Test name
Test status
Simulation time 1090460058 ps
CPU time 2.87 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 213920 kb
Host smart-a09b559a-e028-4fb0-8c37-70ea984c72de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054354035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.1054354035
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.4014553588
Short name T838
Test name
Test status
Simulation time 4206180994 ps
CPU time 2.66 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:47 PM PDT 24
Peak memory 205692 kb
Host smart-2616d95a-8e54-4d80-8a95-1cfb9c01a56a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014553588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.4014553588
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_txstretch.2251554682
Short name T57
Test name
Test status
Simulation time 589432302 ps
CPU time 1.42 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:46 PM PDT 24
Peak memory 222100 kb
Host smart-59fcc85a-e8e8-4484-b5d3-8bca70011060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251554682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_nack_txstretch.2251554682
Directory /workspace/30.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3252999902
Short name T1091
Test name
Test status
Simulation time 2236514543 ps
CPU time 4.03 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:56:45 PM PDT 24
Peak memory 213860 kb
Host smart-2d927200-7825-41aa-93e4-623a8197249b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252999902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3252999902
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.361982426
Short name T183
Test name
Test status
Simulation time 1056021005 ps
CPU time 2.44 seconds
Started Jul 15 06:56:46 PM PDT 24
Finished Jul 15 06:56:49 PM PDT 24
Peak memory 205392 kb
Host smart-e127f4ac-3ac8-4ade-80f4-03a0150e92e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361982426 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_smbus_maxlen.361982426
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1253831658
Short name T915
Test name
Test status
Simulation time 3797463041 ps
CPU time 11.39 seconds
Started Jul 15 06:56:38 PM PDT 24
Finished Jul 15 06:56:50 PM PDT 24
Peak memory 213836 kb
Host smart-817ce4cd-12af-4ccd-a7b1-a762f6842a54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253831658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1253831658
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.2960127486
Short name T967
Test name
Test status
Simulation time 3073626962 ps
CPU time 20.13 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:57:00 PM PDT 24
Peak memory 222168 kb
Host smart-9f30c7ea-424e-4b2c-a41f-e4f4a0611e7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960127486 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.2960127486
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.560685684
Short name T325
Test name
Test status
Simulation time 276507443 ps
CPU time 4.78 seconds
Started Jul 15 06:56:37 PM PDT 24
Finished Jul 15 06:56:42 PM PDT 24
Peak memory 205648 kb
Host smart-bc538dd2-8f21-407e-9c3d-4b16d08c2d18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560685684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.560685684
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.651840073
Short name T929
Test name
Test status
Simulation time 63177893173 ps
CPU time 2487.28 seconds
Started Jul 15 06:56:40 PM PDT 24
Finished Jul 15 07:38:09 PM PDT 24
Peak memory 10850596 kb
Host smart-8153a947-86fd-485b-b523-c685624b116f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651840073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.651840073
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1931821793
Short name T391
Test name
Test status
Simulation time 2145631347 ps
CPU time 108.91 seconds
Started Jul 15 06:56:39 PM PDT 24
Finished Jul 15 06:58:28 PM PDT 24
Peak memory 672432 kb
Host smart-9ca6de7a-353a-4be8-973c-577af88881bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931821793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1931821793
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2396833552
Short name T925
Test name
Test status
Simulation time 4502069325 ps
CPU time 6.65 seconds
Started Jul 15 06:56:37 PM PDT 24
Finished Jul 15 06:56:44 PM PDT 24
Peak memory 219552 kb
Host smart-bb1c303f-4b39-4eba-8c86-e295f73a99b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396833552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2396833552
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.168791025
Short name T576
Test name
Test status
Simulation time 289713927 ps
CPU time 3.98 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:49 PM PDT 24
Peak memory 213788 kb
Host smart-fedefbcc-5605-4b56-a6be-bfb2d095f8c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168791025 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.168791025
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.786253692
Short name T590
Test name
Test status
Simulation time 16401135 ps
CPU time 0.61 seconds
Started Jul 15 06:56:49 PM PDT 24
Finished Jul 15 06:56:50 PM PDT 24
Peak memory 204780 kb
Host smart-cd794d62-2b1c-4b43-8b5e-4d22803393e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786253692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.786253692
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2171914522
Short name T989
Test name
Test status
Simulation time 164033997 ps
CPU time 2.69 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 236048 kb
Host smart-b0295db3-d8ad-4995-89bf-cbde74df8c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171914522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2171914522
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3861806477
Short name T805
Test name
Test status
Simulation time 1197085149 ps
CPU time 29.95 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:57:22 PM PDT 24
Peak memory 332064 kb
Host smart-b4b5a6b1-8265-4dd1-bf1c-6aa278c9b4c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861806477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3861806477
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2612997778
Short name T778
Test name
Test status
Simulation time 37543287989 ps
CPU time 92.22 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:58:17 PM PDT 24
Peak memory 649756 kb
Host smart-bf0759ca-bfc5-421b-a7c8-8a7575f79dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612997778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2612997778
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1651798857
Short name T1256
Test name
Test status
Simulation time 2315642295 ps
CPU time 74.1 seconds
Started Jul 15 06:56:48 PM PDT 24
Finished Jul 15 06:58:02 PM PDT 24
Peak memory 695228 kb
Host smart-9e59b1d5-e547-43b9-aada-358d94877b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651798857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1651798857
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1102558603
Short name T557
Test name
Test status
Simulation time 985545541 ps
CPU time 1.08 seconds
Started Jul 15 06:56:42 PM PDT 24
Finished Jul 15 06:56:44 PM PDT 24
Peak memory 205264 kb
Host smart-7562bc34-379c-4a41-8022-d01d68b0b0de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102558603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1102558603
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.647063381
Short name T1597
Test name
Test status
Simulation time 518394280 ps
CPU time 2.86 seconds
Started Jul 15 06:56:45 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 205556 kb
Host smart-4cde45fa-2a21-4aa8-8a86-1d38edf61bbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647063381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
647063381
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1563975266
Short name T1399
Test name
Test status
Simulation time 79608765370 ps
CPU time 296.43 seconds
Started Jul 15 06:56:45 PM PDT 24
Finished Jul 15 07:01:42 PM PDT 24
Peak memory 1199108 kb
Host smart-b5aee066-9cb2-4f0c-abf2-e1410a24cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563975266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1563975266
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3169572437
Short name T1300
Test name
Test status
Simulation time 1972711763 ps
CPU time 6.16 seconds
Started Jul 15 06:56:45 PM PDT 24
Finished Jul 15 06:56:51 PM PDT 24
Peak memory 205560 kb
Host smart-05615b90-0005-4c48-b434-fa1804939414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169572437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3169572437
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.133595866
Short name T772
Test name
Test status
Simulation time 31611601 ps
CPU time 0.66 seconds
Started Jul 15 06:56:47 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 205248 kb
Host smart-4467bcd5-a045-4976-9fc9-66737ff339e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133595866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.133595866
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3681025830
Short name T479
Test name
Test status
Simulation time 7521054139 ps
CPU time 128.55 seconds
Started Jul 15 06:56:43 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 824556 kb
Host smart-310a1d0f-bfca-4757-93d8-1b320226c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681025830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3681025830
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.535788496
Short name T824
Test name
Test status
Simulation time 53703934 ps
CPU time 1.31 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:46 PM PDT 24
Peak memory 228868 kb
Host smart-b7a93412-8b29-425e-bf68-028e4bbf6f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535788496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.535788496
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1645403851
Short name T695
Test name
Test status
Simulation time 2170132220 ps
CPU time 31.35 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:57:24 PM PDT 24
Peak memory 253536 kb
Host smart-8a55b43d-8cc8-4540-afaa-6070bc8f8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645403851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1645403851
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3857273596
Short name T126
Test name
Test status
Simulation time 697066873 ps
CPU time 4.39 seconds
Started Jul 15 06:56:48 PM PDT 24
Finished Jul 15 06:56:53 PM PDT 24
Peak memory 208752 kb
Host smart-f586702f-37b9-4846-b523-9e7816704c7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857273596 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3857273596
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3143394369
Short name T1651
Test name
Test status
Simulation time 986006606 ps
CPU time 1.19 seconds
Started Jul 15 06:56:46 PM PDT 24
Finished Jul 15 06:56:47 PM PDT 24
Peak memory 205704 kb
Host smart-9d189ff2-e146-43e1-bb9b-360b7fa51777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143394369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3143394369
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.4034433288
Short name T1243
Test name
Test status
Simulation time 362645422 ps
CPU time 1.05 seconds
Started Jul 15 06:56:46 PM PDT 24
Finished Jul 15 06:56:48 PM PDT 24
Peak memory 205424 kb
Host smart-dcb65963-1ce8-4391-a1a8-362010d2d1fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034433288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.4034433288
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2423680458
Short name T711
Test name
Test status
Simulation time 268830866 ps
CPU time 1.79 seconds
Started Jul 15 06:56:48 PM PDT 24
Finished Jul 15 06:56:50 PM PDT 24
Peak memory 205532 kb
Host smart-ed50f4e0-1703-48f5-b1cc-2ea5f27ed6e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423680458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2423680458
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.1357868710
Short name T1433
Test name
Test status
Simulation time 511710371 ps
CPU time 1.41 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:56:54 PM PDT 24
Peak memory 205484 kb
Host smart-052470e5-f279-429e-941d-6eb984728cf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357868710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.1357868710
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1855718880
Short name T1070
Test name
Test status
Simulation time 1093032724 ps
CPU time 6.81 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:52 PM PDT 24
Peak memory 221996 kb
Host smart-fb4a9542-530f-42e1-a8dd-3923fda7cea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855718880 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1855718880
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3482503019
Short name T1370
Test name
Test status
Simulation time 6068602500 ps
CPU time 12.93 seconds
Started Jul 15 06:56:45 PM PDT 24
Finished Jul 15 06:56:59 PM PDT 24
Peak memory 205696 kb
Host smart-8f319241-e660-40bc-9423-f1435654a367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482503019 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3482503019
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.2001040070
Short name T1461
Test name
Test status
Simulation time 998421905 ps
CPU time 2.87 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 213804 kb
Host smart-94dbcb69-d988-472e-862f-7c5200b664d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001040070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.2001040070
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.237764901
Short name T907
Test name
Test status
Simulation time 1163888581 ps
CPU time 2.71 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 205604 kb
Host smart-7e6b6a0a-16bc-4e37-8656-6104610df01e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237764901 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.237764901
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.3734899953
Short name T1055
Test name
Test status
Simulation time 1669053249 ps
CPU time 1.62 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:53 PM PDT 24
Peak memory 222332 kb
Host smart-a0ea37bc-b4d3-4741-89a2-e767a32d25ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734899953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_txstretch.3734899953
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.4062260992
Short name T308
Test name
Test status
Simulation time 1636887390 ps
CPU time 4.94 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:50 PM PDT 24
Peak memory 217076 kb
Host smart-d4bd9fa8-47ab-4114-9540-995135713db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062260992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.4062260992
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.1702632984
Short name T349
Test name
Test status
Simulation time 488284233 ps
CPU time 2.15 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 205388 kb
Host smart-c8740b8c-05e8-4ef5-8d09-fc2824e1e549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702632984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.1702632984
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1568213416
Short name T1427
Test name
Test status
Simulation time 4381899130 ps
CPU time 34.8 seconds
Started Jul 15 06:56:43 PM PDT 24
Finished Jul 15 06:57:18 PM PDT 24
Peak memory 218132 kb
Host smart-b110f2b1-ee39-48b5-9821-3d01e371aa9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568213416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1568213416
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.2496256708
Short name T65
Test name
Test status
Simulation time 53422237606 ps
CPU time 613.87 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 3923804 kb
Host smart-2f80ef57-68d4-45a7-8205-3458c8cebbd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496256708 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.2496256708
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.98372791
Short name T930
Test name
Test status
Simulation time 852191227 ps
CPU time 20.29 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 213820 kb
Host smart-52e7f710-f290-447a-9cec-b206cb0fc959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98372791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_rd.98372791
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2084738812
Short name T1739
Test name
Test status
Simulation time 10522925224 ps
CPU time 11.7 seconds
Started Jul 15 06:56:44 PM PDT 24
Finished Jul 15 06:56:56 PM PDT 24
Peak memory 205708 kb
Host smart-3d73fcf3-1de6-4203-aed5-a76145dee5c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084738812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2084738812
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3594486690
Short name T1718
Test name
Test status
Simulation time 1916874477 ps
CPU time 1.87 seconds
Started Jul 15 06:56:43 PM PDT 24
Finished Jul 15 06:56:46 PM PDT 24
Peak memory 211536 kb
Host smart-0084ffa4-429b-4580-a448-072bf0b88593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594486690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3594486690
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1577858659
Short name T1469
Test name
Test status
Simulation time 5146385203 ps
CPU time 6.39 seconds
Started Jul 15 06:56:48 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 213972 kb
Host smart-cb3f35e8-1ab3-4a87-965a-623148dc8f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577858659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1577858659
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1745500887
Short name T1508
Test name
Test status
Simulation time 77736433 ps
CPU time 1.5 seconds
Started Jul 15 06:56:53 PM PDT 24
Finished Jul 15 06:56:55 PM PDT 24
Peak memory 205652 kb
Host smart-b6e496a9-f5d9-45d1-81ef-fc7be3385833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745500887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1745500887
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.894751333
Short name T1242
Test name
Test status
Simulation time 62932714 ps
CPU time 0.63 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 204880 kb
Host smart-69c5d0c8-e905-411b-9a5f-f102165d888e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894751333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.894751333
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1411573849
Short name T649
Test name
Test status
Simulation time 132229874 ps
CPU time 2.33 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:54 PM PDT 24
Peak memory 221960 kb
Host smart-b02055a1-2739-4b68-b2ff-4f4dfea42327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411573849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1411573849
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1111893010
Short name T98
Test name
Test status
Simulation time 450972265 ps
CPU time 15.26 seconds
Started Jul 15 06:56:53 PM PDT 24
Finished Jul 15 06:57:09 PM PDT 24
Peak memory 266260 kb
Host smart-436db6fa-f992-4600-adf2-8640ce6df5db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111893010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1111893010
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.391368501
Short name T1729
Test name
Test status
Simulation time 11650405281 ps
CPU time 189.94 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 07:00:03 PM PDT 24
Peak memory 671900 kb
Host smart-88ddb974-8147-45cf-9648-21ec2cd0a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391368501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.391368501
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1891463714
Short name T986
Test name
Test status
Simulation time 3140115616 ps
CPU time 53.17 seconds
Started Jul 15 06:56:50 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 595800 kb
Host smart-d82a45a8-c920-4a8f-afc3-01a9687dbe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891463714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1891463714
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3720502537
Short name T1051
Test name
Test status
Simulation time 103709061 ps
CPU time 1.07 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:56:54 PM PDT 24
Peak memory 205216 kb
Host smart-83aecca8-ce3a-4c41-94a5-8aa6bd7bd9c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720502537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3720502537
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2539244442
Short name T1251
Test name
Test status
Simulation time 185831454 ps
CPU time 9.77 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 205480 kb
Host smart-145a7525-9db2-4b14-9c27-97bf0913190f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539244442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2539244442
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1795438734
Short name T713
Test name
Test status
Simulation time 7694292974 ps
CPU time 263.25 seconds
Started Jul 15 06:56:53 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 1128624 kb
Host smart-d23f989a-e260-4245-aefa-3ced661ca626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795438734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1795438734
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1981645310
Short name T1033
Test name
Test status
Simulation time 756477987 ps
CPU time 3.08 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 205512 kb
Host smart-a7cab4b4-436b-4765-8fc2-c4c8f13694a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981645310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1981645310
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.1386423832
Short name T1341
Test name
Test status
Simulation time 54022670 ps
CPU time 0.69 seconds
Started Jul 15 06:56:53 PM PDT 24
Finished Jul 15 06:56:54 PM PDT 24
Peak memory 205244 kb
Host smart-8e544d97-16af-4b07-809f-90d173ab2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386423832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1386423832
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.461878268
Short name T719
Test name
Test status
Simulation time 6822074145 ps
CPU time 18.64 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 213736 kb
Host smart-9eab25ae-bc92-4110-b77e-fef7f3754bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461878268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.461878268
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.2882293975
Short name T1305
Test name
Test status
Simulation time 239586623 ps
CPU time 0.86 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:53 PM PDT 24
Peak memory 205256 kb
Host smart-b0a348ce-16e9-40fe-aae9-5cd8f9ecc450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882293975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.2882293975
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3753688272
Short name T716
Test name
Test status
Simulation time 4097787085 ps
CPU time 22.73 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:57:16 PM PDT 24
Peak memory 324592 kb
Host smart-56a3c010-e5b2-4f77-989d-66040d87c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753688272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3753688272
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2512369892
Short name T1530
Test name
Test status
Simulation time 869959347 ps
CPU time 13.34 seconds
Started Jul 15 06:56:52 PM PDT 24
Finished Jul 15 06:57:06 PM PDT 24
Peak memory 221312 kb
Host smart-99bb3657-3553-4c05-93b7-f1b8a147cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512369892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2512369892
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1816628295
Short name T70
Test name
Test status
Simulation time 1348191344 ps
CPU time 5.58 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:57:03 PM PDT 24
Peak memory 220348 kb
Host smart-c5971645-c410-4d1a-86e1-3f0a8a0748af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816628295 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1816628295
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3730918039
Short name T1666
Test name
Test status
Simulation time 213907839 ps
CPU time 1.45 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:02 PM PDT 24
Peak memory 205632 kb
Host smart-9929931d-e3e2-46ad-8cdb-5b05da8cc07c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730918039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3730918039
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2297984191
Short name T1619
Test name
Test status
Simulation time 200533204 ps
CPU time 1.25 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:02 PM PDT 24
Peak memory 205504 kb
Host smart-add2695d-d595-4620-8517-374cf3390f5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297984191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2297984191
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.2725460022
Short name T1172
Test name
Test status
Simulation time 563819328 ps
CPU time 2.8 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:03 PM PDT 24
Peak memory 205704 kb
Host smart-d61ad7c8-a5cc-4ebb-88c6-6ebde64eb098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725460022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.2725460022
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.409935570
Short name T97
Test name
Test status
Simulation time 136371207 ps
CPU time 1.2 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:02 PM PDT 24
Peak memory 205436 kb
Host smart-c3adb985-f9a0-4cb1-bd30-24a6471f6d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409935570 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.409935570
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.334696519
Short name T1372
Test name
Test status
Simulation time 1993384808 ps
CPU time 3.34 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 213828 kb
Host smart-ae2ae37c-691c-4389-aec4-ba41bee859de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334696519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.334696519
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1325718214
Short name T624
Test name
Test status
Simulation time 3871771558 ps
CPU time 3.59 seconds
Started Jul 15 06:57:01 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 205620 kb
Host smart-7c5152da-827b-46bd-8df3-fc93a7374ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325718214 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1325718214
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.4039835524
Short name T1654
Test name
Test status
Simulation time 956606867 ps
CPU time 3.07 seconds
Started Jul 15 06:57:02 PM PDT 24
Finished Jul 15 06:57:06 PM PDT 24
Peak memory 213852 kb
Host smart-b431662a-e9d9-42bd-8ba3-fd72c21c9c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039835524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.4039835524
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.3635888020
Short name T521
Test name
Test status
Simulation time 533609563 ps
CPU time 2.64 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:57:00 PM PDT 24
Peak memory 206120 kb
Host smart-4cbf879f-42fe-4428-8682-ff173d0fdf5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635888020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.3635888020
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.2109906398
Short name T430
Test name
Test status
Simulation time 510047483 ps
CPU time 4 seconds
Started Jul 15 06:57:03 PM PDT 24
Finished Jul 15 06:57:07 PM PDT 24
Peak memory 213864 kb
Host smart-68ec1767-8b79-4eb3-bedb-810bcab3ae7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109906398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.2109906398
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.4054423517
Short name T1390
Test name
Test status
Simulation time 509443371 ps
CPU time 2.44 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:56:59 PM PDT 24
Peak memory 205472 kb
Host smart-a963bb2e-29ca-4a62-a683-72d19f311e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054423517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.4054423517
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.997466672
Short name T950
Test name
Test status
Simulation time 5894803845 ps
CPU time 11.59 seconds
Started Jul 15 06:56:53 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 213896 kb
Host smart-c2802707-fb7d-4253-aa83-c04fe3acbbe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997466672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.997466672
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.4105103276
Short name T482
Test name
Test status
Simulation time 9536109423 ps
CPU time 88.79 seconds
Started Jul 15 06:56:50 PM PDT 24
Finished Jul 15 06:58:19 PM PDT 24
Peak memory 217976 kb
Host smart-caf2f6e5-2c0e-4931-8c3e-035828b4d98d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105103276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.4105103276
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1490054676
Short name T742
Test name
Test status
Simulation time 8061339483 ps
CPU time 7.1 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:56:58 PM PDT 24
Peak memory 205716 kb
Host smart-38d1196a-2d2a-488c-8409-fc831d852151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490054676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1490054676
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1956400819
Short name T1039
Test name
Test status
Simulation time 3319862473 ps
CPU time 33.18 seconds
Started Jul 15 06:56:51 PM PDT 24
Finished Jul 15 06:57:24 PM PDT 24
Peak memory 688912 kb
Host smart-c6229b90-9894-4b32-a7e5-67804492e03b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956400819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1956400819
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.824031198
Short name T568
Test name
Test status
Simulation time 4427283308 ps
CPU time 6.62 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:57:04 PM PDT 24
Peak memory 213892 kb
Host smart-68caaad7-6879-4997-8043-1184e2c0e9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824031198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.824031198
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.579559530
Short name T1500
Test name
Test status
Simulation time 495881866 ps
CPU time 6.05 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 205600 kb
Host smart-76066feb-29b5-444f-a7c9-75f30efd283d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579559530 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.579559530
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.385692329
Short name T362
Test name
Test status
Simulation time 57646947 ps
CPU time 0.73 seconds
Started Jul 15 06:57:10 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 204840 kb
Host smart-d96c04e5-06a7-498e-8090-24fa3f89ccc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385692329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.385692329
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2415632253
Short name T1715
Test name
Test status
Simulation time 91534699 ps
CPU time 2.6 seconds
Started Jul 15 06:57:02 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 213772 kb
Host smart-a8a3721b-e7b5-45a5-a45a-9854f3532370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415632253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2415632253
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3588122458
Short name T1417
Test name
Test status
Simulation time 1065272057 ps
CPU time 4.96 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:57:03 PM PDT 24
Peak memory 251004 kb
Host smart-4aa7166f-f341-411d-93f1-f082dbfe62b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588122458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3588122458
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.320062168
Short name T478
Test name
Test status
Simulation time 2178125828 ps
CPU time 118.47 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:58:57 PM PDT 24
Peak memory 342588 kb
Host smart-841b9ee8-4605-40eb-bdcf-35ef5f788973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320062168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.320062168
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3736587246
Short name T1697
Test name
Test status
Simulation time 11206596055 ps
CPU time 154.81 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:59:35 PM PDT 24
Peak memory 710484 kb
Host smart-10ac1ccf-6cf0-445c-addb-bea230a6215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736587246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3736587246
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1060354912
Short name T338
Test name
Test status
Simulation time 100872371 ps
CPU time 0.91 seconds
Started Jul 15 06:56:56 PM PDT 24
Finished Jul 15 06:56:57 PM PDT 24
Peak memory 205232 kb
Host smart-70b37968-8ed7-4383-b3db-318c7f50dc5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060354912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1060354912
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3935435443
Short name T1154
Test name
Test status
Simulation time 202126881 ps
CPU time 4.71 seconds
Started Jul 15 06:56:57 PM PDT 24
Finished Jul 15 06:57:02 PM PDT 24
Peak memory 205544 kb
Host smart-e2ef43ae-a768-4237-9f4e-255cf58020cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935435443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3935435443
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1837922291
Short name T507
Test name
Test status
Simulation time 24114268645 ps
CPU time 133.35 seconds
Started Jul 15 06:56:56 PM PDT 24
Finished Jul 15 06:59:10 PM PDT 24
Peak memory 1222872 kb
Host smart-efb0948e-c74f-4267-ba93-9279e6d9a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837922291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1837922291
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1461471589
Short name T1009
Test name
Test status
Simulation time 1421722790 ps
CPU time 5.56 seconds
Started Jul 15 06:57:07 PM PDT 24
Finished Jul 15 06:57:13 PM PDT 24
Peak memory 205500 kb
Host smart-388daabb-4099-4e5e-9592-577e04300f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461471589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1461471589
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.3366907999
Short name T868
Test name
Test status
Simulation time 198937471 ps
CPU time 0.67 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:56:59 PM PDT 24
Peak memory 205160 kb
Host smart-ba0817f1-d5d8-486a-96f9-f8a9df5044d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366907999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3366907999
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.693006033
Short name T1458
Test name
Test status
Simulation time 30496314110 ps
CPU time 111.33 seconds
Started Jul 15 06:56:59 PM PDT 24
Finished Jul 15 06:58:51 PM PDT 24
Peak memory 517316 kb
Host smart-ae90eb29-fcdf-488e-b15f-83a01d820847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693006033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.693006033
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.496130995
Short name T385
Test name
Test status
Simulation time 318571835 ps
CPU time 12.99 seconds
Started Jul 15 06:57:02 PM PDT 24
Finished Jul 15 06:57:15 PM PDT 24
Peak memory 223536 kb
Host smart-fb2492d2-c4bc-4463-9e48-0f93cdd54c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496130995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.496130995
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.108657872
Short name T667
Test name
Test status
Simulation time 5720464957 ps
CPU time 20.52 seconds
Started Jul 15 06:56:58 PM PDT 24
Finished Jul 15 06:57:19 PM PDT 24
Peak memory 329244 kb
Host smart-b4be7d98-2e02-425e-b71c-1d20b334ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108657872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.108657872
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.24369620
Short name T202
Test name
Test status
Simulation time 587838808 ps
CPU time 25.72 seconds
Started Jul 15 06:57:05 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 213664 kb
Host smart-76ce2f3b-0bc9-4326-b9b5-6931f5da80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24369620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.24369620
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2006256458
Short name T1471
Test name
Test status
Simulation time 3447648710 ps
CPU time 4.1 seconds
Started Jul 15 06:57:07 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 209968 kb
Host smart-9944098e-538e-47e7-b498-7e49fe1077c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006256458 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2006256458
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2020992930
Short name T724
Test name
Test status
Simulation time 152345627 ps
CPU time 0.98 seconds
Started Jul 15 06:57:02 PM PDT 24
Finished Jul 15 06:57:04 PM PDT 24
Peak memory 205396 kb
Host smart-2819ec6b-5a57-4cf0-8c25-de67b2ddc127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020992930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2020992930
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.977487240
Short name T1557
Test name
Test status
Simulation time 148401407 ps
CPU time 0.82 seconds
Started Jul 15 06:57:03 PM PDT 24
Finished Jul 15 06:57:05 PM PDT 24
Peak memory 205484 kb
Host smart-adb1b70c-eefa-4a47-8e3f-b70c111485b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977487240 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.977487240
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.956403246
Short name T1438
Test name
Test status
Simulation time 472556724 ps
CPU time 2.71 seconds
Started Jul 15 06:57:13 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 205600 kb
Host smart-e8734fae-4493-4406-b92e-6cb4b7439fd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956403246 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.956403246
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.3616528741
Short name T736
Test name
Test status
Simulation time 2043154646 ps
CPU time 1.61 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 205460 kb
Host smart-7758055d-a4d6-4064-84bb-0a8dfa6b86de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616528741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.3616528741
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2513394952
Short name T345
Test name
Test status
Simulation time 3668238747 ps
CPU time 5.46 seconds
Started Jul 15 06:57:03 PM PDT 24
Finished Jul 15 06:57:09 PM PDT 24
Peak memory 220840 kb
Host smart-255d6b84-5a2b-4374-b272-0aa53473826e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513394952 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2513394952
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1417519004
Short name T615
Test name
Test status
Simulation time 20462670317 ps
CPU time 378.62 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 07:03:27 PM PDT 24
Peak memory 3430704 kb
Host smart-531f8e3f-7ed0-45f2-a02e-96ff22625015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417519004 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1417519004
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.232475457
Short name T1643
Test name
Test status
Simulation time 541740384 ps
CPU time 2.57 seconds
Started Jul 15 06:57:09 PM PDT 24
Finished Jul 15 06:57:12 PM PDT 24
Peak memory 213812 kb
Host smart-e3f59509-a71e-4193-9fa4-67df157299bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232475457 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_nack_acqfull.232475457
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.2172963287
Short name T1573
Test name
Test status
Simulation time 594389096 ps
CPU time 2.9 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 206088 kb
Host smart-f9aa1d22-cb56-48dc-9297-f9fcf8a0ea91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172963287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.2172963287
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_txstretch.3379122374
Short name T181
Test name
Test status
Simulation time 283573650 ps
CPU time 1.3 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:57:10 PM PDT 24
Peak memory 222064 kb
Host smart-c317b7dd-edbb-4325-bdf5-60c9989f9b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379122374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_nack_txstretch.3379122374
Directory /workspace/33.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3452725106
Short name T296
Test name
Test status
Simulation time 1675824687 ps
CPU time 5.63 seconds
Started Jul 15 06:57:00 PM PDT 24
Finished Jul 15 06:57:06 PM PDT 24
Peak memory 213864 kb
Host smart-d1428410-8f93-441b-af80-c003089f6718
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452725106 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3452725106
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.2157217794
Short name T138
Test name
Test status
Simulation time 5524343914 ps
CPU time 2.31 seconds
Started Jul 15 06:57:09 PM PDT 24
Finished Jul 15 06:57:12 PM PDT 24
Peak memory 205584 kb
Host smart-9daa86de-79ee-450b-bbe3-e87d279c2117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157217794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.2157217794
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.905241151
Short name T75
Test name
Test status
Simulation time 3353291983 ps
CPU time 11.37 seconds
Started Jul 15 06:57:04 PM PDT 24
Finished Jul 15 06:57:16 PM PDT 24
Peak memory 213884 kb
Host smart-f572bd6f-6633-452a-9276-de05e2aac762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905241151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.905241151
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.523207946
Short name T1674
Test name
Test status
Simulation time 28363858301 ps
CPU time 42.13 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:57:50 PM PDT 24
Peak memory 279632 kb
Host smart-859de8b1-2274-4a1b-88c2-dfb7df9d4698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523207946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_stress_all.523207946
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3546659006
Short name T1073
Test name
Test status
Simulation time 4178574983 ps
CPU time 22.19 seconds
Started Jul 15 06:57:04 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 232548 kb
Host smart-d0907edd-90bf-47f2-95b3-30f6cb74febb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546659006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3546659006
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2698513553
Short name T1085
Test name
Test status
Simulation time 26137895796 ps
CPU time 117.75 seconds
Started Jul 15 06:57:01 PM PDT 24
Finished Jul 15 06:58:59 PM PDT 24
Peak memory 1737136 kb
Host smart-7b782945-97ce-4cff-bb66-22c2a3338cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698513553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2698513553
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2756687023
Short name T921
Test name
Test status
Simulation time 2388605025 ps
CPU time 55.36 seconds
Started Jul 15 06:57:01 PM PDT 24
Finished Jul 15 06:57:57 PM PDT 24
Peak memory 490816 kb
Host smart-222feff0-b023-46e0-951c-4c746e0f8fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756687023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2756687023
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.922072324
Short name T1013
Test name
Test status
Simulation time 5648915461 ps
CPU time 6.36 seconds
Started Jul 15 06:57:03 PM PDT 24
Finished Jul 15 06:57:10 PM PDT 24
Peak memory 213916 kb
Host smart-e87a2d6c-96a5-4c80-9803-aab1d42c480b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922072324 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.922072324
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.3419721968
Short name T841
Test name
Test status
Simulation time 248078671 ps
CPU time 2.43 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:57:11 PM PDT 24
Peak memory 214844 kb
Host smart-07b8c808-f2b9-43ff-8306-98467793b27f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419721968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3419721968
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.431908321
Short name T1074
Test name
Test status
Simulation time 40115556 ps
CPU time 0.62 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:20 PM PDT 24
Peak memory 204692 kb
Host smart-2ec5fe24-f9a9-4682-8d67-9c2044c2ffd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431908321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.431908321
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.366690890
Short name T1580
Test name
Test status
Simulation time 1315694511 ps
CPU time 5.88 seconds
Started Jul 15 06:57:10 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 272012 kb
Host smart-363c6224-d6ad-4366-beb4-53271ab76385
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366690890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.366690890
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.934982073
Short name T1355
Test name
Test status
Simulation time 3467890742 ps
CPU time 92.02 seconds
Started Jul 15 06:57:12 PM PDT 24
Finished Jul 15 06:58:44 PM PDT 24
Peak memory 588572 kb
Host smart-401bd49a-24f9-4e46-b1b4-5a86f9979773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934982073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.934982073
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3697425494
Short name T726
Test name
Test status
Simulation time 2111329973 ps
CPU time 138.49 seconds
Started Jul 15 06:57:08 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 624920 kb
Host smart-1c80e258-567b-4d4f-aa65-3af978fcfdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697425494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3697425494
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3534013776
Short name T43
Test name
Test status
Simulation time 275544629 ps
CPU time 0.97 seconds
Started Jul 15 06:57:09 PM PDT 24
Finished Jul 15 06:57:10 PM PDT 24
Peak memory 205248 kb
Host smart-347b273f-9ef6-4850-894e-3b403f5a7c93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534013776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3534013776
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.702818397
Short name T1358
Test name
Test status
Simulation time 267379940 ps
CPU time 3.59 seconds
Started Jul 15 06:57:11 PM PDT 24
Finished Jul 15 06:57:15 PM PDT 24
Peak memory 226640 kb
Host smart-bf361d2f-c5ea-4fca-bf22-a2443cb506e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702818397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
702818397
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.112817562
Short name T1401
Test name
Test status
Simulation time 4174152578 ps
CPU time 289.03 seconds
Started Jul 15 06:57:10 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 1167972 kb
Host smart-90e8e28c-f0aa-4f2b-a2ed-030f2c83d47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112817562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.112817562
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1441029547
Short name T1247
Test name
Test status
Simulation time 1265247162 ps
CPU time 12.82 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205532 kb
Host smart-6170658f-18d9-46d4-af01-8b6eba9069ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441029547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1441029547
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.154983902
Short name T13
Test name
Test status
Simulation time 384087083 ps
CPU time 1.85 seconds
Started Jul 15 06:57:16 PM PDT 24
Finished Jul 15 06:57:19 PM PDT 24
Peak memory 205524 kb
Host smart-7c956e4c-322b-43fd-bb30-e7691be5be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154983902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.154983902
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3505306977
Short name T636
Test name
Test status
Simulation time 14831933 ps
CPU time 0.72 seconds
Started Jul 15 06:57:14 PM PDT 24
Finished Jul 15 06:57:15 PM PDT 24
Peak memory 205200 kb
Host smart-5a9084f8-190b-4585-b940-f27687cd3cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505306977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3505306977
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.640148008
Short name T1180
Test name
Test status
Simulation time 19653874975 ps
CPU time 144.39 seconds
Started Jul 15 06:57:13 PM PDT 24
Finished Jul 15 06:59:38 PM PDT 24
Peak memory 446188 kb
Host smart-15d74ddc-ebce-4514-a734-c8dffc751147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640148008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.640148008
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.734124000
Short name T1309
Test name
Test status
Simulation time 83563085 ps
CPU time 1.28 seconds
Started Jul 15 06:57:13 PM PDT 24
Finished Jul 15 06:57:14 PM PDT 24
Peak memory 213604 kb
Host smart-cf514603-0fa3-4ff8-a5c5-20ec8d0e15dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734124000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.734124000
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.648718182
Short name T485
Test name
Test status
Simulation time 1966341947 ps
CPU time 43.33 seconds
Started Jul 15 06:57:09 PM PDT 24
Finished Jul 15 06:57:53 PM PDT 24
Peak memory 384516 kb
Host smart-7e8eca4b-ca81-40b2-9318-f24c6a429519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648718182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.648718182
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2243385317
Short name T1525
Test name
Test status
Simulation time 607016578 ps
CPU time 11.28 seconds
Started Jul 15 06:57:07 PM PDT 24
Finished Jul 15 06:57:18 PM PDT 24
Peak memory 217180 kb
Host smart-87f4084f-9a7a-4b30-9f17-eb9860073630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243385317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2243385317
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3529294164
Short name T1163
Test name
Test status
Simulation time 11730334032 ps
CPU time 4.01 seconds
Started Jul 15 06:57:12 PM PDT 24
Finished Jul 15 06:57:16 PM PDT 24
Peak memory 213908 kb
Host smart-5749f6a7-3d52-47d1-9e61-8b7ef8ea2a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529294164 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3529294164
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.675694130
Short name T1026
Test name
Test status
Simulation time 578424895 ps
CPU time 1.35 seconds
Started Jul 15 06:57:13 PM PDT 24
Finished Jul 15 06:57:15 PM PDT 24
Peak memory 213692 kb
Host smart-f951f55f-2b9b-4277-bc1f-6a732f8f4d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675694130 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.675694130
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1004311704
Short name T883
Test name
Test status
Simulation time 247944001 ps
CPU time 1.11 seconds
Started Jul 15 06:57:13 PM PDT 24
Finished Jul 15 06:57:14 PM PDT 24
Peak memory 205472 kb
Host smart-b3edfd91-0e1b-4cf5-99b9-3a9b7ec4e702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004311704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1004311704
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.756115726
Short name T1202
Test name
Test status
Simulation time 1052032764 ps
CPU time 2.93 seconds
Started Jul 15 06:57:17 PM PDT 24
Finished Jul 15 06:57:20 PM PDT 24
Peak memory 205652 kb
Host smart-bc4b692d-79c7-41dc-a520-fec9183413ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756115726 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.756115726
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1189827674
Short name T495
Test name
Test status
Simulation time 571091632 ps
CPU time 1.23 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 205460 kb
Host smart-87d825d0-265c-4fd4-8d7e-34cb155b16ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189827674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1189827674
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1825515861
Short name T1380
Test name
Test status
Simulation time 3607834793 ps
CPU time 3.73 seconds
Started Jul 15 06:57:14 PM PDT 24
Finished Jul 15 06:57:18 PM PDT 24
Peak memory 214484 kb
Host smart-f89ff231-e34c-4ed2-bb12-ecbc0a99298e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825515861 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1825515861
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.960509029
Short name T1603
Test name
Test status
Simulation time 20980933730 ps
CPU time 9.67 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:25 PM PDT 24
Peak memory 205740 kb
Host smart-0b9398b3-d3ab-44b3-b95d-e2b161f5f67b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960509029 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.960509029
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.2020737772
Short name T1038
Test name
Test status
Simulation time 790269727 ps
CPU time 2.89 seconds
Started Jul 15 06:57:16 PM PDT 24
Finished Jul 15 06:57:19 PM PDT 24
Peak memory 213872 kb
Host smart-2ad7e18c-1663-45a3-b4f2-6421f00de5c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020737772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.2020737772
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_txstretch.2215538359
Short name T1046
Test name
Test status
Simulation time 147415634 ps
CPU time 1.57 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 222448 kb
Host smart-970ede53-64dd-4a6e-81f4-82d9eb168944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215538359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_nack_txstretch.2215538359
Directory /workspace/34.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.4188526392
Short name T545
Test name
Test status
Simulation time 1811650495 ps
CPU time 2.16 seconds
Started Jul 15 06:57:14 PM PDT 24
Finished Jul 15 06:57:16 PM PDT 24
Peak memory 205388 kb
Host smart-ae9a44cf-4b76-4f33-a854-21bef39e6281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188526392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.4188526392
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.298314385
Short name T1214
Test name
Test status
Simulation time 816948053 ps
CPU time 10.16 seconds
Started Jul 15 06:57:11 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 208132 kb
Host smart-a9041776-f8a4-4049-a048-1e31d6b6a601
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298314385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.298314385
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.974487410
Short name T94
Test name
Test status
Simulation time 12290980006 ps
CPU time 147.19 seconds
Started Jul 15 06:57:16 PM PDT 24
Finished Jul 15 06:59:44 PM PDT 24
Peak memory 1245948 kb
Host smart-9bba5fda-f958-4e7f-9205-7517807c9add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974487410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.974487410
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2787051048
Short name T1713
Test name
Test status
Simulation time 778413808 ps
CPU time 4.99 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 205520 kb
Host smart-43595fcd-1416-46f7-8fec-a89e42c72a94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787051048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2787051048
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2237162691
Short name T174
Test name
Test status
Simulation time 19638366055 ps
CPU time 22.89 seconds
Started Jul 15 06:57:14 PM PDT 24
Finished Jul 15 06:57:37 PM PDT 24
Peak memory 205716 kb
Host smart-71fe10b2-6bad-4a16-b8cb-1c8bebeb7ced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237162691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2237162691
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.401166555
Short name T394
Test name
Test status
Simulation time 1586176841 ps
CPU time 7.15 seconds
Started Jul 15 06:57:16 PM PDT 24
Finished Jul 15 06:57:24 PM PDT 24
Peak memory 221916 kb
Host smart-c5def36b-e731-4c7e-9487-792b3d100026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401166555 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.401166555
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.2695431999
Short name T790
Test name
Test status
Simulation time 68056597 ps
CPU time 1.57 seconds
Started Jul 15 06:57:15 PM PDT 24
Finished Jul 15 06:57:17 PM PDT 24
Peak memory 205600 kb
Host smart-b71476f5-7f3f-40a2-aef2-45a5427d51a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695431999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.2695431999
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3236077277
Short name T690
Test name
Test status
Simulation time 17148114 ps
CPU time 0.67 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 204836 kb
Host smart-5754f871-5d0e-4b84-b25e-4dacc6e95a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236077277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3236077277
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3749153172
Short name T1456
Test name
Test status
Simulation time 835142769 ps
CPU time 1.56 seconds
Started Jul 15 06:57:21 PM PDT 24
Finished Jul 15 06:57:23 PM PDT 24
Peak memory 213720 kb
Host smart-4d33907e-8122-4766-8ff6-1314cb4337df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749153172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3749153172
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2392056211
Short name T1189
Test name
Test status
Simulation time 408681363 ps
CPU time 7.41 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 297380 kb
Host smart-61038519-ab69-4ce0-b623-2549a3491a97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392056211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2392056211
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1668928235
Short name T30
Test name
Test status
Simulation time 1756844849 ps
CPU time 45.3 seconds
Started Jul 15 06:57:21 PM PDT 24
Finished Jul 15 06:58:07 PM PDT 24
Peak memory 343964 kb
Host smart-a5853241-2edc-4684-94a6-b786d56dfabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668928235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1668928235
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2344955345
Short name T1048
Test name
Test status
Simulation time 7510513343 ps
CPU time 56.05 seconds
Started Jul 15 06:57:18 PM PDT 24
Finished Jul 15 06:58:14 PM PDT 24
Peak memory 626536 kb
Host smart-525a2863-2d2f-4f07-b59c-803f0d3c2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344955345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2344955345
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3567907921
Short name T528
Test name
Test status
Simulation time 102704974 ps
CPU time 1.08 seconds
Started Jul 15 06:57:20 PM PDT 24
Finished Jul 15 06:57:21 PM PDT 24
Peak memory 205236 kb
Host smart-6a9511a7-724d-4565-b073-e2273aad70df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567907921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3567907921
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.4207645541
Short name T759
Test name
Test status
Simulation time 671452019 ps
CPU time 8.2 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205524 kb
Host smart-d5d6d7f3-3f18-42e4-91ae-d2f0d87b6301
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207645541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.4207645541
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1704299597
Short name T1050
Test name
Test status
Simulation time 7009112652 ps
CPU time 79.69 seconds
Started Jul 15 06:57:21 PM PDT 24
Finished Jul 15 06:58:41 PM PDT 24
Peak memory 781988 kb
Host smart-2803cbed-2704-48c1-b673-e73fcac72ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704299597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1704299597
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.4181010267
Short name T895
Test name
Test status
Simulation time 497666876 ps
CPU time 4.46 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 205472 kb
Host smart-8eedf34b-41a3-4c70-bb2b-7667a29287af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181010267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.4181010267
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3411354460
Short name T11
Test name
Test status
Simulation time 710714738 ps
CPU time 2 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 213632 kb
Host smart-00ac586b-a62b-4104-963f-f1a16bd4596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411354460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3411354460
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3985766109
Short name T145
Test name
Test status
Simulation time 50921359 ps
CPU time 0.68 seconds
Started Jul 15 06:57:22 PM PDT 24
Finished Jul 15 06:57:23 PM PDT 24
Peak memory 205168 kb
Host smart-4a22b995-c282-4552-908c-a9470efa422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985766109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3985766109
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.4227571529
Short name T918
Test name
Test status
Simulation time 7360217416 ps
CPU time 43 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:58:03 PM PDT 24
Peak memory 610912 kb
Host smart-279f56a9-42d5-4d8c-a02e-cb3fd52000ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227571529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4227571529
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.3174970776
Short name T901
Test name
Test status
Simulation time 6038814715 ps
CPU time 22.21 seconds
Started Jul 15 06:57:17 PM PDT 24
Finished Jul 15 06:57:40 PM PDT 24
Peak memory 471792 kb
Host smart-a9409a79-c4f1-4d40-8898-ce38c30a7de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174970776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.3174970776
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2625939528
Short name T432
Test name
Test status
Simulation time 2697508377 ps
CPU time 27.18 seconds
Started Jul 15 06:57:22 PM PDT 24
Finished Jul 15 06:57:49 PM PDT 24
Peak memory 346296 kb
Host smart-d932f987-79e6-4d0e-a458-0adea5ada180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625939528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2625939528
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2054947248
Short name T245
Test name
Test status
Simulation time 110573079460 ps
CPU time 3351.81 seconds
Started Jul 15 06:57:20 PM PDT 24
Finished Jul 15 07:53:13 PM PDT 24
Peak memory 3368536 kb
Host smart-c681cbaf-0807-412c-bb9d-b1be3ee3eef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054947248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2054947248
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1788099541
Short name T1110
Test name
Test status
Simulation time 1315777884 ps
CPU time 29.3 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:49 PM PDT 24
Peak memory 213680 kb
Host smart-17151859-991c-4f06-a84a-410b9a1d304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788099541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1788099541
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2022966999
Short name T384
Test name
Test status
Simulation time 1685135042 ps
CPU time 7.76 seconds
Started Jul 15 06:57:24 PM PDT 24
Finished Jul 15 06:57:32 PM PDT 24
Peak memory 213824 kb
Host smart-09e3a1a1-c9fa-40fe-bcd8-9b9462efaa76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022966999 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2022966999
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2529609434
Short name T903
Test name
Test status
Simulation time 364731620 ps
CPU time 1.32 seconds
Started Jul 15 06:57:25 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 205676 kb
Host smart-d0c2d03b-d38f-4ca4-9d74-cd0adba2b209
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529609434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2529609434
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.825396244
Short name T379
Test name
Test status
Simulation time 312107920 ps
CPU time 1.21 seconds
Started Jul 15 06:57:28 PM PDT 24
Finished Jul 15 06:57:30 PM PDT 24
Peak memory 205452 kb
Host smart-ff5210d6-abb5-47f9-bcc4-227eab7bf748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825396244 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.825396244
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.3784313374
Short name T1217
Test name
Test status
Simulation time 4321015372 ps
CPU time 2.38 seconds
Started Jul 15 06:57:28 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 205676 kb
Host smart-b3813eec-8f32-4f53-9acc-11669e5f5366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784313374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.3784313374
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2042279840
Short name T1624
Test name
Test status
Simulation time 474924214 ps
CPU time 1.11 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205444 kb
Host smart-256dbf1c-4453-4400-8465-289f8aa7b3d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042279840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2042279840
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.552973554
Short name T505
Test name
Test status
Simulation time 2678680265 ps
CPU time 2.36 seconds
Started Jul 15 06:57:24 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 208204 kb
Host smart-1ee9979f-dfeb-4e58-bfbd-6f562a86b98a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552973554 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.552973554
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1100170088
Short name T403
Test name
Test status
Simulation time 1085108678 ps
CPU time 5.97 seconds
Started Jul 15 06:57:19 PM PDT 24
Finished Jul 15 06:57:25 PM PDT 24
Peak memory 216236 kb
Host smart-3c4d7d5e-5507-4ccb-a2f3-ae0e31c8ad4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100170088 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1100170088
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.140330233
Short name T52
Test name
Test status
Simulation time 27387569143 ps
CPU time 930.28 seconds
Started Jul 15 06:57:21 PM PDT 24
Finished Jul 15 07:12:52 PM PDT 24
Peak memory 6572432 kb
Host smart-737b8597-fcc4-4dcc-aa44-97dc1968e1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140330233 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.140330233
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.2318137295
Short name T653
Test name
Test status
Simulation time 621802246 ps
CPU time 3.41 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:30 PM PDT 24
Peak memory 213852 kb
Host smart-e78ee1c3-c736-4b03-8774-3e3bc2cfd5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318137295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.2318137295
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3363260444
Short name T1373
Test name
Test status
Simulation time 480940229 ps
CPU time 2.41 seconds
Started Jul 15 06:57:28 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 205496 kb
Host smart-fbe7f7a3-2a03-45af-9c06-0a101eec3c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363260444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3363260444
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.1922750062
Short name T1647
Test name
Test status
Simulation time 362876940 ps
CPU time 1.5 seconds
Started Jul 15 06:57:25 PM PDT 24
Finished Jul 15 06:57:27 PM PDT 24
Peak memory 222128 kb
Host smart-8e8f0733-125b-4a50-834e-f447afa88a1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922750062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.1922750062
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1628010421
Short name T1008
Test name
Test status
Simulation time 540394076 ps
CPU time 3.82 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:31 PM PDT 24
Peak memory 221956 kb
Host smart-9a830408-72a9-42e4-9583-fb1779793a4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628010421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1628010421
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.2034490148
Short name T176
Test name
Test status
Simulation time 356963687 ps
CPU time 2.01 seconds
Started Jul 15 06:57:25 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205388 kb
Host smart-b8935bad-36ab-4b19-bc85-e817ef94e43c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034490148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.2034490148
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1051786544
Short name T765
Test name
Test status
Simulation time 2725259177 ps
CPU time 20.28 seconds
Started Jul 15 06:57:20 PM PDT 24
Finished Jul 15 06:57:41 PM PDT 24
Peak memory 213840 kb
Host smart-534803ca-b804-43ca-934f-58abdca86435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051786544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1051786544
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.39106556
Short name T863
Test name
Test status
Simulation time 23772377761 ps
CPU time 688.19 seconds
Started Jul 15 06:57:23 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 3611260 kb
Host smart-db627613-5660-4988-90aa-7c21e6e84c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.i2c_target_stress_all.39106556
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3099066964
Short name T508
Test name
Test status
Simulation time 1304655800 ps
CPU time 12.22 seconds
Started Jul 15 06:57:20 PM PDT 24
Finished Jul 15 06:57:32 PM PDT 24
Peak memory 205708 kb
Host smart-f507936e-eb42-4332-8587-622d6e7a9616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099066964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3099066964
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.163493169
Short name T1167
Test name
Test status
Simulation time 42143464400 ps
CPU time 103.92 seconds
Started Jul 15 06:57:21 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 1533200 kb
Host smart-cfae601e-05de-4fcd-9b55-a11de954e235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163493169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.163493169
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.134318616
Short name T135
Test name
Test status
Simulation time 5196763174 ps
CPU time 6.88 seconds
Started Jul 15 06:57:28 PM PDT 24
Finished Jul 15 06:57:36 PM PDT 24
Peak memory 222044 kb
Host smart-4533cd0c-84be-4c5d-851e-1ccad7f02c5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134318616 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.134318616
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2820628303
Short name T1041
Test name
Test status
Simulation time 560766458 ps
CPU time 8.04 seconds
Started Jul 15 06:57:25 PM PDT 24
Finished Jul 15 06:57:33 PM PDT 24
Peak memory 205928 kb
Host smart-ffedaaa0-093d-41d3-81b2-48a4bd55d0b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820628303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2820628303
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2188788068
Short name T799
Test name
Test status
Simulation time 42440298 ps
CPU time 0.64 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 06:57:46 PM PDT 24
Peak memory 204920 kb
Host smart-c8c11df7-df01-4926-b892-b61f9723c2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188788068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2188788068
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3803113356
Short name T80
Test name
Test status
Simulation time 596423681 ps
CPU time 2.86 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:35 PM PDT 24
Peak memory 234520 kb
Host smart-f761a01d-5ee8-4914-8a72-eec8ba43a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803113356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3803113356
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3031869555
Short name T1384
Test name
Test status
Simulation time 1734753079 ps
CPU time 8.54 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:41 PM PDT 24
Peak memory 302364 kb
Host smart-bca6d18a-5ab5-47ce-9559-819b6bec9339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031869555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3031869555
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.4185265117
Short name T161
Test name
Test status
Simulation time 9298915836 ps
CPU time 56.28 seconds
Started Jul 15 06:57:30 PM PDT 24
Finished Jul 15 06:58:27 PM PDT 24
Peak memory 400040 kb
Host smart-048bc240-fb4c-449f-8baf-0cf4b3c05675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185265117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.4185265117
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2878431418
Short name T857
Test name
Test status
Simulation time 36823536488 ps
CPU time 92.46 seconds
Started Jul 15 06:57:25 PM PDT 24
Finished Jul 15 06:58:58 PM PDT 24
Peak memory 849896 kb
Host smart-7be6c048-e8cd-42b6-a0b6-d3b7a0a8fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878431418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2878431418
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3439937035
Short name T1382
Test name
Test status
Simulation time 271769254 ps
CPU time 1.11 seconds
Started Jul 15 06:57:26 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205216 kb
Host smart-a012f8a9-9059-47a5-9e90-98798c6b6402
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439937035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3439937035
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3700351270
Short name T415
Test name
Test status
Simulation time 728343109 ps
CPU time 8.54 seconds
Started Jul 15 06:57:29 PM PDT 24
Finished Jul 15 06:57:38 PM PDT 24
Peak memory 205500 kb
Host smart-16b35d15-1bf9-4a75-b7d6-9e5ec84eec06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700351270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3700351270
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2174747080
Short name T1109
Test name
Test status
Simulation time 16675760346 ps
CPU time 321.08 seconds
Started Jul 15 06:57:27 PM PDT 24
Finished Jul 15 07:02:49 PM PDT 24
Peak memory 1287232 kb
Host smart-1bb27d8d-844d-44dc-ab19-f0b9d50760c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174747080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2174747080
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.595614074
Short name T1638
Test name
Test status
Simulation time 2856427386 ps
CPU time 19.81 seconds
Started Jul 15 06:57:33 PM PDT 24
Finished Jul 15 06:57:53 PM PDT 24
Peak memory 205600 kb
Host smart-6528e8de-8c1d-4860-b1e6-6602349018d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595614074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.595614074
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.3239170606
Short name T1356
Test name
Test status
Simulation time 16907312 ps
CPU time 0.66 seconds
Started Jul 15 06:57:27 PM PDT 24
Finished Jul 15 06:57:28 PM PDT 24
Peak memory 205276 kb
Host smart-9882a6e9-d31a-4c21-b666-2ad19aad55c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239170606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3239170606
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2529384926
Short name T18
Test name
Test status
Simulation time 5017820340 ps
CPU time 230.08 seconds
Started Jul 15 06:57:29 PM PDT 24
Finished Jul 15 07:01:19 PM PDT 24
Peak memory 703120 kb
Host smart-521483ed-35d2-48f9-a8e0-21ab52ccc366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529384926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2529384926
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.4256607373
Short name T158
Test name
Test status
Simulation time 97913273 ps
CPU time 1.68 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:34 PM PDT 24
Peak memory 225060 kb
Host smart-1ace626f-b3e7-4e8b-90bf-e52a33cb8b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256607373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.4256607373
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.292829867
Short name T709
Test name
Test status
Simulation time 1916826989 ps
CPU time 43.7 seconds
Started Jul 15 06:57:24 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 475340 kb
Host smart-4d5e9cec-b7c9-41f6-808e-6040994cb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292829867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.292829867
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1825240616
Short name T672
Test name
Test status
Simulation time 2343928620 ps
CPU time 8.76 seconds
Started Jul 15 06:57:30 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 220048 kb
Host smart-a8a8cbc6-7e8c-41f1-8690-5de41e58d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825240616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1825240616
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1550194277
Short name T1590
Test name
Test status
Simulation time 2472306113 ps
CPU time 6.01 seconds
Started Jul 15 06:57:33 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 213920 kb
Host smart-887761eb-c303-4651-b907-c918eeba3468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550194277 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1550194277
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.734241480
Short name T1164
Test name
Test status
Simulation time 629007048 ps
CPU time 1.09 seconds
Started Jul 15 06:57:31 PM PDT 24
Finished Jul 15 06:57:33 PM PDT 24
Peak memory 205476 kb
Host smart-76604419-2123-4d0c-b1a4-5d51808d43aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734241480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.734241480
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.684021812
Short name T292
Test name
Test status
Simulation time 554911361 ps
CPU time 1.5 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:34 PM PDT 24
Peak memory 205632 kb
Host smart-188b93e0-c946-45ec-92aa-24da42c7df78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684021812 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.684021812
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.3390100419
Short name T887
Test name
Test status
Simulation time 577837226 ps
CPU time 2.9 seconds
Started Jul 15 06:57:31 PM PDT 24
Finished Jul 15 06:57:34 PM PDT 24
Peak memory 205616 kb
Host smart-51e123b3-4dc1-4fb2-ba13-d8048a6f2a00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390100419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3390100419
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.4202281029
Short name T911
Test name
Test status
Simulation time 207680365 ps
CPU time 1.12 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:33 PM PDT 24
Peak memory 205516 kb
Host smart-102b81f9-f283-465e-a474-0a31e5bc5fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202281029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.4202281029
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2111819220
Short name T922
Test name
Test status
Simulation time 3856480213 ps
CPU time 5.86 seconds
Started Jul 15 06:57:33 PM PDT 24
Finished Jul 15 06:57:40 PM PDT 24
Peak memory 222040 kb
Host smart-ff6c7331-863b-4004-8fef-7fd1c2550d7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111819220 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2111819220
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.225333596
Short name T775
Test name
Test status
Simulation time 3442843023 ps
CPU time 4.39 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:37 PM PDT 24
Peak memory 205676 kb
Host smart-2eb68d45-fd57-4f04-9b12-84a28187f2e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225333596 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.225333596
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.3566512330
Short name T1342
Test name
Test status
Simulation time 628179034 ps
CPU time 3.14 seconds
Started Jul 15 06:57:35 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 213852 kb
Host smart-9dfbd7b7-44e7-46dc-b392-c8a471e879a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566512330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.3566512330
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.580153528
Short name T1439
Test name
Test status
Simulation time 1293655128 ps
CPU time 2.58 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 205648 kb
Host smart-6d78bbd2-0256-4d40-9c5e-07847d4b6d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580153528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.580153528
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.3725625485
Short name T1710
Test name
Test status
Simulation time 290888029 ps
CPU time 1.47 seconds
Started Jul 15 06:57:38 PM PDT 24
Finished Jul 15 06:57:40 PM PDT 24
Peak memory 222348 kb
Host smart-0d7a279e-73d8-4460-a116-17eab1cad96e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725625485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_txstretch.3725625485
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.4163276593
Short name T547
Test name
Test status
Simulation time 909492609 ps
CPU time 5.51 seconds
Started Jul 15 06:57:31 PM PDT 24
Finished Jul 15 06:57:37 PM PDT 24
Peak memory 219244 kb
Host smart-809dc4a6-55d0-4859-8377-7ef859f60947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163276593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.4163276593
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.3374394399
Short name T312
Test name
Test status
Simulation time 426673553 ps
CPU time 2.22 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 205428 kb
Host smart-f8cbd335-153d-4181-9679-f1d04d5c45cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374394399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.3374394399
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.206194450
Short name T1675
Test name
Test status
Simulation time 13696538885 ps
CPU time 8.95 seconds
Started Jul 15 06:57:32 PM PDT 24
Finished Jul 15 06:57:42 PM PDT 24
Peak memory 213884 kb
Host smart-99e9bfc1-a3a6-4c35-8f53-30836d9361e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206194450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.206194450
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.1802441378
Short name T741
Test name
Test status
Simulation time 24600329551 ps
CPU time 34.79 seconds
Started Jul 15 06:57:30 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 554896 kb
Host smart-752e4f8b-2f9f-4dca-b3e6-6402815319aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802441378 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.1802441378
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.214851284
Short name T774
Test name
Test status
Simulation time 9611709294 ps
CPU time 16.25 seconds
Started Jul 15 06:57:30 PM PDT 24
Finished Jul 15 06:57:47 PM PDT 24
Peak memory 222012 kb
Host smart-f54ede0d-b147-4b90-8cc1-1ef7a5974fd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214851284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.214851284
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3022538779
Short name T1190
Test name
Test status
Simulation time 62971082682 ps
CPU time 2649.16 seconds
Started Jul 15 06:57:30 PM PDT 24
Finished Jul 15 07:41:40 PM PDT 24
Peak memory 10579340 kb
Host smart-34e4073d-8894-4395-83dd-17e0861d4117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022538779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3022538779
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3724010155
Short name T410
Test name
Test status
Simulation time 4826854286 ps
CPU time 116.28 seconds
Started Jul 15 06:57:33 PM PDT 24
Finished Jul 15 06:59:30 PM PDT 24
Peak memory 739944 kb
Host smart-fd1bdec7-1784-42f1-b298-56a0997c350f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724010155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3724010155
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1319515765
Short name T559
Test name
Test status
Simulation time 1707427073 ps
CPU time 7.21 seconds
Started Jul 15 06:57:31 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 221980 kb
Host smart-43759d42-c256-45dd-b3e2-fd85a2d0f1e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319515765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1319515765
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.3366408895
Short name T859
Test name
Test status
Simulation time 461063016 ps
CPU time 7.39 seconds
Started Jul 15 06:57:34 PM PDT 24
Finished Jul 15 06:57:42 PM PDT 24
Peak memory 216168 kb
Host smart-eb055962-40f2-4865-80e8-68a5569c95b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366408895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.3366408895
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3177619836
Short name T354
Test name
Test status
Simulation time 40171218 ps
CPU time 0.62 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:57:43 PM PDT 24
Peak memory 204800 kb
Host smart-12e274ab-501e-4635-a782-511412e8d2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177619836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3177619836
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3672916510
Short name T1462
Test name
Test status
Simulation time 86423614 ps
CPU time 1.61 seconds
Started Jul 15 06:57:37 PM PDT 24
Finished Jul 15 06:57:39 PM PDT 24
Peak memory 213740 kb
Host smart-fd04368e-3f02-4b09-bf0d-4034e19b24ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672916510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3672916510
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.169511427
Short name T1679
Test name
Test status
Simulation time 186691846 ps
CPU time 3.7 seconds
Started Jul 15 06:57:37 PM PDT 24
Finished Jul 15 06:57:41 PM PDT 24
Peak memory 240400 kb
Host smart-8c7cd5f1-5344-4129-b1c4-d2bb4e421872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169511427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.169511427
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1943914995
Short name T601
Test name
Test status
Simulation time 8024780830 ps
CPU time 169.65 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 824056 kb
Host smart-f74c47da-3572-4149-9e30-7dfbabbfc090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943914995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1943914995
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.732904682
Short name T1171
Test name
Test status
Simulation time 8441883723 ps
CPU time 74.84 seconds
Started Jul 15 06:57:40 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 732108 kb
Host smart-27eda174-c15c-4d2c-b926-b4c7cfdafac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732904682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.732904682
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2683933887
Short name T1735
Test name
Test status
Simulation time 411230613 ps
CPU time 1.18 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:57:38 PM PDT 24
Peak memory 205212 kb
Host smart-d9e44bf1-ad8b-4042-a64c-1d871727cadb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683933887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2683933887
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1739926973
Short name T534
Test name
Test status
Simulation time 384825365 ps
CPU time 4.97 seconds
Started Jul 15 06:57:37 PM PDT 24
Finished Jul 15 06:57:43 PM PDT 24
Peak memory 205532 kb
Host smart-7d9c6327-efbb-4a7b-9950-ff94647fd990
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739926973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1739926973
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3872136927
Short name T1213
Test name
Test status
Simulation time 5329416105 ps
CPU time 224.68 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 07:01:21 PM PDT 24
Peak memory 1020036 kb
Host smart-77baeeac-c463-476a-8e61-2d566ff85e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872136927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3872136927
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2435257179
Short name T685
Test name
Test status
Simulation time 1302619740 ps
CPU time 5.15 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:49 PM PDT 24
Peak memory 205496 kb
Host smart-3d3b52bc-2bc1-45d7-b7e3-d2da64b50da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435257179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2435257179
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2372072551
Short name T267
Test name
Test status
Simulation time 66901563 ps
CPU time 1.41 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 205472 kb
Host smart-589b8042-43b6-4909-9581-e7a3b43db5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372072551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2372072551
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2492389898
Short name T652
Test name
Test status
Simulation time 80744101 ps
CPU time 0.68 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:57:37 PM PDT 24
Peak memory 205192 kb
Host smart-1f491313-6e33-4f5d-8a24-6ca5ae066f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492389898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2492389898
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1698830204
Short name T1212
Test name
Test status
Simulation time 7343575095 ps
CPU time 53.14 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:58:35 PM PDT 24
Peak memory 214856 kb
Host smart-536b1b51-f412-47b2-bde8-2bb6b794b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698830204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1698830204
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.4038962520
Short name T870
Test name
Test status
Simulation time 296399537 ps
CPU time 2.5 seconds
Started Jul 15 06:57:38 PM PDT 24
Finished Jul 15 06:57:41 PM PDT 24
Peak memory 205472 kb
Host smart-803f9078-b1e5-4dc0-8460-8fd212047268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038962520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.4038962520
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.224231607
Short name T368
Test name
Test status
Simulation time 1757340749 ps
CPU time 28.05 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 316928 kb
Host smart-d007daa3-73ef-4cb2-b1f9-9e8a3ad82e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224231607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.224231607
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.4092613141
Short name T189
Test name
Test status
Simulation time 34710174550 ps
CPU time 423.02 seconds
Started Jul 15 06:57:39 PM PDT 24
Finished Jul 15 07:04:43 PM PDT 24
Peak memory 1454292 kb
Host smart-8b014ac2-b050-444b-8c7c-419dfa1d68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092613141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.4092613141
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3182841930
Short name T1523
Test name
Test status
Simulation time 2312967921 ps
CPU time 9.09 seconds
Started Jul 15 06:57:38 PM PDT 24
Finished Jul 15 06:57:47 PM PDT 24
Peak memory 215748 kb
Host smart-a204833c-fb0b-4c0c-8e38-0d348383c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182841930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3182841930
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1960841298
Short name T952
Test name
Test status
Simulation time 4813086655 ps
CPU time 5.65 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:50 PM PDT 24
Peak memory 215024 kb
Host smart-82e1404a-17e3-4d97-9a6e-23c1c9d309c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960841298 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1960841298
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3732364102
Short name T710
Test name
Test status
Simulation time 134763718 ps
CPU time 0.9 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 205468 kb
Host smart-d6e0b7aa-1021-441a-98a6-745e53971de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732364102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3732364102
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2968968634
Short name T1014
Test name
Test status
Simulation time 865109314 ps
CPU time 1.51 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 06:57:46 PM PDT 24
Peak memory 205660 kb
Host smart-8154a0ea-d24b-4d2e-84bd-48e12338cf56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968968634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2968968634
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3077039663
Short name T584
Test name
Test status
Simulation time 1049951371 ps
CPU time 2.04 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 205436 kb
Host smart-9cd39616-2aaa-4145-9cbf-74969508c0d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077039663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3077039663
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.4116703457
Short name T1407
Test name
Test status
Simulation time 737926509 ps
CPU time 1.15 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 205424 kb
Host smart-8bd88346-c2d9-4532-be74-e91b62b80383
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116703457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.4116703457
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.566716135
Short name T834
Test name
Test status
Simulation time 581287746 ps
CPU time 2.06 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 213884 kb
Host smart-9fee6072-57ce-4a4e-9cbb-e985212853e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566716135 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.566716135
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3876503319
Short name T1476
Test name
Test status
Simulation time 2627069419 ps
CPU time 5.91 seconds
Started Jul 15 06:57:36 PM PDT 24
Finished Jul 15 06:57:42 PM PDT 24
Peak memory 222068 kb
Host smart-bf5b2abf-608c-42cc-aa8f-c93e412b1ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876503319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3876503319
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1912163954
Short name T289
Test name
Test status
Simulation time 7488585829 ps
CPU time 17.74 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:58:01 PM PDT 24
Peak memory 322064 kb
Host smart-d542a921-bafa-407a-8d0b-7f79e418b8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912163954 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1912163954
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.4004363024
Short name T73
Test name
Test status
Simulation time 1007816992 ps
CPU time 2.96 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 06:57:47 PM PDT 24
Peak memory 213860 kb
Host smart-aad26123-a981-4360-9e92-ccde7df85e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004363024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.4004363024
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.14590016
Short name T677
Test name
Test status
Simulation time 1050901701 ps
CPU time 2.68 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:47 PM PDT 24
Peak memory 205648 kb
Host smart-33b6c7fd-d452-4644-8f2e-64f44e03f888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14590016 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_nack_acqfull_addr.14590016
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_txstretch.3054045171
Short name T666
Test name
Test status
Simulation time 322225986 ps
CPU time 1.59 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 06:57:46 PM PDT 24
Peak memory 222572 kb
Host smart-6831f42a-f1ec-4735-8303-3eb487df9eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054045171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_nack_txstretch.3054045171
Directory /workspace/37.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/37.i2c_target_perf.3663320024
Short name T1394
Test name
Test status
Simulation time 1661170329 ps
CPU time 3.39 seconds
Started Jul 15 06:57:41 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 213836 kb
Host smart-71a4b45b-80a2-4f33-a1bf-0ab9a672fc8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663320024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.3663320024
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.402254842
Short name T1310
Test name
Test status
Simulation time 1937272483 ps
CPU time 2.03 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 205444 kb
Host smart-0819a32b-fc44-4c7d-8264-598aad0c3fec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402254842 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_smbus_maxlen.402254842
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2060311082
Short name T1515
Test name
Test status
Simulation time 1755948789 ps
CPU time 10.81 seconds
Started Jul 15 06:57:34 PM PDT 24
Finished Jul 15 06:57:45 PM PDT 24
Peak memory 213864 kb
Host smart-6ad7d278-add1-45e8-94f9-9e6ad61b4d9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060311082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2060311082
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3268081599
Short name T1112
Test name
Test status
Simulation time 26050373425 ps
CPU time 36.02 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 06:58:21 PM PDT 24
Peak memory 238476 kb
Host smart-b0c9d3b4-ba66-4015-9714-b929ee10169c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268081599 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3268081599
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3857851705
Short name T340
Test name
Test status
Simulation time 1538161551 ps
CPU time 7.21 seconds
Started Jul 15 06:57:38 PM PDT 24
Finished Jul 15 06:57:46 PM PDT 24
Peak memory 205872 kb
Host smart-202ce348-0f5b-4b17-a44f-964337c65a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857851705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3857851705
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3550287231
Short name T481
Test name
Test status
Simulation time 59480703527 ps
CPU time 687.89 seconds
Started Jul 15 06:57:38 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 4806732 kb
Host smart-75c5598b-54d7-4796-a3dc-06ba261cf3e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550287231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3550287231
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1287402282
Short name T1692
Test name
Test status
Simulation time 5718477145 ps
CPU time 23.28 seconds
Started Jul 15 06:57:35 PM PDT 24
Finished Jul 15 06:57:58 PM PDT 24
Peak memory 498104 kb
Host smart-2614fa85-d8f3-47f6-8e93-195b7e89a7e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287402282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1287402282
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.4136808216
Short name T1421
Test name
Test status
Simulation time 3484722528 ps
CPU time 7.47 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:51 PM PDT 24
Peak memory 222084 kb
Host smart-1b2d0e58-9846-4778-ae90-f9e563935a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136808216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.4136808216
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.2192131626
Short name T1068
Test name
Test status
Simulation time 1523459157 ps
CPU time 17.75 seconds
Started Jul 15 06:57:42 PM PDT 24
Finished Jul 15 06:58:01 PM PDT 24
Peak memory 205576 kb
Host smart-9799a894-4e93-4bfb-ac1c-084b45d889c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192131626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2192131626
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1456502995
Short name T1695
Test name
Test status
Simulation time 17192925 ps
CPU time 0.64 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:57:57 PM PDT 24
Peak memory 204512 kb
Host smart-24599525-21cd-4e51-90fa-1dcd5c4fbac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456502995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1456502995
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3035255871
Short name T909
Test name
Test status
Simulation time 62592727 ps
CPU time 1.51 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:57:52 PM PDT 24
Peak memory 213788 kb
Host smart-cc0bfeab-297b-4a6f-81b3-bf5858f9bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035255871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3035255871
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2160396397
Short name T1201
Test name
Test status
Simulation time 1418272129 ps
CPU time 18.9 seconds
Started Jul 15 06:57:47 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 283424 kb
Host smart-c5b0a165-61c0-406a-b801-8a49615e5f61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160396397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2160396397
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3897897705
Short name T1432
Test name
Test status
Simulation time 21854851817 ps
CPU time 88.22 seconds
Started Jul 15 06:57:52 PM PDT 24
Finished Jul 15 06:59:20 PM PDT 24
Peak memory 514744 kb
Host smart-0cfddcfc-ab0f-4a5f-aaa7-82f41914ec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897897705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3897897705
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2430073631
Short name T1282
Test name
Test status
Simulation time 4287506483 ps
CPU time 78.1 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 742500 kb
Host smart-b9e7a2f7-9c1e-4117-a479-dedcbcc7dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430073631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2430073631
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1355219193
Short name T752
Test name
Test status
Simulation time 99304359 ps
CPU time 0.96 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:57:51 PM PDT 24
Peak memory 205212 kb
Host smart-65a5bb1e-b6b2-4302-8d94-b5d8671fa47d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355219193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1355219193
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.482633864
Short name T655
Test name
Test status
Simulation time 133537449 ps
CPU time 3.54 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 06:57:54 PM PDT 24
Peak memory 226956 kb
Host smart-8fa21085-8f34-4ca2-a2c5-918816053f1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482633864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
482633864
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3336531498
Short name T721
Test name
Test status
Simulation time 4641779230 ps
CPU time 135.67 seconds
Started Jul 15 06:57:44 PM PDT 24
Finished Jul 15 07:00:01 PM PDT 24
Peak memory 1306568 kb
Host smart-30218d3c-b2b7-4215-8066-38de0f19172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336531498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3336531498
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3708713556
Short name T26
Test name
Test status
Simulation time 2492875682 ps
CPU time 8.27 seconds
Started Jul 15 06:57:55 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 205624 kb
Host smart-f429f7b0-da18-435b-906c-12265745d64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708713556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3708713556
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.2893704607
Short name T150
Test name
Test status
Simulation time 19357449 ps
CPU time 0.68 seconds
Started Jul 15 06:57:43 PM PDT 24
Finished Jul 15 06:57:44 PM PDT 24
Peak memory 205232 kb
Host smart-4285a825-412e-4170-a7be-f4779ee1cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893704607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2893704607
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.356577787
Short name T1483
Test name
Test status
Simulation time 18269154812 ps
CPU time 728.16 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 1275740 kb
Host smart-8f727b1b-a710-4684-9c48-7d6d77f9f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356577787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.356577787
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.1976480105
Short name T1690
Test name
Test status
Simulation time 95634505 ps
CPU time 1.91 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 06:57:52 PM PDT 24
Peak memory 213616 kb
Host smart-fd8934cb-bda6-470c-809f-181935cd7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976480105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1976480105
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4165427407
Short name T465
Test name
Test status
Simulation time 8103268978 ps
CPU time 35.14 seconds
Started Jul 15 06:57:45 PM PDT 24
Finished Jul 15 06:58:21 PM PDT 24
Peak memory 418296 kb
Host smart-b36ead1e-f175-4014-8c10-638a03fd92c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165427407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4165427407
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3510729256
Short name T344
Test name
Test status
Simulation time 3773666863 ps
CPU time 18.72 seconds
Started Jul 15 06:57:51 PM PDT 24
Finished Jul 15 06:58:10 PM PDT 24
Peak memory 221480 kb
Host smart-d3cc6188-68f4-4935-bb7d-7e37136921e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510729256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3510729256
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1088587021
Short name T688
Test name
Test status
Simulation time 2146560927 ps
CPU time 5 seconds
Started Jul 15 06:57:55 PM PDT 24
Finished Jul 15 06:58:01 PM PDT 24
Peak memory 214988 kb
Host smart-c9d877db-edb3-4f9d-ba56-23c6403887b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088587021 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1088587021
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3558357918
Short name T1174
Test name
Test status
Simulation time 1016817883 ps
CPU time 0.93 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:57:50 PM PDT 24
Peak memory 205420 kb
Host smart-cd891fe4-bfd4-4057-b39a-9363f098cc47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558357918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3558357918
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3839224685
Short name T168
Test name
Test status
Simulation time 311626379 ps
CPU time 2.12 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 06:57:53 PM PDT 24
Peak memory 212160 kb
Host smart-fb7a8193-205a-4813-af74-883a83319e65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839224685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3839224685
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.3096399634
Short name T1291
Test name
Test status
Simulation time 788729718 ps
CPU time 2.49 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:57:59 PM PDT 24
Peak memory 205684 kb
Host smart-6c03a8dd-aba2-4e63-a957-318492b270bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096399634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.3096399634
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2960639916
Short name T837
Test name
Test status
Simulation time 113718326 ps
CPU time 1.15 seconds
Started Jul 15 06:57:55 PM PDT 24
Finished Jul 15 06:57:56 PM PDT 24
Peak memory 205416 kb
Host smart-8bb82631-e5c5-4728-9929-687fe6c3c493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960639916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2960639916
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.292940678
Short name T96
Test name
Test status
Simulation time 778051591 ps
CPU time 1.75 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:57:59 PM PDT 24
Peak memory 213856 kb
Host smart-3cf060fe-2200-4443-bc2a-1b9f5758092f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292940678 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.292940678
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3880399836
Short name T900
Test name
Test status
Simulation time 2240861404 ps
CPU time 3.12 seconds
Started Jul 15 06:57:52 PM PDT 24
Finished Jul 15 06:57:55 PM PDT 24
Peak memory 213824 kb
Host smart-42dcf813-cde1-47ea-83e9-b838d3e33d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880399836 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3880399836
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1646156627
Short name T569
Test name
Test status
Simulation time 14526613276 ps
CPU time 56.5 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 06:58:47 PM PDT 24
Peak memory 1013600 kb
Host smart-6e784e54-2a3e-45e2-a48d-7f70da592ec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646156627 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1646156627
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.3540097996
Short name T1514
Test name
Test status
Simulation time 2100281865 ps
CPU time 2.72 seconds
Started Jul 15 06:57:54 PM PDT 24
Finished Jul 15 06:57:57 PM PDT 24
Peak memory 213760 kb
Host smart-d80bad28-d844-4886-af3f-0325af5fda6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540097996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.3540097996
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.3654883305
Short name T1159
Test name
Test status
Simulation time 1911294721 ps
CPU time 2.55 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 205584 kb
Host smart-7c6c8d69-0c8d-44af-9763-a241390c4cf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654883305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.3654883305
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1469655123
Short name T1505
Test name
Test status
Simulation time 2382591510 ps
CPU time 4.3 seconds
Started Jul 15 06:57:48 PM PDT 24
Finished Jul 15 06:57:53 PM PDT 24
Peak memory 217564 kb
Host smart-b5e56bae-9d5e-4b41-9823-cb0150e2ebd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469655123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1469655123
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.688510898
Short name T327
Test name
Test status
Simulation time 1943114377 ps
CPU time 2.33 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:58:00 PM PDT 24
Peak memory 205424 kb
Host smart-46f13f99-5f48-4cd9-af5a-fd15d0b5e4b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688510898 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_smbus_maxlen.688510898
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1078220743
Short name T1071
Test name
Test status
Simulation time 1681227404 ps
CPU time 10.76 seconds
Started Jul 15 06:57:51 PM PDT 24
Finished Jul 15 06:58:02 PM PDT 24
Peak memory 213828 kb
Host smart-a1c2178b-17fd-498c-8b3c-a16639601ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078220743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1078220743
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3801108113
Short name T631
Test name
Test status
Simulation time 40575279844 ps
CPU time 1648.83 seconds
Started Jul 15 06:57:59 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 7274360 kb
Host smart-a478e4be-36c9-4898-a879-edaef8681224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801108113 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3801108113
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3110086038
Short name T270
Test name
Test status
Simulation time 2384844042 ps
CPU time 65.02 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 217572 kb
Host smart-0378775e-d138-48ea-b566-692edaef9707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110086038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3110086038
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3779746889
Short name T405
Test name
Test status
Simulation time 10584231234 ps
CPU time 6.33 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:57:56 PM PDT 24
Peak memory 205672 kb
Host smart-25e54a6d-7a4c-43af-bd27-5f31340d34f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779746889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3779746889
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.774684306
Short name T552
Test name
Test status
Simulation time 3267015437 ps
CPU time 15.87 seconds
Started Jul 15 06:57:49 PM PDT 24
Finished Jul 15 06:58:05 PM PDT 24
Peak memory 335388 kb
Host smart-b090db67-9e79-44a6-a9aa-c4c65f2505a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774684306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.774684306
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1270203634
Short name T1352
Test name
Test status
Simulation time 2741842124 ps
CPU time 7.03 seconds
Started Jul 15 06:57:50 PM PDT 24
Finished Jul 15 06:57:58 PM PDT 24
Peak memory 214048 kb
Host smart-ef465070-1dcd-4ef0-a5e8-861614c7f1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270203634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1270203634
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.1830011445
Short name T638
Test name
Test status
Simulation time 226020668 ps
CPU time 2.82 seconds
Started Jul 15 06:57:59 PM PDT 24
Finished Jul 15 06:58:02 PM PDT 24
Peak memory 205652 kb
Host smart-ee75d7e8-0026-4f24-9a07-987bd0f5283b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830011445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.1830011445
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1799815202
Short name T190
Test name
Test status
Simulation time 97993348 ps
CPU time 0.64 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 204788 kb
Host smart-2336d34f-34e7-4d04-945c-903aad8f7855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799815202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1799815202
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2116672066
Short name T678
Test name
Test status
Simulation time 153197264 ps
CPU time 1.33 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:57:58 PM PDT 24
Peak memory 217412 kb
Host smart-5dd4d9bf-d3ab-46c3-853d-3e98738c3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116672066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2116672066
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3727137863
Short name T1709
Test name
Test status
Simulation time 305359482 ps
CPU time 14.63 seconds
Started Jul 15 06:57:55 PM PDT 24
Finished Jul 15 06:58:10 PM PDT 24
Peak memory 250460 kb
Host smart-77380a84-59ff-4edd-a18a-c3c0693f07d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727137863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3727137863
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.239692351
Short name T1648
Test name
Test status
Simulation time 4173991657 ps
CPU time 49.46 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 414456 kb
Host smart-f6d1b521-9534-4bae-afff-20e1b7d49ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239692351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.239692351
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2060200934
Short name T782
Test name
Test status
Simulation time 3225137444 ps
CPU time 83.11 seconds
Started Jul 15 06:58:00 PM PDT 24
Finished Jul 15 06:59:23 PM PDT 24
Peak memory 519188 kb
Host smart-dc9f93d2-6031-40fd-8ef4-f15a8fd5c973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060200934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2060200934
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1719359747
Short name T1506
Test name
Test status
Simulation time 177670448 ps
CPU time 1.16 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:03 PM PDT 24
Peak memory 205372 kb
Host smart-049bbcbd-b961-486f-b34b-3c88c926d040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719359747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1719359747
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3239726031
Short name T1313
Test name
Test status
Simulation time 170465551 ps
CPU time 8.94 seconds
Started Jul 15 06:57:59 PM PDT 24
Finished Jul 15 06:58:09 PM PDT 24
Peak memory 205528 kb
Host smart-969864c9-9c84-4be3-8be8-93f188bad721
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239726031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3239726031
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1794966320
Short name T112
Test name
Test status
Simulation time 3810646258 ps
CPU time 86.91 seconds
Started Jul 15 06:57:57 PM PDT 24
Finished Jul 15 06:59:24 PM PDT 24
Peak memory 1118576 kb
Host smart-219cf58b-9cd4-4608-8c0e-63d6c04fd157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794966320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1794966320
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3058880856
Short name T1182
Test name
Test status
Simulation time 1788934710 ps
CPU time 18.51 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:20 PM PDT 24
Peak memory 205424 kb
Host smart-d89980f1-6c0b-44d4-86a9-03e357bb8c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058880856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3058880856
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2049441134
Short name T1025
Test name
Test status
Simulation time 581431792 ps
CPU time 5.52 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:15 PM PDT 24
Peak memory 213600 kb
Host smart-e5c93579-ce4e-48aa-8fee-42a2e1f8bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049441134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2049441134
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3313737358
Short name T1296
Test name
Test status
Simulation time 29040965 ps
CPU time 0.67 seconds
Started Jul 15 06:57:57 PM PDT 24
Finished Jul 15 06:57:58 PM PDT 24
Peak memory 205184 kb
Host smart-d3ccc4d9-f032-4f86-9de4-5fc39d0e58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313737358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3313737358
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3592207287
Short name T722
Test name
Test status
Simulation time 5409510985 ps
CPU time 55.54 seconds
Started Jul 15 06:57:54 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 539328 kb
Host smart-4fb9e2de-a94d-414b-ab6a-b4992e1ad124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592207287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3592207287
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.2367329449
Short name T514
Test name
Test status
Simulation time 103483052 ps
CPU time 1.15 seconds
Started Jul 15 06:57:57 PM PDT 24
Finished Jul 15 06:57:59 PM PDT 24
Peak memory 205484 kb
Host smart-0e24d0a7-653f-45d5-93a5-038fb443318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367329449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2367329449
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2221480
Short name T1077
Test name
Test status
Simulation time 1895308755 ps
CPU time 14.32 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:16 PM PDT 24
Peak memory 256912 kb
Host smart-ace4fb41-1dd5-4857-9f1b-0d65388144e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2221480
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.2371018593
Short name T965
Test name
Test status
Simulation time 44048883737 ps
CPU time 920.62 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 07:13:23 PM PDT 24
Peak memory 1328772 kb
Host smart-4de4d2ae-d3f6-497e-a7f9-8e3281b43cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371018593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.2371018593
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1396424494
Short name T1656
Test name
Test status
Simulation time 1168125820 ps
CPU time 16.34 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:58:13 PM PDT 24
Peak memory 229404 kb
Host smart-22d27aec-c485-45eb-bab6-78c7d9f0e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396424494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1396424494
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3850812162
Short name T714
Test name
Test status
Simulation time 4517749817 ps
CPU time 5.85 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:09 PM PDT 24
Peak memory 209100 kb
Host smart-a24284c9-acc6-4c95-97bc-cde1443de060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850812162 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3850812162
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.812653216
Short name T248
Test name
Test status
Simulation time 220579772 ps
CPU time 0.78 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 205432 kb
Host smart-7deeee7c-7a2f-47a0-a91e-c10b3dd58bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812653216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.812653216
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1639981783
Short name T1018
Test name
Test status
Simulation time 822998141 ps
CPU time 1.15 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:03 PM PDT 24
Peak memory 205612 kb
Host smart-c721ff14-273d-4cab-8fdb-20644e3ad46e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639981783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1639981783
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.2646447349
Short name T1550
Test name
Test status
Simulation time 635772074 ps
CPU time 3.25 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:14 PM PDT 24
Peak memory 205532 kb
Host smart-ec4f0a47-f81c-44ba-a107-0a62c1123e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646447349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2646447349
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2266289747
Short name T1205
Test name
Test status
Simulation time 749845639 ps
CPU time 1.65 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 205464 kb
Host smart-0ba21386-9d51-4735-a31c-bc2e6664f44a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266289747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2266289747
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.4258693934
Short name T1248
Test name
Test status
Simulation time 1240325431 ps
CPU time 4.74 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 213764 kb
Host smart-3daae084-50b2-46aa-b5e1-a8247dea2b93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258693934 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.4258693934
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2019810114
Short name T1123
Test name
Test status
Simulation time 18337397229 ps
CPU time 40.07 seconds
Started Jul 15 06:57:59 PM PDT 24
Finished Jul 15 06:58:40 PM PDT 24
Peak memory 992608 kb
Host smart-df147de0-cb9a-418a-86c3-fb55104c7fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019810114 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2019810114
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.327137031
Short name T197
Test name
Test status
Simulation time 542416553 ps
CPU time 2.95 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 213808 kb
Host smart-b9b7fc0f-5dda-4ca4-acef-9529fa6ea00c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327137031 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_nack_acqfull.327137031
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.1742670204
Short name T645
Test name
Test status
Simulation time 557389692 ps
CPU time 1.61 seconds
Started Jul 15 06:58:06 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 222316 kb
Host smart-a9fc35a8-befe-4fb9-8eb5-f1ff04c1d772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742670204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_nack_txstretch.1742670204
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.868158562
Short name T606
Test name
Test status
Simulation time 3516871238 ps
CPU time 5.89 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:10 PM PDT 24
Peak memory 215216 kb
Host smart-018f241c-6e95-454a-b084-6b063c1370bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868158562 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_perf.868158562
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3671516235
Short name T298
Test name
Test status
Simulation time 1746903408 ps
CPU time 2.17 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 06:58:04 PM PDT 24
Peak memory 205376 kb
Host smart-19c2bdb2-98d6-419b-a6f7-7658324760bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671516235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3671516235
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3851997015
Short name T562
Test name
Test status
Simulation time 3524014530 ps
CPU time 28.67 seconds
Started Jul 15 06:57:59 PM PDT 24
Finished Jul 15 06:58:29 PM PDT 24
Peak memory 217456 kb
Host smart-23fdd54c-dbb1-4e80-a0bb-7b2ed8233fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851997015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3851997015
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2552106896
Short name T1113
Test name
Test status
Simulation time 103735518923 ps
CPU time 260.23 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 2338836 kb
Host smart-b553a5d6-1628-4b0b-9112-b35dacf99688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552106896 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2552106896
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.558808354
Short name T817
Test name
Test status
Simulation time 2383015916 ps
CPU time 54.64 seconds
Started Jul 15 06:58:00 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 217008 kb
Host smart-4f17a4bf-f758-4d01-b9da-89d8fe42b54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558808354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.558808354
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.352458920
Short name T617
Test name
Test status
Simulation time 50131943063 ps
CPU time 467.99 seconds
Started Jul 15 06:57:58 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 3808704 kb
Host smart-65c67cc5-d670-48ae-8794-ac670bccbf18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352458920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.352458920
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.814938667
Short name T1145
Test name
Test status
Simulation time 1392530704 ps
CPU time 9.59 seconds
Started Jul 15 06:57:56 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 291072 kb
Host smart-7cff9fd0-a044-4a18-bbed-69e3c986529a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814938667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.814938667
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.377187198
Short name T850
Test name
Test status
Simulation time 5377105510 ps
CPU time 7.24 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:09 PM PDT 24
Peak memory 222044 kb
Host smart-6aaf3871-52ea-43d7-8363-8ef9da8272dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377187198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.377187198
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.4022312822
Short name T608
Test name
Test status
Simulation time 126731009 ps
CPU time 2.59 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 205616 kb
Host smart-a949cc0c-d8d5-409d-b6f4-440f13043d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022312822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.4022312822
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2877486739
Short name T1649
Test name
Test status
Simulation time 28394082 ps
CPU time 0.67 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:19 PM PDT 24
Peak memory 204844 kb
Host smart-cb7239c5-2870-4f84-b325-a736e12842a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877486739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2877486739
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3244050878
Short name T1536
Test name
Test status
Simulation time 2188901932 ps
CPU time 2.96 seconds
Started Jul 15 06:52:05 PM PDT 24
Finished Jul 15 06:52:08 PM PDT 24
Peak memory 229972 kb
Host smart-37e1021f-aa02-4f3c-b43d-8f10f58c9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244050878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3244050878
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2087278949
Short name T801
Test name
Test status
Simulation time 401919516 ps
CPU time 7.24 seconds
Started Jul 15 06:52:03 PM PDT 24
Finished Jul 15 06:52:11 PM PDT 24
Peak memory 288556 kb
Host smart-42b81693-587c-4cf9-94f9-b86c27fca11f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087278949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2087278949
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2194783983
Short name T48
Test name
Test status
Simulation time 3194674228 ps
CPU time 123 seconds
Started Jul 15 06:52:03 PM PDT 24
Finished Jul 15 06:54:06 PM PDT 24
Peak memory 662032 kb
Host smart-635931e9-41a7-4471-938a-6e8d8ed224aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194783983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2194783983
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.104722747
Short name T1244
Test name
Test status
Simulation time 5874113151 ps
CPU time 44.35 seconds
Started Jul 15 06:52:07 PM PDT 24
Finished Jul 15 06:52:51 PM PDT 24
Peak memory 464048 kb
Host smart-6f659d64-5894-47bd-ae58-6542b548508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104722747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.104722747
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2791039899
Short name T1477
Test name
Test status
Simulation time 508841819 ps
CPU time 1.04 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:04 PM PDT 24
Peak memory 205244 kb
Host smart-aa514c1b-61b1-4486-85b1-fe388ce9abf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791039899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2791039899
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3281506353
Short name T185
Test name
Test status
Simulation time 5168717782 ps
CPU time 154.27 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:54:37 PM PDT 24
Peak memory 1442720 kb
Host smart-eeaadeab-87f2-44e1-a914-86bf5000f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281506353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3281506353
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2553804805
Short name T272
Test name
Test status
Simulation time 809478882 ps
CPU time 8.94 seconds
Started Jul 15 06:52:07 PM PDT 24
Finished Jul 15 06:52:17 PM PDT 24
Peak memory 205552 kb
Host smart-94911ed3-b274-4869-8ef7-4d3330083402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553804805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2553804805
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.2154648748
Short name T100
Test name
Test status
Simulation time 17666382 ps
CPU time 0.64 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:02 PM PDT 24
Peak memory 205220 kb
Host smart-3abf59c1-89e0-4c2f-ace0-25b1c9fb7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154648748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2154648748
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2677363612
Short name T591
Test name
Test status
Simulation time 2912517518 ps
CPU time 35.91 seconds
Started Jul 15 06:52:08 PM PDT 24
Finished Jul 15 06:52:44 PM PDT 24
Peak memory 223388 kb
Host smart-b70ace4c-d80d-4239-ac49-484c7cda2b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677363612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2677363612
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.2015284116
Short name T1521
Test name
Test status
Simulation time 2814111830 ps
CPU time 7.84 seconds
Started Jul 15 06:52:05 PM PDT 24
Finished Jul 15 06:52:13 PM PDT 24
Peak memory 226296 kb
Host smart-8c2539c0-ee12-4f23-a210-0560f8f6ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015284116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.2015284116
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.817656048
Short name T689
Test name
Test status
Simulation time 1658991533 ps
CPU time 26.52 seconds
Started Jul 15 06:52:06 PM PDT 24
Finished Jul 15 06:52:33 PM PDT 24
Peak memory 362824 kb
Host smart-00807811-33f7-4eff-82d1-14ea713bf2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817656048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.817656048
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.324017176
Short name T1183
Test name
Test status
Simulation time 4076010206 ps
CPU time 15.22 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 221980 kb
Host smart-82f3eea1-4e75-48d6-a1ec-9f36537a97e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324017176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.324017176
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2307620841
Short name T194
Test name
Test status
Simulation time 80231860 ps
CPU time 0.84 seconds
Started Jul 15 06:52:17 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 223872 kb
Host smart-c5ec78b8-7a13-4ff8-8378-0a95d43c7b19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307620841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2307620841
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2433617267
Short name T1022
Test name
Test status
Simulation time 5045015691 ps
CPU time 4.58 seconds
Started Jul 15 06:52:10 PM PDT 24
Finished Jul 15 06:52:15 PM PDT 24
Peak memory 213860 kb
Host smart-a88c8caf-7601-423e-a35d-287c46bff66c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433617267 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2433617267
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3629642648
Short name T322
Test name
Test status
Simulation time 146236227 ps
CPU time 1.13 seconds
Started Jul 15 06:52:07 PM PDT 24
Finished Jul 15 06:52:09 PM PDT 24
Peak memory 205492 kb
Host smart-1e7e5aca-f01a-4e3d-a8b6-0148af87faff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629642648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3629642648
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3846668903
Short name T1681
Test name
Test status
Simulation time 1101772230 ps
CPU time 1.85 seconds
Started Jul 15 06:52:12 PM PDT 24
Finished Jul 15 06:52:14 PM PDT 24
Peak memory 206748 kb
Host smart-adee0b5f-7e66-411e-b744-05c1e2e7d9ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846668903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3846668903
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.2252377250
Short name T532
Test name
Test status
Simulation time 214513362 ps
CPU time 1.41 seconds
Started Jul 15 06:52:11 PM PDT 24
Finished Jul 15 06:52:13 PM PDT 24
Peak memory 205448 kb
Host smart-90545eb2-0a88-400f-bed7-e99f7b1b35e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252377250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.2252377250
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.3160093514
Short name T1684
Test name
Test status
Simulation time 154810398 ps
CPU time 1.24 seconds
Started Jul 15 06:52:10 PM PDT 24
Finished Jul 15 06:52:11 PM PDT 24
Peak memory 205428 kb
Host smart-71ee6e17-bf5c-474d-b2c5-6cefe7998138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160093514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.3160093514
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3887054954
Short name T1088
Test name
Test status
Simulation time 1078684402 ps
CPU time 3.79 seconds
Started Jul 15 06:52:03 PM PDT 24
Finished Jul 15 06:52:08 PM PDT 24
Peak memory 219840 kb
Host smart-26568c68-63fb-42d9-afee-29e5e97f335a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887054954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3887054954
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2376343797
Short name T703
Test name
Test status
Simulation time 4336646362 ps
CPU time 8.94 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:11 PM PDT 24
Peak memory 205660 kb
Host smart-697912bf-7bf9-4f2e-88af-ad68e4cf0129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376343797 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2376343797
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.2971115890
Short name T71
Test name
Test status
Simulation time 546014303 ps
CPU time 2.96 seconds
Started Jul 15 06:52:14 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 213840 kb
Host smart-93aa3afb-3039-4fab-8bea-9d2f61203433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971115890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.2971115890
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.3948899614
Short name T163
Test name
Test status
Simulation time 892983478 ps
CPU time 2.65 seconds
Started Jul 15 06:52:15 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 205600 kb
Host smart-34c25b5f-1d56-48dc-96cf-bd2410ab64ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948899614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.3948899614
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.280604449
Short name T56
Test name
Test status
Simulation time 400782629 ps
CPU time 1.5 seconds
Started Jul 15 06:52:15 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 222320 kb
Host smart-d85b755b-d4d2-4ef4-8c84-720db23e357f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280604449 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_nack_txstretch.280604449
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.3259344097
Short name T1442
Test name
Test status
Simulation time 710522835 ps
CPU time 2.84 seconds
Started Jul 15 06:52:09 PM PDT 24
Finished Jul 15 06:52:12 PM PDT 24
Peak memory 213824 kb
Host smart-cb719200-de97-4eae-8cdf-9c2df0cc4cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259344097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.3259344097
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.939828932
Short name T589
Test name
Test status
Simulation time 441319025 ps
CPU time 2.3 seconds
Started Jul 15 06:52:15 PM PDT 24
Finished Jul 15 06:52:18 PM PDT 24
Peak memory 205500 kb
Host smart-92f99f00-58e5-4b93-9f04-73932212873e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939828932 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_smbus_maxlen.939828932
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2393758558
Short name T422
Test name
Test status
Simulation time 842016023 ps
CPU time 13.18 seconds
Started Jul 15 06:52:02 PM PDT 24
Finished Jul 15 06:52:15 PM PDT 24
Peak memory 213856 kb
Host smart-d95c2e65-5b40-4cec-ba4f-dac2ffd5a421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393758558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2393758558
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.1421707262
Short name T381
Test name
Test status
Simulation time 56162665473 ps
CPU time 3214.83 seconds
Started Jul 15 06:52:10 PM PDT 24
Finished Jul 15 07:45:46 PM PDT 24
Peak memory 10900672 kb
Host smart-3cf2038f-5a9f-4f72-ba13-063edd1567c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421707262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.1421707262
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.164019908
Short name T1397
Test name
Test status
Simulation time 6098833882 ps
CPU time 29.87 seconds
Started Jul 15 06:52:03 PM PDT 24
Finished Jul 15 06:52:34 PM PDT 24
Peak memory 231860 kb
Host smart-26b4cdbf-7421-4793-8dc4-c52c0d3c26b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164019908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.164019908
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3026008155
Short name T1287
Test name
Test status
Simulation time 28732881337 ps
CPU time 31.48 seconds
Started Jul 15 06:52:07 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 635040 kb
Host smart-4d217126-1c06-410c-9b36-6a33188bc21f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026008155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3026008155
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3756574933
Short name T1574
Test name
Test status
Simulation time 3573763308 ps
CPU time 7.29 seconds
Started Jul 15 06:52:01 PM PDT 24
Finished Jul 15 06:52:09 PM PDT 24
Peak memory 205516 kb
Host smart-561c6b15-9699-4b51-9bee-6899a3b3ac56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756574933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3756574933
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2237377833
Short name T848
Test name
Test status
Simulation time 1123057700 ps
CPU time 6.7 seconds
Started Jul 15 06:52:04 PM PDT 24
Finished Jul 15 06:52:12 PM PDT 24
Peak memory 222008 kb
Host smart-55b170c2-72ae-4b3a-9476-a7f9cbb8ccc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237377833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2237377833
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1837018486
Short name T1562
Test name
Test status
Simulation time 188810481 ps
CPU time 3.37 seconds
Started Jul 15 06:52:17 PM PDT 24
Finished Jul 15 06:52:21 PM PDT 24
Peak memory 205776 kb
Host smart-335fb956-fb6c-450d-8f92-9da38a666bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837018486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1837018486
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2271818519
Short name T1410
Test name
Test status
Simulation time 34466894 ps
CPU time 0.71 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:11 PM PDT 24
Peak memory 204768 kb
Host smart-511c93b5-d0aa-4f5e-9fb1-0b320091a120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271818519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2271818519
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2319526235
Short name T20
Test name
Test status
Simulation time 397525612 ps
CPU time 3.83 seconds
Started Jul 15 06:58:04 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 253496 kb
Host smart-a8e23941-a2b1-443c-a869-99656dd47eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319526235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2319526235
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2635931190
Short name T860
Test name
Test status
Simulation time 843356945 ps
CPU time 21.6 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 291116 kb
Host smart-268c933a-2ef9-4575-89a5-58b176a770fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635931190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2635931190
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1365684763
Short name T160
Test name
Test status
Simulation time 2516002518 ps
CPU time 164.18 seconds
Started Jul 15 06:58:04 PM PDT 24
Finished Jul 15 07:00:49 PM PDT 24
Peak memory 512008 kb
Host smart-3a6fd738-3960-49e3-86fa-aaeb3a66dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365684763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1365684763
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1371387077
Short name T101
Test name
Test status
Simulation time 1574140240 ps
CPU time 45.03 seconds
Started Jul 15 06:58:05 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 464080 kb
Host smart-15f22519-1043-4f00-853b-3e8759565d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371387077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1371387077
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1650272454
Short name T1199
Test name
Test status
Simulation time 660902689 ps
CPU time 1.14 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:02 PM PDT 24
Peak memory 205252 kb
Host smart-04fc6921-34f4-4396-91e4-5188537f5bfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650272454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1650272454
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1514475377
Short name T500
Test name
Test status
Simulation time 687473087 ps
CPU time 6.45 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:08 PM PDT 24
Peak memory 251936 kb
Host smart-49a27cac-a6b0-464a-9a17-236b74026c8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514475377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1514475377
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3140737823
Short name T879
Test name
Test status
Simulation time 16697350575 ps
CPU time 107.25 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:59:51 PM PDT 24
Peak memory 1085444 kb
Host smart-4e66fa78-f5ad-4515-8a5b-2e31b3c8e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140737823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3140737823
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1935528302
Short name T262
Test name
Test status
Simulation time 5548044578 ps
CPU time 8.21 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 205576 kb
Host smart-05507515-5415-4757-a4b8-896bfd0f0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935528302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1935528302
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.3035643040
Short name T1253
Test name
Test status
Simulation time 18637076 ps
CPU time 0.68 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:58:30 PM PDT 24
Peak memory 205080 kb
Host smart-5e19c411-ad9c-4705-a4ce-e65d04b12bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035643040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3035643040
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2025656620
Short name T1601
Test name
Test status
Simulation time 28850625948 ps
CPU time 224.2 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 1300840 kb
Host smart-55fedcf8-882f-437c-b2cb-d36981b88f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025656620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2025656620
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.3260921351
Short name T517
Test name
Test status
Simulation time 43643701 ps
CPU time 1.53 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:06 PM PDT 24
Peak memory 229928 kb
Host smart-4744f976-16c9-4b24-836e-775682b534eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260921351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3260921351
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1747208202
Short name T477
Test name
Test status
Simulation time 1223395994 ps
CPU time 23.5 seconds
Started Jul 15 06:58:04 PM PDT 24
Finished Jul 15 06:58:28 PM PDT 24
Peak memory 323072 kb
Host smart-b67ee816-8b08-4d0e-aa3c-0d3715504fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747208202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1747208202
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1663935500
Short name T388
Test name
Test status
Simulation time 3713829686 ps
CPU time 35.8 seconds
Started Jul 15 06:58:01 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 213848 kb
Host smart-b72fd826-4f56-4446-8446-4384d648f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663935500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1663935500
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3517083493
Short name T1204
Test name
Test status
Simulation time 1878525103 ps
CPU time 2.49 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:13 PM PDT 24
Peak memory 205632 kb
Host smart-96e156c8-c40b-4d79-a2ee-0ccf4b079d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517083493 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3517083493
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3079524252
Short name T614
Test name
Test status
Simulation time 302721979 ps
CPU time 1.35 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:12 PM PDT 24
Peak memory 205628 kb
Host smart-d56cbbc5-e5a4-4d62-ac29-a32815149126
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079524252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3079524252
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1154796582
Short name T1585
Test name
Test status
Simulation time 343073347 ps
CPU time 1.03 seconds
Started Jul 15 06:58:11 PM PDT 24
Finished Jul 15 06:58:13 PM PDT 24
Peak memory 205472 kb
Host smart-c18817bc-c16c-4050-aa39-a65e4b48f3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154796582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1154796582
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.3204681557
Short name T940
Test name
Test status
Simulation time 1089266687 ps
CPU time 2.67 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:13 PM PDT 24
Peak memory 205684 kb
Host smart-c559d124-3afa-4fcf-b4be-c0ee439bf407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204681557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3204681557
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.195560461
Short name T1083
Test name
Test status
Simulation time 866626345 ps
CPU time 1.22 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:12 PM PDT 24
Peak memory 205420 kb
Host smart-ad5ebe9c-a8db-41f7-87b2-4a443e2e03c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195560461 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.195560461
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.414487414
Short name T595
Test name
Test status
Simulation time 580935996 ps
CPU time 2.14 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:12 PM PDT 24
Peak memory 213796 kb
Host smart-b43e9aff-f659-4226-9eb8-e4e8cdec44fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414487414 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.414487414
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3324017322
Short name T717
Test name
Test status
Simulation time 3976051296 ps
CPU time 5.89 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:58:23 PM PDT 24
Peak memory 217876 kb
Host smart-fa96be02-096d-45f8-87fa-98819242ceff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324017322 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3324017322
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.37555352
Short name T1657
Test name
Test status
Simulation time 20115195531 ps
CPU time 389.34 seconds
Started Jul 15 06:58:11 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 3383052 kb
Host smart-163d9545-b684-416e-87b7-5e26f309c7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555352 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.37555352
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.2269412178
Short name T875
Test name
Test status
Simulation time 1081362794 ps
CPU time 2.76 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:14 PM PDT 24
Peak memory 213844 kb
Host smart-0db669e4-2f4d-4558-a345-2d516cb935c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269412178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.2269412178
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.2217171043
Short name T1284
Test name
Test status
Simulation time 4914626924 ps
CPU time 2.92 seconds
Started Jul 15 06:58:12 PM PDT 24
Finished Jul 15 06:58:15 PM PDT 24
Peak memory 205688 kb
Host smart-100f7910-6ebd-419a-8c5d-c928178adcf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217171043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.2217171043
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_txstretch.3526912620
Short name T574
Test name
Test status
Simulation time 311063873 ps
CPU time 1.34 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:11 PM PDT 24
Peak memory 222136 kb
Host smart-074161a1-8dfd-4350-a8da-2f25223bf891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526912620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_nack_txstretch.3526912620
Directory /workspace/40.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/40.i2c_target_perf.4165861621
Short name T1138
Test name
Test status
Simulation time 942391599 ps
CPU time 6.6 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 222016 kb
Host smart-6a7cf006-66e4-4f1a-8f70-1304e24ba7d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165861621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.4165861621
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.3073635673
Short name T315
Test name
Test status
Simulation time 1074653940 ps
CPU time 2.45 seconds
Started Jul 15 06:58:11 PM PDT 24
Finished Jul 15 06:58:14 PM PDT 24
Peak memory 205368 kb
Host smart-2612906f-ece4-4018-b559-e62b568bc9ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073635673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.3073635673
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.568990768
Short name T540
Test name
Test status
Simulation time 810771591 ps
CPU time 25.07 seconds
Started Jul 15 06:58:03 PM PDT 24
Finished Jul 15 06:58:29 PM PDT 24
Peak memory 213808 kb
Host smart-c2277269-f383-4f7c-ab6d-4d5aa320dc0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568990768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.568990768
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.435392428
Short name T435
Test name
Test status
Simulation time 43076371314 ps
CPU time 151.74 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 07:00:43 PM PDT 24
Peak memory 1133452 kb
Host smart-a54317ed-aaca-4bd7-9dd5-cb569c5d3114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435392428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_stress_all.435392428
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2283414496
Short name T1546
Test name
Test status
Simulation time 2449240314 ps
CPU time 14.73 seconds
Started Jul 15 06:58:07 PM PDT 24
Finished Jul 15 06:58:22 PM PDT 24
Peak memory 221980 kb
Host smart-4bc3b470-ef1a-4ee8-9973-5a14dd96189c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283414496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2283414496
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1148316810
Short name T862
Test name
Test status
Simulation time 49038810509 ps
CPU time 1424.98 seconds
Started Jul 15 06:58:02 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 7579676 kb
Host smart-2d83f82d-eaa6-4a8c-9114-37e87d3a839a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148316810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1148316810
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3357752253
Short name T706
Test name
Test status
Simulation time 2532202229 ps
CPU time 2.09 seconds
Started Jul 15 06:58:11 PM PDT 24
Finished Jul 15 06:58:14 PM PDT 24
Peak memory 205508 kb
Host smart-4f6a2344-cf58-40f5-b6f4-117450bb935d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357752253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3357752253
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3830061286
Short name T812
Test name
Test status
Simulation time 2593300939 ps
CPU time 6.79 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 222008 kb
Host smart-48dfc168-1fe4-421c-adf6-a7c4e5915467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830061286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3830061286
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.645326743
Short name T656
Test name
Test status
Simulation time 118877624 ps
CPU time 1.62 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:13 PM PDT 24
Peak memory 205584 kb
Host smart-626f0cb8-1100-4e57-9dc5-5d3a4a1ff464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645326743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.645326743
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2053125191
Short name T1374
Test name
Test status
Simulation time 18447652 ps
CPU time 0.65 seconds
Started Jul 15 06:58:23 PM PDT 24
Finished Jul 15 06:58:24 PM PDT 24
Peak memory 204704 kb
Host smart-b01702c1-61c3-48c2-8e7f-b9545b4e9b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053125191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2053125191
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.910841401
Short name T698
Test name
Test status
Simulation time 624959095 ps
CPU time 2.14 seconds
Started Jul 15 06:58:13 PM PDT 24
Finished Jul 15 06:58:16 PM PDT 24
Peak memory 213840 kb
Host smart-e43294b1-ec4e-4982-b09c-095d3722705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910841401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.910841401
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3369153356
Short name T829
Test name
Test status
Simulation time 1449860321 ps
CPU time 8.84 seconds
Started Jul 15 06:58:11 PM PDT 24
Finished Jul 15 06:58:21 PM PDT 24
Peak memory 295600 kb
Host smart-ef20fc90-527c-44f6-a1a6-16b3b924ebed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369153356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3369153356
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.4170515477
Short name T1547
Test name
Test status
Simulation time 5979325106 ps
CPU time 192.22 seconds
Started Jul 15 06:58:08 PM PDT 24
Finished Jul 15 07:01:21 PM PDT 24
Peak memory 594720 kb
Host smart-653afdcb-0366-46ae-bee5-4f66781ab777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170515477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.4170515477
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.229346781
Short name T1607
Test name
Test status
Simulation time 8426265813 ps
CPU time 152.1 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 07:00:43 PM PDT 24
Peak memory 729936 kb
Host smart-e1f9bed7-c256-4bb9-9a68-6db911c30661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229346781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.229346781
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2068868884
Short name T251
Test name
Test status
Simulation time 165457054 ps
CPU time 0.89 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:11 PM PDT 24
Peak memory 205264 kb
Host smart-d8d937d6-d0fa-4fb9-9a6e-7f8a0c946345
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068868884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2068868884
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.79996312
Short name T1336
Test name
Test status
Simulation time 221079659 ps
CPU time 2.56 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:12 PM PDT 24
Peak memory 205504 kb
Host smart-0d2e815b-df84-4522-bf3b-9c3a1ecff810
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79996312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.79996312
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.718439935
Short name T1691
Test name
Test status
Simulation time 3339146519 ps
CPU time 94.35 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:59:45 PM PDT 24
Peak memory 1038836 kb
Host smart-1de88c67-13ab-4b82-99f9-77d2d9ec2fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718439935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.718439935
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_override.551024502
Short name T1520
Test name
Test status
Simulation time 16931041 ps
CPU time 0.68 seconds
Started Jul 15 06:58:09 PM PDT 24
Finished Jul 15 06:58:11 PM PDT 24
Peak memory 205192 kb
Host smart-f1512fdd-905c-4ac5-a773-b2c47f35d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551024502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.551024502
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.598163018
Short name T1010
Test name
Test status
Simulation time 26200725807 ps
CPU time 23.55 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:39 PM PDT 24
Peak memory 213752 kb
Host smart-aba04f54-f23c-446b-8c55-864aec032cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598163018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.598163018
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3831239742
Short name T1332
Test name
Test status
Simulation time 70371735 ps
CPU time 2.91 seconds
Started Jul 15 06:58:18 PM PDT 24
Finished Jul 15 06:58:21 PM PDT 24
Peak memory 206136 kb
Host smart-2ed4f6b5-37d6-47a9-8b1a-cc528679f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831239742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3831239742
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.818712268
Short name T1571
Test name
Test status
Simulation time 4518030546 ps
CPU time 39.1 seconds
Started Jul 15 06:58:10 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 359916 kb
Host smart-e5ed2622-dece-4358-928d-70bfc9cb4cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818712268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.818712268
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.223155366
Short name T1266
Test name
Test status
Simulation time 6395616647 ps
CPU time 9.6 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:25 PM PDT 24
Peak memory 216944 kb
Host smart-c8a6e15d-26df-4846-a906-e2e941066cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223155366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.223155366
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.644507926
Short name T626
Test name
Test status
Simulation time 3888678774 ps
CPU time 5.15 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:21 PM PDT 24
Peak memory 214172 kb
Host smart-764f5cc0-ce3f-40fc-aa07-08f770df6af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644507926 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.644507926
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1158357208
Short name T1672
Test name
Test status
Simulation time 532265977 ps
CPU time 1.13 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 205444 kb
Host smart-3ba8070e-865e-42ca-a4ad-18102d56fcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158357208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1158357208
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3666357439
Short name T510
Test name
Test status
Simulation time 214360939 ps
CPU time 1.32 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:16 PM PDT 24
Peak memory 205604 kb
Host smart-b970661c-ed56-411c-bb8d-54ee54e9e5f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666357439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3666357439
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.2251287380
Short name T1161
Test name
Test status
Simulation time 194987096 ps
CPU time 1.36 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:17 PM PDT 24
Peak memory 205444 kb
Host smart-674413fd-d215-41cc-b835-bb219b6bdad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251287380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.2251287380
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1202868871
Short name T1
Test name
Test status
Simulation time 263783604 ps
CPU time 1.03 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:16 PM PDT 24
Peak memory 205476 kb
Host smart-87a12de0-ba9e-4b6e-a73c-a70b296fa604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202868871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1202868871
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2152608068
Short name T1576
Test name
Test status
Simulation time 3236420416 ps
CPU time 2.53 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:58:19 PM PDT 24
Peak memory 213872 kb
Host smart-e7fc0c49-034e-4c7f-a8a9-e650780e22aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152608068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2152608068
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3159770633
Short name T302
Test name
Test status
Simulation time 704750499 ps
CPU time 3.85 seconds
Started Jul 15 06:58:14 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 220576 kb
Host smart-c17d5b22-433b-485d-8e9b-bd49f1390a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159770633 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3159770633
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3297671522
Short name T1482
Test name
Test status
Simulation time 19214163541 ps
CPU time 46.46 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:59:03 PM PDT 24
Peak memory 764576 kb
Host smart-2e58e885-6fb8-4bdc-82b1-e0e2637b36d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297671522 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3297671522
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.817475542
Short name T745
Test name
Test status
Simulation time 515658504 ps
CPU time 2.95 seconds
Started Jul 15 06:58:22 PM PDT 24
Finished Jul 15 06:58:25 PM PDT 24
Peak memory 213924 kb
Host smart-bcc39bdb-332a-44e0-a7ba-801f8e0c3b53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817475542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_nack_acqfull.817475542
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.3024790104
Short name T1726
Test name
Test status
Simulation time 5054241203 ps
CPU time 2.94 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:24 PM PDT 24
Peak memory 205620 kb
Host smart-9c693695-ed50-4b35-b6c0-7f310f5f6df7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024790104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.3024790104
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_txstretch.3904215621
Short name T177
Test name
Test status
Simulation time 678911130 ps
CPU time 1.44 seconds
Started Jul 15 06:58:24 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 222348 kb
Host smart-e3d22473-fc0e-4587-be7b-a28a970c056d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904215621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_txstretch.3904215621
Directory /workspace/41.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/41.i2c_target_perf.4280602293
Short name T205
Test name
Test status
Simulation time 2518573060 ps
CPU time 5.28 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:58:22 PM PDT 24
Peak memory 213888 kb
Host smart-c527c110-afc6-4e18-a51c-da94e76adedc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280602293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.4280602293
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.3635397371
Short name T1234
Test name
Test status
Simulation time 2093254320 ps
CPU time 2.53 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:18 PM PDT 24
Peak memory 205368 kb
Host smart-8ed7b4cc-3898-4487-947c-44aae43d003a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635397371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.3635397371
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3081160967
Short name T628
Test name
Test status
Simulation time 5270451911 ps
CPU time 37.98 seconds
Started Jul 15 06:58:14 PM PDT 24
Finished Jul 15 06:58:53 PM PDT 24
Peak memory 213856 kb
Host smart-10fc1582-11ea-4197-a07d-b92b3493f0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081160967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3081160967
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.158332786
Short name T603
Test name
Test status
Simulation time 37405910110 ps
CPU time 45.07 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:59:01 PM PDT 24
Peak memory 246800 kb
Host smart-dac748cf-d946-4b70-b237-9caa109e3ab1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158332786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_stress_all.158332786
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1509006966
Short name T1727
Test name
Test status
Simulation time 407067544 ps
CPU time 8.6 seconds
Started Jul 15 06:58:18 PM PDT 24
Finished Jul 15 06:58:27 PM PDT 24
Peak memory 205644 kb
Host smart-97787b84-b16f-4741-9485-fd83357d4b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509006966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1509006966
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.4102852288
Short name T1360
Test name
Test status
Simulation time 7398312243 ps
CPU time 13.54 seconds
Started Jul 15 06:58:17 PM PDT 24
Finished Jul 15 06:58:31 PM PDT 24
Peak memory 205452 kb
Host smart-32ae9b42-3fbd-4d30-9ac0-b4556aa03e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102852288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.4102852288
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.626332516
Short name T740
Test name
Test status
Simulation time 1205481439 ps
CPU time 5.27 seconds
Started Jul 15 06:58:16 PM PDT 24
Finished Jul 15 06:58:22 PM PDT 24
Peak memory 254480 kb
Host smart-a21adeee-cee9-4472-ade6-32d0cfd9ac78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626332516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.626332516
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1970223086
Short name T1188
Test name
Test status
Simulation time 2646145948 ps
CPU time 7.09 seconds
Started Jul 15 06:58:15 PM PDT 24
Finished Jul 15 06:58:22 PM PDT 24
Peak memory 222060 kb
Host smart-9a9b1856-199c-4916-b03e-2826e172d37d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970223086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1970223086
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.2662834197
Short name T1152
Test name
Test status
Simulation time 106011053 ps
CPU time 2.33 seconds
Started Jul 15 06:58:14 PM PDT 24
Finished Jul 15 06:58:16 PM PDT 24
Peak memory 205612 kb
Host smart-5c35c15f-ff27-4b1c-ab37-2189b0b772ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662834197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.2662834197
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2477946983
Short name T821
Test name
Test status
Simulation time 14646993 ps
CPU time 0.66 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:58:31 PM PDT 24
Peak memory 204860 kb
Host smart-d8d9cb8c-8cb6-4570-a88e-e7480189152e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477946983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2477946983
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2287621430
Short name T417
Test name
Test status
Simulation time 321752486 ps
CPU time 1.52 seconds
Started Jul 15 06:58:24 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 213824 kb
Host smart-bd768aa8-1590-4bbc-aded-c9a1ada800a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287621430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2287621430
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.854932885
Short name T602
Test name
Test status
Simulation time 2318501044 ps
CPU time 16.18 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 241940 kb
Host smart-e5002e5e-e59a-430d-9d78-4d86cdcb7b5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854932885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.854932885
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3980025864
Short name T980
Test name
Test status
Simulation time 2761173153 ps
CPU time 83.12 seconds
Started Jul 15 06:58:22 PM PDT 24
Finished Jul 15 06:59:46 PM PDT 24
Peak memory 419432 kb
Host smart-50e835db-5bbe-4c37-bada-fed312d3e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980025864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3980025864
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2787527410
Short name T1096
Test name
Test status
Simulation time 10167727931 ps
CPU time 80.66 seconds
Started Jul 15 06:58:22 PM PDT 24
Finished Jul 15 06:59:44 PM PDT 24
Peak memory 811692 kb
Host smart-d955a63a-00a3-45aa-a2e8-6e2c6e9374fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787527410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2787527410
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1276777852
Short name T1626
Test name
Test status
Simulation time 72782417 ps
CPU time 0.91 seconds
Started Jul 15 06:58:25 PM PDT 24
Finished Jul 15 06:58:27 PM PDT 24
Peak memory 205300 kb
Host smart-2a13086d-e32c-4b44-b55a-878659087763
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276777852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1276777852
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3008796968
Short name T1127
Test name
Test status
Simulation time 536720081 ps
CPU time 3.43 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:25 PM PDT 24
Peak memory 205568 kb
Host smart-00bf88d3-d044-4cae-9431-271f3f234168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008796968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3008796968
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.736110776
Short name T1349
Test name
Test status
Simulation time 4490683315 ps
CPU time 126.72 seconds
Started Jul 15 06:58:24 PM PDT 24
Finished Jul 15 07:00:31 PM PDT 24
Peak memory 1153664 kb
Host smart-d511c3bc-6002-4a7a-9499-866bd74300b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736110776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.736110776
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3425202284
Short name T263
Test name
Test status
Simulation time 785336216 ps
CPU time 5.21 seconds
Started Jul 15 06:58:27 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 205544 kb
Host smart-fc1700b8-455f-4958-929b-ad7180961353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425202284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3425202284
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.1661439024
Short name T771
Test name
Test status
Simulation time 18381009 ps
CPU time 0.64 seconds
Started Jul 15 06:58:25 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 205200 kb
Host smart-35afa84c-9787-4468-8e0b-9b994602a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661439024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1661439024
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.911489053
Short name T523
Test name
Test status
Simulation time 29857352504 ps
CPU time 172.84 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 07:01:15 PM PDT 24
Peak memory 838000 kb
Host smart-a4774e43-397c-451e-9705-10481edd2eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911489053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.911489053
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.4187347322
Short name T612
Test name
Test status
Simulation time 24449125492 ps
CPU time 109.13 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 205476 kb
Host smart-5a84bd32-280d-48e2-ac92-0cd9b46bd3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187347322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.4187347322
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3577342449
Short name T854
Test name
Test status
Simulation time 29412071089 ps
CPU time 90.23 seconds
Started Jul 15 06:58:23 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 311204 kb
Host smart-12441343-82f7-4f73-ace8-bedb8a99ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577342449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3577342449
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2315791052
Short name T1431
Test name
Test status
Simulation time 795290530 ps
CPU time 6.79 seconds
Started Jul 15 06:58:23 PM PDT 24
Finished Jul 15 06:58:30 PM PDT 24
Peak memory 221356 kb
Host smart-4428e3ef-783c-4db5-ba93-3e3c3f2af800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315791052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2315791052
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2150634561
Short name T640
Test name
Test status
Simulation time 2702636145 ps
CPU time 5.01 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:58:35 PM PDT 24
Peak memory 213944 kb
Host smart-9a0972ef-6dbd-48e7-b4b1-36ced609dd18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150634561 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2150634561
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1964060583
Short name T1517
Test name
Test status
Simulation time 253685922 ps
CPU time 1.56 seconds
Started Jul 15 06:58:24 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 207240 kb
Host smart-cc241901-a544-429f-9a09-6fe3af4abbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964060583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1964060583
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3395884181
Short name T984
Test name
Test status
Simulation time 352582186 ps
CPU time 1.07 seconds
Started Jul 15 06:58:25 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 205484 kb
Host smart-baa4a132-eaf4-45ba-b9f6-d40865094697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395884181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3395884181
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1604682304
Short name T727
Test name
Test status
Simulation time 492447815 ps
CPU time 2.82 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 205624 kb
Host smart-25577b8c-09a2-4b33-8e21-e025c9f74503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604682304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1604682304
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3025150409
Short name T939
Test name
Test status
Simulation time 553676252 ps
CPU time 1.51 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:58:31 PM PDT 24
Peak memory 205448 kb
Host smart-e5900048-b36d-4f3a-9935-ad2979120537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025150409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3025150409
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.539618369
Short name T1628
Test name
Test status
Simulation time 196044388 ps
CPU time 1.59 seconds
Started Jul 15 06:58:33 PM PDT 24
Finished Jul 15 06:58:35 PM PDT 24
Peak memory 205696 kb
Host smart-f5c7499c-009b-487e-9331-07a76de87b61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539618369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.539618369
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2016284956
Short name T551
Test name
Test status
Simulation time 2078536907 ps
CPU time 5.59 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:27 PM PDT 24
Peak memory 220052 kb
Host smart-fa04be0d-7382-4a9e-b3f0-33bed2228bb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016284956 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2016284956
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.529018952
Short name T1137
Test name
Test status
Simulation time 24298712229 ps
CPU time 7.94 seconds
Started Jul 15 06:58:25 PM PDT 24
Finished Jul 15 06:58:33 PM PDT 24
Peak memory 317036 kb
Host smart-37e41a09-b340-4e22-83ea-1641658cd550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529018952 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.529018952
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.1184717777
Short name T867
Test name
Test status
Simulation time 1920738362 ps
CPU time 2.74 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 213872 kb
Host smart-447897d2-d806-40a7-ad02-0dd73a43521b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184717777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.1184717777
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.1319543851
Short name T1153
Test name
Test status
Simulation time 2186932612 ps
CPU time 2.49 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:58:32 PM PDT 24
Peak memory 205664 kb
Host smart-6bd3c3ff-2867-4520-893d-133ae53dd685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319543851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.1319543851
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.3462001958
Short name T1141
Test name
Test status
Simulation time 573470880 ps
CPU time 4.72 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:26 PM PDT 24
Peak memory 218100 kb
Host smart-768b6809-74c0-4fb5-bcda-c127413fda3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462001958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.3462001958
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.240260859
Short name T453
Test name
Test status
Simulation time 1663976435 ps
CPU time 2.37 seconds
Started Jul 15 06:58:26 PM PDT 24
Finished Jul 15 06:58:29 PM PDT 24
Peak memory 205492 kb
Host smart-32dcca9c-2bbf-4cae-a397-782c7d8fa176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240260859 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_smbus_maxlen.240260859
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3432702222
Short name T86
Test name
Test status
Simulation time 2263964922 ps
CPU time 35.1 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:59:04 PM PDT 24
Peak memory 213896 kb
Host smart-bf47778c-546b-42a4-a5b1-5ab0063d73c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432702222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3432702222
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.3869865638
Short name T519
Test name
Test status
Simulation time 43984293183 ps
CPU time 490.56 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 4188408 kb
Host smart-b2a7f3f5-4590-4918-ae7f-fd7c8374e99e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869865638 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.3869865638
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.768797605
Short name T1569
Test name
Test status
Simulation time 4503873915 ps
CPU time 46.7 seconds
Started Jul 15 06:58:27 PM PDT 24
Finished Jul 15 06:59:14 PM PDT 24
Peak memory 215784 kb
Host smart-6c5190f3-e87e-432a-8d7b-d1b89290ad8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768797605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.768797605
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3028635649
Short name T828
Test name
Test status
Simulation time 56252081634 ps
CPU time 1758.65 seconds
Started Jul 15 06:58:20 PM PDT 24
Finished Jul 15 07:27:40 PM PDT 24
Peak memory 8956100 kb
Host smart-3ded3da8-6f0d-4e93-bd73-d37ac221838a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028635649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3028635649
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3688923467
Short name T951
Test name
Test status
Simulation time 4166129097 ps
CPU time 77.12 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:59:46 PM PDT 24
Peak memory 1138500 kb
Host smart-91dd7f0b-bf6a-4adf-b01c-c920f74138f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688923467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3688923467
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3928074517
Short name T1430
Test name
Test status
Simulation time 5079594339 ps
CPU time 6.71 seconds
Started Jul 15 06:58:21 PM PDT 24
Finished Jul 15 06:58:28 PM PDT 24
Peak memory 230020 kb
Host smart-e551ae58-f115-4f58-926e-91a20839a6a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928074517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3928074517
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.1530762821
Short name T1095
Test name
Test status
Simulation time 178669495 ps
CPU time 3.64 seconds
Started Jul 15 06:58:34 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 205364 kb
Host smart-ae3243d9-1a70-4a1a-ac60-899ba727ede0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530762821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.1530762821
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2785109313
Short name T169
Test name
Test status
Simulation time 61965398 ps
CPU time 0.66 seconds
Started Jul 15 06:58:46 PM PDT 24
Finished Jul 15 06:58:47 PM PDT 24
Peak memory 204732 kb
Host smart-fd0de0f9-12b8-4e1b-bb7d-54666080c795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785109313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2785109313
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.399674355
Short name T496
Test name
Test status
Simulation time 739369386 ps
CPU time 3.75 seconds
Started Jul 15 06:58:33 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 213692 kb
Host smart-b14d6191-03bd-43b7-9259-c131a1dbef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399674355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.399674355
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2183980529
Short name T981
Test name
Test status
Simulation time 1186354116 ps
CPU time 15.81 seconds
Started Jul 15 06:58:34 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 268628 kb
Host smart-67ff3df6-7c84-4b87-8d56-fcd3011adbb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183980529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2183980529
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3615350310
Short name T29
Test name
Test status
Simulation time 35057824604 ps
CPU time 70.85 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:59:41 PM PDT 24
Peak memory 472084 kb
Host smart-440b9ac7-88b1-4673-86f0-94796c29dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615350310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3615350310
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3298943616
Short name T1613
Test name
Test status
Simulation time 2070985137 ps
CPU time 140.07 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 07:00:50 PM PDT 24
Peak memory 667432 kb
Host smart-961c1975-3267-4a28-8f7e-fe761768c108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298943616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3298943616
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3217034264
Short name T1301
Test name
Test status
Simulation time 81426801 ps
CPU time 0.93 seconds
Started Jul 15 06:58:33 PM PDT 24
Finished Jul 15 06:58:35 PM PDT 24
Peak memory 205236 kb
Host smart-e660c6b0-ceae-441a-8900-426225a102db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217034264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3217034264
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3229600014
Short name T1441
Test name
Test status
Simulation time 234472966 ps
CPU time 6.04 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:58:34 PM PDT 24
Peak memory 247664 kb
Host smart-9a4891e5-99a7-4f1a-9c3a-bef49e3eb5fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229600014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3229600014
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3415174261
Short name T1003
Test name
Test status
Simulation time 10321674200 ps
CPU time 73.13 seconds
Started Jul 15 06:58:28 PM PDT 24
Finished Jul 15 06:59:42 PM PDT 24
Peak memory 815024 kb
Host smart-4f380f56-e2e2-4019-96a3-c09c2475953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415174261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3415174261
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2845509935
Short name T264
Test name
Test status
Simulation time 531412870 ps
CPU time 8.52 seconds
Started Jul 15 06:58:34 PM PDT 24
Finished Jul 15 06:58:43 PM PDT 24
Peak memory 205440 kb
Host smart-a43f8c5f-1a69-43b9-817e-9268dfdcacbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845509935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2845509935
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.544868672
Short name T1034
Test name
Test status
Simulation time 96077707 ps
CPU time 0.69 seconds
Started Jul 15 06:58:33 PM PDT 24
Finished Jul 15 06:58:35 PM PDT 24
Peak memory 205260 kb
Host smart-79553601-ce5e-4e60-822e-860eca479871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544868672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.544868672
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2835929603
Short name T1162
Test name
Test status
Simulation time 49434153063 ps
CPU time 616.62 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 343624 kb
Host smart-d50d1834-08c5-4639-b34b-2978d85efacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835929603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2835929603
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1786714256
Short name T946
Test name
Test status
Simulation time 267798301 ps
CPU time 1.78 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:58:37 PM PDT 24
Peak memory 205712 kb
Host smart-57ef040d-c927-48c5-80fc-1b291228ae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786714256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1786714256
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3059165865
Short name T1067
Test name
Test status
Simulation time 3122042891 ps
CPU time 78.88 seconds
Started Jul 15 06:58:29 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 359220 kb
Host smart-6ee80489-dd64-40cc-a00d-4c82c17d8d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059165865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3059165865
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.324195173
Short name T1249
Test name
Test status
Simulation time 585942151 ps
CPU time 26.8 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:59:02 PM PDT 24
Peak memory 213704 kb
Host smart-c355bf98-6950-4485-98eb-8dfe2e2f6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324195173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.324195173
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.916128844
Short name T1246
Test name
Test status
Simulation time 3614624575 ps
CPU time 4.6 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:58:40 PM PDT 24
Peak memory 220036 kb
Host smart-1ad70ea7-b684-4352-b4bc-8a41898be1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916128844 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.916128844
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3710215640
Short name T1260
Test name
Test status
Simulation time 242927715 ps
CPU time 0.86 seconds
Started Jul 15 06:58:37 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 205424 kb
Host smart-05346ac6-be5c-440c-8380-c37c683b6434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710215640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3710215640
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.645959086
Short name T53
Test name
Test status
Simulation time 562938193 ps
CPU time 1.17 seconds
Started Jul 15 06:58:32 PM PDT 24
Finished Jul 15 06:58:34 PM PDT 24
Peak memory 205452 kb
Host smart-3eab4906-8491-4d5c-a6b6-0a018552fa95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645959086 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.645959086
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.603798039
Short name T1516
Test name
Test status
Simulation time 861614656 ps
CPU time 2.3 seconds
Started Jul 15 06:58:36 PM PDT 24
Finished Jul 15 06:58:39 PM PDT 24
Peak memory 205648 kb
Host smart-b2fce819-0c26-44fe-a117-155fa658eb4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603798039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.603798039
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.3298826721
Short name T1730
Test name
Test status
Simulation time 292132541 ps
CPU time 1.33 seconds
Started Jul 15 06:58:38 PM PDT 24
Finished Jul 15 06:58:40 PM PDT 24
Peak memory 205476 kb
Host smart-b8a27ae0-da6f-4aba-ad56-847f142ff57b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298826721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.3298826721
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1676088374
Short name T720
Test name
Test status
Simulation time 2695724657 ps
CPU time 4.33 seconds
Started Jul 15 06:58:34 PM PDT 24
Finished Jul 15 06:58:39 PM PDT 24
Peak memory 213884 kb
Host smart-d437ceea-7a95-453e-8923-cf71ac4d3f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676088374 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1676088374
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1878714128
Short name T1216
Test name
Test status
Simulation time 8436686622 ps
CPU time 26.31 seconds
Started Jul 15 06:58:36 PM PDT 24
Finished Jul 15 06:59:03 PM PDT 24
Peak memory 808188 kb
Host smart-4f58b65c-7b21-465c-92f0-e796a4c52095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878714128 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1878714128
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.2885618556
Short name T166
Test name
Test status
Simulation time 566852284 ps
CPU time 3.07 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:46 PM PDT 24
Peak memory 213896 kb
Host smart-fb1e06f1-831f-4463-b577-dcada9e62a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885618556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.2885618556
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.2661770200
Short name T1053
Test name
Test status
Simulation time 1907144976 ps
CPU time 2.39 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:45 PM PDT 24
Peak memory 205652 kb
Host smart-f3a1ae84-fdcc-458a-b92f-4a659f9778a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661770200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.2661770200
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.2495758989
Short name T897
Test name
Test status
Simulation time 147894516 ps
CPU time 1.39 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 06:58:46 PM PDT 24
Peak memory 222248 kb
Host smart-51aa0889-272b-49ba-a8eb-1324b0ad0a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495758989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_nack_txstretch.2495758989
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.1306232264
Short name T974
Test name
Test status
Simulation time 436179147 ps
CPU time 3.08 seconds
Started Jul 15 06:58:37 PM PDT 24
Finished Jul 15 06:58:41 PM PDT 24
Peak memory 213876 kb
Host smart-90cc203b-d769-4c69-911c-4717b6cfb6bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306232264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.1306232264
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.1698064616
Short name T814
Test name
Test status
Simulation time 435055032 ps
CPU time 2.04 seconds
Started Jul 15 06:58:41 PM PDT 24
Finished Jul 15 06:58:44 PM PDT 24
Peak memory 205436 kb
Host smart-aefad7ff-5466-4328-8d4e-6668997882cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698064616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.1698064616
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.925322071
Short name T1572
Test name
Test status
Simulation time 912300351 ps
CPU time 31.08 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 213816 kb
Host smart-b71cea25-16e8-45a6-8798-1d2558bbd7fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925322071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.925322071
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.412565783
Short name T1209
Test name
Test status
Simulation time 24605609997 ps
CPU time 460.32 seconds
Started Jul 15 06:58:37 PM PDT 24
Finished Jul 15 07:06:18 PM PDT 24
Peak memory 2960576 kb
Host smart-8ccf014e-0ef9-47a1-8376-331dbc97492f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412565783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.412565783
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2754056447
Short name T269
Test name
Test status
Simulation time 5051777886 ps
CPU time 54.2 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:59:30 PM PDT 24
Peak memory 215172 kb
Host smart-b6c650f0-e812-4b18-abda-e34172561454
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754056447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2754056447
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2360184725
Short name T167
Test name
Test status
Simulation time 13596140633 ps
CPU time 14.5 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 205684 kb
Host smart-63ee56f9-cff6-4dd1-85fa-ea8bfbceff27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360184725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2360184725
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.793522712
Short name T1614
Test name
Test status
Simulation time 1953892657 ps
CPU time 2.24 seconds
Started Jul 15 06:58:37 PM PDT 24
Finished Jul 15 06:58:40 PM PDT 24
Peak memory 220560 kb
Host smart-c3a89bdb-fbf8-42d8-8226-b80102cca7a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793522712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.793522712
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3624868092
Short name T1416
Test name
Test status
Simulation time 4156884944 ps
CPU time 6.3 seconds
Started Jul 15 06:58:35 PM PDT 24
Finished Jul 15 06:58:42 PM PDT 24
Peak memory 222060 kb
Host smart-36ee5e14-3e16-4e4a-b8a4-8ebd3fbad090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624868092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3624868092
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.1001940741
Short name T1484
Test name
Test status
Simulation time 514256282 ps
CPU time 6.85 seconds
Started Jul 15 06:58:37 PM PDT 24
Finished Jul 15 06:58:45 PM PDT 24
Peak memory 205632 kb
Host smart-e712a4e8-0bf5-43d4-9011-775e5c2349c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001940741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.1001940741
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3767212171
Short name T1598
Test name
Test status
Simulation time 16793591 ps
CPU time 0.65 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 204760 kb
Host smart-7d7c2476-87f6-491a-8ece-66c893afcaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767212171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3767212171
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.99252221
Short name T1631
Test name
Test status
Simulation time 320195492 ps
CPU time 1.62 seconds
Started Jul 15 06:58:41 PM PDT 24
Finished Jul 15 06:58:43 PM PDT 24
Peak memory 213816 kb
Host smart-7ce34b42-b86f-4436-b77e-96791310a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99252221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.99252221
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1140359467
Short name T1426
Test name
Test status
Simulation time 499647871 ps
CPU time 19.37 seconds
Started Jul 15 06:58:46 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 286492 kb
Host smart-aeb0788a-8105-40a1-81e2-4ef146addb7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140359467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1140359467
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2650462204
Short name T558
Test name
Test status
Simulation time 5786415948 ps
CPU time 160.02 seconds
Started Jul 15 06:58:47 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 440944 kb
Host smart-ea34ef72-be8e-48cd-90f3-4175010ed4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650462204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2650462204
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1008543155
Short name T1192
Test name
Test status
Simulation time 9215616140 ps
CPU time 67.17 seconds
Started Jul 15 06:58:43 PM PDT 24
Finished Jul 15 06:59:51 PM PDT 24
Peak memory 678740 kb
Host smart-255c8d16-ce70-4176-9ef8-ab529b419df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008543155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1008543155
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1854476795
Short name T395
Test name
Test status
Simulation time 152584596 ps
CPU time 1.03 seconds
Started Jul 15 06:58:45 PM PDT 24
Finished Jul 15 06:58:46 PM PDT 24
Peak memory 205252 kb
Host smart-1aadc2d8-c2cc-48b5-821f-59a8f86f030a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854476795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1854476795
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2336910502
Short name T446
Test name
Test status
Simulation time 250937778 ps
CPU time 5.92 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:49 PM PDT 24
Peak memory 205520 kb
Host smart-a68a50ae-f4dc-4f39-bc9b-a5493588e098
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336910502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2336910502
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3852389372
Short name T423
Test name
Test status
Simulation time 4886476204 ps
CPU time 372.18 seconds
Started Jul 15 06:58:41 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 1377880 kb
Host smart-e2e0541f-6b26-4468-838d-f020a15ba71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852389372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3852389372
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3460318356
Short name T1644
Test name
Test status
Simulation time 2161374519 ps
CPU time 8.84 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:11 PM PDT 24
Peak memory 205556 kb
Host smart-7f1a518d-d1ae-4774-9b26-e0301fd0ebae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460318356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3460318356
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.510801919
Short name T1640
Test name
Test status
Simulation time 158618550 ps
CPU time 2.31 seconds
Started Jul 15 06:58:57 PM PDT 24
Finished Jul 15 06:58:59 PM PDT 24
Peak memory 213660 kb
Host smart-b3c261e9-8129-43e6-8a1c-0ffa5331d705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510801919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.510801919
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2825621467
Short name T680
Test name
Test status
Simulation time 27323701 ps
CPU time 0.72 seconds
Started Jul 15 06:58:43 PM PDT 24
Finished Jul 15 06:58:45 PM PDT 24
Peak memory 205276 kb
Host smart-a5312ddd-c7cf-43bc-a522-1824e38d011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825621467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2825621467
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3126676604
Short name T1375
Test name
Test status
Simulation time 1475401878 ps
CPU time 4.44 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:47 PM PDT 24
Peak memory 221776 kb
Host smart-a32ba553-03aa-4a3c-8a70-d440eadb27d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126676604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3126676604
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1586751465
Short name T1623
Test name
Test status
Simulation time 3013020074 ps
CPU time 8.96 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:51 PM PDT 24
Peak memory 205484 kb
Host smart-09268176-5166-4eea-945b-25d37f8d9f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586751465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1586751465
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1432248149
Short name T1395
Test name
Test status
Simulation time 1332305996 ps
CPU time 18.21 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 06:59:03 PM PDT 24
Peak memory 286600 kb
Host smart-66659184-3258-4345-a8f6-604d33edd94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432248149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1432248149
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2049412787
Short name T491
Test name
Test status
Simulation time 816693387 ps
CPU time 14.5 seconds
Started Jul 15 06:58:39 PM PDT 24
Finished Jul 15 06:58:54 PM PDT 24
Peak memory 221172 kb
Host smart-c0d96c5a-c092-4547-bdee-96db350dc892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049412787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2049412787
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3993572752
Short name T641
Test name
Test status
Simulation time 897452544 ps
CPU time 4.71 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 209736 kb
Host smart-bd44171d-5d48-456f-8914-42951ae1a581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993572752 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3993572752
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.158777203
Short name T1211
Test name
Test status
Simulation time 238804428 ps
CPU time 1.73 seconds
Started Jul 15 06:58:52 PM PDT 24
Finished Jul 15 06:58:54 PM PDT 24
Peak memory 205624 kb
Host smart-9875cc72-db1f-4e58-bed8-d5a2012fbed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158777203 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.158777203
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3728731690
Short name T1115
Test name
Test status
Simulation time 375093865 ps
CPU time 1.57 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 205640 kb
Host smart-cb2ae634-7f0a-4ec9-b2c6-4aed6fac35d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728731690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3728731690
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.1722798764
Short name T773
Test name
Test status
Simulation time 705429739 ps
CPU time 3.26 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 205648 kb
Host smart-3f1cc0a1-7306-4b67-af95-62e930963a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722798764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.1722798764
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.2047437381
Short name T847
Test name
Test status
Simulation time 136370500 ps
CPU time 1.22 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 205444 kb
Host smart-581710a8-d4b0-4bf6-8b30-9cf1fa53c24e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047437381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2047437381
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3153681252
Short name T944
Test name
Test status
Simulation time 1804173874 ps
CPU time 1.93 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:04 PM PDT 24
Peak memory 213824 kb
Host smart-15a75aa9-b988-497c-aab2-d39e1f7fb54c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153681252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3153681252
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.96971203
Short name T767
Test name
Test status
Simulation time 3664526669 ps
CPU time 4.76 seconds
Started Jul 15 06:58:47 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 222032 kb
Host smart-1aad75d0-766d-471b-b4b4-27d8b36cd1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96971203 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.96971203
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.4180066683
Short name T959
Test name
Test status
Simulation time 1002164530 ps
CPU time 1.72 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 06:58:46 PM PDT 24
Peak memory 205636 kb
Host smart-5fdd568d-da9a-4602-9c44-8a77f3a64f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180066683 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.4180066683
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.3121498548
Short name T1323
Test name
Test status
Simulation time 2502386679 ps
CPU time 3.15 seconds
Started Jul 15 06:58:54 PM PDT 24
Finished Jul 15 06:58:57 PM PDT 24
Peak memory 213884 kb
Host smart-efe874ea-0f15-4e05-82da-665fe90561e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121498548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.3121498548
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.480768898
Short name T164
Test name
Test status
Simulation time 875119933 ps
CPU time 2.19 seconds
Started Jul 15 06:58:49 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 205656 kb
Host smart-2aba3856-4835-4e28-a454-b337ec8e02c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480768898 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.480768898
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.4198732942
Short name T1604
Test name
Test status
Simulation time 1406802196 ps
CPU time 5.04 seconds
Started Jul 15 06:58:54 PM PDT 24
Finished Jul 15 06:58:59 PM PDT 24
Peak memory 214764 kb
Host smart-22114dca-6fde-4ab1-8b13-98bd3e06384c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198732942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.4198732942
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.2816130909
Short name T1676
Test name
Test status
Simulation time 2230470615 ps
CPU time 2.38 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:54 PM PDT 24
Peak memory 205484 kb
Host smart-65c2b870-f381-4f97-84fa-c0033c129ab3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816130909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.2816130909
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.948638883
Short name T788
Test name
Test status
Simulation time 43169304154 ps
CPU time 107.68 seconds
Started Jul 15 06:58:51 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 829492 kb
Host smart-20645045-c5d1-4979-ba53-105fc92c5c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948638883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.948638883
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1221928608
Short name T1541
Test name
Test status
Simulation time 1798476324 ps
CPU time 31.51 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:59:14 PM PDT 24
Peak memory 232684 kb
Host smart-a37d4392-a0d5-4fee-a46b-ae1fe079eb88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221928608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1221928608
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.497824500
Short name T1708
Test name
Test status
Simulation time 66690453708 ps
CPU time 324.32 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 07:04:09 PM PDT 24
Peak memory 2966844 kb
Host smart-1330054a-2ca1-4196-b3dc-f26e92032633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497824500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.497824500
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1382952063
Short name T1125
Test name
Test status
Simulation time 2040362489 ps
CPU time 5.75 seconds
Started Jul 15 06:58:44 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 260652 kb
Host smart-2a691542-acd2-415f-ba88-a2ddd6a38b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382952063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1382952063
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1234724676
Short name T705
Test name
Test status
Simulation time 5848803375 ps
CPU time 7.78 seconds
Started Jul 15 06:58:42 PM PDT 24
Finished Jul 15 06:58:51 PM PDT 24
Peak memory 230220 kb
Host smart-74352ec9-4bdc-4750-84db-e7b04d5b6964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234724676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1234724676
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3444723717
Short name T1491
Test name
Test status
Simulation time 502185278 ps
CPU time 6.72 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:07 PM PDT 24
Peak memory 205616 kb
Host smart-6d8b82b4-0f07-47df-b9f6-0a09ad5c02fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444723717 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3444723717
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3633048489
Short name T692
Test name
Test status
Simulation time 50807024 ps
CPU time 0.65 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:00 PM PDT 24
Peak memory 204596 kb
Host smart-d7998c64-3932-4b1f-920a-8e06651f4462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633048489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3633048489
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2973387445
Short name T642
Test name
Test status
Simulation time 124091998 ps
CPU time 4.44 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:55 PM PDT 24
Peak memory 213808 kb
Host smart-35e415b3-c5f2-4cfe-9855-94b78e1b8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973387445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2973387445
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1465229578
Short name T1279
Test name
Test status
Simulation time 1283502227 ps
CPU time 7.08 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 273540 kb
Host smart-14397999-5790-4e03-8abc-e374acf0c3bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465229578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1465229578
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3491336847
Short name T1147
Test name
Test status
Simulation time 8443524109 ps
CPU time 43.74 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:59:35 PM PDT 24
Peak memory 245532 kb
Host smart-d73bb061-1daa-451d-9d4d-02ed4095686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491336847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3491336847
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3750055653
Short name T49
Test name
Test status
Simulation time 2451656065 ps
CPU time 197.88 seconds
Started Jul 15 06:58:57 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 815200 kb
Host smart-b8799cdd-ccce-430b-bd06-497c67459cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750055653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3750055653
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.655381526
Short name T449
Test name
Test status
Simulation time 355981174 ps
CPU time 1.13 seconds
Started Jul 15 06:58:48 PM PDT 24
Finished Jul 15 06:58:50 PM PDT 24
Peak memory 205180 kb
Host smart-94160a8e-a6b0-4d8f-b57f-ca594fb4f4cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655381526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.655381526
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.367244401
Short name T1683
Test name
Test status
Simulation time 235208323 ps
CPU time 5.84 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 248392 kb
Host smart-ba26b06b-1fe0-4948-b362-265ecceab1a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367244401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
367244401
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.119252472
Short name T1405
Test name
Test status
Simulation time 4783201180 ps
CPU time 271.4 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 07:03:33 PM PDT 24
Peak memory 1122948 kb
Host smart-8a5065df-ec53-4415-be09-cdde165ab87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119252472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.119252472
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.4035449268
Short name T1015
Test name
Test status
Simulation time 284714266 ps
CPU time 2.41 seconds
Started Jul 15 06:58:57 PM PDT 24
Finished Jul 15 06:59:00 PM PDT 24
Peak memory 205528 kb
Host smart-92eb04ac-b169-4a88-b62d-40fd95a03654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035449268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.4035449268
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.541033366
Short name T1707
Test name
Test status
Simulation time 31030073 ps
CPU time 0.67 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:52 PM PDT 24
Peak memory 205244 kb
Host smart-c65eeec3-0f2e-41c6-99c8-bfbef499ad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541033366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.541033366
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.3758527498
Short name T694
Test name
Test status
Simulation time 2533814269 ps
CPU time 14.95 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:15 PM PDT 24
Peak memory 358444 kb
Host smart-076ec064-4ab5-41d7-89c9-1187dde65167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758527498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.3758527498
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1631000747
Short name T156
Test name
Test status
Simulation time 1205056453 ps
CPU time 22.48 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:23 PM PDT 24
Peak memory 349120 kb
Host smart-a63a523b-381e-4bf2-abbd-ef8b533aa8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631000747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1631000747
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.891250752
Short name T1187
Test name
Test status
Simulation time 524806134 ps
CPU time 24.94 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 213704 kb
Host smart-9de8daa1-8554-4684-8946-1c57c6c904f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891250752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.891250752
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2334813114
Short name T366
Test name
Test status
Simulation time 5306198204 ps
CPU time 7.51 seconds
Started Jul 15 06:59:01 PM PDT 24
Finished Jul 15 06:59:10 PM PDT 24
Peak memory 212680 kb
Host smart-f0029d22-7cb1-406c-af72-45f2dba1ff03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334813114 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2334813114
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1518547875
Short name T387
Test name
Test status
Simulation time 485420990 ps
CPU time 1.17 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:58:53 PM PDT 24
Peak memory 205476 kb
Host smart-b2d69b65-8c7d-4b71-8a5a-a567022007f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518547875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1518547875
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1476183084
Short name T1317
Test name
Test status
Simulation time 264564321 ps
CPU time 1.25 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:02 PM PDT 24
Peak memory 213868 kb
Host smart-9e0fddfb-f09d-48a3-a3f1-47a55dc96127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476183084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1476183084
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.313388195
Short name T171
Test name
Test status
Simulation time 563017917 ps
CPU time 3.4 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:02 PM PDT 24
Peak memory 205652 kb
Host smart-254363a9-161d-4efc-ad73-fd985b40d12f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313388195 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.313388195
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.2752381887
Short name T958
Test name
Test status
Simulation time 726693468 ps
CPU time 1.19 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:00 PM PDT 24
Peak memory 205460 kb
Host smart-f899e2b8-49b6-4b38-9596-8821ec25e5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752381887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.2752381887
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1482203523
Short name T494
Test name
Test status
Simulation time 2858778539 ps
CPU time 4.82 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:04 PM PDT 24
Peak memory 217500 kb
Host smart-88cb4fd9-7707-4b78-9ae0-10cd69879e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482203523 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1482203523
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2851916253
Short name T188
Test name
Test status
Simulation time 7427073088 ps
CPU time 6.09 seconds
Started Jul 15 06:58:51 PM PDT 24
Finished Jul 15 06:58:58 PM PDT 24
Peak memory 205644 kb
Host smart-01d90f47-356f-44e7-8364-605420712af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851916253 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2851916253
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.591745965
Short name T1449
Test name
Test status
Simulation time 485525018 ps
CPU time 2.79 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:04 PM PDT 24
Peak memory 213876 kb
Host smart-fe21edd4-db9e-4dfb-8fe7-2ff161e74fd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591745965 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_nack_acqfull.591745965
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.819783565
Short name T1122
Test name
Test status
Simulation time 1961734992 ps
CPU time 2.64 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 205608 kb
Host smart-a4906586-2d25-401c-a3f1-53588140cef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819783565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.819783565
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_txstretch.4206857163
Short name T1114
Test name
Test status
Simulation time 139432313 ps
CPU time 1.38 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:07 PM PDT 24
Peak memory 222340 kb
Host smart-47361bc1-f472-4cc1-bf1c-9421ef3434ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206857163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_nack_txstretch.4206857163
Directory /workspace/45.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/45.i2c_target_perf.2983180099
Short name T329
Test name
Test status
Simulation time 6267633706 ps
CPU time 4.89 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 221952 kb
Host smart-930038a2-591a-406a-a4ff-291dca7570e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983180099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.2983180099
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.3839517221
Short name T1239
Test name
Test status
Simulation time 1678761482 ps
CPU time 2.31 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:02 PM PDT 24
Peak memory 205440 kb
Host smart-d6338a43-0145-41ec-be7a-a5f83811588d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839517221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.3839517221
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1309773034
Short name T1087
Test name
Test status
Simulation time 825722101 ps
CPU time 11.69 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:59:03 PM PDT 24
Peak memory 213788 kb
Host smart-42ca9b07-168b-4c06-90e4-dd978ec670c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309773034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1309773034
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.3642805876
Short name T1263
Test name
Test status
Simulation time 29162938069 ps
CPU time 214.76 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 1839008 kb
Host smart-8c04e65c-7fce-4c69-a7bc-d5e5184ef324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642805876 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.3642805876
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3225120630
Short name T1485
Test name
Test status
Simulation time 3287064176 ps
CPU time 16.24 seconds
Started Jul 15 06:58:48 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 221900 kb
Host smart-2e2351fe-0c63-40b9-bde6-8ae39f73fa05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225120630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3225120630
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1786247480
Short name T455
Test name
Test status
Simulation time 68346460380 ps
CPU time 1102.81 seconds
Started Jul 15 06:59:01 PM PDT 24
Finished Jul 15 07:17:25 PM PDT 24
Peak memory 6289160 kb
Host smart-d116b7ff-f8b2-485d-827e-2da8c87d9e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786247480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1786247480
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.533177358
Short name T1400
Test name
Test status
Simulation time 4432855328 ps
CPU time 9.76 seconds
Started Jul 15 06:58:50 PM PDT 24
Finished Jul 15 06:59:01 PM PDT 24
Peak memory 342060 kb
Host smart-0d2f1547-46be-4974-8452-671e10e9afcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533177358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_t
arget_stretch.533177358
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3082767255
Short name T912
Test name
Test status
Simulation time 1372999301 ps
CPU time 7.38 seconds
Started Jul 15 06:58:48 PM PDT 24
Finished Jul 15 06:58:56 PM PDT 24
Peak memory 218268 kb
Host smart-9086329f-8f11-4ec0-9c93-a1b3b89f9b9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082767255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3082767255
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.4125039201
Short name T1035
Test name
Test status
Simulation time 90105071 ps
CPU time 2.06 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 205592 kb
Host smart-4eec9840-298a-4653-9698-258885aa913f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125039201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.4125039201
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2781457835
Short name T806
Test name
Test status
Simulation time 15295232 ps
CPU time 0.65 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 204784 kb
Host smart-d23de513-7419-4e5c-9d95-2a33421b4cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781457835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2781457835
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2370353295
Short name T1391
Test name
Test status
Simulation time 848132010 ps
CPU time 2.95 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 224920 kb
Host smart-4c4dbeb3-654a-4244-8109-4432d3b8c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370353295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2370353295
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.34733932
Short name T700
Test name
Test status
Simulation time 357083850 ps
CPU time 17.89 seconds
Started Jul 15 06:59:05 PM PDT 24
Finished Jul 15 06:59:24 PM PDT 24
Peak memory 279476 kb
Host smart-a14c7c06-77d2-4e86-8313-9eb1aa41c15c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34733932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty
.34733932
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1928934453
Short name T991
Test name
Test status
Simulation time 2431997614 ps
CPU time 64.32 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 07:00:04 PM PDT 24
Peak memory 352088 kb
Host smart-c187544b-8e20-4a66-8eb7-f714c15ac5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928934453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1928934453
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1777980875
Short name T1273
Test name
Test status
Simulation time 1449391110 ps
CPU time 97.4 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 530276 kb
Host smart-e38dfddc-ccdf-48bf-bb02-97b9a68e7009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777980875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1777980875
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1976906781
Short name T723
Test name
Test status
Simulation time 413088827 ps
CPU time 1.28 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:03 PM PDT 24
Peak memory 205432 kb
Host smart-6262a9cf-0117-4bea-b565-5f15931b0e6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976906781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1976906781
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1030555663
Short name T1020
Test name
Test status
Simulation time 150001279 ps
CPU time 8.91 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:11 PM PDT 24
Peak memory 232392 kb
Host smart-03bf51af-f9ce-487b-b793-fbcb9ad7ed45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030555663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1030555663
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3352646171
Short name T1451
Test name
Test status
Simulation time 9921216580 ps
CPU time 377.03 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 07:05:16 PM PDT 24
Peak memory 1446072 kb
Host smart-93a8737b-1e98-4369-9dee-19ff72e92f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352646171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3352646171
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1251091747
Short name T997
Test name
Test status
Simulation time 1511917597 ps
CPU time 5.69 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:11 PM PDT 24
Peak memory 205456 kb
Host smart-ac902c87-9296-4baa-bf51-1578cf4c71c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251091747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1251091747
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.3479024066
Short name T439
Test name
Test status
Simulation time 185610516 ps
CPU time 0.71 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:04 PM PDT 24
Peak memory 205140 kb
Host smart-a3f569cd-56dc-4702-91cc-feab21d5596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479024066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3479024066
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3016049409
Short name T343
Test name
Test status
Simulation time 2219866228 ps
CPU time 3.19 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:07 PM PDT 24
Peak memory 228472 kb
Host smart-81c33bb3-14ba-4f5b-89ca-7602aa9b7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016049409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3016049409
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.1610051739
Short name T1472
Test name
Test status
Simulation time 1514866412 ps
CPU time 5.53 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 205472 kb
Host smart-35402b25-5b58-4674-8233-56d26383e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610051739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1610051739
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.468658131
Short name T1345
Test name
Test status
Simulation time 1413644287 ps
CPU time 25.52 seconds
Started Jul 15 06:58:59 PM PDT 24
Finished Jul 15 06:59:25 PM PDT 24
Peak memory 294640 kb
Host smart-ccebe01e-8dc7-44e3-a407-1cfa55155f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468658131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.468658131
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1863342008
Short name T367
Test name
Test status
Simulation time 695507205 ps
CPU time 11.23 seconds
Started Jul 15 06:58:58 PM PDT 24
Finished Jul 15 06:59:10 PM PDT 24
Peak memory 217572 kb
Host smart-f11ddd9b-95f2-4452-a085-2674a4146235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863342008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1863342008
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3046337811
Short name T594
Test name
Test status
Simulation time 898447131 ps
CPU time 4.86 seconds
Started Jul 15 06:59:05 PM PDT 24
Finished Jul 15 06:59:11 PM PDT 24
Peak memory 215184 kb
Host smart-992c71d3-d05a-4cb1-8450-aef637e48036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046337811 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3046337811
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.922607689
Short name T619
Test name
Test status
Simulation time 284946318 ps
CPU time 1.82 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 06:59:09 PM PDT 24
Peak memory 205644 kb
Host smart-337f23a9-9d7f-41d9-acef-653ddb67b052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922607689 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.922607689
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.433690208
Short name T581
Test name
Test status
Simulation time 500669786 ps
CPU time 1.18 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:07 PM PDT 24
Peak memory 205688 kb
Host smart-6b4d6967-c6f2-4e18-9cdf-138919a1ec36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433690208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.433690208
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1720565554
Short name T820
Test name
Test status
Simulation time 460220732 ps
CPU time 2.41 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 205672 kb
Host smart-85db9091-d600-4808-91ba-18a3de5af362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720565554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1720565554
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.3911676984
Short name T468
Test name
Test status
Simulation time 478645322 ps
CPU time 1.19 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 205468 kb
Host smart-93879a6c-d6a2-463c-813b-c9e0d06a39e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911676984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.3911676984
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3560575733
Short name T941
Test name
Test status
Simulation time 338604843 ps
CPU time 2.23 seconds
Started Jul 15 06:59:02 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 216908 kb
Host smart-3111dc5a-eeb1-4976-8ed5-75694f52697b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560575733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3560575733
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.663427630
Short name T516
Test name
Test status
Simulation time 1522635087 ps
CPU time 5.97 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 222060 kb
Host smart-1cfc5782-7606-4554-be1e-efa8572adfaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663427630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.663427630
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3655348326
Short name T357
Test name
Test status
Simulation time 8894593119 ps
CPU time 11.17 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:15 PM PDT 24
Peak memory 438656 kb
Host smart-cb5d525f-725f-4ee1-9053-1d876448a905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655348326 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3655348326
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.3772907621
Short name T425
Test name
Test status
Simulation time 2065189062 ps
CPU time 2.9 seconds
Started Jul 15 06:59:07 PM PDT 24
Finished Jul 15 06:59:10 PM PDT 24
Peak memory 213860 kb
Host smart-7796f94e-59cd-4b5a-9605-382e9be850d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772907621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.3772907621
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1254181916
Short name T845
Test name
Test status
Simulation time 2031586981 ps
CPU time 2.58 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 205640 kb
Host smart-f8617a19-4380-4df1-b2b9-6167085aa3d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254181916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1254181916
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.37888159
Short name T141
Test name
Test status
Simulation time 1088350732 ps
CPU time 1.58 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:06 PM PDT 24
Peak memory 222324 kb
Host smart-4dc3f66d-c69b-4edc-b990-491fc124b421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37888159 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_txstretch.37888159
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.2238244649
Short name T650
Test name
Test status
Simulation time 411578749 ps
CPU time 3.11 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 213836 kb
Host smart-887544e9-bdb0-4a76-a993-b38e6b86b754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238244649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.2238244649
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.2453790219
Short name T1005
Test name
Test status
Simulation time 485828992 ps
CPU time 2.28 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 06:59:10 PM PDT 24
Peak memory 204936 kb
Host smart-065a1724-523a-4758-b3ae-a73f185c7ced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453790219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.2453790219
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2812571954
Short name T823
Test name
Test status
Simulation time 5257425753 ps
CPU time 19.39 seconds
Started Jul 15 06:59:01 PM PDT 24
Finished Jul 15 06:59:22 PM PDT 24
Peak memory 213864 kb
Host smart-20d3cdcd-56cd-43ee-a062-f18f75339d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812571954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2812571954
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.3433384709
Short name T917
Test name
Test status
Simulation time 37465482694 ps
CPU time 64.46 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 301176 kb
Host smart-a7980d2b-4e21-4425-8759-dcf8bd533e8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433384709 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.3433384709
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1264838270
Short name T1105
Test name
Test status
Simulation time 4108650143 ps
CPU time 21.19 seconds
Started Jul 15 06:59:05 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 230120 kb
Host smart-d8de9342-fa8d-4687-9861-c388d2feddce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264838270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1264838270
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1002253540
Short name T1486
Test name
Test status
Simulation time 40807444533 ps
CPU time 316.53 seconds
Started Jul 15 06:58:57 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 3385352 kb
Host smart-432fae05-e25f-44dc-9830-079d0d2a9daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002253540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1002253540
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.544754304
Short name T335
Test name
Test status
Simulation time 2168432494 ps
CPU time 11.48 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 303984 kb
Host smart-0485e4db-447d-4e4f-b98c-3b2163662090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544754304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.544754304
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1700029429
Short name T1444
Test name
Test status
Simulation time 2541786432 ps
CPU time 7.23 seconds
Started Jul 15 06:59:00 PM PDT 24
Finished Jul 15 06:59:09 PM PDT 24
Peak memory 222012 kb
Host smart-f1d3bb95-d918-41c5-82c3-1ca8737c10c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700029429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1700029429
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.693313547
Short name T945
Test name
Test status
Simulation time 62198586 ps
CPU time 1.47 seconds
Started Jul 15 06:59:05 PM PDT 24
Finished Jul 15 06:59:07 PM PDT 24
Peak memory 205588 kb
Host smart-5b246cb7-ccd5-4632-b899-c9e43ea55dbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693313547 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.693313547
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1153227680
Short name T372
Test name
Test status
Simulation time 15317460 ps
CPU time 0.64 seconds
Started Jul 15 06:59:22 PM PDT 24
Finished Jul 15 06:59:23 PM PDT 24
Peak memory 204700 kb
Host smart-22ea0597-5279-4092-bb5d-d47e93dd60d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153227680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1153227680
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.4244516451
Short name T1605
Test name
Test status
Simulation time 1003600924 ps
CPU time 1.17 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 213840 kb
Host smart-f5981d16-db5a-47c0-838b-9f814ca8f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244516451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.4244516451
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.833467436
Short name T899
Test name
Test status
Simulation time 736580780 ps
CPU time 40.14 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 356036 kb
Host smart-2424d522-a1c0-4b0c-8031-eec4e10ea872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833467436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.833467436
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1783421338
Short name T408
Test name
Test status
Simulation time 13057871222 ps
CPU time 226.53 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 698996 kb
Host smart-c374d88e-2f79-4d37-989c-1f73ffb2e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783421338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1783421338
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3215484000
Short name T563
Test name
Test status
Simulation time 1641000188 ps
CPU time 49.77 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:54 PM PDT 24
Peak memory 614232 kb
Host smart-1bff6314-e1a8-472c-b916-70fd3abc4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215484000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3215484000
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2218719682
Short name T1090
Test name
Test status
Simulation time 107189961 ps
CPU time 1.1 seconds
Started Jul 15 06:59:06 PM PDT 24
Finished Jul 15 06:59:08 PM PDT 24
Peak memory 205288 kb
Host smart-8ab93a93-89f4-4ca0-a1fa-1db7b8009457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218719682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2218719682
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3901091946
Short name T1723
Test name
Test status
Simulation time 884495281 ps
CPU time 5.72 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 251424 kb
Host smart-25ecf2df-f5cc-4d3a-b8ca-fcfd985d2543
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901091946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3901091946
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2316234458
Short name T117
Test name
Test status
Simulation time 5156858759 ps
CPU time 125.62 seconds
Started Jul 15 06:59:04 PM PDT 24
Finished Jul 15 07:01:11 PM PDT 24
Peak memory 1372012 kb
Host smart-24e7a804-100f-4848-b389-5bdd5e92429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316234458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2316234458
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.814738768
Short name T1079
Test name
Test status
Simulation time 609311872 ps
CPU time 6.98 seconds
Started Jul 15 06:59:10 PM PDT 24
Finished Jul 15 06:59:18 PM PDT 24
Peak memory 205532 kb
Host smart-5d1c8c3f-9929-42ea-9eb9-016a2f6e977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814738768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.814738768
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3082242414
Short name T1254
Test name
Test status
Simulation time 66499342 ps
CPU time 1.66 seconds
Started Jul 15 06:59:13 PM PDT 24
Finished Jul 15 06:59:16 PM PDT 24
Peak memory 213664 kb
Host smart-5abb400d-b229-44ba-85cc-799d3f896b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082242414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3082242414
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2503963105
Short name T92
Test name
Test status
Simulation time 204359557 ps
CPU time 0.68 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 06:59:05 PM PDT 24
Peak memory 205172 kb
Host smart-16d585f5-c5e8-47c0-aeed-b404d89a61f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503963105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2503963105
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1761467329
Short name T733
Test name
Test status
Simulation time 12754026751 ps
CPU time 705.58 seconds
Started Jul 15 06:59:07 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 1340940 kb
Host smart-790e3091-e19d-4443-8ad6-7820aae21f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761467329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1761467329
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3406485260
Short name T1737
Test name
Test status
Simulation time 23197882809 ps
CPU time 902.58 seconds
Started Jul 15 06:59:03 PM PDT 24
Finished Jul 15 07:14:07 PM PDT 24
Peak memory 213640 kb
Host smart-ad165c63-c389-4e98-a963-9f451d730fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406485260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3406485260
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2820760947
Short name T389
Test name
Test status
Simulation time 9102018492 ps
CPU time 35.71 seconds
Started Jul 15 06:59:07 PM PDT 24
Finished Jul 15 06:59:43 PM PDT 24
Peak memory 376148 kb
Host smart-d571f22c-80ea-4d14-8515-87ce4c751177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820760947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2820760947
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3858546994
Short name T1734
Test name
Test status
Simulation time 99144031054 ps
CPU time 1336.64 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 07:21:29 PM PDT 24
Peak memory 3156232 kb
Host smart-f14af343-6307-4eb2-8a3d-a7319f6a3532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858546994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3858546994
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3520215044
Short name T445
Test name
Test status
Simulation time 616250783 ps
CPU time 11.97 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 06:59:25 PM PDT 24
Peak memory 217204 kb
Host smart-5c8ba815-e95c-4b57-ad24-c79704ca3383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520215044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3520215044
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1998808396
Short name T1338
Test name
Test status
Simulation time 2397873353 ps
CPU time 4.01 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:24 PM PDT 24
Peak memory 213896 kb
Host smart-84b96262-df26-4a54-8e45-cc7187d64abb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998808396 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1998808396
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3115313151
Short name T620
Test name
Test status
Simulation time 187291463 ps
CPU time 1.28 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 06:59:14 PM PDT 24
Peak memory 205612 kb
Host smart-85f2d95a-97ec-4491-af44-d119b100b3ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115313151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3115313151
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3519161167
Short name T1694
Test name
Test status
Simulation time 198366559 ps
CPU time 1.27 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:13 PM PDT 24
Peak memory 209648 kb
Host smart-1330c242-7950-482c-8733-ae8eba43aee8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519161167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3519161167
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3443871377
Short name T1493
Test name
Test status
Simulation time 3814671322 ps
CPU time 2.95 seconds
Started Jul 15 06:59:09 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 205712 kb
Host smart-7ee72c5f-a072-4a9d-b209-42b8fa043d08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443871377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3443871377
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1821435853
Short name T970
Test name
Test status
Simulation time 86001777 ps
CPU time 0.98 seconds
Started Jul 15 06:59:13 PM PDT 24
Finished Jul 15 06:59:14 PM PDT 24
Peak memory 205392 kb
Host smart-1ee04425-2e5f-4b24-8e03-3efa6f37ebee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821435853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1821435853
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3253692935
Short name T1378
Test name
Test status
Simulation time 356325957 ps
CPU time 2.37 seconds
Started Jul 15 06:59:09 PM PDT 24
Finished Jul 15 06:59:12 PM PDT 24
Peak memory 213832 kb
Host smart-3552fdd1-239a-4d8c-88d4-37befcdb3ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253692935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3253692935
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2650815275
Short name T570
Test name
Test status
Simulation time 1410410207 ps
CPU time 7.79 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:20 PM PDT 24
Peak memory 222060 kb
Host smart-054624c9-5587-4971-af6b-2dd4c743eddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650815275 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2650815275
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1161960093
Short name T555
Test name
Test status
Simulation time 15718627660 ps
CPU time 14.6 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 364404 kb
Host smart-99ac6142-f9a4-4bfc-b40d-414f0ebe02f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161960093 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1161960093
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.2156012407
Short name T623
Test name
Test status
Simulation time 498289509 ps
CPU time 2.62 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 06:59:20 PM PDT 24
Peak memory 213872 kb
Host smart-b133d51d-6357-4c0a-8812-ac87d36c7710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156012407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.2156012407
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.808786655
Short name T414
Test name
Test status
Simulation time 1174424663 ps
CPU time 3.07 seconds
Started Jul 15 06:59:15 PM PDT 24
Finished Jul 15 06:59:18 PM PDT 24
Peak memory 205612 kb
Host smart-d2d1f26c-d28d-48a5-be5d-7a59afd6f26d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808786655 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.808786655
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3735337764
Short name T998
Test name
Test status
Simulation time 274093341 ps
CPU time 1.38 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:21 PM PDT 24
Peak memory 222472 kb
Host smart-244ce4da-162e-474a-aa03-cc27acb43663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735337764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3735337764
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.3247236662
Short name T1019
Test name
Test status
Simulation time 4115289268 ps
CPU time 4.64 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 06:59:17 PM PDT 24
Peak memory 217356 kb
Host smart-7158b2ba-2ce4-4f69-a811-640c8577fc76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247236662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.3247236662
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.1704499921
Short name T382
Test name
Test status
Simulation time 413961812 ps
CPU time 2.14 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:14 PM PDT 24
Peak memory 205404 kb
Host smart-aeb83e94-831f-4617-a6b0-5a8f6019f936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704499921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.1704499921
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2442948933
Short name T1478
Test name
Test status
Simulation time 575560399 ps
CPU time 17.72 seconds
Started Jul 15 06:59:16 PM PDT 24
Finished Jul 15 06:59:34 PM PDT 24
Peak memory 213844 kb
Host smart-f950794c-2103-4cf9-938a-845be9329602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442948933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2442948933
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.215694223
Short name T1448
Test name
Test status
Simulation time 137125695322 ps
CPU time 59.87 seconds
Started Jul 15 06:59:12 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 349100 kb
Host smart-ed55ea30-7c2f-4826-9fee-370885e60e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215694223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_target_stress_all.215694223
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.980057551
Short name T1333
Test name
Test status
Simulation time 4933430584 ps
CPU time 21.9 seconds
Started Jul 15 06:59:10 PM PDT 24
Finished Jul 15 06:59:33 PM PDT 24
Peak memory 233584 kb
Host smart-11a06955-799d-476a-ac9a-7234bfd51d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980057551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.980057551
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1734798372
Short name T1197
Test name
Test status
Simulation time 33349301528 ps
CPU time 122.4 seconds
Started Jul 15 06:59:14 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 1737492 kb
Host smart-9848f4b8-ed6e-4439-b4f0-22d4daf3c72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734798372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1734798372
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1139874666
Short name T1396
Test name
Test status
Simulation time 3221443503 ps
CPU time 7.86 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:19 PM PDT 24
Peak memory 298352 kb
Host smart-fb484435-03e1-4d2e-b810-16368196e3df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139874666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1139874666
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.4111602073
Short name T74
Test name
Test status
Simulation time 5411368963 ps
CPU time 6.79 seconds
Started Jul 15 06:59:11 PM PDT 24
Finished Jul 15 06:59:19 PM PDT 24
Peak memory 220092 kb
Host smart-eebbdb22-cd39-4c62-b123-39f91c664bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111602073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.4111602073
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.94647869
Short name T1250
Test name
Test status
Simulation time 293760339 ps
CPU time 4.25 seconds
Started Jul 15 06:59:10 PM PDT 24
Finished Jul 15 06:59:15 PM PDT 24
Peak memory 205624 kb
Host smart-359c607a-356d-40bb-81c9-33428adcd43d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94647869 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.94647869
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2423291156
Short name T124
Test name
Test status
Simulation time 46279723 ps
CPU time 0.66 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 204912 kb
Host smart-543c1c31-cc68-40b3-a678-629544203bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423291156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2423291156
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2926049567
Short name T1100
Test name
Test status
Simulation time 1942368684 ps
CPU time 25.38 seconds
Started Jul 15 06:59:16 PM PDT 24
Finished Jul 15 06:59:42 PM PDT 24
Peak memory 313864 kb
Host smart-b3a32c87-975d-43f1-8a45-4f4162fa6436
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926049567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2926049567
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.672833519
Short name T962
Test name
Test status
Simulation time 17423953284 ps
CPU time 228.43 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 07:03:07 PM PDT 24
Peak memory 769624 kb
Host smart-0b1bc0bf-abbb-4287-aad6-47b8dd75c8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672833519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.672833519
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2739210783
Short name T186
Test name
Test status
Simulation time 10594555868 ps
CPU time 202.47 seconds
Started Jul 15 06:59:20 PM PDT 24
Finished Jul 15 07:02:43 PM PDT 24
Peak memory 838936 kb
Host smart-62f97c71-5f65-4a9f-8bd3-a1ca0cb19b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739210783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2739210783
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2044769892
Short name T849
Test name
Test status
Simulation time 192651369 ps
CPU time 1.01 seconds
Started Jul 15 06:59:20 PM PDT 24
Finished Jul 15 06:59:21 PM PDT 24
Peak memory 205296 kb
Host smart-7c4d6467-c510-4976-9ef8-a46ea09d6c37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044769892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2044769892
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.643941870
Short name T462
Test name
Test status
Simulation time 1852782044 ps
CPU time 8.86 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 205540 kb
Host smart-96b27916-7c37-42e9-a4aa-cf1d54256402
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643941870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
643941870
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.655349364
Short name T882
Test name
Test status
Simulation time 12689676358 ps
CPU time 84.32 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 07:00:42 PM PDT 24
Peak memory 963976 kb
Host smart-0fcab527-7d99-49c7-bbc5-a4a12f631970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655349364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.655349364
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.495711848
Short name T1069
Test name
Test status
Simulation time 191187752 ps
CPU time 2.53 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 06:59:26 PM PDT 24
Peak memory 205524 kb
Host smart-26227d45-fa7c-4c28-8786-c46942afd584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495711848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.495711848
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.1705213816
Short name T139
Test name
Test status
Simulation time 27806549 ps
CPU time 0.75 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:21 PM PDT 24
Peak memory 205208 kb
Host smart-0f147467-07d4-4aaa-98de-767e609c545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705213816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1705213816
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3919144059
Short name T526
Test name
Test status
Simulation time 7084938094 ps
CPU time 21.8 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 06:59:39 PM PDT 24
Peak memory 427212 kb
Host smart-cc8b48b4-bd74-4c57-ae73-ae1dc672f69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919144059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3919144059
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.3584480368
Short name T632
Test name
Test status
Simulation time 24207201200 ps
CPU time 1672.97 seconds
Started Jul 15 06:59:21 PM PDT 24
Finished Jul 15 07:27:14 PM PDT 24
Peak memory 3927952 kb
Host smart-1f6f8ba4-f85b-4034-8cc8-aba7d36e72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584480368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.3584480368
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.841412278
Short name T1398
Test name
Test status
Simulation time 2769438245 ps
CPU time 61.97 seconds
Started Jul 15 06:59:20 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 293328 kb
Host smart-02f37f30-47fd-4386-8873-e5cced0d98a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841412278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.841412278
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3895932481
Short name T359
Test name
Test status
Simulation time 1577294709 ps
CPU time 16.08 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:35 PM PDT 24
Peak memory 213712 kb
Host smart-7ea0dce2-f89a-43ee-b3c4-b4e418d6754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895932481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3895932481
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.421635909
Short name T807
Test name
Test status
Simulation time 11223674827 ps
CPU time 4.86 seconds
Started Jul 15 06:59:25 PM PDT 24
Finished Jul 15 06:59:30 PM PDT 24
Peak memory 213852 kb
Host smart-a0c157ed-adb3-4d2a-824c-22234d6b5bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421635909 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.421635909
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1198512237
Short name T1663
Test name
Test status
Simulation time 289263447 ps
CPU time 1.34 seconds
Started Jul 15 06:59:21 PM PDT 24
Finished Jul 15 06:59:23 PM PDT 24
Peak memory 205464 kb
Host smart-c9e5d818-8592-4e97-84b9-2ad3991f9a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198512237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1198512237
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3780943898
Short name T754
Test name
Test status
Simulation time 1883761485 ps
CPU time 1.56 seconds
Started Jul 15 06:59:20 PM PDT 24
Finished Jul 15 06:59:22 PM PDT 24
Peak memory 205744 kb
Host smart-cac48316-8f94-4d42-9e47-5c24c2ede04c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780943898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3780943898
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.4120525676
Short name T763
Test name
Test status
Simulation time 6333031048 ps
CPU time 2.7 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 205652 kb
Host smart-6ddb5985-dbbc-42ae-8df7-695db499172f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120525676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.4120525676
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1467664088
Short name T1043
Test name
Test status
Simulation time 538061749 ps
CPU time 1.43 seconds
Started Jul 15 06:59:27 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 205476 kb
Host smart-56ace64d-fe91-414f-b514-caf78bf2b5ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467664088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1467664088
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.216956239
Short name T1157
Test name
Test status
Simulation time 1459972381 ps
CPU time 2.63 seconds
Started Jul 15 06:59:24 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 213848 kb
Host smart-04c9e639-011c-4250-916b-9ed75a0ffec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216956239 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.216956239
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1703228376
Short name T330
Test name
Test status
Simulation time 2394708110 ps
CPU time 4.43 seconds
Started Jul 15 06:59:21 PM PDT 24
Finished Jul 15 06:59:26 PM PDT 24
Peak memory 218096 kb
Host smart-e938e0fd-c371-4fce-9e69-ec66ef5c6626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703228376 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1703228376
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3967078795
Short name T960
Test name
Test status
Simulation time 5366776803 ps
CPU time 2.26 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 06:59:20 PM PDT 24
Peak memory 205696 kb
Host smart-1937bdaa-7dcb-456e-9fa7-b9574acf5f79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967078795 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3967078795
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.3344993694
Short name T1732
Test name
Test status
Simulation time 2266947152 ps
CPU time 2.93 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 213896 kb
Host smart-9efee12a-f254-4c32-aa09-b3488d7be49c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344993694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.3344993694
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.2787338413
Short name T1537
Test name
Test status
Simulation time 1951115157 ps
CPU time 2.66 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 205644 kb
Host smart-11bb7816-99cc-4a98-9643-175e5953a4da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787338413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.2787338413
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.2249740253
Short name T831
Test name
Test status
Simulation time 1043388542 ps
CPU time 5.65 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:25 PM PDT 24
Peak memory 213828 kb
Host smart-c305f7ab-2973-4729-a37c-821a9af15d31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249740253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.2249740253
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.204604111
Short name T1252
Test name
Test status
Simulation time 973652574 ps
CPU time 2.12 seconds
Started Jul 15 06:59:24 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 205432 kb
Host smart-4067d5b4-5b12-4cfc-a7f3-4da90e774aa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204604111 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_smbus_maxlen.204604111
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2314638787
Short name T473
Test name
Test status
Simulation time 843100011 ps
CPU time 27.04 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 06:59:50 PM PDT 24
Peak memory 213804 kb
Host smart-1225bdaf-4357-4949-9700-33efaa432489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314638787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2314638787
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.1247921099
Short name T228
Test name
Test status
Simulation time 124528388860 ps
CPU time 58.06 seconds
Started Jul 15 06:59:17 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 303792 kb
Host smart-4db44324-1845-4cfd-99e8-2aba11b64415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247921099 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.1247921099
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1403387505
Short name T681
Test name
Test status
Simulation time 1183088881 ps
CPU time 6.18 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:26 PM PDT 24
Peak memory 205616 kb
Host smart-65bfda80-c2f4-4813-8aaa-c47a72046890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403387505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1403387505
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3097045379
Short name T1044
Test name
Test status
Simulation time 66558760455 ps
CPU time 3547.68 seconds
Started Jul 15 06:59:21 PM PDT 24
Finished Jul 15 07:58:30 PM PDT 24
Peak memory 11842464 kb
Host smart-930abb17-1c63-4f9a-947c-d5fd03cbe178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097045379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3097045379
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.711340937
Short name T802
Test name
Test status
Simulation time 1721355119 ps
CPU time 7 seconds
Started Jul 15 06:59:22 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 278144 kb
Host smart-99941161-0b91-4473-83f0-aff8659a00bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711340937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.711340937
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1701967037
Short name T988
Test name
Test status
Simulation time 3130316956 ps
CPU time 7.82 seconds
Started Jul 15 06:59:19 PM PDT 24
Finished Jul 15 06:59:27 PM PDT 24
Peak memory 230232 kb
Host smart-d4618cea-3fda-49d6-96dc-64529b528f56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701967037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1701967037
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2470078354
Short name T1237
Test name
Test status
Simulation time 140130083 ps
CPU time 3.22 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:29 PM PDT 24
Peak memory 205700 kb
Host smart-3402d2b7-5e35-4c5a-9506-74adea311b8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470078354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2470078354
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.110317197
Short name T1731
Test name
Test status
Simulation time 20626235 ps
CPU time 0.64 seconds
Started Jul 15 06:59:27 PM PDT 24
Finished Jul 15 06:59:28 PM PDT 24
Peak memory 204876 kb
Host smart-37bd643a-cb8d-47fe-8a45-12574555fce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110317197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.110317197
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1588241289
Short name T1054
Test name
Test status
Simulation time 722021732 ps
CPU time 14.31 seconds
Started Jul 15 06:59:27 PM PDT 24
Finished Jul 15 06:59:42 PM PDT 24
Peak memory 213792 kb
Host smart-867996c2-579b-47eb-93f4-fa9dd61d0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588241289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1588241289
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1484831884
Short name T1368
Test name
Test status
Simulation time 1539406982 ps
CPU time 19.72 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 290528 kb
Host smart-22afd5c6-ae16-4a63-b9bc-bba4784031a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484831884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1484831884
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.241023929
Short name T978
Test name
Test status
Simulation time 2735791117 ps
CPU time 145.83 seconds
Started Jul 15 06:59:22 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 499680 kb
Host smart-629c0c0b-b153-448a-ab72-cc4565a21f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241023929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.241023929
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1824175153
Short name T697
Test name
Test status
Simulation time 9577692542 ps
CPU time 68.48 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 734516 kb
Host smart-0aa17840-cc40-42d1-9aed-0d3268e8f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824175153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1824175153
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3906063605
Short name T1006
Test name
Test status
Simulation time 144124408 ps
CPU time 1.27 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 06:59:25 PM PDT 24
Peak memory 205224 kb
Host smart-7436a8e2-6c94-45a7-928a-4bc057ab4130
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906063605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3906063605
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3133559101
Short name T533
Test name
Test status
Simulation time 739477065 ps
CPU time 5.96 seconds
Started Jul 15 06:59:26 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 244996 kb
Host smart-9a8dd32c-6efc-4d68-aacb-067be819a942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133559101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3133559101
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1476629327
Short name T1297
Test name
Test status
Simulation time 7598334151 ps
CPU time 217.35 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 07:03:01 PM PDT 24
Peak memory 984280 kb
Host smart-c9292858-9a68-4049-8d3b-bd3170ca0a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476629327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1476629327
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1439348699
Short name T884
Test name
Test status
Simulation time 339988484 ps
CPU time 5.55 seconds
Started Jul 15 06:59:34 PM PDT 24
Finished Jul 15 06:59:39 PM PDT 24
Peak memory 205504 kb
Host smart-44d5a6cf-5c6d-49df-8888-951f3b759000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439348699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1439348699
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.821809884
Short name T1498
Test name
Test status
Simulation time 247274679 ps
CPU time 4.5 seconds
Started Jul 15 06:59:36 PM PDT 24
Finished Jul 15 06:59:41 PM PDT 24
Peak memory 231888 kb
Host smart-9e2325a9-9aef-45b2-b1cc-aeed7cf066c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821809884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.821809884
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.504798461
Short name T433
Test name
Test status
Simulation time 29321164 ps
CPU time 0.69 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 06:59:24 PM PDT 24
Peak memory 205212 kb
Host smart-f7a0ab31-8ef0-4c8b-952e-bfaa02e5c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504798461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.504798461
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.5443523
Short name T815
Test name
Test status
Simulation time 5455439913 ps
CPU time 208.97 seconds
Started Jul 15 06:59:32 PM PDT 24
Finished Jul 15 07:03:01 PM PDT 24
Peak memory 229972 kb
Host smart-bed09834-c409-4931-bfed-cbb1aecd1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5443523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.5443523
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.749512542
Short name T902
Test name
Test status
Simulation time 432217988 ps
CPU time 3.07 seconds
Started Jul 15 06:59:27 PM PDT 24
Finished Jul 15 06:59:31 PM PDT 24
Peak memory 205400 kb
Host smart-2ff57b99-9cd0-4790-b021-a4566635635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749512542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.749512542
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4124831599
Short name T1595
Test name
Test status
Simulation time 2204059789 ps
CPU time 40.54 seconds
Started Jul 15 06:59:23 PM PDT 24
Finished Jul 15 07:00:04 PM PDT 24
Peak memory 430800 kb
Host smart-5c29ca88-4c29-4490-bb88-81c6b329884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124831599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4124831599
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2933110048
Short name T1292
Test name
Test status
Simulation time 6051649863 ps
CPU time 10.18 seconds
Started Jul 15 06:59:28 PM PDT 24
Finished Jul 15 06:59:39 PM PDT 24
Peak memory 213744 kb
Host smart-085bd25d-9d75-46ac-aad7-bd4ebff0a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933110048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2933110048
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.853291325
Short name T582
Test name
Test status
Simulation time 1456499670 ps
CPU time 4.26 seconds
Started Jul 15 06:59:27 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 213928 kb
Host smart-b49a5fbe-6b1b-4424-a238-64df5ae1cf5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853291325 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.853291325
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3578620696
Short name T1507
Test name
Test status
Simulation time 222966039 ps
CPU time 1 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 205420 kb
Host smart-eab7cb48-73fe-4ad7-83cd-aa2a585594d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578620696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3578620696
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1392699880
Short name T885
Test name
Test status
Simulation time 526951481 ps
CPU time 1.32 seconds
Started Jul 15 06:59:31 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 205640 kb
Host smart-252717e6-3b49-43c5-b92d-ca2e9d470aae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392699880 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1392699880
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.4147431264
Short name T610
Test name
Test status
Simulation time 1920172016 ps
CPU time 2.43 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 205700 kb
Host smart-3e6cf135-7e8f-4210-8b5b-ef0c1232e8c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147431264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.4147431264
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.295469333
Short name T179
Test name
Test status
Simulation time 154801842 ps
CPU time 1.57 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 06:59:32 PM PDT 24
Peak memory 205456 kb
Host smart-bc5ae89d-9b0f-4bef-8e1b-a22530536b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295469333 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.295469333
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.659666346
Short name T1065
Test name
Test status
Simulation time 1514501761 ps
CPU time 2.91 seconds
Started Jul 15 06:59:35 PM PDT 24
Finished Jul 15 06:59:38 PM PDT 24
Peak memory 220620 kb
Host smart-142f5931-9533-40de-ad33-26c55bd42f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659666346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.659666346
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.4270514982
Short name T321
Test name
Test status
Simulation time 1334479463 ps
CPU time 6.8 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 06:59:37 PM PDT 24
Peak memory 222024 kb
Host smart-f6ea2db7-1dd3-4b8c-a7f3-4a8ea2a5e9fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270514982 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.4270514982
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.111788768
Short name T1097
Test name
Test status
Simulation time 8163798400 ps
CPU time 104.74 seconds
Started Jul 15 06:59:28 PM PDT 24
Finished Jul 15 07:01:14 PM PDT 24
Peak memory 2040296 kb
Host smart-511a13f1-3dac-48f9-8054-fda7530e8a52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111788768 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.111788768
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.3300346558
Short name T1701
Test name
Test status
Simulation time 2495193422 ps
CPU time 3.18 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:33 PM PDT 24
Peak memory 213852 kb
Host smart-13e5d7d5-41bb-4bd9-ac3a-842c7e7580fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300346558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.3300346558
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.3296648150
Short name T1687
Test name
Test status
Simulation time 1440096883 ps
CPU time 2.43 seconds
Started Jul 15 06:59:33 PM PDT 24
Finished Jul 15 06:59:35 PM PDT 24
Peak memory 205620 kb
Host smart-bd530254-bdea-4550-aaef-daa0c7c4c205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296648150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.3296648150
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.1853619081
Short name T715
Test name
Test status
Simulation time 146987750 ps
CPU time 1.36 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:31 PM PDT 24
Peak memory 222412 kb
Host smart-7a1ab851-9eb1-4fe4-800e-6c259e5478fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853619081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.1853619081
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1221987051
Short name T1089
Test name
Test status
Simulation time 2588325077 ps
CPU time 5.23 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:35 PM PDT 24
Peak memory 222100 kb
Host smart-b53c846c-1bf9-402f-a317-83e7c043ac72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221987051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1221987051
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.2696740860
Short name T1636
Test name
Test status
Simulation time 2393758642 ps
CPU time 2.36 seconds
Started Jul 15 06:59:32 PM PDT 24
Finished Jul 15 06:59:34 PM PDT 24
Peak memory 205560 kb
Host smart-a6ca539d-7555-43e4-ad05-e9ffc42bfd47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696740860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.2696740860
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3383553481
Short name T487
Test name
Test status
Simulation time 559166151 ps
CPU time 9.01 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:38 PM PDT 24
Peak memory 213828 kb
Host smart-4b1f9bbe-947d-4a56-85b1-8778a5eb0389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383553481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3383553481
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.1450221310
Short name T1531
Test name
Test status
Simulation time 29100205821 ps
CPU time 173.9 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 1169668 kb
Host smart-a70cea57-e825-43d5-84bc-97e3135e9cc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450221310 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.1450221310
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1713452095
Short name T976
Test name
Test status
Simulation time 689958083 ps
CPU time 29.42 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 213876 kb
Host smart-851c63d4-503d-4a6a-9c44-9547475f1cec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713452095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1713452095
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1579470758
Short name T420
Test name
Test status
Simulation time 26873194480 ps
CPU time 22.95 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 06:59:54 PM PDT 24
Peak memory 504304 kb
Host smart-d8619a93-f8c8-4011-81e4-07c20017b6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579470758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1579470758
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2012162250
Short name T306
Test name
Test status
Simulation time 5662157495 ps
CPU time 8.85 seconds
Started Jul 15 06:59:30 PM PDT 24
Finished Jul 15 06:59:40 PM PDT 24
Peak memory 289612 kb
Host smart-7b957244-e6fe-497c-ada9-a1cb34874925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012162250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2012162250
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1747404086
Short name T492
Test name
Test status
Simulation time 2457148913 ps
CPU time 6.06 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:36 PM PDT 24
Peak memory 213852 kb
Host smart-878b63f8-86e9-458c-b13c-6ea6941d7e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747404086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1747404086
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.1703036624
Short name T544
Test name
Test status
Simulation time 39635290 ps
CPU time 1.08 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 06:59:31 PM PDT 24
Peak memory 205672 kb
Host smart-51f62387-2c62-436d-bd4a-1744ea9b44af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703036624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1703036624
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.669503765
Short name T687
Test name
Test status
Simulation time 21048639 ps
CPU time 0.7 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:52:28 PM PDT 24
Peak memory 204716 kb
Host smart-5540d94d-d216-4ec2-91c6-84db0c460e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669503765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.669503765
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3068841110
Short name T1339
Test name
Test status
Simulation time 6136142066 ps
CPU time 6.09 seconds
Started Jul 15 06:52:16 PM PDT 24
Finished Jul 15 06:52:22 PM PDT 24
Peak memory 263132 kb
Host smart-76c42faa-74f6-4a18-b816-cfe324f07188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068841110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3068841110
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3254892075
Short name T1078
Test name
Test status
Simulation time 359176742 ps
CPU time 9.2 seconds
Started Jul 15 06:52:15 PM PDT 24
Finished Jul 15 06:52:25 PM PDT 24
Peak memory 240048 kb
Host smart-c01133c5-d1fb-4b13-b22c-79c7fe5ba461
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254892075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3254892075
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.4152729304
Short name T326
Test name
Test status
Simulation time 5054547368 ps
CPU time 77.05 seconds
Started Jul 15 06:52:13 PM PDT 24
Finished Jul 15 06:53:30 PM PDT 24
Peak memory 579400 kb
Host smart-f68dd554-7335-4da9-b285-200f9e753a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152729304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.4152729304
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1023436360
Short name T1633
Test name
Test status
Simulation time 2052376568 ps
CPU time 58.32 seconds
Started Jul 15 06:52:15 PM PDT 24
Finished Jul 15 06:53:14 PM PDT 24
Peak memory 666208 kb
Host smart-07f62f2d-68f5-4eb1-91f0-f09d8de78a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023436360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1023436360
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.676580419
Short name T1501
Test name
Test status
Simulation time 99697455 ps
CPU time 0.88 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:20 PM PDT 24
Peak memory 205216 kb
Host smart-e3944316-04a7-4173-a78c-d57a6f635052
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676580419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.676580419
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3588650091
Short name T1699
Test name
Test status
Simulation time 183678850 ps
CPU time 4.43 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 205516 kb
Host smart-f04b187d-338c-4ca8-801e-b2b61c4ecf10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588650091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3588650091
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3024265145
Short name T1611
Test name
Test status
Simulation time 20347214636 ps
CPU time 369.37 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:58:28 PM PDT 24
Peak memory 1455336 kb
Host smart-953fc13b-3dfd-4f24-b27b-28915e6a75fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024265145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3024265145
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3560404668
Short name T256
Test name
Test status
Simulation time 300280418 ps
CPU time 13.08 seconds
Started Jul 15 06:52:21 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 205508 kb
Host smart-b5eb596e-76ce-4c1f-8a54-c54c3c425c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560404668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3560404668
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.2451201778
Short name T399
Test name
Test status
Simulation time 43724661 ps
CPU time 0.69 seconds
Started Jul 15 06:52:14 PM PDT 24
Finished Jul 15 06:52:16 PM PDT 24
Peak memory 205156 kb
Host smart-440400a4-3f32-4fc3-afe1-898367e47b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451201778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2451201778
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3211063444
Short name T648
Test name
Test status
Simulation time 5515849327 ps
CPU time 110.76 seconds
Started Jul 15 06:52:16 PM PDT 24
Finished Jul 15 06:54:07 PM PDT 24
Peak memory 206560 kb
Host smart-18c9bc83-af23-488f-a72f-a7558bcd83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211063444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3211063444
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.4027266362
Short name T1582
Test name
Test status
Simulation time 2525156924 ps
CPU time 7.79 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:27 PM PDT 24
Peak memory 205760 kb
Host smart-d1fb4769-a769-4762-a6e5-209ce9e3b887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027266362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.4027266362
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1045603999
Short name T437
Test name
Test status
Simulation time 17277135457 ps
CPU time 19.71 seconds
Started Jul 15 06:52:13 PM PDT 24
Finished Jul 15 06:52:33 PM PDT 24
Peak memory 258040 kb
Host smart-3ec1f69f-abb4-440a-a6df-9b203e97c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045603999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1045603999
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.486842005
Short name T283
Test name
Test status
Simulation time 31433981670 ps
CPU time 2679.72 seconds
Started Jul 15 06:52:17 PM PDT 24
Finished Jul 15 07:36:57 PM PDT 24
Peak memory 4486324 kb
Host smart-fcbecf03-3c1c-4223-8e79-5052a586974b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486842005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.486842005
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1785074219
Short name T175
Test name
Test status
Simulation time 1419179079 ps
CPU time 12.51 seconds
Started Jul 15 06:52:12 PM PDT 24
Finished Jul 15 06:52:26 PM PDT 24
Peak memory 221364 kb
Host smart-51647561-987a-4f68-b008-fd6fa4c5bc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785074219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1785074219
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1479322144
Short name T1128
Test name
Test status
Simulation time 883830784 ps
CPU time 5.28 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:24 PM PDT 24
Peak memory 218688 kb
Host smart-80094046-6795-42e6-b96e-4f58ede63a8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479322144 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1479322144
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3922607347
Short name T1229
Test name
Test status
Simulation time 312892289 ps
CPU time 1.21 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:20 PM PDT 24
Peak memory 205604 kb
Host smart-fa06bee9-6814-4fcb-ac87-5d17538e91c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922607347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3922607347
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2845927676
Short name T1509
Test name
Test status
Simulation time 267133006 ps
CPU time 1.53 seconds
Started Jul 15 06:52:20 PM PDT 24
Finished Jul 15 06:52:22 PM PDT 24
Peak memory 210880 kb
Host smart-01de2ca7-0341-45b0-b15c-0bb2dee60834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845927676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2845927676
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.520128372
Short name T1223
Test name
Test status
Simulation time 370343067 ps
CPU time 2.57 seconds
Started Jul 15 06:52:20 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 205552 kb
Host smart-d54f4714-1c5f-4420-b10b-8340d871c082
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520128372 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.520128372
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2205514344
Short name T535
Test name
Test status
Simulation time 203069548 ps
CPU time 1.76 seconds
Started Jul 15 06:52:21 PM PDT 24
Finished Jul 15 06:52:24 PM PDT 24
Peak memory 205472 kb
Host smart-5bb3d852-a97a-4c62-854d-7fe89611edd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205514344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2205514344
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3295731809
Short name T953
Test name
Test status
Simulation time 2370554976 ps
CPU time 5.63 seconds
Started Jul 15 06:52:17 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 221852 kb
Host smart-73f3e1f8-15cb-46c2-b0b2-1c2c41d679be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295731809 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3295731809
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2465765746
Short name T739
Test name
Test status
Simulation time 11362535681 ps
CPU time 10.32 seconds
Started Jul 15 06:52:18 PM PDT 24
Finished Jul 15 06:52:29 PM PDT 24
Peak memory 307508 kb
Host smart-01866ecc-f861-463a-bf8c-67e0b11100cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465765746 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2465765746
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.3599200548
Short name T418
Test name
Test status
Simulation time 1055084343 ps
CPU time 3.18 seconds
Started Jul 15 06:52:19 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 213756 kb
Host smart-b2208938-8d96-40f1-8497-459d3706b2ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599200548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.3599200548
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.1604875631
Short name T663
Test name
Test status
Simulation time 487262453 ps
CPU time 2.62 seconds
Started Jul 15 06:52:20 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 206204 kb
Host smart-793c92aa-814e-4c2d-a326-50e24d944088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604875631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.1604875631
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.1205982631
Short name T1139
Test name
Test status
Simulation time 3539225615 ps
CPU time 5.18 seconds
Started Jul 15 06:52:22 PM PDT 24
Finished Jul 15 06:52:28 PM PDT 24
Peak memory 222100 kb
Host smart-2ed42f2d-438c-4847-9ffd-06fa00bc6ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205982631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.1205982631
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.3144245465
Short name T1490
Test name
Test status
Simulation time 448926811 ps
CPU time 2.22 seconds
Started Jul 15 06:52:20 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 205408 kb
Host smart-b487137f-4533-43d9-b86d-9cab5b6e0305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144245465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_smbus_maxlen.3144245465
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1654762466
Short name T1460
Test name
Test status
Simulation time 12223094216 ps
CPU time 34.56 seconds
Started Jul 15 06:52:13 PM PDT 24
Finished Jul 15 06:52:48 PM PDT 24
Peak memory 213920 kb
Host smart-4bb8db64-bc01-400d-a958-4fcebca62f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654762466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1654762466
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.551382766
Short name T301
Test name
Test status
Simulation time 21446847971 ps
CPU time 19.94 seconds
Started Jul 15 06:52:21 PM PDT 24
Finished Jul 15 06:52:42 PM PDT 24
Peak memory 222124 kb
Host smart-69304879-5302-4389-9e98-447cf52665e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551382766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_stress_all.551382766
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3064226732
Short name T780
Test name
Test status
Simulation time 375366510 ps
CPU time 14.21 seconds
Started Jul 15 06:52:17 PM PDT 24
Finished Jul 15 06:52:33 PM PDT 24
Peak memory 205672 kb
Host smart-c9c2f987-c70d-48d2-bb4c-8e0f21e04487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064226732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3064226732
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3578299821
Short name T869
Test name
Test status
Simulation time 47218521014 ps
CPU time 1279.02 seconds
Started Jul 15 06:52:16 PM PDT 24
Finished Jul 15 07:13:36 PM PDT 24
Peak memory 7127856 kb
Host smart-4299b585-84f2-48b4-9b08-2f9a9eaf4072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578299821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3578299821
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3785100825
Short name T334
Test name
Test status
Simulation time 6049967282 ps
CPU time 131.71 seconds
Started Jul 15 06:52:14 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 1402564 kb
Host smart-dc47375c-3d0d-4c79-9268-72187669ac89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785100825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3785100825
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3439395962
Short name T750
Test name
Test status
Simulation time 2847793449 ps
CPU time 7.56 seconds
Started Jul 15 06:52:14 PM PDT 24
Finished Jul 15 06:52:23 PM PDT 24
Peak memory 219112 kb
Host smart-a0ca5324-4f74-497d-877f-1a9d583e8ffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439395962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3439395962
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.3397437009
Short name T916
Test name
Test status
Simulation time 100953026 ps
CPU time 1.56 seconds
Started Jul 15 06:52:23 PM PDT 24
Finished Jul 15 06:52:25 PM PDT 24
Peak memory 205624 kb
Host smart-5482cb1e-0a6d-4afa-ad76-9265c06e7f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397437009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.3397437009
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.531166936
Short name T1653
Test name
Test status
Simulation time 15380538 ps
CPU time 0.67 seconds
Started Jul 15 06:52:42 PM PDT 24
Finished Jul 15 06:52:43 PM PDT 24
Peak memory 204892 kb
Host smart-548afbde-91a9-4003-84c8-37d10b856414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531166936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.531166936
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1909356797
Short name T506
Test name
Test status
Simulation time 411210232 ps
CPU time 2.96 seconds
Started Jul 15 06:52:28 PM PDT 24
Finished Jul 15 06:52:31 PM PDT 24
Peak memory 213748 kb
Host smart-6da89bd5-8e2d-4fd5-a5f9-d3274b0d7255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909356797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1909356797
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.791367784
Short name T1661
Test name
Test status
Simulation time 852557139 ps
CPU time 6.99 seconds
Started Jul 15 06:52:26 PM PDT 24
Finished Jul 15 06:52:34 PM PDT 24
Peak memory 228716 kb
Host smart-7a809caa-4404-4e17-bcb6-8918c233149c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791367784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.791367784
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2278052363
Short name T1587
Test name
Test status
Simulation time 6645231775 ps
CPU time 98.25 seconds
Started Jul 15 06:52:30 PM PDT 24
Finished Jul 15 06:54:08 PM PDT 24
Peak memory 407436 kb
Host smart-cf748d5b-19c5-4468-b224-23e0bb6519f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278052363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2278052363
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3361154735
Short name T758
Test name
Test status
Simulation time 7566911092 ps
CPU time 152.36 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:55:00 PM PDT 24
Peak memory 715020 kb
Host smart-126a24e8-9a46-443b-b648-0532a4ec5fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361154735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3361154735
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1725009975
Short name T734
Test name
Test status
Simulation time 244996472 ps
CPU time 1.2 seconds
Started Jul 15 06:52:30 PM PDT 24
Finished Jul 15 06:52:32 PM PDT 24
Peak memory 205292 kb
Host smart-03a7efb9-6153-47e0-a3ee-452ffdc4f0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725009975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1725009975
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2314065182
Short name T1659
Test name
Test status
Simulation time 150137554 ps
CPU time 4.42 seconds
Started Jul 15 06:52:28 PM PDT 24
Finished Jul 15 06:52:33 PM PDT 24
Peak memory 229996 kb
Host smart-0e24e128-30ce-4f72-b287-f43a75e1e158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314065182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2314065182
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2776271737
Short name T1468
Test name
Test status
Simulation time 8378397706 ps
CPU time 298.2 seconds
Started Jul 15 06:52:26 PM PDT 24
Finished Jul 15 06:57:25 PM PDT 24
Peak memory 1228620 kb
Host smart-c12bd9b5-9238-42ad-9897-f9105167124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776271737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2776271737
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2743111218
Short name T82
Test name
Test status
Simulation time 506778139 ps
CPU time 5.03 seconds
Started Jul 15 06:52:33 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 230136 kb
Host smart-b0235c1f-6b91-4ac8-aab3-824c44c98ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743111218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2743111218
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3055497156
Short name T421
Test name
Test status
Simulation time 29527135 ps
CPU time 0.68 seconds
Started Jul 15 06:52:28 PM PDT 24
Finished Jul 15 06:52:30 PM PDT 24
Peak memory 205168 kb
Host smart-2feb53c4-6091-4d95-bbfa-6b7e89e90d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055497156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3055497156
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3326625793
Short name T779
Test name
Test status
Simulation time 12578308930 ps
CPU time 139.61 seconds
Started Jul 15 06:52:28 PM PDT 24
Finished Jul 15 06:54:48 PM PDT 24
Peak memory 205536 kb
Host smart-7e088ad0-c46d-46a9-b709-b535ad1d1ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326625793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3326625793
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1407410986
Short name T1423
Test name
Test status
Simulation time 139152752 ps
CPU time 1.97 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:52:30 PM PDT 24
Peak memory 213660 kb
Host smart-ba2514af-44d2-458f-94e8-68be8995a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407410986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1407410986
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3689952998
Short name T513
Test name
Test status
Simulation time 8946849051 ps
CPU time 107.97 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:54:15 PM PDT 24
Peak memory 356208 kb
Host smart-c5e98548-4ed9-4375-9cf0-c41c0f42f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689952998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3689952998
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3005761836
Short name T871
Test name
Test status
Simulation time 848787852 ps
CPU time 7.89 seconds
Started Jul 15 06:52:26 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 213676 kb
Host smart-df483e43-2727-49bd-896a-ffdf038c658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005761836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3005761836
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3323567767
Short name T701
Test name
Test status
Simulation time 665269671 ps
CPU time 3.53 seconds
Started Jul 15 06:52:33 PM PDT 24
Finished Jul 15 06:52:37 PM PDT 24
Peak memory 213864 kb
Host smart-97fb6e51-c981-4fc8-bb64-786e13a4858e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323567767 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3323567767
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.751218336
Short name T1693
Test name
Test status
Simulation time 670420445 ps
CPU time 1.44 seconds
Started Jul 15 06:52:35 PM PDT 24
Finished Jul 15 06:52:36 PM PDT 24
Peak memory 205672 kb
Host smart-36397917-7c07-44f6-9547-7fcd64d16d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751218336 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.751218336
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.572489029
Short name T310
Test name
Test status
Simulation time 179976838 ps
CPU time 1.12 seconds
Started Jul 15 06:52:34 PM PDT 24
Finished Jul 15 06:52:36 PM PDT 24
Peak memory 205480 kb
Host smart-87987c6e-90f3-4c88-9941-eb082a7d531d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572489029 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.572489029
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.4019919148
Short name T1057
Test name
Test status
Simulation time 1630312260 ps
CPU time 2.54 seconds
Started Jul 15 06:52:32 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 205628 kb
Host smart-c08e9492-cf8f-411c-8b13-7fa329341371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019919148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.4019919148
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2186504097
Short name T1635
Test name
Test status
Simulation time 556348513 ps
CPU time 1.42 seconds
Started Jul 15 06:52:33 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 205492 kb
Host smart-b26a09dc-706e-4a66-9911-183070d25b42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186504097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2186504097
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.212285465
Short name T599
Test name
Test status
Simulation time 4035007610 ps
CPU time 6.55 seconds
Started Jul 15 06:52:29 PM PDT 24
Finished Jul 15 06:52:36 PM PDT 24
Peak memory 221488 kb
Host smart-fb23edcf-3918-4479-abdf-b17e42c6a0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212285465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.212285465
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1757481294
Short name T1364
Test name
Test status
Simulation time 15471964959 ps
CPU time 334.2 seconds
Started Jul 15 06:52:31 PM PDT 24
Finished Jul 15 06:58:05 PM PDT 24
Peak memory 3834984 kb
Host smart-8f2ceb91-3638-4254-a234-7b58f27f0747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757481294 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1757481294
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.678601149
Short name T165
Test name
Test status
Simulation time 2674347887 ps
CPU time 2.96 seconds
Started Jul 15 06:52:32 PM PDT 24
Finished Jul 15 06:52:36 PM PDT 24
Peak memory 213888 kb
Host smart-e001a335-376b-4257-9457-a88b3ef93687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678601149 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_nack_acqfull.678601149
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.3567140669
Short name T948
Test name
Test status
Simulation time 1125317473 ps
CPU time 2.64 seconds
Started Jul 15 06:52:39 PM PDT 24
Finished Jul 15 06:52:42 PM PDT 24
Peak memory 205660 kb
Host smart-f35e41e9-cb06-4864-a284-3b134bcd20bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567140669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.3567140669
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.3312482882
Short name T303
Test name
Test status
Simulation time 1487952621 ps
CPU time 4.98 seconds
Started Jul 15 06:52:34 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 222012 kb
Host smart-7f39c874-7fe9-4a0f-a408-697b47301e1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312482882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.3312482882
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.2917889329
Short name T1132
Test name
Test status
Simulation time 1938227978 ps
CPU time 2.23 seconds
Started Jul 15 06:52:32 PM PDT 24
Finished Jul 15 06:52:34 PM PDT 24
Peak memory 205424 kb
Host smart-1a847145-1765-4ca9-a39f-cc066918d0fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917889329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.2917889329
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1487685397
Short name T1275
Test name
Test status
Simulation time 2330428360 ps
CPU time 37.35 seconds
Started Jul 15 06:52:26 PM PDT 24
Finished Jul 15 06:53:04 PM PDT 24
Peak memory 213964 kb
Host smart-45eb4fb8-d542-4656-b5ef-130f043b3ba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487685397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1487685397
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.3693942056
Short name T275
Test name
Test status
Simulation time 57435509742 ps
CPU time 2712.65 seconds
Started Jul 15 06:52:34 PM PDT 24
Finished Jul 15 07:37:48 PM PDT 24
Peak memory 9661748 kb
Host smart-7dcde582-2b9d-4944-8b68-1f00a5746742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693942056 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.3693942056
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3586700223
Short name T908
Test name
Test status
Simulation time 5836989848 ps
CPU time 24.14 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:52:52 PM PDT 24
Peak memory 241232 kb
Host smart-0ebb6854-9263-4bc8-afcf-8320f861ba94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586700223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3586700223
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3093748922
Short name T320
Test name
Test status
Simulation time 39260282182 ps
CPU time 76.35 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:53:44 PM PDT 24
Peak memory 1243904 kb
Host smart-767b0ff4-6e49-4f72-bdda-bda51ad9604c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093748922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3093748922
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1425585612
Short name T1577
Test name
Test status
Simulation time 5902896494 ps
CPU time 7.7 seconds
Started Jul 15 06:52:27 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 230280 kb
Host smart-366b6a7d-7b70-4a6d-8d69-a8a95061be00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425585612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1425585612
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.4134008280
Short name T6
Test name
Test status
Simulation time 335961859 ps
CPU time 4.69 seconds
Started Jul 15 06:52:30 PM PDT 24
Finished Jul 15 06:52:35 PM PDT 24
Peak memory 205616 kb
Host smart-f5df5bda-bbb9-4694-ad8a-b4f6c647d8bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134008280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.4134008280
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1437626373
Short name T906
Test name
Test status
Simulation time 37725033 ps
CPU time 0.63 seconds
Started Jul 15 06:52:49 PM PDT 24
Finished Jul 15 06:52:50 PM PDT 24
Peak memory 204920 kb
Host smart-40d8b5eb-3f04-4c15-bba3-6db816868449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437626373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1437626373
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.230599077
Short name T1240
Test name
Test status
Simulation time 79608203 ps
CPU time 1.26 seconds
Started Jul 15 06:52:44 PM PDT 24
Finished Jul 15 06:52:45 PM PDT 24
Peak memory 213808 kb
Host smart-e136a19d-33ad-4752-b477-60905bcf6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230599077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.230599077
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2645355701
Short name T999
Test name
Test status
Simulation time 570160511 ps
CPU time 21.15 seconds
Started Jul 15 06:52:39 PM PDT 24
Finished Jul 15 06:53:01 PM PDT 24
Peak memory 294140 kb
Host smart-f1c77b73-f193-4a50-99eb-0d3ed4169e76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645355701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2645355701
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1355822051
Short name T318
Test name
Test status
Simulation time 2015332407 ps
CPU time 107.54 seconds
Started Jul 15 06:52:44 PM PDT 24
Finished Jul 15 06:54:32 PM PDT 24
Peak memory 401636 kb
Host smart-68c92b81-ea64-4bde-a772-6880ac0309fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355822051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1355822051
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.976613296
Short name T1131
Test name
Test status
Simulation time 2615745379 ps
CPU time 97.72 seconds
Started Jul 15 06:52:38 PM PDT 24
Finished Jul 15 06:54:16 PM PDT 24
Peak memory 824980 kb
Host smart-4a55a24c-aa12-4f4f-965b-c34c948f24e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976613296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.976613296
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2922685202
Short name T651
Test name
Test status
Simulation time 1904130932 ps
CPU time 0.97 seconds
Started Jul 15 06:52:39 PM PDT 24
Finished Jul 15 06:52:41 PM PDT 24
Peak memory 205256 kb
Host smart-1b43381a-481e-4921-b162-cfaf4997260a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922685202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2922685202
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2002431516
Short name T1620
Test name
Test status
Simulation time 373913454 ps
CPU time 5.97 seconds
Started Jul 15 06:52:37 PM PDT 24
Finished Jul 15 06:52:43 PM PDT 24
Peak memory 243212 kb
Host smart-d6ecb93a-dfb6-46ad-afdc-509fdc9cf702
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002431516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2002431516
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3764348016
Short name T541
Test name
Test status
Simulation time 5185921117 ps
CPU time 161.72 seconds
Started Jul 15 06:52:40 PM PDT 24
Finished Jul 15 06:55:22 PM PDT 24
Peak memory 1475152 kb
Host smart-86805c52-e9d1-4fdc-b046-8990d39c26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764348016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3764348016
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1574349010
Short name T798
Test name
Test status
Simulation time 606699612 ps
CPU time 4.72 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:52:51 PM PDT 24
Peak memory 205552 kb
Host smart-9110d24e-52a6-4490-816f-4b833541609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574349010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1574349010
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.1907331823
Short name T1155
Test name
Test status
Simulation time 30244716 ps
CPU time 0.71 seconds
Started Jul 15 06:52:38 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 205264 kb
Host smart-6e37d926-a774-4ebe-b447-611ab9b362aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907331823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1907331823
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1600546127
Short name T1688
Test name
Test status
Simulation time 7254367152 ps
CPU time 40.92 seconds
Started Jul 15 06:52:37 PM PDT 24
Finished Jul 15 06:53:18 PM PDT 24
Peak memory 205532 kb
Host smart-41091d2f-5497-4139-b045-1da56c3b5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600546127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1600546127
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.2547305624
Short name T1634
Test name
Test status
Simulation time 189142704 ps
CPU time 2.03 seconds
Started Jul 15 06:52:37 PM PDT 24
Finished Jul 15 06:52:39 PM PDT 24
Peak memory 213592 kb
Host smart-46012d0c-eabe-42e3-bd39-c610c2dbc54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547305624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2547305624
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.872259086
Short name T1535
Test name
Test status
Simulation time 1287583538 ps
CPU time 60.62 seconds
Started Jul 15 06:52:38 PM PDT 24
Finished Jul 15 06:53:38 PM PDT 24
Peak memory 311708 kb
Host smart-5a69fab1-ada7-4348-8855-2e83283d4ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872259086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.872259086
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2068001591
Short name T281
Test name
Test status
Simulation time 51754528933 ps
CPU time 1293.71 seconds
Started Jul 15 06:52:47 PM PDT 24
Finished Jul 15 07:14:21 PM PDT 24
Peak memory 1994988 kb
Host smart-0c209a40-b186-45a9-82b4-3e6ebff33438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068001591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2068001591
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.220715565
Short name T793
Test name
Test status
Simulation time 6170234990 ps
CPU time 9.96 seconds
Started Jul 15 06:52:40 PM PDT 24
Finished Jul 15 06:52:50 PM PDT 24
Peak memory 213836 kb
Host smart-0c7b0a27-b4d7-49bb-af55-0a264da234a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220715565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.220715565
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3262946623
Short name T365
Test name
Test status
Simulation time 3768600373 ps
CPU time 5.88 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:52:52 PM PDT 24
Peak memory 218540 kb
Host smart-fd51ab5b-5963-4ee3-bd3e-0ed1b32fe16f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262946623 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3262946623
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.876667424
Short name T1481
Test name
Test status
Simulation time 405020068 ps
CPU time 1.02 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:52:47 PM PDT 24
Peak memory 205572 kb
Host smart-8364b1db-72c1-4945-b4d0-01be302f6404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876667424 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.876667424
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.981188828
Short name T791
Test name
Test status
Simulation time 315738304 ps
CPU time 1.42 seconds
Started Jul 15 06:52:44 PM PDT 24
Finished Jul 15 06:52:46 PM PDT 24
Peak memory 206576 kb
Host smart-84d0d22b-5a24-4b14-9b00-3e09f2894dae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981188828 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.981188828
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.1126387351
Short name T1350
Test name
Test status
Simulation time 1617713013 ps
CPU time 2.15 seconds
Started Jul 15 06:52:43 PM PDT 24
Finished Jul 15 06:52:45 PM PDT 24
Peak memory 205500 kb
Host smart-e31aee23-2c01-485c-ac53-1dd589ac2dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126387351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.1126387351
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.2030595785
Short name T753
Test name
Test status
Simulation time 1504878421 ps
CPU time 1.18 seconds
Started Jul 15 06:52:48 PM PDT 24
Finished Jul 15 06:52:49 PM PDT 24
Peak memory 205452 kb
Host smart-4c8b40c1-ec80-4448-bc77-3a35bdaaa487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030595785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2030595785
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1757169884
Short name T76
Test name
Test status
Simulation time 6481750491 ps
CPU time 5.98 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:52:51 PM PDT 24
Peak memory 219676 kb
Host smart-b128cb69-899a-4520-8ce4-421e0f1451be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757169884 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1757169884
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1345926498
Short name T295
Test name
Test status
Simulation time 19923399966 ps
CPU time 354.66 seconds
Started Jul 15 06:52:43 PM PDT 24
Finished Jul 15 06:58:38 PM PDT 24
Peak memory 3263400 kb
Host smart-5cd951de-3935-4eee-8b46-36f0cca369dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345926498 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1345926498
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.1260907964
Short name T204
Test name
Test status
Simulation time 9245090945 ps
CPU time 3.32 seconds
Started Jul 15 06:52:52 PM PDT 24
Finished Jul 15 06:52:56 PM PDT 24
Peak memory 213888 kb
Host smart-b12111b5-ca6a-4863-bb2e-c7d8373b3384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260907964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.1260907964
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.617346135
Short name T708
Test name
Test status
Simulation time 523367108 ps
CPU time 2.47 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:52:54 PM PDT 24
Peak memory 205584 kb
Host smart-8d45ef4c-5976-4197-84ed-5fc9b3cc7ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617346135 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.617346135
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.234310200
Short name T463
Test name
Test status
Simulation time 1414650236 ps
CPU time 5.94 seconds
Started Jul 15 06:52:44 PM PDT 24
Finished Jul 15 06:52:51 PM PDT 24
Peak memory 222064 kb
Host smart-17c0b101-b6c0-41e0-84e2-f157c135bf6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234310200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_perf.234310200
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.2766433217
Short name T136
Test name
Test status
Simulation time 411698022 ps
CPU time 2.19 seconds
Started Jul 15 06:52:43 PM PDT 24
Finished Jul 15 06:52:46 PM PDT 24
Peak memory 205448 kb
Host smart-c8dde6bb-fceb-40bd-8e3d-58bbaaae6edf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766433217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.2766433217
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1631746625
Short name T933
Test name
Test status
Simulation time 1169268052 ps
CPU time 15.87 seconds
Started Jul 15 06:52:46 PM PDT 24
Finished Jul 15 06:53:03 PM PDT 24
Peak memory 218516 kb
Host smart-a75a6021-ef88-459b-a5c0-5f4018df5e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631746625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1631746625
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3199573544
Short name T664
Test name
Test status
Simulation time 32812347331 ps
CPU time 1032.54 seconds
Started Jul 15 06:52:47 PM PDT 24
Finished Jul 15 07:10:00 PM PDT 24
Peak memory 5360680 kb
Host smart-eb87bd91-068e-47ed-bcb1-fa576fe44518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199573544 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3199573544
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.698141996
Short name T1108
Test name
Test status
Simulation time 5048359320 ps
CPU time 46.04 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:53:32 PM PDT 24
Peak memory 214096 kb
Host smart-d603e4f5-ff78-497f-b573-cb216afd6c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698141996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.698141996
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2248245078
Short name T634
Test name
Test status
Simulation time 16174858444 ps
CPU time 8.43 seconds
Started Jul 15 06:52:47 PM PDT 24
Finished Jul 15 06:52:56 PM PDT 24
Peak memory 206076 kb
Host smart-14db980d-37bc-474c-9964-044842e4498a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248245078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2248245078
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.67162115
Short name T1337
Test name
Test status
Simulation time 4245494900 ps
CPU time 14.27 seconds
Started Jul 15 06:52:46 PM PDT 24
Finished Jul 15 06:53:01 PM PDT 24
Peak memory 387204 kb
Host smart-d7fc861b-4b5f-4a20-a52e-77fb23eb44e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67162115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_stretch.67162115
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2014251433
Short name T633
Test name
Test status
Simulation time 2576021182 ps
CPU time 7.17 seconds
Started Jul 15 06:52:44 PM PDT 24
Finished Jul 15 06:52:52 PM PDT 24
Peak memory 213932 kb
Host smart-58a677b0-c5d5-4f5e-aa47-2e824f26b3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014251433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2014251433
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.363507857
Short name T1329
Test name
Test status
Simulation time 88893159 ps
CPU time 1.98 seconds
Started Jul 15 06:52:45 PM PDT 24
Finished Jul 15 06:52:48 PM PDT 24
Peak memory 205592 kb
Host smart-d5e6821b-32cd-4404-8712-567428895c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363507857 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.363507857
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2161729059
Short name T1406
Test name
Test status
Simulation time 56776741 ps
CPU time 0.62 seconds
Started Jul 15 06:53:08 PM PDT 24
Finished Jul 15 06:53:09 PM PDT 24
Peak memory 204736 kb
Host smart-9d4998ff-2529-4f76-9fff-605585640c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161729059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2161729059
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.933840565
Short name T1330
Test name
Test status
Simulation time 556084936 ps
CPU time 2.51 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:52:55 PM PDT 24
Peak memory 213824 kb
Host smart-da72c983-6d0d-469b-b432-9a5779f495cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933840565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.933840565
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2509991879
Short name T1642
Test name
Test status
Simulation time 369342333 ps
CPU time 18.93 seconds
Started Jul 15 06:52:49 PM PDT 24
Finished Jul 15 06:53:09 PM PDT 24
Peak memory 276560 kb
Host smart-71483cf8-0339-43bc-8074-4a841163279b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509991879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2509991879
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3637293784
Short name T816
Test name
Test status
Simulation time 13945070673 ps
CPU time 128.17 seconds
Started Jul 15 06:52:50 PM PDT 24
Finished Jul 15 06:54:58 PM PDT 24
Peak memory 804960 kb
Host smart-aadfac90-58d4-409a-b3f6-5c4a302c732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637293784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3637293784
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1617283523
Short name T1700
Test name
Test status
Simulation time 6330716506 ps
CPU time 123.51 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:54:55 PM PDT 24
Peak memory 614676 kb
Host smart-166fd5ae-3c9a-4654-ad56-86e7e1b006f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617283523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1617283523
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1661790322
Short name T42
Test name
Test status
Simulation time 102084337 ps
CPU time 0.86 seconds
Started Jul 15 06:52:54 PM PDT 24
Finished Jul 15 06:52:55 PM PDT 24
Peak memory 205264 kb
Host smart-0e6e727d-c2cd-46f8-9be9-84e26ce621fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661790322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1661790322
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4267290633
Short name T732
Test name
Test status
Simulation time 190687845 ps
CPU time 9.09 seconds
Started Jul 15 06:52:52 PM PDT 24
Finished Jul 15 06:53:01 PM PDT 24
Peak memory 205532 kb
Host smart-e6fbc395-bb32-4eeb-9b3f-514e8f1ba79c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267290633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
4267290633
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3198043391
Short name T114
Test name
Test status
Simulation time 21195463055 ps
CPU time 150.13 seconds
Started Jul 15 06:52:52 PM PDT 24
Finished Jul 15 06:55:23 PM PDT 24
Peak memory 1524940 kb
Host smart-ced1d6cc-754d-4598-920b-8f9bd7dd9634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198043391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3198043391
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.581239468
Short name T851
Test name
Test status
Simulation time 1249703207 ps
CPU time 14.46 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:53:11 PM PDT 24
Peak memory 205536 kb
Host smart-54182b8e-3d7e-471e-8429-375a82500c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581239468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.581239468
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.4223960769
Short name T81
Test name
Test status
Simulation time 106911152 ps
CPU time 2.05 seconds
Started Jul 15 06:53:07 PM PDT 24
Finished Jul 15 06:53:10 PM PDT 24
Peak memory 213668 kb
Host smart-8616db40-15a4-4a58-b34b-424568e2b419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223960769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.4223960769
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3247329451
Short name T1504
Test name
Test status
Simulation time 84052870 ps
CPU time 0.67 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:52:53 PM PDT 24
Peak memory 205200 kb
Host smart-873b1c65-b617-418b-933b-5647acb1388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247329451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3247329451
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1110282389
Short name T1534
Test name
Test status
Simulation time 5408633866 ps
CPU time 220.2 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:56:32 PM PDT 24
Peak memory 274544 kb
Host smart-106eca53-e5a8-41e9-888c-d20fb27c45ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110282389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1110282389
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.1103844538
Short name T1160
Test name
Test status
Simulation time 24806986180 ps
CPU time 216.95 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:56:29 PM PDT 24
Peak memory 205544 kb
Host smart-f46cf936-cb7e-449a-9901-bb05af66baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103844538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.1103844538
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1393971672
Short name T896
Test name
Test status
Simulation time 1951448556 ps
CPU time 94.53 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:54:27 PM PDT 24
Peak memory 335228 kb
Host smart-cd6593ce-a50a-49a8-bc01-88f86515f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393971672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1393971672
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1643592475
Short name T299
Test name
Test status
Simulation time 5671349142 ps
CPU time 35.82 seconds
Started Jul 15 06:52:53 PM PDT 24
Finished Jul 15 06:53:29 PM PDT 24
Peak memory 213760 kb
Host smart-477dfc5e-c377-49f3-8f1a-7e53894cd309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643592475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1643592475
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.742139213
Short name T454
Test name
Test status
Simulation time 11608490848 ps
CPU time 4.3 seconds
Started Jul 15 06:52:58 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 213892 kb
Host smart-cae6c7b3-80e3-4f14-bb15-5c1c1cbbfee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742139213 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.742139213
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3057928226
Short name T424
Test name
Test status
Simulation time 263013817 ps
CPU time 1.78 seconds
Started Jul 15 06:52:58 PM PDT 24
Finished Jul 15 06:53:00 PM PDT 24
Peak memory 205500 kb
Host smart-19af7f63-6a6b-474e-9c74-02130bf52c13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057928226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3057928226
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2518370184
Short name T683
Test name
Test status
Simulation time 439295465 ps
CPU time 1.34 seconds
Started Jul 15 06:52:58 PM PDT 24
Finished Jul 15 06:53:00 PM PDT 24
Peak memory 205472 kb
Host smart-9f861454-22bb-4feb-835f-a0e323f5e5ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518370184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2518370184
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2376000734
Short name T1526
Test name
Test status
Simulation time 1339632685 ps
CPU time 2.54 seconds
Started Jul 15 06:52:56 PM PDT 24
Finished Jul 15 06:52:59 PM PDT 24
Peak memory 205616 kb
Host smart-e1209cdd-e353-43a9-ac2c-358acc331187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376000734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2376000734
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.2867473696
Short name T1436
Test name
Test status
Simulation time 123063069 ps
CPU time 1.37 seconds
Started Jul 15 06:52:56 PM PDT 24
Finished Jul 15 06:52:58 PM PDT 24
Peak memory 205488 kb
Host smart-88d083cf-6967-4753-92e5-93d7a7b8d161
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867473696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.2867473696
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1867565510
Short name T585
Test name
Test status
Simulation time 2807395665 ps
CPU time 4.63 seconds
Started Jul 15 06:52:48 PM PDT 24
Finished Jul 15 06:52:53 PM PDT 24
Peak memory 222072 kb
Host smart-332c016f-37ab-4439-9823-3c62f32abade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867565510 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1867565510
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2904483598
Short name T1120
Test name
Test status
Simulation time 8074327960 ps
CPU time 99.78 seconds
Started Jul 15 06:52:50 PM PDT 24
Finished Jul 15 06:54:31 PM PDT 24
Peak memory 1999516 kb
Host smart-81661bc9-7064-4078-b7f3-a35a840eb47e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904483598 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2904483598
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.2158611077
Short name T10
Test name
Test status
Simulation time 1880171284 ps
CPU time 2.7 seconds
Started Jul 15 06:52:55 PM PDT 24
Finished Jul 15 06:52:58 PM PDT 24
Peak memory 213892 kb
Host smart-16930edd-238d-49f6-9d09-df5f87904b0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158611077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.2158611077
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.1053995105
Short name T743
Test name
Test status
Simulation time 1084850184 ps
CPU time 3.13 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:53:01 PM PDT 24
Peak memory 205256 kb
Host smart-1ed6716a-5561-42f7-9656-fd4f543c38cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053995105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1053995105
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_txstretch.714464564
Short name T1719
Test name
Test status
Simulation time 128784241 ps
CPU time 1.4 seconds
Started Jul 15 06:52:58 PM PDT 24
Finished Jul 15 06:53:00 PM PDT 24
Peak memory 222220 kb
Host smart-1c3c050b-edec-4f11-9d96-b02425da698f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714464564 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_nack_txstretch.714464564
Directory /workspace/8.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/8.i2c_target_perf.2007982117
Short name T90
Test name
Test status
Simulation time 1836000379 ps
CPU time 7.02 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:53:05 PM PDT 24
Peak memory 222032 kb
Host smart-5a7d5fa0-b0a3-422d-8ce6-6d2cd6937184
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007982117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.2007982117
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.2017644240
Short name T1075
Test name
Test status
Simulation time 1512174213 ps
CPU time 2.03 seconds
Started Jul 15 06:53:06 PM PDT 24
Finished Jul 15 06:53:09 PM PDT 24
Peak memory 205432 kb
Host smart-c7f97284-0d29-4053-8b17-84543b3ad77d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017644240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.2017644240
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1391307983
Short name T1227
Test name
Test status
Simulation time 4500097276 ps
CPU time 15.64 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:53:07 PM PDT 24
Peak memory 214056 kb
Host smart-41bf99d5-9efa-4bcb-8894-6fcaf56bde1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391307983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1391307983
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.2126315715
Short name T1340
Test name
Test status
Simulation time 24728857664 ps
CPU time 137.77 seconds
Started Jul 15 06:52:59 PM PDT 24
Finished Jul 15 06:55:17 PM PDT 24
Peak memory 1208708 kb
Host smart-100e68ce-af49-44f7-84bf-773556a9fb5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126315715 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.2126315715
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3591883917
Short name T1017
Test name
Test status
Simulation time 1314332896 ps
CPU time 24.3 seconds
Started Jul 15 06:52:50 PM PDT 24
Finished Jul 15 06:53:14 PM PDT 24
Peak memory 221876 kb
Host smart-40384266-4338-4610-9353-f3de3b05b7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591883917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3591883917
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.250348956
Short name T278
Test name
Test status
Simulation time 17562501280 ps
CPU time 10.48 seconds
Started Jul 15 06:52:49 PM PDT 24
Finished Jul 15 06:53:00 PM PDT 24
Peak memory 205676 kb
Host smart-1a4e8827-9724-4814-80d7-685737f53ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250348956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.250348956
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1845395165
Short name T1029
Test name
Test status
Simulation time 2825717824 ps
CPU time 4.56 seconds
Started Jul 15 06:52:51 PM PDT 24
Finished Jul 15 06:52:57 PM PDT 24
Peak memory 255304 kb
Host smart-a8b4acaf-0d40-408f-9c25-9214a5ac9b98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845395165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1845395165
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1086110378
Short name T1233
Test name
Test status
Simulation time 5999927143 ps
CPU time 7.27 seconds
Started Jul 15 06:52:50 PM PDT 24
Finished Jul 15 06:52:57 PM PDT 24
Peak memory 222028 kb
Host smart-8d97f553-1e6f-4a09-88e6-a8c755d1ec8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086110378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1086110378
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.2758745111
Short name T1221
Test name
Test status
Simulation time 184825453 ps
CPU time 2.55 seconds
Started Jul 15 06:53:09 PM PDT 24
Finished Jul 15 06:53:12 PM PDT 24
Peak memory 205632 kb
Host smart-b718de88-6dac-4a33-94f4-a418ca9d65ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758745111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.2758745111
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1718606476
Short name T679
Test name
Test status
Simulation time 18148209 ps
CPU time 0.66 seconds
Started Jul 15 06:53:10 PM PDT 24
Finished Jul 15 06:53:12 PM PDT 24
Peak memory 204892 kb
Host smart-66c5b3e2-90c3-438b-9041-1530f48faa55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718606476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1718606476
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.849849117
Short name T38
Test name
Test status
Simulation time 199254565 ps
CPU time 3.47 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:05 PM PDT 24
Peak memory 221144 kb
Host smart-e2ff25e9-917e-4226-814a-d0b809f5bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849849117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.849849117
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3123123172
Short name T550
Test name
Test status
Simulation time 877053070 ps
CPU time 4.15 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 241816 kb
Host smart-f6348bc7-7c2d-4806-b075-d2f9446c4065
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123123172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3123123172
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1822310516
Short name T346
Test name
Test status
Simulation time 6819710515 ps
CPU time 38.42 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:53:36 PM PDT 24
Peak memory 280132 kb
Host smart-a5d6bf23-e58b-414d-b8a1-ec547b8b6974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822310516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1822310516
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3091397274
Short name T1281
Test name
Test status
Simulation time 12247108517 ps
CPU time 58.17 seconds
Started Jul 15 06:52:56 PM PDT 24
Finished Jul 15 06:53:54 PM PDT 24
Peak memory 554728 kb
Host smart-31b021d9-7d76-46f1-aba8-d001f85fc1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091397274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3091397274
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2104738645
Short name T1133
Test name
Test status
Simulation time 341042370 ps
CPU time 0.98 seconds
Started Jul 15 06:52:58 PM PDT 24
Finished Jul 15 06:53:00 PM PDT 24
Peak memory 205248 kb
Host smart-8046a415-1a8a-4370-a452-592da12e3823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104738645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2104738645
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.557966749
Short name T676
Test name
Test status
Simulation time 927192849 ps
CPU time 11.12 seconds
Started Jul 15 06:53:06 PM PDT 24
Finished Jul 15 06:53:18 PM PDT 24
Peak memory 205504 kb
Host smart-89dfa47f-a091-480f-8573-d7fbcd2fb1f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557966749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.557966749
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.615227918
Short name T84
Test name
Test status
Simulation time 27208300870 ps
CPU time 161.53 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:55:39 PM PDT 24
Peak memory 1396728 kb
Host smart-0d85fd97-fc04-4eff-8fce-3a5f605c07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615227918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.615227918
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.686065360
Short name T1518
Test name
Test status
Simulation time 366165343 ps
CPU time 15.32 seconds
Started Jul 15 06:53:06 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 205536 kb
Host smart-8ffda843-05e8-44e8-b998-febbce7de143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686065360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.686065360
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.2359681218
Short name T1565
Test name
Test status
Simulation time 71797309 ps
CPU time 0.65 seconds
Started Jul 15 06:52:57 PM PDT 24
Finished Jul 15 06:52:59 PM PDT 24
Peak memory 205236 kb
Host smart-ff89713b-379f-45af-b7b6-c88c99609cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359681218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2359681218
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.794884034
Short name T910
Test name
Test status
Simulation time 7017176447 ps
CPU time 131.35 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:55:13 PM PDT 24
Peak memory 205600 kb
Host smart-338722bb-3f15-43f1-8653-4c617ed22c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794884034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.794884034
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.394967844
Short name T891
Test name
Test status
Simulation time 103867505 ps
CPU time 1.2 seconds
Started Jul 15 06:53:00 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 222892 kb
Host smart-227f357c-3a63-4d9b-8b06-b5b557794d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394967844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.394967844
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2088646706
Short name T858
Test name
Test status
Simulation time 26269483957 ps
CPU time 40.52 seconds
Started Jul 15 06:53:06 PM PDT 24
Finished Jul 15 06:53:48 PM PDT 24
Peak memory 359424 kb
Host smart-70238154-f0a6-4165-8368-d814ef57a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088646706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2088646706
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1088194521
Short name T1667
Test name
Test status
Simulation time 1384244064 ps
CPU time 28.92 seconds
Started Jul 15 06:53:00 PM PDT 24
Finished Jul 15 06:53:30 PM PDT 24
Peak memory 213764 kb
Host smart-73c3aad4-825f-47bb-81ab-9354256b0a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088194521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1088194521
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2501027028
Short name T480
Test name
Test status
Simulation time 677944493 ps
CPU time 3.97 seconds
Started Jul 15 06:53:09 PM PDT 24
Finished Jul 15 06:53:13 PM PDT 24
Peak memory 213928 kb
Host smart-c436a800-3c7b-4736-9d49-f2c6aa9a0e6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501027028 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2501027028
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1959625058
Short name T781
Test name
Test status
Simulation time 347984732 ps
CPU time 1.02 seconds
Started Jul 15 06:53:00 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 205404 kb
Host smart-e56ff776-5403-42c0-b53c-e96f74031e00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959625058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1959625058
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3828645959
Short name T79
Test name
Test status
Simulation time 407277573 ps
CPU time 1.37 seconds
Started Jul 15 06:53:00 PM PDT 24
Finished Jul 15 06:53:02 PM PDT 24
Peak memory 205572 kb
Host smart-d05b3de6-bf04-4104-9e11-7c810133516d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828645959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3828645959
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.3490378756
Short name T1036
Test name
Test status
Simulation time 1249759205 ps
CPU time 2.27 seconds
Started Jul 15 06:53:08 PM PDT 24
Finished Jul 15 06:53:11 PM PDT 24
Peak memory 205656 kb
Host smart-b088d82e-0d60-410b-b758-0c9a0464b562
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490378756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.3490378756
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.810218696
Short name T353
Test name
Test status
Simulation time 94393719 ps
CPU time 1.01 seconds
Started Jul 15 06:53:06 PM PDT 24
Finished Jul 15 06:53:08 PM PDT 24
Peak memory 205476 kb
Host smart-a796dd39-b274-49e7-898d-b9bbded4a6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810218696 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.810218696
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3326454743
Short name T522
Test name
Test status
Simulation time 823921100 ps
CPU time 4.91 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:06 PM PDT 24
Peak memory 222032 kb
Host smart-444c3d1f-a9a0-40d5-9271-6309263d2dc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326454743 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3326454743
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3206063853
Short name T469
Test name
Test status
Simulation time 7065337101 ps
CPU time 5.28 seconds
Started Jul 15 06:53:09 PM PDT 24
Finished Jul 15 06:53:15 PM PDT 24
Peak memory 205708 kb
Host smart-def163ca-edeb-45fe-8f05-8ce10362ceb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206063853 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3206063853
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.4182150616
Short name T537
Test name
Test status
Simulation time 1051309976 ps
CPU time 2.6 seconds
Started Jul 15 06:53:10 PM PDT 24
Finished Jul 15 06:53:13 PM PDT 24
Peak memory 213864 kb
Host smart-4dc3d279-389d-4d79-a8ed-9bb8769a18b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182150616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.4182150616
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.901411943
Short name T67
Test name
Test status
Simulation time 1046746932 ps
CPU time 2.89 seconds
Started Jul 15 06:53:08 PM PDT 24
Finished Jul 15 06:53:11 PM PDT 24
Peak memory 205600 kb
Host smart-6549bb57-e69e-4cbc-8e03-30fa129ee5f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901411943 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.901411943
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3907812588
Short name T274
Test name
Test status
Simulation time 832019053 ps
CPU time 5.75 seconds
Started Jul 15 06:53:12 PM PDT 24
Finished Jul 15 06:53:18 PM PDT 24
Peak memory 219332 kb
Host smart-64b5b69a-b2c8-440c-a44f-cb7e75f58e2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907812588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3907812588
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.977328484
Short name T336
Test name
Test status
Simulation time 571977918 ps
CPU time 2.55 seconds
Started Jul 15 06:53:07 PM PDT 24
Finished Jul 15 06:53:10 PM PDT 24
Peak memory 205448 kb
Host smart-f028b3bc-befb-473d-95f1-edb6c3892652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977328484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_smbus_maxlen.977328484
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3278024636
Short name T1371
Test name
Test status
Simulation time 2103148533 ps
CPU time 7 seconds
Started Jul 15 06:53:00 PM PDT 24
Finished Jul 15 06:53:07 PM PDT 24
Peak memory 206260 kb
Host smart-560265f7-50de-402e-8bab-cc7095ee88dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278024636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3278024636
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.634572352
Short name T1004
Test name
Test status
Simulation time 26061452304 ps
CPU time 45.44 seconds
Started Jul 15 06:53:11 PM PDT 24
Finished Jul 15 06:53:57 PM PDT 24
Peak memory 305484 kb
Host smart-d684f564-9a30-4df8-bdaa-85f812a47ba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634572352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_stress_all.634572352
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1173214938
Short name T404
Test name
Test status
Simulation time 1740813544 ps
CPU time 14.42 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:16 PM PDT 24
Peak memory 230184 kb
Host smart-04eaf689-e1de-473e-908a-72a052cacf6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173214938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1173214938
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2879406483
Short name T1591
Test name
Test status
Simulation time 11179618132 ps
CPU time 20.33 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:22 PM PDT 24
Peak memory 205684 kb
Host smart-46fe9b65-844b-41c6-8afe-c89cd9274524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879406483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2879406483
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2800230973
Short name T684
Test name
Test status
Simulation time 981059130 ps
CPU time 3.24 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:04 PM PDT 24
Peak memory 213744 kb
Host smart-43e548d4-7a72-493f-a226-d127670026c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800230973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2800230973
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.4134782946
Short name T593
Test name
Test status
Simulation time 5467837857 ps
CPU time 7.45 seconds
Started Jul 15 06:53:01 PM PDT 24
Finished Jul 15 06:53:09 PM PDT 24
Peak memory 222060 kb
Host smart-d3fd8ead-f98a-4490-ab59-e2d5b098a14d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134782946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.4134782946
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3272372843
Short name T1334
Test name
Test status
Simulation time 165726307 ps
CPU time 3.68 seconds
Started Jul 15 06:53:08 PM PDT 24
Finished Jul 15 06:53:12 PM PDT 24
Peak memory 205572 kb
Host smart-af20d858-9388-49b2-9ba3-56061eeef48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272372843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3272372843
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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