Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	785163	1			T1	2		T2	2		T3	2
all_values[1]	785163	1			T1	2		T2	2		T3	2
all_values[2]	785163	1			T1	2		T2	2		T3	2
all_values[3]	785163	1			T1	2		T2	2		T3	2
all_values[4]	785163	1			T1	2		T2	2		T3	2
all_values[5]	785163	1			T1	2		T2	2		T3	2
all_values[6]	785163	1			T1	2		T2	2		T3	2
all_values[7]	785163	1			T1	2		T2	2		T3	2
all_values[8]	785163	1			T1	2		T2	2		T3	2
all_values[9]	785163	1			T1	2		T2	2		T3	2
all_values[10]	785163	1			T1	2		T2	2		T3	2
all_values[11]	785163	1			T1	2		T2	2		T3	2
all_values[12]	785163	1			T1	2		T2	2		T3	2
all_values[13]	785163	1			T1	2		T2	2		T3	2
all_values[14]	785163	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9701155

1

T1

26

T2

24

T3

26

auto[1]

2076290

1

T1

4

T2

6

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10781117

1

T1

30

T2

30

T3

30

auto[1]

996328

1

T17

119288

T18

269260

T33

68032

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	110270	1			T4	184		T14	3		T15	273
all_values[0]	auto[0]	auto[1]	12076	1			T17	1212		T18	2854		T33	1596
all_values[0]	auto[1]	auto[0]	608459	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	54358	1			T17	7310		T18	15097		T33	4074
all_values[1]	auto[0]	auto[0]	718308	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	66188	1			T17	8518		T18	17888		T33	5667
all_values[1]	auto[1]	auto[0]	443	1			T156	5		T254	2		T255	1
all_values[1]	auto[1]	auto[1]	224	1			T17	3		T18	63		T33	1
all_values[2]	auto[0]	auto[0]	715440	1			T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	69375	1			T17	8514		T18	17948		T33	5668
all_values[2]	auto[1]	auto[0]	188	1			T2	1		T6	1		T178	1
all_values[2]	auto[1]	auto[1]	160	1			T17	1		T18	3		T33	2
all_values[3]	auto[0]	auto[0]	721290	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	63696	1			T17	8516		T18	17947		T40	763
all_values[3]	auto[1]	auto[1]	177	1			T17	6		T18	3		T40	3
all_values[4]	auto[0]	auto[0]	716747	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	68248	1			T17	8518		T18	17948		T33	5667
all_values[4]	auto[1]	auto[0]	18	1			T26	1		T28	1		T256	3
all_values[4]	auto[1]	auto[1]	150	1			T17	3		T18	2		T33	2
all_values[5]	auto[0]	auto[0]	721272	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	63727	1			T17	8520		T18	17945		T34	4
all_values[5]	auto[1]	auto[1]	164	1			T17	2		T18	5		T34	2
all_values[6]	auto[0]	auto[0]	718784	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	66205	1			T17	8513		T18	17944		T33	5666
all_values[6]	auto[1]	auto[1]	174	1			T17	4		T18	7		T33	3
all_values[7]	auto[0]	auto[0]	686404	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	65262	1			T17	8156		T18	17760		T33	5118
all_values[7]	auto[1]	auto[0]	29197	1			T4	331		T14	1		T15	117
all_values[7]	auto[1]	auto[1]	4300	1			T17	365		T18	191		T33	552
all_values[8]	auto[0]	auto[0]	724407	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	60570	1			T17	8518		T18	17948		T34	4
all_values[8]	auto[1]	auto[1]	186	1			T17	4		T18	2		T34	2
all_values[9]	auto[0]	auto[0]	176687	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	13506	1			T17	1501		T18	372		T33	1896
all_values[9]	auto[1]	auto[0]	541804	1			T4	8720		T15	4		T16	1
all_values[9]	auto[1]	auto[1]	53166	1			T17	7020		T18	17579		T33	3772
all_values[10]	auto[0]	auto[0]	718750	1			T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	66254	1			T17	8519		T18	17947		T33	5668
all_values[10]	auto[1]	auto[1]	159	1			T17	1		T18	4		T33	1
all_values[11]	auto[0]	auto[0]	2421	1			T4	9		T14	3		T15	5
all_values[11]	auto[0]	auto[1]	374	1			T18	10		T33	20		T34	3
all_values[11]	auto[1]	auto[0]	721707	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	60661	1			T18	17941		T33	5649		T34	2
all_values[12]	auto[0]	auto[0]	716118	1			T1	2		T2	1		T3	2
all_values[12]	auto[0]	auto[1]	68820	1			T17	8518		T18	17947		T33	5669
all_values[12]	auto[1]	auto[0]	68	1			T2	1		T51	1		T66	1
all_values[12]	auto[1]	auto[1]	157	1			T17	3		T18	4		T33	1
all_values[13]	auto[0]	auto[0]	715610	1			T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	69375	1			T17	8519		T18	17948		T33	5667
all_values[13]	auto[1]	auto[1]	178	1			T17	3		T18	3		T33	3
all_values[14]	auto[0]	auto[0]	716725	1			T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	68246	1			T17	8515		T18	17947		T33	5666
all_values[14]	auto[1]	auto[1]	192	1			T17	6		T18	3		T33	4