Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	785163	1			T1	2		T2	2		T3	2
all_pins[1]	785163	1			T1	2		T2	2		T3	2
all_pins[2]	785163	1			T1	2		T2	2		T3	2
all_pins[3]	785163	1			T1	2		T2	2		T3	2
all_pins[4]	785163	1			T1	2		T2	2		T3	2
all_pins[5]	785163	1			T1	2		T2	2		T3	2
all_pins[6]	785163	1			T1	2		T2	2		T3	2
all_pins[7]	785163	1			T1	2		T2	2		T3	2
all_pins[8]	785163	1			T1	2		T2	2		T3	2
all_pins[9]	785163	1			T1	2		T2	2		T3	2
all_pins[10]	785163	1			T1	2		T2	2		T3	2
all_pins[11]	785163	1			T1	2		T2	2		T3	2
all_pins[12]	785163	1			T1	2		T2	2		T3	2
all_pins[13]	785163	1			T1	2		T2	2		T3	2
all_pins[14]	785163	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9708040	1			T1	26		T2	27		T3	26
values[0x1]	2069405	1			T1	4		T2	3		T3	4
transitions[0x0=>0x1]	2068574	1			T1	4		T2	3		T3	4
transitions[0x1=>0x0]	2067278	1			T1	3		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	126381	1			T2	1		T4	184		T14	3
all_pins[0]	values[0x1]	658782	1			T1	2		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	658249	1			T1	2		T2	1		T3	2
all_pins[0]	transitions[0x1=>0x0]	131	1			T17	1		T18	73		T33	1
all_pins[1]	values[0x0]	784499	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	664	1			T17	1		T18	87		T156	6
all_pins[1]	transitions[0x0=>0x1]	647	1			T18	87		T156	6		T254	3
all_pins[1]	transitions[0x1=>0x0]	119	1			T178	1		T18	2		T262	1
all_pins[2]	values[0x0]	785027	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	136	1			T178	1		T17	1		T18	2
all_pins[2]	transitions[0x0=>0x1]	118	1			T178	1		T18	2		T262	1
all_pins[2]	transitions[0x1=>0x0]	69	1			T17	3		T18	1		T40	1
all_pins[3]	values[0x0]	785076	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	87	1			T17	4		T18	1		T40	2
all_pins[3]	transitions[0x0=>0x1]	70	1			T17	3		T18	1		T40	2
all_pins[3]	transitions[0x1=>0x0]	75	1			T18	1		T26	1		T28	1
all_pins[4]	values[0x0]	785071	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	92	1			T17	1		T18	1		T26	1
all_pins[4]	transitions[0x0=>0x1]	78	1			T17	1		T18	1		T26	1
all_pins[4]	transitions[0x1=>0x0]	68	1			T17	1		T18	2		T34	1
all_pins[5]	values[0x0]	785081	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	82	1			T17	1		T18	2		T34	1
all_pins[5]	transitions[0x0=>0x1]	56	1			T17	1		T18	2		T40	1
all_pins[5]	transitions[0x1=>0x0]	68	1			T17	4		T18	3		T34	3
all_pins[6]	values[0x0]	785069	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	94	1			T17	4		T18	3		T34	4
all_pins[6]	transitions[0x0=>0x1]	75	1			T17	2		T18	3		T34	4
all_pins[6]	transitions[0x1=>0x0]	36117	1			T4	364		T14	1		T15	133
all_pins[7]	values[0x0]	749027	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	36136	1			T4	364		T14	1		T15	133
all_pins[7]	transitions[0x0=>0x1]	36113	1			T4	364		T14	1		T15	133
all_pins[7]	transitions[0x1=>0x0]	66	1			T17	1		T18	1		T40	4
all_pins[8]	values[0x0]	785074	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	89	1			T17	1		T18	1		T40	4
all_pins[8]	transitions[0x0=>0x1]	79	1			T18	1		T40	4		T101	3
all_pins[8]	transitions[0x1=>0x0]	594875	1			T4	8720		T15	4		T16	1
all_pins[9]	values[0x0]	190278	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	594885	1			T4	8720		T15	4		T16	1
all_pins[9]	transitions[0x0=>0x1]	594868	1			T4	8720		T15	4		T16	1
all_pins[9]	transitions[0x1=>0x0]	62	1			T18	2		T33	1		T40	2
all_pins[10]	values[0x0]	785084	1			T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	79	1			T18	4		T33	1		T40	2
all_pins[10]	transitions[0x0=>0x1]	57	1			T18	2		T33	1		T40	2
all_pins[10]	transitions[0x1=>0x0]	777927	1			T1	2		T2	1		T3	2
all_pins[11]	values[0x0]	7214	1			T2	1		T4	9		T6	1
all_pins[11]	values[0x1]	777949	1			T1	2		T2	1		T3	2
all_pins[11]	transitions[0x0=>0x1]	777910	1			T1	2		T2	1		T3	2
all_pins[11]	transitions[0x1=>0x0]	108	1			T2	1		T17	1		T18	2
all_pins[12]	values[0x0]	785016	1			T1	2		T2	1		T3	2
all_pins[12]	values[0x1]	147	1			T2	1		T17	3		T18	3
all_pins[12]	transitions[0x0=>0x1]	126	1			T2	1		T17	2		T18	3
all_pins[12]	transitions[0x1=>0x0]	73	1			T17	1		T18	1		T33	3
all_pins[13]	values[0x0]	785069	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	94	1			T17	2		T18	1		T33	3
all_pins[13]	transitions[0x0=>0x1]	82	1			T17	2		T18	1		T33	3
all_pins[13]	transitions[0x1=>0x0]	77	1			T17	4		T40	2		T41	1
all_pins[14]	values[0x0]	785074	1			T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	89	1			T17	4		T40	2		T101	1
all_pins[14]	transitions[0x0=>0x1]	46	1			T17	4		T40	1		T101	1
all_pins[14]	transitions[0x1=>0x0]	657443	1			T1	1		T2	1		T3	1