Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	389	1			T17	8		T18	7		T33	4
all_values[1]	389	1			T17	8		T18	7		T33	4
all_values[2]	389	1			T17	8		T18	7		T33	4
all_values[3]	389	1			T17	8		T18	7		T33	4
all_values[4]	389	1			T17	8		T18	7		T33	4
all_values[5]	389	1			T17	8		T18	7		T33	4
all_values[6]	389	1			T17	8		T18	7		T33	4
all_values[7]	389	1			T17	8		T18	7		T33	4
all_values[8]	389	1			T17	8		T18	7		T33	4
all_values[9]	389	1			T17	8		T18	7		T33	4
all_values[10]	389	1			T17	8		T18	7		T33	4
all_values[11]	389	1			T17	8		T18	7		T33	4
all_values[12]	389	1			T17	8		T18	7		T33	4
all_values[13]	389	1			T17	8		T18	7		T33	4
all_values[14]	389	1			T17	8		T18	7		T33	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3076

1

T17

56

T18

45

T33

35

auto[1]

2759

1

T17

64

T18

60

T33

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963

1

T17

26

T18

5

T33

20

auto[1]

4872

1

T17

94

T18

100

T33

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3414

1

T17

77

T18

62

T33

42

auto[1]

2421

1

T17

43

T18

43

T33

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1			T34	1		T40	1		T41	3
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T17	3		T18	4		T33	2
all_values[0]	auto[0]	auto[1]	auto[0]	16	1			T41	1		T263	2		T120	1
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T17	1		T18	1		T40	1
all_values[0]	auto[1]	auto[0]	auto[1]	84	1			T17	3		T18	1		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T17	1		T18	1		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	44	1			T17	1		T33	2		T34	2
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T17	2		T40	2		T101	2
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T34	2		T41	1		T119	1
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T17	2		T18	4		T33	1
all_values[1]	auto[1]	auto[0]	auto[1]	92	1			T17	2		T40	2		T101	1
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T17	1		T18	3		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T17	4		T40	1		T101	1
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T18	3		T40	2		T41	2
all_values[2]	auto[0]	auto[1]	auto[0]	28	1			T17	2		T34	1		T40	1
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T17	1		T18	1		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	84	1			T18	1		T33	1		T34	1
all_values[2]	auto[1]	auto[1]	auto[1]	76	1			T17	1		T18	2		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T33	2		T34	3		T40	1
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T17	1		T18	1		T101	1
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T18	1		T33	2		T34	1
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T17	2		T18	3		T40	3
all_values[3]	auto[1]	auto[0]	auto[1]	77	1			T17	2		T18	2		T40	1
all_values[3]	auto[1]	auto[1]	auto[1]	81	1			T17	3		T40	1		T119	4
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T33	1		T34	1		T40	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T17	2		T18	1		T34	2
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T17	1		T18	1		T263	1
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T17	2		T18	3		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	82	1			T17	2		T33	1		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T17	1		T18	2		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	28	1			T264	1		T265	1		T266	1
all_values[5]	auto[0]	auto[0]	auto[1]	91	1			T17	2		T18	1		T40	1
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T18	1		T33	4		T101	1
all_values[5]	auto[0]	auto[1]	auto[1]	89	1			T17	3		T18	1		T34	3
all_values[5]	auto[1]	auto[0]	auto[1]	88	1			T17	2		T18	3		T34	1
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T17	1		T18	1		T40	1
all_values[6]	auto[0]	auto[0]	auto[0]	58	1			T17	3		T33	1		T40	2
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T18	1		T33	2		T101	2
all_values[6]	auto[0]	auto[1]	auto[0]	39	1			T17	1		T40	1		T41	1
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T18	2		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T18	2		T33	1		T40	1
all_values[6]	auto[1]	auto[1]	auto[1]	76	1			T17	3		T18	2		T34	3
all_values[7]	auto[0]	auto[0]	auto[0]	29	1			T40	1		T264	2		T267	1
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T18	3		T34	2		T40	1
all_values[7]	auto[0]	auto[1]	auto[0]	21	1			T17	1		T119	1		T268	1
all_values[7]	auto[0]	auto[1]	auto[1]	92	1			T17	4		T18	3		T33	3
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T17	1		T33	1		T34	1
all_values[7]	auto[1]	auto[1]	auto[1]	80	1			T17	2		T18	1		T40	1
all_values[8]	auto[0]	auto[0]	auto[0]	40	1			T33	4		T40	1		T41	3
all_values[8]	auto[0]	auto[0]	auto[1]	94	1			T17	3		T18	2		T34	2
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T18	1		T41	1		T119	2
all_values[8]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T18	2		T40	2
all_values[8]	auto[1]	auto[0]	auto[1]	87	1			T17	3		T18	1		T34	2
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T17	1		T18	1		T40	2
all_values[9]	auto[0]	auto[0]	auto[0]	50	1			T41	2		T119	1		T222	2
all_values[9]	auto[0]	auto[0]	auto[1]	81	1			T17	2		T33	1		T34	2
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T17	1		T33	2		T101	1
all_values[9]	auto[0]	auto[1]	auto[1]	74	1			T18	2		T34	1		T101	4
all_values[9]	auto[1]	auto[0]	auto[1]	88	1			T17	1		T18	2		T33	1
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T17	4		T18	3		T34	1
all_values[10]	auto[0]	auto[0]	auto[0]	36	1			T17	1		T40	1		T41	3
all_values[10]	auto[0]	auto[0]	auto[1]	84	1			T17	4		T33	2		T34	3
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T17	1		T33	1		T41	1
all_values[10]	auto[0]	auto[1]	auto[1]	78	1			T17	1		T18	3		T40	2
all_values[10]	auto[1]	auto[0]	auto[1]	81	1			T34	1		T40	2		T101	3
all_values[10]	auto[1]	auto[1]	auto[1]	78	1			T17	1		T18	4		T33	1
all_values[11]	auto[0]	auto[0]	auto[0]	32	1			T17	3		T34	1		T40	2
all_values[11]	auto[0]	auto[0]	auto[1]	76	1			T18	3		T33	2		T34	1
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T17	5		T33	1		T264	1
all_values[11]	auto[0]	auto[1]	auto[1]	93	1			T40	1		T101	2		T119	2
all_values[11]	auto[1]	auto[0]	auto[1]	79	1			T18	1		T33	1		T34	2
all_values[11]	auto[1]	auto[1]	auto[1]	80	1			T18	3		T40	1		T101	3
all_values[12]	auto[0]	auto[0]	auto[0]	40	1			T17	1		T41	1		T119	1
all_values[12]	auto[0]	auto[0]	auto[1]	86	1			T17	1		T18	2		T33	3
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T41	1		T119	1		T267	2
all_values[12]	auto[0]	auto[1]	auto[1]	77	1			T17	3		T18	1		T34	2
all_values[12]	auto[1]	auto[0]	auto[1]	87	1			T18	1		T33	1		T40	1
all_values[12]	auto[1]	auto[1]	auto[1]	70	1			T17	3		T18	3		T34	1
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T41	2		T263	3		T222	1
all_values[13]	auto[0]	auto[0]	auto[1]	80	1			T17	3		T18	4		T33	1
all_values[13]	auto[0]	auto[1]	auto[0]	25	1			T263	1		T264	1		T266	1
all_values[13]	auto[0]	auto[1]	auto[1]	80	1			T17	3		T18	2		T33	1
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T17	1		T34	1		T40	2
all_values[13]	auto[1]	auto[1]	auto[1]	83	1			T17	1		T18	1		T33	2
all_values[14]	auto[0]	auto[0]	auto[0]	20	1			T17	1		T40	1		T267	1
all_values[14]	auto[0]	auto[0]	auto[1]	114	1			T17	1		T18	4		T33	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T18	1		T34	1		T268	4
all_values[14]	auto[0]	auto[1]	auto[1]	63	1			T17	3		T34	2		T40	2
all_values[14]	auto[1]	auto[0]	auto[1]	102	1			T17	1		T18	2		T33	3
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T17	2		T40	1		T41	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal