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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.29 97.21 89.46 97.22 72.02 94.26 98.44 90.42


Total test records in report: 1850
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T1769 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1552681291 Jul 16 05:38:39 PM PDT 24 Jul 16 05:38:40 PM PDT 24 33900759 ps
T117 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1582385947 Jul 16 05:38:18 PM PDT 24 Jul 16 05:38:21 PM PDT 24 25790905 ps
T1770 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1014243421 Jul 16 05:38:38 PM PDT 24 Jul 16 05:38:40 PM PDT 24 45329806 ps
T1771 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3648129818 Jul 16 05:38:50 PM PDT 24 Jul 16 05:38:52 PM PDT 24 40880405 ps
T118 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2412232891 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 127923769 ps
T1772 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2466160964 Jul 16 05:38:39 PM PDT 24 Jul 16 05:38:42 PM PDT 24 58753173 ps
T1773 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.234626722 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 51697927 ps
T1774 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2860226186 Jul 16 05:38:35 PM PDT 24 Jul 16 05:38:37 PM PDT 24 29552968 ps
T200 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3921490502 Jul 16 05:38:30 PM PDT 24 Jul 16 05:38:32 PM PDT 24 411660214 ps
T187 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2322393488 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:50 PM PDT 24 317836444 ps
T207 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3958398330 Jul 16 05:38:18 PM PDT 24 Jul 16 05:38:22 PM PDT 24 65900253 ps
T1775 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.369575090 Jul 16 05:38:30 PM PDT 24 Jul 16 05:38:31 PM PDT 24 41894556 ps
T1776 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2402656888 Jul 16 05:38:41 PM PDT 24 Jul 16 05:38:43 PM PDT 24 60424279 ps
T201 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2843563077 Jul 16 05:38:30 PM PDT 24 Jul 16 05:38:32 PM PDT 24 137375851 ps
T1777 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2002357038 Jul 16 05:38:40 PM PDT 24 Jul 16 05:38:41 PM PDT 24 67285431 ps
T1778 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2750441009 Jul 16 05:38:29 PM PDT 24 Jul 16 05:38:31 PM PDT 24 96509330 ps
T1779 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2777416410 Jul 16 05:38:40 PM PDT 24 Jul 16 05:38:42 PM PDT 24 423589880 ps
T1780 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1074128662 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 15662987 ps
T1781 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1716990759 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:50 PM PDT 24 15338893 ps
T1782 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1033628048 Jul 16 05:38:50 PM PDT 24 Jul 16 05:38:52 PM PDT 24 28149701 ps
T1783 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3436330386 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:50 PM PDT 24 332579837 ps
T202 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.255378434 Jul 16 05:38:36 PM PDT 24 Jul 16 05:38:38 PM PDT 24 39597388 ps
T1784 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2412638555 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:49 PM PDT 24 29617057 ps
T1785 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.802089171 Jul 16 05:38:30 PM PDT 24 Jul 16 05:38:32 PM PDT 24 376276847 ps
T203 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1685394207 Jul 16 05:38:18 PM PDT 24 Jul 16 05:38:20 PM PDT 24 17275422 ps
T1786 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.76854465 Jul 16 05:38:15 PM PDT 24 Jul 16 05:38:18 PM PDT 24 36082117 ps
T204 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2875685076 Jul 16 05:38:17 PM PDT 24 Jul 16 05:38:19 PM PDT 24 54493054 ps
T1787 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1230302895 Jul 16 05:38:36 PM PDT 24 Jul 16 05:38:37 PM PDT 24 77885717 ps
T1788 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2123477477 Jul 16 05:38:45 PM PDT 24 Jul 16 05:38:46 PM PDT 24 25243373 ps
T1789 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.778088904 Jul 16 05:38:48 PM PDT 24 Jul 16 05:38:51 PM PDT 24 121258298 ps
T1790 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1768958464 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:48 PM PDT 24 16399637 ps
T1791 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.73922321 Jul 16 05:38:35 PM PDT 24 Jul 16 05:38:36 PM PDT 24 26462217 ps
T1792 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3726981542 Jul 16 05:38:59 PM PDT 24 Jul 16 05:39:01 PM PDT 24 16278640 ps
T205 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3819171041 Jul 16 05:38:42 PM PDT 24 Jul 16 05:38:43 PM PDT 24 26279137 ps
T1793 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2974562312 Jul 16 05:38:46 PM PDT 24 Jul 16 05:38:47 PM PDT 24 20074632 ps
T1794 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.749757078 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:35 PM PDT 24 271964247 ps
T206 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.179249594 Jul 16 05:38:36 PM PDT 24 Jul 16 05:38:38 PM PDT 24 64892047 ps
T1795 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2534726509 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:35 PM PDT 24 79184190 ps
T1796 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3067312433 Jul 16 05:38:45 PM PDT 24 Jul 16 05:38:46 PM PDT 24 22075920 ps
T1797 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2672994829 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 71822248 ps
T1798 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.843047118 Jul 16 05:38:38 PM PDT 24 Jul 16 05:38:39 PM PDT 24 69844789 ps
T1799 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1496541847 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:50 PM PDT 24 37257482 ps
T1800 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3341830484 Jul 16 05:38:45 PM PDT 24 Jul 16 05:38:46 PM PDT 24 108057651 ps
T208 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1238597751 Jul 16 05:38:33 PM PDT 24 Jul 16 05:38:39 PM PDT 24 541667181 ps
T1801 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2528150969 Jul 16 05:38:38 PM PDT 24 Jul 16 05:38:41 PM PDT 24 73699332 ps
T1802 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2685095843 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:33 PM PDT 24 184492618 ps
T1803 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1470219758 Jul 16 05:38:49 PM PDT 24 Jul 16 05:38:52 PM PDT 24 46067069 ps
T1804 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2403492793 Jul 16 05:38:16 PM PDT 24 Jul 16 05:38:19 PM PDT 24 50270008 ps
T1805 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3919367313 Jul 16 05:38:35 PM PDT 24 Jul 16 05:38:36 PM PDT 24 30279144 ps
T185 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1938543099 Jul 16 05:38:44 PM PDT 24 Jul 16 05:38:46 PM PDT 24 251325942 ps
T1806 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3232380000 Jul 16 05:38:42 PM PDT 24 Jul 16 05:38:43 PM PDT 24 101793092 ps
T1807 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3853378695 Jul 16 05:38:17 PM PDT 24 Jul 16 05:38:20 PM PDT 24 52039762 ps
T1808 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3106685522 Jul 16 05:38:44 PM PDT 24 Jul 16 05:38:46 PM PDT 24 47015744 ps
T1809 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2059877718 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:32 PM PDT 24 59442836 ps
T190 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3671848865 Jul 16 05:38:34 PM PDT 24 Jul 16 05:38:37 PM PDT 24 184091775 ps
T1810 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3315318990 Jul 16 05:38:38 PM PDT 24 Jul 16 05:38:40 PM PDT 24 36513660 ps
T1811 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1944990995 Jul 16 05:38:36 PM PDT 24 Jul 16 05:38:37 PM PDT 24 26804332 ps
T1812 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2892792286 Jul 16 05:38:50 PM PDT 24 Jul 16 05:38:52 PM PDT 24 57810984 ps
T1813 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4156650882 Jul 16 05:38:34 PM PDT 24 Jul 16 05:38:38 PM PDT 24 240612569 ps
T1814 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1072094985 Jul 16 05:38:47 PM PDT 24 Jul 16 05:38:49 PM PDT 24 93982387 ps
T1815 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2010568416 Jul 16 05:38:37 PM PDT 24 Jul 16 05:38:41 PM PDT 24 263005140 ps
T1816 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3093088933 Jul 16 05:38:29 PM PDT 24 Jul 16 05:38:30 PM PDT 24 36286534 ps
T1817 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3897116872 Jul 16 05:38:30 PM PDT 24 Jul 16 05:38:32 PM PDT 24 879649654 ps
T1818 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1382943502 Jul 16 05:38:48 PM PDT 24 Jul 16 05:38:51 PM PDT 24 18446765 ps
T1819 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1395139751 Jul 16 05:38:36 PM PDT 24 Jul 16 05:38:38 PM PDT 24 109897392 ps
T1820 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.181935687 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:35 PM PDT 24 31741153 ps
T1821 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.4232092711 Jul 16 05:38:50 PM PDT 24 Jul 16 05:38:53 PM PDT 24 250398233 ps
T1822 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.290937733 Jul 16 05:38:20 PM PDT 24 Jul 16 05:38:23 PM PDT 24 45410089 ps
T1823 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1481766972 Jul 16 05:38:46 PM PDT 24 Jul 16 05:38:48 PM PDT 24 155641085 ps
T1824 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1194305478 Jul 16 05:38:57 PM PDT 24 Jul 16 05:38:58 PM PDT 24 20659108 ps
T1825 /workspace/coverage/cover_reg_top/26.i2c_intr_test.4027299822 Jul 16 05:38:46 PM PDT 24 Jul 16 05:38:47 PM PDT 24 42400878 ps
T1826 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3035537689 Jul 16 05:38:18 PM PDT 24 Jul 16 05:38:20 PM PDT 24 132572863 ps
T1827 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3467875681 Jul 16 05:38:48 PM PDT 24 Jul 16 05:38:51 PM PDT 24 76170842 ps
T1828 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4005303774 Jul 16 05:38:29 PM PDT 24 Jul 16 05:38:30 PM PDT 24 142135184 ps
T1829 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4035325746 Jul 16 05:38:37 PM PDT 24 Jul 16 05:38:39 PM PDT 24 46539971 ps
T1830 /workspace/coverage/cover_reg_top/15.i2c_intr_test.612986481 Jul 16 05:38:49 PM PDT 24 Jul 16 05:38:52 PM PDT 24 26998085 ps
T1831 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2405596740 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:33 PM PDT 24 93311924 ps
T1832 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1811437626 Jul 16 05:38:45 PM PDT 24 Jul 16 05:38:47 PM PDT 24 65005376 ps
T1833 /workspace/coverage/cover_reg_top/23.i2c_intr_test.4267066798 Jul 16 05:38:49 PM PDT 24 Jul 16 05:38:51 PM PDT 24 58460700 ps
T1834 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.286980773 Jul 16 05:38:33 PM PDT 24 Jul 16 05:38:35 PM PDT 24 183191908 ps
T1835 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.224108728 Jul 16 05:38:33 PM PDT 24 Jul 16 05:38:37 PM PDT 24 517049331 ps
T1836 /workspace/coverage/cover_reg_top/31.i2c_intr_test.4133182493 Jul 16 05:38:48 PM PDT 24 Jul 16 05:38:51 PM PDT 24 24739957 ps
T1837 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3659657955 Jul 16 05:38:19 PM PDT 24 Jul 16 05:38:21 PM PDT 24 55971473 ps
T1838 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1925680380 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:33 PM PDT 24 52587269 ps
T1839 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1431744009 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 213096730 ps
T1840 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2740474066 Jul 16 05:38:59 PM PDT 24 Jul 16 05:39:01 PM PDT 24 17171431 ps
T1841 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3078526532 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:34 PM PDT 24 246479893 ps
T1842 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3872528895 Jul 16 05:38:35 PM PDT 24 Jul 16 05:38:37 PM PDT 24 58608128 ps
T209 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3783731697 Jul 16 05:38:33 PM PDT 24 Jul 16 05:38:35 PM PDT 24 17486919 ps
T1843 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2565333789 Jul 16 05:38:44 PM PDT 24 Jul 16 05:38:46 PM PDT 24 63240301 ps
T188 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2111491981 Jul 16 05:38:41 PM PDT 24 Jul 16 05:38:43 PM PDT 24 77324607 ps
T1844 /workspace/coverage/cover_reg_top/2.i2c_intr_test.585782404 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:32 PM PDT 24 43004275 ps
T189 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.748132284 Jul 16 05:38:32 PM PDT 24 Jul 16 05:38:35 PM PDT 24 85264765 ps
T210 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1628837226 Jul 16 05:38:15 PM PDT 24 Jul 16 05:38:18 PM PDT 24 650318138 ps
T1845 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3607126351 Jul 16 05:38:46 PM PDT 24 Jul 16 05:38:49 PM PDT 24 104385895 ps
T1846 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2423886457 Jul 16 05:38:48 PM PDT 24 Jul 16 05:38:50 PM PDT 24 19286558 ps
T1847 /workspace/coverage/cover_reg_top/13.i2c_intr_test.59252379 Jul 16 05:38:46 PM PDT 24 Jul 16 05:38:48 PM PDT 24 58190126 ps
T1848 /workspace/coverage/cover_reg_top/24.i2c_intr_test.270965405 Jul 16 05:38:50 PM PDT 24 Jul 16 05:38:52 PM PDT 24 65968572 ps
T1849 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2870015527 Jul 16 05:38:58 PM PDT 24 Jul 16 05:38:59 PM PDT 24 79315062 ps
T1850 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1525088234 Jul 16 05:38:31 PM PDT 24 Jul 16 05:38:33 PM PDT 24 37559713 ps

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.527472662
Short name T4
Test name
Test status
Simulation time 9496204374 ps
CPU time 23.2 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:27 PM PDT 24
Peak memory 230016 kb
Host smart-dc798ff6-6402-45f6-9697-44e85abc3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527472662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.527472662
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3662809382
Short name T3
Test name
Test status
Simulation time 2717748479 ps
CPU time 7.45 seconds
Started Jul 16 05:28:40 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 216912 kb
Host smart-ba88940d-a3dc-4453-b0d7-ca38c0192aca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662809382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3662809382
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3883948689
Short name T17
Test name
Test status
Simulation time 39759048453 ps
CPU time 709.24 seconds
Started Jul 16 05:26:20 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 959016 kb
Host smart-2a55b633-ad4a-4252-8660-2a9b43419872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883948689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3883948689
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.873488417
Short name T47
Test name
Test status
Simulation time 2455843461 ps
CPU time 11.23 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 214232 kb
Host smart-0d26491d-3bfc-4cfa-b006-aeee707c9fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873488417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.873488417
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1791325690
Short name T94
Test name
Test status
Simulation time 313151427 ps
CPU time 1.51 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 204644 kb
Host smart-97c30a0f-b885-4e4c-8f83-5e7020ae55b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791325690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1791325690
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.4145992308
Short name T33
Test name
Test status
Simulation time 40735005908 ps
CPU time 797.92 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:39:09 PM PDT 24
Peak memory 2751640 kb
Host smart-069898ce-e2e7-4234-bdd5-1f3d3164bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145992308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.4145992308
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.4190748610
Short name T48
Test name
Test status
Simulation time 142233015 ps
CPU time 1.76 seconds
Started Jul 16 05:32:07 PM PDT 24
Finished Jul 16 05:32:10 PM PDT 24
Peak memory 222604 kb
Host smart-64f5424e-8ff4-40d6-be18-990c1435a0cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190748610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_txstretch.4190748610
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1086471362
Short name T147
Test name
Test status
Simulation time 119804678 ps
CPU time 1.04 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 223920 kb
Host smart-a0599f68-6fe1-46a5-b1d5-e83c9bb04666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086471362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1086471362
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/14.i2c_host_override.974122515
Short name T86
Test name
Test status
Simulation time 88334785 ps
CPU time 0.66 seconds
Started Jul 16 05:23:42 PM PDT 24
Finished Jul 16 05:23:43 PM PDT 24
Peak memory 205108 kb
Host smart-b3cbbbb0-eeec-45e5-b9ca-be70c0465401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974122515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.974122515
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3937715383
Short name T26
Test name
Test status
Simulation time 582852700 ps
CPU time 8.67 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 205472 kb
Host smart-83d9a237-6b29-4406-9991-d191a3ee2f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937715383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3937715383
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.1971091540
Short name T55
Test name
Test status
Simulation time 41384316418 ps
CPU time 844.58 seconds
Started Jul 16 05:25:17 PM PDT 24
Finished Jul 16 05:39:23 PM PDT 24
Peak memory 4291700 kb
Host smart-f9c3d997-1806-4dbf-9342-f4307d9bdf68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971091540 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.1971091540
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.1744093701
Short name T57
Test name
Test status
Simulation time 2273995095 ps
CPU time 2.66 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:06 PM PDT 24
Peak memory 205692 kb
Host smart-3d00d91b-c2d7-41ae-8079-e1a1bef24321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744093701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.1744093701
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.4177317043
Short name T38
Test name
Test status
Simulation time 619619764 ps
CPU time 1.08 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:07 PM PDT 24
Peak memory 205112 kb
Host smart-e86b4c5c-72d0-43db-a635-8cc795152cd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177317043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.4177317043
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3952851346
Short name T199
Test name
Test status
Simulation time 51668841 ps
CPU time 0.8 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204372 kb
Host smart-69fa529d-8855-4702-9f4c-8f0d3bcd0009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952851346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3952851346
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.955157198
Short name T18
Test name
Test status
Simulation time 33110368861 ps
CPU time 1839.12 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:58:01 PM PDT 24
Peak memory 1949920 kb
Host smart-9a5a8dfd-d3e0-4b7f-a023-b9f375f025a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955157198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.955157198
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.114799623
Short name T89
Test name
Test status
Simulation time 523609150 ps
CPU time 2.16 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204608 kb
Host smart-cc3e1da4-df0e-4463-8ab9-7dc9894cc28c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114799623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.114799623
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.1733990551
Short name T144
Test name
Test status
Simulation time 521901814 ps
CPU time 2.69 seconds
Started Jul 16 05:23:07 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 205532 kb
Host smart-cab27654-4902-4264-8b5d-cf356403bb5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733990551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.1733990551
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.131444768
Short name T59
Test name
Test status
Simulation time 2569215917 ps
CPU time 3.94 seconds
Started Jul 16 05:21:58 PM PDT 24
Finished Jul 16 05:22:02 PM PDT 24
Peak memory 219148 kb
Host smart-8f31eaaa-9425-4336-8539-90cf1c7d3207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131444768 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.131444768
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.2921729565
Short name T63
Test name
Test status
Simulation time 519827637 ps
CPU time 2.89 seconds
Started Jul 16 05:27:07 PM PDT 24
Finished Jul 16 05:27:10 PM PDT 24
Peak memory 213860 kb
Host smart-fbd4772b-40eb-40bc-a6ba-edc053f6d06f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921729565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.2921729565
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1537921278
Short name T41
Test name
Test status
Simulation time 29530069640 ps
CPU time 3435.92 seconds
Started Jul 16 05:33:54 PM PDT 24
Finished Jul 16 06:31:11 PM PDT 24
Peak memory 6019980 kb
Host smart-4e34da86-7834-43dc-bc07-346c93d246d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537921278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1537921278
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2028714397
Short name T234
Test name
Test status
Simulation time 679239441 ps
CPU time 8.86 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:24:02 PM PDT 24
Peak memory 205504 kb
Host smart-68a06cb2-6e4e-4640-9296-18350e325f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028714397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2028714397
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3945405990
Short name T159
Test name
Test status
Simulation time 122978627 ps
CPU time 7.19 seconds
Started Jul 16 05:29:03 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 226600 kb
Host smart-b2363422-1b66-417d-a98e-adeb341929e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945405990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3945405990
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_target_perf.4124140872
Short name T9
Test name
Test status
Simulation time 1929270471 ps
CPU time 5.85 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:42 PM PDT 24
Peak memory 221924 kb
Host smart-74443fbc-390b-47f9-8412-671581ec3699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124140872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.4124140872
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2118628184
Short name T264
Test name
Test status
Simulation time 57278166333 ps
CPU time 951.71 seconds
Started Jul 16 05:25:25 PM PDT 24
Finished Jul 16 05:41:17 PM PDT 24
Peak memory 2225316 kb
Host smart-4867e434-404e-47d0-8b4e-4d7d4f08ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118628184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2118628184
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1634997509
Short name T309
Test name
Test status
Simulation time 57351501 ps
CPU time 0.67 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 204944 kb
Host smart-163badca-b605-4e69-a035-890c3bad33b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634997509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1634997509
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.4068007364
Short name T225
Test name
Test status
Simulation time 412269489 ps
CPU time 1.2 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 205264 kb
Host smart-789ad0b1-4ce2-4aae-903f-974d8e6fbd7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068007364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.4068007364
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3442400770
Short name T231
Test name
Test status
Simulation time 504267100 ps
CPU time 19.16 seconds
Started Jul 16 05:25:25 PM PDT 24
Finished Jul 16 05:25:44 PM PDT 24
Peak memory 205544 kb
Host smart-a9b89ae3-ebfa-41bc-b63d-30dd23fbe892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442400770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3442400770
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2777416410
Short name T1779
Test name
Test status
Simulation time 423589880 ps
CPU time 1.63 seconds
Started Jul 16 05:38:40 PM PDT 24
Finished Jul 16 05:38:42 PM PDT 24
Peak memory 204756 kb
Host smart-26c5ea4f-7da4-4c51-9e95-a3312ce80866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777416410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2777416410
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4229175383
Short name T102
Test name
Test status
Simulation time 14644638403 ps
CPU time 83.31 seconds
Started Jul 16 05:24:38 PM PDT 24
Finished Jul 16 05:26:02 PM PDT 24
Peak memory 1083712 kb
Host smart-008104ef-e321-470f-9f8a-37763a912a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229175383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4229175383
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1952863213
Short name T246
Test name
Test status
Simulation time 374573643 ps
CPU time 3.02 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 215092 kb
Host smart-6dcbbcdc-f57c-45c4-947e-51b52c5694a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952863213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1952863213
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.932681658
Short name T20
Test name
Test status
Simulation time 2873464898 ps
CPU time 5.69 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:34 PM PDT 24
Peak memory 270872 kb
Host smart-2936e7b7-2a3a-4a22-9927-7c6cb1eac196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932681658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.932681658
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1628837226
Short name T210
Test name
Test status
Simulation time 650318138 ps
CPU time 1.93 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 204580 kb
Host smart-499577f1-7ca7-468e-a612-c64cb2d6ef53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628837226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1628837226
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1642390369
Short name T76
Test name
Test status
Simulation time 2215193223 ps
CPU time 38.45 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:24:32 PM PDT 24
Peak memory 213844 kb
Host smart-b407d85b-4079-4069-9c7f-4cfc3173b94b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642390369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1642390369
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.75992381
Short name T182
Test name
Test status
Simulation time 296568334 ps
CPU time 2.09 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204624 kb
Host smart-cefd544b-3352-4a35-a3da-3e8228b12e51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75992381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.75992381
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.620188720
Short name T222
Test name
Test status
Simulation time 76566806614 ps
CPU time 1622.32 seconds
Started Jul 16 05:36:39 PM PDT 24
Finished Jul 16 06:03:43 PM PDT 24
Peak memory 2423716 kb
Host smart-fd84223a-1b3a-4b3c-8ec4-8449f629f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620188720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.620188720
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_override.3281004668
Short name T249
Test name
Test status
Simulation time 23819568 ps
CPU time 0.63 seconds
Started Jul 16 05:25:38 PM PDT 24
Finished Jul 16 05:25:39 PM PDT 24
Peak memory 205176 kb
Host smart-ce178444-a754-4ddb-9a51-ea782f6e48f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281004668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3281004668
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.4100557487
Short name T67
Test name
Test status
Simulation time 6661196043 ps
CPU time 17.83 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:27:26 PM PDT 24
Peak memory 229984 kb
Host smart-3843b209-1ecc-430e-9da5-8fd6cb19429c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100557487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.4100557487
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1518387280
Short name T218
Test name
Test status
Simulation time 211563394 ps
CPU time 1.6 seconds
Started Jul 16 05:28:11 PM PDT 24
Finished Jul 16 05:28:13 PM PDT 24
Peak memory 205472 kb
Host smart-425c1397-321c-4fbd-9d07-66d2acd05738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518387280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1518387280
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3425540295
Short name T139
Test name
Test status
Simulation time 282722892 ps
CPU time 1.89 seconds
Started Jul 16 05:32:01 PM PDT 24
Finished Jul 16 05:32:03 PM PDT 24
Peak memory 205528 kb
Host smart-3350a253-5634-43ae-bbf4-6a8da756e3a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425540295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3425540295
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.798494062
Short name T711
Test name
Test status
Simulation time 5373258854 ps
CPU time 6.19 seconds
Started Jul 16 05:23:13 PM PDT 24
Finished Jul 16 05:23:20 PM PDT 24
Peak memory 214352 kb
Host smart-c471776d-4f34-40cc-9011-cb5cc9657431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798494062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.798494062
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.347272582
Short name T150
Test name
Test status
Simulation time 127109833 ps
CPU time 1.04 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:23:40 PM PDT 24
Peak memory 205408 kb
Host smart-2889e2cf-0b37-4c5e-9b3f-861bfd87dc01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347272582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.347272582
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.793846805
Short name T671
Test name
Test status
Simulation time 1848541864 ps
CPU time 34.12 seconds
Started Jul 16 05:28:51 PM PDT 24
Finished Jul 16 05:29:27 PM PDT 24
Peak memory 325620 kb
Host smart-07926ec2-c5d2-4e91-bb16-5535d842885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793846805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.793846805
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.1101673995
Short name T54
Test name
Test status
Simulation time 59638269 ps
CPU time 1.54 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:17 PM PDT 24
Peak memory 205600 kb
Host smart-7b759cc7-a2b5-4e36-9e9b-00f26ad58b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101673995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1101673995
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.753837181
Short name T244
Test name
Test status
Simulation time 623370736 ps
CPU time 24.29 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:24 PM PDT 24
Peak memory 205256 kb
Host smart-22c7b745-7d48-4bf1-90f4-1a36623f814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753837181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.753837181
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1905119449
Short name T230
Test name
Test status
Simulation time 944366300 ps
CPU time 29.21 seconds
Started Jul 16 05:24:24 PM PDT 24
Finished Jul 16 05:24:54 PM PDT 24
Peak memory 205480 kb
Host smart-efae9257-7dfd-4afa-93bf-214d764dee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905119449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1905119449
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2617762218
Short name T192
Test name
Test status
Simulation time 72586605 ps
CPU time 1.47 seconds
Started Jul 16 05:38:37 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204640 kb
Host smart-e7d9ff12-b520-49c2-9ab4-e1876a84adc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617762218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2617762218
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2322393488
Short name T187
Test name
Test status
Simulation time 317836444 ps
CPU time 2.06 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204576 kb
Host smart-e84e81c1-65d3-4522-a338-eebf37254af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322393488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2322393488
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1938543099
Short name T185
Test name
Test status
Simulation time 251325942 ps
CPU time 1.52 seconds
Started Jul 16 05:38:44 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204660 kb
Host smart-52e82d71-c8d3-47d8-9f29-52a8d0090671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938543099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1938543099
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.4173175846
Short name T12
Test name
Test status
Simulation time 110943462 ps
CPU time 3.7 seconds
Started Jul 16 05:22:46 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 213684 kb
Host smart-6b13d65c-6847-4c28-a03e-78caa4a026c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173175846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.4173175846
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2017841435
Short name T698
Test name
Test status
Simulation time 738148543 ps
CPU time 2.14 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:39 PM PDT 24
Peak memory 221812 kb
Host smart-e198504e-0ef1-4752-9033-a06f84b69714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017841435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2017841435
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3787609180
Short name T71
Test name
Test status
Simulation time 693917906 ps
CPU time 2.56 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 221628 kb
Host smart-be962ad1-4ad8-4791-a4cb-0e3065484da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787609180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3787609180
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3958398330
Short name T207
Test name
Test status
Simulation time 65900253 ps
CPU time 2.6 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 204644 kb
Host smart-7dc34183-1816-4fdf-aa34-11939e6d5232
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958398330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3958398330
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3659657955
Short name T1837
Test name
Test status
Simulation time 55971473 ps
CPU time 0.72 seconds
Started Jul 16 05:38:19 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 204424 kb
Host smart-91e00fca-e9c8-4398-9a9c-497b4f0c5be3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659657955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3659657955
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3035537689
Short name T1826
Test name
Test status
Simulation time 132572863 ps
CPU time 1.01 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 204508 kb
Host smart-e3c9a2e7-9bd5-4e34-b822-c6f2b10082f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035537689 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3035537689
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1582385947
Short name T117
Test name
Test status
Simulation time 25790905 ps
CPU time 0.77 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 204512 kb
Host smart-505ae8eb-830e-4925-a874-8fa35ce1a2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582385947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1582385947
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1590894321
Short name T1745
Test name
Test status
Simulation time 39170042 ps
CPU time 0.66 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 204440 kb
Host smart-3eb91b54-6421-491c-ba3f-2512363ca1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590894321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1590894321
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1372061323
Short name T93
Test name
Test status
Simulation time 127692060 ps
CPU time 1.18 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 204696 kb
Host smart-6dd5a832-a0ee-4866-ba9d-839f6e897bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372061323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1372061323
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.76854465
Short name T1786
Test name
Test status
Simulation time 36082117 ps
CPU time 1.42 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 204648 kb
Host smart-ad48fca6-1aff-408e-b375-9662b31bb1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76854465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.76854465
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3853378695
Short name T1807
Test name
Test status
Simulation time 52039762 ps
CPU time 1.35 seconds
Started Jul 16 05:38:17 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 204544 kb
Host smart-7bca39b2-5a9b-467f-8ac1-e1a93c48ca6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853378695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3853378695
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3921490502
Short name T200
Test name
Test status
Simulation time 411660214 ps
CPU time 1.96 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204552 kb
Host smart-b45b534a-9a79-4f3b-b159-32377740a461
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921490502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3921490502
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.907055185
Short name T1754
Test name
Test status
Simulation time 118669600 ps
CPU time 2.63 seconds
Started Jul 16 05:38:16 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 204704 kb
Host smart-048f632f-9f72-452b-a6de-6f6e138ce433
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907055185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.907055185
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1685394207
Short name T203
Test name
Test status
Simulation time 17275422 ps
CPU time 0.69 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 204420 kb
Host smart-ea225d93-eb7f-4b1d-9bf8-25358bca0f64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685394207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1685394207
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.181935687
Short name T1820
Test name
Test status
Simulation time 31741153 ps
CPU time 1.37 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 212788 kb
Host smart-1e9c067a-37a9-4443-aedd-d490d807e3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181935687 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.181935687
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2875685076
Short name T204
Test name
Test status
Simulation time 54493054 ps
CPU time 0.67 seconds
Started Jul 16 05:38:17 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 204384 kb
Host smart-3e711a73-1c3e-4100-beda-64579d2b5218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875685076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2875685076
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.4232075898
Short name T1744
Test name
Test status
Simulation time 84399007 ps
CPU time 0.68 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 204340 kb
Host smart-715c5293-6f19-4c84-80c3-3a27dfcafbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232075898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.4232075898
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1620350112
Short name T212
Test name
Test status
Simulation time 55000056 ps
CPU time 0.82 seconds
Started Jul 16 05:38:33 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204464 kb
Host smart-4e65b9a7-330b-44e1-8194-074c8bdb3511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620350112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1620350112
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.290937733
Short name T1822
Test name
Test status
Simulation time 45410089 ps
CPU time 2.22 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:23 PM PDT 24
Peak memory 204756 kb
Host smart-cbde548b-cd18-441c-a406-c31e4c7e08cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290937733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.290937733
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2403492793
Short name T1804
Test name
Test status
Simulation time 50270008 ps
CPU time 1.39 seconds
Started Jul 16 05:38:16 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 204572 kb
Host smart-ccdae7a6-8a8d-4814-bda6-b8aa1dd1b5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403492793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2403492793
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1072094985
Short name T1814
Test name
Test status
Simulation time 93982387 ps
CPU time 1.25 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204684 kb
Host smart-81ae57fd-c9e9-40e3-aede-7b2667182a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072094985 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1072094985
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2402656888
Short name T1776
Test name
Test status
Simulation time 60424279 ps
CPU time 0.7 seconds
Started Jul 16 05:38:41 PM PDT 24
Finished Jul 16 05:38:43 PM PDT 24
Peak memory 204460 kb
Host smart-aeacd3f4-b11c-4fca-84ce-98bbb64d7887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402656888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2402656888
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.553230568
Short name T1743
Test name
Test status
Simulation time 35701085 ps
CPU time 0.68 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204328 kb
Host smart-e5bb00ac-179c-46ab-8a42-efd27eb69017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553230568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.553230568
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3872528895
Short name T1842
Test name
Test status
Simulation time 58608128 ps
CPU time 1.1 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204588 kb
Host smart-3a089a7c-52e2-4f65-bb9e-effe9927cfd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872528895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3872528895
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.308207
Short name T1762
Test name
Test status
Simulation time 66705594 ps
CPU time 1.58 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204660 kb
Host smart-584e7bef-e961-47c4-be21-77c86187a1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.308207
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2002357038
Short name T1777
Test name
Test status
Simulation time 67285431 ps
CPU time 1.3 seconds
Started Jul 16 05:38:40 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 204692 kb
Host smart-2ab3e498-eacc-4336-9401-a32ebda509d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002357038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2002357038
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1230302895
Short name T1787
Test name
Test status
Simulation time 77885717 ps
CPU time 0.82 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204580 kb
Host smart-6b8ab391-8221-455a-ab64-59e116a5cd88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230302895 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1230302895
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3719613786
Short name T215
Test name
Test status
Simulation time 75717448 ps
CPU time 0.78 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204436 kb
Host smart-a04b9f20-8969-4b6a-80b9-bfd25a464d9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719613786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3719613786
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1103929372
Short name T1740
Test name
Test status
Simulation time 15519768 ps
CPU time 0.65 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204360 kb
Host smart-404f35ca-1f10-4746-a4e3-e2fac9972dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103929372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1103929372
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2860226186
Short name T1774
Test name
Test status
Simulation time 29552968 ps
CPU time 0.81 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204520 kb
Host smart-3c3c5fbe-cbd9-453e-9080-06f4515773cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860226186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2860226186
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4035325746
Short name T1829
Test name
Test status
Simulation time 46539971 ps
CPU time 1.42 seconds
Started Jul 16 05:38:37 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204608 kb
Host smart-de96b967-85f2-421a-91e2-8ef7bf534c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035325746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4035325746
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1552681291
Short name T1769
Test name
Test status
Simulation time 33900759 ps
CPU time 0.92 seconds
Started Jul 16 05:38:39 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204524 kb
Host smart-3803d33d-bc45-49dd-a191-e2507c1c2dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552681291 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1552681291
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3819171041
Short name T205
Test name
Test status
Simulation time 26279137 ps
CPU time 0.83 seconds
Started Jul 16 05:38:42 PM PDT 24
Finished Jul 16 05:38:43 PM PDT 24
Peak memory 204528 kb
Host smart-f9aa391b-c981-4b20-b0db-36d5854cfdfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819171041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3819171041
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.102796297
Short name T1750
Test name
Test status
Simulation time 123922280 ps
CPU time 0.67 seconds
Started Jul 16 05:38:37 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204360 kb
Host smart-085e3320-0f3a-4ae0-8aea-2f8eac20d270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102796297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.102796297
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.286980773
Short name T1834
Test name
Test status
Simulation time 183191908 ps
CPU time 1.13 seconds
Started Jul 16 05:38:33 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204636 kb
Host smart-1fec4f79-ded0-4b3e-976f-692cdb91514a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286980773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.286980773
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2466160964
Short name T1772
Test name
Test status
Simulation time 58753173 ps
CPU time 1.7 seconds
Started Jul 16 05:38:39 PM PDT 24
Finished Jul 16 05:38:42 PM PDT 24
Peak memory 204724 kb
Host smart-b73f0ceb-5fe2-451f-8f9b-a213e48d1310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466160964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2466160964
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2111491981
Short name T188
Test name
Test status
Simulation time 77324607 ps
CPU time 1.41 seconds
Started Jul 16 05:38:41 PM PDT 24
Finished Jul 16 05:38:43 PM PDT 24
Peak memory 204668 kb
Host smart-9771a537-00d1-41a0-91a5-bb560f44ddf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111491981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2111491981
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1014243421
Short name T1770
Test name
Test status
Simulation time 45329806 ps
CPU time 0.77 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204580 kb
Host smart-2fa779af-7038-4986-a6af-2d8ff2b67724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014243421 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1014243421
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.564639446
Short name T191
Test name
Test status
Simulation time 20977124 ps
CPU time 0.71 seconds
Started Jul 16 05:38:41 PM PDT 24
Finished Jul 16 05:38:42 PM PDT 24
Peak memory 204492 kb
Host smart-b77a54cf-d6df-4544-b30b-3c28c4edf67b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564639446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.564639446
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.59252379
Short name T1847
Test name
Test status
Simulation time 58190126 ps
CPU time 0.68 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 204340 kb
Host smart-33da061f-e84b-45fd-bea7-3595cb37c03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59252379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.59252379
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3467875681
Short name T1827
Test name
Test status
Simulation time 76170842 ps
CPU time 0.88 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204548 kb
Host smart-6af1aa24-a01c-4e67-917f-1500169149d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467875681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3467875681
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2528150969
Short name T1801
Test name
Test status
Simulation time 73699332 ps
CPU time 1.76 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 204692 kb
Host smart-766d4107-97b2-403a-ae6c-15bdb8306a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528150969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2528150969
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2229607735
Short name T196
Test name
Test status
Simulation time 25954681 ps
CPU time 0.89 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204492 kb
Host smart-f37652fd-a16f-49b4-8eae-d8534fef2413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229607735 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2229607735
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2423886457
Short name T1846
Test name
Test status
Simulation time 19286558 ps
CPU time 0.68 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204416 kb
Host smart-9870f4ab-068f-45d0-a21c-688f0aaac196
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423886457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2423886457
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1496541847
Short name T1799
Test name
Test status
Simulation time 37257482 ps
CPU time 0.64 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204376 kb
Host smart-775ee2af-9910-4dab-9a4a-abc3001c2047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496541847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1496541847
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.747236291
Short name T213
Test name
Test status
Simulation time 61159317 ps
CPU time 0.94 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 204476 kb
Host smart-5fabe76c-c80a-4553-b35a-99766369229d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747236291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.747236291
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2099089453
Short name T194
Test name
Test status
Simulation time 44029805 ps
CPU time 0.81 seconds
Started Jul 16 05:38:49 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204488 kb
Host smart-9faddcf0-d48d-411d-9b79-f4f260ed004e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099089453 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2099089453
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1481766972
Short name T1823
Test name
Test status
Simulation time 155641085 ps
CPU time 0.73 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 204332 kb
Host smart-c44b07c8-99c2-42a0-b503-2bc186785876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481766972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1481766972
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.612986481
Short name T1830
Test name
Test status
Simulation time 26998085 ps
CPU time 0.72 seconds
Started Jul 16 05:38:49 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204444 kb
Host smart-6c3f33f1-4c51-4de9-aef3-2c4e31fc0c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612986481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.612986481
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2662081444
Short name T214
Test name
Test status
Simulation time 26831047 ps
CPU time 1.1 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204596 kb
Host smart-f625ba19-380e-4bb0-99cf-0dea03965038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662081444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2662081444
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3436330386
Short name T1783
Test name
Test status
Simulation time 332579837 ps
CPU time 1.99 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204628 kb
Host smart-335e2f2b-6276-41c7-aab8-539e8eb5088d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436330386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3436330386
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3106685522
Short name T1808
Test name
Test status
Simulation time 47015744 ps
CPU time 1.42 seconds
Started Jul 16 05:38:44 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204588 kb
Host smart-48665e77-c6d5-472b-832d-2a6aa3db8467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106685522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3106685522
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.778088904
Short name T1789
Test name
Test status
Simulation time 121258298 ps
CPU time 0.96 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204460 kb
Host smart-0d98df2c-16a0-43ab-9df2-1f385ec5cf59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778088904 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.778088904
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.461475320
Short name T1763
Test name
Test status
Simulation time 69760587 ps
CPU time 0.67 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204432 kb
Host smart-a939443b-6c1b-4908-814b-613edc0a82ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461475320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.461475320
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2430022708
Short name T121
Test name
Test status
Simulation time 31410304 ps
CPU time 0.71 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204392 kb
Host smart-d9e3068e-a9e9-4115-9ba3-3bc85ef01c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430022708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2430022708
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1811437626
Short name T1832
Test name
Test status
Simulation time 65005376 ps
CPU time 1.23 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:47 PM PDT 24
Peak memory 204668 kb
Host smart-be7871e9-9c74-4928-8e64-da562521ad90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811437626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1811437626
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.116165901
Short name T183
Test name
Test status
Simulation time 87342612 ps
CPU time 2.52 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204684 kb
Host smart-28940c90-8cdb-4174-a3e1-fbe6de237fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116165901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.116165901
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3245968143
Short name T91
Test name
Test status
Simulation time 64962801 ps
CPU time 0.76 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204388 kb
Host smart-6530c0fb-cc1c-4498-a832-daa27cd65b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245968143 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3245968143
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2123477477
Short name T1788
Test name
Test status
Simulation time 25243373 ps
CPU time 0.76 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204388 kb
Host smart-5c0028c5-e988-4f09-8218-b8010ded4d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123477477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2123477477
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2974562312
Short name T1793
Test name
Test status
Simulation time 20074632 ps
CPU time 0.67 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:47 PM PDT 24
Peak memory 204428 kb
Host smart-f86f40df-fca2-41c0-80dd-3e7c4a3caad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974562312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2974562312
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1923577877
Short name T96
Test name
Test status
Simulation time 40275422 ps
CPU time 0.92 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204396 kb
Host smart-d6bfbddd-e3fe-45f9-8684-5fada9eea661
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923577877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1923577877
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3282451419
Short name T184
Test name
Test status
Simulation time 55017995 ps
CPU time 2.62 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 212920 kb
Host smart-55ed1c59-f6a7-4b3a-b676-4df1f5bdb713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282451419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3282451419
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1063376942
Short name T98
Test name
Test status
Simulation time 964955956 ps
CPU time 2.22 seconds
Started Jul 16 05:38:44 PM PDT 24
Finished Jul 16 05:38:47 PM PDT 24
Peak memory 204584 kb
Host smart-548b82cd-3f6d-4236-b78d-f30a7dd8ffe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063376942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1063376942
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3607126351
Short name T1845
Test name
Test status
Simulation time 104385895 ps
CPU time 1.52 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 212904 kb
Host smart-a0097b48-af18-44bb-981d-b7289d488cfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607126351 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3607126351
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1382943502
Short name T1818
Test name
Test status
Simulation time 18446765 ps
CPU time 0.69 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204388 kb
Host smart-75f029de-8433-4bb7-ba58-d9452ed29b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382943502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1382943502
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2565333789
Short name T1843
Test name
Test status
Simulation time 63240301 ps
CPU time 0.85 seconds
Started Jul 16 05:38:44 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204476 kb
Host smart-9d44df55-d9bb-420f-9409-2e2a333dd4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565333789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2565333789
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.381154707
Short name T173
Test name
Test status
Simulation time 126786267 ps
CPU time 1.36 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 204680 kb
Host smart-f14d1146-18af-4d5c-af52-22644ed2d850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381154707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.381154707
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4147289323
Short name T195
Test name
Test status
Simulation time 71813830 ps
CPU time 0.78 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204496 kb
Host smart-d46f7961-fbdb-444b-a86d-ef529466d3bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147289323 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4147289323
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2892792286
Short name T1812
Test name
Test status
Simulation time 57810984 ps
CPU time 0.69 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204396 kb
Host smart-3c4b3a66-704b-4d49-8575-656dab9ee422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892792286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2892792286
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.4139714643
Short name T1768
Test name
Test status
Simulation time 29033794 ps
CPU time 0.65 seconds
Started Jul 16 05:38:49 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204428 kb
Host smart-977003f1-24f2-441f-ab86-642cd34cae1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139714643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4139714643
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3341830484
Short name T1800
Test name
Test status
Simulation time 108057651 ps
CPU time 0.82 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204548 kb
Host smart-5b07209e-381e-4f66-808a-7258b7cd426d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341830484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3341830484
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.4232092711
Short name T1821
Test name
Test status
Simulation time 250398233 ps
CPU time 1.68 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:53 PM PDT 24
Peak memory 204720 kb
Host smart-e3fe665e-40cd-43d1-8202-1a8440e14131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232092711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.4232092711
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4106732861
Short name T1764
Test name
Test status
Simulation time 82096491 ps
CPU time 1.56 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:47 PM PDT 24
Peak memory 204676 kb
Host smart-9f24e9fb-1718-4208-8fec-ae6d824db7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106732861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4106732861
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2395058657
Short name T1759
Test name
Test status
Simulation time 202149678 ps
CPU time 1.9 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204632 kb
Host smart-86f7aaf5-0e90-4564-958c-1f76f069e2b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395058657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2395058657
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1057182984
Short name T1761
Test name
Test status
Simulation time 65302261 ps
CPU time 2.64 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204588 kb
Host smart-1ace89e8-9b27-474e-9b1e-c0e4408679b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057182984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1057182984
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.750408315
Short name T1766
Test name
Test status
Simulation time 176875314 ps
CPU time 0.72 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204460 kb
Host smart-79e1b324-dfa0-4cbd-9816-a165c2772f58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750408315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.750408315
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.369575090
Short name T1775
Test name
Test status
Simulation time 41894556 ps
CPU time 0.99 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:31 PM PDT 24
Peak memory 204540 kb
Host smart-8b1b775a-8458-43c0-b1d9-64aa3003e58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369575090 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.369575090
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.255378434
Short name T202
Test name
Test status
Simulation time 39597388 ps
CPU time 0.73 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:38 PM PDT 24
Peak memory 204492 kb
Host smart-cdc189d6-a967-4396-b363-1b124d5c198d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255378434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.255378434
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.585782404
Short name T1844
Test name
Test status
Simulation time 43004275 ps
CPU time 0.69 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204400 kb
Host smart-87649d82-2df6-41ad-ae00-f74d010ee2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585782404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.585782404
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.686699948
Short name T92
Test name
Test status
Simulation time 56391246 ps
CPU time 1.12 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204676 kb
Host smart-b4a777fb-8015-4899-ac1b-bd03dd919481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686699948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.686699948
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2629323406
Short name T1757
Test name
Test status
Simulation time 214762015 ps
CPU time 2.45 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204560 kb
Host smart-69f8ed9b-f0bf-4d77-a9ae-4d346769676b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629323406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2629323406
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.748132284
Short name T189
Test name
Test status
Simulation time 85264765 ps
CPU time 1.46 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204644 kb
Host smart-6464e596-d754-4a57-9d7f-c0e65497798e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748132284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.748132284
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1768958464
Short name T1790
Test name
Test status
Simulation time 16399637 ps
CPU time 0.69 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:48 PM PDT 24
Peak memory 204472 kb
Host smart-85181dae-0f31-48dc-ab6f-a8f36e136593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768958464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1768958464
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4279127146
Short name T1755
Test name
Test status
Simulation time 17944563 ps
CPU time 0.69 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204408 kb
Host smart-47b4aa4b-8efb-4582-9109-d224284278b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279127146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4279127146
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2113043080
Short name T123
Test name
Test status
Simulation time 63723864 ps
CPU time 0.69 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204360 kb
Host smart-bcce3814-7e39-4183-a864-1dc8812eac8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113043080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2113043080
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.4267066798
Short name T1833
Test name
Test status
Simulation time 58460700 ps
CPU time 0.71 seconds
Started Jul 16 05:38:49 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204364 kb
Host smart-0c1532cf-f795-485c-a05a-4c61f0cfeba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267066798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4267066798
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.270965405
Short name T1848
Test name
Test status
Simulation time 65968572 ps
CPU time 0.67 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204404 kb
Host smart-9986a1b8-cbcc-4ac8-837d-6d104c27aa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270965405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.270965405
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3648129818
Short name T1771
Test name
Test status
Simulation time 40880405 ps
CPU time 0.7 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204392 kb
Host smart-61e9a1a4-d8be-4b49-aa17-78611f8495c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648129818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3648129818
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.4027299822
Short name T1825
Test name
Test status
Simulation time 42400878 ps
CPU time 0.65 seconds
Started Jul 16 05:38:46 PM PDT 24
Finished Jul 16 05:38:47 PM PDT 24
Peak memory 204436 kb
Host smart-eb213fd6-f967-487c-b042-bace118b74e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027299822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4027299822
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1716990759
Short name T1781
Test name
Test status
Simulation time 15338893 ps
CPU time 0.64 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:50 PM PDT 24
Peak memory 204360 kb
Host smart-1131576b-07b0-4b21-b3f2-5084094d89a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716990759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1716990759
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1887679809
Short name T1748
Test name
Test status
Simulation time 41440080 ps
CPU time 0.68 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204284 kb
Host smart-b11559c9-e3cb-4d29-b456-e9cfbb951ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887679809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1887679809
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4190341931
Short name T122
Test name
Test status
Simulation time 19902415 ps
CPU time 0.69 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204424 kb
Host smart-b866bd0f-bc10-4fd0-913f-02f87f6650f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190341931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4190341931
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2843563077
Short name T201
Test name
Test status
Simulation time 137375851 ps
CPU time 1.75 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204552 kb
Host smart-5789deec-dbd8-4da3-ad01-33d3c60a665e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843563077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2843563077
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3310907062
Short name T1739
Test name
Test status
Simulation time 422216325 ps
CPU time 4.41 seconds
Started Jul 16 05:38:29 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204572 kb
Host smart-d996b253-3161-4de3-a381-8f2418159ea6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310907062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3310907062
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2672994829
Short name T1797
Test name
Test status
Simulation time 71822248 ps
CPU time 0.78 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204516 kb
Host smart-08d785a0-b995-4403-979e-aa27feee7feb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672994829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2672994829
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3078526532
Short name T1841
Test name
Test status
Simulation time 246479893 ps
CPU time 0.99 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204536 kb
Host smart-b0442a15-d4e9-43bb-8890-63429f3c9ef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078526532 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3078526532
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1712647641
Short name T216
Test name
Test status
Simulation time 31279493 ps
CPU time 0.71 seconds
Started Jul 16 05:38:34 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204448 kb
Host smart-d0578bcc-ead5-44aa-a394-81d5d4322cb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712647641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1712647641
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3116930850
Short name T1742
Test name
Test status
Simulation time 21693684 ps
CPU time 0.69 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204424 kb
Host smart-7ad3493e-7f0d-46fc-8373-9fea51e0b067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116930850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3116930850
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3897116872
Short name T1817
Test name
Test status
Simulation time 879649654 ps
CPU time 1.12 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204684 kb
Host smart-eb935489-751f-46c6-a787-3aced4f936cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897116872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3897116872
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2750441009
Short name T1778
Test name
Test status
Simulation time 96509330 ps
CPU time 1.29 seconds
Started Jul 16 05:38:29 PM PDT 24
Finished Jul 16 05:38:31 PM PDT 24
Peak memory 204700 kb
Host smart-98eba459-04d7-47b3-ada8-bec75b410dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750441009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2750441009
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3671848865
Short name T190
Test name
Test status
Simulation time 184091775 ps
CPU time 1.47 seconds
Started Jul 16 05:38:34 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204616 kb
Host smart-9cbad917-5166-4638-a3a5-eb82f5958efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671848865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3671848865
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2412638555
Short name T1784
Test name
Test status
Simulation time 29617057 ps
CPU time 0.72 seconds
Started Jul 16 05:38:47 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 204472 kb
Host smart-3c8bd44c-7cdc-4878-adee-11ec14242f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412638555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2412638555
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.4133182493
Short name T1836
Test name
Test status
Simulation time 24739957 ps
CPU time 0.74 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204324 kb
Host smart-6fce3a5d-f21e-4eca-9294-d6c6d88c513f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133182493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4133182493
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1812616606
Short name T1756
Test name
Test status
Simulation time 52491875 ps
CPU time 0.71 seconds
Started Jul 16 05:38:44 PM PDT 24
Finished Jul 16 05:38:45 PM PDT 24
Peak memory 204324 kb
Host smart-82ac0e65-f274-41cf-9bb2-12601b564fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812616606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1812616606
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3067312433
Short name T1796
Test name
Test status
Simulation time 22075920 ps
CPU time 0.7 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204344 kb
Host smart-e626ac5c-6100-4aa5-86ae-7d62c42c24dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067312433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3067312433
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1470219758
Short name T1803
Test name
Test status
Simulation time 46067069 ps
CPU time 0.67 seconds
Started Jul 16 05:38:49 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204444 kb
Host smart-25f32d23-2a20-468c-a917-dfea46424faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470219758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1470219758
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2670302052
Short name T120
Test name
Test status
Simulation time 20202714 ps
CPU time 0.73 seconds
Started Jul 16 05:38:45 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 204404 kb
Host smart-63630bf2-a816-4982-845d-189b2bd1d5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670302052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2670302052
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1559287410
Short name T1767
Test name
Test status
Simulation time 17123368 ps
CPU time 0.77 seconds
Started Jul 16 05:38:48 PM PDT 24
Finished Jul 16 05:38:51 PM PDT 24
Peak memory 204360 kb
Host smart-57943fd6-4b78-4926-9bb3-0793c04ecd9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559287410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1559287410
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1033628048
Short name T1782
Test name
Test status
Simulation time 28149701 ps
CPU time 0.65 seconds
Started Jul 16 05:38:50 PM PDT 24
Finished Jul 16 05:38:52 PM PDT 24
Peak memory 204444 kb
Host smart-37ff7c65-64d3-4c4e-9e4b-82bb34e5d228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033628048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1033628048
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1453416584
Short name T1751
Test name
Test status
Simulation time 16998445 ps
CPU time 0.67 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:38:58 PM PDT 24
Peak memory 204408 kb
Host smart-9513133c-bb93-49fb-8033-3f3e9354f1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453416584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1453416584
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2691747040
Short name T1749
Test name
Test status
Simulation time 21852878 ps
CPU time 0.69 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:01 PM PDT 24
Peak memory 204300 kb
Host smart-a8960f57-fe16-44b9-8572-dea22c516f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691747040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2691747040
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3865010197
Short name T198
Test name
Test status
Simulation time 212991143 ps
CPU time 1.29 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204700 kb
Host smart-3d8f11ef-6a60-4c07-be4f-76a8e5927410
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865010197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3865010197
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1238597751
Short name T208
Test name
Test status
Simulation time 541667181 ps
CPU time 5.01 seconds
Started Jul 16 05:38:33 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204684 kb
Host smart-9a74f670-ac67-427b-a31e-33a2d4be9e2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238597751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1238597751
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1848446012
Short name T197
Test name
Test status
Simulation time 48329134 ps
CPU time 0.78 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204336 kb
Host smart-52121bcf-07ea-4248-8fff-242e3d1b1414
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848446012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1848446012
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.406167391
Short name T172
Test name
Test status
Simulation time 78220558 ps
CPU time 1.2 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 212988 kb
Host smart-e51cddee-894e-446a-a1ef-a599b5db01ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406167391 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.406167391
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1074128662
Short name T1780
Test name
Test status
Simulation time 15662987 ps
CPU time 0.69 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204328 kb
Host smart-35aeb2f6-ebde-45cd-8c80-773910a27c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074128662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1074128662
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2011556073
Short name T1753
Test name
Test status
Simulation time 33395644 ps
CPU time 0.68 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:38 PM PDT 24
Peak memory 204400 kb
Host smart-77dca087-dc2f-4530-a8cc-0c2f954182bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011556073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2011556073
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3093088933
Short name T1816
Test name
Test status
Simulation time 36286534 ps
CPU time 0.84 seconds
Started Jul 16 05:38:29 PM PDT 24
Finished Jul 16 05:38:30 PM PDT 24
Peak memory 204384 kb
Host smart-17a2ea48-c8e1-43af-b52d-f692259ffd13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093088933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3093088933
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2534726509
Short name T1795
Test name
Test status
Simulation time 79184190 ps
CPU time 1.96 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204708 kb
Host smart-5006e476-e5f3-453f-8fe0-6f9ac85d7e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534726509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2534726509
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.224108728
Short name T1835
Test name
Test status
Simulation time 517049331 ps
CPU time 2.35 seconds
Started Jul 16 05:38:33 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204644 kb
Host smart-b2e064e2-b754-45e8-81f8-e8f7d81a01c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224108728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.224108728
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2396156438
Short name T1747
Test name
Test status
Simulation time 15932827 ps
CPU time 0.66 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:00 PM PDT 24
Peak memory 204268 kb
Host smart-10280547-a7f4-4c42-9ff8-9f36625150c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396156438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2396156438
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1194305478
Short name T1824
Test name
Test status
Simulation time 20659108 ps
CPU time 0.73 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:38:58 PM PDT 24
Peak memory 204388 kb
Host smart-e995ddab-8fd1-4571-bb23-95af663b75e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194305478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1194305478
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3726981542
Short name T1792
Test name
Test status
Simulation time 16278640 ps
CPU time 0.71 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:01 PM PDT 24
Peak memory 204388 kb
Host smart-951d9e95-59d0-49e3-85e1-54dcc06ee11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726981542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3726981542
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1186104789
Short name T1741
Test name
Test status
Simulation time 30652219 ps
CPU time 0.71 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:38:58 PM PDT 24
Peak memory 204400 kb
Host smart-9fec46e2-8c71-4c9c-b172-5596416f0d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186104789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1186104789
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2870015527
Short name T1849
Test name
Test status
Simulation time 79315062 ps
CPU time 0.66 seconds
Started Jul 16 05:38:58 PM PDT 24
Finished Jul 16 05:38:59 PM PDT 24
Peak memory 204332 kb
Host smart-9507150c-e8c6-4273-b159-4109daf66427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870015527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2870015527
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2740474066
Short name T1840
Test name
Test status
Simulation time 17171431 ps
CPU time 0.72 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:01 PM PDT 24
Peak memory 204288 kb
Host smart-1d2eb3f0-bb1a-48f4-8d05-8a8ef1613878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740474066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2740474066
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3941214551
Short name T1760
Test name
Test status
Simulation time 19041602 ps
CPU time 0.71 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:38:58 PM PDT 24
Peak memory 204428 kb
Host smart-e0d6f30d-3ada-4beb-b60d-3db6b01ccfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941214551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3941214551
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1929455413
Short name T1752
Test name
Test status
Simulation time 19202342 ps
CPU time 0.7 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:38:58 PM PDT 24
Peak memory 204404 kb
Host smart-06aa3773-a530-4f28-b1f2-92d1d80fd1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929455413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1929455413
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3001507443
Short name T1746
Test name
Test status
Simulation time 45916408 ps
CPU time 0.65 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:01 PM PDT 24
Peak memory 204360 kb
Host smart-19e16842-cbe4-4e66-948d-b77373ac14df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001507443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3001507443
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2028450558
Short name T1765
Test name
Test status
Simulation time 24266421 ps
CPU time 0.66 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:39:00 PM PDT 24
Peak memory 204428 kb
Host smart-e34c2b49-db4f-40b3-b89a-ba9a3087b216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028450558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2028450558
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2412232891
Short name T118
Test name
Test status
Simulation time 127923769 ps
CPU time 0.94 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204576 kb
Host smart-91762c82-347d-4167-bd75-6e7029492180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412232891 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2412232891
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3315318990
Short name T1810
Test name
Test status
Simulation time 36513660 ps
CPU time 0.7 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204524 kb
Host smart-7db308ce-2182-4b3d-8f0b-5f64fedb5b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315318990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3315318990
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2059877718
Short name T1809
Test name
Test status
Simulation time 59442836 ps
CPU time 0.67 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204436 kb
Host smart-45c14bfb-37a1-4dc7-ae92-4a4669c43586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059877718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2059877718
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4005303774
Short name T1828
Test name
Test status
Simulation time 142135184 ps
CPU time 0.93 seconds
Started Jul 16 05:38:29 PM PDT 24
Finished Jul 16 05:38:30 PM PDT 24
Peak memory 204340 kb
Host smart-2b90fc26-5610-4bf7-84c0-291bd9089935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005303774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4005303774
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2405596740
Short name T1831
Test name
Test status
Simulation time 93311924 ps
CPU time 1.33 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204692 kb
Host smart-f19f50aa-3032-4989-b36d-49a2834de256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405596740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2405596740
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.749757078
Short name T1794
Test name
Test status
Simulation time 271964247 ps
CPU time 1.52 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204644 kb
Host smart-9ce6807a-6f53-420d-8a75-d8c7f6828889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749757078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.749757078
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1525088234
Short name T1850
Test name
Test status
Simulation time 37559713 ps
CPU time 0.98 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204476 kb
Host smart-969d7684-d974-49b8-930e-49569679ba55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525088234 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1525088234
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.234626722
Short name T1773
Test name
Test status
Simulation time 51697927 ps
CPU time 0.75 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204416 kb
Host smart-4f8bb4c0-fde4-450c-ba19-a6f7b522f4bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234626722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.234626722
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1854515397
Short name T266
Test name
Test status
Simulation time 121678810 ps
CPU time 0.64 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204424 kb
Host smart-c40f1bff-52d0-4797-bedf-4c58151a8615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854515397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1854515397
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4099317774
Short name T211
Test name
Test status
Simulation time 23651618 ps
CPU time 0.87 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204488 kb
Host smart-4ce14c63-4b21-4cbf-9daf-d01d6fbb2fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099317774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4099317774
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2685095843
Short name T1802
Test name
Test status
Simulation time 184492618 ps
CPU time 1.62 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204568 kb
Host smart-f1fdf8f1-0b14-42cc-9758-6fcb9a182065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685095843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2685095843
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4166134400
Short name T186
Test name
Test status
Simulation time 270708158 ps
CPU time 2.21 seconds
Started Jul 16 05:38:31 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204528 kb
Host smart-dcb3145a-d191-4822-9405-3f14b41fe840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166134400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4166134400
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.928305195
Short name T95
Test name
Test status
Simulation time 75135243 ps
CPU time 0.81 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204540 kb
Host smart-e355a886-c2f5-49d0-8373-44c82e609481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928305195 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.928305195
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3783731697
Short name T209
Test name
Test status
Simulation time 17486919 ps
CPU time 0.72 seconds
Started Jul 16 05:38:33 PM PDT 24
Finished Jul 16 05:38:35 PM PDT 24
Peak memory 204452 kb
Host smart-3aa618ec-aad7-4aab-9287-89df67657545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783731697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3783731697
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1925680380
Short name T1838
Test name
Test status
Simulation time 52587269 ps
CPU time 0.69 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 204340 kb
Host smart-75e960f3-7abd-403a-90b1-4ad1e03e1931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925680380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1925680380
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1431744009
Short name T1839
Test name
Test status
Simulation time 213096730 ps
CPU time 1.07 seconds
Started Jul 16 05:38:32 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 204656 kb
Host smart-0949a170-3f1f-412c-9f36-a44decd63c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431744009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1431744009
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2667039184
Short name T97
Test name
Test status
Simulation time 481214452 ps
CPU time 2.31 seconds
Started Jul 16 05:38:29 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204760 kb
Host smart-0dfe2f92-f28b-4183-b20b-5dd2bcc0e4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667039184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2667039184
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.802089171
Short name T1785
Test name
Test status
Simulation time 376276847 ps
CPU time 1.33 seconds
Started Jul 16 05:38:30 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 204632 kb
Host smart-053e2f87-8078-4359-840a-6c0d048ac287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802089171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.802089171
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.73922321
Short name T1791
Test name
Test status
Simulation time 26462217 ps
CPU time 0.83 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204400 kb
Host smart-a2c80b41-0900-405d-8f3f-9c03eef30df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73922321 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.73922321
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.179249594
Short name T206
Test name
Test status
Simulation time 64892047 ps
CPU time 0.68 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:38 PM PDT 24
Peak memory 204528 kb
Host smart-deacbf5f-9e8b-4d90-b08d-4b46da116c23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179249594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.179249594
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1395139751
Short name T1819
Test name
Test status
Simulation time 109897392 ps
CPU time 0.65 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:38 PM PDT 24
Peak memory 204408 kb
Host smart-880261c3-6b93-40e7-aad2-2f9529509bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395139751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1395139751
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.843047118
Short name T1798
Test name
Test status
Simulation time 69844789 ps
CPU time 0.89 seconds
Started Jul 16 05:38:38 PM PDT 24
Finished Jul 16 05:38:39 PM PDT 24
Peak memory 204456 kb
Host smart-5ac5eea6-9c05-470a-973b-0dea2603b0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843047118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.843047118
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2010568416
Short name T1815
Test name
Test status
Simulation time 263005140 ps
CPU time 2.47 seconds
Started Jul 16 05:38:37 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 204696 kb
Host smart-423712c6-ba3c-43a7-8f50-16c0bf1a92a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010568416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2010568416
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4278975504
Short name T90
Test name
Test status
Simulation time 154275950 ps
CPU time 2.16 seconds
Started Jul 16 05:38:37 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 204584 kb
Host smart-c7e7dbf0-a2db-4dae-ba5f-6afde5df7033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278975504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4278975504
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3232380000
Short name T1806
Test name
Test status
Simulation time 101793092 ps
CPU time 0.96 seconds
Started Jul 16 05:38:42 PM PDT 24
Finished Jul 16 05:38:43 PM PDT 24
Peak memory 204616 kb
Host smart-b82513af-b144-4c9d-8d54-b8c5c11e53cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232380000 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3232380000
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1944990995
Short name T1811
Test name
Test status
Simulation time 26804332 ps
CPU time 0.66 seconds
Started Jul 16 05:38:36 PM PDT 24
Finished Jul 16 05:38:37 PM PDT 24
Peak memory 204412 kb
Host smart-21ba88b1-eedf-4131-bb7e-45ecd30ebaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944990995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1944990995
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4162731173
Short name T1758
Test name
Test status
Simulation time 17546326 ps
CPU time 0.7 seconds
Started Jul 16 05:38:39 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 204436 kb
Host smart-184e0038-2322-409a-8128-b3b9df7a2640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162731173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4162731173
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3919367313
Short name T1805
Test name
Test status
Simulation time 30279144 ps
CPU time 1.18 seconds
Started Jul 16 05:38:35 PM PDT 24
Finished Jul 16 05:38:36 PM PDT 24
Peak memory 204608 kb
Host smart-c8e196b2-c97b-4dfb-b985-bdffbaf85911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919367313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3919367313
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4156650882
Short name T1813
Test name
Test status
Simulation time 240612569 ps
CPU time 2.49 seconds
Started Jul 16 05:38:34 PM PDT 24
Finished Jul 16 05:38:38 PM PDT 24
Peak memory 204712 kb
Host smart-3fbc00cd-85c8-42d5-b4d3-85c4d222bb52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156650882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4156650882
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2398397946
Short name T1062
Test name
Test status
Simulation time 55192221 ps
CPU time 0.63 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 204740 kb
Host smart-8883d76f-d509-487e-a946-9917c728c12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398397946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2398397946
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3527818966
Short name T419
Test name
Test status
Simulation time 232714469 ps
CPU time 3.76 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 213752 kb
Host smart-8f3de147-bac8-4274-afa6-8a377c0eb048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527818966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3527818966
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.4181928942
Short name T1162
Test name
Test status
Simulation time 668446512 ps
CPU time 7.3 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:22:11 PM PDT 24
Peak memory 276216 kb
Host smart-f7c7fe08-d572-4396-a94d-4afe47653b12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181928942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.4181928942
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3867115179
Short name T25
Test name
Test status
Simulation time 2369963144 ps
CPU time 66.77 seconds
Started Jul 16 05:27:07 PM PDT 24
Finished Jul 16 05:28:14 PM PDT 24
Peak memory 595268 kb
Host smart-4ce1f446-3cfe-4216-b502-00e63ef26d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867115179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3867115179
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1356440888
Short name T1133
Test name
Test status
Simulation time 1568536543 ps
CPU time 44.96 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:50 PM PDT 24
Peak memory 562424 kb
Host smart-64c125e2-6227-4861-a7a0-3ad63110d631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356440888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1356440888
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.996015446
Short name T1523
Test name
Test status
Simulation time 300310158 ps
CPU time 4.36 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 229796 kb
Host smart-b0751e1b-ff33-48b7-8afe-961019d6b4d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996015446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.996015446
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1807992
Short name T1458
Test name
Test status
Simulation time 42518864012 ps
CPU time 360.81 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:28:05 PM PDT 24
Peak memory 1372592 kb
Host smart-aa42f47a-ebdd-4224-9638-abe7762da278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1807992
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3324048309
Short name T27
Test name
Test status
Simulation time 636394103 ps
CPU time 25.7 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:22:33 PM PDT 24
Peak memory 205336 kb
Host smart-628f416b-09d0-4787-bfed-de8075047ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324048309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3324048309
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.297696256
Short name T1280
Test name
Test status
Simulation time 45831907 ps
CPU time 0.66 seconds
Started Jul 16 05:21:59 PM PDT 24
Finished Jul 16 05:22:00 PM PDT 24
Peak memory 205140 kb
Host smart-3aec8f9d-0593-445e-96de-b72dd7e66878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297696256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.297696256
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3591123455
Short name T1466
Test name
Test status
Simulation time 7363636886 ps
CPU time 30.13 seconds
Started Jul 16 05:22:00 PM PDT 24
Finished Jul 16 05:22:30 PM PDT 24
Peak memory 283456 kb
Host smart-3e8d6392-17e3-44b1-b1b6-e7388152d5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591123455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3591123455
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.3468523861
Short name T1717
Test name
Test status
Simulation time 143019200 ps
CPU time 2.02 seconds
Started Jul 16 05:23:54 PM PDT 24
Finished Jul 16 05:23:57 PM PDT 24
Peak memory 218716 kb
Host smart-bf151b4b-f555-4546-a863-119f57014bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468523861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3468523861
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1213054676
Short name T772
Test name
Test status
Simulation time 2588102727 ps
CPU time 60.01 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:23:03 PM PDT 24
Peak memory 303176 kb
Host smart-9ea351be-9e4a-48a9-96ed-d36e3796320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213054676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1213054676
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2991135158
Short name T1457
Test name
Test status
Simulation time 51501644423 ps
CPU time 165.38 seconds
Started Jul 16 05:21:59 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 624676 kb
Host smart-0fe69542-d14a-4f9f-a60c-4a10ea2979a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991135158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2991135158
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.588548455
Short name T756
Test name
Test status
Simulation time 681058583 ps
CPU time 31.86 seconds
Started Jul 16 05:24:17 PM PDT 24
Finished Jul 16 05:24:49 PM PDT 24
Peak memory 213664 kb
Host smart-ace195ea-a19b-4e46-ad92-78daa22f150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588548455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.588548455
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3506277650
Short name T176
Test name
Test status
Simulation time 142350806 ps
CPU time 0.93 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:03 PM PDT 24
Peak memory 224020 kb
Host smart-6ad2895c-cb21-4d7d-9afc-69fa54d956b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506277650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3506277650
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3961805825
Short name T148
Test name
Test status
Simulation time 205953175 ps
CPU time 1.55 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 205628 kb
Host smart-25f26001-cb60-4286-b4ff-c8e06ec9c25a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961805825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3961805825
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.59768228
Short name T1456
Test name
Test status
Simulation time 420182138 ps
CPU time 1.05 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:22:08 PM PDT 24
Peak memory 205624 kb
Host smart-91f1e5c8-b304-4a51-825f-f97dd145e8bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59768228 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_fifo_reset_tx.59768228
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1728091962
Short name T1308
Test name
Test status
Simulation time 554942290 ps
CPU time 3.24 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:05 PM PDT 24
Peak memory 213812 kb
Host smart-215d95b7-2008-4035-8d43-d0fcbf92d09f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728091962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1728091962
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.3459246821
Short name T352
Test name
Test status
Simulation time 275263021 ps
CPU time 1.49 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:03 PM PDT 24
Peak memory 205460 kb
Host smart-691bde71-bded-4dc5-813d-9ade2cb5be4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459246821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.3459246821
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1545518749
Short name T1091
Test name
Test status
Simulation time 1184262827 ps
CPU time 6.22 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:11 PM PDT 24
Peak memory 222008 kb
Host smart-38afccc5-d3e5-4d39-bead-2bd00677876e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545518749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1545518749
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1410941928
Short name T284
Test name
Test status
Simulation time 1097869175 ps
CPU time 1.86 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 205368 kb
Host smart-5bc3f4ea-846a-4f41-99a2-2bbe0b3485fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410941928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1410941928
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.578824908
Short name T1459
Test name
Test status
Simulation time 10371449466 ps
CPU time 3.2 seconds
Started Jul 16 05:22:07 PM PDT 24
Finished Jul 16 05:22:11 PM PDT 24
Peak memory 213764 kb
Host smart-4328eb79-339a-4b9a-9c0e-2b8e1c033f6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578824908 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_nack_acqfull.578824908
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.413914075
Short name T146
Test name
Test status
Simulation time 2538680601 ps
CPU time 2.86 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:08 PM PDT 24
Peak memory 205596 kb
Host smart-f0e65f4e-48a5-428d-8d1a-a8051ad9f31d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413914075 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.413914075
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.1609189662
Short name T1361
Test name
Test status
Simulation time 583511449 ps
CPU time 5 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:22:12 PM PDT 24
Peak memory 221452 kb
Host smart-a4aad80e-8c53-45eb-a424-ba3e3dfc89c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609189662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.1609189662
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.345148542
Short name T701
Test name
Test status
Simulation time 1594382597 ps
CPU time 2.29 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:05 PM PDT 24
Peak memory 205472 kb
Host smart-118fbe44-1ec1-421a-9fff-3402e9f64312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345148542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_smbus_maxlen.345148542
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.166359279
Short name T1552
Test name
Test status
Simulation time 1608239303 ps
CPU time 24.03 seconds
Started Jul 16 05:22:02 PM PDT 24
Finished Jul 16 05:22:27 PM PDT 24
Peak memory 213820 kb
Host smart-1cc5c7ab-1a40-4e82-8eef-e020f6dab886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166359279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.166359279
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.668070944
Short name T576
Test name
Test status
Simulation time 1649979975 ps
CPU time 28.02 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:42 PM PDT 24
Peak memory 232016 kb
Host smart-456e13df-70dd-421c-9c38-d4062e5c8c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668070944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.668070944
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.5023465
Short name T606
Test name
Test status
Simulation time 55810252193 ps
CPU time 97.18 seconds
Started Jul 16 05:26:00 PM PDT 24
Finished Jul 16 05:27:38 PM PDT 24
Peak memory 1385132 kb
Host smart-682378b3-f819-4b95-adcd-6be1c98f9e8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5023465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stress_wr.5023465
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2507925039
Short name T872
Test name
Test status
Simulation time 4150809434 ps
CPU time 7.86 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:09 PM PDT 24
Peak memory 239208 kb
Host smart-d155daf2-11a9-4c9b-9f75-19c031808ed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507925039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2507925039
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.76044543
Short name T1159
Test name
Test status
Simulation time 3032345706 ps
CPU time 6.9 seconds
Started Jul 16 05:21:57 PM PDT 24
Finished Jul 16 05:22:05 PM PDT 24
Peak memory 222112 kb
Host smart-819498cb-05b0-4791-a557-6934793a61fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76044543 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_timeout.76044543
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.1725273288
Short name T1340
Test name
Test status
Simulation time 464218065 ps
CPU time 6.57 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 205500 kb
Host smart-2e2a00ef-c051-421e-82f7-b39b90e39236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725273288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.1725273288
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2121857071
Short name T1367
Test name
Test status
Simulation time 17535758 ps
CPU time 0.69 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 204836 kb
Host smart-b769bdea-d6f0-4379-a67a-308aeb1a8d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121857071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2121857071
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2587806719
Short name T30
Test name
Test status
Simulation time 387981306 ps
CPU time 17.63 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 283160 kb
Host smart-44edcc63-338a-45a0-998d-9bdd84983d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587806719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2587806719
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1596999464
Short name T1081
Test name
Test status
Simulation time 429057548 ps
CPU time 5.68 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:14 PM PDT 24
Peak memory 256308 kb
Host smart-515ec02e-46fe-4c99-9bb4-e3b0c2dec45d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596999464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1596999464
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2637452647
Short name T1382
Test name
Test status
Simulation time 9728605590 ps
CPU time 66.9 seconds
Started Jul 16 05:32:01 PM PDT 24
Finished Jul 16 05:33:08 PM PDT 24
Peak memory 367976 kb
Host smart-5130ec4d-ae2c-46f0-af0b-60555b06e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637452647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2637452647
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.842517501
Short name T933
Test name
Test status
Simulation time 47282764452 ps
CPU time 60.14 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:23:07 PM PDT 24
Peak memory 606356 kb
Host smart-2fec6026-b098-4dee-81f2-fdbf7bfd0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842517501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.842517501
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2916416172
Short name T1499
Test name
Test status
Simulation time 361584231 ps
CPU time 1 seconds
Started Jul 16 05:22:05 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 205244 kb
Host smart-1b3391c9-dcd6-44df-90e2-1f7d14659177
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916416172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2916416172
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2258570766
Short name T1477
Test name
Test status
Simulation time 162537749 ps
CPU time 3.48 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 205548 kb
Host smart-faa8af65-db22-44c2-aa0f-bc486ad9031b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258570766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2258570766
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1095684115
Short name T107
Test name
Test status
Simulation time 27525537389 ps
CPU time 133.09 seconds
Started Jul 16 05:22:07 PM PDT 24
Finished Jul 16 05:24:20 PM PDT 24
Peak memory 1470108 kb
Host smart-53eec898-650b-4517-8138-7c56911be4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095684115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1095684115
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1130567136
Short name T886
Test name
Test status
Simulation time 2768785547 ps
CPU time 7.91 seconds
Started Jul 16 05:22:12 PM PDT 24
Finished Jul 16 05:22:20 PM PDT 24
Peak memory 205576 kb
Host smart-2a325f4e-da01-48db-80b8-f7989a9ad12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130567136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1130567136
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.1232961559
Short name T1275
Test name
Test status
Simulation time 28549184 ps
CPU time 0.71 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:09 PM PDT 24
Peak memory 205152 kb
Host smart-44f37a97-b6d7-4285-9bc7-cf6c4e044204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232961559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1232961559
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2951162409
Short name T1074
Test name
Test status
Simulation time 1050950215 ps
CPU time 11.29 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:16 PM PDT 24
Peak memory 218916 kb
Host smart-fd4214fa-a733-454f-90f0-adc800b7df30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951162409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2951162409
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.1651735562
Short name T14
Test name
Test status
Simulation time 281668648 ps
CPU time 2.72 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 213660 kb
Host smart-c21ad895-4ba5-46b6-be83-2b0bd3725675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651735562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.1651735562
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3931845898
Short name T484
Test name
Test status
Simulation time 7608436206 ps
CPU time 18.97 seconds
Started Jul 16 05:22:07 PM PDT 24
Finished Jul 16 05:22:26 PM PDT 24
Peak memory 337836 kb
Host smart-3724f817-f716-4293-979c-846fa8838b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931845898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3931845898
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1621535625
Short name T386
Test name
Test status
Simulation time 747369259 ps
CPU time 35.48 seconds
Started Jul 16 05:26:08 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 213668 kb
Host smart-6c21fa6e-7b5e-467f-b8a2-b287f94768e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621535625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1621535625
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1358788448
Short name T175
Test name
Test status
Simulation time 127527852 ps
CPU time 0.84 seconds
Started Jul 16 05:22:14 PM PDT 24
Finished Jul 16 05:22:16 PM PDT 24
Peak memory 223784 kb
Host smart-525a91d9-1cc3-4e20-a3f3-f3da415b31a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358788448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1358788448
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.371556823
Short name T1025
Test name
Test status
Simulation time 1970876127 ps
CPU time 3.35 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 213860 kb
Host smart-ac364526-db0c-4d4f-8f8e-99d584e3ebd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371556823 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.371556823
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2040051001
Short name T116
Test name
Test status
Simulation time 179552404 ps
CPU time 0.99 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:10 PM PDT 24
Peak memory 205468 kb
Host smart-ed7d6645-4336-4036-8d76-879da27d0d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040051001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2040051001
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1960412503
Short name T927
Test name
Test status
Simulation time 266342090 ps
CPU time 1.65 seconds
Started Jul 16 05:22:07 PM PDT 24
Finished Jul 16 05:22:09 PM PDT 24
Peak memory 209024 kb
Host smart-e6e620af-e502-4323-b5a0-afc7a6653467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960412503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1960412503
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.1155987841
Short name T315
Test name
Test status
Simulation time 257214745 ps
CPU time 1.89 seconds
Started Jul 16 05:22:19 PM PDT 24
Finished Jul 16 05:22:22 PM PDT 24
Peak memory 205476 kb
Host smart-254b3c31-5f60-471f-af38-59d9971278c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155987841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.1155987841
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2615191667
Short name T1469
Test name
Test status
Simulation time 1370408589 ps
CPU time 1.34 seconds
Started Jul 16 05:22:10 PM PDT 24
Finished Jul 16 05:22:12 PM PDT 24
Peak memory 205468 kb
Host smart-b451e00b-f069-42c0-b304-84f4992b6133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615191667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2615191667
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.838804718
Short name T50
Test name
Test status
Simulation time 6131200941 ps
CPU time 9.22 seconds
Started Jul 16 05:22:05 PM PDT 24
Finished Jul 16 05:22:15 PM PDT 24
Peak memory 214084 kb
Host smart-88d0fa6d-da04-4a6d-9364-6890e0f71ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838804718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.838804718
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2812945151
Short name T1044
Test name
Test status
Simulation time 1058705258 ps
CPU time 2.14 seconds
Started Jul 16 05:22:17 PM PDT 24
Finished Jul 16 05:22:19 PM PDT 24
Peak memory 207396 kb
Host smart-831fb9cf-84f9-4233-92e1-164dc44f7fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812945151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2812945151
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3555884957
Short name T380
Test name
Test status
Simulation time 6164977968 ps
CPU time 8.06 seconds
Started Jul 16 05:22:09 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 213952 kb
Host smart-afeca434-3c21-4bda-a42a-280571475261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555884957 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3555884957
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2260694256
Short name T534
Test name
Test status
Simulation time 10245231732 ps
CPU time 21.76 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:30 PM PDT 24
Peak memory 701084 kb
Host smart-6909df97-64ab-4afb-87aa-c146a7dfb14e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260694256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2260694256
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.3159126800
Short name T1136
Test name
Test status
Simulation time 634545554 ps
CPU time 2.96 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 213764 kb
Host smart-2579ff41-d429-429e-b77b-da09d4047beb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159126800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.3159126800
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.2699464030
Short name T1126
Test name
Test status
Simulation time 513351125 ps
CPU time 2.66 seconds
Started Jul 16 05:22:15 PM PDT 24
Finished Jul 16 05:22:19 PM PDT 24
Peak memory 205808 kb
Host smart-11803fea-a8d9-481e-b2eb-27cd180c14f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699464030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2699464030
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.2449043265
Short name T1379
Test name
Test status
Simulation time 3001069365 ps
CPU time 8.24 seconds
Started Jul 16 05:22:05 PM PDT 24
Finished Jul 16 05:22:14 PM PDT 24
Peak memory 213812 kb
Host smart-214b51c1-c283-48ca-8636-e670497ac356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449043265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.2449043265
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.4270870280
Short name T1719
Test name
Test status
Simulation time 2232608740 ps
CPU time 2.39 seconds
Started Jul 16 05:22:14 PM PDT 24
Finished Jul 16 05:22:17 PM PDT 24
Peak memory 205520 kb
Host smart-597ed354-eee9-433e-b36d-0b6fa0c9c9fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270870280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.4270870280
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1920923006
Short name T1495
Test name
Test status
Simulation time 775143122 ps
CPU time 10.02 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:18 PM PDT 24
Peak memory 213764 kb
Host smart-801ee73e-c093-4b21-a70e-5c77e26cec4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920923006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1920923006
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.953037643
Short name T621
Test name
Test status
Simulation time 12345927690 ps
CPU time 38.3 seconds
Started Jul 16 05:22:05 PM PDT 24
Finished Jul 16 05:22:44 PM PDT 24
Peak memory 238448 kb
Host smart-e8fae2a4-5e27-42ad-b146-c336a41138d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953037643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.953037643
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3471189949
Short name T790
Test name
Test status
Simulation time 637522143 ps
CPU time 27.91 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:36 PM PDT 24
Peak memory 213748 kb
Host smart-31ff1549-66cb-4613-bb08-93e674391155
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471189949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3471189949
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3102546850
Short name T1000
Test name
Test status
Simulation time 40715295634 ps
CPU time 624.84 seconds
Started Jul 16 05:22:06 PM PDT 24
Finished Jul 16 05:32:31 PM PDT 24
Peak memory 5026440 kb
Host smart-64d718e8-946d-47a4-94bc-4943f037781a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102546850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3102546850
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.912875380
Short name T1134
Test name
Test status
Simulation time 555933046 ps
CPU time 6.76 seconds
Started Jul 16 05:22:08 PM PDT 24
Finished Jul 16 05:22:16 PM PDT 24
Peak memory 283616 kb
Host smart-ae9d2fdc-a4dc-413e-b4d8-645b7772810e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912875380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.912875380
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2760220024
Short name T295
Test name
Test status
Simulation time 11141782710 ps
CPU time 8.09 seconds
Started Jul 16 05:22:09 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 221976 kb
Host smart-4d26c759-eb81-49cf-bd8b-95ae7bc48edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760220024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2760220024
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.259541133
Short name T1362
Test name
Test status
Simulation time 118476240 ps
CPU time 2.13 seconds
Started Jul 16 05:22:10 PM PDT 24
Finished Jul 16 05:22:12 PM PDT 24
Peak memory 205520 kb
Host smart-ae340bf0-58e6-43c7-adf1-ed249f35ac63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259541133 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.259541133
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.727189688
Short name T848
Test name
Test status
Simulation time 25093717 ps
CPU time 0.68 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 204792 kb
Host smart-391e9ac5-056b-4f58-9730-9fc3f84cc56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727189688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.727189688
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.399250466
Short name T1378
Test name
Test status
Simulation time 109150892 ps
CPU time 1.64 seconds
Started Jul 16 05:23:03 PM PDT 24
Finished Jul 16 05:23:07 PM PDT 24
Peak memory 213776 kb
Host smart-d7b66c6b-6d90-404f-86d1-d721ce1140fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399250466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.399250466
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3221966364
Short name T1255
Test name
Test status
Simulation time 1903277128 ps
CPU time 8.67 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 287748 kb
Host smart-a76c86d9-3a44-40d0-a991-e7b4550cea85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221966364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3221966364
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.369633951
Short name T145
Test name
Test status
Simulation time 7262839173 ps
CPU time 48.6 seconds
Started Jul 16 05:22:57 PM PDT 24
Finished Jul 16 05:23:47 PM PDT 24
Peak memory 380888 kb
Host smart-78a29e0a-06b0-4e95-a940-a96e7c4cbaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369633951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.369633951
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.111963138
Short name T941
Test name
Test status
Simulation time 24476680221 ps
CPU time 83.54 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 843288 kb
Host smart-5c5a2d51-d50e-45d2-baab-5283918cce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111963138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.111963138
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.4026736951
Short name T1301
Test name
Test status
Simulation time 80272404 ps
CPU time 0.83 seconds
Started Jul 16 05:23:03 PM PDT 24
Finished Jul 16 05:23:06 PM PDT 24
Peak memory 205220 kb
Host smart-2922f16b-ba60-44c1-aaec-fdc915fd4abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026736951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.4026736951
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2709186466
Short name T936
Test name
Test status
Simulation time 3883968699 ps
CPU time 5.19 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 243068 kb
Host smart-7a0d4316-f70e-49ec-99ff-cbe30cc32710
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709186466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2709186466
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3582422520
Short name T526
Test name
Test status
Simulation time 14950143749 ps
CPU time 107.31 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:24:53 PM PDT 24
Peak memory 1102668 kb
Host smart-1f1c2346-a5ef-4ad8-acaf-5f9e0c6a3838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582422520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3582422520
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1729881502
Short name T256
Test name
Test status
Simulation time 378830556 ps
CPU time 4.62 seconds
Started Jul 16 05:22:59 PM PDT 24
Finished Jul 16 05:23:05 PM PDT 24
Peak memory 205544 kb
Host smart-5ee17d37-a172-400b-8024-e77ce254d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729881502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1729881502
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.3796911295
Short name T130
Test name
Test status
Simulation time 53600049 ps
CPU time 0.67 seconds
Started Jul 16 05:32:13 PM PDT 24
Finished Jul 16 05:32:14 PM PDT 24
Peak memory 205212 kb
Host smart-6bb2baf0-ad72-4e21-925b-0785a8963ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796911295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3796911295
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3120769178
Short name T1718
Test name
Test status
Simulation time 316482223 ps
CPU time 1.72 seconds
Started Jul 16 05:32:02 PM PDT 24
Finished Jul 16 05:32:05 PM PDT 24
Peak memory 228004 kb
Host smart-3fb36e52-c3e8-43ca-9a68-8cb79afbc268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120769178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3120769178
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.2062755127
Short name T307
Test name
Test status
Simulation time 89088810 ps
CPU time 2.27 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 229720 kb
Host smart-23d621bc-830b-425c-b8c1-2d6bb0915047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062755127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.2062755127
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1747413497
Short name T900
Test name
Test status
Simulation time 1859640978 ps
CPU time 28.57 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:29 PM PDT 24
Peak memory 329600 kb
Host smart-00c46e49-f210-4c4c-8794-d42bd99b8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747413497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1747413497
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1047893629
Short name T79
Test name
Test status
Simulation time 1026287185 ps
CPU time 3.29 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:10 PM PDT 24
Peak memory 214588 kb
Host smart-1e9504bc-afd6-4771-854d-2f567852f37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047893629 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1047893629
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3348870715
Short name T1295
Test name
Test status
Simulation time 668016543 ps
CPU time 1.6 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 213840 kb
Host smart-58c937ca-3791-45bc-ac15-e99e1a2f3869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348870715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3348870715
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1508617848
Short name T1522
Test name
Test status
Simulation time 2210854464 ps
CPU time 1.14 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:07 PM PDT 24
Peak memory 205476 kb
Host smart-7eac2d65-e65a-4cfc-b27e-8ffaa9a55354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508617848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1508617848
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.4074276007
Short name T997
Test name
Test status
Simulation time 1348881851 ps
CPU time 2.07 seconds
Started Jul 16 05:23:19 PM PDT 24
Finished Jul 16 05:23:21 PM PDT 24
Peak memory 205468 kb
Host smart-f464f8e4-7578-4e26-87a2-d3d09b28e38e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074276007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.4074276007
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2152772121
Short name T1266
Test name
Test status
Simulation time 162777900 ps
CPU time 1 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:10 PM PDT 24
Peak memory 205364 kb
Host smart-747a8ea2-5c0c-4b3b-8932-9d46e71c6d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152772121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2152772121
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.487466576
Short name T641
Test name
Test status
Simulation time 2039717595 ps
CPU time 5.16 seconds
Started Jul 16 05:23:07 PM PDT 24
Finished Jul 16 05:23:13 PM PDT 24
Peak memory 215408 kb
Host smart-06a5ac70-25ae-4d04-9756-5f278bd200de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487466576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.487466576
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2493622143
Short name T1408
Test name
Test status
Simulation time 11741027884 ps
CPU time 13.14 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:24 PM PDT 24
Peak memory 362820 kb
Host smart-3b925458-2400-4734-8509-0723279ec895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493622143 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2493622143
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.3236903820
Short name T1516
Test name
Test status
Simulation time 523290162 ps
CPU time 2.84 seconds
Started Jul 16 05:23:26 PM PDT 24
Finished Jul 16 05:23:30 PM PDT 24
Peak memory 213876 kb
Host smart-ce3abbd7-2c9d-477a-bcf7-efe7bf499393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236903820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.3236903820
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.1630800473
Short name T472
Test name
Test status
Simulation time 1624420000 ps
CPU time 1.36 seconds
Started Jul 16 05:23:05 PM PDT 24
Finished Jul 16 05:23:07 PM PDT 24
Peak memory 222384 kb
Host smart-e1d6c88a-049b-4380-b3f1-d317645c4ceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630800473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_nack_txstretch.1630800473
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.1495639581
Short name T1292
Test name
Test status
Simulation time 601646911 ps
CPU time 4.84 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:15 PM PDT 24
Peak memory 221892 kb
Host smart-282d1bed-3e8d-4c2c-8579-6d867de7a368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495639581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.1495639581
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2313882709
Short name T1396
Test name
Test status
Simulation time 1628415256 ps
CPU time 2.01 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:16 PM PDT 24
Peak memory 205360 kb
Host smart-a05bd1a9-a3a0-492d-9c03-b53073a1eab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313882709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2313882709
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2074818557
Short name T180
Test name
Test status
Simulation time 1619446694 ps
CPU time 13.65 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 213668 kb
Host smart-8bb2dec1-6291-4b08-a32f-7118ff5a8bbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074818557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2074818557
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.3196654888
Short name T1283
Test name
Test status
Simulation time 7201143691 ps
CPU time 34.41 seconds
Started Jul 16 05:23:05 PM PDT 24
Finished Jul 16 05:23:41 PM PDT 24
Peak memory 266784 kb
Host smart-673e6698-07c3-4163-adc0-333d8dfb0794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196654888 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.3196654888
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3553493576
Short name T1208
Test name
Test status
Simulation time 993459346 ps
CPU time 43.14 seconds
Started Jul 16 05:32:03 PM PDT 24
Finished Jul 16 05:32:47 PM PDT 24
Peak memory 214012 kb
Host smart-bdcc9a01-3cb1-40e2-b06c-2c04542bd430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553493576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3553493576
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3574768819
Short name T1296
Test name
Test status
Simulation time 56918031117 ps
CPU time 120.06 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 1460744 kb
Host smart-4b6bcdd3-6956-4d27-bd02-03ef574bc663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574768819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3574768819
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.176637804
Short name T1206
Test name
Test status
Simulation time 3629833105 ps
CPU time 10.37 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:15 PM PDT 24
Peak memory 239916 kb
Host smart-00b23c3e-c66a-4b65-bb8f-4694605a38e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176637804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.176637804
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3828673135
Short name T1675
Test name
Test status
Simulation time 4407737923 ps
CPU time 6.83 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 232348 kb
Host smart-e47095fc-cb16-4851-a56e-014eba0ac038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828673135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3828673135
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.3584029247
Short name T1217
Test name
Test status
Simulation time 66359623 ps
CPU time 1.34 seconds
Started Jul 16 05:23:11 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 205600 kb
Host smart-eeca114d-0f05-4568-9f71-6802d8ab96ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584029247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.3584029247
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.676547153
Short name T1413
Test name
Test status
Simulation time 210603903 ps
CPU time 1.38 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 213816 kb
Host smart-098bb703-1fea-44cf-8079-2cb444240be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676547153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.676547153
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2855120906
Short name T322
Test name
Test status
Simulation time 926825380 ps
CPU time 4.35 seconds
Started Jul 16 05:23:13 PM PDT 24
Finished Jul 16 05:23:18 PM PDT 24
Peak memory 253376 kb
Host smart-46284405-6721-4bc7-91f0-365ec7155cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855120906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2855120906
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3018035551
Short name T536
Test name
Test status
Simulation time 1808961717 ps
CPU time 42.44 seconds
Started Jul 16 05:23:07 PM PDT 24
Finished Jul 16 05:23:50 PM PDT 24
Peak memory 325860 kb
Host smart-27ca07ab-de9d-4717-9bea-232e9355c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018035551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3018035551
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.95461821
Short name T160
Test name
Test status
Simulation time 7710288898 ps
CPU time 110.75 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 610548 kb
Host smart-03588494-b16a-4202-8e61-f26756368151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95461821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.95461821
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.955030767
Short name T1110
Test name
Test status
Simulation time 78050843 ps
CPU time 0.82 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 205264 kb
Host smart-69835eb5-07cf-4387-a496-e6cb8ab466b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955030767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.955030767
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2883956104
Short name T390
Test name
Test status
Simulation time 983139352 ps
CPU time 3.93 seconds
Started Jul 16 05:26:46 PM PDT 24
Finished Jul 16 05:26:50 PM PDT 24
Peak memory 205468 kb
Host smart-7632e81c-73cc-4e6c-8447-014e2f6fdcf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883956104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2883956104
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2245030888
Short name T1158
Test name
Test status
Simulation time 5367619987 ps
CPU time 62.49 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:24:14 PM PDT 24
Peak memory 876088 kb
Host smart-e28238d0-1764-45a0-8a95-6d6024688db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245030888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2245030888
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1471518186
Short name T232
Test name
Test status
Simulation time 526844038 ps
CPU time 21.56 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:25 PM PDT 24
Peak memory 205188 kb
Host smart-f9809da1-b7f9-4970-9d1c-207e875dd924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471518186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1471518186
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.522537302
Short name T1250
Test name
Test status
Simulation time 72266740 ps
CPU time 1.26 seconds
Started Jul 16 05:23:14 PM PDT 24
Finished Jul 16 05:23:16 PM PDT 24
Peak memory 213752 kb
Host smart-86995d3e-40d8-41d0-9109-2d06770db8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522537302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.522537302
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3485177756
Short name T1220
Test name
Test status
Simulation time 25768536 ps
CPU time 0.7 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 205140 kb
Host smart-17b0a5ef-ea22-4680-b93e-672e001abe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485177756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3485177756
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1834154503
Short name T1138
Test name
Test status
Simulation time 1171808943 ps
CPU time 7.36 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:18 PM PDT 24
Peak memory 226252 kb
Host smart-fc4aa964-f04b-4ef6-ae51-0539fc6c274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834154503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1834154503
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.847602064
Short name T635
Test name
Test status
Simulation time 490316216 ps
CPU time 3.62 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:17 PM PDT 24
Peak memory 205500 kb
Host smart-5488ba65-0746-467c-a959-3d7a6eeddd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847602064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.847602064
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2241665209
Short name T466
Test name
Test status
Simulation time 5297032538 ps
CPU time 59.5 seconds
Started Jul 16 05:23:13 PM PDT 24
Finished Jul 16 05:24:14 PM PDT 24
Peak memory 297724 kb
Host smart-fef538fe-57bf-45d2-8a0d-aef3c3076ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241665209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2241665209
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4008951000
Short name T34
Test name
Test status
Simulation time 32486421284 ps
CPU time 1132.26 seconds
Started Jul 16 05:23:11 PM PDT 24
Finished Jul 16 05:42:04 PM PDT 24
Peak memory 3048856 kb
Host smart-ca962fe2-46f0-4c0f-88e2-99cfbf698957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008951000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4008951000
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1510303369
Short name T1153
Test name
Test status
Simulation time 674527856 ps
CPU time 15.21 seconds
Started Jul 16 05:23:11 PM PDT 24
Finished Jul 16 05:23:28 PM PDT 24
Peak memory 213660 kb
Host smart-238c2439-6fad-4ae7-ac7a-e66d8c80d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510303369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1510303369
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2045787699
Short name T896
Test name
Test status
Simulation time 3535785775 ps
CPU time 4.16 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 217008 kb
Host smart-f9a23811-ddd0-43ce-bf9f-df810bcadf5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045787699 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2045787699
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1170670285
Short name T1187
Test name
Test status
Simulation time 157043209 ps
CPU time 1.02 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 205448 kb
Host smart-82f1e5b8-9d72-4140-9b2a-be3b3fcf7c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170670285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1170670285
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.858379506
Short name T1519
Test name
Test status
Simulation time 360277502 ps
CPU time 0.93 seconds
Started Jul 16 05:23:07 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 205384 kb
Host smart-13478b25-163f-4276-9ed5-595f8a8bb007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858379506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.858379506
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.1725011696
Short name T1551
Test name
Test status
Simulation time 2787384517 ps
CPU time 3.6 seconds
Started Jul 16 05:23:17 PM PDT 24
Finished Jul 16 05:23:21 PM PDT 24
Peak memory 205672 kb
Host smart-4d1970f1-4366-4986-9c23-8b659c9028d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725011696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.1725011696
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.3808550578
Short name T324
Test name
Test status
Simulation time 380304702 ps
CPU time 1.1 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 205416 kb
Host smart-24dd899d-8848-4b0d-8461-aa76008bbc31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808550578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3808550578
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3717145458
Short name T748
Test name
Test status
Simulation time 7519125309 ps
CPU time 17.58 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:29 PM PDT 24
Peak memory 274092 kb
Host smart-5b698831-a3d8-4bc4-a1e1-e7c6d25fd3ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717145458 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3717145458
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.1694814319
Short name T916
Test name
Test status
Simulation time 474721740 ps
CPU time 2.74 seconds
Started Jul 16 05:23:15 PM PDT 24
Finished Jul 16 05:23:18 PM PDT 24
Peak memory 213864 kb
Host smart-9d8892d3-841c-4291-b880-c050f093a180
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694814319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.1694814319
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.1867416696
Short name T715
Test name
Test status
Simulation time 3427155015 ps
CPU time 2.34 seconds
Started Jul 16 05:23:08 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 205756 kb
Host smart-049ed229-8c31-4ba4-9cd1-d3c79d022fae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867416696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.1867416696
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.3621192845
Short name T1156
Test name
Test status
Simulation time 1171747234 ps
CPU time 3.55 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:17 PM PDT 24
Peak memory 213816 kb
Host smart-cb75d791-0a4b-4d30-b792-0baca853db4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621192845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.3621192845
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.2755636844
Short name T505
Test name
Test status
Simulation time 1998220425 ps
CPU time 2.33 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:16 PM PDT 24
Peak memory 205464 kb
Host smart-df0d0750-872c-4192-8d9a-432ea629e435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755636844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.2755636844
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3832752960
Short name T1650
Test name
Test status
Simulation time 1291159582 ps
CPU time 15.81 seconds
Started Jul 16 05:23:19 PM PDT 24
Finished Jul 16 05:23:35 PM PDT 24
Peak memory 213824 kb
Host smart-32f418c8-8a78-409d-8974-18cff880a96b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832752960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3832752960
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.813142761
Short name T517
Test name
Test status
Simulation time 32024774066 ps
CPU time 42.59 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 632620 kb
Host smart-fbf2886d-5169-470b-89d3-2406692417de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813142761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.813142761
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.735803791
Short name T895
Test name
Test status
Simulation time 3791543829 ps
CPU time 16.27 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:29 PM PDT 24
Peak memory 221916 kb
Host smart-fb40b2df-43e0-4e76-8669-823c939ae32e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735803791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.735803791
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.210634846
Short name T563
Test name
Test status
Simulation time 33594019748 ps
CPU time 51.73 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:27:02 PM PDT 24
Peak memory 960156 kb
Host smart-e97d5805-0613-4e5c-8c17-dd9b99a00ea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210634846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.210634846
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.720719778
Short name T1225
Test name
Test status
Simulation time 1203268265 ps
CPU time 14.67 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:38 PM PDT 24
Peak memory 399140 kb
Host smart-ce4b76b5-571c-4f09-9962-9ad8bbc95c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720719778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.720719778
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2861447487
Short name T642
Test name
Test status
Simulation time 1183434592 ps
CPU time 7.06 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:19 PM PDT 24
Peak memory 238384 kb
Host smart-a6c0555f-def9-4b6c-b5af-5c86998170a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861447487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2861447487
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.811561574
Short name T1684
Test name
Test status
Simulation time 138092329 ps
CPU time 2.96 seconds
Started Jul 16 05:32:07 PM PDT 24
Finished Jul 16 05:32:11 PM PDT 24
Peak memory 205628 kb
Host smart-299d340c-36e9-4219-beb9-cc3bcc032491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811561574 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.811561574
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2861733867
Short name T661
Test name
Test status
Simulation time 31826715 ps
CPU time 0.6 seconds
Started Jul 16 05:23:24 PM PDT 24
Finished Jul 16 05:23:25 PM PDT 24
Peak memory 204792 kb
Host smart-79f3d458-fdbc-43e7-a241-b6e609d3977a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861733867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2861733867
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3705607636
Short name T504
Test name
Test status
Simulation time 458956576 ps
CPU time 1.88 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:13 PM PDT 24
Peak memory 214860 kb
Host smart-c8318ff3-6a6b-4d4f-9bf7-1917cf78764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705607636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3705607636
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1719478635
Short name T753
Test name
Test status
Simulation time 426519262 ps
CPU time 8.08 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:12 PM PDT 24
Peak memory 292572 kb
Host smart-03ef2025-1ea8-4b62-b86a-baad6e7e8e9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719478635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1719478635
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1754462240
Short name T1141
Test name
Test status
Simulation time 21245329876 ps
CPU time 228.74 seconds
Started Jul 16 05:23:18 PM PDT 24
Finished Jul 16 05:27:07 PM PDT 24
Peak memory 670680 kb
Host smart-fdd8a4d5-0c9b-4a05-b3e6-a644bdfd9492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754462240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1754462240
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1916671583
Short name T660
Test name
Test status
Simulation time 1757902768 ps
CPU time 55.59 seconds
Started Jul 16 05:23:18 PM PDT 24
Finished Jul 16 05:24:15 PM PDT 24
Peak memory 621920 kb
Host smart-82650bdd-63cb-45f3-bae5-3d711d43c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916671583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1916671583
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2546508631
Short name T1199
Test name
Test status
Simulation time 503080693 ps
CPU time 1.09 seconds
Started Jul 16 05:23:13 PM PDT 24
Finished Jul 16 05:23:16 PM PDT 24
Peak memory 205260 kb
Host smart-5d019a51-2fbb-4cf2-bbde-b46a5b4d7bd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546508631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2546508631
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2043016468
Short name T1039
Test name
Test status
Simulation time 209182638 ps
CPU time 10.25 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:14 PM PDT 24
Peak memory 205456 kb
Host smart-afff7e65-080b-47af-92ad-77ee3cf7d1e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043016468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2043016468
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2229959479
Short name T367
Test name
Test status
Simulation time 5527347027 ps
CPU time 74.3 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:24:25 PM PDT 24
Peak memory 862732 kb
Host smart-e796e6f0-9845-476f-be85-77b4fc970233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229959479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2229959479
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.677199546
Short name T1151
Test name
Test status
Simulation time 420454926 ps
CPU time 16.37 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:23:40 PM PDT 24
Peak memory 205340 kb
Host smart-c0e177bf-a207-4ea9-a1c1-4881388d21a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677199546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.677199546
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2309157183
Short name T1385
Test name
Test status
Simulation time 92695532 ps
CPU time 1.38 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:27:37 PM PDT 24
Peak memory 213624 kb
Host smart-8b53081c-eea0-436b-92d7-2546ab94227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309157183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2309157183
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.4018253883
Short name T1620
Test name
Test status
Simulation time 27969257 ps
CPU time 0.67 seconds
Started Jul 16 05:23:12 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 205248 kb
Host smart-c9047d2e-0ac9-405c-a0ac-febcf17f4fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018253883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4018253883
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1982962569
Short name T985
Test name
Test status
Simulation time 49230135032 ps
CPU time 2701.51 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 06:08:14 PM PDT 24
Peak memory 4057376 kb
Host smart-5f458fef-70f9-4197-aeeb-99c7fb1feda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982962569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1982962569
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.2160473630
Short name T734
Test name
Test status
Simulation time 269258670 ps
CPU time 3.31 seconds
Started Jul 16 05:23:16 PM PDT 24
Finished Jul 16 05:23:20 PM PDT 24
Peak memory 223872 kb
Host smart-8f0038a6-92e5-4d7b-98e0-f37b39b3ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160473630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2160473630
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.403388050
Short name T532
Test name
Test status
Simulation time 2111812304 ps
CPU time 102.68 seconds
Started Jul 16 05:23:19 PM PDT 24
Finished Jul 16 05:25:02 PM PDT 24
Peak memory 460108 kb
Host smart-774c4033-b7e8-49d4-a8d1-8ceb511496e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403388050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.403388050
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3411162632
Short name T589
Test name
Test status
Simulation time 1091661130 ps
CPU time 23.49 seconds
Started Jul 16 05:23:13 PM PDT 24
Finished Jul 16 05:23:38 PM PDT 24
Peak memory 213752 kb
Host smart-b94c92d1-fa35-42b3-936f-87874ac365cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411162632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3411162632
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3654801334
Short name T1544
Test name
Test status
Simulation time 1001057041 ps
CPU time 3.59 seconds
Started Jul 16 05:23:20 PM PDT 24
Finished Jul 16 05:23:24 PM PDT 24
Peak memory 213780 kb
Host smart-75711953-1e6c-4d80-8586-a5e2f669e8aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654801334 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3654801334
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3014343611
Short name T1669
Test name
Test status
Simulation time 306443011 ps
CPU time 0.8 seconds
Started Jul 16 05:27:33 PM PDT 24
Finished Jul 16 05:27:35 PM PDT 24
Peak memory 205308 kb
Host smart-575e92bc-3b14-4174-80d6-539878d5b595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014343611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3014343611
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2241487679
Short name T796
Test name
Test status
Simulation time 264800006 ps
CPU time 1.56 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 205572 kb
Host smart-2547e11e-6f00-40af-950b-4e45bd6bd32e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241487679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2241487679
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.631233663
Short name T1089
Test name
Test status
Simulation time 281209968 ps
CPU time 1.68 seconds
Started Jul 16 05:26:52 PM PDT 24
Finished Jul 16 05:26:54 PM PDT 24
Peak memory 205396 kb
Host smart-a4bb7adf-0a21-4b7e-9987-089719cc9746
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631233663 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.631233663
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.1923101562
Short name T713
Test name
Test status
Simulation time 251431195 ps
CPU time 1.17 seconds
Started Jul 16 05:23:21 PM PDT 24
Finished Jul 16 05:23:23 PM PDT 24
Peak memory 205336 kb
Host smart-3cabc8ac-23d0-40e7-8c61-6dd64abae3f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923101562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.1923101562
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3250353757
Short name T1724
Test name
Test status
Simulation time 3628500170 ps
CPU time 5.81 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 221608 kb
Host smart-1910a05a-52b4-4869-9e2a-b37b243c1aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250353757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3250353757
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1000001911
Short name T1033
Test name
Test status
Simulation time 6851536548 ps
CPU time 11.97 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:23 PM PDT 24
Peak memory 497552 kb
Host smart-715eecda-6f9e-4436-8fae-d9d64a3c1f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000001911 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1000001911
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.567330224
Short name T435
Test name
Test status
Simulation time 11251820706 ps
CPU time 2.81 seconds
Started Jul 16 05:23:21 PM PDT 24
Finished Jul 16 05:23:24 PM PDT 24
Peak memory 213948 kb
Host smart-a8976a9d-35cc-43c7-b45a-7cfa852b985b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567330224 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_nack_acqfull.567330224
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.2585330138
Short name T1038
Test name
Test status
Simulation time 978323490 ps
CPU time 2.47 seconds
Started Jul 16 05:28:28 PM PDT 24
Finished Jul 16 05:28:30 PM PDT 24
Peak memory 205628 kb
Host smart-ab2c1707-858e-444a-9590-7ce0f3218a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585330138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.2585330138
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.3910130191
Short name T1511
Test name
Test status
Simulation time 1058176215 ps
CPU time 1.41 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:23:25 PM PDT 24
Peak memory 222132 kb
Host smart-7a3367dd-81ff-4830-b117-a697c846387f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910130191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.3910130191
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/12.i2c_target_perf.1612557548
Short name T138
Test name
Test status
Simulation time 1257406597 ps
CPU time 5.03 seconds
Started Jul 16 05:23:14 PM PDT 24
Finished Jul 16 05:23:20 PM PDT 24
Peak memory 222008 kb
Host smart-d9652eab-ec72-48ba-97a2-c4003d65dc37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612557548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.1612557548
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.712170702
Short name T708
Test name
Test status
Simulation time 472598523 ps
CPU time 2.21 seconds
Started Jul 16 05:28:28 PM PDT 24
Finished Jul 16 05:28:30 PM PDT 24
Peak memory 205440 kb
Host smart-0593ed52-80c0-43aa-ade6-033e26b13e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712170702 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_smbus_maxlen.712170702
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.245653459
Short name T1626
Test name
Test status
Simulation time 4676102734 ps
CPU time 38.41 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:49 PM PDT 24
Peak memory 213808 kb
Host smart-ceef086b-db93-4fb3-b57f-f1fad4757ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245653459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.245653459
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2128006106
Short name T564
Test name
Test status
Simulation time 57288783273 ps
CPU time 303.67 seconds
Started Jul 16 05:23:21 PM PDT 24
Finished Jul 16 05:28:25 PM PDT 24
Peak memory 1838236 kb
Host smart-6e244c36-27e7-4954-bf0a-8f235630c514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128006106 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2128006106
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1615437563
Short name T1389
Test name
Test status
Simulation time 5825317716 ps
CPU time 64.02 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:24:15 PM PDT 24
Peak memory 218240 kb
Host smart-e94ade60-615d-4cd0-9eb9-27c5fc2f4c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615437563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1615437563
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1239846237
Short name T976
Test name
Test status
Simulation time 25850344975 ps
CPU time 104.34 seconds
Started Jul 16 05:23:14 PM PDT 24
Finished Jul 16 05:25:00 PM PDT 24
Peak memory 1455064 kb
Host smart-cff36e06-8a93-4154-a830-827a8ae7a945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239846237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1239846237
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.380500796
Short name T422
Test name
Test status
Simulation time 4436097383 ps
CPU time 8.5 seconds
Started Jul 16 05:26:46 PM PDT 24
Finished Jul 16 05:26:55 PM PDT 24
Peak memory 291192 kb
Host smart-e7178513-a5e7-4d56-bb90-5cd19543ff28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380500796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.380500796
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1771882921
Short name T1381
Test name
Test status
Simulation time 5605641198 ps
CPU time 6.76 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 220112 kb
Host smart-71b4df12-1f07-4dbd-8d1d-c4845d4f00d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771882921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1771882921
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2680867361
Short name T1331
Test name
Test status
Simulation time 185345292 ps
CPU time 3.12 seconds
Started Jul 16 05:23:25 PM PDT 24
Finished Jul 16 05:23:28 PM PDT 24
Peak memory 205632 kb
Host smart-64f81276-0e03-41b6-9490-ea70c86bc932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680867361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2680867361
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3539282449
Short name T1682
Test name
Test status
Simulation time 23148740 ps
CPU time 0.65 seconds
Started Jul 16 05:23:31 PM PDT 24
Finished Jul 16 05:23:32 PM PDT 24
Peak memory 204896 kb
Host smart-db4cb28b-f985-4e62-a6a8-c18c83ae51c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539282449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3539282449
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3737793112
Short name T1148
Test name
Test status
Simulation time 190074536 ps
CPU time 3.36 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 239876 kb
Host smart-0da5b40a-ba78-4458-ae00-f2c4aa3f610e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737793112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3737793112
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.234667876
Short name T726
Test name
Test status
Simulation time 6841677283 ps
CPU time 84.88 seconds
Started Jul 16 05:23:19 PM PDT 24
Finished Jul 16 05:24:44 PM PDT 24
Peak memory 458352 kb
Host smart-0080fbc8-6147-4f88-9d0d-2e8a8e2848d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234667876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.234667876
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2340303907
Short name T620
Test name
Test status
Simulation time 4708695885 ps
CPU time 72.18 seconds
Started Jul 16 05:31:56 PM PDT 24
Finished Jul 16 05:33:08 PM PDT 24
Peak memory 656900 kb
Host smart-cf3af334-6a52-434b-bd80-b804dcc64cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340303907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2340303907
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1352358580
Short name T497
Test name
Test status
Simulation time 138173926 ps
CPU time 1.22 seconds
Started Jul 16 05:23:24 PM PDT 24
Finished Jul 16 05:23:26 PM PDT 24
Peak memory 205256 kb
Host smart-e69c5481-5447-4eb1-8b22-91a969fc3fc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352358580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1352358580
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1123832056
Short name T1644
Test name
Test status
Simulation time 425857349 ps
CPU time 11.78 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 248572 kb
Host smart-c93b1cd2-db4d-4dff-a43a-62de49b45de6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123832056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1123832056
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1070234873
Short name T1006
Test name
Test status
Simulation time 33501771731 ps
CPU time 159.26 seconds
Started Jul 16 05:23:27 PM PDT 24
Finished Jul 16 05:26:07 PM PDT 24
Peak memory 1344072 kb
Host smart-b5dc957d-529d-4bef-b737-02ec8c59dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070234873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1070234873
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3063428151
Short name T241
Test name
Test status
Simulation time 380262879 ps
CPU time 5.11 seconds
Started Jul 16 05:23:25 PM PDT 24
Finished Jul 16 05:23:31 PM PDT 24
Peak memory 205692 kb
Host smart-dc8d318a-c963-41cd-b435-bf61fcf7dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063428151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3063428151
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.300869404
Short name T1073
Test name
Test status
Simulation time 32403044 ps
CPU time 0.68 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:11 PM PDT 24
Peak memory 205104 kb
Host smart-cb67c95b-850b-4259-a948-bedd443015b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300869404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.300869404
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3444124158
Short name T1727
Test name
Test status
Simulation time 29035870576 ps
CPU time 31.63 seconds
Started Jul 16 05:23:22 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 229116 kb
Host smart-f5bafc70-f756-4232-a42c-d3d98446f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444124158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3444124158
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.3558219843
Short name T1063
Test name
Test status
Simulation time 2570071826 ps
CPU time 25.38 seconds
Started Jul 16 05:26:52 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 472224 kb
Host smart-0fb2dbc2-ad75-496e-be55-ec8b2cb00d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558219843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.3558219843
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2085853288
Short name T533
Test name
Test status
Simulation time 1476001477 ps
CPU time 70.62 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:24:35 PM PDT 24
Peak memory 361724 kb
Host smart-444ec74f-76c7-4642-b1c8-d5f791d2c082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085853288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2085853288
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.655445852
Short name T1705
Test name
Test status
Simulation time 1415735026 ps
CPU time 30.53 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 213716 kb
Host smart-6fe50569-ef13-4b8c-82a6-0314fb6bad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655445852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.655445852
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3961093333
Short name T389
Test name
Test status
Simulation time 720878829 ps
CPU time 4.4 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:23:28 PM PDT 24
Peak memory 215132 kb
Host smart-9eb5e0a1-6e88-449d-ba6e-376156c260a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961093333 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3961093333
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1634841850
Short name T1655
Test name
Test status
Simulation time 176606661 ps
CPU time 0.85 seconds
Started Jul 16 05:23:26 PM PDT 24
Finished Jul 16 05:23:27 PM PDT 24
Peak memory 205452 kb
Host smart-d6f04f8c-4476-4125-a88f-2bb24875e520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634841850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1634841850
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.884816412
Short name T333
Test name
Test status
Simulation time 229165106 ps
CPU time 1.27 seconds
Started Jul 16 05:28:05 PM PDT 24
Finished Jul 16 05:28:07 PM PDT 24
Peak memory 205320 kb
Host smart-863e73c7-88c4-4b9f-8774-d35c45901dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884816412 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.884816412
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3327737320
Short name T262
Test name
Test status
Simulation time 446953646 ps
CPU time 2.37 seconds
Started Jul 16 05:23:43 PM PDT 24
Finished Jul 16 05:23:46 PM PDT 24
Peak memory 205520 kb
Host smart-6c75d38f-b0a5-4cd0-b93b-e8f5927fb2e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327737320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3327737320
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2782099515
Short name T1665
Test name
Test status
Simulation time 696606483 ps
CPU time 0.89 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:35 PM PDT 24
Peak memory 205368 kb
Host smart-d938c311-11e3-4b13-b6b3-0b0d4062987b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782099515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2782099515
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1203719825
Short name T837
Test name
Test status
Simulation time 1268731169 ps
CPU time 2.55 seconds
Started Jul 16 05:28:04 PM PDT 24
Finished Jul 16 05:28:07 PM PDT 24
Peak memory 213676 kb
Host smart-7fa8eb9b-108b-4531-a746-ccb4d0757518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203719825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1203719825
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3563152184
Short name T908
Test name
Test status
Simulation time 3049401489 ps
CPU time 4.72 seconds
Started Jul 16 05:23:23 PM PDT 24
Finished Jul 16 05:23:28 PM PDT 24
Peak memory 218780 kb
Host smart-e9f04619-209e-456b-9c2b-25b5fd245534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563152184 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3563152184
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2640976337
Short name T340
Test name
Test status
Simulation time 7455299276 ps
CPU time 16.57 seconds
Started Jul 16 05:23:27 PM PDT 24
Finished Jul 16 05:23:44 PM PDT 24
Peak memory 261004 kb
Host smart-95fca64e-bfb4-4fb5-b6b7-9f556a582258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640976337 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2640976337
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.1871285662
Short name T1163
Test name
Test status
Simulation time 528942605 ps
CPU time 2.7 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 213440 kb
Host smart-05afeb0b-e751-48b1-b99f-10cd3469fa2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871285662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.1871285662
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.448232194
Short name T1507
Test name
Test status
Simulation time 2265977244 ps
CPU time 2.97 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:23:43 PM PDT 24
Peak memory 205692 kb
Host smart-61602ec1-68b4-48a7-90c2-0c27d183877e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448232194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.448232194
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.2192985782
Short name T65
Test name
Test status
Simulation time 520099118 ps
CPU time 1.6 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:23:35 PM PDT 24
Peak memory 222188 kb
Host smart-e5b586fe-c87b-4756-85ea-4dc1f9e8ddbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192985782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_txstretch.2192985782
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.1082504202
Short name T1652
Test name
Test status
Simulation time 3830568261 ps
CPU time 6.69 seconds
Started Jul 16 05:23:21 PM PDT 24
Finished Jul 16 05:23:28 PM PDT 24
Peak memory 234100 kb
Host smart-dd118eed-b8cc-433a-b57c-1d5fa4767efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082504202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.1082504202
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.461403547
Short name T485
Test name
Test status
Simulation time 977991758 ps
CPU time 2.3 seconds
Started Jul 16 05:23:32 PM PDT 24
Finished Jul 16 05:23:35 PM PDT 24
Peak memory 205372 kb
Host smart-e576bd1d-6a31-41e2-bdb4-1030045d783e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461403547 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_smbus_maxlen.461403547
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.325587483
Short name T836
Test name
Test status
Simulation time 5644229220 ps
CPU time 20.13 seconds
Started Jul 16 05:23:25 PM PDT 24
Finished Jul 16 05:23:45 PM PDT 24
Peak memory 213856 kb
Host smart-ac11ddd2-9294-4349-bd78-982f9b1587c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325587483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.325587483
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.1187184613
Short name T300
Test name
Test status
Simulation time 15569217378 ps
CPU time 60.48 seconds
Started Jul 16 05:28:28 PM PDT 24
Finished Jul 16 05:29:28 PM PDT 24
Peak memory 940060 kb
Host smart-16496dda-d065-4245-8019-91e4d5cd9a91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187184613 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.1187184613
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3048863555
Short name T1697
Test name
Test status
Simulation time 1172972216 ps
CPU time 5.25 seconds
Started Jul 16 05:23:25 PM PDT 24
Finished Jul 16 05:23:31 PM PDT 24
Peak memory 205836 kb
Host smart-411dd06f-6a06-4818-affe-87c25c48a729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048863555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3048863555
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1897453757
Short name T854
Test name
Test status
Simulation time 53990223329 ps
CPU time 791.39 seconds
Started Jul 16 05:23:25 PM PDT 24
Finished Jul 16 05:36:37 PM PDT 24
Peak memory 5821396 kb
Host smart-5e0d0510-5176-47df-a64a-c387af7a63cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897453757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1897453757
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.372273474
Short name T392
Test name
Test status
Simulation time 1950932462 ps
CPU time 2.11 seconds
Started Jul 16 05:23:24 PM PDT 24
Finished Jul 16 05:23:26 PM PDT 24
Peak memory 213828 kb
Host smart-c42c1d66-6a35-4fce-ad46-435ce0d9f244
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372273474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.372273474
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.704690306
Short name T325
Test name
Test status
Simulation time 1059671892 ps
CPU time 6.89 seconds
Started Jul 16 05:23:26 PM PDT 24
Finished Jul 16 05:23:33 PM PDT 24
Peak memory 230132 kb
Host smart-d35c3bdc-d926-44f1-a539-4ac4103bb6d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704690306 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.704690306
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.2317140461
Short name T1416
Test name
Test status
Simulation time 399938931 ps
CPU time 5.8 seconds
Started Jul 16 05:23:36 PM PDT 24
Finished Jul 16 05:23:43 PM PDT 24
Peak memory 205516 kb
Host smart-6d402aa6-05a4-4920-b287-3333ce7e2516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317140461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2317140461
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2607351223
Short name T327
Test name
Test status
Simulation time 32109024 ps
CPU time 0.64 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:37 PM PDT 24
Peak memory 204692 kb
Host smart-e16f87b2-ff5f-41e0-b7d6-1f1f7a4d7b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607351223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2607351223
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2292725443
Short name T1365
Test name
Test status
Simulation time 218220555 ps
CPU time 1.52 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:36 PM PDT 24
Peak memory 217312 kb
Host smart-86a30c18-4cdb-4c30-87c0-7e793592e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292725443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2292725443
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1629596441
Short name T870
Test name
Test status
Simulation time 1002788203 ps
CPU time 9.53 seconds
Started Jul 16 05:23:37 PM PDT 24
Finished Jul 16 05:23:47 PM PDT 24
Peak memory 316584 kb
Host smart-296cfb13-f54c-4290-b4af-ddf6a4b3aef1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629596441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1629596441
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1928850092
Short name T615
Test name
Test status
Simulation time 12363708604 ps
CPU time 173.91 seconds
Started Jul 16 05:23:32 PM PDT 24
Finished Jul 16 05:26:26 PM PDT 24
Peak memory 506648 kb
Host smart-0e4e4680-e1dc-4842-a469-0f184e73e7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928850092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1928850092
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.556018968
Short name T157
Test name
Test status
Simulation time 1661042084 ps
CPU time 49.43 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:24:26 PM PDT 24
Peak memory 608872 kb
Host smart-785aaff2-9e79-4b35-a024-4f96a84cbafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556018968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.556018968
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3460275343
Short name T878
Test name
Test status
Simulation time 464711930 ps
CPU time 1.2 seconds
Started Jul 16 05:23:36 PM PDT 24
Finished Jul 16 05:23:38 PM PDT 24
Peak memory 205392 kb
Host smart-c4208d5e-727f-4318-a545-64feef23ab6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460275343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3460275343
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3264010514
Short name T1709
Test name
Test status
Simulation time 11871898604 ps
CPU time 78.02 seconds
Started Jul 16 05:36:26 PM PDT 24
Finished Jul 16 05:37:44 PM PDT 24
Peak memory 945412 kb
Host smart-5c402d63-264e-401a-9a06-11a3352352cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264010514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3264010514
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1091712168
Short name T1540
Test name
Test status
Simulation time 52331792083 ps
CPU time 144.88 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:31:11 PM PDT 24
Peak memory 597820 kb
Host smart-7c4e825e-2f6c-4986-8f69-238f40f11986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091712168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1091712168
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.1118443508
Short name T417
Test name
Test status
Simulation time 5884592504 ps
CPU time 192.07 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 897648 kb
Host smart-21d7b1c5-7751-4d62-a0fa-ba218565642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118443508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1118443508
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.4281697694
Short name T637
Test name
Test status
Simulation time 1321680323 ps
CPU time 65.02 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:28:31 PM PDT 24
Peak memory 366016 kb
Host smart-aedd5456-421d-443f-a3b7-4a19b1befdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281697694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.4281697694
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3213926775
Short name T119
Test name
Test status
Simulation time 92416142535 ps
CPU time 844.26 seconds
Started Jul 16 05:32:18 PM PDT 24
Finished Jul 16 05:46:23 PM PDT 24
Peak memory 1183816 kb
Host smart-87843d3b-5fcf-4a97-96ce-50b99e33d733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213926775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3213926775
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1998365989
Short name T1198
Test name
Test status
Simulation time 3965931277 ps
CPU time 34.8 seconds
Started Jul 16 05:32:07 PM PDT 24
Finished Jul 16 05:32:42 PM PDT 24
Peak memory 213824 kb
Host smart-c8e1699e-0fd5-4646-81af-53662aac00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998365989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1998365989
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3730624475
Short name T774
Test name
Test status
Simulation time 5430951694 ps
CPU time 7.58 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:42 PM PDT 24
Peak memory 221104 kb
Host smart-d1df51ed-f1b8-402d-969c-38ce02e9de2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730624475 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3730624475
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1780897550
Short name T164
Test name
Test status
Simulation time 203182152 ps
CPU time 1.25 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:27:37 PM PDT 24
Peak memory 205392 kb
Host smart-e21d71be-442c-43c7-8a88-73835bf349da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780897550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1780897550
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.3806902915
Short name T1137
Test name
Test status
Simulation time 1842714344 ps
CPU time 2.6 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:23:42 PM PDT 24
Peak memory 205604 kb
Host smart-09006a86-5c15-4d83-982c-0ab0237d7350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806902915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.3806902915
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.209826985
Short name T1204
Test name
Test status
Simulation time 173797733 ps
CPU time 1.06 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:23:41 PM PDT 24
Peak memory 205412 kb
Host smart-907ceac4-2840-47b5-bb09-61b2bad2b012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209826985 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.209826985
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1277334540
Short name T1083
Test name
Test status
Simulation time 4399394668 ps
CPU time 6.02 seconds
Started Jul 16 05:29:04 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 213888 kb
Host smart-46a24358-5bd2-4e00-baa3-8a3bc404d72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277334540 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1277334540
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1492084066
Short name T1515
Test name
Test status
Simulation time 12470700451 ps
CPU time 105.87 seconds
Started Jul 16 05:36:39 PM PDT 24
Finished Jul 16 05:38:26 PM PDT 24
Peak memory 2032276 kb
Host smart-5cea7eec-ea07-47d3-a1de-fb28c3a247cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492084066 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1492084066
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.3533542723
Short name T875
Test name
Test status
Simulation time 520612557 ps
CPU time 2.81 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:39 PM PDT 24
Peak memory 213848 kb
Host smart-2fb5ce04-f2ae-425f-b55a-cd7b10254b90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533542723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.3533542723
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.1069369216
Short name T406
Test name
Test status
Simulation time 485094893 ps
CPU time 2.6 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:23:42 PM PDT 24
Peak memory 205628 kb
Host smart-7208baa8-4418-4478-a5d9-c95fd9f20f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069369216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.1069369216
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.1276843160
Short name T152
Test name
Test status
Simulation time 270218449 ps
CPU time 1.38 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:36 PM PDT 24
Peak memory 222436 kb
Host smart-678ae238-6285-42be-92bc-81287d0c14b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276843160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_nack_txstretch.1276843160
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.2194052084
Short name T706
Test name
Test status
Simulation time 2314255092 ps
CPU time 2.38 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:23:36 PM PDT 24
Peak memory 205500 kb
Host smart-3a6cfae3-cd2b-45e1-b185-e8f7eb6afdb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194052084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.2194052084
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3579637079
Short name T314
Test name
Test status
Simulation time 704391607 ps
CPU time 8.46 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:44 PM PDT 24
Peak memory 213808 kb
Host smart-0e72f199-a549-4beb-a05f-e84c2eeeb1d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579637079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3579637079
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.3823276045
Short name T461
Test name
Test status
Simulation time 43563333693 ps
CPU time 364.92 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:29:38 PM PDT 24
Peak memory 2746304 kb
Host smart-e277ec5b-ed5e-46d2-ae6d-8a3c889fa92c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823276045 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.3823276045
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3327463988
Short name T457
Test name
Test status
Simulation time 23345236909 ps
CPU time 25.8 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:24:02 PM PDT 24
Peak memory 230316 kb
Host smart-da7e8e6f-e5fa-41cf-9103-2cf87496923e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327463988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3327463988
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3788263982
Short name T404
Test name
Test status
Simulation time 51583799204 ps
CPU time 1322.2 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:51:05 PM PDT 24
Peak memory 7730156 kb
Host smart-f09b4921-5b74-4b0c-ab99-610dc991d48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788263982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3788263982
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3037742332
Short name T1184
Test name
Test status
Simulation time 4604702226 ps
CPU time 51.33 seconds
Started Jul 16 05:23:39 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 879828 kb
Host smart-513bc7d6-2956-4189-a620-73bb64a91717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037742332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3037742332
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.78169560
Short name T1018
Test name
Test status
Simulation time 5718441382 ps
CPU time 7.14 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:42 PM PDT 24
Peak memory 217344 kb
Host smart-25b26f2e-6044-4631-861e-057ea343e8f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78169560 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_timeout.78169560
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1074686767
Short name T1417
Test name
Test status
Simulation time 77472097 ps
CPU time 1.24 seconds
Started Jul 16 05:23:34 PM PDT 24
Finished Jul 16 05:23:36 PM PDT 24
Peak memory 205628 kb
Host smart-266e2ec3-a779-4dc3-b729-90b99d1280ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074686767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1074686767
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1174733654
Short name T782
Test name
Test status
Simulation time 16989144 ps
CPU time 0.67 seconds
Started Jul 16 05:23:49 PM PDT 24
Finished Jul 16 05:23:50 PM PDT 24
Peak memory 204836 kb
Host smart-11570824-e859-42da-9a67-64e580c76af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174733654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1174733654
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.187291363
Short name T1641
Test name
Test status
Simulation time 64065590 ps
CPU time 1.68 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:38 PM PDT 24
Peak memory 213788 kb
Host smart-bb05ab15-3fdf-413b-8fef-5d7f4cd9cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187291363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.187291363
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2514672354
Short name T980
Test name
Test status
Simulation time 444837098 ps
CPU time 22.64 seconds
Started Jul 16 05:23:41 PM PDT 24
Finished Jul 16 05:24:04 PM PDT 24
Peak memory 301728 kb
Host smart-1d2561e7-00e0-4c72-8045-f40992a619d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514672354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2514672354
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2763985492
Short name T1246
Test name
Test status
Simulation time 2377685152 ps
CPU time 70.7 seconds
Started Jul 16 05:23:42 PM PDT 24
Finished Jul 16 05:24:53 PM PDT 24
Peak memory 616408 kb
Host smart-7841eec8-67d9-4832-be3a-21c0f0a40589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763985492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2763985492
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3805738537
Short name T1628
Test name
Test status
Simulation time 3490986103 ps
CPU time 46.92 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:24:23 PM PDT 24
Peak memory 596068 kb
Host smart-822620b1-c447-404a-a2fa-7cdd7bee8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805738537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3805738537
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3889342898
Short name T850
Test name
Test status
Simulation time 464322304 ps
CPU time 1.01 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:23:37 PM PDT 24
Peak memory 205260 kb
Host smart-eaf75aa1-580e-4fd4-9e31-fb2709fc6444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889342898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3889342898
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2536843065
Short name T866
Test name
Test status
Simulation time 527874661 ps
CPU time 3.91 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:23:37 PM PDT 24
Peak memory 224916 kb
Host smart-8b844707-19b9-49b5-8abc-ac453c7cf073
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536843065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2536843065
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.158202199
Short name T978
Test name
Test status
Simulation time 16974950028 ps
CPU time 377.95 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:29:54 PM PDT 24
Peak memory 1462536 kb
Host smart-caefa03e-92e5-4b53-bfe6-e62e00bfc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158202199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.158202199
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.3958143872
Short name T1563
Test name
Test status
Simulation time 790496627 ps
CPU time 8.82 seconds
Started Jul 16 05:23:51 PM PDT 24
Finished Jul 16 05:24:00 PM PDT 24
Peak memory 205500 kb
Host smart-6627b50b-e4ac-4712-9699-161482ab792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958143872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3958143872
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.4275916172
Short name T127
Test name
Test status
Simulation time 25875550 ps
CPU time 0.66 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:23:34 PM PDT 24
Peak memory 205240 kb
Host smart-ad6f0762-b923-44c4-8199-b626e885b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275916172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.4275916172
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1398880280
Short name T1070
Test name
Test status
Simulation time 6999134495 ps
CPU time 117.09 seconds
Started Jul 16 05:23:35 PM PDT 24
Finished Jul 16 05:25:34 PM PDT 24
Peak memory 442340 kb
Host smart-c5ac8e0f-ff59-4e02-97e1-e5928cf45537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398880280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1398880280
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.4093977498
Short name T816
Test name
Test status
Simulation time 265607035 ps
CPU time 2.81 seconds
Started Jul 16 05:23:41 PM PDT 24
Finished Jul 16 05:23:45 PM PDT 24
Peak memory 205280 kb
Host smart-17d75c44-42c7-44c7-a173-281afd2c797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093977498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.4093977498
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3082250538
Short name T1324
Test name
Test status
Simulation time 2252425443 ps
CPU time 17.55 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:27:45 PM PDT 24
Peak memory 221364 kb
Host smart-2ea01f29-d0ea-48cc-9d8e-373ac8a0f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082250538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3082250538
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3540993582
Short name T351
Test name
Test status
Simulation time 1926446296 ps
CPU time 4.79 seconds
Started Jul 16 05:26:44 PM PDT 24
Finished Jul 16 05:26:49 PM PDT 24
Peak memory 213888 kb
Host smart-4d5820eb-133e-4dd4-8fee-a18b4ba1cf88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540993582 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3540993582
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2554207904
Short name T449
Test name
Test status
Simulation time 221968172 ps
CPU time 1.18 seconds
Started Jul 16 05:23:45 PM PDT 24
Finished Jul 16 05:23:46 PM PDT 24
Peak memory 205416 kb
Host smart-ee85a623-a20d-47af-920d-52bef8687ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554207904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2554207904
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.554650457
Short name T812
Test name
Test status
Simulation time 310696117 ps
CPU time 1.21 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:27 PM PDT 24
Peak memory 205376 kb
Host smart-7399a97f-45d0-4145-a458-1a0d36b4189e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554650457 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.554650457
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.447545997
Short name T1662
Test name
Test status
Simulation time 119348717 ps
CPU time 1.05 seconds
Started Jul 16 05:23:51 PM PDT 24
Finished Jul 16 05:23:53 PM PDT 24
Peak memory 205404 kb
Host smart-76da89ad-9a94-4501-9f96-5971b34c7c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447545997 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.447545997
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.566080384
Short name T297
Test name
Test status
Simulation time 581001030 ps
CPU time 1.31 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 205480 kb
Host smart-ac8a0ab9-8604-443c-963e-1699b08bf2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566080384 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.566080384
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.308366212
Short name T1612
Test name
Test status
Simulation time 559963202 ps
CPU time 3.5 seconds
Started Jul 16 05:23:50 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 219840 kb
Host smart-384428dc-9e58-4d4c-bb07-a2817fdde65c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308366212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.308366212
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.900324391
Short name T493
Test name
Test status
Simulation time 9432326556 ps
CPU time 7.02 seconds
Started Jul 16 05:23:51 PM PDT 24
Finished Jul 16 05:23:58 PM PDT 24
Peak memory 205672 kb
Host smart-faa3a7e5-cab1-405d-ba65-e3c431a6734d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900324391 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.900324391
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.3402715231
Short name T831
Test name
Test status
Simulation time 474080146 ps
CPU time 2.67 seconds
Started Jul 16 05:23:48 PM PDT 24
Finished Jul 16 05:23:52 PM PDT 24
Peak memory 213816 kb
Host smart-af3c5a57-34ed-4f62-b632-47e467453437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402715231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.3402715231
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.2936295981
Short name T421
Test name
Test status
Simulation time 2782293449 ps
CPU time 2.64 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:32:28 PM PDT 24
Peak memory 205712 kb
Host smart-4fdbdce7-ef66-48c7-a404-5fd4c13e26ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936295981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.2936295981
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.1030333389
Short name T1358
Test name
Test status
Simulation time 146061996 ps
CPU time 1.62 seconds
Started Jul 16 05:23:47 PM PDT 24
Finished Jul 16 05:23:48 PM PDT 24
Peak memory 222088 kb
Host smart-52a6d3fd-2408-4a0b-8b52-01a4851c8b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030333389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.1030333389
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/15.i2c_target_perf.3389094022
Short name T903
Test name
Test status
Simulation time 10853382647 ps
CPU time 4.62 seconds
Started Jul 16 05:32:18 PM PDT 24
Finished Jul 16 05:32:23 PM PDT 24
Peak memory 213744 kb
Host smart-c9dde4f9-2952-4044-ae1e-59c998d9d667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389094022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.3389094022
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.2515211018
Short name T1497
Test name
Test status
Simulation time 820221397 ps
CPU time 2.1 seconds
Started Jul 16 05:23:50 PM PDT 24
Finished Jul 16 05:23:52 PM PDT 24
Peak memory 205416 kb
Host smart-9ef30962-cb04-464f-b6b3-3bd64b27495f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515211018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.2515211018
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1712798255
Short name T982
Test name
Test status
Simulation time 29614446796 ps
CPU time 534.59 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:32:47 PM PDT 24
Peak memory 3813204 kb
Host smart-fd4610ed-e117-43f7-b336-9527024a0c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712798255 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1712798255
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2102324188
Short name T1587
Test name
Test status
Simulation time 391417516 ps
CPU time 6.2 seconds
Started Jul 16 05:23:50 PM PDT 24
Finished Jul 16 05:23:57 PM PDT 24
Peak memory 207132 kb
Host smart-17d56838-c0f1-4dc8-b8b4-a41012158ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102324188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2102324188
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2444269662
Short name T795
Test name
Test status
Simulation time 60398033468 ps
CPU time 1033.79 seconds
Started Jul 16 05:23:48 PM PDT 24
Finished Jul 16 05:41:04 PM PDT 24
Peak memory 6206208 kb
Host smart-a654e7d9-d2b4-4e89-b1a3-ce5e6bc88d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444269662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2444269662
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3512164698
Short name T443
Test name
Test status
Simulation time 3655742110 ps
CPU time 14.64 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:24:07 PM PDT 24
Peak memory 370940 kb
Host smart-343fe1c8-3c5c-430c-bf6d-d0ccdffe74b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512164698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3512164698
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.4007374216
Short name T1732
Test name
Test status
Simulation time 3104960117 ps
CPU time 6.81 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:23 PM PDT 24
Peak memory 213800 kb
Host smart-e4923d3a-6374-4cd7-8d85-b8b080c92bbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007374216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.4007374216
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.565182230
Short name T302
Test name
Test status
Simulation time 33835301 ps
CPU time 0.6 seconds
Started Jul 16 05:24:08 PM PDT 24
Finished Jul 16 05:24:09 PM PDT 24
Peak memory 204760 kb
Host smart-3d249aaa-ec38-44ba-aeba-1d59c035f55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565182230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.565182230
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3459300803
Short name T964
Test name
Test status
Simulation time 992311834 ps
CPU time 2.4 seconds
Started Jul 16 05:23:51 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 213656 kb
Host smart-a9e00023-382b-40e7-b459-2a2c1683b5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459300803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3459300803
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2349808607
Short name T1703
Test name
Test status
Simulation time 1122753347 ps
CPU time 28.3 seconds
Started Jul 16 05:23:54 PM PDT 24
Finished Jul 16 05:24:23 PM PDT 24
Peak memory 309180 kb
Host smart-098f6292-adb5-44c4-99a1-dab3e092cac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349808607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2349808607
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3097786966
Short name T899
Test name
Test status
Simulation time 11657482842 ps
CPU time 185.29 seconds
Started Jul 16 05:28:40 PM PDT 24
Finished Jul 16 05:31:46 PM PDT 24
Peak memory 677604 kb
Host smart-12873a59-15d7-4ef4-ad26-3f48b39ac9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097786966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3097786966
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1916824668
Short name T856
Test name
Test status
Simulation time 3415130839 ps
CPU time 98.07 seconds
Started Jul 16 05:23:51 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 829956 kb
Host smart-56ac8e6e-0937-4735-a7de-7d92b03841c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916824668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1916824668
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1384175286
Short name T371
Test name
Test status
Simulation time 144567678 ps
CPU time 1.16 seconds
Started Jul 16 05:23:48 PM PDT 24
Finished Jul 16 05:23:50 PM PDT 24
Peak memory 205264 kb
Host smart-02cfc29e-65cf-40c2-adf9-9fa852ada416
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384175286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1384175286
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1026187507
Short name T1584
Test name
Test status
Simulation time 145226858 ps
CPU time 4.02 seconds
Started Jul 16 05:28:40 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 228676 kb
Host smart-b4c511a8-b16c-4cfe-9182-85ea6e98ba66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026187507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1026187507
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2357996457
Short name T770
Test name
Test status
Simulation time 5700924513 ps
CPU time 407.26 seconds
Started Jul 16 05:32:23 PM PDT 24
Finished Jul 16 05:39:11 PM PDT 24
Peak memory 1487148 kb
Host smart-f2a77d85-b020-4d59-97b9-ec627d9960bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357996457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2357996457
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3971229371
Short name T247
Test name
Test status
Simulation time 1100782617 ps
CPU time 4.76 seconds
Started Jul 16 05:24:05 PM PDT 24
Finished Jul 16 05:24:11 PM PDT 24
Peak memory 205472 kb
Host smart-0373765d-6173-40b7-aa90-a40d7e3c488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971229371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3971229371
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.2950761932
Short name T1553
Test name
Test status
Simulation time 29296475 ps
CPU time 0.63 seconds
Started Jul 16 05:23:46 PM PDT 24
Finished Jul 16 05:23:47 PM PDT 24
Peak memory 205096 kb
Host smart-3f672e1b-aa9d-453b-ac7a-84310b9cef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950761932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2950761932
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3457239090
Short name T1004
Test name
Test status
Simulation time 12942171947 ps
CPU time 240.73 seconds
Started Jul 16 05:23:50 PM PDT 24
Finished Jul 16 05:27:51 PM PDT 24
Peak memory 762852 kb
Host smart-fc46a30a-4de3-4b1d-a64d-497bd498c1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457239090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3457239090
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.1523125771
Short name T961
Test name
Test status
Simulation time 272509223 ps
CPU time 4.04 seconds
Started Jul 16 05:23:47 PM PDT 24
Finished Jul 16 05:23:51 PM PDT 24
Peak memory 206028 kb
Host smart-45c45159-468e-4042-926f-ec17f84fa501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523125771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.1523125771
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2676080235
Short name T44
Test name
Test status
Simulation time 13026328591 ps
CPU time 30.81 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:27:58 PM PDT 24
Peak memory 342704 kb
Host smart-b15f11cf-151a-4f41-9fbb-3f531b37b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676080235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2676080235
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2566424736
Short name T1530
Test name
Test status
Simulation time 33565623801 ps
CPU time 955.78 seconds
Started Jul 16 05:23:48 PM PDT 24
Finished Jul 16 05:39:46 PM PDT 24
Peak memory 3163344 kb
Host smart-a24c1180-e1f2-4c2f-8503-241048ceba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566424736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2566424736
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1394877867
Short name T1341
Test name
Test status
Simulation time 550359701 ps
CPU time 23.81 seconds
Started Jul 16 05:23:54 PM PDT 24
Finished Jul 16 05:24:19 PM PDT 24
Peak memory 213708 kb
Host smart-b2929149-9478-4181-a223-9c1e47545d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394877867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1394877867
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1688307096
Short name T755
Test name
Test status
Simulation time 3650920813 ps
CPU time 4.31 seconds
Started Jul 16 05:24:04 PM PDT 24
Finished Jul 16 05:24:09 PM PDT 24
Peak memory 220404 kb
Host smart-179eefe5-ff99-422e-9670-5460f936535d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688307096 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1688307096
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1796908224
Short name T74
Test name
Test status
Simulation time 259992445 ps
CPU time 1.56 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:18 PM PDT 24
Peak memory 205440 kb
Host smart-6b668540-6748-40be-9d08-db715b0efbd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796908224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1796908224
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3355313718
Short name T1117
Test name
Test status
Simulation time 221504542 ps
CPU time 1.02 seconds
Started Jul 16 05:24:00 PM PDT 24
Finished Jul 16 05:24:02 PM PDT 24
Peak memory 205488 kb
Host smart-9a5b5a13-3552-4991-87b4-105e7e27a299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355313718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3355313718
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3749985556
Short name T1427
Test name
Test status
Simulation time 375620682 ps
CPU time 2.46 seconds
Started Jul 16 05:24:00 PM PDT 24
Finished Jul 16 05:24:03 PM PDT 24
Peak memory 205604 kb
Host smart-8a08d970-9310-4c16-b2f3-299f56c47dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749985556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3749985556
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.883027109
Short name T712
Test name
Test status
Simulation time 69862593 ps
CPU time 0.96 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:04 PM PDT 24
Peak memory 205480 kb
Host smart-25a70f7d-5a13-4793-86af-6a6639ffff19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883027109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.883027109
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2152363480
Short name T1567
Test name
Test status
Simulation time 3794093186 ps
CPU time 6.22 seconds
Started Jul 16 05:23:50 PM PDT 24
Finished Jul 16 05:23:57 PM PDT 24
Peak memory 222068 kb
Host smart-d84a9b70-5112-48f8-a8c9-87b401abdd2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152363480 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2152363480
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.4080883132
Short name T1398
Test name
Test status
Simulation time 16709253537 ps
CPU time 362.49 seconds
Started Jul 16 05:24:00 PM PDT 24
Finished Jul 16 05:30:03 PM PDT 24
Peak memory 4040388 kb
Host smart-d9a64db4-ce2a-4681-b1d3-050a07b36b8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080883132 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.4080883132
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.531230631
Short name T436
Test name
Test status
Simulation time 4112270448 ps
CPU time 2.71 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:14 PM PDT 24
Peak memory 213908 kb
Host smart-00be01f4-9925-46a7-8875-bede3e3beb40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531230631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_nack_acqfull.531230631
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.2989888221
Short name T1327
Test name
Test status
Simulation time 6138960653 ps
CPU time 2.72 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:06 PM PDT 24
Peak memory 205392 kb
Host smart-86e5905c-e92d-4182-b637-30157b227a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989888221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.2989888221
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.3218961459
Short name T1404
Test name
Test status
Simulation time 5868644803 ps
CPU time 6.11 seconds
Started Jul 16 05:24:06 PM PDT 24
Finished Jul 16 05:24:13 PM PDT 24
Peak memory 222096 kb
Host smart-0a041046-9df7-4eaf-bf51-8cbda615aed8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218961459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.3218961459
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.2788351364
Short name T730
Test name
Test status
Simulation time 2004632757 ps
CPU time 2.18 seconds
Started Jul 16 05:24:01 PM PDT 24
Finished Jul 16 05:24:04 PM PDT 24
Peak memory 205408 kb
Host smart-339791ac-cbf6-4612-9d50-4ccb2f75a8bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788351364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.2788351364
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3767595055
Short name T260
Test name
Test status
Simulation time 1413210529 ps
CPU time 9.81 seconds
Started Jul 16 05:23:49 PM PDT 24
Finished Jul 16 05:24:00 PM PDT 24
Peak memory 213824 kb
Host smart-89be6490-f2c0-43cf-ae89-b6515edc6473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767595055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3767595055
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1772547230
Short name T72
Test name
Test status
Simulation time 5266030971 ps
CPU time 27.04 seconds
Started Jul 16 05:24:04 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 230284 kb
Host smart-c7e4fd88-ec22-49c1-82f8-bfd4c2af1e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772547230 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1772547230
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.508515447
Short name T741
Test name
Test status
Simulation time 823617784 ps
CPU time 9.15 seconds
Started Jul 16 05:32:23 PM PDT 24
Finished Jul 16 05:32:33 PM PDT 24
Peak memory 205668 kb
Host smart-c4eee044-7b55-4ccd-bcb7-7d47d05a9215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508515447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.508515447
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2184610507
Short name T1193
Test name
Test status
Simulation time 30617996443 ps
CPU time 170.22 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:30:18 PM PDT 24
Peak memory 2187172 kb
Host smart-8d637ffb-6626-49a2-b03c-267d24a24e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184610507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2184610507
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.605746280
Short name T277
Test name
Test status
Simulation time 1694444065 ps
CPU time 7.08 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:10 PM PDT 24
Peak memory 219112 kb
Host smart-ef92fb1c-db4c-4b75-b78b-6c33c5b257ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605746280 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.605746280
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.2384286556
Short name T869
Test name
Test status
Simulation time 43600369 ps
CPU time 1.22 seconds
Started Jul 16 05:24:05 PM PDT 24
Finished Jul 16 05:24:07 PM PDT 24
Peak memory 205024 kb
Host smart-b9e3e7ba-fa55-4fd3-921f-480ee340605e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384286556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2384286556
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4250082979
Short name T803
Test name
Test status
Simulation time 17002259 ps
CPU time 0.64 seconds
Started Jul 16 05:24:08 PM PDT 24
Finished Jul 16 05:24:09 PM PDT 24
Peak memory 204680 kb
Host smart-782ec552-b0a8-4b29-aaf5-5372d48f8a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250082979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4250082979
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3560936610
Short name T1233
Test name
Test status
Simulation time 364794649 ps
CPU time 1.4 seconds
Started Jul 16 05:24:01 PM PDT 24
Finished Jul 16 05:24:03 PM PDT 24
Peak memory 213820 kb
Host smart-49998653-6ddb-462e-9dc2-384befe6a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560936610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3560936610
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.96512618
Short name T604
Test name
Test status
Simulation time 444413523 ps
CPU time 4.34 seconds
Started Jul 16 05:24:00 PM PDT 24
Finished Jul 16 05:24:05 PM PDT 24
Peak memory 247712 kb
Host smart-1d5bf278-9394-4041-8314-5f39a8d2dc68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96512618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty
.96512618
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.542614136
Short name T304
Test name
Test status
Simulation time 2787950455 ps
CPU time 82.17 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:25:25 PM PDT 24
Peak memory 607144 kb
Host smart-bec3ed5d-a31c-4a2e-b9fa-cec0cbb20953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542614136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.542614136
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.300148412
Short name T913
Test name
Test status
Simulation time 6476536237 ps
CPU time 47.43 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:58 PM PDT 24
Peak memory 517036 kb
Host smart-32d2c54b-7490-4532-99d1-f399f4f66ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300148412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.300148412
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2779417286
Short name T609
Test name
Test status
Simulation time 287436031 ps
CPU time 1.07 seconds
Started Jul 16 05:24:10 PM PDT 24
Finished Jul 16 05:24:12 PM PDT 24
Peak memory 205264 kb
Host smart-08e49a21-64e5-4315-9572-8aec98c868b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779417286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2779417286
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.176491200
Short name T1721
Test name
Test status
Simulation time 654819979 ps
CPU time 4.2 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:08 PM PDT 24
Peak memory 205684 kb
Host smart-64abfa82-2ee3-4d80-a208-6b7197ea0804
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176491200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
176491200
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.639714283
Short name T162
Test name
Test status
Simulation time 3428170305 ps
CPU time 129.46 seconds
Started Jul 16 05:24:01 PM PDT 24
Finished Jul 16 05:26:11 PM PDT 24
Peak memory 597856 kb
Host smart-0505442e-8adb-4fe2-ad11-0d60b41291a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639714283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.639714283
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1255028165
Short name T28
Test name
Test status
Simulation time 208830257 ps
CPU time 8.2 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:11 PM PDT 24
Peak memory 205496 kb
Host smart-e5d63b25-d449-4248-87da-5d8dfcfdeac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255028165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1255028165
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.1967640988
Short name T1351
Test name
Test status
Simulation time 33164606 ps
CPU time 0.65 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:03 PM PDT 24
Peak memory 205176 kb
Host smart-4f2f5311-3f09-483e-9d07-5619181467e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967640988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1967640988
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2598867333
Short name T39
Test name
Test status
Simulation time 25563465677 ps
CPU time 56.19 seconds
Started Jul 16 05:24:05 PM PDT 24
Finished Jul 16 05:25:02 PM PDT 24
Peak memory 213768 kb
Host smart-5ed73f86-16d3-41a6-8708-c779135803af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598867333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2598867333
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3615342041
Short name T758
Test name
Test status
Simulation time 358510914 ps
CPU time 2.05 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:05 PM PDT 24
Peak memory 217184 kb
Host smart-b07831ea-8560-475b-a9b6-2ed8bd22008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615342041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3615342041
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3293126558
Short name T1065
Test name
Test status
Simulation time 4949295160 ps
CPU time 45.9 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:57 PM PDT 24
Peak memory 282020 kb
Host smart-cf371008-34f7-4c28-806b-357ca1e121ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293126558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3293126558
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2189559799
Short name T268
Test name
Test status
Simulation time 18047335712 ps
CPU time 1157.92 seconds
Started Jul 16 05:24:07 PM PDT 24
Finished Jul 16 05:43:26 PM PDT 24
Peak memory 1883920 kb
Host smart-0155aa1d-6582-4f43-a39b-50a035630744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189559799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2189559799
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1366146268
Short name T994
Test name
Test status
Simulation time 2161910129 ps
CPU time 16.63 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:20 PM PDT 24
Peak memory 213704 kb
Host smart-d6f08cbc-63a5-4b87-8951-9f0112dd2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366146268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1366146268
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1440549075
Short name T424
Test name
Test status
Simulation time 987036232 ps
CPU time 4.49 seconds
Started Jul 16 05:24:00 PM PDT 24
Finished Jul 16 05:24:05 PM PDT 24
Peak memory 213840 kb
Host smart-c7972c7e-55db-443a-ae29-12edf8302b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440549075 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1440549075
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.563076721
Short name T113
Test name
Test status
Simulation time 520591762 ps
CPU time 1.18 seconds
Started Jul 16 05:24:04 PM PDT 24
Finished Jul 16 05:24:06 PM PDT 24
Peak memory 205640 kb
Host smart-227c7253-da05-4a0a-9aee-9f0bcb4e11b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563076721 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.563076721
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.867765089
Short name T1555
Test name
Test status
Simulation time 136778042 ps
CPU time 0.96 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:12 PM PDT 24
Peak memory 205500 kb
Host smart-00f6e469-7720-47b9-8a2e-bf6753da52d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867765089 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.867765089
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.4015676333
Short name T624
Test name
Test status
Simulation time 482229968 ps
CPU time 1.1 seconds
Started Jul 16 05:24:04 PM PDT 24
Finished Jul 16 05:24:06 PM PDT 24
Peak memory 205440 kb
Host smart-9acd4283-7199-4637-a526-3578a1aa65c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015676333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.4015676333
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1303624079
Short name T676
Test name
Test status
Simulation time 3707846957 ps
CPU time 4.45 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:08 PM PDT 24
Peak memory 222048 kb
Host smart-7c7c09ce-f31a-420c-bfab-c388236d21d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303624079 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1303624079
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2276730297
Short name T1335
Test name
Test status
Simulation time 13588088175 ps
CPU time 111.89 seconds
Started Jul 16 05:24:06 PM PDT 24
Finished Jul 16 05:25:58 PM PDT 24
Peak memory 1681064 kb
Host smart-86c1be61-0045-4762-979e-6c189e89429c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276730297 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2276730297
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.305915616
Short name T518
Test name
Test status
Simulation time 581557291 ps
CPU time 3.14 seconds
Started Jul 16 05:24:07 PM PDT 24
Finished Jul 16 05:24:11 PM PDT 24
Peak memory 213752 kb
Host smart-1c941d91-9206-48be-b082-27499f9a2482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305915616 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_nack_acqfull.305915616
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_perf.1287938466
Short name T1722
Test name
Test status
Simulation time 2347827102 ps
CPU time 4.07 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:08 PM PDT 24
Peak memory 213888 kb
Host smart-f18d1c8f-f363-44c0-8db7-3db51a2a4cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287938466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.1287938466
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.3516615860
Short name T1473
Test name
Test status
Simulation time 1936771833 ps
CPU time 2.52 seconds
Started Jul 16 05:24:03 PM PDT 24
Finished Jul 16 05:24:06 PM PDT 24
Peak memory 205400 kb
Host smart-ef6556d0-bdc9-4a13-a217-a3ba4306a622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516615860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.3516615860
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.622065491
Short name T569
Test name
Test status
Simulation time 792479299 ps
CPU time 11.16 seconds
Started Jul 16 05:24:07 PM PDT 24
Finished Jul 16 05:24:19 PM PDT 24
Peak memory 213708 kb
Host smart-1e973991-4be5-4341-a7d8-fee379ffb666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622065491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_tar
get_smoke.622065491
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.1883043017
Short name T257
Test name
Test status
Simulation time 36208191016 ps
CPU time 1003.56 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:40:46 PM PDT 24
Peak memory 7920280 kb
Host smart-d47f8098-2435-4498-b38e-f5e36ac1896b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883043017 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.1883043017
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.4290940718
Short name T412
Test name
Test status
Simulation time 1659066281 ps
CPU time 5.09 seconds
Started Jul 16 05:32:18 PM PDT 24
Finished Jul 16 05:32:23 PM PDT 24
Peak memory 205536 kb
Host smart-4e73e4a4-55f2-45f9-aabd-4c024541d93e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290940718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.4290940718
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1702634298
Short name T5
Test name
Test status
Simulation time 43569766418 ps
CPU time 759.11 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:36:51 PM PDT 24
Peak memory 5444608 kb
Host smart-fc1ee073-42d3-48d1-bd53-8520d102009e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702634298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1702634298
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3041004266
Short name T830
Test name
Test status
Simulation time 1361168019 ps
CPU time 1.63 seconds
Started Jul 16 05:24:02 PM PDT 24
Finished Jul 16 05:24:04 PM PDT 24
Peak memory 213672 kb
Host smart-66ee2a5d-f37c-42b9-934f-5bd79463fbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041004266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3041004266
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.786555726
Short name T1037
Test name
Test status
Simulation time 2125861118 ps
CPU time 5.49 seconds
Started Jul 16 05:36:26 PM PDT 24
Finished Jul 16 05:36:32 PM PDT 24
Peak memory 222020 kb
Host smart-a8be3663-2955-435b-9af3-192b83b29ffb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786555726 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.786555726
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.3607943587
Short name T847
Test name
Test status
Simulation time 205204661 ps
CPU time 3.15 seconds
Started Jul 16 05:24:05 PM PDT 24
Finished Jul 16 05:24:09 PM PDT 24
Peak memory 204940 kb
Host smart-a5752e1b-2910-4e37-9f98-3a77cecbd3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607943587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3607943587
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.423240379
Short name T1060
Test name
Test status
Simulation time 49511826 ps
CPU time 0.68 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 204756 kb
Host smart-13a2c7aa-53f6-463c-9a96-282cdc935c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423240379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.423240379
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.396045125
Short name T1429
Test name
Test status
Simulation time 110011304 ps
CPU time 2.46 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:12 PM PDT 24
Peak memory 213748 kb
Host smart-d879606e-fd12-4e21-a1dc-e8067a1a095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396045125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.396045125
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.4110581652
Short name T924
Test name
Test status
Simulation time 1238285321 ps
CPU time 17.31 seconds
Started Jul 16 05:24:10 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 265012 kb
Host smart-71e077b1-42f0-435e-b31d-2f817b3524ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110581652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.4110581652
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1555112021
Short name T1375
Test name
Test status
Simulation time 2180478923 ps
CPU time 78.58 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:33:44 PM PDT 24
Peak memory 682076 kb
Host smart-40ceacee-a1a6-4700-9f60-cb3618a36583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555112021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1555112021
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1265511684
Short name T529
Test name
Test status
Simulation time 2297366630 ps
CPU time 66.84 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:33:32 PM PDT 24
Peak memory 767828 kb
Host smart-bdc17113-fe49-44fb-ba46-b03494200faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265511684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1265511684
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1151014358
Short name T37
Test name
Test status
Simulation time 1313792809 ps
CPU time 1.1 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:10 PM PDT 24
Peak memory 205176 kb
Host smart-39e701e8-db0b-42ae-bec8-f730a37885c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151014358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1151014358
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1953482627
Short name T1325
Test name
Test status
Simulation time 454430175 ps
CPU time 6.42 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:16 PM PDT 24
Peak memory 247588 kb
Host smart-8f685661-c3f7-44e2-bfc2-f5a499d333ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953482627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1953482627
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.729797753
Short name T943
Test name
Test status
Simulation time 7203591633 ps
CPU time 244.08 seconds
Started Jul 16 05:24:13 PM PDT 24
Finished Jul 16 05:28:18 PM PDT 24
Peak memory 1077624 kb
Host smart-bc18ed85-a123-41e0-9da7-454a981789c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729797753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.729797753
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1529254238
Short name T1547
Test name
Test status
Simulation time 430324000 ps
CPU time 5.36 seconds
Started Jul 16 05:34:07 PM PDT 24
Finished Jul 16 05:34:13 PM PDT 24
Peak memory 205492 kb
Host smart-0d6f2eef-1ee1-4d98-ae05-06a5ac90520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529254238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1529254238
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.222997334
Short name T131
Test name
Test status
Simulation time 28943447 ps
CPU time 0.67 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:12 PM PDT 24
Peak memory 205144 kb
Host smart-dcfa59b3-3b4a-447c-84f7-5377ba365749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222997334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.222997334
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.470489578
Short name T1685
Test name
Test status
Simulation time 210480713 ps
CPU time 1.33 seconds
Started Jul 16 05:24:08 PM PDT 24
Finished Jul 16 05:24:10 PM PDT 24
Peak memory 214368 kb
Host smart-01c9c991-5a57-4179-bbf9-52fc2580df74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470489578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.470489578
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.1907402621
Short name T855
Test name
Test status
Simulation time 222768715 ps
CPU time 3.86 seconds
Started Jul 16 05:24:08 PM PDT 24
Finished Jul 16 05:24:12 PM PDT 24
Peak memory 205376 kb
Host smart-bc316b4d-076c-4d2c-958e-c0f928628e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907402621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1907402621
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1369124958
Short name T531
Test name
Test status
Simulation time 2791529580 ps
CPU time 26.22 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 406408 kb
Host smart-c33067fa-de6c-4c42-8a32-f8339ef29e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369124958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1369124958
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2623701905
Short name T263
Test name
Test status
Simulation time 11389369569 ps
CPU time 498.31 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:32:28 PM PDT 24
Peak memory 1753352 kb
Host smart-4c78f78f-6509-4bea-a70d-870a2465f0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623701905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2623701905
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.2497304013
Short name T1707
Test name
Test status
Simulation time 781678022 ps
CPU time 13.38 seconds
Started Jul 16 05:24:10 PM PDT 24
Finished Jul 16 05:24:24 PM PDT 24
Peak memory 221924 kb
Host smart-c0830d31-9abf-448d-a27b-5ff98779a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497304013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.2497304013
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3610642783
Short name T622
Test name
Test status
Simulation time 1897086086 ps
CPU time 5.78 seconds
Started Jul 16 05:25:09 PM PDT 24
Finished Jul 16 05:25:15 PM PDT 24
Peak memory 218432 kb
Host smart-7232f08f-54aa-4175-9f03-d6492a8541c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610642783 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3610642783
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.806416284
Short name T857
Test name
Test status
Simulation time 223043970 ps
CPU time 1.32 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:11 PM PDT 24
Peak memory 213708 kb
Host smart-63c9a0a6-dd2a-49f8-8e60-842fad377fa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806416284 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.806416284
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3740085760
Short name T1328
Test name
Test status
Simulation time 283807511 ps
CPU time 1.71 seconds
Started Jul 16 05:24:06 PM PDT 24
Finished Jul 16 05:24:09 PM PDT 24
Peak memory 213844 kb
Host smart-c5ef2255-5792-4999-b0b3-47840b24f536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740085760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3740085760
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.1421467621
Short name T1179
Test name
Test status
Simulation time 740364257 ps
CPU time 2.73 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:08 PM PDT 24
Peak memory 205580 kb
Host smart-08758c94-830d-4431-8335-4f4452ef4db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421467621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.1421467621
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.1216066456
Short name T550
Test name
Test status
Simulation time 137274057 ps
CPU time 1 seconds
Started Jul 16 05:24:13 PM PDT 24
Finished Jul 16 05:24:15 PM PDT 24
Peak memory 205372 kb
Host smart-cc2ff483-fd11-4074-8281-4ad41c290655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216066456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1216066456
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2900193842
Short name T1699
Test name
Test status
Simulation time 404648534 ps
CPU time 2.9 seconds
Started Jul 16 05:26:56 PM PDT 24
Finished Jul 16 05:26:59 PM PDT 24
Peak memory 221948 kb
Host smart-965f1a4d-e3c5-4036-8200-e816bbf6ce16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900193842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2900193842
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1331262524
Short name T1196
Test name
Test status
Simulation time 8716469406 ps
CPU time 3.7 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:29 PM PDT 24
Peak memory 213872 kb
Host smart-2004b4dd-0ac8-4d46-84e2-2399bb23bc1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331262524 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1331262524
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1967593768
Short name T1661
Test name
Test status
Simulation time 12322737155 ps
CPU time 12.29 seconds
Started Jul 16 05:24:07 PM PDT 24
Finished Jul 16 05:24:20 PM PDT 24
Peak memory 330824 kb
Host smart-e6ca2e97-c56f-4914-891d-f904decf0593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967593768 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1967593768
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.3821520128
Short name T683
Test name
Test status
Simulation time 2295044429 ps
CPU time 3.1 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:30 PM PDT 24
Peak memory 213832 kb
Host smart-80108839-768a-42b2-80e1-440cf2068853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821520128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.3821520128
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.93034860
Short name T1486
Test name
Test status
Simulation time 2662641432 ps
CPU time 2.95 seconds
Started Jul 16 05:24:23 PM PDT 24
Finished Jul 16 05:24:26 PM PDT 24
Peak memory 205668 kb
Host smart-2f84828b-97c2-4df5-b9f4-9d80f3f835cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93034860 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_nack_acqfull_addr.93034860
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.591766786
Short name T670
Test name
Test status
Simulation time 140288390 ps
CPU time 1.32 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 222204 kb
Host smart-b6df8679-8e77-467f-96fc-0606d701e50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591766786 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_nack_txstretch.591766786
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.823411981
Short name T1050
Test name
Test status
Simulation time 2882223461 ps
CPU time 5.27 seconds
Started Jul 16 05:24:09 PM PDT 24
Finished Jul 16 05:24:15 PM PDT 24
Peak memory 222116 kb
Host smart-720a4528-b32f-4869-a8fb-a97a09a1b6e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823411981 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_perf.823411981
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.566871102
Short name T114
Test name
Test status
Simulation time 976844694 ps
CPU time 2.33 seconds
Started Jul 16 05:24:15 PM PDT 24
Finished Jul 16 05:24:18 PM PDT 24
Peak memory 205356 kb
Host smart-5758d838-39fe-48cb-a2d2-35abaf657850
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566871102 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_smbus_maxlen.566871102
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.147506172
Short name T1629
Test name
Test status
Simulation time 3858618723 ps
CPU time 29.6 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:32:55 PM PDT 24
Peak memory 213920 kb
Host smart-a78edec5-4436-4211-812f-20e5f1cdff44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147506172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.147506172
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.101735549
Short name T939
Test name
Test status
Simulation time 1147068662 ps
CPU time 22.83 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:49 PM PDT 24
Peak memory 223960 kb
Host smart-969ac429-5f2a-45a8-a8a3-89c2338ea9f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101735549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.101735549
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.751896226
Short name T738
Test name
Test status
Simulation time 19808197668 ps
CPU time 19.42 seconds
Started Jul 16 05:36:22 PM PDT 24
Finished Jul 16 05:36:42 PM PDT 24
Peak memory 205656 kb
Host smart-d64bcf4d-815d-4422-96ef-3152f3b6c784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751896226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.751896226
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2367796631
Short name T293
Test name
Test status
Simulation time 2697547845 ps
CPU time 19.36 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 484732 kb
Host smart-aca8e620-1822-4932-add1-9f23d263dbc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367796631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2367796631
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.572708718
Short name T343
Test name
Test status
Simulation time 1429636688 ps
CPU time 7.44 seconds
Started Jul 16 05:24:08 PM PDT 24
Finished Jul 16 05:24:16 PM PDT 24
Peak memory 213800 kb
Host smart-6e0d9b00-9c66-461e-a5fd-24fb0da6142c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572708718 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.572708718
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3559482675
Short name T764
Test name
Test status
Simulation time 98648161 ps
CPU time 1.72 seconds
Started Jul 16 05:28:49 PM PDT 24
Finished Jul 16 05:28:53 PM PDT 24
Peak memory 205552 kb
Host smart-65bd4bbd-978f-455d-80bb-c420663dde95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559482675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3559482675
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3737848038
Short name T754
Test name
Test status
Simulation time 39326502 ps
CPU time 0.75 seconds
Started Jul 16 05:24:14 PM PDT 24
Finished Jul 16 05:24:15 PM PDT 24
Peak memory 204872 kb
Host smart-027e4c07-23cf-4e8f-97b0-13d6d5d7201e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737848038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3737848038
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3790020281
Short name T707
Test name
Test status
Simulation time 484448501 ps
CPU time 24.71 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:53 PM PDT 24
Peak memory 310608 kb
Host smart-d3e3bd97-8942-4511-9ad4-e80136fd4502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790020281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3790020281
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1693977940
Short name T1017
Test name
Test status
Simulation time 2489021701 ps
CPU time 69.16 seconds
Started Jul 16 05:24:22 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 511728 kb
Host smart-ab173990-d129-4538-8244-fbc5c1eef417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693977940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1693977940
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1115119014
Short name T544
Test name
Test status
Simulation time 1848303304 ps
CPU time 95.98 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:26:03 PM PDT 24
Peak memory 546304 kb
Host smart-4b8664f5-2b09-4529-9dd9-cbc832ff4bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115119014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1115119014
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.927213255
Short name T911
Test name
Test status
Simulation time 83874570 ps
CPU time 1.02 seconds
Started Jul 16 05:24:20 PM PDT 24
Finished Jul 16 05:24:22 PM PDT 24
Peak memory 205212 kb
Host smart-b5fe6b0b-2371-4c90-8197-ad3abd603a74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927213255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.927213255
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3331449156
Short name T1599
Test name
Test status
Simulation time 253762545 ps
CPU time 6.52 seconds
Started Jul 16 05:24:20 PM PDT 24
Finished Jul 16 05:24:27 PM PDT 24
Peak memory 205504 kb
Host smart-56351634-a2ca-48a7-baf0-67a2c153a7cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331449156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3331449156
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2559885947
Short name T1657
Test name
Test status
Simulation time 10248159401 ps
CPU time 349.73 seconds
Started Jul 16 05:24:23 PM PDT 24
Finished Jul 16 05:30:13 PM PDT 24
Peak memory 1461208 kb
Host smart-9eb5f9ed-99d9-4193-9d79-633674a88135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559885947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2559885947
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.196202067
Short name T775
Test name
Test status
Simulation time 448618600 ps
CPU time 8.93 seconds
Started Jul 16 05:24:18 PM PDT 24
Finished Jul 16 05:24:27 PM PDT 24
Peak memory 205516 kb
Host smart-4f9da2de-6574-4820-94fc-f64f16f90c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196202067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.196202067
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.3604662692
Short name T1291
Test name
Test status
Simulation time 17492997 ps
CPU time 0.66 seconds
Started Jul 16 05:24:15 PM PDT 24
Finished Jul 16 05:24:16 PM PDT 24
Peak memory 205388 kb
Host smart-a7fd2ab8-559c-4ef6-9888-b3b06891e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604662692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3604662692
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2885449325
Short name T557
Test name
Test status
Simulation time 26041772739 ps
CPU time 296.45 seconds
Started Jul 16 05:24:18 PM PDT 24
Finished Jul 16 05:29:15 PM PDT 24
Peak memory 235196 kb
Host smart-092dbb6e-1bb1-4424-804c-0e1f08095d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885449325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2885449325
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.1770737062
Short name T998
Test name
Test status
Simulation time 6034193980 ps
CPU time 41.83 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:25:09 PM PDT 24
Peak memory 205468 kb
Host smart-b2ce4f85-9c57-41ce-b2a1-932df82dde70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770737062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.1770737062
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2790514443
Short name T542
Test name
Test status
Simulation time 1100158196 ps
CPU time 16.33 seconds
Started Jul 16 05:24:14 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 260548 kb
Host smart-1c2444a5-fc95-450c-850b-71c6c48a1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790514443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2790514443
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.566882030
Short name T673
Test name
Test status
Simulation time 5565512841 ps
CPU time 29.81 seconds
Started Jul 16 05:24:12 PM PDT 24
Finished Jul 16 05:24:42 PM PDT 24
Peak memory 213684 kb
Host smart-78fd29dc-1889-4b0b-a582-620dff519366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566882030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.566882030
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.4128733290
Short name T659
Test name
Test status
Simulation time 1614208878 ps
CPU time 4.7 seconds
Started Jul 16 05:33:58 PM PDT 24
Finished Jul 16 05:34:03 PM PDT 24
Peak memory 213804 kb
Host smart-7d729b46-96c2-464c-9782-bc48a60d8ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128733290 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.4128733290
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.622711388
Short name T570
Test name
Test status
Simulation time 433552547 ps
CPU time 1.07 seconds
Started Jul 16 05:24:16 PM PDT 24
Finished Jul 16 05:24:17 PM PDT 24
Peak memory 205672 kb
Host smart-ec644202-c3e1-40bb-9b8b-9844d5b5f577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622711388 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.622711388
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.4132654889
Short name T486
Test name
Test status
Simulation time 133837226 ps
CPU time 0.95 seconds
Started Jul 16 05:24:28 PM PDT 24
Finished Jul 16 05:24:30 PM PDT 24
Peak memory 205420 kb
Host smart-7518f261-f2e4-4618-ac4c-5a1a78b6c82e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132654889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.4132654889
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3808920286
Short name T321
Test name
Test status
Simulation time 7596928629 ps
CPU time 2.64 seconds
Started Jul 16 05:24:23 PM PDT 24
Finished Jul 16 05:24:26 PM PDT 24
Peak memory 205640 kb
Host smart-bdac667b-6423-4c0b-810f-f8f987ebb4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808920286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3808920286
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.2233916044
Short name T1102
Test name
Test status
Simulation time 297911331 ps
CPU time 0.93 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 205412 kb
Host smart-c942abb8-1ac4-4a5f-b488-672e5df8811c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233916044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.2233916044
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1278014462
Short name T167
Test name
Test status
Simulation time 1498745149 ps
CPU time 2.77 seconds
Started Jul 16 05:24:22 PM PDT 24
Finished Jul 16 05:24:26 PM PDT 24
Peak memory 213800 kb
Host smart-36b3cb57-2c93-4e46-bd5d-79f51fba93e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278014462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1278014462
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.3208181688
Short name T500
Test name
Test status
Simulation time 3550061325 ps
CPU time 5.51 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:34:33 PM PDT 24
Peak memory 221856 kb
Host smart-a05a0aa5-c5bf-44b8-92cd-b4aa1ebab44d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208181688 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.3208181688
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1923522427
Short name T1678
Test name
Test status
Simulation time 5699667705 ps
CPU time 4.34 seconds
Started Jul 16 05:28:51 PM PDT 24
Finished Jul 16 05:28:57 PM PDT 24
Peak memory 205676 kb
Host smart-fca42833-24a1-4afc-98cb-96a5841b1445
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923522427 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1923522427
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.1124471476
Short name T1216
Test name
Test status
Simulation time 9377089893 ps
CPU time 3.05 seconds
Started Jul 16 05:33:58 PM PDT 24
Finished Jul 16 05:34:02 PM PDT 24
Peak memory 213844 kb
Host smart-ce9f20d5-566b-4c17-8b11-fab714211725
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124471476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.1124471476
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.993312455
Short name T1560
Test name
Test status
Simulation time 869148677 ps
CPU time 2.57 seconds
Started Jul 16 05:24:13 PM PDT 24
Finished Jul 16 05:24:17 PM PDT 24
Peak memory 205576 kb
Host smart-b9a3d28f-cd5d-49d1-862c-0164cedbd517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993312455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.993312455
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.3781883986
Short name T1345
Test name
Test status
Simulation time 598743193 ps
CPU time 1.47 seconds
Started Jul 16 05:24:20 PM PDT 24
Finished Jul 16 05:24:22 PM PDT 24
Peak memory 222252 kb
Host smart-c3d158fe-44ff-4201-bd73-b05319f81c9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781883986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.3781883986
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.4065819365
Short name T749
Test name
Test status
Simulation time 442092499 ps
CPU time 3.11 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:28:55 PM PDT 24
Peak memory 213848 kb
Host smart-01bf8041-7196-4b4a-98ef-674b1a4abd1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065819365 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.4065819365
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.1643661805
Short name T305
Test name
Test status
Simulation time 2016050492 ps
CPU time 2.47 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:29 PM PDT 24
Peak memory 205356 kb
Host smart-35fed509-30e9-41f9-914a-106d1c6378a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643661805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.1643661805
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.478440244
Short name T75
Test name
Test status
Simulation time 3428243066 ps
CPU time 10.59 seconds
Started Jul 16 05:24:20 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 213880 kb
Host smart-473a9743-ad46-4541-a571-eefe33021b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478440244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.478440244
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.957615422
Short name T745
Test name
Test status
Simulation time 87089770997 ps
CPU time 236.99 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 1712348 kb
Host smart-fe8b2302-77ea-4b17-b711-2a2651094d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957615422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_target_stress_all.957615422
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1399960204
Short name T1618
Test name
Test status
Simulation time 4024683904 ps
CPU time 23.34 seconds
Started Jul 16 05:32:18 PM PDT 24
Finished Jul 16 05:32:42 PM PDT 24
Peak memory 230028 kb
Host smart-393d7927-e3d0-4d1e-81bf-e8c4d77ceb0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399960204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1399960204
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2384406329
Short name T1730
Test name
Test status
Simulation time 44709661918 ps
CPU time 1130.99 seconds
Started Jul 16 05:24:13 PM PDT 24
Finished Jul 16 05:43:05 PM PDT 24
Peak memory 6328032 kb
Host smart-4d78c4a2-527e-4636-a890-998c47bb3d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384406329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2384406329
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3114501294
Short name T732
Test name
Test status
Simulation time 2507453541 ps
CPU time 12.61 seconds
Started Jul 16 05:24:22 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 624660 kb
Host smart-9c666b04-094a-456e-910b-42bcedf26efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114501294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3114501294
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.130008850
Short name T700
Test name
Test status
Simulation time 13349833361 ps
CPU time 7.03 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:37 PM PDT 24
Peak memory 221996 kb
Host smart-609e116d-9e45-4da9-a78e-f9966d9ff36a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130008850 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.130008850
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.1514504993
Short name T1103
Test name
Test status
Simulation time 639210702 ps
CPU time 9.09 seconds
Started Jul 16 05:24:16 PM PDT 24
Finished Jul 16 05:24:25 PM PDT 24
Peak memory 207276 kb
Host smart-1c05903b-f757-4a0c-8c16-f0822aa01ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514504993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1514504993
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3063842285
Short name T1244
Test name
Test status
Simulation time 53003996 ps
CPU time 0.62 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:23 PM PDT 24
Peak memory 204664 kb
Host smart-72084395-cbb5-4eca-bef2-bec400c84839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063842285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3063842285
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3337637730
Short name T24
Test name
Test status
Simulation time 217200330 ps
CPU time 3.33 seconds
Started Jul 16 05:22:15 PM PDT 24
Finished Jul 16 05:22:19 PM PDT 24
Peak memory 233700 kb
Host smart-6b68ecbb-5705-4386-9993-a5617a58016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337637730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3337637730
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.979306027
Short name T420
Test name
Test status
Simulation time 352925872 ps
CPU time 5.58 seconds
Started Jul 16 05:22:14 PM PDT 24
Finished Jul 16 05:22:21 PM PDT 24
Peak memory 238088 kb
Host smart-eeabb3ce-3c65-4dca-ae3e-4cde409e25f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979306027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.979306027
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2483541321
Short name T29
Test name
Test status
Simulation time 28472581628 ps
CPU time 67 seconds
Started Jul 16 05:22:10 PM PDT 24
Finished Jul 16 05:23:18 PM PDT 24
Peak memory 482652 kb
Host smart-b7b02318-f444-4914-8032-41e98c289a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483541321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2483541321
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2272039041
Short name T499
Test name
Test status
Simulation time 2633480450 ps
CPU time 36.58 seconds
Started Jul 16 05:22:22 PM PDT 24
Finished Jul 16 05:23:00 PM PDT 24
Peak memory 438736 kb
Host smart-288ee9b0-6050-44f5-a641-1d40f11f0e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272039041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2272039041
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3603288733
Short name T224
Test name
Test status
Simulation time 168403498 ps
CPU time 1.38 seconds
Started Jul 16 05:22:11 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 205468 kb
Host smart-894ba737-da2d-467a-b92a-3e77ee840972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603288733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3603288733
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1989816533
Short name T580
Test name
Test status
Simulation time 121234846 ps
CPU time 3.23 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:24 PM PDT 24
Peak memory 205552 kb
Host smart-6bfbd546-44d6-4884-95d4-c63fe22c1a6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989816533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1989816533
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.44076661
Short name T1561
Test name
Test status
Simulation time 10619173307 ps
CPU time 344.3 seconds
Started Jul 16 05:34:02 PM PDT 24
Finished Jul 16 05:39:47 PM PDT 24
Peak memory 1370548 kb
Host smart-2d16223e-0bc1-41a4-87a8-727f5b487768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44076661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.44076661
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_override.1352221262
Short name T1645
Test name
Test status
Simulation time 38994888 ps
CPU time 0.7 seconds
Started Jul 16 05:34:02 PM PDT 24
Finished Jul 16 05:34:03 PM PDT 24
Peak memory 204932 kb
Host smart-700e6cb8-3ab8-44f9-a2e3-81057250de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352221262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1352221262
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2146276231
Short name T1087
Test name
Test status
Simulation time 28862866771 ps
CPU time 480.79 seconds
Started Jul 16 05:22:11 PM PDT 24
Finished Jul 16 05:30:12 PM PDT 24
Peak memory 213788 kb
Host smart-528b75b4-50a4-4960-aa33-8894da81bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146276231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2146276231
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2377138523
Short name T1447
Test name
Test status
Simulation time 1456490204 ps
CPU time 15.13 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:37 PM PDT 24
Peak memory 205456 kb
Host smart-629e0abe-c374-4947-a8d4-708ae7e15a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377138523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2377138523
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2761627129
Short name T761
Test name
Test status
Simulation time 1312738400 ps
CPU time 64.67 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:26:05 PM PDT 24
Peak memory 336512 kb
Host smart-76d48e4a-f051-4bf0-b00f-30bf792103b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761627129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2761627129
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2917031551
Short name T125
Test name
Test status
Simulation time 1489040737 ps
CPU time 13.59 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:35 PM PDT 24
Peak memory 219504 kb
Host smart-6ff60660-26f8-40ba-9126-ea52ca62658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917031551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2917031551
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3334478581
Short name T174
Test name
Test status
Simulation time 44842542 ps
CPU time 0.85 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:22:27 PM PDT 24
Peak memory 223748 kb
Host smart-5e58e3a6-1bc9-4ddd-91a3-b4ae95622755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334478581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3334478581
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2112159191
Short name T1388
Test name
Test status
Simulation time 1690221209 ps
CPU time 4.58 seconds
Started Jul 16 05:22:16 PM PDT 24
Finished Jul 16 05:22:21 PM PDT 24
Peak memory 219276 kb
Host smart-fb6e7100-a9a5-4dbc-885a-3f0b1384e3a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112159191 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2112159191
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.511487536
Short name T697
Test name
Test status
Simulation time 127815613 ps
CPU time 0.94 seconds
Started Jul 16 05:22:13 PM PDT 24
Finished Jul 16 05:22:15 PM PDT 24
Peak memory 205320 kb
Host smart-91744bce-7555-4b6d-a8f2-ec8112fcfec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511487536 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.511487536
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1711973029
Short name T938
Test name
Test status
Simulation time 362292506 ps
CPU time 1.4 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 205616 kb
Host smart-44125d68-b4f0-49b3-89f1-7c3ceaa41714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711973029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1711973029
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1447208509
Short name T425
Test name
Test status
Simulation time 2008658847 ps
CPU time 3 seconds
Started Jul 16 05:22:15 PM PDT 24
Finished Jul 16 05:22:19 PM PDT 24
Peak memory 205676 kb
Host smart-e57270f5-b26e-4f81-8a33-994b9452f0d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447208509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1447208509
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.353661689
Short name T905
Test name
Test status
Simulation time 537405529 ps
CPU time 1.43 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:22 PM PDT 24
Peak memory 205496 kb
Host smart-25839424-56c4-4a3c-b6e7-d9c04bf2b982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353661689 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.353661689
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.121329914
Short name T1001
Test name
Test status
Simulation time 2242032679 ps
CPU time 6.63 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:08 PM PDT 24
Peak memory 221980 kb
Host smart-46f67c52-94c7-4730-aee7-a941dd73e992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121329914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.121329914
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3165200674
Short name T956
Test name
Test status
Simulation time 24768632698 ps
CPU time 81.71 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:23:44 PM PDT 24
Peak memory 1360604 kb
Host smart-59857cff-665f-4784-bc97-935934a4658c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165200674 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3165200674
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.1628307509
Short name T1112
Test name
Test status
Simulation time 499954175 ps
CPU time 2.79 seconds
Started Jul 16 05:22:14 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 213836 kb
Host smart-82cf4549-ea5f-45e6-a204-71a10994803e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628307509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.1628307509
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.723547665
Short name T898
Test name
Test status
Simulation time 443561188 ps
CPU time 2.47 seconds
Started Jul 16 05:22:14 PM PDT 24
Finished Jul 16 05:22:17 PM PDT 24
Peak memory 205636 kb
Host smart-5499c024-fe2e-4dab-abe8-49d717a20153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723547665 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.723547665
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2413950888
Short name T1251
Test name
Test status
Simulation time 927729663 ps
CPU time 6.54 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:27 PM PDT 24
Peak memory 222036 kb
Host smart-b36b44e1-dcb7-4eb8-b619-cc06ebfebc2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413950888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2413950888
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.2115885590
Short name T1438
Test name
Test status
Simulation time 453693474 ps
CPU time 2.28 seconds
Started Jul 16 05:22:15 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 205424 kb
Host smart-b5c376f2-10c9-4dd1-a442-d1a89999c833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115885590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.2115885590
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.861644482
Short name T1558
Test name
Test status
Simulation time 762459625 ps
CPU time 12.28 seconds
Started Jul 16 05:22:17 PM PDT 24
Finished Jul 16 05:22:30 PM PDT 24
Peak memory 215312 kb
Host smart-8bcb7c9b-bb46-4680-aecd-a0d3e9cdf2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861644482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.861644482
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1325471124
Short name T597
Test name
Test status
Simulation time 25394889808 ps
CPU time 313.33 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 2141372 kb
Host smart-6c7cb03a-d324-4905-a245-88bacc4c0d56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325471124 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1325471124
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.4034401422
Short name T1356
Test name
Test status
Simulation time 1904409675 ps
CPU time 67.08 seconds
Started Jul 16 05:22:19 PM PDT 24
Finished Jul 16 05:23:27 PM PDT 24
Peak memory 215012 kb
Host smart-5879aa8b-6efb-46a1-896e-868f2ee4374d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034401422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.4034401422
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.394629433
Short name T1132
Test name
Test status
Simulation time 25453044223 ps
CPU time 105.36 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:24:07 PM PDT 24
Peak memory 1521184 kb
Host smart-f3437e30-8711-4057-a233-508aff9871f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394629433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.394629433
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2943795807
Short name T975
Test name
Test status
Simulation time 356877945 ps
CPU time 10.06 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:22:36 PM PDT 24
Peak memory 244308 kb
Host smart-b27af8fd-cc0c-46b9-ab61-33b33f23d182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943795807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2943795807
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3362250953
Short name T1424
Test name
Test status
Simulation time 1512066952 ps
CPU time 7.26 seconds
Started Jul 16 05:22:13 PM PDT 24
Finished Jul 16 05:22:20 PM PDT 24
Peak memory 221848 kb
Host smart-1a288eaa-25f1-4b7d-84bc-5606083db8e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362250953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3362250953
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2520755029
Short name T308
Test name
Test status
Simulation time 1283977056 ps
CPU time 14.62 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 220948 kb
Host smart-37746ffb-ef44-422f-9dd6-fee718917eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520755029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2520755029
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3823931389
Short name T963
Test name
Test status
Simulation time 15533379 ps
CPU time 0.61 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:27 PM PDT 24
Peak memory 204868 kb
Host smart-1734ff49-f6dd-45a1-89de-13926f39d6a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823931389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3823931389
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.472000758
Short name T962
Test name
Test status
Simulation time 232636067 ps
CPU time 5.07 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:31 PM PDT 24
Peak memory 213976 kb
Host smart-828a86bb-c6c1-42dd-a506-c5433e08dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472000758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.472000758
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1953246645
Short name T1536
Test name
Test status
Simulation time 1043462033 ps
CPU time 12.18 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 240908 kb
Host smart-a5867e1c-90dd-4484-bec0-e504578bbfe8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953246645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1953246645
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3033384353
Short name T1207
Test name
Test status
Simulation time 2558877725 ps
CPU time 160.25 seconds
Started Jul 16 05:29:03 PM PDT 24
Finished Jul 16 05:31:44 PM PDT 24
Peak memory 595120 kb
Host smart-69ca5a60-5cb0-4fe1-aea2-10a0d0e6bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033384353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3033384353
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3589054673
Short name T679
Test name
Test status
Simulation time 2070383953 ps
CPU time 138.75 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:31:11 PM PDT 24
Peak memory 649188 kb
Host smart-5de0145e-3613-49c0-962a-5166e0050b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589054673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3589054673
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2477627249
Short name T1702
Test name
Test status
Simulation time 138104391 ps
CPU time 1 seconds
Started Jul 16 05:24:23 PM PDT 24
Finished Jul 16 05:24:25 PM PDT 24
Peak memory 205220 kb
Host smart-0642309a-df62-4747-996c-a18f63dcb890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477627249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2477627249
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3563304027
Short name T1664
Test name
Test status
Simulation time 492000166 ps
CPU time 3.88 seconds
Started Jul 16 05:29:04 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 228556 kb
Host smart-5fc22cb2-30b8-496a-a739-17d9fb7e26a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563304027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3563304027
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.433077932
Short name T1322
Test name
Test status
Simulation time 44899283914 ps
CPU time 319.92 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:29:50 PM PDT 24
Peak memory 1326040 kb
Host smart-237d2e8d-2f4e-467c-bea3-ba7ac02b1bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433077932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.433077932
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_override.2994019074
Short name T1521
Test name
Test status
Simulation time 40399732 ps
CPU time 0.63 seconds
Started Jul 16 05:24:22 PM PDT 24
Finished Jul 16 05:24:24 PM PDT 24
Peak memory 205172 kb
Host smart-3ba8f5d5-7f40-43e3-b33d-0ca3c98e72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994019074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2994019074
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2344680413
Short name T1088
Test name
Test status
Simulation time 8566989910 ps
CPU time 44.34 seconds
Started Jul 16 05:24:11 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 218100 kb
Host smart-2b77c36e-9158-4417-993a-5328f77e638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344680413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2344680413
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2525511749
Short name T408
Test name
Test status
Simulation time 1389732316 ps
CPU time 24.55 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:25:00 PM PDT 24
Peak memory 404688 kb
Host smart-413fc276-ee3c-4615-877c-dc08250de333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525511749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2525511749
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3878549265
Short name T646
Test name
Test status
Simulation time 1082306972 ps
CPU time 17.72 seconds
Started Jul 16 05:24:19 PM PDT 24
Finished Jul 16 05:24:37 PM PDT 24
Peak memory 331324 kb
Host smart-48a31a79-9aa3-4b60-b232-d0e701436e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878549265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3878549265
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3067997197
Short name T1520
Test name
Test status
Simulation time 623824155 ps
CPU time 27.44 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 213656 kb
Host smart-2e2a4c3c-d89f-4959-bed6-5d830b6e7ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067997197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3067997197
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1370711337
Short name T954
Test name
Test status
Simulation time 1186113314 ps
CPU time 5.54 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:41 PM PDT 24
Peak memory 213708 kb
Host smart-0d8f1d12-e9e9-4717-b401-a2efe59e4577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370711337 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1370711337
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.896043652
Short name T1694
Test name
Test status
Simulation time 239590383 ps
CPU time 1.03 seconds
Started Jul 16 05:24:24 PM PDT 24
Finished Jul 16 05:24:25 PM PDT 24
Peak memory 205396 kb
Host smart-dfcc5f2d-81c8-4aae-ba37-8f19df8b3e91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896043652 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.896043652
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2705308950
Short name T559
Test name
Test status
Simulation time 314879340 ps
CPU time 0.97 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:29 PM PDT 24
Peak memory 205480 kb
Host smart-7199a41d-8f46-4cd3-95a2-77d5ca988882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705308950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2705308950
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.319611086
Short name T822
Test name
Test status
Simulation time 992376450 ps
CPU time 2.88 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:33 PM PDT 24
Peak memory 205616 kb
Host smart-9517917b-ab9e-4876-9186-ad6daec5516a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319611086 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.319611086
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3041338569
Short name T1229
Test name
Test status
Simulation time 632915825 ps
CPU time 1.45 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 205324 kb
Host smart-1719ac37-91a8-4e9c-a50c-f0a313f46e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041338569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3041338569
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1917615858
Short name T566
Test name
Test status
Simulation time 229981545 ps
CPU time 1.8 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:27 PM PDT 24
Peak memory 213804 kb
Host smart-1af776b9-f444-4f6b-9467-2640a3f94265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917615858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1917615858
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2952275329
Short name T451
Test name
Test status
Simulation time 2177495748 ps
CPU time 3.75 seconds
Started Jul 16 05:24:23 PM PDT 24
Finished Jul 16 05:24:27 PM PDT 24
Peak memory 221580 kb
Host smart-093b02fe-69ad-486e-beb9-b7bb30c1f4f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952275329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2952275329
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.1319040820
Short name T285
Test name
Test status
Simulation time 24091227501 ps
CPU time 201.37 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:27:51 PM PDT 24
Peak memory 2688184 kb
Host smart-8da1881c-e010-4e72-86f1-8c83f8fcf8ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319040820 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1319040820
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.1318619344
Short name T1077
Test name
Test status
Simulation time 2982539350 ps
CPU time 2.88 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:32 PM PDT 24
Peak memory 213844 kb
Host smart-4a753682-210c-4225-946d-38dc3988941a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318619344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.1318619344
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.27582789
Short name T1240
Test name
Test status
Simulation time 441562524 ps
CPU time 2.41 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 205856 kb
Host smart-6a46ee2a-adb8-438f-b7cc-3d1220322a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582789 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_acqfull_addr.27582789
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.3796682382
Short name T1406
Test name
Test status
Simulation time 452542207 ps
CPU time 1.5 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:29 PM PDT 24
Peak memory 222132 kb
Host smart-c290f903-66ec-45a1-b486-be87bc748162
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796682382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.3796682382
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.2570807148
Short name T1415
Test name
Test status
Simulation time 1332301443 ps
CPU time 4.79 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:33 PM PDT 24
Peak memory 214312 kb
Host smart-488fb9c4-ea97-40dd-8dd0-2ce94e32bf8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570807148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.2570807148
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.3326182736
Short name T1573
Test name
Test status
Simulation time 2446968597 ps
CPU time 2.25 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:38 PM PDT 24
Peak memory 205204 kb
Host smart-1a771d88-7266-453d-8474-d130ab207c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326182736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.3326182736
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4249502818
Short name T318
Test name
Test status
Simulation time 1241344422 ps
CPU time 17.26 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:48 PM PDT 24
Peak memory 213732 kb
Host smart-7215a91c-7b86-4552-8f5f-5d84c6c96e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249502818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4249502818
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.427457712
Short name T1285
Test name
Test status
Simulation time 85993038374 ps
CPU time 290.36 seconds
Started Jul 16 05:24:28 PM PDT 24
Finished Jul 16 05:29:19 PM PDT 24
Peak memory 1948868 kb
Host smart-2c4e21e7-060e-4d74-8bc9-b985187bc2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427457712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_stress_all.427457712
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2815799395
Short name T1175
Test name
Test status
Simulation time 4494199741 ps
CPU time 21.36 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:50 PM PDT 24
Peak memory 230180 kb
Host smart-fc45c40e-7d8e-4dc6-86c6-5817877cb348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815799395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2815799395
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2688901620
Short name T591
Test name
Test status
Simulation time 14400746753 ps
CPU time 15.75 seconds
Started Jul 16 05:24:24 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 205648 kb
Host smart-52ceab27-c841-4e7c-9f5a-a028eb206ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688901620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2688901620
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1366360549
Short name T1731
Test name
Test status
Simulation time 1282367475 ps
CPU time 3.07 seconds
Started Jul 16 05:24:24 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 214740 kb
Host smart-e1a9301b-63ad-45d2-840c-f3975c3d1ee8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366360549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1366360549
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.664918434
Short name T561
Test name
Test status
Simulation time 2330877489 ps
CPU time 6.34 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 222000 kb
Host smart-1dd1a669-dbbe-4af4-82aa-f3c67ede1f83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664918434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.664918434
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1207671401
Short name T1474
Test name
Test status
Simulation time 616487834 ps
CPU time 6.41 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 213732 kb
Host smart-41b6c4c1-ab6e-4a02-93e6-9714a8dc0061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207671401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1207671401
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3416452752
Short name T1270
Test name
Test status
Simulation time 43844900 ps
CPU time 0.62 seconds
Started Jul 16 05:24:39 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 204920 kb
Host smart-4aa96051-9726-44ca-a2ff-32238d14bd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416452752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3416452752
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2589635198
Short name T1005
Test name
Test status
Simulation time 698167697 ps
CPU time 2.84 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:30 PM PDT 24
Peak memory 232100 kb
Host smart-77afd20d-7392-426b-8069-ad27a4047659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589635198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2589635198
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2816747908
Short name T1028
Test name
Test status
Simulation time 3377713939 ps
CPU time 12.04 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 252020 kb
Host smart-42658697-4360-47f0-b64e-e39d3fba1b43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816747908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2816747908
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.975174736
Short name T1402
Test name
Test status
Simulation time 7833394103 ps
CPU time 58.11 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:25:25 PM PDT 24
Peak memory 530172 kb
Host smart-ec74f8c8-0f44-4c46-b372-5c039f8e460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975174736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.975174736
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2155528608
Short name T471
Test name
Test status
Simulation time 2106936055 ps
CPU time 146.62 seconds
Started Jul 16 05:24:21 PM PDT 24
Finished Jul 16 05:26:48 PM PDT 24
Peak memory 706544 kb
Host smart-89e58ad0-6ed0-4e99-9b40-08b82c00ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155528608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2155528608
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2178015901
Short name T983
Test name
Test status
Simulation time 993971902 ps
CPU time 1 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 205220 kb
Host smart-a3ba5bf5-1604-41b8-988e-630995812fd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178015901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2178015901
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3251199181
Short name T411
Test name
Test status
Simulation time 667968348 ps
CPU time 6.4 seconds
Started Jul 16 05:24:28 PM PDT 24
Finished Jul 16 05:24:35 PM PDT 24
Peak memory 251176 kb
Host smart-a608e6f9-c4a3-4369-9d72-73ed0905dcea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251199181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3251199181
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.383536777
Short name T1468
Test name
Test status
Simulation time 21720909951 ps
CPU time 71.18 seconds
Started Jul 16 05:24:28 PM PDT 24
Finished Jul 16 05:25:40 PM PDT 24
Peak memory 966228 kb
Host smart-f983a9e2-f608-475e-ac07-3e395d28b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383536777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.383536777
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2996682672
Short name T897
Test name
Test status
Simulation time 503139295 ps
CPU time 7.48 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 205536 kb
Host smart-1e17991a-37c2-462b-bdbd-913796d9c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996682672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2996682672
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.133779039
Short name T129
Test name
Test status
Simulation time 44693775 ps
CPU time 0.64 seconds
Started Jul 16 05:24:28 PM PDT 24
Finished Jul 16 05:24:30 PM PDT 24
Peak memory 205064 kb
Host smart-645dc02c-490b-4f0a-a635-0b8f1d68b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133779039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.133779039
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1486689238
Short name T1339
Test name
Test status
Simulation time 2754635378 ps
CPU time 29.7 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:55 PM PDT 24
Peak memory 214420 kb
Host smart-941fdb62-388c-4875-bd32-c5c437bad6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486689238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1486689238
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3036707993
Short name T1421
Test name
Test status
Simulation time 24277429758 ps
CPU time 895.64 seconds
Started Jul 16 05:24:30 PM PDT 24
Finished Jul 16 05:39:26 PM PDT 24
Peak memory 205528 kb
Host smart-b93d59f3-8963-48ba-94df-8dec1b0d3880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036707993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3036707993
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2021710129
Short name T1049
Test name
Test status
Simulation time 1862164042 ps
CPU time 37.41 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 370904 kb
Host smart-89cb56a1-a457-494a-b99c-3089002e339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021710129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2021710129
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.43894918
Short name T1596
Test name
Test status
Simulation time 1961223968 ps
CPU time 10.29 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 213692 kb
Host smart-3f843b2f-d087-4557-8390-28aca7d47536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43894918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.43894918
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2330436958
Short name T1189
Test name
Test status
Simulation time 2488571877 ps
CPU time 5.08 seconds
Started Jul 16 05:24:29 PM PDT 24
Finished Jul 16 05:24:35 PM PDT 24
Peak memory 218048 kb
Host smart-38dcc06e-312a-4f11-bc0a-32955d7ebd37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330436958 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2330436958
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1731716929
Short name T448
Test name
Test status
Simulation time 317044291 ps
CPU time 1.49 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:24:28 PM PDT 24
Peak memory 205472 kb
Host smart-0113a617-2938-4334-b12f-3eccc8f0e1c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731716929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1731716929
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3762639475
Short name T1651
Test name
Test status
Simulation time 218238548 ps
CPU time 1.43 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:37 PM PDT 24
Peak memory 205496 kb
Host smart-353e1a50-eb58-431d-bff4-7bc82b21d74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762639475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3762639475
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.499645846
Short name T1738
Test name
Test status
Simulation time 511154824 ps
CPU time 2.9 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 205568 kb
Host smart-8ee6472e-92a0-420c-9356-9b33e93851af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499645846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.499645846
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.499276612
Short name T280
Test name
Test status
Simulation time 120395548 ps
CPU time 1.19 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:39 PM PDT 24
Peak memory 205416 kb
Host smart-40801847-952e-431d-8a56-7aceaa0b068b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499276612 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.499276612
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2372346141
Short name T970
Test name
Test status
Simulation time 2907967616 ps
CPU time 7.31 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 222108 kb
Host smart-c2c0bf74-b787-419d-979d-16bf25fd7ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372346141 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2372346141
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3953951840
Short name T1002
Test name
Test status
Simulation time 19703149902 ps
CPU time 62.37 seconds
Started Jul 16 05:24:34 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 853636 kb
Host smart-633b1359-e815-4b7e-8918-5ae8fca44c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953951840 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3953951840
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.1498879322
Short name T1057
Test name
Test status
Simulation time 2264728690 ps
CPU time 2.69 seconds
Started Jul 16 05:28:56 PM PDT 24
Finished Jul 16 05:29:05 PM PDT 24
Peak memory 213840 kb
Host smart-cfd7418d-6673-4430-ab0a-49b051bac706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498879322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.1498879322
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.693477620
Short name T1726
Test name
Test status
Simulation time 1790691533 ps
CPU time 2.4 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:41 PM PDT 24
Peak memory 205644 kb
Host smart-c6e7cc12-80d8-441c-8ee4-0086c2439ab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693477620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.693477620
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.63964774
Short name T1585
Test name
Test status
Simulation time 265665344 ps
CPU time 1.7 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:38 PM PDT 24
Peak memory 222840 kb
Host smart-5defa060-c1fb-49eb-9880-91dbaf93e549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63964774 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_txstretch.63964774
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.454151291
Short name T527
Test name
Test status
Simulation time 2079061191 ps
CPU time 3.65 seconds
Started Jul 16 05:24:30 PM PDT 24
Finished Jul 16 05:24:35 PM PDT 24
Peak memory 217484 kb
Host smart-965045a3-7aa9-4aa0-83b8-7bc68060b2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454151291 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_perf.454151291
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.3170507690
Short name T347
Test name
Test status
Simulation time 1170026002 ps
CPU time 2.37 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 205236 kb
Host smart-3358e36c-36cd-41fd-b1bc-8e1a896576be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170507690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.3170507690
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.4211407853
Short name T1369
Test name
Test status
Simulation time 1802144337 ps
CPU time 29.28 seconds
Started Jul 16 05:24:25 PM PDT 24
Finished Jul 16 05:24:55 PM PDT 24
Peak memory 213776 kb
Host smart-fcbc3de9-881d-4804-bc4d-b43bb0170256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211407853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.4211407853
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.376148200
Short name T1265
Test name
Test status
Simulation time 75863962473 ps
CPU time 124.39 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 841552 kb
Host smart-c7db99d5-c0c6-4641-b4ab-654ee2fa2433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376148200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.376148200
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1975012732
Short name T930
Test name
Test status
Simulation time 5991461401 ps
CPU time 68.13 seconds
Started Jul 16 05:24:22 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 218388 kb
Host smart-e59a6460-897e-4489-b8c4-36f628be82cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975012732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1975012732
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4048027200
Short name T1287
Test name
Test status
Simulation time 27746476067 ps
CPU time 148.47 seconds
Started Jul 16 05:24:24 PM PDT 24
Finished Jul 16 05:26:53 PM PDT 24
Peak memory 2013636 kb
Host smart-7f2f4260-d630-4f11-9f76-4e00732aae7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048027200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4048027200
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1230532671
Short name T1273
Test name
Test status
Simulation time 3533870104 ps
CPU time 190.15 seconds
Started Jul 16 05:24:26 PM PDT 24
Finished Jul 16 05:27:38 PM PDT 24
Peak memory 1004824 kb
Host smart-2b89b226-ef31-4e83-916f-f0116a97ab68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230532671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1230532671
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2591166883
Short name T551
Test name
Test status
Simulation time 1492351431 ps
CPU time 7.81 seconds
Started Jul 16 05:24:27 PM PDT 24
Finished Jul 16 05:24:36 PM PDT 24
Peak memory 230116 kb
Host smart-5675a04f-87f5-4895-859a-f945cc5c378e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591166883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2591166883
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.2177153829
Short name T1622
Test name
Test status
Simulation time 468510254 ps
CPU time 6.08 seconds
Started Jul 16 05:24:39 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 205600 kb
Host smart-154585af-8908-499a-97c8-ecc2114c4961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177153829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2177153829
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1620889836
Short name T1580
Test name
Test status
Simulation time 17766204 ps
CPU time 0.65 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:50 PM PDT 24
Peak memory 204684 kb
Host smart-3675bd02-d7c2-4aeb-97e5-4fa4e55ee338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620889836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1620889836
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3871756527
Short name T1363
Test name
Test status
Simulation time 141631402 ps
CPU time 1.54 seconds
Started Jul 16 05:24:38 PM PDT 24
Finished Jul 16 05:24:41 PM PDT 24
Peak memory 213768 kb
Host smart-a3c2465a-6ebf-4beb-95f5-f54dedb903c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871756527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3871756527
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1383304274
Short name T269
Test name
Test status
Simulation time 811200979 ps
CPU time 4.67 seconds
Started Jul 16 05:24:41 PM PDT 24
Finished Jul 16 05:24:46 PM PDT 24
Peak memory 244908 kb
Host smart-d84caeae-2def-4a9c-956a-4f922d913db1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383304274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1383304274
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2296434844
Short name T42
Test name
Test status
Simulation time 4947290478 ps
CPU time 52.29 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 363876 kb
Host smart-0b322f07-aa03-45a7-9940-94b361009500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296434844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2296434844
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.4024303051
Short name T1524
Test name
Test status
Simulation time 1212942111 ps
CPU time 79.22 seconds
Started Jul 16 05:24:39 PM PDT 24
Finished Jul 16 05:25:59 PM PDT 24
Peak memory 475144 kb
Host smart-b082a661-d3be-421b-b8e5-97d681b59065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024303051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.4024303051
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.94730403
Short name T1572
Test name
Test status
Simulation time 144668016 ps
CPU time 1.28 seconds
Started Jul 16 05:24:41 PM PDT 24
Finished Jul 16 05:24:42 PM PDT 24
Peak memory 205276 kb
Host smart-07f4a537-31ad-468d-9cdf-24065f845d94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94730403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt
.94730403
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1440958595
Short name T46
Test name
Test status
Simulation time 172935612 ps
CPU time 4.22 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:32:30 PM PDT 24
Peak memory 205532 kb
Host smart-90edc03d-b9f1-4e84-a0d6-a7c990b0da45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440958595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1440958595
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3303931797
Short name T253
Test name
Test status
Simulation time 537409038 ps
CPU time 3.29 seconds
Started Jul 16 05:24:47 PM PDT 24
Finished Jul 16 05:24:51 PM PDT 24
Peak memory 205488 kb
Host smart-d86ef2fe-9ba3-4573-98ba-22107f9a84ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303931797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3303931797
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.2904831684
Short name T133
Test name
Test status
Simulation time 98837724 ps
CPU time 0.7 seconds
Started Jul 16 05:24:40 PM PDT 24
Finished Jul 16 05:24:41 PM PDT 24
Peak memory 205236 kb
Host smart-de9f2c8b-8928-4981-8090-976fcebfd88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904831684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2904831684
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3883661776
Short name T1394
Test name
Test status
Simulation time 3005184306 ps
CPU time 11.11 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:49 PM PDT 24
Peak memory 229936 kb
Host smart-c1468ffc-53f1-407f-a190-0d76826bd224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883661776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3883661776
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.1086749977
Short name T1019
Test name
Test status
Simulation time 199667737 ps
CPU time 1.38 seconds
Started Jul 16 05:24:38 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 213644 kb
Host smart-fab4378d-d06f-43ca-8fe2-c1df72200804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086749977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1086749977
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3269805998
Short name T867
Test name
Test status
Simulation time 4611384496 ps
CPU time 52.91 seconds
Started Jul 16 05:25:58 PM PDT 24
Finished Jul 16 05:26:51 PM PDT 24
Peak memory 282880 kb
Host smart-3267b87b-9c46-4a8d-b318-df9bce470bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269805998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3269805998
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2142161012
Short name T929
Test name
Test status
Simulation time 7605094852 ps
CPU time 9.4 seconds
Started Jul 16 05:24:39 PM PDT 24
Finished Jul 16 05:24:49 PM PDT 24
Peak memory 221952 kb
Host smart-7b525565-5f50-4673-99ed-0418f8402ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142161012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2142161012
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3084050526
Short name T1613
Test name
Test status
Simulation time 3503304368 ps
CPU time 3.77 seconds
Started Jul 16 05:24:41 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 213800 kb
Host smart-8b59ea10-5567-4ebe-9039-5b9292697a96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084050526 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3084050526
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3488069352
Short name T969
Test name
Test status
Simulation time 848951432 ps
CPU time 1.53 seconds
Started Jul 16 05:24:41 PM PDT 24
Finished Jul 16 05:24:43 PM PDT 24
Peak memory 205620 kb
Host smart-afa8e060-4841-4062-a180-412adecdf006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488069352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3488069352
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1964913398
Short name T583
Test name
Test status
Simulation time 260256202 ps
CPU time 1.47 seconds
Started Jul 16 05:32:33 PM PDT 24
Finished Jul 16 05:32:35 PM PDT 24
Peak memory 213720 kb
Host smart-e00253dd-ef9e-4c29-a081-7063a13cf6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964913398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1964913398
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1086900008
Short name T261
Test name
Test status
Simulation time 715695892 ps
CPU time 3.64 seconds
Started Jul 16 05:24:52 PM PDT 24
Finished Jul 16 05:24:57 PM PDT 24
Peak memory 205560 kb
Host smart-377bb3ac-2bfb-4d9f-a59b-2b29516bc60e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086900008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1086900008
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2752029840
Short name T294
Test name
Test status
Simulation time 126116167 ps
CPU time 1.24 seconds
Started Jul 16 05:24:54 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 205416 kb
Host smart-7405b3dc-88dd-4319-a371-4e95ca066669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752029840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2752029840
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.372452254
Short name T992
Test name
Test status
Simulation time 838109581 ps
CPU time 4.08 seconds
Started Jul 16 05:24:36 PM PDT 24
Finished Jul 16 05:24:41 PM PDT 24
Peak memory 213824 kb
Host smart-df902483-cf16-40d7-89be-901e84341127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372452254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.372452254
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.331459778
Short name T1277
Test name
Test status
Simulation time 282455307 ps
CPU time 1.85 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:38 PM PDT 24
Peak memory 205352 kb
Host smart-10ec4b10-dde7-490c-8d8c-aec5c8f7ff47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331459778 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.331459778
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.2890869646
Short name T744
Test name
Test status
Simulation time 1781017883 ps
CPU time 2.68 seconds
Started Jul 16 05:24:50 PM PDT 24
Finished Jul 16 05:24:53 PM PDT 24
Peak memory 213752 kb
Host smart-c33b26da-d19d-4a38-ac1f-d1ba10ea6ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890869646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.2890869646
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.867597349
Short name T66
Test name
Test status
Simulation time 542980960 ps
CPU time 2.76 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:24:51 PM PDT 24
Peak memory 205532 kb
Host smart-6abe2c94-b676-4875-9ff6-b7cb748b1987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867597349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.867597349
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.777007415
Short name T163
Test name
Test status
Simulation time 3307808405 ps
CPU time 5.98 seconds
Started Jul 16 05:24:36 PM PDT 24
Finished Jul 16 05:24:43 PM PDT 24
Peak memory 221408 kb
Host smart-326279dc-614d-4347-9985-c86e5e4ebcd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777007415 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_perf.777007415
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.3685963594
Short name T525
Test name
Test status
Simulation time 2910048965 ps
CPU time 2.5 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:24:51 PM PDT 24
Peak memory 205436 kb
Host smart-8202b870-b858-4f51-be6c-627f9145a7a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685963594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.3685963594
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3622115846
Short name T1080
Test name
Test status
Simulation time 1136073015 ps
CPU time 36.44 seconds
Started Jul 16 05:24:38 PM PDT 24
Finished Jul 16 05:25:15 PM PDT 24
Peak memory 213816 kb
Host smart-90f63efc-0753-4e88-a14f-ff7a494239d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622115846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3622115846
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.3279508648
Short name T1281
Test name
Test status
Simulation time 36738478039 ps
CPU time 990.99 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:41:09 PM PDT 24
Peak memory 5408932 kb
Host smart-d94f6ce4-da82-4b90-ae61-3acc8d19f666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279508648 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.3279508648
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2463700525
Short name T398
Test name
Test status
Simulation time 3245573143 ps
CPU time 16.8 seconds
Started Jul 16 05:24:41 PM PDT 24
Finished Jul 16 05:24:58 PM PDT 24
Peak memory 222072 kb
Host smart-a84257f9-c152-4546-89bb-8203822e3215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463700525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2463700525
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1083713698
Short name T877
Test name
Test status
Simulation time 53113503574 ps
CPU time 1649.43 seconds
Started Jul 16 05:24:38 PM PDT 24
Finished Jul 16 05:52:09 PM PDT 24
Peak memory 8492428 kb
Host smart-2738c983-024e-4da9-837a-1cf557c73675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083713698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1083713698
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.482924503
Short name T1614
Test name
Test status
Simulation time 3800463216 ps
CPU time 68.12 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:25:46 PM PDT 24
Peak memory 1044788 kb
Host smart-693c0ec2-d35a-40f1-87f9-262f5eb1121c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482924503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.482924503
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.340471532
Short name T7
Test name
Test status
Simulation time 1436441680 ps
CPU time 7.73 seconds
Started Jul 16 05:32:23 PM PDT 24
Finished Jul 16 05:32:32 PM PDT 24
Peak memory 230172 kb
Host smart-5bb05496-e81f-456b-a84f-14e4c6f71e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340471532 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.340471532
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.1533363807
Short name T1238
Test name
Test status
Simulation time 275803298 ps
CPU time 3.8 seconds
Started Jul 16 05:24:52 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 221220 kb
Host smart-1d7a1664-0b8f-4825-8ed9-24a299da3107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533363807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1533363807
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3213083299
Short name T1329
Test name
Test status
Simulation time 47041033 ps
CPU time 0.68 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:00 PM PDT 24
Peak memory 204572 kb
Host smart-f944197a-9e91-4b0b-938f-741c1b531ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213083299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3213083299
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.474839032
Short name T1648
Test name
Test status
Simulation time 198281428 ps
CPU time 2.6 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:52 PM PDT 24
Peak memory 213620 kb
Host smart-b5dbe55b-893e-4769-a20a-c13f662f776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474839032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.474839032
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.581039751
Short name T543
Test name
Test status
Simulation time 426655925 ps
CPU time 9.33 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 296480 kb
Host smart-f37de547-c8c5-4b58-9fa3-f65c4cf9aa69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581039751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.581039751
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2087605186
Short name T1539
Test name
Test status
Simulation time 4263795512 ps
CPU time 66.35 seconds
Started Jul 16 05:24:51 PM PDT 24
Finished Jul 16 05:25:58 PM PDT 24
Peak memory 620844 kb
Host smart-ac6a1491-fde8-4cb1-8c16-04d7dc4cf791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087605186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2087605186
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.499318861
Short name T1616
Test name
Test status
Simulation time 2434810439 ps
CPU time 109.65 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:26:40 PM PDT 24
Peak memory 587480 kb
Host smart-51b3996a-e24a-48cc-aa87-95871f700aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499318861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.499318861
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3118425250
Short name T223
Test name
Test status
Simulation time 101772523 ps
CPU time 0.96 seconds
Started Jul 16 05:24:53 PM PDT 24
Finished Jul 16 05:24:55 PM PDT 24
Peak memory 205220 kb
Host smart-aa9d163c-bf8a-4f91-a437-f072cc8bfe94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118425250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3118425250
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2970031909
Short name T691
Test name
Test status
Simulation time 232490092 ps
CPU time 4.87 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:55 PM PDT 24
Peak memory 205532 kb
Host smart-9c9ad337-4c5e-4330-a407-3c1d0e1a12aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970031909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2970031909
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2380858233
Short name T1518
Test name
Test status
Simulation time 11495306566 ps
CPU time 168.82 seconds
Started Jul 16 05:24:50 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 1556312 kb
Host smart-e80bef59-ac70-429e-8993-e28931e48012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380858233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2380858233
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1344997356
Short name T1604
Test name
Test status
Simulation time 1244463255 ps
CPU time 9.34 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 205436 kb
Host smart-74e059c4-dceb-438c-8e22-ba61e99ed252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344997356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1344997356
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.4234116642
Short name T1557
Test name
Test status
Simulation time 29624833 ps
CPU time 0.72 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:51 PM PDT 24
Peak memory 205276 kb
Host smart-b8ba2cbd-bb45-4e59-8634-f8843e76e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234116642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4234116642
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2999099568
Short name T1354
Test name
Test status
Simulation time 1968122892 ps
CPU time 21.02 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:25:10 PM PDT 24
Peak memory 217932 kb
Host smart-746aabb8-d994-485d-ac72-d7c38ac73505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999099568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2999099568
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1121457372
Short name T1441
Test name
Test status
Simulation time 598504108 ps
CPU time 4.08 seconds
Started Jul 16 05:24:49 PM PDT 24
Finished Jul 16 05:24:53 PM PDT 24
Peak memory 205452 kb
Host smart-1e14f50a-bb4d-4679-a39e-40c030391dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121457372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1121457372
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2654283593
Short name T851
Test name
Test status
Simulation time 6353815512 ps
CPU time 65.8 seconds
Started Jul 16 05:24:56 PM PDT 24
Finished Jul 16 05:26:03 PM PDT 24
Peak memory 298688 kb
Host smart-6d16a329-3ee4-4422-a67d-717fbd1affe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654283593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2654283593
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2531678566
Short name T1656
Test name
Test status
Simulation time 3006029391 ps
CPU time 9.38 seconds
Started Jul 16 05:24:53 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 221676 kb
Host smart-0d88db09-1212-4a87-a7b3-ba7385bb5fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531678566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2531678566
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.771374613
Short name T409
Test name
Test status
Simulation time 4045801126 ps
CPU time 5.45 seconds
Started Jul 16 05:24:51 PM PDT 24
Finished Jul 16 05:24:57 PM PDT 24
Peak memory 213912 kb
Host smart-e385d345-8fca-4fef-8c29-be4c81aa9db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771374613 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.771374613
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.4094019680
Short name T1323
Test name
Test status
Simulation time 146979701 ps
CPU time 0.86 seconds
Started Jul 16 05:24:52 PM PDT 24
Finished Jul 16 05:24:54 PM PDT 24
Peak memory 205292 kb
Host smart-5209b454-2e0a-46d1-9015-f5f48e2a2684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094019680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.4094019680
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3483438654
Short name T690
Test name
Test status
Simulation time 236665025 ps
CPU time 0.79 seconds
Started Jul 16 05:24:51 PM PDT 24
Finished Jul 16 05:24:52 PM PDT 24
Peak memory 205440 kb
Host smart-3b9692e4-6176-42da-83aa-2ea932939892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483438654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3483438654
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2804575743
Short name T824
Test name
Test status
Simulation time 1802445513 ps
CPU time 2.28 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:05 PM PDT 24
Peak memory 205644 kb
Host smart-0e6d687e-6eef-41da-beaa-15c650af4914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804575743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2804575743
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.3637327428
Short name T703
Test name
Test status
Simulation time 325552152 ps
CPU time 1.53 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 205396 kb
Host smart-dedee645-98a0-4092-b872-40b519863460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637327428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.3637327428
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2437835011
Short name T1284
Test name
Test status
Simulation time 6282315037 ps
CPU time 2.36 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:24:51 PM PDT 24
Peak memory 213884 kb
Host smart-bbc184c0-8833-47e3-8b45-044d4a725363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437835011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2437835011
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.36921998
Short name T1119
Test name
Test status
Simulation time 1972985557 ps
CPU time 5.81 seconds
Started Jul 16 05:24:52 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 230060 kb
Host smart-fec4f221-5809-4b50-bfe5-a43fb01e9647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.36921998
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.901683446
Short name T1409
Test name
Test status
Simulation time 14346324621 ps
CPU time 21.24 seconds
Started Jul 16 05:24:54 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 486144 kb
Host smart-7c4f2f80-18af-46a8-8235-53437169193a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901683446 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.901683446
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.965140598
Short name T1695
Test name
Test status
Simulation time 517624881 ps
CPU time 2.9 seconds
Started Jul 16 05:25:02 PM PDT 24
Finished Jul 16 05:25:06 PM PDT 24
Peak memory 213848 kb
Host smart-63ae7442-3d9a-427b-a087-2d4065f96734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965140598 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_nack_acqfull.965140598
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.1009112862
Short name T922
Test name
Test status
Simulation time 770027887 ps
CPU time 3.04 seconds
Started Jul 16 05:25:03 PM PDT 24
Finished Jul 16 05:25:07 PM PDT 24
Peak memory 205476 kb
Host smart-2959f2a9-1289-43a9-88d9-4fcd9b8787b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009112862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.1009112862
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_txstretch.736846834
Short name T1309
Test name
Test status
Simulation time 132705344 ps
CPU time 1.61 seconds
Started Jul 16 05:25:03 PM PDT 24
Finished Jul 16 05:25:06 PM PDT 24
Peak memory 222352 kb
Host smart-c4e392ef-32c4-431e-93d6-2094945fa7bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736846834 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_nack_txstretch.736846834
Directory /workspace/23.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3483191096
Short name T952
Test name
Test status
Simulation time 1731351371 ps
CPU time 3.59 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:24:52 PM PDT 24
Peak memory 213844 kb
Host smart-72b6d27f-6ee1-40b6-9ec3-6090f7488a06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483191096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3483191096
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.155755374
Short name T846
Test name
Test status
Simulation time 509649275 ps
CPU time 2.36 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 205468 kb
Host smart-fc1be8bb-09fd-46dd-b58d-e3ac3388fcf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155755374 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_smbus_maxlen.155755374
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.700867314
Short name T1659
Test name
Test status
Simulation time 3233796310 ps
CPU time 13.11 seconds
Started Jul 16 05:24:50 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 213944 kb
Host smart-18e08261-b1bd-4db8-8af0-2ab9db37bb68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700867314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.700867314
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.3935577765
Short name T272
Test name
Test status
Simulation time 43633451822 ps
CPU time 158.77 seconds
Started Jul 16 05:24:51 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 1510840 kb
Host smart-753cab40-b5a8-4ce0-95ff-6a9eba909fda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935577765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.3935577765
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.38678101
Short name T806
Test name
Test status
Simulation time 2477692536 ps
CPU time 25.73 seconds
Started Jul 16 05:24:51 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 213856 kb
Host smart-4b8178ad-0c83-4496-a5d6-a66b110fee8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stress_rd.38678101
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1205983549
Short name T405
Test name
Test status
Simulation time 58014139679 ps
CPU time 167.76 seconds
Started Jul 16 05:24:50 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 1887484 kb
Host smart-497fd17a-9733-4a5b-80ca-d6be347e44b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205983549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1205983549
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2770757297
Short name T1582
Test name
Test status
Simulation time 2908951531 ps
CPU time 20.58 seconds
Started Jul 16 05:24:48 PM PDT 24
Finished Jul 16 05:25:09 PM PDT 24
Peak memory 280936 kb
Host smart-6a34f06b-3bd7-4633-a932-0f80ce23b252
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770757297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2770757297
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2605763658
Short name T1169
Test name
Test status
Simulation time 2592020210 ps
CPU time 6.66 seconds
Started Jul 16 05:24:52 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 213892 kb
Host smart-6089dbf1-090c-4e51-b89d-c3f22c3a1cb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605763658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2605763658
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2384257313
Short name T1638
Test name
Test status
Simulation time 144781878 ps
CPU time 2.92 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:05 PM PDT 24
Peak memory 205500 kb
Host smart-4f9ba59b-95bc-4a63-b935-8061c3fbfff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384257313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2384257313
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1280471928
Short name T1712
Test name
Test status
Simulation time 115531402 ps
CPU time 0.6 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 204816 kb
Host smart-eb9c3ca8-4257-4738-8cfc-2382c3a91dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280471928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1280471928
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2376124073
Short name T1492
Test name
Test status
Simulation time 1051006061 ps
CPU time 11.12 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 225288 kb
Host smart-7f0b1492-1c95-4e42-a168-5f04ad08ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376124073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2376124073
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3843527237
Short name T1330
Test name
Test status
Simulation time 698049558 ps
CPU time 7.4 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 276320 kb
Host smart-d008136a-dba0-4974-9e49-233d4a8d5758
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843527237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3843527237
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2187075904
Short name T940
Test name
Test status
Simulation time 1797262146 ps
CPU time 42.88 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:45 PM PDT 24
Peak memory 284836 kb
Host smart-8e972038-4299-43bf-a9d6-1472b68a66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187075904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2187075904
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3191514507
Short name T1639
Test name
Test status
Simulation time 12846110538 ps
CPU time 90.24 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 815196 kb
Host smart-e079ae32-4f08-4742-89f5-fcd3efe4097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191514507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3191514507
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2610142397
Short name T1399
Test name
Test status
Simulation time 102883546 ps
CPU time 1.02 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 205128 kb
Host smart-7d99e488-6097-4baf-9790-23460b85fba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610142397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2610142397
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3899180350
Short name T592
Test name
Test status
Simulation time 884434307 ps
CPU time 5.59 seconds
Started Jul 16 05:25:02 PM PDT 24
Finished Jul 16 05:25:09 PM PDT 24
Peak memory 205500 kb
Host smart-61b3898b-4b6c-40b9-a489-ab4177f102b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899180350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3899180350
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1241278960
Short name T1419
Test name
Test status
Simulation time 4153224169 ps
CPU time 97.6 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 1194128 kb
Host smart-949e5bf3-973e-490a-bbe0-ddb584012cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241278960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1241278960
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2965907847
Short name T1493
Test name
Test status
Simulation time 775696163 ps
CPU time 15.24 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:17 PM PDT 24
Peak memory 205368 kb
Host smart-0b997f87-63f3-48a4-a4d0-6757dc580a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965907847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2965907847
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.2385304563
Short name T1130
Test name
Test status
Simulation time 27344355 ps
CPU time 0.66 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 205144 kb
Host smart-e225b579-b6ef-42e0-8c31-a37702e85713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385304563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2385304563
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3459676648
Short name T1058
Test name
Test status
Simulation time 713094419 ps
CPU time 11.39 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:27 PM PDT 24
Peak memory 247580 kb
Host smart-acdb8d18-4145-48d3-9559-f4761af73080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459676648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3459676648
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.2956941905
Short name T1548
Test name
Test status
Simulation time 51723235 ps
CPU time 1.39 seconds
Started Jul 16 05:25:02 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 214404 kb
Host smart-51e77607-44ba-400d-b910-279df71eb893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956941905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.2956941905
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3744603199
Short name T1529
Test name
Test status
Simulation time 7758801821 ps
CPU time 94.33 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:26:34 PM PDT 24
Peak memory 383336 kb
Host smart-17fddf72-d9dd-4a1f-9a12-960609439329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744603199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3744603199
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1230947231
Short name T1364
Test name
Test status
Simulation time 537611840 ps
CPU time 9.94 seconds
Started Jul 16 05:24:58 PM PDT 24
Finished Jul 16 05:25:09 PM PDT 24
Peak memory 213724 kb
Host smart-427bcff4-bb9d-40bb-8cad-9270f549e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230947231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1230947231
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.477095201
Short name T809
Test name
Test status
Simulation time 4062245458 ps
CPU time 5.72 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:06 PM PDT 24
Peak memory 214996 kb
Host smart-868eaed1-92d8-4053-9bfa-1ee41ae8a027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477095201 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.477095201
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.622168041
Short name T522
Test name
Test status
Simulation time 205592793 ps
CPU time 1.43 seconds
Started Jul 16 05:25:11 PM PDT 24
Finished Jul 16 05:25:13 PM PDT 24
Peak memory 205452 kb
Host smart-dce75bef-250a-4770-a604-e007ab4a66f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622168041 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.622168041
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1165476132
Short name T988
Test name
Test status
Simulation time 173124208 ps
CPU time 1.17 seconds
Started Jul 16 05:33:38 PM PDT 24
Finished Jul 16 05:33:40 PM PDT 24
Peak memory 205472 kb
Host smart-0200d94d-099e-4fb2-b3cc-570317b95ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165476132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1165476132
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.4074112897
Short name T1735
Test name
Test status
Simulation time 439741154 ps
CPU time 2.9 seconds
Started Jul 16 05:25:03 PM PDT 24
Finished Jul 16 05:25:06 PM PDT 24
Peak memory 205584 kb
Host smart-22f9018d-7be7-450d-b685-1a7d683c1e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074112897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.4074112897
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1402889306
Short name T1079
Test name
Test status
Simulation time 1643885169 ps
CPU time 1.57 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:03 PM PDT 24
Peak memory 205488 kb
Host smart-732bd0ec-6214-445f-abb0-fa0d61689a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402889306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1402889306
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.631121819
Short name T69
Test name
Test status
Simulation time 3509555158 ps
CPU time 4.57 seconds
Started Jul 16 05:25:10 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 219412 kb
Host smart-3a0c2e3a-ed19-4c22-a8c1-cd32d68ecc16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631121819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.631121819
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2128581115
Short name T1143
Test name
Test status
Simulation time 8885078486 ps
CPU time 12.87 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 350536 kb
Host smart-58177bca-8623-4f11-a9d7-6330b7460db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128581115 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2128581115
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.558109424
Short name T1422
Test name
Test status
Simulation time 594588016 ps
CPU time 3.05 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:05 PM PDT 24
Peak memory 213736 kb
Host smart-78986257-6c05-4933-afa5-9f1dce4283ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558109424 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_nack_acqfull.558109424
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.3297956864
Short name T142
Test name
Test status
Simulation time 2509026790 ps
CPU time 2.98 seconds
Started Jul 16 05:25:03 PM PDT 24
Finished Jul 16 05:25:07 PM PDT 24
Peak memory 205604 kb
Host smart-9dcbf0cb-e86e-42b7-a577-4c56a26ed5be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297956864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3297956864
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_txstretch.3608023546
Short name T935
Test name
Test status
Simulation time 486741158 ps
CPU time 1.36 seconds
Started Jul 16 05:24:57 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 222404 kb
Host smart-5f0c4ecc-96b9-4464-bfa0-9614759381f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608023546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_nack_txstretch.3608023546
Directory /workspace/24.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2559087565
Short name T946
Test name
Test status
Simulation time 1989330982 ps
CPU time 7.27 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 229964 kb
Host smart-88849816-5864-46f0-80a5-0873b85d4ee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559087565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2559087565
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.260159874
Short name T1104
Test name
Test status
Simulation time 486289177 ps
CPU time 2.2 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:05 PM PDT 24
Peak memory 205356 kb
Host smart-5a3e4d16-a116-45d3-9135-a3a2696907f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260159874 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.260159874
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1094336721
Short name T1660
Test name
Test status
Simulation time 4106651145 ps
CPU time 14.48 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 213932 kb
Host smart-17fddac5-4140-4a1b-ba0a-aaff5d147f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094336721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1094336721
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.1483374879
Short name T1334
Test name
Test status
Simulation time 51026785600 ps
CPU time 144.96 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:29:51 PM PDT 24
Peak memory 1244672 kb
Host smart-6c06f626-4451-4ab2-8a71-34299d652747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483374879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.1483374879
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1700191106
Short name T450
Test name
Test status
Simulation time 2394068710 ps
CPU time 8.68 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:25 PM PDT 24
Peak memory 206024 kb
Host smart-7f7f88c5-4ef7-4e14-bf81-05463bc19e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700191106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1700191106
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3453372086
Short name T1105
Test name
Test status
Simulation time 26771808395 ps
CPU time 121.61 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 1769104 kb
Host smart-3adadf2c-1292-4a5e-8d50-8bd271bcc8e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453372086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3453372086
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.4129787072
Short name T1609
Test name
Test status
Simulation time 2249163892 ps
CPU time 39.44 seconds
Started Jul 16 05:32:06 PM PDT 24
Finished Jul 16 05:32:46 PM PDT 24
Peak memory 680120 kb
Host smart-403b7ec2-1fd5-44c2-abfc-86fef688fd36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129787072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.4129787072
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3945976163
Short name T1589
Test name
Test status
Simulation time 1270932527 ps
CPU time 7.88 seconds
Started Jul 16 05:25:03 PM PDT 24
Finished Jul 16 05:25:11 PM PDT 24
Peak memory 218900 kb
Host smart-a1939976-81f5-4cbb-8ea2-6a181f8f1329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945976163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3945976163
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.3989309101
Short name T512
Test name
Test status
Simulation time 452269752 ps
CPU time 6.44 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:06 PM PDT 24
Peak memory 206748 kb
Host smart-f74361cc-7514-4b6c-a42d-88842b866db7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989309101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3989309101
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.225772349
Short name T372
Test name
Test status
Simulation time 15121476 ps
CPU time 0.65 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 204724 kb
Host smart-f6a35159-1aa2-4b43-a571-d8db6aca0277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225772349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.225772349
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.657644941
Short name T348
Test name
Test status
Simulation time 118177438 ps
CPU time 3.42 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 221924 kb
Host smart-e292bf49-9680-4e30-9f1f-f0575f04c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657644941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.657644941
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.758708449
Short name T463
Test name
Test status
Simulation time 489690752 ps
CPU time 10.43 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:26 PM PDT 24
Peak memory 308368 kb
Host smart-53223ba1-a77c-4a25-9a9b-8db573ef95ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758708449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.758708449
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2408367793
Short name T743
Test name
Test status
Simulation time 3767930991 ps
CPU time 119.08 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:27:02 PM PDT 24
Peak memory 612340 kb
Host smart-2b448306-8f32-4110-b0d9-6e25cf09237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408367793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2408367793
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1058278855
Short name T1239
Test name
Test status
Simulation time 1280252624 ps
CPU time 39.31 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:25:41 PM PDT 24
Peak memory 521392 kb
Host smart-afb37f2b-de17-4269-bfa1-33c8d8cf070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058278855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1058278855
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3777320291
Short name T227
Test name
Test status
Simulation time 1038764519 ps
CPU time 1.13 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:25:04 PM PDT 24
Peak memory 205268 kb
Host smart-8ffec2b6-864b-43ff-90f8-7011281eda8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777320291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3777320291
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1681999113
Short name T219
Test name
Test status
Simulation time 817647159 ps
CPU time 3.93 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:21 PM PDT 24
Peak memory 225604 kb
Host smart-31b6e42f-5c6e-499d-9b3f-b3e8221ed343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681999113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1681999113
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2897177703
Short name T1736
Test name
Test status
Simulation time 17092866483 ps
CPU time 277.09 seconds
Started Jul 16 05:25:01 PM PDT 24
Finished Jul 16 05:29:40 PM PDT 24
Peak memory 1166800 kb
Host smart-43f1fc54-5aad-4d30-97c8-66bf4eee2299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897177703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2897177703
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.4104679561
Short name T243
Test name
Test status
Simulation time 1106996704 ps
CPU time 11.26 seconds
Started Jul 16 05:25:18 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 205544 kb
Host smart-fecfa989-a097-4258-b534-0627a790dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104679561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.4104679561
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.3055399427
Short name T1258
Test name
Test status
Simulation time 26400129 ps
CPU time 0.65 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 205216 kb
Host smart-f1ff718e-0b9b-41a4-ac63-16aed046aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055399427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3055399427
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1029077869
Short name T575
Test name
Test status
Simulation time 3031817933 ps
CPU time 116.33 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:27:12 PM PDT 24
Peak memory 205940 kb
Host smart-d2468e92-b07c-4973-be52-5d02afcceaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029077869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1029077869
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.2064716410
Short name T1116
Test name
Test status
Simulation time 261307111 ps
CPU time 5.41 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:22 PM PDT 24
Peak memory 205404 kb
Host smart-b7a01fbd-b9a5-448c-b061-20b21601f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064716410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.2064716410
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.327834483
Short name T773
Test name
Test status
Simulation time 2862458527 ps
CPU time 39.17 seconds
Started Jul 16 05:25:10 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 383520 kb
Host smart-3c5175c8-3915-4fe6-b4a2-516471b73688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327834483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.327834483
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2641766554
Short name T265
Test name
Test status
Simulation time 70429983602 ps
CPU time 412.06 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:32:07 PM PDT 24
Peak memory 1053560 kb
Host smart-f4a6b623-34a2-4ee3-804c-f36c0035392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641766554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2641766554
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3846823743
Short name T331
Test name
Test status
Simulation time 890371337 ps
CPU time 33.89 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:49 PM PDT 24
Peak memory 213716 kb
Host smart-ec3dbdb4-7e63-457e-a410-03642e18a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846823743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3846823743
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3377332973
Short name T1630
Test name
Test status
Simulation time 2981594436 ps
CPU time 4.25 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:25 PM PDT 24
Peak memory 217576 kb
Host smart-a7a60876-bcda-4d74-b2eb-f9cfdf7ddb70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377332973 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3377332973
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2758558363
Short name T1177
Test name
Test status
Simulation time 342126906 ps
CPU time 1.59 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:22 PM PDT 24
Peak memory 205540 kb
Host smart-df57b6a8-8617-4876-bc78-b06bb87bb18c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758558363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2758558363
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1885232996
Short name T650
Test name
Test status
Simulation time 151521922 ps
CPU time 0.99 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:15 PM PDT 24
Peak memory 205488 kb
Host smart-6e412b3b-7dc1-4794-ab18-878c72a038cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885232996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1885232996
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3781786331
Short name T584
Test name
Test status
Simulation time 497072994 ps
CPU time 1.17 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 205424 kb
Host smart-2ec4a090-a6f8-4a56-9238-69633fbcbc0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781786331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3781786331
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.904408454
Short name T475
Test name
Test status
Simulation time 118327007 ps
CPU time 0.89 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 205416 kb
Host smart-82bf75e6-33ae-4fe4-9b0d-eeaed3d61d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904408454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.904408454
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3024761659
Short name T1708
Test name
Test status
Simulation time 515158726 ps
CPU time 3.2 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 213904 kb
Host smart-49583562-8049-4b6e-b98c-77d137f204e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024761659 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3024761659
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1547150494
Short name T414
Test name
Test status
Simulation time 17365676528 ps
CPU time 38.61 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 866276 kb
Host smart-7932e1de-d986-4fc3-80a9-2edd402c9302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547150494 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1547150494
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.3365167288
Short name T1414
Test name
Test status
Simulation time 3249849906 ps
CPU time 3.33 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:25:20 PM PDT 24
Peak memory 213944 kb
Host smart-75ec34c8-282f-4324-8939-263bfe96edc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365167288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.3365167288
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.716045640
Short name T840
Test name
Test status
Simulation time 1890892027 ps
CPU time 2.42 seconds
Started Jul 16 05:26:44 PM PDT 24
Finished Jul 16 05:26:47 PM PDT 24
Peak memory 205516 kb
Host smart-56aa9f5c-901c-4464-81e1-5aaa3bf1e569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716045640 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.716045640
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.1936473667
Short name T959
Test name
Test status
Simulation time 529707847 ps
CPU time 1.39 seconds
Started Jul 16 05:25:18 PM PDT 24
Finished Jul 16 05:25:20 PM PDT 24
Peak memory 222244 kb
Host smart-609413da-b0c0-4770-8989-675add90033f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936473667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.1936473667
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/25.i2c_target_perf.2311477276
Short name T714
Test name
Test status
Simulation time 3202187094 ps
CPU time 6.39 seconds
Started Jul 16 05:25:22 PM PDT 24
Finished Jul 16 05:25:28 PM PDT 24
Peak memory 213920 kb
Host smart-30e3d789-c88e-4bcb-88dd-8ecc99250e2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311477276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.2311477276
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.215221159
Short name T990
Test name
Test status
Simulation time 524065177 ps
CPU time 2.41 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:38 PM PDT 24
Peak memory 205316 kb
Host smart-1b294fca-ee72-4efb-a8d9-b2d89d122f11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215221159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_smbus_maxlen.215221159
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1088674220
Short name T1498
Test name
Test status
Simulation time 1464975969 ps
CPU time 18.55 seconds
Started Jul 16 05:25:11 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 213840 kb
Host smart-7af4bedf-2464-4b97-823a-85067a0c0cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088674220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1088674220
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3163259351
Short name T828
Test name
Test status
Simulation time 1510314484 ps
CPU time 9.79 seconds
Started Jul 16 05:25:19 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 205580 kb
Host smart-47368501-6cf3-4f3b-be20-a0e9e1109383
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163259351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3163259351
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3858974522
Short name T695
Test name
Test status
Simulation time 11309615466 ps
CPU time 8.69 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 204740 kb
Host smart-301b05e8-9403-4715-9a86-45bbeff1f807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858974522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3858974522
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3788495973
Short name T1688
Test name
Test status
Simulation time 1744710166 ps
CPU time 16.66 seconds
Started Jul 16 05:25:17 PM PDT 24
Finished Jul 16 05:25:35 PM PDT 24
Peak memory 281004 kb
Host smart-22e7c771-052d-49be-af77-5177c2ea5946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788495973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3788495973
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3011039646
Short name T336
Test name
Test status
Simulation time 4548227740 ps
CPU time 7.05 seconds
Started Jul 16 05:25:12 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 221896 kb
Host smart-23c9bdcc-7b12-41f0-9078-3bf23d9cb2f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011039646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3011039646
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2896386339
Short name T273
Test name
Test status
Simulation time 268790437 ps
CPU time 4.44 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 205992 kb
Host smart-53714549-8602-4e4a-86b0-dcf826a4c757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896386339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2896386339
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.420439758
Short name T1303
Test name
Test status
Simulation time 18209532 ps
CPU time 0.64 seconds
Started Jul 16 05:25:34 PM PDT 24
Finished Jul 16 05:25:35 PM PDT 24
Peak memory 204756 kb
Host smart-1e712117-ff47-49e3-8dce-5239ecd6f03b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420439758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.420439758
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1239717619
Short name T1306
Test name
Test status
Simulation time 82730313 ps
CPU time 1.46 seconds
Started Jul 16 05:25:17 PM PDT 24
Finished Jul 16 05:25:19 PM PDT 24
Peak memory 213548 kb
Host smart-690489a6-5d6d-4302-ac80-481a627f592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239717619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1239717619
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3266247648
Short name T573
Test name
Test status
Simulation time 1627152300 ps
CPU time 21.28 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 295372 kb
Host smart-d893b8de-2135-4a8b-b4f7-f9a053ad36c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266247648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3266247648
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.20787608
Short name T801
Test name
Test status
Simulation time 17353775943 ps
CPU time 93.14 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:26:50 PM PDT 24
Peak memory 710400 kb
Host smart-c5176230-aa33-44eb-a6d5-ea2a67a290e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20787608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.20787608
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2306317657
Short name T468
Test name
Test status
Simulation time 9373753170 ps
CPU time 70.96 seconds
Started Jul 16 05:25:17 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 760604 kb
Host smart-4fa2de75-8212-4b20-a355-0bddbeb77043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306317657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2306317657
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3666214972
Short name T36
Test name
Test status
Simulation time 179672665 ps
CPU time 0.94 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 205204 kb
Host smart-fb31fa20-36ca-4786-ac41-212d8ae6a1c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666214972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3666214972
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3179376880
Short name T363
Test name
Test status
Simulation time 184697567 ps
CPU time 4.37 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:25:22 PM PDT 24
Peak memory 205468 kb
Host smart-a1a3731c-65fe-4edb-8f4b-d7b0ee54b0f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179376880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3179376880
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1034803601
Short name T1121
Test name
Test status
Simulation time 16544718146 ps
CPU time 80.49 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:26:37 PM PDT 24
Peak memory 1043404 kb
Host smart-bf145d5a-4e95-43d9-9734-f965a7dffd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034803601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1034803601
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3644179887
Short name T1448
Test name
Test status
Simulation time 252191184 ps
CPU time 3.83 seconds
Started Jul 16 05:25:23 PM PDT 24
Finished Jul 16 05:25:27 PM PDT 24
Peak memory 213732 kb
Host smart-7eca8fb6-1ff1-4ea1-aaa7-8527930c9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644179887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3644179887
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.26826270
Short name T1173
Test name
Test status
Simulation time 29894004 ps
CPU time 0.67 seconds
Started Jul 16 05:25:16 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 205188 kb
Host smart-d7a0c422-a242-4896-934e-cdfe4fff3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26826270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.26826270
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2586450625
Short name T1430
Test name
Test status
Simulation time 5499024375 ps
CPU time 77.11 seconds
Started Jul 16 05:25:21 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 526028 kb
Host smart-10aed8ff-1b18-4850-8dcb-2addc7f59c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586450625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2586450625
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.2537287108
Short name T1642
Test name
Test status
Simulation time 260999159 ps
CPU time 3.27 seconds
Started Jul 16 05:25:19 PM PDT 24
Finished Jul 16 05:25:23 PM PDT 24
Peak memory 229872 kb
Host smart-042bbddb-2752-4aab-b8c1-dd7f32d8198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537287108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.2537287108
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.2400591031
Short name T769
Test name
Test status
Simulation time 3195664005 ps
CPU time 70.12 seconds
Started Jul 16 05:25:12 PM PDT 24
Finished Jul 16 05:26:23 PM PDT 24
Peak memory 307720 kb
Host smart-e16d0e25-3d1d-4ef9-b49b-7d8eaabef0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400591031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2400591031
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3127103266
Short name T815
Test name
Test status
Simulation time 63036676315 ps
CPU time 945.5 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:52:20 PM PDT 24
Peak memory 2214228 kb
Host smart-71bae678-e0aa-44c3-bbf4-b3d1a5b56cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127103266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3127103266
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.206848660
Short name T760
Test name
Test status
Simulation time 870734881 ps
CPU time 14.79 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:35 PM PDT 24
Peak memory 216764 kb
Host smart-4b3ae68f-4922-4dec-9d78-f374a99ef332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206848660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.206848660
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2129320415
Short name T1015
Test name
Test status
Simulation time 12029016782 ps
CPU time 6.09 seconds
Started Jul 16 05:25:19 PM PDT 24
Finished Jul 16 05:25:27 PM PDT 24
Peak memory 210784 kb
Host smart-5348b6bc-d764-443d-9370-a4043208ead9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129320415 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2129320415
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3161331790
Short name T1254
Test name
Test status
Simulation time 192181560 ps
CPU time 1.24 seconds
Started Jul 16 05:25:19 PM PDT 24
Finished Jul 16 05:25:21 PM PDT 24
Peak memory 205560 kb
Host smart-f8a8aec2-9e6d-4f90-bdaa-5fd0c929f9d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161331790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3161331790
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.941433937
Short name T750
Test name
Test status
Simulation time 162063633 ps
CPU time 1.18 seconds
Started Jul 16 05:25:22 PM PDT 24
Finished Jul 16 05:25:23 PM PDT 24
Peak memory 205324 kb
Host smart-56e16d39-3a82-4687-8949-f16458160381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941433937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.941433937
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.2893910500
Short name T178
Test name
Test status
Simulation time 289412188 ps
CPU time 1.21 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 205300 kb
Host smart-b4ac6e73-617d-429c-a610-2cc4ac55a841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893910500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.2893910500
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.303820109
Short name T1350
Test name
Test status
Simulation time 284815846 ps
CPU time 1.2 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 205316 kb
Host smart-4b19f1c5-d45f-4f1a-a27f-8971e1b129eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303820109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.303820109
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2224320269
Short name T718
Test name
Test status
Simulation time 233011615 ps
CPU time 2 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 215400 kb
Host smart-3a9f7269-333c-49a3-8d7a-d7161729ad71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224320269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2224320269
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.896283900
Short name T1149
Test name
Test status
Simulation time 2564118595 ps
CPU time 8.66 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 222736 kb
Host smart-89716f33-a26a-4147-87a2-0de9ad25e0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896283900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.896283900
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.394648556
Short name T918
Test name
Test status
Simulation time 10262629251 ps
CPU time 187.02 seconds
Started Jul 16 05:25:12 PM PDT 24
Finished Jul 16 05:28:19 PM PDT 24
Peak memory 2621568 kb
Host smart-3e53ed8a-8212-4eef-a3fc-e406a725b6b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394648556 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.394648556
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.3356662843
Short name T719
Test name
Test status
Simulation time 609146138 ps
CPU time 2.92 seconds
Started Jul 16 05:25:22 PM PDT 24
Finished Jul 16 05:25:26 PM PDT 24
Peak memory 213828 kb
Host smart-1edda39c-67bd-4cc7-bcb6-237ddd5b41a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356662843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_nack_acqfull.3356662843
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.4125309175
Short name T678
Test name
Test status
Simulation time 1198421770 ps
CPU time 2.86 seconds
Started Jul 16 05:25:30 PM PDT 24
Finished Jul 16 05:25:34 PM PDT 24
Peak memory 205604 kb
Host smart-301fa223-ee8d-4be3-82f8-f07b67955226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125309175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.4125309175
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.3827045857
Short name T1359
Test name
Test status
Simulation time 649582243 ps
CPU time 4.7 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:21 PM PDT 24
Peak memory 213872 kb
Host smart-bc5ef79e-7dd8-454e-ad13-0e6df8ef4d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827045857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.3827045857
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.2080632996
Short name T818
Test name
Test status
Simulation time 371239663 ps
CPU time 2.05 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:30 PM PDT 24
Peak memory 205396 kb
Host smart-e8ff3383-272a-4e58-bec9-1d6dd012bdc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080632996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.2080632996
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3828763557
Short name T1342
Test name
Test status
Simulation time 970014367 ps
CPU time 14.15 seconds
Started Jul 16 05:25:12 PM PDT 24
Finished Jul 16 05:25:26 PM PDT 24
Peak memory 213740 kb
Host smart-2019a79e-5212-4b48-b7f8-e76a1f16fa96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828763557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3828763557
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.4275100387
Short name T193
Test name
Test status
Simulation time 130164547111 ps
CPU time 264.62 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:29:38 PM PDT 24
Peak memory 2232972 kb
Host smart-be268956-7dff-42ac-9864-0dadce0ee39f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275100387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.4275100387
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3144976707
Short name T1442
Test name
Test status
Simulation time 446146417 ps
CPU time 8.2 seconds
Started Jul 16 05:25:20 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 213024 kb
Host smart-99446813-13af-473f-a119-19aa7b7c2a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144976707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3144976707
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2465232937
Short name T616
Test name
Test status
Simulation time 44574386369 ps
CPU time 109.41 seconds
Started Jul 16 05:25:12 PM PDT 24
Finished Jul 16 05:27:02 PM PDT 24
Peak memory 1590228 kb
Host smart-f132767e-8111-4c44-af91-f51c33f5f0f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465232937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2465232937
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.542923972
Short name T494
Test name
Test status
Simulation time 2888457424 ps
CPU time 6.66 seconds
Started Jul 16 05:25:19 PM PDT 24
Finished Jul 16 05:25:26 PM PDT 24
Peak memory 218848 kb
Host smart-0c5d1b18-5b12-484b-8b85-80bf643dbe58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542923972 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.542923972
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.3601139553
Short name T339
Test name
Test status
Simulation time 91992369 ps
CPU time 1.65 seconds
Started Jul 16 05:25:31 PM PDT 24
Finished Jul 16 05:25:33 PM PDT 24
Peak memory 205588 kb
Host smart-65021a8d-01b6-4216-b7d1-e12de7b069c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601139553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3601139553
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1721256304
Short name T977
Test name
Test status
Simulation time 15132994 ps
CPU time 0.62 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:27 PM PDT 24
Peak memory 204748 kb
Host smart-433804eb-38fc-4e22-b4fc-8f13d0c53d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721256304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1721256304
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2288912669
Short name T22
Test name
Test status
Simulation time 540248205 ps
CPU time 2.17 seconds
Started Jul 16 05:29:02 PM PDT 24
Finished Jul 16 05:29:05 PM PDT 24
Peak memory 213636 kb
Host smart-09c15ec6-4d4e-4211-b32d-f34a0d717571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288912669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2288912669
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.4079193287
Short name T1410
Test name
Test status
Simulation time 963220666 ps
CPU time 20.65 seconds
Started Jul 16 05:25:25 PM PDT 24
Finished Jul 16 05:25:47 PM PDT 24
Peak memory 274440 kb
Host smart-6456b473-ce04-415b-ad70-337e6f853895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079193287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.4079193287
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1950407898
Short name T827
Test name
Test status
Simulation time 1788910925 ps
CPU time 53.23 seconds
Started Jul 16 05:25:23 PM PDT 24
Finished Jul 16 05:26:16 PM PDT 24
Peak memory 534072 kb
Host smart-dc25e933-4ade-467e-a2a0-988a364cf9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950407898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1950407898
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2274106571
Short name T383
Test name
Test status
Simulation time 10503117978 ps
CPU time 124.41 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:27:31 PM PDT 24
Peak memory 626744 kb
Host smart-9ff65381-72bf-4228-8288-36234d6bd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274106571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2274106571
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2734174662
Short name T1550
Test name
Test status
Simulation time 378132104 ps
CPU time 1.15 seconds
Started Jul 16 05:25:33 PM PDT 24
Finished Jul 16 05:25:35 PM PDT 24
Peak memory 205392 kb
Host smart-211f744a-9c2f-4c71-9cf0-0c2ce9be775a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734174662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2734174662
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.534910326
Short name T1538
Test name
Test status
Simulation time 374267949 ps
CPU time 5.1 seconds
Started Jul 16 05:25:23 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 237660 kb
Host smart-ba735884-cd7f-45c9-8b82-fc92392bb357
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534910326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
534910326
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1190630301
Short name T32
Test name
Test status
Simulation time 17874107474 ps
CPU time 303.65 seconds
Started Jul 16 05:29:02 PM PDT 24
Finished Jul 16 05:34:07 PM PDT 24
Peak memory 1277876 kb
Host smart-587a7fde-b4a8-43f1-9bf5-7fb29208daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190630301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1190630301
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2211694124
Short name T1056
Test name
Test status
Simulation time 2281918004 ps
CPU time 6.86 seconds
Started Jul 16 05:25:29 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 205364 kb
Host smart-095531cf-cced-4b7b-9ec0-5afd398992b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211694124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2211694124
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.2535969946
Short name T1052
Test name
Test status
Simulation time 24150129 ps
CPU time 0.65 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:28 PM PDT 24
Peak memory 205168 kb
Host smart-77a3a458-3952-4717-82ee-864c805d1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535969946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2535969946
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.4222270187
Short name T1533
Test name
Test status
Simulation time 887419759 ps
CPU time 11.03 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:29:13 PM PDT 24
Peak memory 280636 kb
Host smart-ab59616d-2e9d-4c08-bc6e-7eb04e096f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222270187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.4222270187
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.226061425
Short name T1109
Test name
Test status
Simulation time 774104416 ps
CPU time 9.01 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 240012 kb
Host smart-57e2e9c6-ecdd-4628-9074-2f045d8d6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226061425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.226061425
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.636956163
Short name T349
Test name
Test status
Simulation time 18988377433 ps
CPU time 104.73 seconds
Started Jul 16 05:25:31 PM PDT 24
Finished Jul 16 05:27:17 PM PDT 24
Peak memory 434176 kb
Host smart-b58744bb-0570-4e87-99d7-f8c591df3e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636956163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.636956163
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.4086401723
Short name T1704
Test name
Test status
Simulation time 994974094 ps
CPU time 12.36 seconds
Started Jul 16 05:25:23 PM PDT 24
Finished Jul 16 05:25:36 PM PDT 24
Peak memory 221880 kb
Host smart-9e0d4ed9-43a5-4c67-917d-f7830a4fc56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086401723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.4086401723
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2400174728
Short name T1514
Test name
Test status
Simulation time 1174585544 ps
CPU time 6.09 seconds
Started Jul 16 05:25:29 PM PDT 24
Finished Jul 16 05:25:36 PM PDT 24
Peak memory 214684 kb
Host smart-6ece4c7c-6b9e-4bae-b664-f6796b39cfdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400174728 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2400174728
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1216610161
Short name T669
Test name
Test status
Simulation time 516967884 ps
CPU time 1.06 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 205404 kb
Host smart-ba917acf-3aae-4fad-afe4-e6eadb044c84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216610161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1216610161
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.635486738
Short name T1298
Test name
Test status
Simulation time 303704521 ps
CPU time 1.2 seconds
Started Jul 16 05:25:29 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 205216 kb
Host smart-6c0d6d47-2439-4e9e-b6f0-e0b218ddbf02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635486738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.635486738
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.1883484938
Short name T681
Test name
Test status
Simulation time 612799720 ps
CPU time 3.17 seconds
Started Jul 16 05:25:25 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 205788 kb
Host smart-ceb983f8-d8fb-4b9d-b1a5-1dec143141bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883484938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.1883484938
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.341379788
Short name T310
Test name
Test status
Simulation time 145811316 ps
CPU time 1.21 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:29 PM PDT 24
Peak memory 205400 kb
Host smart-a45873f1-92f9-4b99-8dc8-5aa93e65ba06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341379788 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.341379788
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.745253312
Short name T10
Test name
Test status
Simulation time 979887180 ps
CPU time 6.2 seconds
Started Jul 16 05:25:32 PM PDT 24
Finished Jul 16 05:25:39 PM PDT 24
Peak memory 222072 kb
Host smart-07fa0200-90a7-4cef-b570-aeed08430bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745253312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.745253312
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3948339649
Short name T1674
Test name
Test status
Simulation time 8973933428 ps
CPU time 25.06 seconds
Started Jul 16 05:25:25 PM PDT 24
Finished Jul 16 05:25:51 PM PDT 24
Peak memory 495288 kb
Host smart-1291b42b-616d-42f4-94d6-db21477e1d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948339649 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3948339649
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.1447866827
Short name T369
Test name
Test status
Simulation time 1828489195 ps
CPU time 2.59 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:27:11 PM PDT 24
Peak memory 213728 kb
Host smart-e8c7db8c-bcd1-4ff1-a40b-ed6d85ed7c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447866827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.1447866827
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.2062729877
Short name T298
Test name
Test status
Simulation time 1075170045 ps
CPU time 2.78 seconds
Started Jul 16 05:25:31 PM PDT 24
Finished Jul 16 05:25:35 PM PDT 24
Peak memory 205608 kb
Host smart-2a7f1030-6c11-48a7-aff6-883e168b9158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062729877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.2062729877
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.937478596
Short name T326
Test name
Test status
Simulation time 2877878904 ps
CPU time 4.51 seconds
Started Jul 16 05:25:32 PM PDT 24
Finished Jul 16 05:25:38 PM PDT 24
Peak memory 214688 kb
Host smart-d311cc91-f6aa-4b2c-b985-750398ec8f45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937478596 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_perf.937478596
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.384897636
Short name T366
Test name
Test status
Simulation time 973704869 ps
CPU time 2.23 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 205440 kb
Host smart-cd34b56b-e6d4-4aa3-ad08-35f2e8100f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384897636 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_smbus_maxlen.384897636
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1010218950
Short name T1122
Test name
Test status
Simulation time 5961307079 ps
CPU time 14.73 seconds
Started Jul 16 05:25:32 PM PDT 24
Finished Jul 16 05:25:47 PM PDT 24
Peak memory 213896 kb
Host smart-e8fc602c-9655-462e-9c55-2d8c88384d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010218950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1010218950
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.3874239788
Short name T731
Test name
Test status
Simulation time 101816033140 ps
CPU time 95.47 seconds
Started Jul 16 05:25:30 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 691636 kb
Host smart-a4da3f92-4a4b-4984-9d8f-df03227ae656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874239788 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.3874239788
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.464493014
Short name T361
Test name
Test status
Simulation time 2360546627 ps
CPU time 11.62 seconds
Started Jul 16 05:33:54 PM PDT 24
Finished Jul 16 05:34:06 PM PDT 24
Peak memory 205572 kb
Host smart-b007d9c1-8223-487b-8203-c7bbc52b6532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464493014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.464493014
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2974962684
Short name T1667
Test name
Test status
Simulation time 12502740027 ps
CPU time 24.86 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:25:53 PM PDT 24
Peak memory 205608 kb
Host smart-0ea56d9c-162a-42fa-bb2b-1d92357c5d7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974962684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2974962684
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.1031825171
Short name T1489
Test name
Test status
Simulation time 4991204455 ps
CPU time 60.12 seconds
Started Jul 16 05:25:27 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 856252 kb
Host smart-9ffc3762-7ec6-4f09-81dc-2850104fc72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031825171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.1031825171
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3767173927
Short name T593
Test name
Test status
Simulation time 1195425110 ps
CPU time 6.02 seconds
Started Jul 16 05:25:24 PM PDT 24
Finished Jul 16 05:25:31 PM PDT 24
Peak memory 219152 kb
Host smart-3f00e46b-edfe-45b6-96f1-450a1491411c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767173927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3767173927
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.3350558236
Short name T883
Test name
Test status
Simulation time 105086492 ps
CPU time 2.34 seconds
Started Jul 16 05:25:31 PM PDT 24
Finished Jul 16 05:25:34 PM PDT 24
Peak memory 205584 kb
Host smart-e06de8c2-5aa0-4556-ab17-64f7fb47f048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350558236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3350558236
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1852419878
Short name T1076
Test name
Test status
Simulation time 39587209 ps
CPU time 0.58 seconds
Started Jul 16 05:25:36 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 204536 kb
Host smart-0f67ae14-dae0-4f3d-a598-1ffced40a78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852419878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1852419878
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2061700349
Short name T1011
Test name
Test status
Simulation time 937152731 ps
CPU time 7.7 seconds
Started Jul 16 05:25:42 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 237996 kb
Host smart-862dfd1d-fd1d-4541-b84e-b25203f40799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061700349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2061700349
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2984651789
Short name T1475
Test name
Test status
Simulation time 567675737 ps
CPU time 14 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:41 PM PDT 24
Peak memory 262764 kb
Host smart-1fbf12f6-b5db-420f-bb32-ee1c174f05ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984651789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2984651789
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.1372420774
Short name T374
Test name
Test status
Simulation time 4014605148 ps
CPU time 312.57 seconds
Started Jul 16 05:33:53 PM PDT 24
Finished Jul 16 05:39:06 PM PDT 24
Peak memory 968348 kb
Host smart-98f5343a-9ae5-4b02-9951-d13f1af81512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372420774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1372420774
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3386907098
Short name T1294
Test name
Test status
Simulation time 4862102354 ps
CPU time 73.85 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:28:42 PM PDT 24
Peak memory 802696 kb
Host smart-43e3b2ab-8885-4de6-a5ed-bae1ca54cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386907098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3386907098
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3013966101
Short name T1094
Test name
Test status
Simulation time 286792737 ps
CPU time 1.11 seconds
Started Jul 16 05:25:26 PM PDT 24
Finished Jul 16 05:25:28 PM PDT 24
Peak memory 205224 kb
Host smart-301eaa4f-5118-4b09-b0d1-1b51677f77b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013966101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3013966101
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1613202415
Short name T1737
Test name
Test status
Simulation time 925215914 ps
CPU time 4.93 seconds
Started Jul 16 05:25:36 PM PDT 24
Finished Jul 16 05:25:42 PM PDT 24
Peak memory 205452 kb
Host smart-7d44cca4-1e3a-413d-8f62-eb405b678a3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613202415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1613202415
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2329519062
Short name T43
Test name
Test status
Simulation time 20207206423 ps
CPU time 369.71 seconds
Started Jul 16 05:25:31 PM PDT 24
Finished Jul 16 05:31:41 PM PDT 24
Peak memory 1462868 kb
Host smart-91cb1714-763d-4989-a335-281154483506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329519062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2329519062
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2547678665
Short name T863
Test name
Test status
Simulation time 795385902 ps
CPU time 5.52 seconds
Started Jul 16 05:25:38 PM PDT 24
Finished Jul 16 05:25:44 PM PDT 24
Peak memory 205396 kb
Host smart-2404f1fd-e1cb-45f3-ac5d-ae209d8b5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547678665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2547678665
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3822482135
Short name T766
Test name
Test status
Simulation time 170745475 ps
CPU time 2.06 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:24 PM PDT 24
Peak memory 213680 kb
Host smart-4209a32d-7ba7-46b5-be3b-e65f3c8d3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822482135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3822482135
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2278768323
Short name T373
Test name
Test status
Simulation time 17630058 ps
CPU time 0.66 seconds
Started Jul 16 05:25:32 PM PDT 24
Finished Jul 16 05:25:34 PM PDT 24
Peak memory 204852 kb
Host smart-3ae782cc-cfb4-483d-9769-9a082b6dd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278768323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2278768323
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2096146938
Short name T736
Test name
Test status
Simulation time 11927005628 ps
CPU time 68.26 seconds
Started Jul 16 05:25:38 PM PDT 24
Finished Jul 16 05:26:47 PM PDT 24
Peak memory 213796 kb
Host smart-cc5151cb-226f-4868-8802-d958b4fb02e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096146938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2096146938
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.396878659
Short name T781
Test name
Test status
Simulation time 597601885 ps
CPU time 2.14 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:26:58 PM PDT 24
Peak memory 205464 kb
Host smart-655d50d8-9ec5-4de0-b8fb-35f2fcd625de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396878659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.396878659
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2056168098
Short name T1527
Test name
Test status
Simulation time 1492166780 ps
CPU time 25.32 seconds
Started Jul 16 05:25:24 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 316804 kb
Host smart-c65b4b3c-f038-4b5b-9e75-8dbc40c1aee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056168098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2056168098
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3121665534
Short name T1531
Test name
Test status
Simulation time 8347761864 ps
CPU time 594.47 seconds
Started Jul 16 05:25:42 PM PDT 24
Finished Jul 16 05:35:37 PM PDT 24
Peak memory 1207016 kb
Host smart-b7c3a250-d0b3-4a03-b8a0-a3a61cd327b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121665534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3121665534
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2854722286
Short name T682
Test name
Test status
Simulation time 2096077729 ps
CPU time 23.88 seconds
Started Jul 16 05:32:06 PM PDT 24
Finished Jul 16 05:32:30 PM PDT 24
Peak memory 213700 kb
Host smart-86a13f88-59a1-421e-9064-030c5ae150e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854722286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2854722286
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1676891386
Short name T1333
Test name
Test status
Simulation time 5026209193 ps
CPU time 5.86 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:25:42 PM PDT 24
Peak memory 213748 kb
Host smart-85f1c03c-d77d-4d3a-b2cf-5751eb0f8c14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676891386 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1676891386
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1664168489
Short name T454
Test name
Test status
Simulation time 167052480 ps
CPU time 1.11 seconds
Started Jul 16 05:25:34 PM PDT 24
Finished Jul 16 05:25:36 PM PDT 24
Peak memory 205396 kb
Host smart-c2336482-921f-442a-95cf-c26cc9ac5e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664168489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1664168489
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2081934951
Short name T288
Test name
Test status
Simulation time 819381566 ps
CPU time 1.35 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 205572 kb
Host smart-98283994-3026-4cdf-991a-5ae2f131b8a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081934951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2081934951
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.3235634392
Short name T445
Test name
Test status
Simulation time 2263666825 ps
CPU time 1.55 seconds
Started Jul 16 05:25:32 PM PDT 24
Finished Jul 16 05:25:34 PM PDT 24
Peak memory 205452 kb
Host smart-398daae2-0947-4c49-8cd2-68c36e9052f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235634392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3235634392
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.2504043629
Short name T1252
Test name
Test status
Simulation time 265437999 ps
CPU time 1.22 seconds
Started Jul 16 05:33:53 PM PDT 24
Finished Jul 16 05:33:54 PM PDT 24
Peak memory 205484 kb
Host smart-902baec4-153a-4c55-92e8-4ebea0a2daea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504043629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.2504043629
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3331516005
Short name T1687
Test name
Test status
Simulation time 1324526145 ps
CPU time 2.1 seconds
Started Jul 16 05:25:34 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 213844 kb
Host smart-a7b992e6-ff27-4e34-8419-a73706642a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331516005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3331516005
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2570478199
Short name T354
Test name
Test status
Simulation time 14974365449 ps
CPU time 5.78 seconds
Started Jul 16 05:32:04 PM PDT 24
Finished Jul 16 05:32:10 PM PDT 24
Peak memory 230792 kb
Host smart-bf71b077-39d5-4691-84d1-ab4c3451818d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570478199 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2570478199
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.29448698
Short name T902
Test name
Test status
Simulation time 2036466276 ps
CPU time 13.4 seconds
Started Jul 16 05:25:33 PM PDT 24
Finished Jul 16 05:25:47 PM PDT 24
Peak memory 636968 kb
Host smart-8b56768b-e09b-47e0-b0fa-852259759abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448698 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.29448698
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.3000644106
Short name T1621
Test name
Test status
Simulation time 4240515396 ps
CPU time 2.84 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:20 PM PDT 24
Peak memory 213868 kb
Host smart-42bdf7b8-246a-4028-8ce4-9cff13e8451b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000644106 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.3000644106
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.2285343859
Short name T662
Test name
Test status
Simulation time 439380087 ps
CPU time 2.27 seconds
Started Jul 16 05:25:38 PM PDT 24
Finished Jul 16 05:25:41 PM PDT 24
Peak memory 205636 kb
Host smart-47be0087-4864-4056-bf4c-dc2b159a1e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285343859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.2285343859
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_txstretch.3211635512
Short name T1332
Test name
Test status
Simulation time 133312477 ps
CPU time 1.35 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:25:38 PM PDT 24
Peak memory 222076 kb
Host smart-5c156106-a9d5-4e00-858d-6d6936eef77a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211635512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_nack_txstretch.3211635512
Directory /workspace/28.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/28.i2c_target_perf.1414501410
Short name T1623
Test name
Test status
Simulation time 3614757758 ps
CPU time 6.81 seconds
Started Jul 16 05:25:34 PM PDT 24
Finished Jul 16 05:25:42 PM PDT 24
Peak memory 218016 kb
Host smart-9e1ecec1-23b8-4ebd-83d0-32164c70a895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414501410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.1414501410
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.254190771
Short name T1508
Test name
Test status
Simulation time 1599769743 ps
CPU time 1.97 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:25:40 PM PDT 24
Peak memory 205384 kb
Host smart-849cdde1-3552-44e3-b5a1-522903952c95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254190771 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_smbus_maxlen.254190771
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1030206439
Short name T1440
Test name
Test status
Simulation time 3417287428 ps
CPU time 11.94 seconds
Started Jul 16 05:25:42 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 213856 kb
Host smart-89f82b87-a197-4437-8c92-9fee4d589550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030206439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1030206439
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.1460313632
Short name T603
Test name
Test status
Simulation time 39216061323 ps
CPU time 46.58 seconds
Started Jul 16 05:25:36 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 423924 kb
Host smart-dcddd22b-ea7c-4898-af66-ad759817b851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460313632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.1460313632
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1574988121
Short name T479
Test name
Test status
Simulation time 8055627151 ps
CPU time 41.35 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:26:17 PM PDT 24
Peak memory 230368 kb
Host smart-60acadb7-d09f-4f20-a1ca-31c3027c4c44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574988121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1574988121
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2338013623
Short name T1316
Test name
Test status
Simulation time 31578819898 ps
CPU time 18.46 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 469768 kb
Host smart-6fa553d1-04ff-471d-adbf-f775af18f9e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338013623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2338013623
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2101964214
Short name T516
Test name
Test status
Simulation time 1303898466 ps
CPU time 25.76 seconds
Started Jul 16 05:25:36 PM PDT 24
Finished Jul 16 05:26:03 PM PDT 24
Peak memory 329944 kb
Host smart-39ba5ffb-51ba-4206-9e51-5638644d8587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101964214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2101964214
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3972034155
Short name T290
Test name
Test status
Simulation time 1054954991 ps
CPU time 6.31 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:27:02 PM PDT 24
Peak memory 213812 kb
Host smart-87d60367-5742-4e2e-9b64-4867d665906b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972034155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3972034155
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.831402235
Short name T1007
Test name
Test status
Simulation time 680188758 ps
CPU time 9.5 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:25:48 PM PDT 24
Peak memory 206660 kb
Host smart-cf23a629-c29c-4504-a744-2a3919f1740f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831402235 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.831402235
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2906611847
Short name T399
Test name
Test status
Simulation time 39332163 ps
CPU time 0.62 seconds
Started Jul 16 05:25:47 PM PDT 24
Finished Jul 16 05:25:49 PM PDT 24
Peak memory 204676 kb
Host smart-1f58b5a9-79b7-469a-8998-601d09e77205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906611847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2906611847
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.438963360
Short name T1317
Test name
Test status
Simulation time 79034737 ps
CPU time 1.33 seconds
Started Jul 16 05:25:48 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 216416 kb
Host smart-cb5f3652-522f-4570-9c77-b09a881e462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438963360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.438963360
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2024133557
Short name T1086
Test name
Test status
Simulation time 693691322 ps
CPU time 17.55 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 251956 kb
Host smart-4d1213cd-3acc-4511-870d-e3d5d9c32a4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024133557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2024133557
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2749950202
Short name T1161
Test name
Test status
Simulation time 2787265202 ps
CPU time 213.32 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 701384 kb
Host smart-afed79a4-7531-448e-a9e8-2994311433b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749950202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2749950202
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2823073457
Short name T1142
Test name
Test status
Simulation time 1895603138 ps
CPU time 54.99 seconds
Started Jul 16 05:25:33 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 590528 kb
Host smart-5fa1d96e-d0e3-4293-a19c-dfce7434c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823073457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2823073457
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3928835867
Short name T735
Test name
Test status
Simulation time 713556545 ps
CPU time 1.26 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:25:39 PM PDT 24
Peak memory 205356 kb
Host smart-e999de08-5d44-4abe-8b7e-cd9f89eb05af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928835867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3928835867
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1648454543
Short name T1637
Test name
Test status
Simulation time 494496271 ps
CPU time 5.37 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:25:43 PM PDT 24
Peak memory 205464 kb
Host smart-59ddc4f8-1650-451e-b1c4-5afb26425c3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648454543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1648454543
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.696339399
Short name T104
Test name
Test status
Simulation time 58009949531 ps
CPU time 95.79 seconds
Started Jul 16 05:25:37 PM PDT 24
Finished Jul 16 05:27:14 PM PDT 24
Peak memory 1188784 kb
Host smart-12ad2e35-494a-4c0d-991e-c405cf0e0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696339399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.696339399
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.2778164224
Short name T236
Test name
Test status
Simulation time 4859399391 ps
CPU time 8.43 seconds
Started Jul 16 05:25:45 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 205528 kb
Host smart-5abb3286-d45d-4b75-aecc-5db57eb4ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778164224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2778164224
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1623783711
Short name T470
Test name
Test status
Simulation time 49143987296 ps
CPU time 2923.15 seconds
Started Jul 16 05:25:38 PM PDT 24
Finished Jul 16 06:14:22 PM PDT 24
Peak memory 3793888 kb
Host smart-78dba760-78ba-4c46-82e2-36a0c549c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623783711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1623783711
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.587251015
Short name T631
Test name
Test status
Simulation time 409022252 ps
CPU time 1.43 seconds
Started Jul 16 05:25:35 PM PDT 24
Finished Jul 16 05:25:37 PM PDT 24
Peak memory 217196 kb
Host smart-db144060-08ce-4737-a927-578499439a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587251015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.587251015
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.4210554463
Short name T1581
Test name
Test status
Simulation time 1675372711 ps
CPU time 31.59 seconds
Started Jul 16 05:25:42 PM PDT 24
Finished Jul 16 05:26:14 PM PDT 24
Peak memory 364208 kb
Host smart-203081ff-aa38-4796-bec9-00b92fe65bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210554463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.4210554463
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.4215901422
Short name T1269
Test name
Test status
Simulation time 991363170 ps
CPU time 21.85 seconds
Started Jul 16 05:28:59 PM PDT 24
Finished Jul 16 05:29:24 PM PDT 24
Peak memory 213592 kb
Host smart-5bf83db8-3fac-4c8e-a4d8-1fe270978d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215901422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4215901422
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3492474016
Short name T1371
Test name
Test status
Simulation time 917968709 ps
CPU time 4.27 seconds
Started Jul 16 05:25:43 PM PDT 24
Finished Jul 16 05:25:48 PM PDT 24
Peak memory 221920 kb
Host smart-1f48b1a0-6665-4725-b57f-7ed34de02a55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492474016 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3492474016
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2703404914
Short name T636
Test name
Test status
Simulation time 132784788 ps
CPU time 0.78 seconds
Started Jul 16 05:25:49 PM PDT 24
Finished Jul 16 05:25:51 PM PDT 24
Peak memory 205448 kb
Host smart-8d8bb900-bde4-4b44-89ef-52a4fe77ffdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703404914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2703404914
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1260622768
Short name T702
Test name
Test status
Simulation time 400777574 ps
CPU time 0.94 seconds
Started Jul 16 05:25:47 PM PDT 24
Finished Jul 16 05:25:49 PM PDT 24
Peak memory 205584 kb
Host smart-34968dcd-465f-4e67-9099-e3eb382c57e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260622768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1260622768
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.1272461784
Short name T313
Test name
Test status
Simulation time 607683076 ps
CPU time 2.91 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 205604 kb
Host smart-de961bf5-240c-4475-b5fc-e638f1ea6dc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272461784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.1272461784
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2606162196
Short name T430
Test name
Test status
Simulation time 588800638 ps
CPU time 1.77 seconds
Started Jul 16 05:31:00 PM PDT 24
Finished Jul 16 05:31:02 PM PDT 24
Peak memory 205292 kb
Host smart-f03ad931-b36b-4b6b-902a-08bd8758826d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606162196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2606162196
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1696966515
Short name T1635
Test name
Test status
Simulation time 2050958374 ps
CPU time 5.64 seconds
Started Jul 16 05:25:44 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 221920 kb
Host smart-e902e388-f67f-4d4e-a0fc-4b1f0001a066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696966515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1696966515
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3412712145
Short name T1146
Test name
Test status
Simulation time 11362766228 ps
CPU time 48.6 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:30:12 PM PDT 24
Peak memory 1205840 kb
Host smart-956bb49e-3748-485b-9d21-de65997ba154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412712145 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3412712145
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.4038433198
Short name T1590
Test name
Test status
Simulation time 491173665 ps
CPU time 2.67 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:09 PM PDT 24
Peak memory 213492 kb
Host smart-dd3c1b8c-bb30-4c90-ac73-aa9972f6835c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038433198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.4038433198
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.2624072631
Short name T825
Test name
Test status
Simulation time 5018512113 ps
CPU time 2.39 seconds
Started Jul 16 05:25:45 PM PDT 24
Finished Jul 16 05:25:48 PM PDT 24
Peak memory 205536 kb
Host smart-cb156aef-0093-4766-b7d5-2f8c4812c34b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624072631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2624072631
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_txstretch.3366761136
Short name T1696
Test name
Test status
Simulation time 162981064 ps
CPU time 1.66 seconds
Started Jul 16 05:31:00 PM PDT 24
Finished Jul 16 05:31:02 PM PDT 24
Peak memory 222060 kb
Host smart-674d0af6-7267-4dc9-8029-0a2e90c407a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366761136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_nack_txstretch.3366761136
Directory /workspace/29.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_target_perf.1456964797
Short name T1432
Test name
Test status
Simulation time 661445184 ps
CPU time 5.35 seconds
Started Jul 16 05:25:48 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 219196 kb
Host smart-9e7ebcf9-ab0b-4faa-ad3d-4f576e730af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456964797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.1456964797
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.2293395568
Short name T397
Test name
Test status
Simulation time 855848874 ps
CPU time 2.25 seconds
Started Jul 16 05:25:46 PM PDT 24
Finished Jul 16 05:25:49 PM PDT 24
Peak memory 205372 kb
Host smart-a8871f9e-fc1c-4a66-bd6b-32ce9332eea8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293395568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.2293395568
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.731611134
Short name T1467
Test name
Test status
Simulation time 6081770364 ps
CPU time 19.42 seconds
Started Jul 16 05:25:45 PM PDT 24
Finished Jul 16 05:26:05 PM PDT 24
Peak memory 213772 kb
Host smart-58e7cce7-f046-43dc-9c53-b1e4c318ab9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731611134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.731611134
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.2591516642
Short name T317
Test name
Test status
Simulation time 53242910434 ps
CPU time 105.51 seconds
Started Jul 16 05:25:46 PM PDT 24
Finished Jul 16 05:27:32 PM PDT 24
Peak memory 768524 kb
Host smart-db74243b-daa4-4b18-a007-d9d8a05cfbcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591516642 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.2591516642
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3664621509
Short name T1055
Test name
Test status
Simulation time 3549191689 ps
CPU time 16.86 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:47 PM PDT 24
Peak memory 220712 kb
Host smart-7f945eaa-951b-4d17-9ec0-18b7647d4178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664621509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3664621509
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.1447779625
Short name T537
Test name
Test status
Simulation time 9426826737 ps
CPU time 17.54 seconds
Started Jul 16 05:25:47 PM PDT 24
Finished Jul 16 05:26:05 PM PDT 24
Peak memory 205660 kb
Host smart-37c2e24f-11d0-4549-b287-554656bb970a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447779625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.1447779625
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3920040892
Short name T1320
Test name
Test status
Simulation time 2896219230 ps
CPU time 16.1 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:26:08 PM PDT 24
Peak memory 425572 kb
Host smart-9faf21c4-b7b0-4582-9c6a-33c53d5acaec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920040892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3920040892
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2077051749
Short name T710
Test name
Test status
Simulation time 1258403830 ps
CPU time 7.14 seconds
Started Jul 16 05:25:47 PM PDT 24
Finished Jul 16 05:25:55 PM PDT 24
Peak memory 222064 kb
Host smart-10095a3e-bbe3-4ec9-80e7-ce0f0af0ff4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077051749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2077051749
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1498651182
Short name T400
Test name
Test status
Simulation time 566163405 ps
CPU time 8.17 seconds
Started Jul 16 05:31:00 PM PDT 24
Finished Jul 16 05:31:09 PM PDT 24
Peak memory 205448 kb
Host smart-3d4a9608-b101-4948-b4b1-8ab639b0e0f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498651182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1498651182
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.512480204
Short name T1098
Test name
Test status
Simulation time 40313165 ps
CPU time 0.62 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 204728 kb
Host smart-53265206-7bc3-4d7a-a756-5d7148a7434f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512480204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.512480204
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3460443747
Short name T1420
Test name
Test status
Simulation time 1082613889 ps
CPU time 4.36 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 213664 kb
Host smart-b31f385f-f6aa-4499-ad3d-574e602d390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460443747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3460443747
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2325376731
Short name T920
Test name
Test status
Simulation time 1171099514 ps
CPU time 16.3 seconds
Started Jul 16 05:24:59 PM PDT 24
Finished Jul 16 05:25:17 PM PDT 24
Peak memory 273044 kb
Host smart-474b3409-45ae-4af1-b137-e36e48b3c37f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325376731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2325376731
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.897065369
Short name T1615
Test name
Test status
Simulation time 6535331313 ps
CPU time 233.91 seconds
Started Jul 16 05:22:19 PM PDT 24
Finished Jul 16 05:26:13 PM PDT 24
Peak memory 678124 kb
Host smart-79b4a7df-e3ea-4d8c-a7c9-493a614e9c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897065369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.897065369
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2062912019
Short name T1315
Test name
Test status
Simulation time 21725338256 ps
CPU time 51.22 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:23:16 PM PDT 24
Peak memory 639460 kb
Host smart-24527ed6-d07e-4153-82b8-1a7ed7643940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062912019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2062912019
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3796898634
Short name T1423
Test name
Test status
Simulation time 132444623 ps
CPU time 1.18 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:23 PM PDT 24
Peak memory 205088 kb
Host smart-fc27857c-d21f-417e-9fda-a179447e2887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796898634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3796898634
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3898884923
Short name T439
Test name
Test status
Simulation time 2124757584 ps
CPU time 3.16 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:25 PM PDT 24
Peak memory 205388 kb
Host smart-707eedc8-2157-4912-a0ed-dd2225b16035
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898884923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3898884923
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2492626936
Short name T1226
Test name
Test status
Simulation time 18084224270 ps
CPU time 341.88 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:28:03 PM PDT 24
Peak memory 1333644 kb
Host smart-1f7c1b62-ca86-4a4e-94cb-7e1102019c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492626936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2492626936
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_override.963371007
Short name T1168
Test name
Test status
Simulation time 47833410 ps
CPU time 0.66 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:23 PM PDT 24
Peak memory 205140 kb
Host smart-79e6e403-96f7-4635-8563-b06893765ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963371007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.963371007
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1703888553
Short name T1203
Test name
Test status
Simulation time 6605850899 ps
CPU time 475.12 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:30:19 PM PDT 24
Peak memory 1505224 kb
Host smart-5316414a-cdc3-4fe2-8f85-8188f69d159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703888553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1703888553
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.97761982
Short name T45
Test name
Test status
Simulation time 73644814 ps
CPU time 1.47 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:22:25 PM PDT 24
Peak memory 225612 kb
Host smart-19bbf39b-d92c-4dd8-a939-c4f8d65cf257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97761982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.97761982
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1112363466
Short name T1487
Test name
Test status
Simulation time 6404360461 ps
CPU time 79.49 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:23:44 PM PDT 24
Peak memory 335644 kb
Host smart-290ef73b-d74e-4abd-b4a6-61cf6d3a08ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112363466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1112363466
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4169288755
Short name T648
Test name
Test status
Simulation time 804053574 ps
CPU time 13.11 seconds
Started Jul 16 05:22:22 PM PDT 24
Finished Jul 16 05:22:37 PM PDT 24
Peak memory 220000 kb
Host smart-14d5e987-3e2e-4f3f-bfa5-9caa49e6ebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169288755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4169288755
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3035138764
Short name T177
Test name
Test status
Simulation time 592488164 ps
CPU time 0.86 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:37 PM PDT 24
Peak memory 223748 kb
Host smart-f957c5e9-a637-40bd-94f9-520b761191c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035138764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3035138764
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3493226452
Short name T535
Test name
Test status
Simulation time 1931213111 ps
CPU time 5.44 seconds
Started Jul 16 05:22:12 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 219652 kb
Host smart-4cd465df-c7a6-4696-90d9-b30315589286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493226452 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3493226452
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2506428131
Short name T396
Test name
Test status
Simulation time 282879110 ps
CPU time 1.55 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:22:25 PM PDT 24
Peak memory 207128 kb
Host smart-72e85ffa-907f-4c5c-b294-eb9ee95190d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506428131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2506428131
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2958468341
Short name T407
Test name
Test status
Simulation time 521101665 ps
CPU time 2.79 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:24 PM PDT 24
Peak memory 205560 kb
Host smart-cb38352c-9020-4a7b-8958-8593a9f7ee01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958468341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2958468341
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.88481470
Short name T279
Test name
Test status
Simulation time 126321907 ps
CPU time 1.15 seconds
Started Jul 16 05:22:35 PM PDT 24
Finished Jul 16 05:22:37 PM PDT 24
Peak memory 203212 kb
Host smart-fb33b565-7fb1-4747-b900-82aaddc90321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88481470 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.88481470
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3114494789
Short name T1384
Test name
Test status
Simulation time 888224346 ps
CPU time 6.21 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 221916 kb
Host smart-8764d7a6-62f9-4b0c-8149-bd55f16fd89d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114494789 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3114494789
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1676425528
Short name T1711
Test name
Test status
Simulation time 20281910621 ps
CPU time 55.77 seconds
Started Jul 16 05:22:13 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 1165964 kb
Host smart-44c1b3b8-dcbc-4175-818b-f0b319d121a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676425528 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1676425528
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.1456049888
Short name T996
Test name
Test status
Simulation time 486663095 ps
CPU time 2.77 seconds
Started Jul 16 05:22:27 PM PDT 24
Finished Jul 16 05:22:31 PM PDT 24
Peak memory 213772 kb
Host smart-18b41552-100f-4541-94b7-91ac2495521d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456049888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.1456049888
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.1039956100
Short name T51
Test name
Test status
Simulation time 521208848 ps
CPU time 2.71 seconds
Started Jul 16 05:22:31 PM PDT 24
Finished Jul 16 05:22:34 PM PDT 24
Peak memory 205576 kb
Host smart-043f7c25-a5bc-4480-8ab2-377b10f7246d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039956100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.1039956100
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_txstretch.797415821
Short name T768
Test name
Test status
Simulation time 509252356 ps
CPU time 1.33 seconds
Started Jul 16 05:22:27 PM PDT 24
Finished Jul 16 05:22:29 PM PDT 24
Peak memory 222288 kb
Host smart-b09c70ca-f120-405c-894f-76a39d3ec1a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797415821 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_nack_txstretch.797415821
Directory /workspace/3.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/3.i2c_target_perf.3203163603
Short name T8
Test name
Test status
Simulation time 752836200 ps
CPU time 5.7 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:16 PM PDT 24
Peak memory 213860 kb
Host smart-be83c1b1-bcda-48e2-832e-0ae99aac4ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203163603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.3203163603
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.842289970
Short name T1554
Test name
Test status
Simulation time 600686465 ps
CPU time 2.83 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 205404 kb
Host smart-05c02075-7677-469b-9890-5235953b126b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842289970 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_smbus_maxlen.842289970
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.356112205
Short name T1366
Test name
Test status
Simulation time 899651470 ps
CPU time 10.34 seconds
Started Jul 16 05:34:08 PM PDT 24
Finished Jul 16 05:34:19 PM PDT 24
Peak memory 213732 kb
Host smart-93801b47-1178-424a-a29a-4a9399de1835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356112205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.356112205
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1567536229
Short name T56
Test name
Test status
Simulation time 51426369872 ps
CPU time 175.32 seconds
Started Jul 16 05:22:56 PM PDT 24
Finished Jul 16 05:25:53 PM PDT 24
Peak memory 1706540 kb
Host smart-da580b29-8897-4a90-acbe-2038b68740e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567536229 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1567536229
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3297540680
Short name T476
Test name
Test status
Simulation time 4597993758 ps
CPU time 22.69 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 222008 kb
Host smart-438d3e38-89ed-4068-99e4-8aeef9f5d136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297540680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3297540680
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.4178912177
Short name T921
Test name
Test status
Simulation time 16168169018 ps
CPU time 32.92 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 205668 kb
Host smart-8251fc3d-6a26-4b76-b98e-cabb345d3931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178912177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.4178912177
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3452869476
Short name T833
Test name
Test status
Simulation time 346253547 ps
CPU time 2.06 seconds
Started Jul 16 05:22:56 PM PDT 24
Finished Jul 16 05:22:59 PM PDT 24
Peak memory 213928 kb
Host smart-499468c4-540a-43c1-9273-1468ece6c778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452869476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3452869476
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1901971879
Short name T582
Test name
Test status
Simulation time 3687797695 ps
CPU time 7.14 seconds
Started Jul 16 05:36:22 PM PDT 24
Finished Jul 16 05:36:30 PM PDT 24
Peak memory 230608 kb
Host smart-a71c352b-e528-48b3-902e-4c03cee42908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901971879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1901971879
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.3658472925
Short name T1155
Test name
Test status
Simulation time 83107177 ps
CPU time 1.91 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:17 PM PDT 24
Peak memory 205624 kb
Host smart-75e835b8-1ed4-4724-95a6-461629d9f03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658472925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3658472925
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1745888653
Short name T1611
Test name
Test status
Simulation time 45826529 ps
CPU time 0.65 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:09 PM PDT 24
Peak memory 204852 kb
Host smart-4a27960c-1af9-4c21-990f-b4213e7f334c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745888653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1745888653
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3126684557
Short name T595
Test name
Test status
Simulation time 460519660 ps
CPU time 2.57 seconds
Started Jul 16 05:25:49 PM PDT 24
Finished Jul 16 05:25:53 PM PDT 24
Peak memory 221928 kb
Host smart-2f0df5b8-bd4c-481f-a252-c858a8cfd9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126684557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3126684557
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1573536861
Short name T281
Test name
Test status
Simulation time 707975181 ps
CPU time 6.76 seconds
Started Jul 16 05:25:45 PM PDT 24
Finished Jul 16 05:25:53 PM PDT 24
Peak memory 274232 kb
Host smart-736b5f98-f3a9-426c-824e-3e6c3c088486
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573536861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1573536861
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3912804621
Short name T585
Test name
Test status
Simulation time 2976455950 ps
CPU time 64.14 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:26:55 PM PDT 24
Peak memory 432944 kb
Host smart-9cd63fc3-6a6e-4e21-b5e4-3a3a910efe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912804621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3912804621
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.848353186
Short name T802
Test name
Test status
Simulation time 5190240997 ps
CPU time 88.83 seconds
Started Jul 16 05:25:51 PM PDT 24
Finished Jul 16 05:27:20 PM PDT 24
Peak memory 801616 kb
Host smart-c3f1c003-84c5-4af8-83f8-e9e00f2fb424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848353186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.848353186
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.479489671
Short name T1671
Test name
Test status
Simulation time 110557946 ps
CPU time 0.98 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:27:27 PM PDT 24
Peak memory 205188 kb
Host smart-3b0e8458-82ca-4293-af15-6aab2037e1f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479489671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.479489671
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1222389652
Short name T1449
Test name
Test status
Simulation time 222553458 ps
CPU time 5.55 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:25:56 PM PDT 24
Peak memory 205508 kb
Host smart-83da9767-5def-4dad-8a01-04c90ba5053d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222389652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1222389652
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3655331178
Short name T106
Test name
Test status
Simulation time 12688782234 ps
CPU time 80.2 seconds
Started Jul 16 05:25:45 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 1061408 kb
Host smart-b472ba99-b2fb-4847-8684-cfc965f8e111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655331178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3655331178
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.229880916
Short name T433
Test name
Test status
Simulation time 1087393765 ps
CPU time 6.91 seconds
Started Jul 16 05:26:06 PM PDT 24
Finished Jul 16 05:26:13 PM PDT 24
Peak memory 205492 kb
Host smart-6c99de0d-f12f-41d6-aef7-294f163e4ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229880916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.229880916
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.2922587169
Short name T989
Test name
Test status
Simulation time 46021284 ps
CPU time 0.7 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:25:53 PM PDT 24
Peak memory 205116 kb
Host smart-0bcfb5d9-7e0e-4ec4-9ae3-d0d39592d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922587169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2922587169
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.485181199
Short name T882
Test name
Test status
Simulation time 7559075843 ps
CPU time 32.15 seconds
Started Jul 16 05:25:44 PM PDT 24
Finished Jul 16 05:26:17 PM PDT 24
Peak memory 362436 kb
Host smart-d716a610-bb10-49f7-840a-6bfca5ffeae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485181199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.485181199
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.560194053
Short name T510
Test name
Test status
Simulation time 217494821 ps
CPU time 6.09 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:29 PM PDT 24
Peak memory 213624 kb
Host smart-f58af8ce-2727-4679-9b53-663ad1809fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560194053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.560194053
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2684196957
Short name T1100
Test name
Test status
Simulation time 7611067652 ps
CPU time 91.42 seconds
Started Jul 16 05:25:53 PM PDT 24
Finished Jul 16 05:27:25 PM PDT 24
Peak memory 341344 kb
Host smart-eea980a5-add0-42e7-9fdb-89545f310172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684196957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2684196957
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.290359073
Short name T1603
Test name
Test status
Simulation time 917059154 ps
CPU time 42.1 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 213776 kb
Host smart-4dfa9743-1566-422f-9229-040226e05673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290359073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.290359073
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3300797929
Short name T393
Test name
Test status
Simulation time 723195521 ps
CPU time 4.01 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:25:57 PM PDT 24
Peak memory 213800 kb
Host smart-666422e7-bd0b-4e6c-8851-a14f0f7bb936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300797929 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3300797929
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3923996222
Short name T403
Test name
Test status
Simulation time 152573938 ps
CPU time 1.08 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 205380 kb
Host smart-2875b71b-b223-457c-8d22-d6ec53396a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923996222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3923996222
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.965258728
Short name T394
Test name
Test status
Simulation time 468877695 ps
CPU time 1.2 seconds
Started Jul 16 05:25:48 PM PDT 24
Finished Jul 16 05:25:50 PM PDT 24
Peak memory 205648 kb
Host smart-c6b087aa-bdb9-42ac-b7a2-baaace074738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965258728 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.965258728
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.174344655
Short name T1205
Test name
Test status
Simulation time 546816888 ps
CPU time 2.9 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:11 PM PDT 24
Peak memory 205656 kb
Host smart-a5e978be-0d42-4aed-adc6-1796b584e651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174344655 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.174344655
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.622398694
Short name T1172
Test name
Test status
Simulation time 98417749 ps
CPU time 1.22 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:20 PM PDT 24
Peak memory 205412 kb
Host smart-b6ffafb6-5d53-47ec-9743-35366cc7eb5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622398694 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.622398694
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2985300652
Short name T1431
Test name
Test status
Simulation time 265640556 ps
CPU time 2.02 seconds
Started Jul 16 05:25:48 PM PDT 24
Finished Jul 16 05:25:51 PM PDT 24
Peak memory 213776 kb
Host smart-1a923391-8fb4-4710-b122-66e59082078e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985300652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2985300652
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1489161304
Short name T995
Test name
Test status
Simulation time 881887418 ps
CPU time 5.57 seconds
Started Jul 16 05:33:57 PM PDT 24
Finished Jul 16 05:34:03 PM PDT 24
Peak memory 213860 kb
Host smart-9ee15daa-90be-48ec-8953-b47963780022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489161304 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1489161304
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2319559349
Short name T799
Test name
Test status
Simulation time 19373196537 ps
CPU time 344.28 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:31:36 PM PDT 24
Peak memory 3767992 kb
Host smart-c2009d26-5c30-4af6-8b65-bb28866e018e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319559349 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2319559349
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.3393099109
Short name T693
Test name
Test status
Simulation time 520731654 ps
CPU time 2.81 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:14 PM PDT 24
Peak memory 213736 kb
Host smart-8189296c-450b-4716-8b64-f1d2278660c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393099109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.3393099109
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.2456871959
Short name T1556
Test name
Test status
Simulation time 1823463730 ps
CPU time 2.48 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:26 PM PDT 24
Peak memory 205560 kb
Host smart-b6c6e562-8b5b-4de2-936c-1bc5dbdd3a07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456871959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.2456871959
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.986071890
Short name T1219
Test name
Test status
Simulation time 892831326 ps
CPU time 6.03 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:27:15 PM PDT 24
Peak memory 219968 kb
Host smart-e6f68463-bbb6-451d-8d47-2a7246d0f043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986071890 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.986071890
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.572698283
Short name T459
Test name
Test status
Simulation time 2122770342 ps
CPU time 2.43 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:33 PM PDT 24
Peak memory 205344 kb
Host smart-b355c8ed-1dbf-4776-b380-50fc6d96c6fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572698283 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_smbus_maxlen.572698283
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1763855020
Short name T323
Test name
Test status
Simulation time 5240299048 ps
CPU time 15.72 seconds
Started Jul 16 05:32:12 PM PDT 24
Finished Jul 16 05:32:28 PM PDT 24
Peak memory 213912 kb
Host smart-01bfcc35-2cd5-4b09-b2b3-0e5ef138f817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763855020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1763855020
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.2855043773
Short name T306
Test name
Test status
Simulation time 30515586012 ps
CPU time 430.77 seconds
Started Jul 16 05:25:46 PM PDT 24
Finished Jul 16 05:32:58 PM PDT 24
Peak memory 4614924 kb
Host smart-385523fe-c543-4c05-b18a-40f86180f208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855043773 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.2855043773
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2743427948
Short name T1247
Test name
Test status
Simulation time 1173455614 ps
CPU time 50.51 seconds
Started Jul 16 05:25:46 PM PDT 24
Finished Jul 16 05:26:38 PM PDT 24
Peak memory 221916 kb
Host smart-306925dc-c9cf-42c7-b707-49e5a6eaf4f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743427948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2743427948
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3145438826
Short name T1509
Test name
Test status
Simulation time 24435307862 ps
CPU time 87.3 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 1250380 kb
Host smart-7b22fe1e-fbe9-44b0-bd53-0265c3a70757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145438826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3145438826
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2338131623
Short name T814
Test name
Test status
Simulation time 4585525618 ps
CPU time 11.79 seconds
Started Jul 16 05:33:59 PM PDT 24
Finished Jul 16 05:34:11 PM PDT 24
Peak memory 327980 kb
Host smart-e42f0d1b-6def-4394-88e0-874f89b58608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338131623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2338131623
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3554275597
Short name T596
Test name
Test status
Simulation time 5257213047 ps
CPU time 7.16 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:25:58 PM PDT 24
Peak memory 230236 kb
Host smart-1e02d6f4-2c3d-4330-810d-1ed86afc53a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554275597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3554275597
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.3070362606
Short name T53
Test name
Test status
Simulation time 287359935 ps
CPU time 4.91 seconds
Started Jul 16 05:26:04 PM PDT 24
Finished Jul 16 05:26:09 PM PDT 24
Peak memory 206564 kb
Host smart-c9a33596-645b-407a-a85e-40861865e806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070362606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3070362606
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3789641686
Short name T1673
Test name
Test status
Simulation time 42398363 ps
CPU time 0.64 seconds
Started Jul 16 05:32:06 PM PDT 24
Finished Jul 16 05:32:07 PM PDT 24
Peak memory 204584 kb
Host smart-cf740fb7-110c-4aab-84a8-9cf316fc1e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789641686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3789641686
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1046968759
Short name T767
Test name
Test status
Simulation time 276523494 ps
CPU time 1.98 seconds
Started Jul 16 05:26:05 PM PDT 24
Finished Jul 16 05:26:07 PM PDT 24
Peak memory 205456 kb
Host smart-722ef7ae-7d28-4af4-b211-4918276b46c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046968759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1046968759
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1416435170
Short name T783
Test name
Test status
Simulation time 370248573 ps
CPU time 7.03 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:18 PM PDT 24
Peak memory 285116 kb
Host smart-2d236666-6400-4af9-95a4-d33420a53946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416435170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1416435170
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.68685304
Short name T1636
Test name
Test status
Simulation time 9121027874 ps
CPU time 120.03 seconds
Started Jul 16 05:34:13 PM PDT 24
Finished Jul 16 05:36:14 PM PDT 24
Peak memory 355536 kb
Host smart-6c56de1f-3332-4e41-9c53-9c9717646fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68685304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.68685304
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2891690911
Short name T904
Test name
Test status
Simulation time 8001141590 ps
CPU time 35.99 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 512824 kb
Host smart-96f7078f-ba9d-4870-8764-aa8e9376fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891690911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2891690911
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1568283853
Short name T1085
Test name
Test status
Simulation time 164258063 ps
CPU time 1.23 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:12 PM PDT 24
Peak memory 205172 kb
Host smart-36b2b0f1-cf1c-4ba5-bf49-b74af61a9055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568283853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1568283853
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.532456976
Short name T1681
Test name
Test status
Simulation time 802891155 ps
CPU time 10.29 seconds
Started Jul 16 05:27:07 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 205404 kb
Host smart-15bde4c4-a0d0-4877-ab65-be67b41282a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532456976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
532456976
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1772832283
Short name T431
Test name
Test status
Simulation time 17034638198 ps
CPU time 308.34 seconds
Started Jul 16 05:26:04 PM PDT 24
Finished Jul 16 05:31:13 PM PDT 24
Peak memory 1267452 kb
Host smart-b15f76d0-de98-4cb4-87ab-2fc8530e0ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772832283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1772832283
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2799835883
Short name T441
Test name
Test status
Simulation time 669330648 ps
CPU time 6.78 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:27 PM PDT 24
Peak memory 205488 kb
Host smart-dfc978f2-ef72-40c7-bf3f-c62a84905f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799835883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2799835883
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1394566766
Short name T1041
Test name
Test status
Simulation time 120408074 ps
CPU time 3.86 seconds
Started Jul 16 05:26:20 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 213700 kb
Host smart-c8d6b555-34e5-4576-bf1e-e63a4dd00f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394566766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1394566766
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2824920344
Short name T740
Test name
Test status
Simulation time 16027909 ps
CPU time 0.67 seconds
Started Jul 16 05:26:04 PM PDT 24
Finished Jul 16 05:26:06 PM PDT 24
Peak memory 205212 kb
Host smart-61651d71-65db-4e55-b8ff-4f641368a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824920344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2824920344
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3835906198
Short name T871
Test name
Test status
Simulation time 13148842806 ps
CPU time 317.98 seconds
Started Jul 16 05:32:13 PM PDT 24
Finished Jul 16 05:37:31 PM PDT 24
Peak memory 1453872 kb
Host smart-d7b2c28f-6291-4ded-b8ca-810f9834526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835906198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3835906198
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.3010871350
Short name T1061
Test name
Test status
Simulation time 435169293 ps
CPU time 1.02 seconds
Started Jul 16 05:26:08 PM PDT 24
Finished Jul 16 05:26:10 PM PDT 24
Peak memory 205268 kb
Host smart-21ccb874-ca19-4469-ad78-d63a55e5af9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010871350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3010871350
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.198961262
Short name T255
Test name
Test status
Simulation time 5081408439 ps
CPU time 22.69 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 302960 kb
Host smart-73d94492-1ff4-41ec-a51c-8cd311808ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198961262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.198961262
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.420107705
Short name T746
Test name
Test status
Simulation time 6528469256 ps
CPU time 35.94 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 213788 kb
Host smart-fc91fc6e-89f5-4d4a-bb2e-10c319c7fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420107705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.420107705
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2847134114
Short name T1223
Test name
Test status
Simulation time 878797248 ps
CPU time 4.47 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:24 PM PDT 24
Peak memory 213776 kb
Host smart-3ba9cbfe-0680-4f94-839f-4ef492666704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847134114 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2847134114
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3375216668
Short name T1670
Test name
Test status
Simulation time 772816905 ps
CPU time 1.41 seconds
Started Jul 16 05:29:15 PM PDT 24
Finished Jul 16 05:29:17 PM PDT 24
Peak memory 209192 kb
Host smart-10b685e7-f581-46c8-a650-1597f7fa1cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375216668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3375216668
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.991609339
Short name T910
Test name
Test status
Simulation time 187341202 ps
CPU time 1.16 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:09 PM PDT 24
Peak memory 213652 kb
Host smart-c11914fc-b509-4461-8ed1-c287506d390a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991609339 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.991609339
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2067485918
Short name T1532
Test name
Test status
Simulation time 1939481160 ps
CPU time 2.54 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:20 PM PDT 24
Peak memory 205660 kb
Host smart-634ce268-2027-4b52-9a97-4a9df0d867a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067485918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2067485918
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.2449196092
Short name T838
Test name
Test status
Simulation time 546999017 ps
CPU time 1.46 seconds
Started Jul 16 05:32:06 PM PDT 24
Finished Jul 16 05:32:08 PM PDT 24
Peak memory 205360 kb
Host smart-3b2c7bb8-88bf-4e9b-a83e-8022d87328ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449196092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.2449196092
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.634374920
Short name T1082
Test name
Test status
Simulation time 2312319339 ps
CPU time 1.97 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 214580 kb
Host smart-f2ea033e-644f-4031-bea2-752425251805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634374920 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.634374920
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3136778881
Short name T614
Test name
Test status
Simulation time 2089773423 ps
CPU time 6.87 seconds
Started Jul 16 05:32:04 PM PDT 24
Finished Jul 16 05:32:12 PM PDT 24
Peak memory 221912 kb
Host smart-a3b966a7-d53b-4073-a38c-883d1871403b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136778881 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3136778881
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2570343594
Short name T1176
Test name
Test status
Simulation time 6118663492 ps
CPU time 8.02 seconds
Started Jul 16 05:26:06 PM PDT 24
Finished Jul 16 05:26:15 PM PDT 24
Peak memory 205600 kb
Host smart-257d3659-dd54-4648-8956-dc24008b9433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570343594 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2570343594
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.911457434
Short name T885
Test name
Test status
Simulation time 647230106 ps
CPU time 2.78 seconds
Started Jul 16 05:31:27 PM PDT 24
Finished Jul 16 05:31:30 PM PDT 24
Peak memory 213752 kb
Host smart-bdb6f7db-00d7-4845-9364-c20e71e6d4d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911457434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_nack_acqfull.911457434
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.1375577383
Short name T1501
Test name
Test status
Simulation time 921136730 ps
CPU time 2.61 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 205632 kb
Host smart-bbcfe436-5480-4aa4-9618-dad5097e7890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375577383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.1375577383
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.1227652233
Short name T972
Test name
Test status
Simulation time 548009234 ps
CPU time 1.42 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:17 PM PDT 24
Peak memory 222200 kb
Host smart-38112c59-7394-46b9-9f1f-85c9b36db447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227652233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_txstretch.1227652233
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.2231216779
Short name T376
Test name
Test status
Simulation time 932635940 ps
CPU time 5.56 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:14 PM PDT 24
Peak memory 221720 kb
Host smart-367d9cba-0299-45b5-832d-1b8c190c6330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231216779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.2231216779
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.3704325964
Short name T881
Test name
Test status
Simulation time 526976556 ps
CPU time 2.26 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 205444 kb
Host smart-fa969418-51df-4405-b3a7-97215a022f63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704325964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.3704325964
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2256264092
Short name T286
Test name
Test status
Simulation time 2357271068 ps
CPU time 19.76 seconds
Started Jul 16 05:26:07 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 213864 kb
Host smart-baaa9f2d-a4f0-4dce-a92d-b84cc3c1a6a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256264092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2256264092
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.1003765864
Short name T1676
Test name
Test status
Simulation time 75686904667 ps
CPU time 125.98 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:30:58 PM PDT 24
Peak memory 788464 kb
Host smart-f02421a9-0c99-40d7-aec4-01ae3ff79723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003765864 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.1003765864
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.967694036
Short name T1024
Test name
Test status
Simulation time 687680855 ps
CPU time 11.4 seconds
Started Jul 16 05:26:06 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 209796 kb
Host smart-9e9619ca-b256-4f0c-9cb1-478f91e96c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967694036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.967694036
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1419877463
Short name T1014
Test name
Test status
Simulation time 61934518038 ps
CPU time 286.22 seconds
Started Jul 16 05:26:03 PM PDT 24
Finished Jul 16 05:30:50 PM PDT 24
Peak memory 2606548 kb
Host smart-f48d5c9a-ad06-4da7-b3fc-7f62bde45488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419877463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1419877463
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.781837429
Short name T1461
Test name
Test status
Simulation time 1830716658 ps
CPU time 3.13 seconds
Started Jul 16 05:32:06 PM PDT 24
Finished Jul 16 05:32:09 PM PDT 24
Peak memory 213812 kb
Host smart-3345075b-f366-48d2-90be-5952e227f2f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781837429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.781837429
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1372073706
Short name T502
Test name
Test status
Simulation time 4787228192 ps
CPU time 6.87 seconds
Started Jul 16 05:31:07 PM PDT 24
Finished Jul 16 05:31:14 PM PDT 24
Peak memory 220128 kb
Host smart-87e4e28d-4816-43a2-837c-00544f448c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372073706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1372073706
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.19523404
Short name T1068
Test name
Test status
Simulation time 152075445 ps
CPU time 2.97 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 205132 kb
Host smart-3534321f-dfbe-4181-b2e7-75ce40f458c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523404 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.19523404
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.110483533
Short name T654
Test name
Test status
Simulation time 17190413 ps
CPU time 0.63 seconds
Started Jul 16 05:26:19 PM PDT 24
Finished Jul 16 05:26:20 PM PDT 24
Peak memory 204736 kb
Host smart-1056e428-1564-4e96-88c4-00e1426f67c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110483533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.110483533
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1075433723
Short name T1174
Test name
Test status
Simulation time 302979125 ps
CPU time 2.09 seconds
Started Jul 16 05:31:27 PM PDT 24
Finished Jul 16 05:31:30 PM PDT 24
Peak memory 213668 kb
Host smart-23087dac-d35f-4350-8bec-0a7635ba44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075433723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1075433723
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4213338619
Short name T282
Test name
Test status
Simulation time 728912732 ps
CPU time 7.95 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:28 PM PDT 24
Peak memory 274980 kb
Host smart-01fb0bd5-cfdf-4233-a2df-a12e96e3d34e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213338619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4213338619
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.649906386
Short name T401
Test name
Test status
Simulation time 6809747239 ps
CPU time 43.51 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:27:03 PM PDT 24
Peak memory 412212 kb
Host smart-8ed66348-6db7-43ae-b3ef-1335441e853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649906386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.649906386
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3662623647
Short name T328
Test name
Test status
Simulation time 1545232599 ps
CPU time 99.13 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:27:55 PM PDT 24
Peak memory 574084 kb
Host smart-4a4a7907-c81c-4f3e-ba02-9d41fd1f9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662623647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3662623647
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1873776880
Short name T1213
Test name
Test status
Simulation time 378144397 ps
CPU time 1.04 seconds
Started Jul 16 05:26:22 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 205264 kb
Host smart-0e2aeb07-c41f-4a7a-83b5-6bbf50bff5df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873776880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1873776880
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.4200152221
Short name T1716
Test name
Test status
Simulation time 166194028 ps
CPU time 3.57 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:22 PM PDT 24
Peak memory 205460 kb
Host smart-5a2ec6e1-d51d-468f-b26a-c5352f2ec339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200152221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.4200152221
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.891200716
Short name T1537
Test name
Test status
Simulation time 14962765531 ps
CPU time 108.79 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 1103200 kb
Host smart-c3884abf-5e50-4098-837f-e7f4bb9f4828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891200716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.891200716
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1372689807
Short name T626
Test name
Test status
Simulation time 3777039110 ps
CPU time 22.32 seconds
Started Jul 16 05:36:39 PM PDT 24
Finished Jul 16 05:37:03 PM PDT 24
Peak memory 205600 kb
Host smart-3c3eb4ac-c5a3-41fc-a238-dd5636f45717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372689807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1372689807
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.789302613
Short name T1683
Test name
Test status
Simulation time 333540475 ps
CPU time 0.65 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:20 PM PDT 24
Peak memory 204948 kb
Host smart-135ea3ad-d343-4d81-95f2-253bd712e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789302613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.789302613
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1916965312
Short name T1263
Test name
Test status
Simulation time 5520139304 ps
CPU time 46.02 seconds
Started Jul 16 05:26:20 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 523284 kb
Host smart-07810078-6375-4a74-ae42-cfc4556b6bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916965312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1916965312
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.485353083
Short name T19
Test name
Test status
Simulation time 25445175287 ps
CPU time 14.56 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:31:41 PM PDT 24
Peak memory 205484 kb
Host smart-24792f6e-438c-42de-bf2d-013ebd47af29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485353083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.485353083
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.34145088
Short name T513
Test name
Test status
Simulation time 1397180221 ps
CPU time 65.85 seconds
Started Jul 16 05:31:14 PM PDT 24
Finished Jul 16 05:32:20 PM PDT 24
Peak memory 367064 kb
Host smart-226f8e58-be24-4d0a-83b6-c324460b3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34145088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.34145088
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3315804881
Short name T1145
Test name
Test status
Simulation time 5033383950 ps
CPU time 47.55 seconds
Started Jul 16 05:31:27 PM PDT 24
Finished Jul 16 05:32:15 PM PDT 24
Peak memory 215068 kb
Host smart-a089813b-7390-4eea-b6c5-7ab8f07a7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315804881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3315804881
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3095726320
Short name T61
Test name
Test status
Simulation time 6393510566 ps
CPU time 7.53 seconds
Started Jul 16 05:26:22 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 213940 kb
Host smart-af136a2d-cba6-4cec-a1d1-61688a3d6246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095726320 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3095726320
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3489095363
Short name T1701
Test name
Test status
Simulation time 697853502 ps
CPU time 1.58 seconds
Started Jul 16 05:26:22 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 205628 kb
Host smart-a9b81359-c20a-4159-9909-4828bca7e5c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489095363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3489095363
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1101911498
Short name T1195
Test name
Test status
Simulation time 307072852 ps
CPU time 0.79 seconds
Started Jul 16 05:26:20 PM PDT 24
Finished Jul 16 05:26:22 PM PDT 24
Peak memory 205472 kb
Host smart-e95f53fb-d22b-4329-89e8-5f0f832abb29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101911498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1101911498
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.3176642664
Short name T460
Test name
Test status
Simulation time 697166783 ps
CPU time 3.69 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:24 PM PDT 24
Peak memory 205604 kb
Host smart-69590d11-57af-4626-8a32-013e359bdc3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176642664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.3176642664
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.4049979866
Short name T1541
Test name
Test status
Simulation time 272637247 ps
CPU time 1.53 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:22 PM PDT 24
Peak memory 205448 kb
Host smart-06900e6a-f5f1-491e-b5c5-d239c08a8e21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049979866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.4049979866
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2175612487
Short name T979
Test name
Test status
Simulation time 1451180742 ps
CPU time 2.43 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:17 PM PDT 24
Peak memory 213860 kb
Host smart-a43bf352-cdc5-4e08-8e74-bd23a15086e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175612487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2175612487
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.717279487
Short name T1691
Test name
Test status
Simulation time 1048388915 ps
CPU time 5.96 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 213808 kb
Host smart-14f0f15c-dd18-47a1-a3de-dda583db6a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717279487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.717279487
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.721346173
Short name T1237
Test name
Test status
Simulation time 18137250681 ps
CPU time 42.55 seconds
Started Jul 16 05:26:22 PM PDT 24
Finished Jul 16 05:27:05 PM PDT 24
Peak memory 771912 kb
Host smart-59027cf7-04a2-494c-ada8-9df026c65be3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721346173 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.721346173
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.2895573055
Short name T657
Test name
Test status
Simulation time 958120041 ps
CPU time 2.58 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:26 PM PDT 24
Peak memory 205604 kb
Host smart-4e01722b-e536-4138-81e4-e4bda81b57b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895573055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.2895573055
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.1301515610
Short name T949
Test name
Test status
Simulation time 729809582 ps
CPU time 4.75 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:24 PM PDT 24
Peak memory 218076 kb
Host smart-a7263d32-8c82-43d5-a11f-bdb07c94be59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301515610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.1301515610
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.980710756
Short name T1478
Test name
Test status
Simulation time 475920366 ps
CPU time 2.13 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 205328 kb
Host smart-c3633f90-6bab-453f-b4a4-df5f616ba681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980710756 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_smbus_maxlen.980710756
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3814082906
Short name T1261
Test name
Test status
Simulation time 1103270204 ps
CPU time 8.64 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:36 PM PDT 24
Peak memory 213836 kb
Host smart-873a6db5-2743-444c-8eaa-a9dce7680e15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814082906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3814082906
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.3291082511
Short name T689
Test name
Test status
Simulation time 16042129428 ps
CPU time 273.49 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:33:41 PM PDT 24
Peak memory 2086028 kb
Host smart-ed11c7f5-d5a5-4125-aa4b-71d898f3fb27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291082511 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.3291082511
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2508724806
Short name T464
Test name
Test status
Simulation time 5526924502 ps
CPU time 13.34 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:34 PM PDT 24
Peak memory 222008 kb
Host smart-4a192202-25bc-4bc2-87e8-8525c102397e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508724806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2508724806
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1968185206
Short name T876
Test name
Test status
Simulation time 44131661413 ps
CPU time 895.07 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:46:13 PM PDT 24
Peak memory 6054736 kb
Host smart-f309a97c-93bd-45a9-9fdc-9b17dcbd8698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968185206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1968185206
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3563689243
Short name T1040
Test name
Test status
Simulation time 7223557892 ps
CPU time 441.19 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:33:42 PM PDT 24
Peak memory 1759072 kb
Host smart-e46db164-0cc9-4940-b39c-fbcaf1ed17db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563689243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3563689243
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2905327471
Short name T629
Test name
Test status
Simulation time 1512526790 ps
CPU time 7.21 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:37 PM PDT 24
Peak memory 219060 kb
Host smart-e3031310-d04e-4d7a-b24f-b2dca35de9f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905327471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2905327471
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.4236271459
Short name T951
Test name
Test status
Simulation time 167333520 ps
CPU time 2.4 seconds
Started Jul 16 05:31:24 PM PDT 24
Finished Jul 16 05:31:27 PM PDT 24
Peak memory 205628 kb
Host smart-629bc5ed-a488-4225-8a72-1d43e1125035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236271459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.4236271459
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1527060934
Short name T607
Test name
Test status
Simulation time 28882656 ps
CPU time 0.68 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 204740 kb
Host smart-a723ecd8-1d50-41c9-acff-28b717b4a04a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527060934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1527060934
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.680198055
Short name T1107
Test name
Test status
Simulation time 317453896 ps
CPU time 2.98 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:31:29 PM PDT 24
Peak memory 232716 kb
Host smart-367d6e56-0c5a-4146-9610-9f62938f057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680198055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.680198055
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.968129003
Short name T1653
Test name
Test status
Simulation time 2500820939 ps
CPU time 8.43 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:30 PM PDT 24
Peak memory 299300 kb
Host smart-f7330246-a1e2-4d5a-b7de-0adc41da79e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968129003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.968129003
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3749108498
Short name T1347
Test name
Test status
Simulation time 3934192481 ps
CPU time 45.79 seconds
Started Jul 16 05:29:24 PM PDT 24
Finished Jul 16 05:30:10 PM PDT 24
Peak memory 373888 kb
Host smart-0e34fa01-0c68-4680-a03e-b624fb774a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749108498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3749108498
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2541555435
Short name T765
Test name
Test status
Simulation time 3034099138 ps
CPU time 66.21 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:27:25 PM PDT 24
Peak memory 675816 kb
Host smart-668ae37c-4d11-41ad-99b7-1e0b345a91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541555435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2541555435
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.4023541507
Short name T229
Test name
Test status
Simulation time 271497061 ps
CPU time 1.18 seconds
Started Jul 16 05:29:16 PM PDT 24
Finished Jul 16 05:29:18 PM PDT 24
Peak memory 205064 kb
Host smart-fbac2ca1-1c37-483a-8449-cc0d5cc4239c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023541507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.4023541507
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3891216480
Short name T1383
Test name
Test status
Simulation time 158212403 ps
CPU time 3.26 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 205484 kb
Host smart-5d60ce9c-ca15-4807-b26b-8a7c21811277
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891216480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3891216480
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2108327397
Short name T778
Test name
Test status
Simulation time 8908898316 ps
CPU time 128.2 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:28:32 PM PDT 24
Peak memory 1261888 kb
Host smart-40f86254-9860-43eb-8f8b-01cea0336850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108327397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2108327397
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2176118443
Short name T235
Test name
Test status
Simulation time 539736347 ps
CPU time 20.95 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:50 PM PDT 24
Peak memory 205508 kb
Host smart-deddcc31-d531-4318-9c9f-783979a8c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176118443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2176118443
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4220871423
Short name T252
Test name
Test status
Simulation time 280641255 ps
CPU time 1.11 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:16 PM PDT 24
Peak memory 213744 kb
Host smart-26070cbe-d9e8-4900-b2d3-efc644f6b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220871423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4220871423
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.905321451
Short name T446
Test name
Test status
Simulation time 45615091 ps
CPU time 0.74 seconds
Started Jul 16 05:31:27 PM PDT 24
Finished Jul 16 05:31:28 PM PDT 24
Peak memory 205044 kb
Host smart-8ad0958e-3614-47ee-a2b0-db0f329c8180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905321451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.905321451
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3730025227
Short name T538
Test name
Test status
Simulation time 3100581307 ps
CPU time 33.95 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:32:00 PM PDT 24
Peak memory 226776 kb
Host smart-da110d98-d1e2-47f7-a00e-096a45310815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730025227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3730025227
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.162119317
Short name T329
Test name
Test status
Simulation time 42653123 ps
CPU time 1.22 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:26 PM PDT 24
Peak memory 205972 kb
Host smart-cc30e711-e4fe-4433-8fd5-61d12d186f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162119317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.162119317
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3298183603
Short name T547
Test name
Test status
Simulation time 10064980264 ps
CPU time 35.88 seconds
Started Jul 16 05:29:25 PM PDT 24
Finished Jul 16 05:30:01 PM PDT 24
Peak memory 401976 kb
Host smart-776779a7-6a37-4e89-933e-3dc2cfccd610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298183603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3298183603
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1811253428
Short name T35
Test name
Test status
Simulation time 854106157 ps
CPU time 13.01 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:34 PM PDT 24
Peak memory 229260 kb
Host smart-54a44376-bc19-4258-80fb-5f48eecb1716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811253428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1811253428
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.487709017
Short name T1568
Test name
Test status
Simulation time 886509367 ps
CPU time 4.01 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:26:23 PM PDT 24
Peak memory 213808 kb
Host smart-2eb0283a-cf55-467f-a8e5-c914b16db19d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487709017 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.487709017
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.363189826
Short name T1201
Test name
Test status
Simulation time 123334858 ps
CPU time 0.89 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:26:20 PM PDT 24
Peak memory 205368 kb
Host smart-d0814663-a3ef-4007-a1e5-8c15c00626f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363189826 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.363189826
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.913089704
Short name T1348
Test name
Test status
Simulation time 304888858 ps
CPU time 0.89 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:30 PM PDT 24
Peak memory 205448 kb
Host smart-faa41d8e-63aa-4bd0-9cec-cfe4bd156c50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913089704 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.913089704
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3179894038
Short name T289
Test name
Test status
Simulation time 540307015 ps
CPU time 2.96 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 205628 kb
Host smart-0cab286f-75d7-4b7a-a7bc-3802a0c05ed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179894038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3179894038
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.481164292
Short name T1586
Test name
Test status
Simulation time 90628093 ps
CPU time 1.04 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 205376 kb
Host smart-db65dc89-fc86-4850-a1ba-36592081a6c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481164292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.481164292
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1166205129
Short name T1352
Test name
Test status
Simulation time 927450917 ps
CPU time 2.79 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 214128 kb
Host smart-9bfdb009-58b7-47c5-8232-0e72a89b7ef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166205129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1166205129
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1242304301
Short name T966
Test name
Test status
Simulation time 4386577957 ps
CPU time 6.6 seconds
Started Jul 16 05:26:20 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 213500 kb
Host smart-0bcbd2da-10cc-4c03-abdd-89c7603ea6c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242304301 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1242304301
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3678928739
Short name T1023
Test name
Test status
Simulation time 28496097408 ps
CPU time 292.59 seconds
Started Jul 16 05:31:27 PM PDT 24
Finished Jul 16 05:36:20 PM PDT 24
Peak memory 3172264 kb
Host smart-d3b415f8-fa87-4647-a0f7-22be0dcd4594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678928739 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3678928739
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2164667743
Short name T1593
Test name
Test status
Simulation time 841077889 ps
CPU time 3.15 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 213836 kb
Host smart-f1f12761-30df-427b-a22b-4c0d14f90ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164667743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2164667743
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.2230564685
Short name T1185
Test name
Test status
Simulation time 732884850 ps
CPU time 2.38 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:30 PM PDT 24
Peak memory 205812 kb
Host smart-230a19ef-b909-46c2-b9ad-28fc163ae34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230564685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.2230564685
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.1934118523
Short name T686
Test name
Test status
Simulation time 2273755587 ps
CPU time 4.23 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:26:24 PM PDT 24
Peak memory 221668 kb
Host smart-6b3e9ff1-3e89-44fb-aa14-769b9ed80623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934118523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.1934118523
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.3267390050
Short name T287
Test name
Test status
Simulation time 2728444787 ps
CPU time 2.15 seconds
Started Jul 16 05:26:26 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 205508 kb
Host smart-593bb1c5-019f-4952-b0c8-e8abccddd2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267390050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.3267390050
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3339247397
Short name T478
Test name
Test status
Simulation time 16040340928 ps
CPU time 37.8 seconds
Started Jul 16 05:29:15 PM PDT 24
Finished Jul 16 05:29:54 PM PDT 24
Peak memory 213692 kb
Host smart-483a0c39-db4f-42d8-b274-7e9322e94440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339247397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3339247397
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.913520729
Short name T1048
Test name
Test status
Simulation time 32485918146 ps
CPU time 871.83 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:45:51 PM PDT 24
Peak memory 5505804 kb
Host smart-063a1397-6ce8-473d-b669-839ac9eb87c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913520729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_stress_all.913520729
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.441064962
Short name T1658
Test name
Test status
Simulation time 7988891333 ps
CPU time 28.11 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:26:50 PM PDT 24
Peak memory 213904 kb
Host smart-53971617-e293-4a8e-91b9-046f04e5bebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441064962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.441064962
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3083625860
Short name T432
Test name
Test status
Simulation time 23799380229 ps
CPU time 66.98 seconds
Started Jul 16 05:26:21 PM PDT 24
Finished Jul 16 05:27:29 PM PDT 24
Peak memory 956476 kb
Host smart-a16a0deb-baaa-4a88-bc16-9ba88e17e295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083625860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3083625860
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2677788981
Short name T555
Test name
Test status
Simulation time 2309218594 ps
CPU time 111.09 seconds
Started Jul 16 05:31:14 PM PDT 24
Finished Jul 16 05:33:06 PM PDT 24
Peak memory 729340 kb
Host smart-7e21081e-b2a7-4316-82dd-3f851ee727f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677788981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2677788981
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2135920323
Short name T1663
Test name
Test status
Simulation time 15731843306 ps
CPU time 6.19 seconds
Started Jul 16 05:31:14 PM PDT 24
Finished Jul 16 05:31:20 PM PDT 24
Peak memory 222084 kb
Host smart-0d4ae013-6f78-4f1f-9839-239911018948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135920323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2135920323
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.1029407371
Short name T677
Test name
Test status
Simulation time 254246572 ps
CPU time 3.66 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 205368 kb
Host smart-44b0b9b6-e6ae-4fc6-9170-6adb8b34cf41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029407371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.1029407371
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1964169494
Short name T630
Test name
Test status
Simulation time 21091774 ps
CPU time 0.63 seconds
Started Jul 16 05:26:26 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 204500 kb
Host smart-b636edc2-e70b-49e5-ab0a-e3621f310a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964169494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1964169494
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1081351680
Short name T509
Test name
Test status
Simulation time 96132311 ps
CPU time 1.48 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 221884 kb
Host smart-4ba8f1eb-938a-44c8-bb9e-152799b0a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081351680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1081351680
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.911864612
Short name T434
Test name
Test status
Simulation time 423485518 ps
CPU time 19.93 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 258368 kb
Host smart-c7f257f1-496a-4ef6-9267-95d16fa611bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911864612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.911864612
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1879345093
Short name T1619
Test name
Test status
Simulation time 12984822783 ps
CPU time 93.77 seconds
Started Jul 16 05:29:15 PM PDT 24
Finished Jul 16 05:30:50 PM PDT 24
Peak memory 677308 kb
Host smart-abaa612f-9147-449c-8b35-ea248bfb3ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879345093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1879345093
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3031430393
Short name T721
Test name
Test status
Simulation time 17946085849 ps
CPU time 189.13 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:37:15 PM PDT 24
Peak memory 767784 kb
Host smart-f68bf64e-e3b9-4a3b-ab6f-0e0aa27b34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031430393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3031430393
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.595855202
Short name T1260
Test name
Test status
Simulation time 87068690 ps
CPU time 0.89 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:31 PM PDT 24
Peak memory 205220 kb
Host smart-a8c6c7ca-276f-468f-95cd-fe3bff9c0201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595855202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.595855202
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.263356422
Short name T413
Test name
Test status
Simulation time 177927423 ps
CPU time 9.1 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 205492 kb
Host smart-f2dde5b3-ed22-4d9d-a892-03ac652bbfe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263356422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
263356422
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1294330926
Short name T108
Test name
Test status
Simulation time 10373633206 ps
CPU time 135.1 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:28:42 PM PDT 24
Peak memory 1504648 kb
Host smart-26b8e067-5632-4dca-ba97-c39d094de23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294330926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1294330926
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2790919263
Short name T1286
Test name
Test status
Simulation time 255656596 ps
CPU time 3.2 seconds
Started Jul 16 05:29:16 PM PDT 24
Finished Jul 16 05:29:20 PM PDT 24
Peak memory 205328 kb
Host smart-3733d7fe-f41f-420f-ba5e-474a247eeeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790919263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2790919263
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.1905002560
Short name T128
Test name
Test status
Simulation time 31315517 ps
CPU time 0.71 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 205208 kb
Host smart-06ff0221-625a-4467-9881-0b1001986b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905002560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1905002560
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2242058227
Short name T1097
Test name
Test status
Simulation time 52974914009 ps
CPU time 362.93 seconds
Started Jul 16 05:26:25 PM PDT 24
Finished Jul 16 05:32:29 PM PDT 24
Peak memory 1346584 kb
Host smart-f9518375-05f9-42d4-ba8e-d77dd144befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242058227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2242058227
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.3459596227
Short name T588
Test name
Test status
Simulation time 236504951 ps
CPU time 2.22 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:41 PM PDT 24
Peak memory 227236 kb
Host smart-bc867fe3-1722-4319-8ca9-46104b166be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459596227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3459596227
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.910601678
Short name T915
Test name
Test status
Simulation time 6319019300 ps
CPU time 27.78 seconds
Started Jul 16 05:26:26 PM PDT 24
Finished Jul 16 05:26:55 PM PDT 24
Peak memory 417332 kb
Host smart-b6cf053d-7a80-4238-aaa0-49a71e5348c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910601678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.910601678
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2472671351
Short name T1528
Test name
Test status
Simulation time 20994414884 ps
CPU time 1529.61 seconds
Started Jul 16 05:26:32 PM PDT 24
Finished Jul 16 05:52:03 PM PDT 24
Peak memory 2394564 kb
Host smart-d10fc22f-9c36-4428-91cd-e953abd5c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472671351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2472671351
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.404337784
Short name T1706
Test name
Test status
Simulation time 3094960180 ps
CPU time 15.19 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:31:33 PM PDT 24
Peak memory 217092 kb
Host smart-992d8ba7-0e6f-4031-b05b-dbc589e8e8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404337784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.404337784
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4227822252
Short name T560
Test name
Test status
Simulation time 2496813305 ps
CPU time 4.77 seconds
Started Jul 16 05:26:28 PM PDT 24
Finished Jul 16 05:26:34 PM PDT 24
Peak memory 217664 kb
Host smart-e704dec5-da58-4b4a-9440-311036d14178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227822252 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4227822252
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.597885332
Short name T1643
Test name
Test status
Simulation time 584964294 ps
CPU time 1.32 seconds
Started Jul 16 05:29:25 PM PDT 24
Finished Jul 16 05:29:27 PM PDT 24
Peak memory 205588 kb
Host smart-b560295c-edf4-4ae1-b747-919501bf87c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597885332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.597885332
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.5692151
Short name T1484
Test name
Test status
Simulation time 452794971 ps
CPU time 1.12 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:26 PM PDT 24
Peak memory 205544 kb
Host smart-b49e80a2-5a32-4c9a-ba7f-49b9738f6eb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5692151 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_fifo_reset_tx.5692151
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.2480469527
Short name T1188
Test name
Test status
Simulation time 1448766945 ps
CPU time 2.06 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:40 PM PDT 24
Peak memory 205648 kb
Host smart-81efd2bd-1e23-46bb-8b47-7e9aa9cf077d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480469527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.2480469527
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.2982933562
Short name T1051
Test name
Test status
Simulation time 186922448 ps
CPU time 1.04 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:07 PM PDT 24
Peak memory 205368 kb
Host smart-37f3d148-490a-459c-bd35-01a815274e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982933562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.2982933562
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2058992430
Short name T126
Test name
Test status
Simulation time 2059466097 ps
CPU time 5.19 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:26:35 PM PDT 24
Peak memory 214104 kb
Host smart-5d147c07-c21b-42e0-80bc-ca9ea852d2e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058992430 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2058992430
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.3392025049
Short name T1114
Test name
Test status
Simulation time 3132131625 ps
CPU time 23.29 seconds
Started Jul 16 05:29:23 PM PDT 24
Finished Jul 16 05:29:47 PM PDT 24
Peak memory 912560 kb
Host smart-4389bf66-fc8c-43f3-844f-f9ec0fd07045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392025049 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3392025049
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.3934018873
Short name T462
Test name
Test status
Simulation time 5617766040 ps
CPU time 2.5 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:25 PM PDT 24
Peak memory 213856 kb
Host smart-5e448f4f-9ca2-442f-84b3-12d66ee1eaac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934018873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.3934018873
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.3432745048
Short name T1300
Test name
Test status
Simulation time 1679754312 ps
CPU time 2.16 seconds
Started Jul 16 05:26:26 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 205588 kb
Host smart-431ff0dc-0b9e-4bb5-96f3-16f0a4787c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432745048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.3432745048
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_txstretch.1344330647
Short name T1020
Test name
Test status
Simulation time 150059297 ps
CPU time 1.42 seconds
Started Jul 16 05:26:31 PM PDT 24
Finished Jul 16 05:26:33 PM PDT 24
Peak memory 222172 kb
Host smart-34621e7c-f1f7-4ca0-b8be-c1cb376944c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344330647 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_nack_txstretch.1344330647
Directory /workspace/34.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/34.i2c_target_perf.1524842820
Short name T1454
Test name
Test status
Simulation time 2449767820 ps
CPU time 4.26 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:31:30 PM PDT 24
Peak memory 222028 kb
Host smart-1f0c1003-c3b5-4dc9-b439-8840367c9955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524842820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.1524842820
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.3211214969
Short name T1053
Test name
Test status
Simulation time 2331143831 ps
CPU time 2.65 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:09 PM PDT 24
Peak memory 205140 kb
Host smart-9c696737-4af0-4ea0-97a3-928bc08095ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211214969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.3211214969
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3080945544
Short name T839
Test name
Test status
Simulation time 842935164 ps
CPU time 11.43 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 213816 kb
Host smart-1d586999-1e5b-4130-909b-1df93a2d8665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080945544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3080945544
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2032074490
Short name T1131
Test name
Test status
Simulation time 2168679071 ps
CPU time 8.02 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:46 PM PDT 24
Peak memory 218076 kb
Host smart-e9989f97-f279-4c39-bc2e-c16f1e6ab5ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032074490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2032074490
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2187125848
Short name T565
Test name
Test status
Simulation time 8060692062 ps
CPU time 4.88 seconds
Started Jul 16 05:34:14 PM PDT 24
Finished Jul 16 05:34:19 PM PDT 24
Peak memory 205524 kb
Host smart-fef781ca-6d18-408a-985d-29e00d7d6aae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187125848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2187125848
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.417265102
Short name T1021
Test name
Test status
Simulation time 196442637 ps
CPU time 1.22 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:08 PM PDT 24
Peak memory 205332 kb
Host smart-77aef17d-ccc6-43bf-94ab-9055d83c1acc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417265102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.417265102
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3924202776
Short name T586
Test name
Test status
Simulation time 5023282631 ps
CPU time 6.89 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 222268 kb
Host smart-22ede2e6-c16b-41b2-bbb4-f71633e9c6f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924202776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3924202776
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.2017421087
Short name T723
Test name
Test status
Simulation time 118567730 ps
CPU time 2.55 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:09 PM PDT 24
Peak memory 205416 kb
Host smart-962553b4-a603-480f-a0e5-b70178b90a46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017421087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.2017421087
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.661278177
Short name T1123
Test name
Test status
Simulation time 24978742 ps
CPU time 0.65 seconds
Started Jul 16 05:26:46 PM PDT 24
Finished Jul 16 05:26:47 PM PDT 24
Peak memory 204700 kb
Host smart-5e4cc00e-8eb1-422a-a6b0-867923e23da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661278177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.661278177
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.692909034
Short name T495
Test name
Test status
Simulation time 409354576 ps
CPU time 3.11 seconds
Started Jul 16 05:26:48 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 213768 kb
Host smart-4c1316bb-dc27-4cb2-9616-efc0ccdfce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692909034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.692909034
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2788794332
Short name T1290
Test name
Test status
Simulation time 318578912 ps
CPU time 5.5 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 269212 kb
Host smart-05834652-6d61-41ac-83c5-9b410bef235c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788794332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2788794332
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1175669802
Short name T1646
Test name
Test status
Simulation time 5279650736 ps
CPU time 78.72 seconds
Started Jul 16 05:26:36 PM PDT 24
Finished Jul 16 05:27:55 PM PDT 24
Peak memory 550824 kb
Host smart-1449052c-d7d7-4215-8316-de44643d71d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175669802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1175669802
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3311879127
Short name T907
Test name
Test status
Simulation time 38906857270 ps
CPU time 145.64 seconds
Started Jul 16 05:26:27 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 692572 kb
Host smart-98d175f7-4402-4b26-bff2-29f85b375006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311879127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3311879127
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2235589839
Short name T458
Test name
Test status
Simulation time 590434655 ps
CPU time 1.02 seconds
Started Jul 16 05:32:07 PM PDT 24
Finished Jul 16 05:32:09 PM PDT 24
Peak memory 205264 kb
Host smart-1be10c49-355d-423d-9f45-63210fe9dd1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235589839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2235589839
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.4267034054
Short name T350
Test name
Test status
Simulation time 502550233 ps
CPU time 5.82 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:12 PM PDT 24
Peak memory 243584 kb
Host smart-36812dda-8194-4f38-9dc0-b7686ae1f391
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267034054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.4267034054
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2388317277
Short name T103
Test name
Test status
Simulation time 10823191684 ps
CPU time 125.19 seconds
Started Jul 16 05:26:29 PM PDT 24
Finished Jul 16 05:28:35 PM PDT 24
Peak memory 1376292 kb
Host smart-effc018c-3dbd-492a-a5c5-ef22daa627b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388317277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2388317277
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3269331003
Short name T1583
Test name
Test status
Simulation time 572017061 ps
CPU time 5.77 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 205488 kb
Host smart-ad001b7c-70d9-46ec-8d0d-889cd6cde0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269331003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3269331003
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.825080521
Short name T346
Test name
Test status
Simulation time 59027065 ps
CPU time 0.72 seconds
Started Jul 16 05:32:14 PM PDT 24
Finished Jul 16 05:32:16 PM PDT 24
Peak memory 205216 kb
Host smart-f32c7a1e-5363-448b-a11d-c213f13857e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825080521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.825080521
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3383839636
Short name T1403
Test name
Test status
Simulation time 5628372686 ps
CPU time 41.4 seconds
Started Jul 16 05:34:05 PM PDT 24
Finished Jul 16 05:34:47 PM PDT 24
Peak memory 214396 kb
Host smart-aa76332e-56c6-4ec7-a9a9-00d2a731be67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383839636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3383839636
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.65126175
Short name T1700
Test name
Test status
Simulation time 40496554 ps
CPU time 1.79 seconds
Started Jul 16 05:34:14 PM PDT 24
Finished Jul 16 05:34:17 PM PDT 24
Peak memory 206108 kb
Host smart-a7de2c0f-6243-45e5-a68d-bd793ba11bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65126175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.65126175
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.988134815
Short name T520
Test name
Test status
Simulation time 5691645111 ps
CPU time 63.66 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:32:21 PM PDT 24
Peak memory 298388 kb
Host smart-65755806-b776-4776-acf0-339d27ac33cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988134815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.988134815
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3716593908
Short name T914
Test name
Test status
Simulation time 1561218825 ps
CPU time 12.37 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:32 PM PDT 24
Peak memory 221168 kb
Host smart-f7efaa91-1a17-42e1-ad80-11be4d53ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716593908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3716593908
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1133345951
Short name T610
Test name
Test status
Simulation time 2773411563 ps
CPU time 3.53 seconds
Started Jul 16 05:26:42 PM PDT 24
Finished Jul 16 05:26:46 PM PDT 24
Peak memory 214008 kb
Host smart-2747aead-bb7f-487b-a5b3-25466c7b7e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133345951 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1133345951
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1329666085
Short name T508
Test name
Test status
Simulation time 95714169 ps
CPU time 0.96 seconds
Started Jul 16 05:33:23 PM PDT 24
Finished Jul 16 05:33:25 PM PDT 24
Peak memory 205488 kb
Host smart-1ecc841f-55fd-4bc0-8b69-df57656e7d34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329666085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1329666085
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.768881720
Short name T1008
Test name
Test status
Simulation time 639496403 ps
CPU time 1.29 seconds
Started Jul 16 05:26:43 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 205624 kb
Host smart-1b1014ca-14df-43d8-b05e-821378d26e87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768881720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.768881720
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.167432820
Short name T1289
Test name
Test status
Simulation time 1374333482 ps
CPU time 1.89 seconds
Started Jul 16 05:26:36 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 205372 kb
Host smart-2cb6a0be-f457-4df1-9aed-4c737da01b78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167432820 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.167432820
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2816282560
Short name T947
Test name
Test status
Simulation time 636044359 ps
CPU time 1.11 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:26:56 PM PDT 24
Peak memory 205372 kb
Host smart-46c85a61-d33f-43f0-af62-6882a6a5cf34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816282560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2816282560
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1957518115
Short name T467
Test name
Test status
Simulation time 277496906 ps
CPU time 1.84 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:26:57 PM PDT 24
Peak memory 205196 kb
Host smart-987a54e9-84f8-440c-9df9-2a5ee8c85713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957518115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1957518115
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.999210608
Short name T1183
Test name
Test status
Simulation time 20540393147 ps
CPU time 7.17 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:27:03 PM PDT 24
Peak memory 215212 kb
Host smart-25205161-ba1b-4d50-a6c2-366c9d93dfeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999210608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.999210608
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.214243339
Short name T853
Test name
Test status
Simulation time 10917456706 ps
CPU time 9.19 seconds
Started Jul 16 05:27:26 PM PDT 24
Finished Jul 16 05:27:36 PM PDT 24
Peak memory 257016 kb
Host smart-2e256f62-1d6a-46d1-abb7-28131c5bd22b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214243339 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.214243339
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.1401401778
Short name T888
Test name
Test status
Simulation time 590553584 ps
CPU time 2.91 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:42 PM PDT 24
Peak memory 213832 kb
Host smart-64443327-0999-4a16-b7df-0ea89ffdbc89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401401778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.1401401778
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.4049016435
Short name T993
Test name
Test status
Simulation time 1644477997 ps
CPU time 2.35 seconds
Started Jul 16 05:26:44 PM PDT 24
Finished Jul 16 05:26:47 PM PDT 24
Peak memory 205484 kb
Host smart-1829b001-49d0-44d8-b38a-55d8c2d0a470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049016435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.4049016435
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1267322946
Short name T945
Test name
Test status
Simulation time 483891049 ps
CPU time 3.56 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:43 PM PDT 24
Peak memory 213868 kb
Host smart-31ac4954-964f-4a1b-8f05-8d3ceda966e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267322946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1267322946
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.2326390703
Short name T1307
Test name
Test status
Simulation time 1079293440 ps
CPU time 2.57 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:40 PM PDT 24
Peak memory 205476 kb
Host smart-0821a41a-eb97-427f-9e82-7b5eac3d67ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326390703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.2326390703
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1747526863
Short name T1
Test name
Test status
Simulation time 4312874282 ps
CPU time 10.69 seconds
Started Jul 16 05:26:43 PM PDT 24
Finished Jul 16 05:26:54 PM PDT 24
Peak memory 213868 kb
Host smart-8854e87e-f483-44c6-95de-7187d49be4ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747526863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1747526863
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.739869283
Short name T889
Test name
Test status
Simulation time 34655053997 ps
CPU time 68.81 seconds
Started Jul 16 05:26:54 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 799008 kb
Host smart-9fc219b6-3c99-4ee7-b697-a2c063e79622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739869283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_target_stress_all.739869283
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1181195266
Short name T1602
Test name
Test status
Simulation time 807533966 ps
CPU time 13.92 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:53 PM PDT 24
Peak memory 210444 kb
Host smart-dfe4331c-fda0-4eb6-bc5f-dbeb2f644be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181195266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1181195266
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.188324054
Short name T720
Test name
Test status
Simulation time 31261778829 ps
CPU time 102.43 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:28:38 PM PDT 24
Peak memory 1667560 kb
Host smart-a7ef825c-987c-4e4a-b686-b73456b171bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188324054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.188324054
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3094243330
Short name T813
Test name
Test status
Simulation time 4988278075 ps
CPU time 124.44 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:33:25 PM PDT 24
Peak memory 1371964 kb
Host smart-3ac312f1-f081-4e11-b0a4-68802f621792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094243330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3094243330
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3049077278
Short name T1253
Test name
Test status
Simulation time 2400488041 ps
CPU time 6.63 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 221964 kb
Host smart-d5afe2d3-1bbd-436a-8706-f676e3811c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049077278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3049077278
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.350443445
Short name T332
Test name
Test status
Simulation time 68212129 ps
CPU time 1.63 seconds
Started Jul 16 05:26:43 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 205616 kb
Host smart-8447651c-da79-4000-9708-57cab7f7aaa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350443445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.350443445
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3610241029
Short name T1546
Test name
Test status
Simulation time 16814367 ps
CPU time 0.61 seconds
Started Jul 16 05:26:52 PM PDT 24
Finished Jul 16 05:26:53 PM PDT 24
Peak memory 204768 kb
Host smart-d8c13cb8-5ed5-48b9-b22b-5e79b7a9cc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610241029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3610241029
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1729713131
Short name T987
Test name
Test status
Simulation time 3022723861 ps
CPU time 7.6 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:47 PM PDT 24
Peak memory 213844 kb
Host smart-bc0bfd98-1db7-4692-910d-a39a5106bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729713131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1729713131
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3989702292
Short name T779
Test name
Test status
Simulation time 705483977 ps
CPU time 5.87 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 253876 kb
Host smart-59add3ab-01bb-4ff1-82b2-0595e0b8a7dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989702292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3989702292
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.249402633
Short name T1564
Test name
Test status
Simulation time 12227918874 ps
CPU time 167.8 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:29:43 PM PDT 24
Peak memory 429580 kb
Host smart-42cd0fe9-7d39-4763-a788-de24b7e225e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249402633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.249402633
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1246397586
Short name T1689
Test name
Test status
Simulation time 6833314599 ps
CPU time 49.75 seconds
Started Jul 16 05:27:13 PM PDT 24
Finished Jul 16 05:28:03 PM PDT 24
Peak memory 582424 kb
Host smart-ffd4fbc1-f434-4267-9e50-2db96628043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246397586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1246397586
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.110750268
Short name T1488
Test name
Test status
Simulation time 633498699 ps
CPU time 1.09 seconds
Started Jul 16 05:26:43 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 205176 kb
Host smart-9f263b5b-66b4-46eb-b245-5e533e16e362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110750268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.110750268
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2481108754
Short name T829
Test name
Test status
Simulation time 129563838 ps
CPU time 3.63 seconds
Started Jul 16 05:26:47 PM PDT 24
Finished Jul 16 05:26:51 PM PDT 24
Peak memory 223524 kb
Host smart-57b08dfa-b85b-49f9-bd5e-76b8d574d850
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481108754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2481108754
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2311703834
Short name T158
Test name
Test status
Simulation time 5003001970 ps
CPU time 158.84 seconds
Started Jul 16 05:29:24 PM PDT 24
Finished Jul 16 05:32:04 PM PDT 24
Peak memory 1458484 kb
Host smart-f5799040-2042-4157-89c1-d4f77f7b1957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311703834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2311703834
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.4211676012
Short name T238
Test name
Test status
Simulation time 1486381417 ps
CPU time 5.32 seconds
Started Jul 16 05:31:43 PM PDT 24
Finished Jul 16 05:31:48 PM PDT 24
Peak memory 205464 kb
Host smart-6488f610-62c1-4e5e-9f7c-5d78aab1f366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211676012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.4211676012
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.179571010
Short name T1160
Test name
Test status
Simulation time 110066342 ps
CPU time 1.63 seconds
Started Jul 16 05:26:50 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 213676 kb
Host smart-a30c6121-d4ad-4cae-8106-95fb035ba97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179571010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.179571010
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.490668456
Short name T135
Test name
Test status
Simulation time 51124747 ps
CPU time 0.68 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:40 PM PDT 24
Peak memory 205188 kb
Host smart-b6d5ac29-8334-401a-ac0e-dc7beab5ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490668456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.490668456
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.515671973
Short name T357
Test name
Test status
Simulation time 4849851109 ps
CPU time 153.94 seconds
Started Jul 16 05:26:42 PM PDT 24
Finished Jul 16 05:29:17 PM PDT 24
Peak memory 1259452 kb
Host smart-697c431f-0f2a-40bc-9950-c22595b022ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515671973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.515671973
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.1665181335
Short name T549
Test name
Test status
Simulation time 94280990 ps
CPU time 1.58 seconds
Started Jul 16 05:26:50 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 213500 kb
Host smart-3bd1d784-9fb6-4960-80ed-81331cf8fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665181335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1665181335
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.706797372
Short name T1171
Test name
Test status
Simulation time 1505738892 ps
CPU time 69.53 seconds
Started Jul 16 05:26:42 PM PDT 24
Finished Jul 16 05:27:52 PM PDT 24
Peak memory 359580 kb
Host smart-1dedf5ed-b4e4-4f5a-8f2b-e2f0dbd94b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706797372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.706797372
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1447679160
Short name T453
Test name
Test status
Simulation time 18392519140 ps
CPU time 638.61 seconds
Started Jul 16 05:27:13 PM PDT 24
Finished Jul 16 05:37:52 PM PDT 24
Peak memory 1199928 kb
Host smart-d8c29c3a-9cc1-417f-b30f-07bd73a159ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447679160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1447679160
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.4241087308
Short name T270
Test name
Test status
Simulation time 2485979941 ps
CPU time 27.42 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:27:05 PM PDT 24
Peak memory 213804 kb
Host smart-1c339a32-718d-4b34-bb0e-11229a89d5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241087308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.4241087308
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2530760905
Short name T1042
Test name
Test status
Simulation time 2543938836 ps
CPU time 4.13 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:43 PM PDT 24
Peak memory 213900 kb
Host smart-387bef3c-124d-4bc1-a0fb-ccad77cc3074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530760905 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2530760905
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1916103983
Short name T780
Test name
Test status
Simulation time 692793402 ps
CPU time 1.2 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:26:57 PM PDT 24
Peak memory 205348 kb
Host smart-446b072b-fdf9-4bf5-9a7e-29e8f707cbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916103983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1916103983
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1051292177
Short name T378
Test name
Test status
Simulation time 329258502 ps
CPU time 0.77 seconds
Started Jul 16 05:26:55 PM PDT 24
Finished Jul 16 05:26:56 PM PDT 24
Peak memory 205072 kb
Host smart-13da2e37-c668-4ade-9d91-d900aac97cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051292177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1051292177
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.3432546257
Short name T1027
Test name
Test status
Simulation time 1071855140 ps
CPU time 2.97 seconds
Started Jul 16 05:33:54 PM PDT 24
Finished Jul 16 05:33:58 PM PDT 24
Peak memory 205572 kb
Host smart-dbeb3a18-1d90-4a63-a9c3-e7cc0952ab07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432546257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3432546257
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.1801212266
Short name T311
Test name
Test status
Simulation time 109501112 ps
CPU time 1.05 seconds
Started Jul 16 05:27:28 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 205332 kb
Host smart-ee8d1322-7eab-4253-ae2b-1c53c0e3e3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801212266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1801212266
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3939697872
Short name T1446
Test name
Test status
Simulation time 313152441 ps
CPU time 1.45 seconds
Started Jul 16 05:26:47 PM PDT 24
Finished Jul 16 05:26:49 PM PDT 24
Peak memory 213752 kb
Host smart-6dd0d162-0c6d-4a81-88db-1ef0661cf060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939697872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3939697872
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2452574001
Short name T1035
Test name
Test status
Simulation time 1263393361 ps
CPU time 5.94 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:31:32 PM PDT 24
Peak memory 213608 kb
Host smart-d61264bb-b95b-46eb-9f04-a9cb97bf62b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452574001 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2452574001
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3620913807
Short name T319
Test name
Test status
Simulation time 3449304041 ps
CPU time 7.84 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:48 PM PDT 24
Peak memory 205644 kb
Host smart-0249493e-5a74-43ac-a260-d15ec06184b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620913807 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3620913807
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.3559538072
Short name T841
Test name
Test status
Simulation time 851643915 ps
CPU time 2.49 seconds
Started Jul 16 05:26:50 PM PDT 24
Finished Jul 16 05:26:53 PM PDT 24
Peak memory 213828 kb
Host smart-5c37c40b-83dc-4163-adb1-47327cc8fe87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559538072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.3559538072
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.65728209
Short name T1314
Test name
Test status
Simulation time 525177266 ps
CPU time 2.6 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 205592 kb
Host smart-87f22452-e45d-4dfc-93d4-f15d800607fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65728209 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_acqfull_addr.65728209
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.649725518
Short name T1545
Test name
Test status
Simulation time 3321198291 ps
CPU time 5.91 seconds
Started Jul 16 05:26:38 PM PDT 24
Finished Jul 16 05:26:45 PM PDT 24
Peak memory 218064 kb
Host smart-1db06836-5cfb-4059-854c-1fb069ec5f17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649725518 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_perf.649725518
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.4027729925
Short name T276
Test name
Test status
Simulation time 417445699 ps
CPU time 2.06 seconds
Started Jul 16 05:31:16 PM PDT 24
Finished Jul 16 05:31:19 PM PDT 24
Peak memory 205404 kb
Host smart-6deb54a6-f5ef-4b43-80f6-bfe69bb1941f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027729925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.4027729925
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2939444067
Short name T844
Test name
Test status
Simulation time 1395917274 ps
CPU time 42.26 seconds
Started Jul 16 05:26:37 PM PDT 24
Finished Jul 16 05:27:19 PM PDT 24
Peak memory 213752 kb
Host smart-4c4c6f7f-f7e1-4852-9f08-fe0ccda92f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939444067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2939444067
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3111276469
Short name T1443
Test name
Test status
Simulation time 35287741239 ps
CPU time 43.77 seconds
Started Jul 16 05:26:49 PM PDT 24
Finished Jul 16 05:27:33 PM PDT 24
Peak memory 286676 kb
Host smart-63ff4d24-138e-4463-8557-b409e3d1394b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111276469 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3111276469
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3330831486
Short name T110
Test name
Test status
Simulation time 36053704436 ps
CPU time 425.83 seconds
Started Jul 16 05:29:25 PM PDT 24
Finished Jul 16 05:36:32 PM PDT 24
Peak memory 3998208 kb
Host smart-b888cb13-8bb9-4c4e-9b3a-fd42f762ba4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330831486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3330831486
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2156702943
Short name T733
Test name
Test status
Simulation time 3260349689 ps
CPU time 4.76 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:24 PM PDT 24
Peak memory 333656 kb
Host smart-f28b5044-9e70-4d36-87a4-54e6f0f64201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156702943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2156702943
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3937002932
Short name T1271
Test name
Test status
Simulation time 1336438711 ps
CPU time 6.98 seconds
Started Jul 16 05:33:31 PM PDT 24
Finished Jul 16 05:33:39 PM PDT 24
Peak memory 222020 kb
Host smart-228df3b2-ba1f-4ec7-951e-d5070ec2df23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937002932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3937002932
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.3480686725
Short name T605
Test name
Test status
Simulation time 1006447317 ps
CPU time 12.35 seconds
Started Jul 16 05:26:49 PM PDT 24
Finished Jul 16 05:27:02 PM PDT 24
Peak memory 205632 kb
Host smart-0f940ce9-ed01-42fb-83c5-ef450a404d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480686725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.3480686725
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2813138444
Short name T1072
Test name
Test status
Simulation time 37937603 ps
CPU time 0.7 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 204908 kb
Host smart-dad3a79f-3939-49a1-bb4a-a7c7857b264b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813138444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2813138444
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4191828427
Short name T1190
Test name
Test status
Simulation time 681451912 ps
CPU time 6.25 seconds
Started Jul 16 05:27:04 PM PDT 24
Finished Jul 16 05:27:10 PM PDT 24
Peak memory 229896 kb
Host smart-c6dc8d2f-1759-4ebc-9659-ec71a024018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191828427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4191828427
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3079989067
Short name T296
Test name
Test status
Simulation time 789351989 ps
CPU time 16.23 seconds
Started Jul 16 05:26:52 PM PDT 24
Finished Jul 16 05:27:08 PM PDT 24
Peak memory 268972 kb
Host smart-c4ce1d8a-4149-4313-acd1-777a6ea61806
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079989067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3079989067
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.230014671
Short name T379
Test name
Test status
Simulation time 18512994008 ps
CPU time 81.78 seconds
Started Jul 16 05:30:51 PM PDT 24
Finished Jul 16 05:32:13 PM PDT 24
Peak memory 528892 kb
Host smart-9cd1747b-f7df-4169-ba82-71e0db1beea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230014671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.230014671
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2458985227
Short name T1272
Test name
Test status
Simulation time 8909047406 ps
CPU time 133.15 seconds
Started Jul 16 05:34:22 PM PDT 24
Finished Jul 16 05:36:35 PM PDT 24
Peak memory 627280 kb
Host smart-275c9fac-680e-427f-ad05-7520324ca4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458985227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2458985227
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1775419198
Short name T1452
Test name
Test status
Simulation time 142994454 ps
CPU time 1.17 seconds
Started Jul 16 05:34:14 PM PDT 24
Finished Jul 16 05:34:16 PM PDT 24
Peak memory 205428 kb
Host smart-082ed8ce-0f91-400d-a800-38ae1f1d4fe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775419198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1775419198
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3673884776
Short name T1470
Test name
Test status
Simulation time 1561495926 ps
CPU time 4.64 seconds
Started Jul 16 05:31:30 PM PDT 24
Finished Jul 16 05:31:36 PM PDT 24
Peak memory 205480 kb
Host smart-f67a9fc2-634b-4ba6-ac77-c0e3e2c57c31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673884776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3673884776
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.975369657
Short name T1434
Test name
Test status
Simulation time 2605652148 ps
CPU time 144.9 seconds
Started Jul 16 05:26:50 PM PDT 24
Finished Jul 16 05:29:15 PM PDT 24
Peak memory 768148 kb
Host smart-b4368918-a026-4663-a763-6205eae5a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975369657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.975369657
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1190859391
Short name T239
Test name
Test status
Simulation time 1377564390 ps
CPU time 8.37 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:44 PM PDT 24
Peak memory 205448 kb
Host smart-c01e713e-510c-485f-a6e6-5c95f688d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190859391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1190859391
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_override.555413578
Short name T134
Test name
Test status
Simulation time 70247940 ps
CPU time 0.72 seconds
Started Jul 16 05:26:51 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 205224 kb
Host smart-4a9ca58d-7595-411e-99c1-bbabcf1f906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555413578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.555413578
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3867878230
Short name T217
Test name
Test status
Simulation time 28842746196 ps
CPU time 149.39 seconds
Started Jul 16 05:27:01 PM PDT 24
Finished Jul 16 05:29:31 PM PDT 24
Peak memory 292260 kb
Host smart-a8a0e5e8-bf83-429b-b7cc-9601d4d452f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867878230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3867878230
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.2122368650
Short name T599
Test name
Test status
Simulation time 142937322 ps
CPU time 1.16 seconds
Started Jul 16 05:36:21 PM PDT 24
Finished Jul 16 05:36:22 PM PDT 24
Peak memory 223808 kb
Host smart-1e6bc8a6-1918-4f2a-8ac3-7680dff013ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122368650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.2122368650
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3730011740
Short name T156
Test name
Test status
Simulation time 4625759298 ps
CPU time 32.65 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:52 PM PDT 24
Peak memory 338512 kb
Host smart-2449ace6-f3af-45a1-b751-665b85ca5501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730011740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3730011740
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3739384577
Short name T267
Test name
Test status
Simulation time 51049387743 ps
CPU time 877.8 seconds
Started Jul 16 05:27:02 PM PDT 24
Finished Jul 16 05:41:41 PM PDT 24
Peak memory 2281952 kb
Host smart-44c5ab99-1d02-472b-9df1-7ad9f8f7c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739384577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3739384577
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.663716556
Short name T1191
Test name
Test status
Simulation time 1573855213 ps
CPU time 7.79 seconds
Started Jul 16 05:27:03 PM PDT 24
Finished Jul 16 05:27:11 PM PDT 24
Peak memory 220952 kb
Host smart-d1bb7b79-145a-47a9-8eb8-0ddddaeeea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663716556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.663716556
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2249939510
Short name T1009
Test name
Test status
Simulation time 1166627601 ps
CPU time 6.9 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:27:15 PM PDT 24
Peak memory 215952 kb
Host smart-d401af86-53f1-4b7f-ba57-36fd138d572b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249939510 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2249939510
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2804971957
Short name T727
Test name
Test status
Simulation time 282167143 ps
CPU time 0.83 seconds
Started Jul 16 05:33:22 PM PDT 24
Finished Jul 16 05:33:23 PM PDT 24
Peak memory 205468 kb
Host smart-2d3f6f69-2b4f-434f-bc2e-15a103f9ff54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804971957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2804971957
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3583590609
Short name T1248
Test name
Test status
Simulation time 193783716 ps
CPU time 0.96 seconds
Started Jul 16 05:32:04 PM PDT 24
Finished Jul 16 05:32:06 PM PDT 24
Peak memory 205324 kb
Host smart-bd591e33-ec6b-4fc3-aa60-9e38f268cdfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583590609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3583590609
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3022063143
Short name T362
Test name
Test status
Simulation time 1060307922 ps
CPU time 2.89 seconds
Started Jul 16 05:34:07 PM PDT 24
Finished Jul 16 05:34:10 PM PDT 24
Peak memory 205440 kb
Host smart-682e34b0-8081-4c82-ad97-867214bb4d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022063143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3022063143
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2631510706
Short name T1600
Test name
Test status
Simulation time 176842260 ps
CPU time 1.5 seconds
Started Jul 16 05:27:03 PM PDT 24
Finished Jul 16 05:27:05 PM PDT 24
Peak memory 205464 kb
Host smart-074c43c7-f2a1-4905-8cd1-d471a2ac484d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631510706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2631510706
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1092444353
Short name T965
Test name
Test status
Simulation time 614454283 ps
CPU time 3.81 seconds
Started Jul 16 05:27:02 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 216272 kb
Host smart-684e2e2f-83b3-4c0f-acf6-b2eb6d9ed064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092444353 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1092444353
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3718711947
Short name T1165
Test name
Test status
Simulation time 9144628933 ps
CPU time 7.14 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:13 PM PDT 24
Peak memory 205524 kb
Host smart-ef812bce-a2ac-43dd-8c4a-3929d65e4425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718711947 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3718711947
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.1016745386
Short name T385
Test name
Test status
Simulation time 606568446 ps
CPU time 2.99 seconds
Started Jul 16 05:27:01 PM PDT 24
Finished Jul 16 05:27:04 PM PDT 24
Peak memory 213732 kb
Host smart-75ca43d7-c78f-4a7d-ba9c-b1743227605a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016745386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.1016745386
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.3992691695
Short name T438
Test name
Test status
Simulation time 514000699 ps
CPU time 2.76 seconds
Started Jul 16 05:27:02 PM PDT 24
Finished Jul 16 05:27:05 PM PDT 24
Peak memory 205536 kb
Host smart-a98e62a0-79bd-4c0b-8260-538792f2a85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992691695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.3992691695
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_txstretch.2217288281
Short name T1481
Test name
Test status
Simulation time 355224144 ps
CPU time 1.59 seconds
Started Jul 16 05:27:06 PM PDT 24
Finished Jul 16 05:27:09 PM PDT 24
Peak memory 222336 kb
Host smart-7b5144c1-750d-45e2-88f1-16759bd55f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217288281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_nack_txstretch.2217288281
Directory /workspace/37.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/37.i2c_target_perf.2406455137
Short name T751
Test name
Test status
Simulation time 640766532 ps
CPU time 4.86 seconds
Started Jul 16 05:27:03 PM PDT 24
Finished Jul 16 05:27:08 PM PDT 24
Peak memory 221868 kb
Host smart-391083d0-99aa-4dcd-9da0-41b9b59219b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406455137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.2406455137
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.3995480311
Short name T1274
Test name
Test status
Simulation time 1776903575 ps
CPU time 2.13 seconds
Started Jul 16 05:31:42 PM PDT 24
Finished Jul 16 05:31:44 PM PDT 24
Peak memory 205388 kb
Host smart-1d8998d1-9765-46ca-ba8a-934e5650e25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995480311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.3995480311
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3611961295
Short name T868
Test name
Test status
Simulation time 1380277425 ps
CPU time 16.38 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:51 PM PDT 24
Peak memory 213708 kb
Host smart-bb0957cd-1527-4ecb-afc2-8c6461ff0e77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611961295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3611961295
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.305863987
Short name T165
Test name
Test status
Simulation time 67070657858 ps
CPU time 97.59 seconds
Started Jul 16 05:33:22 PM PDT 24
Finished Jul 16 05:35:00 PM PDT 24
Peak memory 958276 kb
Host smart-1b57250b-4e54-410e-b342-095c87498f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305863987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_stress_all.305863987
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3051337408
Short name T1338
Test name
Test status
Simulation time 1565437596 ps
CPU time 5.55 seconds
Started Jul 16 05:27:27 PM PDT 24
Finished Jul 16 05:27:34 PM PDT 24
Peak memory 205540 kb
Host smart-3c59b2a7-7f11-44a2-b686-29b5e6b4648c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051337408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3051337408
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1444227301
Short name T955
Test name
Test status
Simulation time 29890450110 ps
CPU time 20.06 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:25 PM PDT 24
Peak memory 470564 kb
Host smart-302b5c94-549b-40f5-b121-cea92f418dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444227301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1444227301
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3467229611
Short name T568
Test name
Test status
Simulation time 3205708743 ps
CPU time 39.85 seconds
Started Jul 16 05:32:00 PM PDT 24
Finished Jul 16 05:32:40 PM PDT 24
Peak memory 774476 kb
Host smart-4ec9fbb5-eb3d-4ef8-b566-4f110eb7c8ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467229611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3467229611
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2353872702
Short name T611
Test name
Test status
Simulation time 2388391856 ps
CPU time 6.27 seconds
Started Jul 16 05:27:04 PM PDT 24
Finished Jul 16 05:27:11 PM PDT 24
Peak memory 222028 kb
Host smart-e531444b-c8a3-444b-9ce2-63c9e7983dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353872702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2353872702
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.1067966679
Short name T858
Test name
Test status
Simulation time 107617017 ps
CPU time 2.09 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:27:10 PM PDT 24
Peak memory 205592 kb
Host smart-0bd9cd81-5642-498d-b8c7-24f3b4603c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067966679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.1067966679
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2271244376
Short name T663
Test name
Test status
Simulation time 22099096 ps
CPU time 0.65 seconds
Started Jul 16 05:27:12 PM PDT 24
Finished Jul 16 05:27:13 PM PDT 24
Peak memory 204748 kb
Host smart-07b67845-c1b1-4590-8b12-792703f629f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271244376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2271244376
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1743748032
Short name T1390
Test name
Test status
Simulation time 129257198 ps
CPU time 3.24 seconds
Started Jul 16 05:27:07 PM PDT 24
Finished Jul 16 05:27:11 PM PDT 24
Peak memory 215236 kb
Host smart-a8fee21b-ad63-4ef6-9284-b496b17ccbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743748032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1743748032
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2592235296
Short name T1426
Test name
Test status
Simulation time 346563163 ps
CPU time 16.64 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 269136 kb
Host smart-f531b2e0-d3e4-4cbc-8fd0-97e274658c0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592235296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2592235296
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2294979319
Short name T143
Test name
Test status
Simulation time 11713021164 ps
CPU time 196.79 seconds
Started Jul 16 05:27:08 PM PDT 24
Finished Jul 16 05:30:25 PM PDT 24
Peak memory 546544 kb
Host smart-51b5e5de-a602-4ca2-bb08-fb611aa7db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294979319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2294979319
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1520484613
Short name T1631
Test name
Test status
Simulation time 7378992668 ps
CPU time 133.42 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:29:19 PM PDT 24
Peak memory 666640 kb
Host smart-c78714ef-27ca-46bf-a747-e4ceec3a763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520484613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1520484613
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1469786118
Short name T330
Test name
Test status
Simulation time 231150203 ps
CPU time 11.15 seconds
Started Jul 16 05:27:02 PM PDT 24
Finished Jul 16 05:27:14 PM PDT 24
Peak memory 242632 kb
Host smart-7e3d8c66-5ce9-40ef-bce7-be7925f66c5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469786118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1469786118
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1693518802
Short name T1111
Test name
Test status
Simulation time 4050704938 ps
CPU time 86.13 seconds
Started Jul 16 05:31:16 PM PDT 24
Finished Jul 16 05:32:43 PM PDT 24
Peak memory 1000532 kb
Host smart-95904609-3e2c-4206-87a8-acc44a1ce8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693518802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1693518802
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1840421761
Short name T1679
Test name
Test status
Simulation time 589537331 ps
CPU time 24.71 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:31:43 PM PDT 24
Peak memory 205428 kb
Host smart-9ed19322-34c9-4a61-9c8e-541ecf94e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840421761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1840421761
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.1046318889
Short name T395
Test name
Test status
Simulation time 43412357 ps
CPU time 0.67 seconds
Started Jul 16 05:34:06 PM PDT 24
Finished Jul 16 05:34:08 PM PDT 24
Peak memory 205024 kb
Host smart-bf0ae807-564f-426e-a7ac-407d23343e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046318889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1046318889
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.3172700751
Short name T1407
Test name
Test status
Simulation time 79393651 ps
CPU time 1.08 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:41 PM PDT 24
Peak memory 205904 kb
Host smart-d5d87e3c-5adf-43eb-b0f3-4bee3a5f2b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172700751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.3172700751
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1531865080
Short name T1036
Test name
Test status
Simulation time 3052470594 ps
CPU time 38.43 seconds
Started Jul 16 05:27:06 PM PDT 24
Finished Jul 16 05:27:45 PM PDT 24
Peak memory 254340 kb
Host smart-c62f9074-0a17-40fa-b6b8-ff89a32238c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531865080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1531865080
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1704280728
Short name T692
Test name
Test status
Simulation time 6984494873 ps
CPU time 31.45 seconds
Started Jul 16 05:27:03 PM PDT 24
Finished Jul 16 05:27:35 PM PDT 24
Peak memory 213788 kb
Host smart-e2c6bb4e-1d1d-4cd6-a371-60d482b6dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704280728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1704280728
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3615269201
Short name T1128
Test name
Test status
Simulation time 1477832614 ps
CPU time 3.66 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:44 PM PDT 24
Peak memory 212960 kb
Host smart-afc841cc-56c4-4bbc-96eb-9332e5fb2724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615269201 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3615269201
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2549107812
Short name T810
Test name
Test status
Simulation time 973723970 ps
CPU time 0.78 seconds
Started Jul 16 05:36:21 PM PDT 24
Finished Jul 16 05:36:22 PM PDT 24
Peak memory 205428 kb
Host smart-373748ac-14ad-4b95-bebf-09e9ce34dbbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549107812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2549107812
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3985453096
Short name T1502
Test name
Test status
Simulation time 273412974 ps
CPU time 1.63 seconds
Started Jul 16 05:31:25 PM PDT 24
Finished Jul 16 05:31:27 PM PDT 24
Peak memory 205248 kb
Host smart-4253d2eb-883f-428f-9baf-d16f21d3a030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985453096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3985453096
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1600013726
Short name T1491
Test name
Test status
Simulation time 802533216 ps
CPU time 1.61 seconds
Started Jul 16 05:27:06 PM PDT 24
Finished Jul 16 05:27:08 PM PDT 24
Peak memory 205372 kb
Host smart-389e706f-27bf-4a1f-b7ac-d4fb7ccdb20e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600013726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1600013726
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2456673754
Short name T581
Test name
Test status
Simulation time 276588607 ps
CPU time 1.25 seconds
Started Jul 16 05:27:18 PM PDT 24
Finished Jul 16 05:27:20 PM PDT 24
Peak memory 205140 kb
Host smart-f7590bdf-9b0b-42ce-843e-ac817c20aad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456673754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2456673754
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2531335932
Short name T506
Test name
Test status
Simulation time 1493058509 ps
CPU time 4.63 seconds
Started Jul 16 05:31:30 PM PDT 24
Finished Jul 16 05:31:36 PM PDT 24
Peak memory 213816 kb
Host smart-c241cb84-47e9-4f46-a1bb-3d690d7cfcd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531335932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2531335932
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3246919064
Short name T1312
Test name
Test status
Simulation time 17385343990 ps
CPU time 356.98 seconds
Started Jul 16 05:27:05 PM PDT 24
Finished Jul 16 05:33:03 PM PDT 24
Peak memory 4078448 kb
Host smart-832030a3-9e6c-4f25-905b-b7990da75660
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246919064 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3246919064
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.288957161
Short name T668
Test name
Test status
Simulation time 1159872777 ps
CPU time 3.05 seconds
Started Jul 16 05:27:14 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 213736 kb
Host smart-00e0866d-0b43-4dba-9c81-defce6b5d022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288957161 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_nack_acqfull.288957161
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.3992924154
Short name T1099
Test name
Test status
Simulation time 1843373743 ps
CPU time 2.46 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:24 PM PDT 24
Peak memory 205604 kb
Host smart-991a219e-4049-409f-a34d-174177c63d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992924154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.3992924154
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.75438724
Short name T149
Test name
Test status
Simulation time 273309872 ps
CPU time 1.32 seconds
Started Jul 16 05:27:28 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 222412 kb
Host smart-1c63bcac-6ea2-43b6-bf10-8deff501bd32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75438724 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_txstretch.75438724
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1264346447
Short name T1106
Test name
Test status
Simulation time 725864071 ps
CPU time 5.07 seconds
Started Jul 16 05:27:04 PM PDT 24
Finished Jul 16 05:27:09 PM PDT 24
Peak memory 216468 kb
Host smart-a1f5f585-b611-438d-8f70-ef66dcea6e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264346447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1264346447
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.3239568786
Short name T6
Test name
Test status
Simulation time 391749037 ps
CPU time 2 seconds
Started Jul 16 05:27:12 PM PDT 24
Finished Jul 16 05:27:14 PM PDT 24
Peak memory 205388 kb
Host smart-448a202e-5e1a-4880-83ca-3c6ae03e4c02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239568786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_smbus_maxlen.3239568786
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3311962826
Short name T292
Test name
Test status
Simulation time 838734158 ps
CPU time 10.78 seconds
Started Jul 16 05:36:39 PM PDT 24
Finished Jul 16 05:36:51 PM PDT 24
Peak memory 213712 kb
Host smart-518d16d6-6345-43dc-b16e-f1586bcff726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311962826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3311962826
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.1577259532
Short name T991
Test name
Test status
Simulation time 4538954683 ps
CPU time 27.88 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:31:46 PM PDT 24
Peak memory 249556 kb
Host smart-45b3b8b9-95f4-4741-96c9-fb417716813d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577259532 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.1577259532
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2625874974
Short name T251
Test name
Test status
Simulation time 322597210 ps
CPU time 4.54 seconds
Started Jul 16 05:31:17 PM PDT 24
Finished Jul 16 05:31:22 PM PDT 24
Peak memory 205588 kb
Host smart-fc6d8f90-5980-4b0f-9af2-abd3aa161212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625874974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2625874974
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1969609767
Short name T948
Test name
Test status
Simulation time 53038211652 ps
CPU time 146.94 seconds
Started Jul 16 05:34:25 PM PDT 24
Finished Jul 16 05:36:53 PM PDT 24
Peak memory 1842432 kb
Host smart-79be192c-4903-453e-9f71-84d10a37a135
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969609767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1969609767
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.768919797
Short name T1445
Test name
Test status
Simulation time 1761978139 ps
CPU time 14.16 seconds
Started Jul 16 05:27:04 PM PDT 24
Finished Jul 16 05:27:19 PM PDT 24
Peak memory 407900 kb
Host smart-b86a41dd-4452-430e-a842-bd7c057c7b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768919797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.768919797
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3578381265
Short name T572
Test name
Test status
Simulation time 4813916107 ps
CPU time 6.58 seconds
Started Jul 16 05:32:08 PM PDT 24
Finished Jul 16 05:32:16 PM PDT 24
Peak memory 222012 kb
Host smart-26752aca-1ab9-47fd-b2c4-0a5eab6f1cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578381265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3578381265
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.3008899980
Short name T1245
Test name
Test status
Simulation time 124254538 ps
CPU time 2.63 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:27 PM PDT 24
Peak memory 205612 kb
Host smart-9b622298-5c5b-4692-a4c1-7e0ef16973a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008899980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3008899980
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.919692163
Short name T1392
Test name
Test status
Simulation time 24822028 ps
CPU time 0.64 seconds
Started Jul 16 05:27:16 PM PDT 24
Finished Jul 16 05:27:17 PM PDT 24
Peak memory 204728 kb
Host smart-48adec68-ed72-432f-a0f1-9635956184fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919692163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.919692163
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.603271787
Short name T807
Test name
Test status
Simulation time 318393498 ps
CPU time 1.15 seconds
Started Jul 16 05:27:17 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 213776 kb
Host smart-82f87059-547d-43d1-b1c2-182ed36087f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603271787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.603271787
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3168365075
Short name T757
Test name
Test status
Simulation time 2504904164 ps
CPU time 6.89 seconds
Started Jul 16 05:27:15 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 285572 kb
Host smart-0695f5f9-6be5-48fb-b68e-b56cbe742f8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168365075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3168365075
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1369950778
Short name T984
Test name
Test status
Simulation time 24621259106 ps
CPU time 132.71 seconds
Started Jul 16 05:27:13 PM PDT 24
Finished Jul 16 05:29:27 PM PDT 24
Peak memory 387272 kb
Host smart-dc8a1a89-d39f-46d1-80f8-7b0392ad1aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369950778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1369950778
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.306572272
Short name T1066
Test name
Test status
Simulation time 25025676705 ps
CPU time 97.85 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:36:06 PM PDT 24
Peak memory 545640 kb
Host smart-8d5073f5-e594-485d-8d17-d91bfe69daf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306572272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.306572272
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1221599280
Short name T699
Test name
Test status
Simulation time 651216446 ps
CPU time 1.21 seconds
Started Jul 16 05:27:18 PM PDT 24
Finished Jul 16 05:27:20 PM PDT 24
Peak memory 205196 kb
Host smart-79bd181a-3d79-44c2-befe-09e45b421904
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221599280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1221599280
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.521619182
Short name T645
Test name
Test status
Simulation time 829303108 ps
CPU time 11.04 seconds
Started Jul 16 05:27:15 PM PDT 24
Finished Jul 16 05:27:26 PM PDT 24
Peak memory 205528 kb
Host smart-a4740feb-c130-4b12-9f56-8c01ca7f648e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521619182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
521619182
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3529424309
Short name T1436
Test name
Test status
Simulation time 13007960529 ps
CPU time 86.84 seconds
Started Jul 16 05:27:22 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 951812 kb
Host smart-b87b150c-ff3c-4800-8816-282019fadd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529424309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3529424309
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.129881957
Short name T1693
Test name
Test status
Simulation time 3745088404 ps
CPU time 4.7 seconds
Started Jul 16 05:27:11 PM PDT 24
Finished Jul 16 05:27:16 PM PDT 24
Peak memory 205460 kb
Host smart-eb2368c4-a714-48de-906d-a00ab228e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129881957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.129881957
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.562544685
Short name T942
Test name
Test status
Simulation time 154096098 ps
CPU time 1.43 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 213768 kb
Host smart-d1f2c1ab-3fdb-4c4d-a892-9c770a08ef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562544685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.562544685
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1991765563
Short name T335
Test name
Test status
Simulation time 29376968 ps
CPU time 0.67 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:41 PM PDT 24
Peak memory 205160 kb
Host smart-7f9477a2-36b4-49e1-9570-f4c264d39e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991765563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1991765563
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.85166579
Short name T301
Test name
Test status
Simulation time 2391777894 ps
CPU time 9.45 seconds
Started Jul 16 05:27:20 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 205560 kb
Host smart-caf590bd-8849-4328-80ad-562bd761f3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85166579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.85166579
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.3515413498
Short name T1574
Test name
Test status
Simulation time 317963731 ps
CPU time 3.22 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:22 PM PDT 24
Peak memory 205948 kb
Host smart-37a3b941-20a5-4742-a919-a1314b5ad867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515413498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.3515413498
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2835843121
Short name T1249
Test name
Test status
Simulation time 5110486751 ps
CPU time 59.63 seconds
Started Jul 16 05:27:20 PM PDT 24
Finished Jul 16 05:28:20 PM PDT 24
Peak memory 330964 kb
Host smart-5c0aeebd-0bd0-436e-af5e-cbca685d3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835843121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2835843121
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.526483771
Short name T1479
Test name
Test status
Simulation time 3764574439 ps
CPU time 23.7 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:48 PM PDT 24
Peak memory 213760 kb
Host smart-3ee31653-da9d-485a-9220-331baa78b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526483771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.526483771
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2015935917
Short name T823
Test name
Test status
Simulation time 3505991782 ps
CPU time 4.53 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:26 PM PDT 24
Peak memory 210372 kb
Host smart-b9722174-4413-4747-91a8-b93aeee7e137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015935917 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2015935917
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1964246751
Short name T752
Test name
Test status
Simulation time 296243791 ps
CPU time 0.94 seconds
Started Jul 16 05:27:14 PM PDT 24
Finished Jul 16 05:27:16 PM PDT 24
Peak memory 205404 kb
Host smart-a5ce32d0-37a9-4ab7-ad04-713aea2cad3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964246751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1964246751
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2397571184
Short name T1720
Test name
Test status
Simulation time 671332292 ps
CPU time 1.08 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 205440 kb
Host smart-06ec8fc3-7b97-4594-b37d-46995278e91e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397571184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2397571184
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.86043216
Short name T428
Test name
Test status
Simulation time 501981731 ps
CPU time 2.34 seconds
Started Jul 16 05:27:15 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 205596 kb
Host smart-c702a5ec-8923-430c-bf2f-24b5649832fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86043216 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.86043216
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2794628535
Short name T1513
Test name
Test status
Simulation time 78797306 ps
CPU time 0.96 seconds
Started Jul 16 05:31:46 PM PDT 24
Finished Jul 16 05:31:47 PM PDT 24
Peak memory 205408 kb
Host smart-03c5416a-b598-4998-9a69-537f9a7dbf8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794628535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2794628535
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3217146577
Short name T613
Test name
Test status
Simulation time 2703125575 ps
CPU time 4.97 seconds
Started Jul 16 05:27:17 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 213880 kb
Host smart-1f44b449-1c59-4bf2-9c74-da9b7d92f913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217146577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3217146577
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2995025555
Short name T1480
Test name
Test status
Simulation time 11788744297 ps
CPU time 6.49 seconds
Started Jul 16 05:27:19 PM PDT 24
Finished Jul 16 05:27:26 PM PDT 24
Peak memory 239068 kb
Host smart-aa4afac8-5c32-43b8-a05f-26137c320db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995025555 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2995025555
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.979923860
Short name T52
Test name
Test status
Simulation time 2131975352 ps
CPU time 2.86 seconds
Started Jul 16 05:36:22 PM PDT 24
Finished Jul 16 05:36:25 PM PDT 24
Peak memory 213820 kb
Host smart-9b38cd13-7292-4b57-b1de-42baaa050455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979923860 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_nack_acqfull.979923860
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.3308608457
Short name T1236
Test name
Test status
Simulation time 528131512 ps
CPU time 2.7 seconds
Started Jul 16 05:27:19 PM PDT 24
Finished Jul 16 05:27:22 PM PDT 24
Peak memory 206324 kb
Host smart-dd696e9f-7b6f-4a5d-b1a4-50f8de45acfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308608457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.3308608457
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.1054141781
Short name T465
Test name
Test status
Simulation time 146088719 ps
CPU time 1.61 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:26 PM PDT 24
Peak memory 222460 kb
Host smart-3d760c3e-f837-4b36-a518-210e42ad1292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054141781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_nack_txstretch.1054141781
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.884311682
Short name T1297
Test name
Test status
Simulation time 724776391 ps
CPU time 4.78 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:34:33 PM PDT 24
Peak memory 221996 kb
Host smart-2ddcabbc-ce76-403d-820d-21b92d171266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884311682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_perf.884311682
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.260932162
Short name T1069
Test name
Test status
Simulation time 1720000054 ps
CPU time 2.21 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:27 PM PDT 24
Peak memory 205424 kb
Host smart-42bb534d-2d8b-46ce-9d7f-c61f891ab54c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260932162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_smbus_maxlen.260932162
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2720938290
Short name T664
Test name
Test status
Simulation time 4904285214 ps
CPU time 9.99 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:31 PM PDT 24
Peak memory 213860 kb
Host smart-d9123b90-da34-4e44-a077-dd9ab6624ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720938290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2720938290
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2382181577
Short name T808
Test name
Test status
Simulation time 63069953099 ps
CPU time 1543.27 seconds
Started Jul 16 05:31:46 PM PDT 24
Finished Jul 16 05:57:30 PM PDT 24
Peak memory 8732484 kb
Host smart-210d2a37-93d5-44de-9ac8-686b682ea426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382181577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2382181577
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.843646766
Short name T523
Test name
Test status
Simulation time 371675629 ps
CPU time 15.16 seconds
Started Jul 16 05:31:20 PM PDT 24
Finished Jul 16 05:31:36 PM PDT 24
Peak memory 205444 kb
Host smart-b98b87cd-8a3e-4eea-9f16-5bfaba8c918d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843646766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.843646766
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3379770521
Short name T737
Test name
Test status
Simulation time 73570254086 ps
CPU time 203.47 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:34:44 PM PDT 24
Peak memory 1957232 kb
Host smart-d68ab154-033f-43d4-92d2-24ef9149fe1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379770521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3379770521
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1208130983
Short name T1346
Test name
Test status
Simulation time 2044993006 ps
CPU time 94.1 seconds
Started Jul 16 05:27:16 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 640404 kb
Host smart-4d510adc-98db-4e9b-8c6b-1f2c4e172eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208130983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1208130983
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.473924278
Short name T860
Test name
Test status
Simulation time 22140581760 ps
CPU time 6.96 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:27:34 PM PDT 24
Peak memory 213784 kb
Host smart-71c9cfe5-0ce4-4a2d-94a9-bdf01d1268ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473924278 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.473924278
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.3464364147
Short name T1113
Test name
Test status
Simulation time 125740651 ps
CPU time 1.86 seconds
Started Jul 16 05:27:18 PM PDT 24
Finished Jul 16 05:27:20 PM PDT 24
Peak memory 221104 kb
Host smart-fae7de64-149e-4fc4-a33c-0e7f541cd9de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464364147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3464364147
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3467150452
Short name T912
Test name
Test status
Simulation time 37220929 ps
CPU time 0.64 seconds
Started Jul 16 05:22:35 PM PDT 24
Finished Jul 16 05:22:37 PM PDT 24
Peak memory 202244 kb
Host smart-637df772-9d6a-4e8a-9ddc-a98828888222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467150452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3467150452
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1074194366
Short name T437
Test name
Test status
Simulation time 1736712123 ps
CPU time 6.86 seconds
Started Jul 16 05:22:33 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 258976 kb
Host smart-0d1c650f-89c5-4d2e-beee-73c62c401b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074194366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1074194366
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.207644450
Short name T684
Test name
Test status
Simulation time 2227636999 ps
CPU time 8.27 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:31 PM PDT 24
Peak memory 311412 kb
Host smart-73c01124-1562-427d-9438-925812d08ec6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207644450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.207644450
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3781191784
Short name T496
Test name
Test status
Simulation time 18403636071 ps
CPU time 44.8 seconds
Started Jul 16 05:34:08 PM PDT 24
Finished Jul 16 05:34:54 PM PDT 24
Peak memory 335616 kb
Host smart-4c35b586-d434-4e8f-9849-7ac40f1f14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781191784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3781191784
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3625945719
Short name T480
Test name
Test status
Simulation time 1833644923 ps
CPU time 119.2 seconds
Started Jul 16 05:25:00 PM PDT 24
Finished Jul 16 05:27:01 PM PDT 24
Peak memory 615512 kb
Host smart-7f307e0b-dadd-4d8f-a588-6d750da7fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625945719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3625945719
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3255625240
Short name T1030
Test name
Test status
Simulation time 74218215 ps
CPU time 0.89 seconds
Started Jul 16 05:22:27 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 205204 kb
Host smart-599f3c60-73c4-4a9f-adb3-73f1ffa4914d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255625240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3255625240
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.176806965
Short name T1243
Test name
Test status
Simulation time 809976755 ps
CPU time 6.16 seconds
Started Jul 16 05:22:25 PM PDT 24
Finished Jul 16 05:22:32 PM PDT 24
Peak memory 247004 kb
Host smart-fe19b881-9088-4339-962a-4a71f71d3dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176806965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.176806965
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1012358458
Short name T1713
Test name
Test status
Simulation time 84520471397 ps
CPU time 393.02 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:29:39 PM PDT 24
Peak memory 1466744 kb
Host smart-5804204f-684b-499b-81d1-3a0e1d36d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012358458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1012358458
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3611272550
Short name T1435
Test name
Test status
Simulation time 1043226605 ps
CPU time 23.5 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 205436 kb
Host smart-0bc44ca5-c75c-4e59-88e0-dfcba3cdab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611272550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3611272550
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2430005956
Short name T1374
Test name
Test status
Simulation time 221617583 ps
CPU time 1.62 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:38 PM PDT 24
Peak memory 213680 kb
Host smart-99f0e181-35c7-4a17-83bd-c4c246647a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430005956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2430005956
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.336557731
Short name T73
Test name
Test status
Simulation time 28028293 ps
CPU time 0.7 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:25 PM PDT 24
Peak memory 205160 kb
Host smart-c7fce8d2-9f8c-4aa3-852a-8f52ab400973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336557731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.336557731
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2354941989
Short name T1186
Test name
Test status
Simulation time 2847953892 ps
CPU time 106.35 seconds
Started Jul 16 05:22:35 PM PDT 24
Finished Jul 16 05:24:22 PM PDT 24
Peak memory 245336 kb
Host smart-3308bb9d-191b-40cc-a828-655829ccee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354941989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2354941989
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.964134589
Short name T1288
Test name
Test status
Simulation time 23361913164 ps
CPU time 155.12 seconds
Started Jul 16 05:23:03 PM PDT 24
Finished Jul 16 05:25:40 PM PDT 24
Peak memory 205296 kb
Host smart-b9cf5f41-d887-4ee9-9637-fef87097d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964134589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.964134589
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3672587033
Short name T1476
Test name
Test status
Simulation time 4438502738 ps
CPU time 53.06 seconds
Started Jul 16 05:25:11 PM PDT 24
Finished Jul 16 05:26:04 PM PDT 24
Peak memory 316704 kb
Host smart-fe112d35-56a2-4e72-9575-33e0573cf23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672587033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3672587033
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2201533290
Short name T40
Test name
Test status
Simulation time 109858107296 ps
CPU time 1060.94 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:40:04 PM PDT 24
Peak memory 2711420 kb
Host smart-85ab24d3-f4f4-43d3-a35c-6eb16272f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201533290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2201533290
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1512794545
Short name T1728
Test name
Test status
Simulation time 792025695 ps
CPU time 7.4 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 213748 kb
Host smart-5b843015-a524-4b29-a74c-620e7af5b0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512794545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1512794545
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2018080187
Short name T429
Test name
Test status
Simulation time 2161894366 ps
CPU time 6.59 seconds
Started Jul 16 05:22:28 PM PDT 24
Finished Jul 16 05:22:35 PM PDT 24
Peak memory 221944 kb
Host smart-3424b87b-c606-4d39-84fd-08b1f917acc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018080187 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2018080187
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2588328489
Short name T410
Test name
Test status
Simulation time 441415395 ps
CPU time 1.1 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:24 PM PDT 24
Peak memory 205596 kb
Host smart-63a5bb56-6b52-4c89-af46-2b59f50fa897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588328489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2588328489
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.4139650802
Short name T1256
Test name
Test status
Simulation time 468895981 ps
CPU time 1.04 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 205380 kb
Host smart-c3bad529-d938-4365-9d99-2fc76a11443b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139650802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.4139650802
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.967891926
Short name T1692
Test name
Test status
Simulation time 117791788 ps
CPU time 0.99 seconds
Started Jul 16 05:22:22 PM PDT 24
Finished Jul 16 05:22:24 PM PDT 24
Peak memory 205436 kb
Host smart-b9864e85-1d41-4279-bac0-6c7d732c0a30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967891926 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.967891926
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2819570674
Short name T644
Test name
Test status
Simulation time 150890063 ps
CPU time 1.38 seconds
Started Jul 16 05:22:20 PM PDT 24
Finished Jul 16 05:22:22 PM PDT 24
Peak memory 205424 kb
Host smart-6f580b64-226e-4c5a-84af-3652a8ac0b14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819570674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2819570674
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2884952675
Short name T789
Test name
Test status
Simulation time 3832376647 ps
CPU time 3.28 seconds
Started Jul 16 05:22:31 PM PDT 24
Finished Jul 16 05:22:34 PM PDT 24
Peak memory 217536 kb
Host smart-2f5c4d14-6e86-4f14-8af4-ea2f52e3e2d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884952675 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2884952675
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3950887142
Short name T598
Test name
Test status
Simulation time 5696409973 ps
CPU time 7.6 seconds
Started Jul 16 05:22:27 PM PDT 24
Finished Jul 16 05:22:35 PM PDT 24
Peak memory 205592 kb
Host smart-3bb08861-0ca5-4201-91bc-e5382255841e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950887142 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3950887142
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.3707476761
Short name T1428
Test name
Test status
Simulation time 1125267822 ps
CPU time 3.09 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:30 PM PDT 24
Peak memory 213884 kb
Host smart-3dbfad2e-79d9-4eb7-a41c-ac8c14b0344d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707476761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.3707476761
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.3653136764
Short name T2
Test name
Test status
Simulation time 500822970 ps
CPU time 2.62 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:29 PM PDT 24
Peak memory 205656 kb
Host smart-b351ed60-e531-405b-84d4-a9deff40a9f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653136764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.3653136764
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.1888557806
Short name T1120
Test name
Test status
Simulation time 1430371107 ps
CPU time 5.37 seconds
Started Jul 16 05:22:32 PM PDT 24
Finished Jul 16 05:22:38 PM PDT 24
Peak memory 220832 kb
Host smart-56fcdcb4-0b64-4564-a0d7-47b4d5adb7cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888557806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.1888557806
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.2183990028
Short name T672
Test name
Test status
Simulation time 1735916789 ps
CPU time 2.14 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:27 PM PDT 24
Peak memory 205372 kb
Host smart-97c5a8a1-a978-4506-b6af-68835a86b741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183990028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_smbus_maxlen.2183990028
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2092376378
Short name T342
Test name
Test status
Simulation time 1296478305 ps
CPU time 42.34 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:46 PM PDT 24
Peak memory 213784 kb
Host smart-09e0057e-c469-42a3-9670-b73b0141da87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092376378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2092376378
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.1799273947
Short name T259
Test name
Test status
Simulation time 10430131266 ps
CPU time 101.06 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:24:44 PM PDT 24
Peak memory 1456596 kb
Host smart-6a06c456-c55e-4d2e-8f90-3a7e564fa32a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799273947 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.1799273947
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2631469731
Short name T1268
Test name
Test status
Simulation time 4224187522 ps
CPU time 22.09 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:47 PM PDT 24
Peak memory 230100 kb
Host smart-3b031111-6fc1-4648-9913-5b6c25a57dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631469731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2631469731
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2740145594
Short name T675
Test name
Test status
Simulation time 55119351247 ps
CPU time 578.41 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:34:53 PM PDT 24
Peak memory 4483780 kb
Host smart-2bc4db8a-6b34-4bb1-9016-62b5404db8d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740145594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2740145594
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3462035931
Short name T887
Test name
Test status
Simulation time 1423116186 ps
CPU time 8.06 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:31 PM PDT 24
Peak memory 221872 kb
Host smart-d7fc8556-a373-4d05-8abe-80bea515eb46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462035931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3462035931
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.4163958478
Short name T1405
Test name
Test status
Simulation time 140847813 ps
CPU time 3.17 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 205468 kb
Host smart-aa8a7906-4755-41c0-82e5-548ca70f8670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163958478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.4163958478
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2855834864
Short name T77
Test name
Test status
Simulation time 20818496 ps
CPU time 0.63 seconds
Started Jul 16 05:27:26 PM PDT 24
Finished Jul 16 05:27:28 PM PDT 24
Peak memory 204868 kb
Host smart-1d07dd9f-8d92-4621-ab02-8ce29118d389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855834864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2855834864
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3365152123
Short name T1610
Test name
Test status
Simulation time 282265646 ps
CPU time 1.55 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:27:28 PM PDT 24
Peak memory 213644 kb
Host smart-3ceb3341-6bbb-402a-9272-368186af8709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365152123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3365152123
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1178247194
Short name T416
Test name
Test status
Simulation time 756275875 ps
CPU time 18.13 seconds
Started Jul 16 05:27:17 PM PDT 24
Finished Jul 16 05:27:35 PM PDT 24
Peak memory 264416 kb
Host smart-2694cc1a-25b6-4df9-9032-2134e042f961
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178247194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1178247194
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3712735433
Short name T747
Test name
Test status
Simulation time 1725100402 ps
CPU time 55.14 seconds
Started Jul 16 05:27:12 PM PDT 24
Finished Jul 16 05:28:07 PM PDT 24
Peak memory 428232 kb
Host smart-37e71f09-e696-42dd-9d89-60fa3d763a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712735433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3712735433
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2084264104
Short name T884
Test name
Test status
Simulation time 9732278533 ps
CPU time 81.45 seconds
Started Jul 16 05:27:18 PM PDT 24
Finished Jul 16 05:28:40 PM PDT 24
Peak memory 813316 kb
Host smart-6eb927dc-be0d-42d0-bfbf-1842eb9e03e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084264104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2084264104
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2871405589
Short name T375
Test name
Test status
Simulation time 350754869 ps
CPU time 1.21 seconds
Started Jul 16 05:27:16 PM PDT 24
Finished Jul 16 05:27:18 PM PDT 24
Peak memory 205116 kb
Host smart-6f58e0ed-2809-4dbd-9796-a0f842b45d99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871405589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2871405589
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3052995580
Short name T1595
Test name
Test status
Simulation time 381995121 ps
CPU time 10.29 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:27:36 PM PDT 24
Peak memory 239744 kb
Host smart-69c9fff2-966a-4ecf-840a-24ecd23e085c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052995580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3052995580
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2949499428
Short name T1267
Test name
Test status
Simulation time 16989878419 ps
CPU time 96.81 seconds
Started Jul 16 05:27:22 PM PDT 24
Finished Jul 16 05:29:00 PM PDT 24
Peak memory 1093428 kb
Host smart-44e9db5f-ad86-4f19-895c-724baed1710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949499428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2949499428
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3507953368
Short name T1154
Test name
Test status
Simulation time 2027407141 ps
CPU time 4.54 seconds
Started Jul 16 05:36:35 PM PDT 24
Finished Jul 16 05:36:41 PM PDT 24
Peak memory 205524 kb
Host smart-a375b27f-8791-42c4-a777-bef10b9d07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507953368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3507953368
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.1242159476
Short name T894
Test name
Test status
Simulation time 18225483 ps
CPU time 0.66 seconds
Started Jul 16 05:27:18 PM PDT 24
Finished Jul 16 05:27:20 PM PDT 24
Peak memory 205172 kb
Host smart-456c22aa-6e5e-46dc-b9b6-25dfeb28cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242159476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1242159476
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1973460656
Short name T612
Test name
Test status
Simulation time 6955035371 ps
CPU time 35.44 seconds
Started Jul 16 05:32:18 PM PDT 24
Finished Jul 16 05:32:54 PM PDT 24
Peak memory 251028 kb
Host smart-fb2da11c-adb9-4193-acbd-32ed4f16286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973460656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1973460656
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1279381927
Short name T442
Test name
Test status
Simulation time 142072113 ps
CPU time 1.19 seconds
Started Jul 16 05:27:21 PM PDT 24
Finished Jul 16 05:27:23 PM PDT 24
Peak memory 213648 kb
Host smart-806b78f8-f39a-4876-ba39-1ff70b4836b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279381927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1279381927
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.959861074
Short name T254
Test name
Test status
Simulation time 2670843019 ps
CPU time 22.5 seconds
Started Jul 16 05:27:20 PM PDT 24
Finished Jul 16 05:27:43 PM PDT 24
Peak memory 368480 kb
Host smart-ccd251bd-1d94-42b3-a706-2952304b6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959861074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.959861074
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.577972685
Short name T788
Test name
Test status
Simulation time 893891794 ps
CPU time 19.92 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:27:46 PM PDT 24
Peak memory 213560 kb
Host smart-e48c1897-3f4e-4c7b-81ce-b2455d04bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577972685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.577972685
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1210056938
Short name T1234
Test name
Test status
Simulation time 5203142264 ps
CPU time 6.57 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:27:43 PM PDT 24
Peak memory 215224 kb
Host smart-d8b9bc34-df08-4323-9133-5552606da70a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210056938 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1210056938
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1089068874
Short name T1591
Test name
Test status
Simulation time 314991076 ps
CPU time 1.28 seconds
Started Jul 16 05:33:21 PM PDT 24
Finished Jul 16 05:33:23 PM PDT 24
Peak memory 205584 kb
Host smart-2f535a66-6405-4832-bdb1-d27560838d54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089068874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1089068874
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2285004357
Short name T275
Test name
Test status
Simulation time 332002150 ps
CPU time 1.45 seconds
Started Jul 16 05:32:27 PM PDT 24
Finished Jul 16 05:32:29 PM PDT 24
Peak memory 205688 kb
Host smart-f72e258c-ba90-4003-9114-22fdbfdb7a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285004357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2285004357
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.3777594519
Short name T558
Test name
Test status
Simulation time 1337121183 ps
CPU time 2.43 seconds
Started Jul 16 05:32:16 PM PDT 24
Finished Jul 16 05:32:19 PM PDT 24
Peak memory 205324 kb
Host smart-e0d11e52-454e-4ec1-972c-d5ea340b0f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777594519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3777594519
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.813036591
Short name T862
Test name
Test status
Simulation time 136410766 ps
CPU time 1.51 seconds
Started Jul 16 05:31:40 PM PDT 24
Finished Jul 16 05:31:42 PM PDT 24
Peak memory 205432 kb
Host smart-bceb089c-7b89-4c9a-a07f-84a8e8d7a85b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813036591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.813036591
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1495829810
Short name T821
Test name
Test status
Simulation time 2326017841 ps
CPU time 5.35 seconds
Started Jul 16 05:27:23 PM PDT 24
Finished Jul 16 05:27:29 PM PDT 24
Peak memory 221964 kb
Host smart-17e3421c-fe72-4376-a5bd-17b2d29b2f62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495829810 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1495829810
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3338453068
Short name T455
Test name
Test status
Simulation time 22265512916 ps
CPU time 213.85 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:40:09 PM PDT 24
Peak memory 2677572 kb
Host smart-45727382-5475-4cfe-a42b-037d0924d120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338453068 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3338453068
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.1673979919
Short name T1064
Test name
Test status
Simulation time 7067755718 ps
CPU time 2.51 seconds
Started Jul 16 05:31:19 PM PDT 24
Finished Jul 16 05:31:23 PM PDT 24
Peak memory 213880 kb
Host smart-c0d6dae3-1520-4279-a3c6-11e677b17686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673979919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.1673979919
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.3140160845
Short name T634
Test name
Test status
Simulation time 6183557211 ps
CPU time 2.82 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 205644 kb
Host smart-c83e4d4d-f059-4df0-83ce-c2279e1d1e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140160845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.3140160845
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_txstretch.1047993185
Short name T1465
Test name
Test status
Simulation time 152364248 ps
CPU time 1.38 seconds
Started Jul 16 05:27:26 PM PDT 24
Finished Jul 16 05:27:28 PM PDT 24
Peak memory 222228 kb
Host smart-9c61c4cb-c001-4ac0-95c4-56992fe6f1fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047993185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_nack_txstretch.1047993185
Directory /workspace/40.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/40.i2c_target_perf.498161468
Short name T842
Test name
Test status
Simulation time 2822891574 ps
CPU time 4.69 seconds
Started Jul 16 05:32:25 PM PDT 24
Finished Jul 16 05:32:30 PM PDT 24
Peak memory 216724 kb
Host smart-75611813-3a66-4396-a293-b39b8e23b589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498161468 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_perf.498161468
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.2681102739
Short name T1672
Test name
Test status
Simulation time 2935023968 ps
CPU time 2.17 seconds
Started Jul 16 05:27:28 PM PDT 24
Finished Jul 16 05:27:31 PM PDT 24
Peak memory 205468 kb
Host smart-4afd29fd-51b3-4a28-afc3-8c00991756d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681102739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.2681102739
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2530746073
Short name T1129
Test name
Test status
Simulation time 1183606539 ps
CPU time 38.12 seconds
Started Jul 16 05:32:16 PM PDT 24
Finished Jul 16 05:32:55 PM PDT 24
Peak memory 213732 kb
Host smart-b516f595-a9b2-4550-b3b5-c592cfc9337a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530746073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2530746073
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.1640606862
Short name T1534
Test name
Test status
Simulation time 30252149992 ps
CPU time 39.31 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:28:15 PM PDT 24
Peak memory 366496 kb
Host smart-c8cdffe8-9efe-409a-ac60-1b74764a5077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640606862 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.1640606862
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.4083995848
Short name T360
Test name
Test status
Simulation time 6181294003 ps
CPU time 25.51 seconds
Started Jul 16 05:27:12 PM PDT 24
Finished Jul 16 05:27:38 PM PDT 24
Peak memory 246420 kb
Host smart-ac2c04b2-0ac2-4674-9868-0b68c01a6f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083995848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.4083995848
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.149228898
Short name T1242
Test name
Test status
Simulation time 28792043855 ps
CPU time 159.28 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:30:06 PM PDT 24
Peak memory 2310076 kb
Host smart-4bc95273-f9e4-4b3a-911f-ed1885609d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149228898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.149228898
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3801408569
Short name T469
Test name
Test status
Simulation time 1659496239 ps
CPU time 26.19 seconds
Started Jul 16 05:27:14 PM PDT 24
Finished Jul 16 05:27:40 PM PDT 24
Peak memory 558972 kb
Host smart-da725328-5608-492a-b1ad-e4d979686777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801408569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3801408569
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.442171309
Short name T1209
Test name
Test status
Simulation time 1559681439 ps
CPU time 5.9 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 213876 kb
Host smart-39e6ab5a-9c3f-4f54-a340-e69977531d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442171309 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.442171309
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.4103937038
Short name T1264
Test name
Test status
Simulation time 253435631 ps
CPU time 4.49 seconds
Started Jul 16 05:31:43 PM PDT 24
Finished Jul 16 05:31:48 PM PDT 24
Peak memory 205560 kb
Host smart-781fba05-b974-45a7-82e1-d6cea639ad64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103937038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.4103937038
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.197972462
Short name T355
Test name
Test status
Simulation time 27467529 ps
CPU time 0.61 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:40 PM PDT 24
Peak memory 204828 kb
Host smart-f5f86852-f046-44b2-aca7-09d32c648708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197972462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.197972462
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.42125673
Short name T391
Test name
Test status
Simulation time 503572910 ps
CPU time 3.17 seconds
Started Jul 16 05:31:53 PM PDT 24
Finished Jul 16 05:31:56 PM PDT 24
Peak memory 231948 kb
Host smart-72c73d42-1dc7-40d3-b907-3aed99f83fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42125673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.42125673
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.4064493592
Short name T382
Test name
Test status
Simulation time 3769725944 ps
CPU time 4.47 seconds
Started Jul 16 05:27:31 PM PDT 24
Finished Jul 16 05:27:36 PM PDT 24
Peak memory 253816 kb
Host smart-4bbfb706-66a4-4ead-abe2-ce0559bf1733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064493592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.4064493592
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2495379872
Short name T835
Test name
Test status
Simulation time 2164063359 ps
CPU time 55.58 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:28:21 PM PDT 24
Peak memory 404568 kb
Host smart-a95a8702-61bb-4628-9818-89a89bc000bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495379872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2495379872
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1525031014
Short name T819
Test name
Test status
Simulation time 5202939183 ps
CPU time 72.25 seconds
Started Jul 16 05:27:36 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 683084 kb
Host smart-865a8001-8893-4640-8e7c-78269027c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525031014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1525031014
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.70536804
Short name T228
Test name
Test status
Simulation time 70311569 ps
CPU time 0.91 seconds
Started Jul 16 05:27:23 PM PDT 24
Finished Jul 16 05:27:25 PM PDT 24
Peak memory 205212 kb
Host smart-5c0e8175-6776-406a-b7ba-9eca0207a208
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70536804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt
.70536804
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.513615036
Short name T1152
Test name
Test status
Simulation time 1499508795 ps
CPU time 3.45 seconds
Started Jul 16 05:32:23 PM PDT 24
Finished Jul 16 05:32:27 PM PDT 24
Peak memory 205552 kb
Host smart-4575ca6a-476a-4552-a09e-717b82aae22d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513615036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
513615036
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1031765784
Short name T1444
Test name
Test status
Simulation time 3113929969 ps
CPU time 78.51 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:37:53 PM PDT 24
Peak memory 948340 kb
Host smart-d146e33b-b2c6-4ff5-a2b6-8d9f9c89d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031765784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1031765784
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2560790427
Short name T338
Test name
Test status
Simulation time 984924179 ps
CPU time 3.57 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:31:44 PM PDT 24
Peak memory 205528 kb
Host smart-9748ab79-6d78-4e1c-b523-0b826b873253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560790427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2560790427
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.3949694235
Short name T1647
Test name
Test status
Simulation time 29967145 ps
CPU time 0.69 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:36 PM PDT 24
Peak memory 205156 kb
Host smart-b60d0843-0d11-455e-821c-b6a52c2c3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949694235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3949694235
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1140534020
Short name T1526
Test name
Test status
Simulation time 28308477493 ps
CPU time 905.72 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:42:32 PM PDT 24
Peak memory 2594088 kb
Host smart-4d201b6b-68f2-4c93-9ccf-df4fd0e338d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140534020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1140534020
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.2475238655
Short name T791
Test name
Test status
Simulation time 292468508 ps
CPU time 2.97 seconds
Started Jul 16 05:27:28 PM PDT 24
Finished Jul 16 05:27:31 PM PDT 24
Peak memory 218432 kb
Host smart-2b3e640a-4a73-46c4-8f70-8c7fa51595b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475238655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.2475238655
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2319265896
Short name T387
Test name
Test status
Simulation time 10344280146 ps
CPU time 38.89 seconds
Started Jul 16 05:27:25 PM PDT 24
Finished Jul 16 05:28:05 PM PDT 24
Peak memory 403872 kb
Host smart-f48eb73c-bbfb-4958-bf6b-8b7a02128993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319265896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2319265896
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.63451048
Short name T31
Test name
Test status
Simulation time 70130327095 ps
CPU time 1262.07 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:48:26 PM PDT 24
Peak memory 3337852 kb
Host smart-14e68ebf-ba01-4ae6-8c1b-816702884fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63451048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.63451048
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.38130131
Short name T1029
Test name
Test status
Simulation time 1901877991 ps
CPU time 8.05 seconds
Started Jul 16 05:29:16 PM PDT 24
Finished Jul 16 05:29:25 PM PDT 24
Peak memory 213496 kb
Host smart-095cd4a5-3efe-4fd2-99af-cb6fad3992b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38130131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.38130131
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2730839385
Short name T1357
Test name
Test status
Simulation time 689186389 ps
CPU time 3.57 seconds
Started Jul 16 05:34:21 PM PDT 24
Finished Jul 16 05:34:25 PM PDT 24
Peak memory 221956 kb
Host smart-88f54955-bccb-4a6f-91b3-234b45d59b41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730839385 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2730839385
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2050296925
Short name T1569
Test name
Test status
Simulation time 114502838 ps
CPU time 0.96 seconds
Started Jul 16 05:27:39 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 205436 kb
Host smart-c03ec90f-5f81-4940-8b08-870e1c101ea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050296925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2050296925
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1339270401
Short name T1228
Test name
Test status
Simulation time 490638277 ps
CPU time 1.05 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:27:36 PM PDT 24
Peak memory 205576 kb
Host smart-da58f785-71fc-4345-9813-ed35189284aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339270401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1339270401
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1860727159
Short name T447
Test name
Test status
Simulation time 1677239835 ps
CPU time 2.65 seconds
Started Jul 16 05:27:44 PM PDT 24
Finished Jul 16 05:27:47 PM PDT 24
Peak memory 205512 kb
Host smart-c8e6b1e0-588e-4fde-8bee-3e099313cee8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860727159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1860727159
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3959517250
Short name T1483
Test name
Test status
Simulation time 2158540533 ps
CPU time 1.52 seconds
Started Jul 16 05:28:51 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 205472 kb
Host smart-4bb5dee9-216c-47ef-bf35-c03efcc4f468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959517250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3959517250
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2523066948
Short name T1319
Test name
Test status
Simulation time 568210881 ps
CPU time 2.32 seconds
Started Jul 16 05:27:40 PM PDT 24
Finished Jul 16 05:27:43 PM PDT 24
Peak memory 213824 kb
Host smart-604ff8e7-f041-44c5-bdc0-a26d79cfddcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523066948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2523066948
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3240457917
Short name T179
Test name
Test status
Simulation time 6764383393 ps
CPU time 6.24 seconds
Started Jul 16 05:27:23 PM PDT 24
Finished Jul 16 05:27:30 PM PDT 24
Peak memory 216012 kb
Host smart-04d010dd-acf7-476e-80d2-f33440eff23e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240457917 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3240457917
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1741858989
Short name T811
Test name
Test status
Simulation time 9087902613 ps
CPU time 19.16 seconds
Started Jul 16 05:27:23 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 619752 kb
Host smart-cadf1f5a-e961-4a72-9dde-5911c03ff3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741858989 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1741858989
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.2493185135
Short name T1170
Test name
Test status
Simulation time 473442481 ps
CPU time 2.71 seconds
Started Jul 16 05:32:35 PM PDT 24
Finished Jul 16 05:32:39 PM PDT 24
Peak memory 213792 kb
Host smart-6b0a7e89-97b9-4999-b9d2-c79fa4072cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493185135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.2493185135
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.3860304193
Short name T58
Test name
Test status
Simulation time 1410283288 ps
CPU time 2.5 seconds
Started Jul 16 05:27:44 PM PDT 24
Finished Jul 16 05:27:47 PM PDT 24
Peak memory 205440 kb
Host smart-0d1a0051-bd6f-4406-bdb1-c67bd65ef0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860304193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.3860304193
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_txstretch.2841727405
Short name T1118
Test name
Test status
Simulation time 565445786 ps
CPU time 1.38 seconds
Started Jul 16 05:31:24 PM PDT 24
Finished Jul 16 05:31:26 PM PDT 24
Peak memory 222164 kb
Host smart-b41092b4-b85e-4792-9ee6-867ad8549559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841727405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_txstretch.2841727405
Directory /workspace/41.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/41.i2c_target_perf.504829424
Short name T278
Test name
Test status
Simulation time 602651426 ps
CPU time 4.62 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 210148 kb
Host smart-305af6f7-8350-4c9e-99b0-5842f8316349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504829424 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_perf.504829424
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.2551097408
Short name T1401
Test name
Test status
Simulation time 953735188 ps
CPU time 2.19 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 204740 kb
Host smart-6def34f4-410f-462f-acc1-f657ff8a8ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551097408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.2551097408
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3434565490
Short name T704
Test name
Test status
Simulation time 1466416790 ps
CPU time 13.86 seconds
Started Jul 16 05:27:24 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 213796 kb
Host smart-2555e526-8311-4319-8d80-3503dc6a64f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434565490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3434565490
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3159749096
Short name T515
Test name
Test status
Simulation time 41778422200 ps
CPU time 65.77 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 697660 kb
Host smart-ee6787b6-4440-4d00-99d4-90c076de4798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159749096 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3159749096
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3600577713
Short name T934
Test name
Test status
Simulation time 6331777048 ps
CPU time 29.15 seconds
Started Jul 16 05:34:26 PM PDT 24
Finished Jul 16 05:34:57 PM PDT 24
Peak memory 230120 kb
Host smart-b6c11be2-7051-4527-80ab-09c2f50ffd14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600577713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3600577713
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3319593296
Short name T427
Test name
Test status
Simulation time 62210043731 ps
CPU time 2160 seconds
Started Jul 16 05:27:23 PM PDT 24
Finished Jul 16 06:03:24 PM PDT 24
Peak memory 10359396 kb
Host smart-39c0026b-e26a-4b7f-a4f3-fc44a6b3560e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319593296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3319593296
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3568914324
Short name T1463
Test name
Test status
Simulation time 4238427095 ps
CPU time 53.61 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:35:22 PM PDT 24
Peak memory 472860 kb
Host smart-11db5417-1253-4434-8d14-6d059da179b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568914324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3568914324
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2600864355
Short name T656
Test name
Test status
Simulation time 1859725972 ps
CPU time 7.43 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 217576 kb
Host smart-66d62180-f55c-4984-9c8f-60801fedf99d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600864355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2600864355
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.4142228561
Short name T729
Test name
Test status
Simulation time 473592248 ps
CPU time 7.02 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:45 PM PDT 24
Peak memory 205584 kb
Host smart-2be0b9e8-1992-4023-97af-f84b200f0284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142228561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.4142228561
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1524197776
Short name T1166
Test name
Test status
Simulation time 19955686 ps
CPU time 0.64 seconds
Started Jul 16 05:27:43 PM PDT 24
Finished Jul 16 05:27:45 PM PDT 24
Peak memory 204660 kb
Host smart-fba19ddd-fc86-4995-891f-b87f3dfeab0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524197776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1524197776
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2151219926
Short name T511
Test name
Test status
Simulation time 302979572 ps
CPU time 1.24 seconds
Started Jul 16 05:28:56 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 213668 kb
Host smart-83b103bf-778e-41e7-8fed-41e1d1bf4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151219926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2151219926
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.41181475
Short name T514
Test name
Test status
Simulation time 451904313 ps
CPU time 23.32 seconds
Started Jul 16 05:27:36 PM PDT 24
Finished Jul 16 05:28:00 PM PDT 24
Peak memory 302716 kb
Host smart-f79b07d8-6eee-47fc-be56-20de231088ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty
.41181475
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3604580571
Short name T1503
Test name
Test status
Simulation time 14766957885 ps
CPU time 92.05 seconds
Started Jul 16 05:27:36 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 552340 kb
Host smart-49c3a1a5-7a0d-4bcf-9971-f397711d370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604580571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3604580571
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.787996043
Short name T1624
Test name
Test status
Simulation time 11288048464 ps
CPU time 166.69 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:30:25 PM PDT 24
Peak memory 743160 kb
Host smart-9db8be04-3530-4a84-91cb-ff51b7b0505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787996043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.787996043
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2570952428
Short name T861
Test name
Test status
Simulation time 598273740 ps
CPU time 1.25 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 205172 kb
Host smart-7b5ea289-c457-472a-a02f-dde5950c61c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570952428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2570952428
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1145635896
Short name T1075
Test name
Test status
Simulation time 163329701 ps
CPU time 8.14 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 205292 kb
Host smart-1a077767-d817-445d-be8f-c460b51754d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145635896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1145635896
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3633459153
Short name T1606
Test name
Test status
Simulation time 8137064885 ps
CPU time 233.8 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:31:31 PM PDT 24
Peak memory 1015484 kb
Host smart-80d8ac52-d278-432e-9bb8-f17e1d087333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633459153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3633459153
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1023406304
Short name T233
Test name
Test status
Simulation time 1000075412 ps
CPU time 18.91 seconds
Started Jul 16 05:27:50 PM PDT 24
Finished Jul 16 05:28:10 PM PDT 24
Peak memory 205536 kb
Host smart-07300740-0dce-438e-adfc-a08426ec8d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023406304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1023406304
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.150468173
Short name T132
Test name
Test status
Simulation time 27900110 ps
CPU time 0.66 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:37 PM PDT 24
Peak memory 205192 kb
Host smart-ac515f80-2704-42b2-9cdf-6c7e53b07d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150468173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.150468173
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3745009783
Short name T688
Test name
Test status
Simulation time 9314266729 ps
CPU time 192.27 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:30:50 PM PDT 24
Peak memory 1135040 kb
Host smart-e8767f18-91e9-487c-ab98-c7f5a899ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745009783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3745009783
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.3509518576
Short name T832
Test name
Test status
Simulation time 310519555 ps
CPU time 1.69 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 219332 kb
Host smart-4fb9ed50-7353-4232-864b-5f594a046b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509518576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3509518576
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2457582082
Short name T1597
Test name
Test status
Simulation time 2570291438 ps
CPU time 127.97 seconds
Started Jul 16 05:27:35 PM PDT 24
Finished Jul 16 05:29:43 PM PDT 24
Peak memory 486276 kb
Host smart-f02ae9e1-a709-44b4-8cf8-c398a3ac31ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457582082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2457582082
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.931232098
Short name T931
Test name
Test status
Simulation time 7530946939 ps
CPU time 12.11 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:50 PM PDT 24
Peak memory 218608 kb
Host smart-b1bd0887-99f4-4d2d-ae1e-7af54f4b3a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931232098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.931232098
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3352911389
Short name T1311
Test name
Test status
Simulation time 2346787952 ps
CPU time 5.21 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:43 PM PDT 24
Peak memory 213940 kb
Host smart-80c0d904-e209-419b-99c6-282a4dfbd1be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352911389 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3352911389
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2773695414
Short name T1377
Test name
Test status
Simulation time 237501754 ps
CPU time 1.55 seconds
Started Jul 16 05:27:36 PM PDT 24
Finished Jul 16 05:27:38 PM PDT 24
Peak memory 205780 kb
Host smart-7dd7b60a-14b9-4fdd-94db-fd9dee10acad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773695414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2773695414
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.702228880
Short name T153
Test name
Test status
Simulation time 259920274 ps
CPU time 1.83 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:27:52 PM PDT 24
Peak memory 209384 kb
Host smart-cac0046f-1d05-4f12-b655-a63c6bcedd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702228880 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.702228880
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1160033715
Short name T625
Test name
Test status
Simulation time 340136557 ps
CPU time 1.87 seconds
Started Jul 16 05:36:36 PM PDT 24
Finished Jul 16 05:36:40 PM PDT 24
Peak memory 205452 kb
Host smart-ea534e8a-e342-4bcd-a632-7e744982226f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160033715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1160033715
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.704822480
Short name T124
Test name
Test status
Simulation time 159916062 ps
CPU time 1.48 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:27:51 PM PDT 24
Peak memory 205484 kb
Host smart-894c071e-783d-4a7a-96da-ece044d5b41b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704822480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.704822480
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1137937482
Short name T168
Test name
Test status
Simulation time 238421086 ps
CPU time 1.89 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 213744 kb
Host smart-628b1daa-038b-4ad2-88d8-fd362b4c1a46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137937482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1137937482
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3599619719
Short name T507
Test name
Test status
Simulation time 2029268024 ps
CPU time 6.74 seconds
Started Jul 16 05:27:39 PM PDT 24
Finished Jul 16 05:27:47 PM PDT 24
Peak memory 230108 kb
Host smart-608f8b40-b4d5-40a6-95e5-ab8b353302c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599619719 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3599619719
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3742548832
Short name T843
Test name
Test status
Simulation time 12371946870 ps
CPU time 72.76 seconds
Started Jul 16 05:27:50 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 1556376 kb
Host smart-60cfffdc-7344-4c6a-aa31-bfa8becb1f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742548832 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3742548832
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.4061017139
Short name T524
Test name
Test status
Simulation time 1823049490 ps
CPU time 2.64 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:41 PM PDT 24
Peak memory 213300 kb
Host smart-84b1220e-3673-4681-9926-1ef74ef1a8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061017139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.4061017139
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.3957797477
Short name T141
Test name
Test status
Simulation time 502426714 ps
CPU time 2.6 seconds
Started Jul 16 05:27:39 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 205880 kb
Host smart-9b8bd258-efb9-48ab-8fbf-03116e0d92e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957797477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.3957797477
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.1573751327
Short name T873
Test name
Test status
Simulation time 750141160 ps
CPU time 5.26 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:27:55 PM PDT 24
Peak memory 221992 kb
Host smart-cfebefce-7d9d-4e11-96c5-acf4127d3ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573751327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.1573751327
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.701317108
Short name T1605
Test name
Test status
Simulation time 491485349 ps
CPU time 2.14 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 205460 kb
Host smart-b1d024bf-a3c9-44b5-a17f-dde66f1fc62a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701317108 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_smbus_maxlen.701317108
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.116919892
Short name T574
Test name
Test status
Simulation time 11436063884 ps
CPU time 10.52 seconds
Started Jul 16 05:27:36 PM PDT 24
Finished Jul 16 05:27:47 PM PDT 24
Peak memory 213816 kb
Host smart-bd4344f9-66a5-45f2-9f40-4fd24772e4e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116919892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.116919892
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1665189696
Short name T258
Test name
Test status
Simulation time 33973499552 ps
CPU time 85.12 seconds
Started Jul 16 05:27:34 PM PDT 24
Finished Jul 16 05:29:00 PM PDT 24
Peak memory 546008 kb
Host smart-499ae368-1120-4382-8e27-5f92c9aece96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665189696 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1665189696
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.1952930498
Short name T1460
Test name
Test status
Simulation time 771951361 ps
CPU time 34.46 seconds
Started Jul 16 05:34:22 PM PDT 24
Finished Jul 16 05:34:57 PM PDT 24
Peak memory 213704 kb
Host smart-54abfa83-c452-42b8-8799-440a37eba160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952930498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.1952930498
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.656326860
Short name T334
Test name
Test status
Simulation time 13949273033 ps
CPU time 16.04 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:56 PM PDT 24
Peak memory 205704 kb
Host smart-5fd67b09-150a-4e43-8b4d-44394d137f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656326860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.656326860
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2970590164
Short name T1221
Test name
Test status
Simulation time 4761278437 ps
CPU time 15.02 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:55 PM PDT 24
Peak memory 648796 kb
Host smart-6dce57bf-46a9-4128-ab4b-fbf0950edcd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970590164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2970590164
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2176372327
Short name T1214
Test name
Test status
Simulation time 1382196233 ps
CPU time 6.78 seconds
Started Jul 16 05:27:43 PM PDT 24
Finished Jul 16 05:27:51 PM PDT 24
Peak memory 213748 kb
Host smart-dabc5000-03ca-4613-9625-1ddd17088c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176372327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2176372327
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.3898653625
Short name T1355
Test name
Test status
Simulation time 161372543 ps
CPU time 2.24 seconds
Started Jul 16 05:27:38 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 205512 kb
Host smart-b0451f37-7ff4-4d68-abdb-fdce713791b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898653625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3898653625
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3172448160
Short name T1210
Test name
Test status
Simulation time 18353193 ps
CPU time 0.64 seconds
Started Jul 16 05:27:47 PM PDT 24
Finished Jul 16 05:27:49 PM PDT 24
Peak memory 204660 kb
Host smart-fdcc3621-3e2a-4651-9feb-dd5b4bbfff7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172448160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3172448160
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3252464524
Short name T1157
Test name
Test status
Simulation time 196291671 ps
CPU time 3.01 seconds
Started Jul 16 05:32:41 PM PDT 24
Finished Jul 16 05:32:45 PM PDT 24
Peak memory 221796 kb
Host smart-bb6513cd-d2e3-4402-9b0c-608c921ac6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252464524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3252464524
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2500055261
Short name T384
Test name
Test status
Simulation time 549958963 ps
CPU time 9.58 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:44 PM PDT 24
Peak memory 319188 kb
Host smart-055fc5d8-c9c6-43c3-bc34-7f82b27b1c8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500055261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2500055261
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2151991358
Short name T1200
Test name
Test status
Simulation time 2827115503 ps
CPU time 98.72 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:29:29 PM PDT 24
Peak memory 682064 kb
Host smart-ea288bf8-dea8-4d36-9331-645de81f5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151991358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2151991358
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2904488880
Short name T1490
Test name
Test status
Simulation time 2139980092 ps
CPU time 59.33 seconds
Started Jul 16 05:27:50 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 678644 kb
Host smart-d86d652b-d850-4608-94e7-1b4f377c595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904488880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2904488880
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2140365828
Short name T111
Test name
Test status
Simulation time 511866323 ps
CPU time 1.11 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:39 PM PDT 24
Peak memory 205264 kb
Host smart-f7d2183b-a9a4-40bc-a656-37b218c5be6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140365828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2140365828
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3200454804
Short name T932
Test name
Test status
Simulation time 370516918 ps
CPU time 4.58 seconds
Started Jul 16 05:27:37 PM PDT 24
Finished Jul 16 05:27:43 PM PDT 24
Peak memory 205476 kb
Host smart-0fcbfe67-bdbd-4b19-81c0-0214b51fd359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200454804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3200454804
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2080100
Short name T665
Test name
Test status
Simulation time 30430975525 ps
CPU time 114.25 seconds
Started Jul 16 05:32:35 PM PDT 24
Finished Jul 16 05:34:30 PM PDT 24
Peak memory 1137736 kb
Host smart-22df20be-541b-49cf-9f7a-88b20501624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2080100
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.4172899157
Short name T601
Test name
Test status
Simulation time 184606420 ps
CPU time 2.55 seconds
Started Jul 16 05:27:53 PM PDT 24
Finished Jul 16 05:27:56 PM PDT 24
Peak memory 205468 kb
Host smart-f285a778-bdb1-4217-bd0f-0b161285b30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172899157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.4172899157
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.2051162624
Short name T477
Test name
Test status
Simulation time 38554009 ps
CPU time 0.67 seconds
Started Jul 16 05:27:40 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 205244 kb
Host smart-588375c0-c592-4f65-896a-0f996b02abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051162624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2051162624
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.909049212
Short name T481
Test name
Test status
Simulation time 719769142 ps
CPU time 6.7 seconds
Started Jul 16 05:32:12 PM PDT 24
Finished Jul 16 05:32:20 PM PDT 24
Peak memory 253088 kb
Host smart-dc0cab5c-05af-4334-bb3c-a60ec7653ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909049212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.909049212
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3714025370
Short name T1634
Test name
Test status
Simulation time 5893245867 ps
CPU time 181.36 seconds
Started Jul 16 05:27:47 PM PDT 24
Finished Jul 16 05:30:50 PM PDT 24
Peak memory 1244568 kb
Host smart-eaa0dba1-b254-440e-a6a9-e172ef27482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714025370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3714025370
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3682272451
Short name T1045
Test name
Test status
Simulation time 1876624236 ps
CPU time 72.9 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 314536 kb
Host smart-7e997187-6cca-4eb6-b367-4a88ebb1dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682272451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3682272451
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1308114164
Short name T1278
Test name
Test status
Simulation time 3563557310 ps
CPU time 16.31 seconds
Started Jul 16 05:27:46 PM PDT 24
Finished Jul 16 05:28:03 PM PDT 24
Peak memory 217852 kb
Host smart-44ec1de7-b22f-4739-94c8-626557a0d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308114164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1308114164
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.4265211316
Short name T1343
Test name
Test status
Simulation time 3800009220 ps
CPU time 3.84 seconds
Started Jul 16 05:27:51 PM PDT 24
Finished Jul 16 05:27:56 PM PDT 24
Peak memory 214140 kb
Host smart-ce322b16-63d0-47f2-a4b2-12eed3c85605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265211316 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.4265211316
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4189795694
Short name T83
Test name
Test status
Simulation time 104514977 ps
CPU time 0.84 seconds
Started Jul 16 05:27:47 PM PDT 24
Finished Jul 16 05:27:50 PM PDT 24
Peak memory 205340 kb
Host smart-0da066c2-929e-4f09-9024-85546d8e318f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189795694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4189795694
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1682569412
Short name T1418
Test name
Test status
Simulation time 316846093 ps
CPU time 1.11 seconds
Started Jul 16 05:27:46 PM PDT 24
Finished Jul 16 05:27:49 PM PDT 24
Peak memory 205460 kb
Host smart-08b245a5-06cd-4cfb-a3a4-ccaae0e4da6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682569412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1682569412
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.22231354
Short name T792
Test name
Test status
Simulation time 694542938 ps
CPU time 2.16 seconds
Started Jul 16 05:27:45 PM PDT 24
Finished Jul 16 05:27:48 PM PDT 24
Peak memory 205476 kb
Host smart-9e607a67-89df-4aa9-a644-448b7ac9615a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231354 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.22231354
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.1771384393
Short name T653
Test name
Test status
Simulation time 175249732 ps
CPU time 1.53 seconds
Started Jul 16 05:32:26 PM PDT 24
Finished Jul 16 05:32:29 PM PDT 24
Peak memory 205476 kb
Host smart-5c184e0c-9dbb-452a-9f1c-ab50bb83f7d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771384393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.1771384393
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3783800440
Short name T628
Test name
Test status
Simulation time 2211800136 ps
CPU time 2.86 seconds
Started Jul 16 05:29:15 PM PDT 24
Finished Jul 16 05:29:19 PM PDT 24
Peak memory 217432 kb
Host smart-eedeca6f-b429-498f-aac2-784fa16921b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783800440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3783800440
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1661602740
Short name T1047
Test name
Test status
Simulation time 2450451197 ps
CPU time 3.66 seconds
Started Jul 16 05:27:49 PM PDT 24
Finished Jul 16 05:27:54 PM PDT 24
Peak memory 217436 kb
Host smart-acf146ec-ab85-4d9a-9030-2286c6b80d9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661602740 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1661602740
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3741404755
Short name T632
Test name
Test status
Simulation time 13717416455 ps
CPU time 17.46 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:53 PM PDT 24
Peak memory 430520 kb
Host smart-5b3f07b9-45c1-4238-b923-92cd53538599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741404755 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3741404755
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.4278103521
Short name T1344
Test name
Test status
Simulation time 544413999 ps
CPU time 2.9 seconds
Started Jul 16 05:27:47 PM PDT 24
Finished Jul 16 05:27:52 PM PDT 24
Peak memory 213824 kb
Host smart-e0c758b6-2274-410a-a100-fbdfa5a37f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278103521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.4278103521
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.2119440110
Short name T1230
Test name
Test status
Simulation time 388488940 ps
CPU time 2.3 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 205536 kb
Host smart-9b19db00-1ad0-4a43-a052-cd054df74d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119440110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.2119440110
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.2346324168
Short name T652
Test name
Test status
Simulation time 622877939 ps
CPU time 1.38 seconds
Started Jul 16 05:27:52 PM PDT 24
Finished Jul 16 05:27:54 PM PDT 24
Peak memory 222472 kb
Host smart-59a9584a-7dd7-4581-821e-d6b508ef7f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346324168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_nack_txstretch.2346324168
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.2706692851
Short name T1215
Test name
Test status
Simulation time 744872983 ps
CPU time 5.22 seconds
Started Jul 16 05:27:52 PM PDT 24
Finished Jul 16 05:27:58 PM PDT 24
Peak memory 222044 kb
Host smart-de5d784d-3a2a-4b32-a194-25a434d50eed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706692851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.2706692851
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.3063660818
Short name T960
Test name
Test status
Simulation time 506410595 ps
CPU time 2.37 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 205352 kb
Host smart-d49e5916-052b-4e33-a6a2-c4d0ecdc2abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063660818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.3063660818
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3955584418
Short name T1147
Test name
Test status
Simulation time 1997922339 ps
CPU time 39.58 seconds
Started Jul 16 05:31:20 PM PDT 24
Finished Jul 16 05:32:00 PM PDT 24
Peak memory 213596 kb
Host smart-4ea716f3-6ae9-4718-81bd-83bd9e59def3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955584418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3955584418
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.120641189
Short name T530
Test name
Test status
Simulation time 101744711177 ps
CPU time 35.31 seconds
Started Jul 16 05:27:43 PM PDT 24
Finished Jul 16 05:28:19 PM PDT 24
Peak memory 238428 kb
Host smart-3b649539-919b-45fd-81f1-5c23dfcb1b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120641189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.120641189
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.4233687342
Short name T649
Test name
Test status
Simulation time 1895668020 ps
CPU time 75.41 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:33:46 PM PDT 24
Peak memory 217908 kb
Host smart-2898fbab-fc6d-48ef-a189-2c4e7e426f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233687342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.4233687342
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3130999134
Short name T1336
Test name
Test status
Simulation time 34950201870 ps
CPU time 131.62 seconds
Started Jul 16 05:36:40 PM PDT 24
Finished Jul 16 05:38:53 PM PDT 24
Peak memory 1906212 kb
Host smart-c4ebc98a-9ec6-4d41-98ec-b822783db2ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130999134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3130999134
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3521004900
Short name T776
Test name
Test status
Simulation time 1277622170 ps
CPU time 4.74 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:28:57 PM PDT 24
Peak memory 213792 kb
Host smart-0ea0e3e6-70a5-4bc5-9aef-27fa1c42439b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521004900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3521004900
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.812372483
Short name T643
Test name
Test status
Simulation time 1310351378 ps
CPU time 6.95 seconds
Started Jul 16 05:27:53 PM PDT 24
Finished Jul 16 05:28:00 PM PDT 24
Peak memory 214060 kb
Host smart-257ff7b8-91aa-4287-8bac-c671bf939b03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812372483 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.812372483
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.3715423133
Short name T483
Test name
Test status
Simulation time 958812022 ps
CPU time 11.41 seconds
Started Jul 16 05:27:52 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 221548 kb
Host smart-9cc175ad-adc7-4547-a575-d4d6689794ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715423133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3715423133
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3064573112
Short name T805
Test name
Test status
Simulation time 16872661 ps
CPU time 0.65 seconds
Started Jul 16 05:28:00 PM PDT 24
Finished Jul 16 05:28:01 PM PDT 24
Peak memory 204764 kb
Host smart-c28bff9d-157e-4281-9024-bd18c4ad2781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064573112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3064573112
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3350358748
Short name T1031
Test name
Test status
Simulation time 368545181 ps
CPU time 4.36 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:28:01 PM PDT 24
Peak memory 247996 kb
Host smart-75fc13fd-db9c-46c8-87ae-957e3ec957b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350358748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3350358748
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3309118912
Short name T368
Test name
Test status
Simulation time 785165573 ps
CPU time 8.62 seconds
Started Jul 16 05:28:04 PM PDT 24
Finished Jul 16 05:28:14 PM PDT 24
Peak memory 289772 kb
Host smart-0e8a7d28-6516-403b-9c0e-0933ab2ed5b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309118912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3309118912
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1450659271
Short name T299
Test name
Test status
Simulation time 10889004390 ps
CPU time 172.14 seconds
Started Jul 16 05:27:47 PM PDT 24
Finished Jul 16 05:30:41 PM PDT 24
Peak memory 542948 kb
Host smart-c5a7f718-7b9a-41e7-a3e4-acd1b96054ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450659271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1450659271
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.27397114
Short name T1504
Test name
Test status
Simulation time 7168816720 ps
CPU time 62.37 seconds
Started Jul 16 05:27:51 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 654988 kb
Host smart-26094b9e-5ef4-4f37-8c7b-c194f0eda711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27397114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.27397114
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2584621934
Short name T358
Test name
Test status
Simulation time 104710483 ps
CPU time 1.05 seconds
Started Jul 16 05:32:35 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 205184 kb
Host smart-354491b4-e8a9-445a-961f-0f161f9211f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584621934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2584621934
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.231182249
Short name T981
Test name
Test status
Simulation time 694464891 ps
CPU time 3.55 seconds
Started Jul 16 05:27:44 PM PDT 24
Finished Jul 16 05:27:49 PM PDT 24
Peak memory 228396 kb
Host smart-325f9c55-e881-47f3-8e78-04dfde4709be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231182249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
231182249
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.546035447
Short name T1124
Test name
Test status
Simulation time 5444603039 ps
CPU time 67.31 seconds
Started Jul 16 05:27:46 PM PDT 24
Finished Jul 16 05:28:55 PM PDT 24
Peak memory 858012 kb
Host smart-d6e49d22-68c6-4d5e-97df-cd56922ef321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546035447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.546035447
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.464206300
Short name T1525
Test name
Test status
Simulation time 452872021 ps
CPU time 19.54 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:28:17 PM PDT 24
Peak memory 205472 kb
Host smart-de96b881-104f-49fa-bb66-b5465d158273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464206300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.464206300
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1412243330
Short name T845
Test name
Test status
Simulation time 138134969 ps
CPU time 1.02 seconds
Started Jul 16 05:27:58 PM PDT 24
Finished Jul 16 05:28:00 PM PDT 24
Peak memory 213628 kb
Host smart-d3df4ebe-596e-439c-a00a-b5d43ac3b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412243330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1412243330
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.118470095
Short name T444
Test name
Test status
Simulation time 80374435 ps
CPU time 0.64 seconds
Started Jul 16 05:27:52 PM PDT 24
Finished Jul 16 05:27:54 PM PDT 24
Peak memory 205384 kb
Host smart-f2975abc-ef92-4e1c-9e78-072e475d9cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118470095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.118470095
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3045506502
Short name T777
Test name
Test status
Simulation time 26005715667 ps
CPU time 592.63 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:37:50 PM PDT 24
Peak memory 308212 kb
Host smart-3a6b1933-3a7d-4a4a-aa23-bba25d3b3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045506502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3045506502
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1047591905
Short name T1232
Test name
Test status
Simulation time 156599356 ps
CPU time 1.73 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:37 PM PDT 24
Peak memory 223824 kb
Host smart-eb7207d4-ba33-409a-be89-06cfb04a1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047591905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1047591905
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.434261273
Short name T890
Test name
Test status
Simulation time 6598103374 ps
CPU time 25.39 seconds
Started Jul 16 05:27:46 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 323164 kb
Host smart-02c17b0a-afc8-496a-b757-82d15a57510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434261273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.434261273
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.180506016
Short name T1471
Test name
Test status
Simulation time 573263829 ps
CPU time 26.5 seconds
Started Jul 16 05:27:58 PM PDT 24
Finished Jul 16 05:28:25 PM PDT 24
Peak memory 213780 kb
Host smart-60f19349-8fd3-4287-8004-01db9c40bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180506016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.180506016
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.334213764
Short name T1167
Test name
Test status
Simulation time 2286820700 ps
CPU time 4.57 seconds
Started Jul 16 05:27:59 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 217936 kb
Host smart-087da7dc-3a23-450e-86dd-0d99dd762e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334213764 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.334213764
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.282065665
Short name T1235
Test name
Test status
Simulation time 139321157 ps
CPU time 1.06 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:36 PM PDT 24
Peak memory 205328 kb
Host smart-97e9344e-15ae-4fd1-89a1-8a26af474d44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282065665 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.282065665
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3560600758
Short name T491
Test name
Test status
Simulation time 1735859629 ps
CPU time 1.3 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:27:58 PM PDT 24
Peak memory 205604 kb
Host smart-180ece67-9e16-4750-8322-402ca69324cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560600758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3560600758
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.3984510010
Short name T1617
Test name
Test status
Simulation time 391230033 ps
CPU time 2.15 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:27:59 PM PDT 24
Peak memory 205540 kb
Host smart-3c7f810d-531b-4f34-bf03-0d6f7494cd3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984510010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.3984510010
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.1103172996
Short name T370
Test name
Test status
Simulation time 285443438 ps
CPU time 1.23 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:36 PM PDT 24
Peak memory 205364 kb
Host smart-0826d52f-1479-443d-9f7a-a861151d25c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103172996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.1103172996
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2027009341
Short name T82
Test name
Test status
Simulation time 193734508 ps
CPU time 1.45 seconds
Started Jul 16 05:27:57 PM PDT 24
Finished Jul 16 05:27:59 PM PDT 24
Peak memory 213724 kb
Host smart-0340cd92-3fc1-4eb7-a530-a363a465a2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027009341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2027009341
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1415618269
Short name T84
Test name
Test status
Simulation time 3371067779 ps
CPU time 8.52 seconds
Started Jul 16 05:28:55 PM PDT 24
Finished Jul 16 05:29:10 PM PDT 24
Peak memory 220848 kb
Host smart-3a063db6-f318-4807-b0f5-23a09f368dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415618269 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1415618269
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.941476447
Short name T680
Test name
Test status
Simulation time 13641144945 ps
CPU time 249.18 seconds
Started Jul 16 05:31:39 PM PDT 24
Finished Jul 16 05:35:49 PM PDT 24
Peak memory 3291916 kb
Host smart-0fe9b559-9661-4c65-b587-0323c7ee02aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941476447 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.941476447
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.103771897
Short name T1506
Test name
Test status
Simulation time 1857348420 ps
CPU time 2.33 seconds
Started Jul 16 05:28:00 PM PDT 24
Finished Jul 16 05:28:03 PM PDT 24
Peak memory 213820 kb
Host smart-8efb250e-0acc-4c29-9f38-48fb805c5852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103771897 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_nack_acqfull.103771897
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.1037171619
Short name T1453
Test name
Test status
Simulation time 2704135681 ps
CPU time 2.48 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:34:30 PM PDT 24
Peak memory 205668 kb
Host smart-8461e26f-645f-4ebd-a7b6-ed3f58c80bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037171619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1037171619
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_txstretch.507932170
Short name T1241
Test name
Test status
Simulation time 164640600 ps
CPU time 1.49 seconds
Started Jul 16 05:36:36 PM PDT 24
Finished Jul 16 05:36:39 PM PDT 24
Peak memory 222116 kb
Host smart-ca4c2db2-0e20-4ffe-ab4c-2dcb811c4add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507932170 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_nack_txstretch.507932170
Directory /workspace/44.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/44.i2c_target_perf.2436467242
Short name T1579
Test name
Test status
Simulation time 1448530854 ps
CPU time 5.25 seconds
Started Jul 16 05:32:12 PM PDT 24
Finished Jul 16 05:32:18 PM PDT 24
Peak memory 221972 kb
Host smart-5bd87176-88e6-4e5e-bd83-3e113a922e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436467242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.2436467242
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.2141532423
Short name T1517
Test name
Test status
Simulation time 2653084188 ps
CPU time 2.31 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:27:59 PM PDT 24
Peak memory 205436 kb
Host smart-50aedaa9-bd75-4048-974c-853c8b6ab9f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141532423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.2141532423
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2362510172
Short name T578
Test name
Test status
Simulation time 3287768887 ps
CPU time 13.2 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:32:49 PM PDT 24
Peak memory 213736 kb
Host smart-13242dd7-207c-4b2a-86d7-b48323474054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362510172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2362510172
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.1113958234
Short name T1067
Test name
Test status
Simulation time 79614469897 ps
CPU time 154.92 seconds
Started Jul 16 05:27:59 PM PDT 24
Finished Jul 16 05:30:34 PM PDT 24
Peak memory 1032548 kb
Host smart-e714ebd2-01b1-40a0-acdb-473130fd691f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113958234 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.1113958234
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.126121221
Short name T739
Test name
Test status
Simulation time 370424666 ps
CPU time 4.54 seconds
Started Jul 16 05:27:59 PM PDT 24
Finished Jul 16 05:28:04 PM PDT 24
Peak memory 205524 kb
Host smart-34b7f9bf-4069-46e9-a1b9-0ef6c08c6a86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126121221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.126121221
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3951352305
Short name T1092
Test name
Test status
Simulation time 67767254982 ps
CPU time 952.92 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:52:28 PM PDT 24
Peak memory 6043300 kb
Host smart-813b07f1-402f-4238-97ff-c5a84fcd3338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951352305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3951352305
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3713096662
Short name T68
Test name
Test status
Simulation time 1444984250 ps
CPU time 1.63 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:27:58 PM PDT 24
Peak memory 205432 kb
Host smart-b196b8aa-41bc-47d7-84db-07c0aed9b449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713096662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3713096662
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1989324663
Short name T316
Test name
Test status
Simulation time 5435446689 ps
CPU time 6.92 seconds
Started Jul 16 05:36:40 PM PDT 24
Finished Jul 16 05:36:49 PM PDT 24
Peak memory 232028 kb
Host smart-c3594149-a9b7-4a56-b18e-33e6a2c17390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989324663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1989324663
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.1291569036
Short name T1505
Test name
Test status
Simulation time 151276669 ps
CPU time 3.44 seconds
Started Jul 16 05:27:55 PM PDT 24
Finished Jul 16 05:27:59 PM PDT 24
Peak memory 206620 kb
Host smart-2964666d-b9f4-4ff7-a6fe-505d4d3ffef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291569036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.1291569036
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3956058265
Short name T170
Test name
Test status
Simulation time 25274476 ps
CPU time 0.66 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:11 PM PDT 24
Peak memory 204776 kb
Host smart-c86c5a9d-5272-471d-9d25-bf528013884c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956058265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3956058265
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1857104751
Short name T1197
Test name
Test status
Simulation time 146465119 ps
CPU time 1.25 seconds
Started Jul 16 05:34:26 PM PDT 24
Finished Jul 16 05:34:28 PM PDT 24
Peak memory 213752 kb
Host smart-e7dc3090-5a9a-4f1d-8407-2f86d674a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857104751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1857104751
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3004255668
Short name T716
Test name
Test status
Simulation time 365358275 ps
CPU time 8.5 seconds
Started Jul 16 05:27:55 PM PDT 24
Finished Jul 16 05:28:05 PM PDT 24
Peak memory 286420 kb
Host smart-4c4938e2-5377-486c-83fe-ef9d38169900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004255668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3004255668
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1470680589
Short name T1125
Test name
Test status
Simulation time 15706096241 ps
CPU time 246.32 seconds
Started Jul 16 05:28:06 PM PDT 24
Finished Jul 16 05:32:13 PM PDT 24
Peak memory 709348 kb
Host smart-1f47cd64-27d2-4925-9dea-5bad3898bd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470680589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1470680589
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3262662499
Short name T1305
Test name
Test status
Simulation time 7572648131 ps
CPU time 55.28 seconds
Started Jul 16 05:28:06 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 582840 kb
Host smart-786d0acb-e2a7-4057-926e-ab8f0b2868d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262662499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3262662499
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1919810245
Short name T226
Test name
Test status
Simulation time 475068519 ps
CPU time 1.04 seconds
Started Jul 16 05:27:55 PM PDT 24
Finished Jul 16 05:27:57 PM PDT 24
Peak memory 205160 kb
Host smart-ad69f835-e21c-434d-8dc9-cb689daeb107
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919810245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1919810245
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3618949037
Short name T1016
Test name
Test status
Simulation time 826118660 ps
CPU time 5.15 seconds
Started Jul 16 05:27:59 PM PDT 24
Finished Jul 16 05:28:05 PM PDT 24
Peak memory 245716 kb
Host smart-8cf3a2c3-4d4e-4984-9811-4946482ad53b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618949037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3618949037
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.976249898
Short name T100
Test name
Test status
Simulation time 3886466519 ps
CPU time 88.21 seconds
Started Jul 16 05:27:58 PM PDT 24
Finished Jul 16 05:29:27 PM PDT 24
Peak memory 1100432 kb
Host smart-9da8fb1a-5009-42f4-8253-50d3c3e84d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976249898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.976249898
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1875024961
Short name T242
Test name
Test status
Simulation time 2193280802 ps
CPU time 24.07 seconds
Started Jul 16 05:28:08 PM PDT 24
Finished Jul 16 05:28:32 PM PDT 24
Peak memory 205568 kb
Host smart-4075bc5e-323a-47fd-84a7-e9f90e77e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875024961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1875024961
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3461791440
Short name T879
Test name
Test status
Simulation time 370800369 ps
CPU time 3.05 seconds
Started Jul 16 05:36:35 PM PDT 24
Finished Jul 16 05:36:39 PM PDT 24
Peak memory 205364 kb
Host smart-8db7d45d-1ebc-4b26-a3bb-4f60fec15b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461791440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3461791440
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3688475051
Short name T545
Test name
Test status
Simulation time 37979938 ps
CPU time 0.65 seconds
Started Jul 16 05:27:56 PM PDT 24
Finished Jul 16 05:27:57 PM PDT 24
Peak memory 205132 kb
Host smart-11de85c0-ca90-4178-ab99-91af35ef986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688475051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3688475051
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2178639269
Short name T1353
Test name
Test status
Simulation time 7532298386 ps
CPU time 148.47 seconds
Started Jul 16 05:28:12 PM PDT 24
Finished Jul 16 05:30:41 PM PDT 24
Peak memory 803716 kb
Host smart-eb08f260-b1ba-46e1-a84c-4769307cf204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178639269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2178639269
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.3978561631
Short name T1543
Test name
Test status
Simulation time 2876585206 ps
CPU time 14.06 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 340612 kb
Host smart-693c99fa-6ceb-4712-b29e-a36195cd705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978561631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.3978561631
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1732049336
Short name T651
Test name
Test status
Simulation time 7051367786 ps
CPU time 31.17 seconds
Started Jul 16 05:32:12 PM PDT 24
Finished Jul 16 05:32:44 PM PDT 24
Peak memory 414488 kb
Host smart-63ddb7a8-d3dc-4b76-a972-6cb3894f16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732049336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1732049336
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2074680142
Short name T1276
Test name
Test status
Simulation time 1842506545 ps
CPU time 12.85 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:23 PM PDT 24
Peak memory 221852 kb
Host smart-67e5538b-2065-4aae-87a8-1e1d33f7dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074680142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2074680142
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2630616684
Short name T60
Test name
Test status
Simulation time 1344841278 ps
CPU time 6.54 seconds
Started Jul 16 05:28:10 PM PDT 24
Finished Jul 16 05:28:18 PM PDT 24
Peak memory 213796 kb
Host smart-52d67944-5ae1-4147-8fdd-d987708f01d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630616684 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2630616684
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1362802138
Short name T820
Test name
Test status
Simulation time 660283817 ps
CPU time 1.43 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 205628 kb
Host smart-3c99c792-d037-4cf0-8ec3-49de1e832a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362802138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1362802138
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.3006854044
Short name T623
Test name
Test status
Simulation time 468327142 ps
CPU time 2.4 seconds
Started Jul 16 05:28:08 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 205584 kb
Host smart-d6db10bf-0dad-4495-9e9c-258993c0f29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006854044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.3006854044
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.2883061834
Short name T1032
Test name
Test status
Simulation time 131442293 ps
CPU time 1.24 seconds
Started Jul 16 05:28:10 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 205400 kb
Host smart-8c17708d-e880-464e-9fd5-bd8743fdbe50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883061834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.2883061834
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.777686699
Short name T1178
Test name
Test status
Simulation time 1931293329 ps
CPU time 1.83 seconds
Started Jul 16 05:28:13 PM PDT 24
Finished Jul 16 05:28:15 PM PDT 24
Peak memory 213772 kb
Host smart-ab950e30-b017-4ada-8497-5d9244a81e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777686699 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.777686699
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.4121792801
Short name T786
Test name
Test status
Simulation time 780963747 ps
CPU time 4.86 seconds
Started Jul 16 05:28:12 PM PDT 24
Finished Jul 16 05:28:17 PM PDT 24
Peak memory 222000 kb
Host smart-bbe9e92f-a495-4100-a940-4a12a1cc4bc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121792801 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.4121792801
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3559335243
Short name T440
Test name
Test status
Simulation time 23363028806 ps
CPU time 58.66 seconds
Started Jul 16 05:28:08 PM PDT 24
Finished Jul 16 05:29:08 PM PDT 24
Peak memory 866220 kb
Host smart-80c8b9fb-5d7d-4ab6-9e7e-40366bda90cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559335243 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3559335243
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.2088916216
Short name T62
Test name
Test status
Simulation time 548992440 ps
CPU time 2.68 seconds
Started Jul 16 05:28:07 PM PDT 24
Finished Jul 16 05:28:10 PM PDT 24
Peak memory 213796 kb
Host smart-20177033-0d2e-44f5-936f-51b13880a35d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088916216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.2088916216
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.494902925
Short name T426
Test name
Test status
Simulation time 497225641 ps
CPU time 2.55 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 205472 kb
Host smart-c0e6ab61-d8ab-4d14-b7b6-335627fe94b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494902925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.494902925
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_txstretch.38683863
Short name T562
Test name
Test status
Simulation time 145157095 ps
CPU time 1.36 seconds
Started Jul 16 05:28:12 PM PDT 24
Finished Jul 16 05:28:14 PM PDT 24
Peak memory 222260 kb
Host smart-6c66519f-8f48-4b2e-979b-4514e9f0bc26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38683863 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_txstretch.38683863
Directory /workspace/45.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/45.i2c_target_perf.2400107058
Short name T1349
Test name
Test status
Simulation time 1560888935 ps
CPU time 3.46 seconds
Started Jul 16 05:32:36 PM PDT 24
Finished Jul 16 05:32:40 PM PDT 24
Peak memory 209608 kb
Host smart-99d19c22-029d-4462-bdd7-844fae461afd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400107058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.2400107058
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.3423328202
Short name T552
Test name
Test status
Simulation time 2673987008 ps
CPU time 2.31 seconds
Started Jul 16 05:28:10 PM PDT 24
Finished Jul 16 05:28:13 PM PDT 24
Peak memory 205468 kb
Host smart-a3cebe92-47ce-4f5e-91cc-1915a837a7eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423328202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.3423328202
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.153731846
Short name T958
Test name
Test status
Simulation time 2476536414 ps
CPU time 9.01 seconds
Started Jul 16 05:28:13 PM PDT 24
Finished Jul 16 05:28:23 PM PDT 24
Peak memory 213836 kb
Host smart-b3709363-768f-4e56-bab4-8c96179b3dc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153731846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.153731846
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.2620516743
Short name T1425
Test name
Test status
Simulation time 32908328271 ps
CPU time 1422.35 seconds
Started Jul 16 05:32:45 PM PDT 24
Finished Jul 16 05:56:27 PM PDT 24
Peak memory 6286228 kb
Host smart-cd97b5a8-5d34-458f-8cfb-2013ada437a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620516743 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.2620516743
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.4216423174
Short name T341
Test name
Test status
Simulation time 870632197 ps
CPU time 16.59 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:26 PM PDT 24
Peak memory 208852 kb
Host smart-400e9631-6d40-4466-a36f-017720f0ab89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216423174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.4216423174
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.4263471266
Short name T556
Test name
Test status
Simulation time 60226916553 ps
CPU time 37.47 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 620776 kb
Host smart-31870f52-7993-47c5-8523-514b45df598b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263471266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.4263471266
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2915669610
Short name T136
Test name
Test status
Simulation time 2018001469 ps
CPU time 52.63 seconds
Started Jul 16 05:36:36 PM PDT 24
Finished Jul 16 05:37:30 PM PDT 24
Peak memory 571608 kb
Host smart-5c344963-7ec1-4d7b-937b-7b4a947fa19c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915669610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2915669610
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.4053966056
Short name T1370
Test name
Test status
Simulation time 1375215293 ps
CPU time 6.81 seconds
Started Jul 16 05:28:07 PM PDT 24
Finished Jul 16 05:28:15 PM PDT 24
Peak memory 219520 kb
Host smart-17159016-02c0-4d91-b8ba-7547b09c5b76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053966056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.4053966056
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2317678460
Short name T891
Test name
Test status
Simulation time 156127634 ps
CPU time 3.26 seconds
Started Jul 16 05:28:08 PM PDT 24
Finished Jul 16 05:28:12 PM PDT 24
Peak memory 205696 kb
Host smart-2fec4ce3-d240-4cec-a46b-5cf052ab8c12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317678460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2317678460
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1353841093
Short name T169
Test name
Test status
Simulation time 46468201 ps
CPU time 0.64 seconds
Started Jul 16 05:28:23 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 204792 kb
Host smart-d3b9fcf9-54db-41a2-b350-e7f02c0c83d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353841093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1353841093
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2812506439
Short name T1411
Test name
Test status
Simulation time 268482885 ps
CPU time 1.63 seconds
Started Jul 16 05:28:06 PM PDT 24
Finished Jul 16 05:28:08 PM PDT 24
Peak memory 213708 kb
Host smart-0baf4b70-bd9d-4b7b-a7d8-1bb23aae32fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812506439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2812506439
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2749319652
Short name T919
Test name
Test status
Simulation time 530281355 ps
CPU time 5.57 seconds
Started Jul 16 05:28:08 PM PDT 24
Finished Jul 16 05:28:15 PM PDT 24
Peak memory 253256 kb
Host smart-49ddba43-96a5-4189-8e1d-bd65e6d913f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749319652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2749319652
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3400120186
Short name T353
Test name
Test status
Simulation time 4471229697 ps
CPU time 209.11 seconds
Started Jul 16 05:28:05 PM PDT 24
Finished Jul 16 05:31:35 PM PDT 24
Peak memory 516860 kb
Host smart-dfffe8ee-fd86-4d26-81e7-7259e7bc1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400120186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3400120186
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2655376560
Short name T865
Test name
Test status
Simulation time 19696408272 ps
CPU time 200 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:31:31 PM PDT 24
Peak memory 846620 kb
Host smart-ac0924c6-bb1e-4de5-938c-41c590648962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655376560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2655376560
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.310042389
Short name T1549
Test name
Test status
Simulation time 334549024 ps
CPU time 1.15 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:11 PM PDT 24
Peak memory 205204 kb
Host smart-fb14a7df-886d-4798-9946-2259b0487237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310042389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.310042389
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1310982518
Short name T817
Test name
Test status
Simulation time 459841566 ps
CPU time 4.21 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:14 PM PDT 24
Peak memory 230524 kb
Host smart-46047e4f-51a2-4b23-97e3-fd5bc52fda93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310982518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1310982518
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4201995580
Short name T1302
Test name
Test status
Simulation time 4173424580 ps
CPU time 122.01 seconds
Started Jul 16 05:28:11 PM PDT 24
Finished Jul 16 05:30:14 PM PDT 24
Peak memory 1234828 kb
Host smart-0df19866-4256-4980-8a44-87a23327bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201995580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4201995580
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1019538470
Short name T548
Test name
Test status
Simulation time 625111202 ps
CPU time 6.82 seconds
Started Jul 16 05:32:41 PM PDT 24
Finished Jul 16 05:32:48 PM PDT 24
Peak memory 205544 kb
Host smart-2b8b331f-0e6a-424e-aacd-70943b3d6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019538470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1019538470
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.23246906
Short name T602
Test name
Test status
Simulation time 26343241 ps
CPU time 0.7 seconds
Started Jul 16 05:28:13 PM PDT 24
Finished Jul 16 05:28:15 PM PDT 24
Peak memory 205184 kb
Host smart-80dacb8d-857e-4d11-b98e-94cb96c1c1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23246906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.23246906
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.791211149
Short name T1608
Test name
Test status
Simulation time 52099320680 ps
CPU time 423.48 seconds
Started Jul 16 05:28:07 PM PDT 24
Finished Jul 16 05:35:11 PM PDT 24
Peak memory 1688060 kb
Host smart-e46a62e0-d5be-4ded-bfa9-c4c31ecf3cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791211149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.791211149
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3828592050
Short name T155
Test name
Test status
Simulation time 250422685 ps
CPU time 2.66 seconds
Started Jul 16 05:28:06 PM PDT 24
Finished Jul 16 05:28:09 PM PDT 24
Peak memory 220296 kb
Host smart-7b59ce00-39d2-4a78-9bf0-d09587426fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828592050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3828592050
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2957294010
Short name T1400
Test name
Test status
Simulation time 1649572417 ps
CPU time 71.79 seconds
Started Jul 16 05:28:13 PM PDT 24
Finished Jul 16 05:29:25 PM PDT 24
Peak memory 319468 kb
Host smart-72273775-f09b-4ec6-9f70-f1856b08ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957294010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2957294010
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2247012605
Short name T1666
Test name
Test status
Simulation time 805605729 ps
CPU time 35.2 seconds
Started Jul 16 05:28:09 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 213728 kb
Host smart-f0992d7a-370e-4c2b-8583-b9af6e8e594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247012605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2247012605
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1178696841
Short name T793
Test name
Test status
Simulation time 3823725351 ps
CPU time 5.33 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:41 PM PDT 24
Peak memory 221848 kb
Host smart-90bc44c7-1993-425d-ac3b-790bff182c2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178696841 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1178696841
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3073704469
Short name T151
Test name
Test status
Simulation time 331681660 ps
CPU time 1.33 seconds
Started Jul 16 05:28:22 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 205564 kb
Host smart-47fd50b3-94f9-45fa-a131-f4d4d7dbafc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073704469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3073704469
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1860237640
Short name T1391
Test name
Test status
Simulation time 379051008 ps
CPU time 1.01 seconds
Started Jul 16 05:28:25 PM PDT 24
Finished Jul 16 05:28:26 PM PDT 24
Peak memory 205416 kb
Host smart-7fcaee92-0eed-4d81-a800-c2743bacf781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860237640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1860237640
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.799290908
Short name T1034
Test name
Test status
Simulation time 1348837816 ps
CPU time 2.09 seconds
Started Jul 16 05:32:26 PM PDT 24
Finished Jul 16 05:32:29 PM PDT 24
Peak memory 205512 kb
Host smart-77939a87-636e-433d-be31-75206819176b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799290908 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.799290908
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.686251788
Short name T1224
Test name
Test status
Simulation time 153910940 ps
CPU time 1.36 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:37 PM PDT 24
Peak memory 205436 kb
Host smart-26e980e8-223c-4baa-a2ad-1ca8eb393167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686251788 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.686251788
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3820987682
Short name T1150
Test name
Test status
Simulation time 3617192931 ps
CPU time 5.38 seconds
Started Jul 16 05:28:24 PM PDT 24
Finished Jul 16 05:28:30 PM PDT 24
Peak memory 217752 kb
Host smart-7da4b8e3-bf24-4875-be61-5db972bc0f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820987682 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3820987682
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2479352478
Short name T115
Test name
Test status
Simulation time 28683905471 ps
CPU time 90.2 seconds
Started Jul 16 05:28:25 PM PDT 24
Finished Jul 16 05:29:55 PM PDT 24
Peak memory 1555400 kb
Host smart-14ef9882-b39f-4e3a-b6f5-a4ed1ed3e27f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479352478 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2479352478
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.1979111872
Short name T892
Test name
Test status
Simulation time 1112502863 ps
CPU time 2.65 seconds
Started Jul 16 05:36:35 PM PDT 24
Finished Jul 16 05:36:39 PM PDT 24
Peak memory 213812 kb
Host smart-f42e1cf2-cba6-4763-a112-c790275cd55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979111872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.1979111872
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1551964555
Short name T1598
Test name
Test status
Simulation time 1968966441 ps
CPU time 2.49 seconds
Started Jul 16 05:28:21 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 205540 kb
Host smart-33f4b71b-a617-44de-ba0f-4787be9e1223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551964555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1551964555
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.2154759389
Short name T402
Test name
Test status
Simulation time 3583887253 ps
CPU time 3.76 seconds
Started Jul 16 05:28:25 PM PDT 24
Finished Jul 16 05:28:29 PM PDT 24
Peak memory 221584 kb
Host smart-3edf4b33-6e97-4bb5-aebf-b226bc006610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154759389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.2154759389
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.2790100387
Short name T488
Test name
Test status
Simulation time 491905925 ps
CPU time 2.34 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:34:30 PM PDT 24
Peak memory 205272 kb
Host smart-f37e6e35-a486-497d-9e80-18d5ed5af1f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790100387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.2790100387
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2186640342
Short name T356
Test name
Test status
Simulation time 5529344244 ps
CPU time 22.63 seconds
Started Jul 16 05:28:07 PM PDT 24
Finished Jul 16 05:28:30 PM PDT 24
Peak memory 213880 kb
Host smart-2b81da76-6bdc-4a0c-8a2f-c54b17fbd29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186640342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2186640342
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.4177703851
Short name T1393
Test name
Test status
Simulation time 57900191533 ps
CPU time 3321.76 seconds
Started Jul 16 05:28:21 PM PDT 24
Finished Jul 16 06:23:44 PM PDT 24
Peak memory 11274284 kb
Host smart-6719ec80-d75e-4593-bb1f-dff4f68f68f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177703851 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.4177703851
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2748915679
Short name T1326
Test name
Test status
Simulation time 279655981 ps
CPU time 4.32 seconds
Started Jul 16 05:32:36 PM PDT 24
Finished Jul 16 05:32:41 PM PDT 24
Peak memory 205392 kb
Host smart-81204b09-e704-4f22-95f8-a02e3f520488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748915679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2748915679
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3531297654
Short name T1439
Test name
Test status
Simulation time 7481331583 ps
CPU time 7.38 seconds
Started Jul 16 05:28:10 PM PDT 24
Finished Jul 16 05:28:18 PM PDT 24
Peak memory 205432 kb
Host smart-f2760785-da2d-428e-893c-c831fa9e3558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531297654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3531297654
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.193324799
Short name T274
Test name
Test status
Simulation time 2966490234 ps
CPU time 4.9 seconds
Started Jul 16 05:28:10 PM PDT 24
Finished Jul 16 05:28:16 PM PDT 24
Peak memory 252408 kb
Host smart-287b3fbf-2c47-4ecc-a60a-b2b8bd4a3189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193324799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.193324799
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3671038645
Short name T1710
Test name
Test status
Simulation time 4996787887 ps
CPU time 6.68 seconds
Started Jul 16 05:28:22 PM PDT 24
Finished Jul 16 05:28:30 PM PDT 24
Peak memory 213952 kb
Host smart-627c1bef-8232-41d1-9ed4-1d8fea520f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671038645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3671038645
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2222698187
Short name T1733
Test name
Test status
Simulation time 17962266 ps
CPU time 0.64 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:04 PM PDT 24
Peak memory 204388 kb
Host smart-d7f81701-b06b-4170-a2d6-8a4b5ee0f497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222698187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2222698187
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.260944087
Short name T826
Test name
Test status
Simulation time 363400597 ps
CPU time 1.65 seconds
Started Jul 16 05:28:19 PM PDT 24
Finished Jul 16 05:28:21 PM PDT 24
Peak memory 213708 kb
Host smart-eea77a04-8006-42e9-9928-92e6080958fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260944087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.260944087
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3984333742
Short name T1321
Test name
Test status
Simulation time 1492363645 ps
CPU time 19.17 seconds
Started Jul 16 05:32:10 PM PDT 24
Finished Jul 16 05:32:30 PM PDT 24
Peak memory 284400 kb
Host smart-2265e114-a680-4592-bc65-41e3f83c7435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984333742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3984333742
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.865360489
Short name T1181
Test name
Test status
Simulation time 3255342377 ps
CPU time 104.95 seconds
Started Jul 16 05:28:21 PM PDT 24
Finished Jul 16 05:30:07 PM PDT 24
Peak memory 640784 kb
Host smart-492c6e03-f89c-442d-9847-3299993e2111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865360489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.865360489
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.617972147
Short name T834
Test name
Test status
Simulation time 3186473049 ps
CPU time 40.12 seconds
Started Jul 16 05:28:22 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 508940 kb
Host smart-0d09d4e9-9fd9-41ef-8122-bffd64bc9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617972147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.617972147
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3081851016
Short name T1360
Test name
Test status
Simulation time 191363178 ps
CPU time 1.11 seconds
Started Jul 16 05:28:23 PM PDT 24
Finished Jul 16 05:28:25 PM PDT 24
Peak memory 205328 kb
Host smart-936920af-6719-4f00-9a1c-06684a1aa3d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081851016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3081851016
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2729067732
Short name T849
Test name
Test status
Simulation time 287160135 ps
CPU time 2.93 seconds
Started Jul 16 05:28:30 PM PDT 24
Finished Jul 16 05:28:33 PM PDT 24
Peak memory 205376 kb
Host smart-3789a301-2736-48cc-90cb-64b3ba90953f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729067732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2729067732
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1974599726
Short name T1218
Test name
Test status
Simulation time 8586522086 ps
CPU time 96.85 seconds
Started Jul 16 05:28:23 PM PDT 24
Finished Jul 16 05:30:00 PM PDT 24
Peak memory 1222816 kb
Host smart-579bad45-c306-4301-9f4e-7c1cadc4ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974599726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1974599726
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.939931270
Short name T1594
Test name
Test status
Simulation time 1006580680 ps
CPU time 8.09 seconds
Started Jul 16 05:28:37 PM PDT 24
Finished Jul 16 05:28:46 PM PDT 24
Peak memory 205444 kb
Host smart-70db1349-6705-4720-930f-c86bdadc7c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939931270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.939931270
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.4149709194
Short name T1373
Test name
Test status
Simulation time 27001024 ps
CPU time 0.63 seconds
Started Jul 16 05:32:25 PM PDT 24
Finished Jul 16 05:32:27 PM PDT 24
Peak memory 205096 kb
Host smart-3184aaf3-57e4-4a68-a290-6da5f690e178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149709194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.4149709194
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.4016655965
Short name T617
Test name
Test status
Simulation time 2543847716 ps
CPU time 31.62 seconds
Started Jul 16 05:32:59 PM PDT 24
Finished Jul 16 05:33:31 PM PDT 24
Peak memory 493948 kb
Host smart-0701deab-6bf0-46dd-ae54-41fca702648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016655965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.4016655965
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3522512305
Short name T1026
Test name
Test status
Simulation time 225530815 ps
CPU time 8.91 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:39 PM PDT 24
Peak memory 205292 kb
Host smart-d895c1df-bb5b-4f97-9284-87aec1575b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522512305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3522512305
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2321485713
Short name T1108
Test name
Test status
Simulation time 3405517021 ps
CPU time 17.72 seconds
Started Jul 16 05:28:22 PM PDT 24
Finished Jul 16 05:28:40 PM PDT 24
Peak memory 315976 kb
Host smart-6aca8c76-4071-4c82-92f2-ce5b5649aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321485713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2321485713
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3206106902
Short name T728
Test name
Test status
Simulation time 692405657 ps
CPU time 10.54 seconds
Started Jul 16 05:28:26 PM PDT 24
Finished Jul 16 05:28:37 PM PDT 24
Peak memory 229956 kb
Host smart-037fca3d-4405-49c5-a615-1100f12034a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206106902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3206106902
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3232379753
Short name T1562
Test name
Test status
Simulation time 705257747 ps
CPU time 4.03 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:39 PM PDT 24
Peak memory 218640 kb
Host smart-a8f89162-2860-4b11-98fe-0fe96ce5e16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232379753 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3232379753
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3307613334
Short name T415
Test name
Test status
Simulation time 177538496 ps
CPU time 1.01 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 205412 kb
Host smart-0f0cf4f4-bae8-4248-946a-9a6ef5ddcfc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307613334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3307613334
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2772672321
Short name T800
Test name
Test status
Simulation time 364568791 ps
CPU time 0.97 seconds
Started Jul 16 05:36:50 PM PDT 24
Finished Jul 16 05:36:52 PM PDT 24
Peak memory 205360 kb
Host smart-71032e67-038e-448f-a093-b33d64583856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772672321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2772672321
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3224846838
Short name T640
Test name
Test status
Simulation time 485689930 ps
CPU time 2.54 seconds
Started Jul 16 05:32:10 PM PDT 24
Finished Jul 16 05:32:14 PM PDT 24
Peak memory 205472 kb
Host smart-71050524-05de-4517-aaa1-0136495efade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224846838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3224846838
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.3330763397
Short name T1565
Test name
Test status
Simulation time 311897512 ps
CPU time 0.94 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:31 PM PDT 24
Peak memory 205440 kb
Host smart-f6ef95c2-1f2b-4974-9593-34b9ca6e7b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330763397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.3330763397
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1450379545
Short name T928
Test name
Test status
Simulation time 728514128 ps
CPU time 1.51 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:38 PM PDT 24
Peak memory 205700 kb
Host smart-3104d345-e95c-45c9-bc55-29104e58652f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450379545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1450379545
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2377051003
Short name T880
Test name
Test status
Simulation time 1470073045 ps
CPU time 8.94 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:13 PM PDT 24
Peak memory 213676 kb
Host smart-eab25e39-b2c4-4380-9783-51270620c0e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377051003 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2377051003
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.159755141
Short name T577
Test name
Test status
Simulation time 10362191822 ps
CPU time 152.96 seconds
Started Jul 16 05:28:34 PM PDT 24
Finished Jul 16 05:31:07 PM PDT 24
Peak memory 2596148 kb
Host smart-02360d84-bdfc-46be-91cf-c0e0a69d69e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159755141 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.159755141
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.2533621314
Short name T957
Test name
Test status
Simulation time 934464711 ps
CPU time 2.75 seconds
Started Jul 16 05:28:39 PM PDT 24
Finished Jul 16 05:28:42 PM PDT 24
Peak memory 214072 kb
Host smart-03fcd7af-0c36-4595-a1c2-0a5cecce496e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533621314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.2533621314
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.3847279370
Short name T521
Test name
Test status
Simulation time 544862692 ps
CPU time 2.65 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:28:47 PM PDT 24
Peak memory 205656 kb
Host smart-6d75a802-3ac1-473b-a67b-e6fb13e7bdb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847279370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.3847279370
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3204984961
Short name T49
Test name
Test status
Simulation time 261163304 ps
CPU time 1.59 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:28:46 PM PDT 24
Peak memory 222216 kb
Host smart-65f110f7-4509-4a90-be41-feead862db02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204984961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3204984961
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.3725861420
Short name T359
Test name
Test status
Simulation time 498956357 ps
CPU time 3.67 seconds
Started Jul 16 05:31:30 PM PDT 24
Finished Jul 16 05:31:35 PM PDT 24
Peak memory 221976 kb
Host smart-46f3b042-e621-40d3-8afc-c5f3422db282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725861420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.3725861420
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.565762175
Short name T1625
Test name
Test status
Simulation time 461384466 ps
CPU time 2.27 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:36 PM PDT 24
Peak memory 205468 kb
Host smart-c6515b00-8417-44cd-8c14-2ba24214379b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565762175 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_smbus_maxlen.565762175
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1310239049
Short name T1310
Test name
Test status
Simulation time 3061953515 ps
CPU time 45.84 seconds
Started Jul 16 05:33:00 PM PDT 24
Finished Jul 16 05:33:47 PM PDT 24
Peak memory 213920 kb
Host smart-43419348-c8dd-4496-a697-79058b7a5c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310239049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1310239049
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.1139467301
Short name T1494
Test name
Test status
Simulation time 16233778552 ps
CPU time 297.76 seconds
Started Jul 16 05:28:39 PM PDT 24
Finished Jul 16 05:33:37 PM PDT 24
Peak memory 2980376 kb
Host smart-3348f869-0797-4496-b2f9-6d2de56414c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139467301 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.1139467301
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2159334029
Short name T1500
Test name
Test status
Simulation time 1272034081 ps
CPU time 52.23 seconds
Started Jul 16 05:28:25 PM PDT 24
Finished Jul 16 05:29:18 PM PDT 24
Peak memory 213960 kb
Host smart-ead7ad0d-b130-4373-b81c-70e786354e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159334029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2159334029
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2279072908
Short name T487
Test name
Test status
Simulation time 41269271315 ps
CPU time 66.18 seconds
Started Jul 16 05:28:23 PM PDT 24
Finished Jul 16 05:29:30 PM PDT 24
Peak memory 1131576 kb
Host smart-05c9453a-75f0-4898-8025-3799aae0fda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279072908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2279072908
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1304163663
Short name T1013
Test name
Test status
Simulation time 2397690721 ps
CPU time 7.11 seconds
Started Jul 16 05:28:30 PM PDT 24
Finished Jul 16 05:28:37 PM PDT 24
Peak memory 277724 kb
Host smart-46603336-2bba-45ec-b688-e1e670561355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304163663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1304163663
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.75360899
Short name T587
Test name
Test status
Simulation time 11906093936 ps
CPU time 6.94 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:55 PM PDT 24
Peak memory 221984 kb
Host smart-eb7223e5-7c6e-4a72-9fec-6e57440f5d0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75360899 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_timeout.75360899
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.220111656
Short name T953
Test name
Test status
Simulation time 541260975 ps
CPU time 7.05 seconds
Started Jul 16 05:33:54 PM PDT 24
Finished Jul 16 05:34:01 PM PDT 24
Peak memory 205372 kb
Host smart-80ee5435-84c0-4311-bc34-9a58dd7ab272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220111656 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.220111656
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3555338653
Short name T1212
Test name
Test status
Simulation time 17865372 ps
CPU time 0.65 seconds
Started Jul 16 05:28:37 PM PDT 24
Finished Jul 16 05:28:38 PM PDT 24
Peak memory 204760 kb
Host smart-d8de67f0-4347-4810-b4f3-9c28d636981d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555338653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3555338653
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.4106494743
Short name T655
Test name
Test status
Simulation time 91794852 ps
CPU time 1.95 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:21 PM PDT 24
Peak memory 213704 kb
Host smart-92619f9f-70f2-40a1-9f9b-04fb72bb0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106494743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.4106494743
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.768121175
Short name T1496
Test name
Test status
Simulation time 390081058 ps
CPU time 20.67 seconds
Started Jul 16 05:28:42 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 286896 kb
Host smart-aad230cf-1be2-44d6-b856-ae974949c08e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768121175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.768121175
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3398855777
Short name T1101
Test name
Test status
Simulation time 4918443182 ps
CPU time 71.28 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:37:46 PM PDT 24
Peak memory 481432 kb
Host smart-dd65765d-4ae6-4c28-873c-c7f9f6deae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398855777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3398855777
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3084829637
Short name T1059
Test name
Test status
Simulation time 4227983069 ps
CPU time 71.36 seconds
Started Jul 16 05:28:50 PM PDT 24
Finished Jul 16 05:30:03 PM PDT 24
Peak memory 766884 kb
Host smart-dbe0e6fa-d499-461c-ab0d-0e24c015328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084829637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3084829637
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.720759300
Short name T1437
Test name
Test status
Simulation time 295650301 ps
CPU time 1.05 seconds
Started Jul 16 05:32:26 PM PDT 24
Finished Jul 16 05:32:27 PM PDT 24
Peak memory 205144 kb
Host smart-d907fa30-b99c-42aa-9148-88b900da910a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720759300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.720759300
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1573570339
Short name T685
Test name
Test status
Simulation time 432186262 ps
CPU time 7.33 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:44 PM PDT 24
Peak memory 227488 kb
Host smart-fffa7f1f-a93b-4ae0-ad8c-cf46dd06704e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573570339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1573570339
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2452325230
Short name T452
Test name
Test status
Simulation time 3166852329 ps
CPU time 71.53 seconds
Started Jul 16 05:28:35 PM PDT 24
Finished Jul 16 05:29:47 PM PDT 24
Peak memory 882424 kb
Host smart-c0d820a4-c67d-4d29-b8e3-bd948cceb396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452325230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2452325230
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2411585780
Short name T237
Test name
Test status
Simulation time 463077713 ps
CPU time 17.65 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 205512 kb
Host smart-2492aff7-cd92-454e-96b5-f7b23d340592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411585780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2411585780
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.2824883841
Short name T87
Test name
Test status
Simulation time 28183908 ps
CPU time 0.67 seconds
Started Jul 16 05:28:37 PM PDT 24
Finished Jul 16 05:28:38 PM PDT 24
Peak memory 205384 kb
Host smart-069276bf-e300-4176-bd68-035ffa8cdaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824883841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2824883841
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1141773971
Short name T1592
Test name
Test status
Simulation time 1809479848 ps
CPU time 7.95 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:28:53 PM PDT 24
Peak memory 205568 kb
Host smart-44376ef3-1614-4dde-bd3f-2783a91bf7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141773971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1141773971
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1917362446
Short name T1632
Test name
Test status
Simulation time 796978411 ps
CPU time 4.34 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:40 PM PDT 24
Peak memory 205184 kb
Host smart-02689109-2dc1-4dd8-9232-0fc438b1268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917362446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1917362446
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3928760917
Short name T1535
Test name
Test status
Simulation time 3634641708 ps
CPU time 16.35 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 282196 kb
Host smart-5fdbac2a-0ecd-4439-9e7d-064973c1aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928760917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3928760917
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.574565025
Short name T1304
Test name
Test status
Simulation time 2731138132 ps
CPU time 18.17 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:51 PM PDT 24
Peak memory 229804 kb
Host smart-2ab6f902-01d4-4cc7-b872-9fb9ecc79266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574565025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.574565025
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.4258001502
Short name T638
Test name
Test status
Simulation time 2974749444 ps
CPU time 4.13 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:51 PM PDT 24
Peak memory 213828 kb
Host smart-7bc21e2c-c382-4f8b-ba4a-0e6adfc5e3bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258001502 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.4258001502
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.4211428398
Short name T221
Test name
Test status
Simulation time 600641490 ps
CPU time 1.48 seconds
Started Jul 16 05:28:40 PM PDT 24
Finished Jul 16 05:28:42 PM PDT 24
Peak memory 205396 kb
Host smart-6c3b13f0-79df-498b-9bc6-80d6eda6b989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211428398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.4211428398
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.390130349
Short name T1715
Test name
Test status
Simulation time 218590803 ps
CPU time 1.48 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:35 PM PDT 24
Peak memory 209132 kb
Host smart-ea21e4e6-6a37-4745-bca1-50db28ee6cd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390130349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.390130349
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.1307316096
Short name T1078
Test name
Test status
Simulation time 390758849 ps
CPU time 2.46 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:31:06 PM PDT 24
Peak memory 205464 kb
Host smart-ed9ab5f9-766e-47c2-8354-c2282064db61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307316096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.1307316096
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.4177737303
Short name T717
Test name
Test status
Simulation time 166165986 ps
CPU time 1.28 seconds
Started Jul 16 05:33:00 PM PDT 24
Finished Jul 16 05:33:02 PM PDT 24
Peak memory 205444 kb
Host smart-3bf1943d-cea0-4b0a-8a02-bcc642e6b3d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177737303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.4177737303
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3225162953
Short name T166
Test name
Test status
Simulation time 5883213108 ps
CPU time 3.78 seconds
Started Jul 16 05:32:26 PM PDT 24
Finished Jul 16 05:32:31 PM PDT 24
Peak memory 213908 kb
Host smart-5d9c8b01-cb52-40f2-bd70-b18287f270ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225162953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3225162953
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.4123672827
Short name T944
Test name
Test status
Simulation time 1380168523 ps
CPU time 4.94 seconds
Started Jul 16 05:28:32 PM PDT 24
Finished Jul 16 05:28:37 PM PDT 24
Peak memory 214552 kb
Host smart-87fbdc05-bb02-4be1-8cb7-68d94c238db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123672827 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.4123672827
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.913785154
Short name T553
Test name
Test status
Simulation time 16275914240 ps
CPU time 83.25 seconds
Started Jul 16 05:28:39 PM PDT 24
Finished Jul 16 05:30:03 PM PDT 24
Peak memory 1225480 kb
Host smart-bea8887f-0beb-48db-b162-63f25abe4932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913785154 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.913785154
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.1948957935
Short name T687
Test name
Test status
Simulation time 610030977 ps
CPU time 3.09 seconds
Started Jul 16 05:28:42 PM PDT 24
Finished Jul 16 05:28:46 PM PDT 24
Peak memory 213900 kb
Host smart-1a4b8db2-7419-4246-a952-578b0bd3cbc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948957935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.1948957935
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.2681527212
Short name T365
Test name
Test status
Simulation time 5224185685 ps
CPU time 2.53 seconds
Started Jul 16 05:28:42 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 205716 kb
Host smart-4c5bae6f-9652-4cd5-9acb-65c5b2a8c721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681527212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.2681527212
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_txstretch.48112274
Short name T1372
Test name
Test status
Simulation time 157319679 ps
CPU time 1.36 seconds
Started Jul 16 05:28:34 PM PDT 24
Finished Jul 16 05:28:35 PM PDT 24
Peak memory 222348 kb
Host smart-6d65b770-dc25-42ce-934e-b1f0bd40dc6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48112274 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_txstretch.48112274
Directory /workspace/48.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/48.i2c_target_perf.1363204975
Short name T1649
Test name
Test status
Simulation time 739299661 ps
CPU time 4.74 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:28 PM PDT 24
Peak memory 221944 kb
Host smart-6f22121d-6aef-4c10-9b54-afd149621763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363204975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.1363204975
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.342107332
Short name T1559
Test name
Test status
Simulation time 415913806 ps
CPU time 1.95 seconds
Started Jul 16 05:33:00 PM PDT 24
Finished Jul 16 05:33:02 PM PDT 24
Peak memory 205384 kb
Host smart-eb800cd9-78b8-4431-b2e9-2181538060a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342107332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_smbus_maxlen.342107332
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.124264831
Short name T639
Test name
Test status
Simulation time 2765291783 ps
CPU time 9.65 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:43 PM PDT 24
Peak memory 213804 kb
Host smart-a833f3c3-8d2b-40fb-add2-063c0dfb1804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124264831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.124264831
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.3854058349
Short name T667
Test name
Test status
Simulation time 53261087021 ps
CPU time 68.12 seconds
Started Jul 16 05:28:40 PM PDT 24
Finished Jul 16 05:29:49 PM PDT 24
Peak memory 601988 kb
Host smart-f2cc7806-e653-4ebc-9fb9-854b44487c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854058349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.3854058349
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1104541584
Short name T694
Test name
Test status
Simulation time 2824741361 ps
CPU time 14.35 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 221028 kb
Host smart-58bb1031-865b-4d02-991a-a344edbfcc8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104541584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1104541584
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3897403503
Short name T852
Test name
Test status
Simulation time 53930951093 ps
CPU time 1523.53 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:53:57 PM PDT 24
Peak memory 8741804 kb
Host smart-eea92753-5d39-4c99-a429-6fdbc46298d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897403503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3897403503
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1431803726
Short name T1299
Test name
Test status
Simulation time 1747842174 ps
CPU time 11.45 seconds
Started Jul 16 05:28:33 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 592476 kb
Host smart-4257f296-a632-4c43-b67c-20f00d05fcb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431803726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1431803726
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.766399126
Short name T1395
Test name
Test status
Simulation time 198192430 ps
CPU time 3.14 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:28:40 PM PDT 24
Peak memory 205696 kb
Host smart-adfc45fe-c4bb-4668-bc00-0c4c844c475c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766399126 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.766399126
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3489848894
Short name T171
Test name
Test status
Simulation time 43558275 ps
CPU time 0.64 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 204820 kb
Host smart-fe05c8fc-b6c9-448e-907a-f6248bc02898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489848894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3489848894
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3349396818
Short name T1575
Test name
Test status
Simulation time 197529463 ps
CPU time 6.75 seconds
Started Jul 16 05:28:35 PM PDT 24
Finished Jul 16 05:28:43 PM PDT 24
Peak memory 234072 kb
Host smart-903b5381-fa27-4a92-a054-78a0c9df0400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349396818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3349396818
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.25216855
Short name T759
Test name
Test status
Simulation time 162625317 ps
CPU time 3.46 seconds
Started Jul 16 05:33:00 PM PDT 24
Finished Jul 16 05:33:04 PM PDT 24
Peak memory 231636 kb
Host smart-e257e0da-1e71-4722-8f6b-b2012ac50313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty
.25216855
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2267781582
Short name T968
Test name
Test status
Simulation time 11634925933 ps
CPU time 82.35 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:30:10 PM PDT 24
Peak memory 506796 kb
Host smart-0d7dbf97-c7ba-4953-b4a0-4375cf87164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267781582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2267781582
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3108284644
Short name T161
Test name
Test status
Simulation time 6623395960 ps
CPU time 52.21 seconds
Started Jul 16 05:28:38 PM PDT 24
Finished Jul 16 05:29:31 PM PDT 24
Peak memory 560036 kb
Host smart-94faffec-9f8e-4efe-8af1-87fa1f14e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108284644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3108284644
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2414582852
Short name T937
Test name
Test status
Simulation time 467394416 ps
CPU time 1.16 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:28:46 PM PDT 24
Peak memory 205284 kb
Host smart-a3980efe-a971-4f7e-821b-42e133bed909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414582852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2414582852
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3311917715
Short name T1510
Test name
Test status
Simulation time 339110631 ps
CPU time 4.22 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 205376 kb
Host smart-0b6c6818-bfaf-402e-80a6-c6d0eda4756d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311917715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3311917715
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1548003685
Short name T1455
Test name
Test status
Simulation time 9755114278 ps
CPU time 119.94 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:30:45 PM PDT 24
Peak memory 1400000 kb
Host smart-a79c0456-d41d-4457-a8ef-07593aaf08f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548003685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1548003685
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3764900130
Short name T501
Test name
Test status
Simulation time 3138617168 ps
CPU time 6.59 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:42 PM PDT 24
Peak memory 205496 kb
Host smart-ab908f27-f3fb-43d6-a7b4-420d281e7801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764900130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3764900130
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.166678345
Short name T13
Test name
Test status
Simulation time 283473587 ps
CPU time 1.42 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 213600 kb
Host smart-c9664d0c-de6d-4970-9003-3b68a276f2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166678345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.166678345
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1593231040
Short name T291
Test name
Test status
Simulation time 87123997 ps
CPU time 0.69 seconds
Started Jul 16 05:28:39 PM PDT 24
Finished Jul 16 05:28:40 PM PDT 24
Peak memory 205180 kb
Host smart-aff69dad-79c4-4de0-80a8-8c794138b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593231040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1593231040
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1902301452
Short name T1433
Test name
Test status
Simulation time 938222137 ps
CPU time 4.14 seconds
Started Jul 16 05:28:45 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 233488 kb
Host smart-7fcdab17-1dff-46bc-90ba-cbda0729f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902301452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1902301452
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.2132679607
Short name T784
Test name
Test status
Simulation time 564105629 ps
CPU time 5.91 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:53 PM PDT 24
Peak memory 205408 kb
Host smart-1685720c-6f48-4b36-a0b4-bb4b31d02930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132679607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.2132679607
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.132085642
Short name T950
Test name
Test status
Simulation time 1848168222 ps
CPU time 32.66 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:29:10 PM PDT 24
Peak memory 294076 kb
Host smart-14592f77-3388-44a3-bd29-164f46d9be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132085642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.132085642
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3037421578
Short name T567
Test name
Test status
Simulation time 1627922336 ps
CPU time 34.45 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:29:20 PM PDT 24
Peak memory 213576 kb
Host smart-a342ef6b-c32f-499a-8c56-80bb9c36cf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037421578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3037421578
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2069753667
Short name T1387
Test name
Test status
Simulation time 12397285280 ps
CPU time 5.55 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:52 PM PDT 24
Peak memory 219492 kb
Host smart-b5498662-37bc-43ff-a150-1baa0d99b788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069753667 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2069753667
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.490607788
Short name T901
Test name
Test status
Simulation time 159554483 ps
CPU time 0.89 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 213608 kb
Host smart-93f07913-d716-4ed6-868b-4256ccf96b41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490607788 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_acq.490607788
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2307458333
Short name T1640
Test name
Test status
Simulation time 347978062 ps
CPU time 0.94 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 205336 kb
Host smart-26305d0a-1b9b-4a0a-81b7-5387f463ccc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307458333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2307458333
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.809023309
Short name T1588
Test name
Test status
Simulation time 76901935 ps
CPU time 0.85 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 205384 kb
Host smart-24f77f4f-6449-473d-ae30-15e3c3ae59e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809023309 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.809023309
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3291835678
Short name T377
Test name
Test status
Simulation time 773793974 ps
CPU time 1.61 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 205656 kb
Host smart-49e1060f-6d68-411f-9ce0-208318d113b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291835678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3291835678
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3123371484
Short name T423
Test name
Test status
Simulation time 705778018 ps
CPU time 4.35 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:24 PM PDT 24
Peak memory 213916 kb
Host smart-bf1da542-ca95-4d3f-b896-be59293c16bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123371484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3123371484
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2912685620
Short name T70
Test name
Test status
Simulation time 28370057336 ps
CPU time 17.21 seconds
Started Jul 16 05:32:30 PM PDT 24
Finished Jul 16 05:32:49 PM PDT 24
Peak memory 470940 kb
Host smart-435d7f79-9af1-4dd9-acee-7e96f74c0d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912685620 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2912685620
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.135009762
Short name T926
Test name
Test status
Simulation time 1933171886 ps
CPU time 2.81 seconds
Started Jul 16 05:32:30 PM PDT 24
Finished Jul 16 05:32:34 PM PDT 24
Peak memory 213848 kb
Host smart-ab9b0bf6-f986-4a7b-8863-ba8487a76a68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135009762 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_nack_acqfull.135009762
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.286580105
Short name T627
Test name
Test status
Simulation time 480893240 ps
CPU time 2.64 seconds
Started Jul 16 05:32:25 PM PDT 24
Finished Jul 16 05:32:29 PM PDT 24
Peak memory 205496 kb
Host smart-add72cf6-b84f-4eeb-98b6-21dc8765a284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286580105 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.286580105
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1547078142
Short name T482
Test name
Test status
Simulation time 974516959 ps
CPU time 7.57 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:08 PM PDT 24
Peak memory 213876 kb
Host smart-3058da1e-942c-4b17-ac8a-a98ae8bccc38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547078142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1547078142
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.2659017355
Short name T1202
Test name
Test status
Simulation time 7700889857 ps
CPU time 2.09 seconds
Started Jul 16 05:28:42 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 205440 kb
Host smart-1614b6bf-99c3-432f-8e23-26a65585ff43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659017355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.2659017355
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2136664468
Short name T1668
Test name
Test status
Simulation time 1431476709 ps
CPU time 23.51 seconds
Started Jul 16 05:28:35 PM PDT 24
Finished Jul 16 05:28:59 PM PDT 24
Peak memory 213892 kb
Host smart-ad60a307-3aae-4f12-88af-379cba41b4b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136664468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2136664468
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.349735232
Short name T1127
Test name
Test status
Simulation time 7601513711 ps
CPU time 43.02 seconds
Started Jul 16 05:32:34 PM PDT 24
Finished Jul 16 05:33:18 PM PDT 24
Peak memory 285428 kb
Host smart-27e0cd78-d348-4452-8edc-4935173f9b9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349735232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.349735232
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1943563387
Short name T1095
Test name
Test status
Simulation time 443256035 ps
CPU time 7.2 seconds
Started Jul 16 05:32:30 PM PDT 24
Finished Jul 16 05:32:38 PM PDT 24
Peak memory 206096 kb
Host smart-5d897c7b-81d4-4e85-bb95-4989b5c33716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943563387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1943563387
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.93526014
Short name T1010
Test name
Test status
Simulation time 41016293941 ps
CPU time 544.08 seconds
Started Jul 16 05:28:36 PM PDT 24
Finished Jul 16 05:37:41 PM PDT 24
Peak memory 4653560 kb
Host smart-3cbb8037-b2dd-483b-8459-5d828317eb23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93526014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stress_wr.93526014
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1012539907
Short name T345
Test name
Test status
Simulation time 2130562554 ps
CPU time 6.62 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:28:52 PM PDT 24
Peak memory 268768 kb
Host smart-d645fcbf-7cdf-457a-b839-62ca9133feda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012539907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1012539907
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2158706779
Short name T725
Test name
Test status
Simulation time 2814668577 ps
CPU time 6.84 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:54 PM PDT 24
Peak memory 213828 kb
Host smart-a29a5913-09a2-4952-ab13-23db816d552f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158706779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2158706779
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.3155476434
Short name T1084
Test name
Test status
Simulation time 106593860 ps
CPU time 1.89 seconds
Started Jul 16 05:28:44 PM PDT 24
Finished Jul 16 05:28:47 PM PDT 24
Peak memory 205608 kb
Host smart-99060116-e16e-46fb-8893-8d5142ba18a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155476434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.3155476434
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.316927179
Short name T967
Test name
Test status
Simulation time 16608563 ps
CPU time 0.64 seconds
Started Jul 16 05:26:10 PM PDT 24
Finished Jul 16 05:26:12 PM PDT 24
Peak memory 204844 kb
Host smart-8790965b-b0cd-4ed0-abbe-d06c2ae4a955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316927179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.316927179
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1561510290
Short name T666
Test name
Test status
Simulation time 121229415 ps
CPU time 4.43 seconds
Started Jul 16 05:22:26 PM PDT 24
Finished Jul 16 05:22:31 PM PDT 24
Peak memory 221932 kb
Host smart-a7721454-dc76-4e89-9576-fb2fb24c63b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561510290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1561510290
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2947546306
Short name T1211
Test name
Test status
Simulation time 409318233 ps
CPU time 7.28 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:33 PM PDT 24
Peak memory 293696 kb
Host smart-4eaa6a9f-9be6-404a-8eac-5e1d9397d59c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947546306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2947546306
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3600521446
Short name T418
Test name
Test status
Simulation time 3681036788 ps
CPU time 208.66 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:26:38 PM PDT 24
Peak memory 579928 kb
Host smart-2d757b4d-69da-43b9-bee7-7c470bc0a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600521446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3600521446
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.28679751
Short name T16
Test name
Test status
Simulation time 8347552604 ps
CPU time 176.26 seconds
Started Jul 16 05:22:22 PM PDT 24
Finished Jul 16 05:25:20 PM PDT 24
Peak memory 729564 kb
Host smart-de7322e1-c4c6-493e-b14d-21a4fbc7194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28679751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.28679751
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3410575219
Short name T1542
Test name
Test status
Simulation time 450010114 ps
CPU time 1.03 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:26 PM PDT 24
Peak memory 205168 kb
Host smart-df48ac79-3435-425a-b1eb-4abbfa325e0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410575219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3410575219
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.403247000
Short name T1164
Test name
Test status
Simulation time 382974539 ps
CPU time 3.3 seconds
Started Jul 16 05:22:24 PM PDT 24
Finished Jul 16 05:22:28 PM PDT 24
Peak memory 205436 kb
Host smart-a2572c3d-eb13-46e9-b874-3f8b107d32a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403247000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.403247000
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1161434248
Short name T105
Test name
Test status
Simulation time 5847700526 ps
CPU time 145.28 seconds
Started Jul 16 05:22:59 PM PDT 24
Finished Jul 16 05:25:26 PM PDT 24
Peak memory 1632996 kb
Host smart-0d3c0df7-bb57-455b-a411-9873edf187e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161434248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1161434248
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3966961727
Short name T1576
Test name
Test status
Simulation time 8133006355 ps
CPU time 9.17 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 205572 kb
Host smart-c2fe78c8-ed0b-4b7b-908f-c876eaeaec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966961727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3966961727
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.1018282943
Short name T519
Test name
Test status
Simulation time 56614047 ps
CPU time 0.68 seconds
Started Jul 16 05:22:23 PM PDT 24
Finished Jul 16 05:22:25 PM PDT 24
Peak memory 205212 kb
Host smart-c8468ce0-39dc-4bfd-b6b0-773e82b4c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018282943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1018282943
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.384716644
Short name T594
Test name
Test status
Simulation time 8010974044 ps
CPU time 26 seconds
Started Jul 16 05:22:32 PM PDT 24
Finished Jul 16 05:22:59 PM PDT 24
Peak memory 469012 kb
Host smart-bdc54b1b-46d3-41b2-97e5-03a5e6e50a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384716644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.384716644
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.3493020685
Short name T1182
Test name
Test status
Simulation time 241675409 ps
CPU time 2.49 seconds
Started Jul 16 05:22:30 PM PDT 24
Finished Jul 16 05:22:32 PM PDT 24
Peak memory 213488 kb
Host smart-e7e4a5eb-6997-469b-88ed-f08e236aef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493020685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.3493020685
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.289913247
Short name T1566
Test name
Test status
Simulation time 3557751565 ps
CPU time 87.9 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:27:47 PM PDT 24
Peak memory 383304 kb
Host smart-6c9bf33b-3b5d-4951-b531-07561883240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289913247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.289913247
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2121356524
Short name T381
Test name
Test status
Simulation time 2937824027 ps
CPU time 34.5 seconds
Started Jul 16 05:22:27 PM PDT 24
Finished Jul 16 05:23:02 PM PDT 24
Peak memory 213704 kb
Host smart-634dafb3-b78f-43d0-8cb2-eedacbb86556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121356524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2121356524
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.4188242324
Short name T1376
Test name
Test status
Simulation time 970671274 ps
CPU time 3.04 seconds
Started Jul 16 05:34:26 PM PDT 24
Finished Jul 16 05:34:30 PM PDT 24
Peak memory 213728 kb
Host smart-ed03ac45-ddd0-4e37-b31f-c027c8b5b708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188242324 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.4188242324
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1878741674
Short name T619
Test name
Test status
Simulation time 158910047 ps
CPU time 1.13 seconds
Started Jul 16 05:22:32 PM PDT 24
Finished Jul 16 05:22:34 PM PDT 24
Peak memory 205360 kb
Host smart-6b2936fb-2055-412f-9f4a-fb74412c428d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878741674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1878741674
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2027243090
Short name T923
Test name
Test status
Simulation time 179590125 ps
CPU time 1.25 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:38 PM PDT 24
Peak memory 205492 kb
Host smart-bbe7ba33-9d0b-4660-9024-19d7b902b47a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027243090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2027243090
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.2061238270
Short name T1485
Test name
Test status
Simulation time 1209489109 ps
CPU time 2.15 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 205360 kb
Host smart-4336e7c7-c16a-4e96-b1cc-178282245b44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061238270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.2061238270
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.1710074317
Short name T283
Test name
Test status
Simulation time 1142403081 ps
CPU time 1.42 seconds
Started Jul 16 05:22:38 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 205412 kb
Host smart-63df265d-da0d-4aad-8bfd-801a03912ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710074317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.1710074317
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3161178916
Short name T1698
Test name
Test status
Simulation time 3380716366 ps
CPU time 5.54 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:22:44 PM PDT 24
Peak memory 219376 kb
Host smart-10b8cff2-9e75-4f31-9c47-1ba92f3c9236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161178916 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3161178916
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.570540150
Short name T971
Test name
Test status
Simulation time 12132043148 ps
CPU time 3.95 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:41 PM PDT 24
Peak memory 205696 kb
Host smart-6c58a060-18af-46df-9a1a-3de05c7cedb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570540150 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.570540150
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.2262628764
Short name T1607
Test name
Test status
Simulation time 505243974 ps
CPU time 2.92 seconds
Started Jul 16 05:22:44 PM PDT 24
Finished Jul 16 05:22:47 PM PDT 24
Peak memory 213820 kb
Host smart-f5a7d4da-86e3-4164-a017-26766dcf3435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262628764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.2262628764
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.2788950654
Short name T1368
Test name
Test status
Simulation time 462858885 ps
CPU time 2.6 seconds
Started Jul 16 05:26:18 PM PDT 24
Finished Jul 16 05:26:21 PM PDT 24
Peak memory 205564 kb
Host smart-42fb2aab-c3b1-4103-9ffe-51a6110c99ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788950654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.2788950654
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_txstretch.265803993
Short name T1313
Test name
Test status
Simulation time 810422342 ps
CPU time 1.35 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:12 PM PDT 24
Peak memory 222444 kb
Host smart-9d1f82d8-ace9-4ca2-8a66-ef38e5c6fe7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265803993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_nack_txstretch.265803993
Directory /workspace/5.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/5.i2c_target_perf.1222564357
Short name T312
Test name
Test status
Simulation time 1034743791 ps
CPU time 4.11 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:41 PM PDT 24
Peak memory 213880 kb
Host smart-e4b9953f-ff68-4227-855b-1516dcb1ec5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222564357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.1222564357
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.155955201
Short name T1096
Test name
Test status
Simulation time 502486367 ps
CPU time 2.39 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:20 PM PDT 24
Peak memory 205392 kb
Host smart-e5487a6f-4c89-46ea-af84-c5c9fef6b6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155955201 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_smbus_maxlen.155955201
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1350152462
Short name T1577
Test name
Test status
Simulation time 1467320581 ps
CPU time 9.01 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:13 PM PDT 24
Peak memory 213764 kb
Host smart-460cc766-fdf3-4f4a-be9d-b235356bd505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350152462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1350152462
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.2359470263
Short name T906
Test name
Test status
Simulation time 25407600304 ps
CPU time 397.5 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:41:05 PM PDT 24
Peak memory 2476856 kb
Host smart-5cd2b8bb-a4d4-48c8-b002-f13783ec05cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359470263 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.2359470263
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3135408566
Short name T1144
Test name
Test status
Simulation time 3901084973 ps
CPU time 46.56 seconds
Started Jul 16 05:22:34 PM PDT 24
Finished Jul 16 05:23:21 PM PDT 24
Peak memory 214824 kb
Host smart-95314984-0904-46e5-b7bf-c4777355b5a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135408566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3135408566
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2050824454
Short name T742
Test name
Test status
Simulation time 18104137362 ps
CPU time 14.57 seconds
Started Jul 16 05:22:34 PM PDT 24
Finished Jul 16 05:22:49 PM PDT 24
Peak memory 205756 kb
Host smart-f71be3aa-381c-4046-9bc0-a2df57d42fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050824454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2050824454
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.944427214
Short name T1714
Test name
Test status
Simulation time 5519997875 ps
CPU time 6.43 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:44 PM PDT 24
Peak memory 219316 kb
Host smart-9e0db263-8cc2-4fe9-b40b-7f6a5bcc1f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944427214 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.944427214
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.387504939
Short name T925
Test name
Test status
Simulation time 41696284 ps
CPU time 1.15 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:22:39 PM PDT 24
Peak memory 205536 kb
Host smart-a1289ead-be5b-421b-be2f-6059c918ab05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387504939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.387504939
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3154372098
Short name T492
Test name
Test status
Simulation time 18064816 ps
CPU time 0.63 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:22:38 PM PDT 24
Peak memory 204720 kb
Host smart-365fdf54-e8f3-445d-8ac7-79892fbd3fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154372098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3154372098
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.240555509
Short name T1257
Test name
Test status
Simulation time 1813390740 ps
CPU time 24.58 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:23:03 PM PDT 24
Peak memory 305352 kb
Host smart-dde904c2-015a-4d37-ad20-fe0208cb2bfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240555509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.240555509
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3147142723
Short name T1090
Test name
Test status
Simulation time 16830238800 ps
CPU time 226.45 seconds
Started Jul 16 05:22:34 PM PDT 24
Finished Jul 16 05:26:21 PM PDT 24
Peak memory 669296 kb
Host smart-02fbf604-3681-42f7-af50-13d6514a14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147142723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3147142723
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.813514841
Short name T546
Test name
Test status
Simulation time 35815671257 ps
CPU time 78.03 seconds
Started Jul 16 05:22:35 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 833612 kb
Host smart-0b3a3a01-f1ae-4776-9492-2b65ba2ed911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813514841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.813514841
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1416519214
Short name T1262
Test name
Test status
Simulation time 434982065 ps
CPU time 0.83 seconds
Started Jul 16 05:22:43 PM PDT 24
Finished Jul 16 05:22:44 PM PDT 24
Peak memory 205212 kb
Host smart-63f34b45-bd96-4629-8741-d65a58dba777
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416519214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1416519214
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3530998555
Short name T303
Test name
Test status
Simulation time 285909778 ps
CPU time 9.97 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:48 PM PDT 24
Peak memory 205440 kb
Host smart-b3a47e81-5075-47c3-9ba0-1725c1af7857
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530998555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3530998555
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2015608900
Short name T705
Test name
Test status
Simulation time 9336450422 ps
CPU time 361.78 seconds
Started Jul 16 05:22:39 PM PDT 24
Finished Jul 16 05:28:41 PM PDT 24
Peak memory 1447372 kb
Host smart-8f64aa7f-ad9f-4de7-87d9-9ad21c817bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015608900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2015608900
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2061375392
Short name T245
Test name
Test status
Simulation time 1445948955 ps
CPU time 5.64 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:43 PM PDT 24
Peak memory 205500 kb
Host smart-09e24129-2fe0-4527-8c0b-fc92c7d6710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061375392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2061375392
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.807666092
Short name T1222
Test name
Test status
Simulation time 1549272590 ps
CPU time 3.3 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:21 PM PDT 24
Peak memory 205500 kb
Host smart-75d36b6c-8b7c-4c19-bc98-742bdcc99e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807666092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.807666092
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.170530247
Short name T1601
Test name
Test status
Simulation time 45075426 ps
CPU time 0.69 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:38 PM PDT 24
Peak memory 205136 kb
Host smart-6fbf0d57-bc70-423d-a571-6d317626851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170530247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.170530247
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.157291759
Short name T140
Test name
Test status
Simulation time 28214818138 ps
CPU time 144.85 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:28:35 PM PDT 24
Peak memory 764240 kb
Host smart-acccf82a-a5e0-44c7-be27-d294daeddb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157291759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.157291759
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.3905876922
Short name T388
Test name
Test status
Simulation time 439812505 ps
CPU time 5.07 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:22:43 PM PDT 24
Peak memory 244404 kb
Host smart-3cfc0048-64f5-4e60-80b3-7ec152bae172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905876922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.3905876922
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2295008502
Short name T1337
Test name
Test status
Simulation time 6489241751 ps
CPU time 28.55 seconds
Started Jul 16 05:31:16 PM PDT 24
Finished Jul 16 05:31:45 PM PDT 24
Peak memory 367672 kb
Host smart-1f64341f-ab19-48c5-bafb-0e80e8d30ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295008502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2295008502
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1739003879
Short name T1386
Test name
Test status
Simulation time 2576486168 ps
CPU time 9.72 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 221704 kb
Host smart-f12072ce-9d3c-4624-8f90-66623fab206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739003879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1739003879
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4195537500
Short name T1192
Test name
Test status
Simulation time 7499933117 ps
CPU time 6.98 seconds
Started Jul 16 05:22:38 PM PDT 24
Finished Jul 16 05:22:45 PM PDT 24
Peak memory 214080 kb
Host smart-198f2468-4666-498a-8780-39ca5b555370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195537500 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4195537500
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2364263025
Short name T633
Test name
Test status
Simulation time 896807338 ps
CPU time 1.23 seconds
Started Jul 16 05:22:39 PM PDT 24
Finished Jul 16 05:22:41 PM PDT 24
Peak memory 205572 kb
Host smart-f1f760d1-6173-4d2c-bc6e-5f56d5c04c98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364263025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2364263025
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3350920217
Short name T785
Test name
Test status
Simulation time 350896703 ps
CPU time 0.93 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:05 PM PDT 24
Peak memory 205388 kb
Host smart-d299e519-7f75-467e-879f-de3e563a6a48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350920217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3350920217
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.3628063031
Short name T1012
Test name
Test status
Simulation time 289633961 ps
CPU time 2.19 seconds
Started Jul 16 05:22:35 PM PDT 24
Finished Jul 16 05:22:38 PM PDT 24
Peak memory 205520 kb
Host smart-1ac495e6-d4bf-4483-a9a3-c693fd8a7046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628063031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3628063031
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2493067773
Short name T1482
Test name
Test status
Simulation time 183400592 ps
CPU time 0.99 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 205184 kb
Host smart-d9b81045-cb26-4d0d-b93f-832c6fef08d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493067773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2493067773
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1560577899
Short name T1462
Test name
Test status
Simulation time 1112496501 ps
CPU time 6.1 seconds
Started Jul 16 05:22:38 PM PDT 24
Finished Jul 16 05:22:45 PM PDT 24
Peak memory 211996 kb
Host smart-1a919e91-7b1e-4cfd-9ea1-c98937a86013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560577899 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1560577899
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2067558773
Short name T474
Test name
Test status
Simulation time 19117823249 ps
CPU time 22.77 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 694516 kb
Host smart-4fc20c63-8beb-4cd8-8b8a-748caeeccd18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067558773 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2067558773
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.2786023051
Short name T1043
Test name
Test status
Simulation time 1061715767 ps
CPU time 3 seconds
Started Jul 16 05:26:15 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 213684 kb
Host smart-fd391d4e-842f-4a23-bbf3-754246d44053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786023051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.2786023051
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.3261958389
Short name T364
Test name
Test status
Simulation time 1078492712 ps
CPU time 2.41 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 205632 kb
Host smart-aa83b935-75c9-4a28-8822-00918055f234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261958389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.3261958389
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.4130820460
Short name T1259
Test name
Test status
Simulation time 139751258 ps
CPU time 1.35 seconds
Started Jul 16 05:31:16 PM PDT 24
Finished Jul 16 05:31:18 PM PDT 24
Peak memory 222084 kb
Host smart-91e8e317-70ac-474a-b1b3-5fdcc92d5f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130820460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_txstretch.4130820460
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.191934550
Short name T1723
Test name
Test status
Simulation time 378153085 ps
CPU time 3.2 seconds
Started Jul 16 05:22:40 PM PDT 24
Finished Jul 16 05:22:44 PM PDT 24
Peak memory 221176 kb
Host smart-211261a1-e7af-432b-9712-78f8c28171bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191934550 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_perf.191934550
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.1736426491
Short name T1627
Test name
Test status
Simulation time 1890866163 ps
CPU time 2.55 seconds
Started Jul 16 05:22:43 PM PDT 24
Finished Jul 16 05:22:46 PM PDT 24
Peak memory 205380 kb
Host smart-e30cd939-c877-4e1b-af81-bf2fc5ffd927
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736426491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.1736426491
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1312920396
Short name T724
Test name
Test status
Simulation time 1582419449 ps
CPU time 25.2 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:40 PM PDT 24
Peak memory 213836 kb
Host smart-8afac840-8a22-4e26-b6d7-effd59e1dc2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312920396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1312920396
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.459972179
Short name T1194
Test name
Test status
Simulation time 76505598198 ps
CPU time 326.81 seconds
Started Jul 16 05:22:56 PM PDT 24
Finished Jul 16 05:28:24 PM PDT 24
Peak memory 1884312 kb
Host smart-ea15a510-3243-45dc-aae6-14c8322c2f3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459972179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_stress_all.459972179
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3358695853
Short name T804
Test name
Test status
Simulation time 241561147 ps
CPU time 3.7 seconds
Started Jul 16 05:24:35 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 205588 kb
Host smart-76e44e66-d208-462f-be96-a46f78fa6182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358695853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3358695853
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1311732907
Short name T1318
Test name
Test status
Simulation time 40054705012 ps
CPU time 67.5 seconds
Started Jul 16 05:22:33 PM PDT 24
Finished Jul 16 05:23:41 PM PDT 24
Peak memory 1197120 kb
Host smart-aac0bcfb-7965-4aed-97bd-01e5d18a3153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311732907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1311732907
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.599421948
Short name T181
Test name
Test status
Simulation time 2199228940 ps
CPU time 93.14 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:24:11 PM PDT 24
Peak memory 693864 kb
Host smart-6de171ec-5ec2-4e62-b8d6-4d15918f2335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599421948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.599421948
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.6904508
Short name T1227
Test name
Test status
Simulation time 5835244313 ps
CPU time 6.78 seconds
Started Jul 16 05:32:07 PM PDT 24
Finished Jul 16 05:32:14 PM PDT 24
Peak memory 222072 kb
Host smart-c7bc9180-d738-48fb-bdc0-8c1d4b3f301e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6904508 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_timeout.6904508
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.792192437
Short name T1022
Test name
Test status
Simulation time 244639764 ps
CPU time 4.6 seconds
Started Jul 16 05:22:34 PM PDT 24
Finished Jul 16 05:22:39 PM PDT 24
Peak memory 206476 kb
Host smart-732bf0e0-d9cd-4559-922b-210023ee48fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792192437 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.792192437
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2272673238
Short name T1135
Test name
Test status
Simulation time 17833446 ps
CPU time 0.61 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:25 PM PDT 24
Peak memory 204832 kb
Host smart-da6283a9-bfec-4945-b504-7e89f8b9a6ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272673238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2272673238
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1655535730
Short name T1093
Test name
Test status
Simulation time 1566952356 ps
CPU time 3.1 seconds
Started Jul 16 05:22:46 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 237264 kb
Host smart-0345c481-0209-4dac-a8ef-b2a271aeb435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655535730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1655535730
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4282393877
Short name T1451
Test name
Test status
Simulation time 1329433008 ps
CPU time 6.51 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:06 PM PDT 24
Peak memory 280064 kb
Host smart-ac5deea8-2e64-4dfb-a0f3-e6d08ae7114f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282393877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4282393877
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1746854130
Short name T498
Test name
Test status
Simulation time 14806371126 ps
CPU time 230.57 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 472884 kb
Host smart-36c09a1b-6fac-40d4-9d07-1c5b17b9fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746854130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1746854130
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1826922789
Short name T579
Test name
Test status
Simulation time 6511398121 ps
CPU time 163.18 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:25:21 PM PDT 24
Peak memory 726104 kb
Host smart-a5aecfc3-7579-4300-aba1-ea2200322870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826922789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1826922789
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3521902033
Short name T917
Test name
Test status
Simulation time 130175018 ps
CPU time 0.85 seconds
Started Jul 16 05:22:47 PM PDT 24
Finished Jul 16 05:22:48 PM PDT 24
Peak memory 205152 kb
Host smart-5249d30b-514e-4ba5-966e-8ba4dc9725cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521902033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3521902033
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3097256003
Short name T109
Test name
Test status
Simulation time 164478483 ps
CPU time 3.84 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:54 PM PDT 24
Peak memory 231340 kb
Host smart-9ddd0702-54d6-4a5b-b2a5-729faabb5cb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097256003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3097256003
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.227830955
Short name T787
Test name
Test status
Simulation time 12729534137 ps
CPU time 231.45 seconds
Started Jul 16 05:22:37 PM PDT 24
Finished Jul 16 05:26:30 PM PDT 24
Peak memory 1064892 kb
Host smart-10037917-fb5d-421f-b6a7-f015a29e358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227830955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.227830955
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3272386383
Short name T240
Test name
Test status
Simulation time 2270077761 ps
CPU time 7.97 seconds
Started Jul 16 05:31:16 PM PDT 24
Finished Jul 16 05:31:25 PM PDT 24
Peak memory 205608 kb
Host smart-c2e39610-9752-4638-afd8-ac75f4b21996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272386383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3272386383
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.1577701811
Short name T1003
Test name
Test status
Simulation time 82687902 ps
CPU time 0.66 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:22:37 PM PDT 24
Peak memory 205184 kb
Host smart-7ba2b6b5-c7b3-422b-aed9-2e84ae669283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577701811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1577701811
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1968018419
Short name T974
Test name
Test status
Simulation time 13745297083 ps
CPU time 53.24 seconds
Started Jul 16 05:22:47 PM PDT 24
Finished Jul 16 05:23:41 PM PDT 24
Peak memory 249920 kb
Host smart-c2dca271-6b61-4747-af92-09dcf88b2db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968018419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1968018419
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.4160456241
Short name T1729
Test name
Test status
Simulation time 223730566 ps
CPU time 3.06 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:34:31 PM PDT 24
Peak memory 205304 kb
Host smart-b4349fe8-8f46-4c24-8c31-a44301030b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160456241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.4160456241
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.983041327
Short name T1140
Test name
Test status
Simulation time 5981447546 ps
CPU time 34.52 seconds
Started Jul 16 05:22:36 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 351600 kb
Host smart-725c3c5d-ffdf-4415-83fa-94430bb2c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983041327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.983041327
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3764996006
Short name T503
Test name
Test status
Simulation time 2630010752 ps
CPU time 28.77 seconds
Started Jul 16 05:25:10 PM PDT 24
Finished Jul 16 05:25:40 PM PDT 24
Peak memory 213720 kb
Host smart-e20f0a54-de19-4c47-98bc-f0aab4477a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764996006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3764996006
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3787013745
Short name T600
Test name
Test status
Simulation time 6794538395 ps
CPU time 6.73 seconds
Started Jul 16 05:25:10 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 221124 kb
Host smart-cc3df5ff-188b-479c-b967-49862add3d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787013745 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3787013745
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2556305960
Short name T85
Test name
Test status
Simulation time 829816351 ps
CPU time 1.68 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 205536 kb
Host smart-cf2f8215-1dcd-4b89-8cbe-2490e68934af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556305960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2556305960
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.4088083824
Short name T88
Test name
Test status
Simulation time 158704430 ps
CPU time 0.85 seconds
Started Jul 16 05:28:04 PM PDT 24
Finished Jul 16 05:28:05 PM PDT 24
Peak memory 213520 kb
Host smart-550bcec2-911b-4614-a422-3b6efc2a8963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088083824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.4088083824
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.4274329651
Short name T1180
Test name
Test status
Simulation time 478400592 ps
CPU time 2.85 seconds
Started Jul 16 05:22:51 PM PDT 24
Finished Jul 16 05:22:55 PM PDT 24
Peak memory 205532 kb
Host smart-35ea8483-1e92-49ff-999d-c6ba5bcc803d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274329651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.4274329651
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.760004282
Short name T554
Test name
Test status
Simulation time 57652459 ps
CPU time 0.78 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:22:49 PM PDT 24
Peak memory 205472 kb
Host smart-3afb3e8f-18a8-4b87-8a4e-6c967c81cc6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760004282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.760004282
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2069848898
Short name T1397
Test name
Test status
Simulation time 2091476928 ps
CPU time 6.2 seconds
Started Jul 16 05:22:54 PM PDT 24
Finished Jul 16 05:23:01 PM PDT 24
Peak memory 222036 kb
Host smart-a4b4f412-2cbb-43cf-af3c-c211e0f4a586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069848898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2069848898
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3516351392
Short name T344
Test name
Test status
Simulation time 5033586086 ps
CPU time 19.27 seconds
Started Jul 16 05:22:54 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 726344 kb
Host smart-de70c792-0641-40b1-9c60-95ff04756c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516351392 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3516351392
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.3318723733
Short name T1571
Test name
Test status
Simulation time 575283461 ps
CPU time 2.8 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:53 PM PDT 24
Peak memory 213852 kb
Host smart-1a08a922-4a5e-4546-9caf-e3f9ad634abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318723733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.3318723733
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.3281147888
Short name T763
Test name
Test status
Simulation time 4421056454 ps
CPU time 2.34 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:52 PM PDT 24
Peak memory 205556 kb
Host smart-67214358-466d-446e-95b4-bdfa0f8462ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281147888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3281147888
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.2432261194
Short name T81
Test name
Test status
Simulation time 495716761 ps
CPU time 3.87 seconds
Started Jul 16 05:22:47 PM PDT 24
Finished Jul 16 05:22:52 PM PDT 24
Peak memory 213860 kb
Host smart-374e382d-a01e-4837-b700-2116fd51e687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432261194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.2432261194
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.687533454
Short name T798
Test name
Test status
Simulation time 421787401 ps
CPU time 2.42 seconds
Started Jul 16 05:25:51 PM PDT 24
Finished Jul 16 05:25:54 PM PDT 24
Peak memory 205332 kb
Host smart-fde9685f-696e-42fc-82a3-5b3256355743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687533454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_smbus_maxlen.687533454
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3699397416
Short name T893
Test name
Test status
Simulation time 26837703724 ps
CPU time 21.32 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:21 PM PDT 24
Peak memory 213880 kb
Host smart-bf80864c-8155-48df-88af-af837bef4b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699397416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3699397416
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3083377255
Short name T674
Test name
Test status
Simulation time 54896508502 ps
CPU time 751.24 seconds
Started Jul 16 05:25:53 PM PDT 24
Finished Jul 16 05:38:25 PM PDT 24
Peak memory 4570048 kb
Host smart-566e906b-43df-413b-a3e3-23067e59bcb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083377255 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3083377255
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.621876078
Short name T647
Test name
Test status
Simulation time 7000443984 ps
CPU time 27.3 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:23:17 PM PDT 24
Peak memory 234188 kb
Host smart-e8e8245e-6836-49d6-a250-ea515bf7894d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621876078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.621876078
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1707645758
Short name T80
Test name
Test status
Simulation time 64653026559 ps
CPU time 3197.34 seconds
Started Jul 16 05:22:54 PM PDT 24
Finished Jul 16 06:16:13 PM PDT 24
Peak memory 11335892 kb
Host smart-435ab951-bc76-4bbb-8af6-033225e71a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707645758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1707645758
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2619508869
Short name T1512
Test name
Test status
Simulation time 3078199654 ps
CPU time 158.54 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:25:27 PM PDT 24
Peak memory 894916 kb
Host smart-77b071b2-6557-4a13-a914-f26342e38d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619508869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2619508869
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2024226955
Short name T696
Test name
Test status
Simulation time 9183466720 ps
CPU time 6.85 seconds
Started Jul 16 05:25:53 PM PDT 24
Finished Jul 16 05:26:01 PM PDT 24
Peak memory 213764 kb
Host smart-ce0da7dc-c08c-4070-964c-c6025bd7f824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024226955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2024226955
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.3192024467
Short name T590
Test name
Test status
Simulation time 144451175 ps
CPU time 3.24 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:53 PM PDT 24
Peak memory 205972 kb
Host smart-890d4b8f-f2c4-4122-b7cf-4e5d97e5777d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192024467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.3192024467
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2481200648
Short name T1139
Test name
Test status
Simulation time 16868799 ps
CPU time 0.66 seconds
Started Jul 16 05:22:53 PM PDT 24
Finished Jul 16 05:22:54 PM PDT 24
Peak memory 204804 kb
Host smart-fc89cb22-a599-432e-8435-3aec5670a789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481200648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2481200648
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1550357040
Short name T23
Test name
Test status
Simulation time 1645511739 ps
CPU time 2.15 seconds
Started Jul 16 05:22:54 PM PDT 24
Finished Jul 16 05:22:57 PM PDT 24
Peak memory 217780 kb
Host smart-c55d04aa-c48e-4038-9867-46222aa27732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550357040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1550357040
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.4244793423
Short name T540
Test name
Test status
Simulation time 1473649524 ps
CPU time 20.58 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:23:10 PM PDT 24
Peak memory 289456 kb
Host smart-014c2507-309d-4586-aa42-79230705d1c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244793423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.4244793423
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.815965550
Short name T15
Test name
Test status
Simulation time 8306815117 ps
CPU time 53.25 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:27:11 PM PDT 24
Peak memory 506280 kb
Host smart-0e1de964-70ae-41ec-87fa-f3813bf6825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815965550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.815965550
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1767164355
Short name T1412
Test name
Test status
Simulation time 3346212651 ps
CPU time 88.34 seconds
Started Jul 16 05:25:10 PM PDT 24
Finished Jul 16 05:26:39 PM PDT 24
Peak memory 848680 kb
Host smart-3cd3d52a-5586-4064-9e86-9db2a9a9d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767164355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1767164355
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3813719793
Short name T973
Test name
Test status
Simulation time 506864245 ps
CPU time 1.06 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:51 PM PDT 24
Peak memory 205240 kb
Host smart-374ff2f1-d040-47ab-bf97-dad841b7438b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813719793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3813719793
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3261814251
Short name T874
Test name
Test status
Simulation time 1246713513 ps
CPU time 4.04 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 225472 kb
Host smart-80d31cf5-2c69-4755-b942-d1eb78f3d79f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261814251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3261814251
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3244488807
Short name T771
Test name
Test status
Simulation time 10116533085 ps
CPU time 328.54 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:28:19 PM PDT 24
Peak memory 1266964 kb
Host smart-86e4ff88-37d7-44aa-8b07-13d2c18facac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244488807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3244488807
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.3554404764
Short name T1690
Test name
Test status
Simulation time 370304376 ps
CPU time 6 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:29 PM PDT 24
Peak memory 205528 kb
Host smart-a7edbb74-befa-4183-999e-a9a56927411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554404764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3554404764
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.2126002972
Short name T248
Test name
Test status
Simulation time 209309083 ps
CPU time 0.68 seconds
Started Jul 16 05:26:17 PM PDT 24
Finished Jul 16 05:26:19 PM PDT 24
Peak memory 204860 kb
Host smart-6b46a597-46c5-4b8d-a533-b0a01e4f1289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126002972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2126002972
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3776696313
Short name T618
Test name
Test status
Simulation time 2679293849 ps
CPU time 60.76 seconds
Started Jul 16 05:22:51 PM PDT 24
Finished Jul 16 05:23:52 PM PDT 24
Peak memory 470816 kb
Host smart-4db8e77c-8042-49c6-8c49-2598bbb39c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776696313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3776696313
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.1078759839
Short name T658
Test name
Test status
Simulation time 2279653822 ps
CPU time 5.4 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:15 PM PDT 24
Peak memory 205084 kb
Host smart-65d621e7-1205-4126-9a0b-ffc85a9cfee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078759839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.1078759839
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.20584046
Short name T539
Test name
Test status
Simulation time 2788219778 ps
CPU time 66.65 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:23:56 PM PDT 24
Peak memory 376796 kb
Host smart-c579c78f-2eff-4662-b06f-9753f2fe5b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20584046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.20584046
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1213199718
Short name T337
Test name
Test status
Simulation time 1663982452 ps
CPU time 19.13 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:44 PM PDT 24
Peak memory 213720 kb
Host smart-94b4f08b-86ef-4ec4-91a3-515e7fa14470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213199718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1213199718
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2901866630
Short name T859
Test name
Test status
Simulation time 1082292092 ps
CPU time 6.03 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:22:55 PM PDT 24
Peak memory 214280 kb
Host smart-b60cf6b2-e6e3-41e2-a559-db4b317d6a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901866630 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2901866630
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1198407583
Short name T1071
Test name
Test status
Simulation time 182503992 ps
CPU time 1.03 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:26 PM PDT 24
Peak memory 205468 kb
Host smart-43b8fe7f-796e-4454-b38b-09c358cbe2c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198407583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1198407583
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.4147015874
Short name T1450
Test name
Test status
Simulation time 468958824 ps
CPU time 1.15 seconds
Started Jul 16 05:22:59 PM PDT 24
Finished Jul 16 05:23:02 PM PDT 24
Peak memory 205572 kb
Host smart-a5f25eec-ed31-4b68-91b8-da11a0709213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147015874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.4147015874
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.3147642845
Short name T1654
Test name
Test status
Simulation time 2714877175 ps
CPU time 3.15 seconds
Started Jul 16 05:22:51 PM PDT 24
Finished Jul 16 05:22:54 PM PDT 24
Peak memory 205676 kb
Host smart-a51c1e4e-f5aa-447c-963b-32c176fa62b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147642845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.3147642845
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.2139064053
Short name T709
Test name
Test status
Simulation time 633797315 ps
CPU time 1.5 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:04 PM PDT 24
Peak memory 205412 kb
Host smart-4e5b6aa0-b272-434e-a647-f142cec8afaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139064053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.2139064053
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2173425914
Short name T1231
Test name
Test status
Simulation time 2699379075 ps
CPU time 8.36 seconds
Started Jul 16 05:26:09 PM PDT 24
Finished Jul 16 05:26:18 PM PDT 24
Peak memory 231744 kb
Host smart-0fac8d61-a030-41f9-805a-8d148d9ff448
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173425914 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2173425914
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1407092073
Short name T1633
Test name
Test status
Simulation time 15634536884 ps
CPU time 180.65 seconds
Started Jul 16 05:34:27 PM PDT 24
Finished Jul 16 05:37:29 PM PDT 24
Peak memory 2250424 kb
Host smart-aea41f55-2cc7-40b9-be62-e1df1e6975df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407092073 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1407092073
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.2880406529
Short name T1677
Test name
Test status
Simulation time 513752432 ps
CPU time 2.87 seconds
Started Jul 16 05:22:50 PM PDT 24
Finished Jul 16 05:22:54 PM PDT 24
Peak memory 213768 kb
Host smart-35714862-764a-4000-90f2-01cfd0fc2c5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880406529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.2880406529
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.1787932807
Short name T112
Test name
Test status
Simulation time 450988541 ps
CPU time 2.49 seconds
Started Jul 16 05:22:52 PM PDT 24
Finished Jul 16 05:22:55 PM PDT 24
Peak memory 206536 kb
Host smart-7fdfa7c8-56df-408e-8336-5d154b9d7a22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787932807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1787932807
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.3679196017
Short name T78
Test name
Test status
Simulation time 993968343 ps
CPU time 5.43 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 217216 kb
Host smart-fa05ac46-ba0e-4148-bbf4-5ca00eb5d3c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679196017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.3679196017
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.1444180149
Short name T1578
Test name
Test status
Simulation time 1030549951 ps
CPU time 2.58 seconds
Started Jul 16 05:22:50 PM PDT 24
Finished Jul 16 05:22:53 PM PDT 24
Peak memory 205288 kb
Host smart-8142d775-5827-4043-a611-8dcf0ff7ff03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444180149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.1444180149
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2686931256
Short name T137
Test name
Test status
Simulation time 972568319 ps
CPU time 30.05 seconds
Started Jul 16 05:22:59 PM PDT 24
Finished Jul 16 05:23:31 PM PDT 24
Peak memory 213792 kb
Host smart-8b8fb120-e66a-48f0-8ae5-e75a35c2788e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686931256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2686931256
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.1678873583
Short name T986
Test name
Test status
Simulation time 33949319402 ps
CPU time 986.29 seconds
Started Jul 16 05:22:47 PM PDT 24
Finished Jul 16 05:39:14 PM PDT 24
Peak memory 5038644 kb
Host smart-a406d8be-ed4b-4cfe-92a5-3ca7fc6cbd64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678873583 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.1678873583
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1771239105
Short name T271
Test name
Test status
Simulation time 3585285089 ps
CPU time 25.88 seconds
Started Jul 16 05:22:45 PM PDT 24
Finished Jul 16 05:23:11 PM PDT 24
Peak memory 213852 kb
Host smart-99b7c6bd-7d96-41d6-85c9-d6b00b78b799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771239105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1771239105
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2154836642
Short name T1725
Test name
Test status
Simulation time 32295122496 ps
CPU time 29.43 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:23:18 PM PDT 24
Peak memory 658296 kb
Host smart-e4382380-fc17-4845-ae6e-b7f76c7d8cff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154836642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2154836642
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3777394558
Short name T456
Test name
Test status
Simulation time 483402333 ps
CPU time 0.99 seconds
Started Jul 16 05:22:48 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 205656 kb
Host smart-9ff510a0-98c0-4faf-8bb0-6a89b81facd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777394558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3777394558
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1010240441
Short name T541
Test name
Test status
Simulation time 1235733377 ps
CPU time 6.66 seconds
Started Jul 16 05:22:51 PM PDT 24
Finished Jul 16 05:22:59 PM PDT 24
Peak memory 219284 kb
Host smart-b12a5172-b5cf-4a7d-8eeb-5e02269663b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010240441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1010240441
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.4293301260
Short name T320
Test name
Test status
Simulation time 144773021 ps
CPU time 2.35 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 205604 kb
Host smart-bd04ad6c-5081-481e-a69f-0ee747b8303c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293301260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4293301260
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.243433450
Short name T473
Test name
Test status
Simulation time 16309568 ps
CPU time 0.64 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:03 PM PDT 24
Peak memory 204792 kb
Host smart-6f865280-f684-4609-b0a5-22881d7e56f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243433450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.243433450
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3429246098
Short name T21
Test name
Test status
Simulation time 63794675 ps
CPU time 1.6 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:00 PM PDT 24
Peak memory 213784 kb
Host smart-f3066ecc-d7c3-4d39-a6c8-45b1470f7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429246098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3429246098
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.788124991
Short name T722
Test name
Test status
Simulation time 2170960213 ps
CPU time 3.97 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:10 PM PDT 24
Peak memory 220940 kb
Host smart-127f7e01-18a2-4b73-b103-e779479d309f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788124991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.788124991
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.561378012
Short name T490
Test name
Test status
Simulation time 4024302531 ps
CPU time 103.55 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:24:43 PM PDT 24
Peak memory 340012 kb
Host smart-391b16db-031f-427c-b695-8354fddaa925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561378012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.561378012
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2350252236
Short name T1046
Test name
Test status
Simulation time 2485733853 ps
CPU time 90.4 seconds
Started Jul 16 05:23:02 PM PDT 24
Finished Jul 16 05:24:35 PM PDT 24
Peak memory 827184 kb
Host smart-fa4a60c2-1775-487b-a44c-7299e8d83a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350252236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2350252236
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2620027611
Short name T909
Test name
Test status
Simulation time 103885146 ps
CPU time 1.05 seconds
Started Jul 16 05:22:57 PM PDT 24
Finished Jul 16 05:22:58 PM PDT 24
Peak memory 205212 kb
Host smart-2a34102d-fa43-4e1e-9197-3341d55230ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620027611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2620027611
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.232237529
Short name T999
Test name
Test status
Simulation time 615564345 ps
CPU time 3.39 seconds
Started Jul 16 05:23:10 PM PDT 24
Finished Jul 16 05:23:14 PM PDT 24
Peak memory 205532 kb
Host smart-929fa7a4-a8eb-476e-b04f-088528730d31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232237529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.232237529
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.111523961
Short name T99
Test name
Test status
Simulation time 5187255695 ps
CPU time 134.03 seconds
Started Jul 16 05:36:26 PM PDT 24
Finished Jul 16 05:38:40 PM PDT 24
Peak memory 1526900 kb
Host smart-105c61d7-5b21-4412-80ba-ce12fe39eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111523961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.111523961
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1220431332
Short name T571
Test name
Test status
Simulation time 620912740 ps
CPU time 5.8 seconds
Started Jul 16 05:23:01 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 205508 kb
Host smart-d8e2ae9c-1a16-4da3-8006-838f8fcc414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220431332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1220431332
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3014040792
Short name T11
Test name
Test status
Simulation time 511446622 ps
CPU time 1.96 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 217024 kb
Host smart-04aa540a-e6f4-41a0-97fb-78f639939c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014040792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3014040792
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.258927526
Short name T1279
Test name
Test status
Simulation time 21338483 ps
CPU time 0.65 seconds
Started Jul 16 05:22:49 PM PDT 24
Finished Jul 16 05:22:50 PM PDT 24
Peak memory 205148 kb
Host smart-a6993a30-0021-457c-941e-7f403d270886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258927526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.258927526
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.32263616
Short name T1115
Test name
Test status
Simulation time 18434368551 ps
CPU time 183.84 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:34:08 PM PDT 24
Peak memory 294248 kb
Host smart-bf8e95cc-7c25-4a33-8943-4238703bb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32263616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.32263616
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.2502866339
Short name T1282
Test name
Test status
Simulation time 6025658707 ps
CPU time 224.05 seconds
Started Jul 16 05:26:16 PM PDT 24
Finished Jul 16 05:30:02 PM PDT 24
Peak memory 205288 kb
Host smart-5a5b5b2d-c9fc-4003-a78f-3e273dd66054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502866339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.2502866339
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3432608845
Short name T489
Test name
Test status
Simulation time 4850051379 ps
CPU time 19.42 seconds
Started Jul 16 05:22:52 PM PDT 24
Finished Jul 16 05:23:13 PM PDT 24
Peak memory 284812 kb
Host smart-b6e8e2af-bd46-46d9-b15f-2a1091067a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432608845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3432608845
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3930549825
Short name T101
Test name
Test status
Simulation time 51402718403 ps
CPU time 385.86 seconds
Started Jul 16 05:32:02 PM PDT 24
Finished Jul 16 05:38:29 PM PDT 24
Peak memory 2957604 kb
Host smart-20377c62-3512-477c-8505-0bad43ee7774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930549825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3930549825
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3691226547
Short name T1680
Test name
Test status
Simulation time 2666504597 ps
CPU time 10.25 seconds
Started Jul 16 05:22:59 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 214776 kb
Host smart-1507e7b5-b1db-4137-80f5-e3a5d1c98847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691226547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3691226547
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.4088846325
Short name T608
Test name
Test status
Simulation time 2525973060 ps
CPU time 3.65 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:07 PM PDT 24
Peak memory 207532 kb
Host smart-181804a2-3c40-485b-b2ec-134dbe8c53c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088846325 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.4088846325
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3794719833
Short name T1686
Test name
Test status
Simulation time 167991928 ps
CPU time 0.94 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:03 PM PDT 24
Peak memory 205356 kb
Host smart-c164276e-9123-4f92-8210-37d70ebd6812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794719833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3794719833
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2763183435
Short name T220
Test name
Test status
Simulation time 142973212 ps
CPU time 1.09 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:04 PM PDT 24
Peak memory 205468 kb
Host smart-fd1f42a5-bf11-4084-9b7b-673dcccfedd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763183435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2763183435
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.665855946
Short name T797
Test name
Test status
Simulation time 558575790 ps
CPU time 2.81 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:03 PM PDT 24
Peak memory 205652 kb
Host smart-b193bba3-ac00-4450-9505-2f64827454ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665855946 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.665855946
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.309778662
Short name T1570
Test name
Test status
Simulation time 2043312326 ps
CPU time 1.28 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 204988 kb
Host smart-e62804df-7bd2-4718-87f9-743cb81f8d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309778662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.309778662
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.548604715
Short name T864
Test name
Test status
Simulation time 3698892513 ps
CPU time 5.05 seconds
Started Jul 16 05:23:09 PM PDT 24
Finished Jul 16 05:23:15 PM PDT 24
Peak memory 216868 kb
Host smart-9777c37f-63b0-4866-bcd1-4f475bbcc507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548604715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.548604715
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.100205988
Short name T528
Test name
Test status
Simulation time 20291000630 ps
CPU time 31.94 seconds
Started Jul 16 05:22:58 PM PDT 24
Finished Jul 16 05:23:31 PM PDT 24
Peak memory 813052 kb
Host smart-8d7b2af9-f874-4d80-aae2-88d94104d182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100205988 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.100205988
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.2896991093
Short name T64
Test name
Test status
Simulation time 2270515881 ps
CPU time 2.76 seconds
Started Jul 16 05:26:24 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 213908 kb
Host smart-c7554218-3726-441a-a99c-dcdbefabee23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896991093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.2896991093
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.1516491890
Short name T1380
Test name
Test status
Simulation time 3076903397 ps
CPU time 2.81 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:27 PM PDT 24
Peak memory 205716 kb
Host smart-af22ab65-ad4f-4576-8e99-5e8dfb92aa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516491890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.1516491890
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_txstretch.3011777845
Short name T154
Test name
Test status
Simulation time 446340234 ps
CPU time 1.32 seconds
Started Jul 16 05:23:06 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 222300 kb
Host smart-6b75ddec-7f53-4377-9957-3f122a555520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011777845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_nack_txstretch.3011777845
Directory /workspace/9.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/9.i2c_target_perf.774965036
Short name T1472
Test name
Test status
Simulation time 796771406 ps
CPU time 5.81 seconds
Started Jul 16 05:24:34 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 213800 kb
Host smart-ce978804-77b5-412b-aa7b-18d8c74bd6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774965036 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_perf.774965036
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.4063473616
Short name T1734
Test name
Test status
Simulation time 438950636 ps
CPU time 2.33 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:08 PM PDT 24
Peak memory 205356 kb
Host smart-c37446c8-221c-4504-b186-6bb93c3dc5e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063473616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.4063473616
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2997533531
Short name T762
Test name
Test status
Simulation time 1462711418 ps
CPU time 9.19 seconds
Started Jul 16 05:23:00 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 213784 kb
Host smart-45d9d765-900b-41c6-8164-e4d7fc85867b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997533531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2997533531
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.1014449223
Short name T1054
Test name
Test status
Simulation time 8894647560 ps
CPU time 64.01 seconds
Started Jul 16 05:31:03 PM PDT 24
Finished Jul 16 05:32:07 PM PDT 24
Peak memory 956648 kb
Host smart-241d0fdb-fec9-4e60-87a4-3cdbc00d9e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014449223 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.1014449223
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1499304829
Short name T250
Test name
Test status
Simulation time 1516582294 ps
CPU time 27.94 seconds
Started Jul 16 05:26:23 PM PDT 24
Finished Jul 16 05:26:52 PM PDT 24
Peak memory 230172 kb
Host smart-a684e72e-de40-49df-b004-c4c6ca1426a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499304829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1499304829
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1662382494
Short name T1464
Test name
Test status
Simulation time 49444263775 ps
CPU time 1254.78 seconds
Started Jul 16 05:36:22 PM PDT 24
Finished Jul 16 05:57:18 PM PDT 24
Peak memory 7411644 kb
Host smart-7163b5f7-3379-4a62-ab4b-fa1a7b3237c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662382494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1662382494
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2503684221
Short name T1293
Test name
Test status
Simulation time 2740028631 ps
CPU time 7.42 seconds
Started Jul 16 05:27:33 PM PDT 24
Finished Jul 16 05:27:42 PM PDT 24
Peak memory 221920 kb
Host smart-b69024e1-bdcf-47a3-8162-cf5ad3e0d98d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503684221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2503684221
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3104086963
Short name T794
Test name
Test status
Simulation time 227007223 ps
CPU time 3.86 seconds
Started Jul 16 05:23:03 PM PDT 24
Finished Jul 16 05:23:09 PM PDT 24
Peak memory 205604 kb
Host smart-1c5ff19b-bd08-4e4b-837e-f1bc2fa6fe37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104086963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3104086963
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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