Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	735690	1			T1	3		T2	3		T3	2
all_values[1]	735690	1			T1	3		T2	3		T3	2
all_values[2]	735690	1			T1	3		T2	3		T3	2
all_values[3]	735690	1			T1	3		T2	3		T3	2
all_values[4]	735690	1			T1	3		T2	3		T3	2
all_values[5]	735690	1			T1	3		T2	3		T3	2
all_values[6]	735690	1			T1	3		T2	3		T3	2
all_values[7]	735690	1			T1	3		T2	3		T3	2
all_values[8]	735690	1			T1	3		T2	3		T3	2
all_values[9]	735690	1			T1	3		T2	3		T3	2
all_values[10]	735690	1			T1	3		T2	3		T3	2
all_values[11]	735690	1			T1	3		T2	3		T3	2
all_values[12]	735690	1			T1	3		T2	3		T3	2
all_values[13]	735690	1			T1	3		T2	3		T3	2
all_values[14]	735690	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9177450

1

T1

39

T2

36

T3

24

auto[1]

1857900

1

T1

6

T2

9

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10934690

1

T1

45

T2

45

T3

30

auto[1]

100660

1

T24

23724

T25

5181

T31

85

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	135451	1			T1	1		T7	1		T8	8
all_values[0]	auto[0]	auto[1]	3248	1			T24	1315		T25	254		T31	4
all_values[0]	auto[1]	auto[0]	594556	1			T1	2		T2	3		T3	2
all_values[0]	auto[1]	auto[1]	2435	1			T24	379		T25	92		T31	2
all_values[1]	auto[0]	auto[0]	728276	1			T1	3		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	6957	1			T24	1691		T25	341		T31	4
all_values[1]	auto[1]	auto[0]	311	1			T123	21		T264	2		T16	16
all_values[1]	auto[1]	auto[1]	146	1			T24	4		T25	4		T31	2
all_values[2]	auto[0]	auto[0]	728393	1			T1	3		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	6955	1			T24	1691		T25	342		T31	3
all_values[2]	auto[1]	auto[0]	196	1			T2	2		T3	1		T4	2
all_values[2]	auto[1]	auto[1]	146	1			T24	3		T25	4		T31	3
all_values[3]	auto[0]	auto[0]	728561	1			T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	6963	1			T24	1688		T25	342		T31	4
all_values[3]	auto[1]	auto[1]	166	1			T24	7		T25	4		T31	1
all_values[4]	auto[0]	auto[0]	728555	1			T1	3		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	6958	1			T24	1689		T25	342		T31	3
all_values[4]	auto[1]	auto[0]	9	1			T245	2		T253	1		T265	2
all_values[4]	auto[1]	auto[1]	168	1			T24	5		T25	4		T31	3
all_values[5]	auto[0]	auto[0]	728567	1			T1	3		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	6969	1			T24	1692		T25	339		T31	4
all_values[5]	auto[1]	auto[1]	154	1			T24	2		T25	4		T235	2
all_values[6]	auto[0]	auto[0]	728568	1			T1	3		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	6948	1			T24	1688		T25	340		T31	5
all_values[6]	auto[1]	auto[1]	174	1			T24	5		T25	5		T31	1
all_values[7]	auto[0]	auto[0]	698210	1			T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	4304	1			T24	4		T25	293		T31	2
all_values[7]	auto[1]	auto[0]	32070	1			T1	1		T8	126		T9	1
all_values[7]	auto[1]	auto[1]	1106	1			T24	2		T25	52		T31	4
all_values[8]	auto[0]	auto[0]	730066	1			T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	5472	1			T24	1688		T25	339		T31	2
all_values[8]	auto[1]	auto[1]	152	1			T24	6		T25	7		T31	4
all_values[9]	auto[0]	auto[0]	236559	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	6716	1			T24	1658		T25	331		T31	4
all_values[9]	auto[1]	auto[0]	492027	1			T1	1		T2	1		T4	1
all_values[9]	auto[1]	auto[1]	388	1			T24	36		T25	14		T31	1
all_values[10]	auto[0]	auto[0]	728560	1			T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	6975	1			T24	1689		T25	342		T31	5
all_values[10]	auto[1]	auto[1]	155	1			T24	5		T25	3		T31	1
all_values[11]	auto[0]	auto[0]	2382	1			T1	1		T7	1		T8	2
all_values[11]	auto[0]	auto[1]	310	1			T24	13		T25	9		T31	4
all_values[11]	auto[1]	auto[0]	726191	1			T1	2		T2	3		T3	2
all_values[11]	auto[1]	auto[1]	6807	1			T24	1681		T25	337		T31	1
all_values[12]	auto[0]	auto[0]	728507	1			T1	3		T2	3		T3	1
all_values[12]	auto[0]	auto[1]	6974	1			T24	1689		T25	341		T31	4
all_values[12]	auto[1]	auto[0]	60	1			T3	1		T70	1		T71	1
all_values[12]	auto[1]	auto[1]	149	1			T24	6		T25	5		T31	2
all_values[13]	auto[0]	auto[0]	728568	1			T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	6939	1			T24	1689		T25	340		T31	4
all_values[13]	auto[1]	auto[1]	183	1			T24	6		T25	5		T31	2
all_values[14]	auto[0]	auto[0]	730047	1			T1	3		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	5492	1			T24	1690		T25	344		T31	5
all_values[14]	auto[1]	auto[1]	151	1			T24	3		T25	2		T31	1