Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	735690	1			T1	3		T2	3		T3	2
all_pins[1]	735690	1			T1	3		T2	3		T3	2
all_pins[2]	735690	1			T1	3		T2	3		T3	2
all_pins[3]	735690	1			T1	3		T2	3		T3	2
all_pins[4]	735690	1			T1	3		T2	3		T3	2
all_pins[5]	735690	1			T1	3		T2	3		T3	2
all_pins[6]	735690	1			T1	3		T2	3		T3	2
all_pins[7]	735690	1			T1	3		T2	3		T3	2
all_pins[8]	735690	1			T1	3		T2	3		T3	2
all_pins[9]	735690	1			T1	3		T2	3		T3	2
all_pins[10]	735690	1			T1	3		T2	3		T3	2
all_pins[11]	735690	1			T1	3		T2	3		T3	2
all_pins[12]	735690	1			T1	3		T2	3		T3	2
all_pins[13]	735690	1			T1	3		T2	3		T3	2
all_pins[14]	735690	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9182709	1			T1	39		T2	40		T3	27
values[0x1]	1852641	1			T1	6		T2	5		T3	3
transitions[0x0=>0x1]	1852031	1			T1	6		T2	5		T3	3
transitions[0x1=>0x0]	1850714	1			T1	5		T2	4		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	141936	1			T1	1		T3	1		T7	1
all_pins[0]	values[0x1]	593754	1			T1	2		T2	3		T3	1
all_pins[0]	transitions[0x0=>0x1]	593389	1			T1	2		T2	3		T3	1
all_pins[0]	transitions[0x1=>0x0]	53	1			T24	1		T25	2		T259	2
all_pins[1]	values[0x0]	735272	1			T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	418	1			T24	2		T123	28		T264	3
all_pins[1]	transitions[0x0=>0x1]	406	1			T24	2		T123	28		T264	3
all_pins[1]	transitions[0x1=>0x0]	124	1			T169	1		T143	1		T145	1
all_pins[2]	values[0x0]	735554	1			T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	136	1			T169	1		T143	1		T145	1
all_pins[2]	transitions[0x0=>0x1]	117	1			T169	1		T143	1		T145	1
all_pins[2]	transitions[0x1=>0x0]	63	1			T24	6		T31	1		T272	1
all_pins[3]	values[0x0]	735608	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	82	1			T24	6		T25	2		T31	1
all_pins[3]	transitions[0x0=>0x1]	66	1			T24	6		T25	1		T31	1
all_pins[3]	transitions[0x1=>0x0]	71	1			T24	1		T31	1		T245	2
all_pins[4]	values[0x0]	735603	1			T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	87	1			T24	1		T25	1		T31	1
all_pins[4]	transitions[0x0=>0x1]	70	1			T24	1		T25	1		T31	1
all_pins[4]	transitions[0x1=>0x0]	61	1			T25	3		T272	3		T126	1
all_pins[5]	values[0x0]	735612	1			T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	78	1			T25	3		T272	3		T126	2
all_pins[5]	transitions[0x0=>0x1]	58	1			T272	1		T126	2		T129	2
all_pins[5]	transitions[0x1=>0x0]	67	1			T24	2		T31	1		T235	2
all_pins[6]	values[0x0]	735603	1			T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	87	1			T24	2		T25	3		T31	1
all_pins[6]	transitions[0x0=>0x1]	72	1			T24	2		T25	3		T31	1
all_pins[6]	transitions[0x1=>0x0]	35971	1			T1	1		T8	128		T9	1
all_pins[7]	values[0x0]	699704	1			T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	35986	1			T1	1		T8	128		T9	1
all_pins[7]	transitions[0x0=>0x1]	35981	1			T1	1		T8	128		T9	1
all_pins[7]	transitions[0x1=>0x0]	57	1			T24	2		T25	1		T272	4
all_pins[8]	values[0x0]	735628	1			T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	62	1			T24	2		T25	1		T272	5
all_pins[8]	transitions[0x0=>0x1]	50	1			T24	1		T25	1		T272	5
all_pins[8]	transitions[0x1=>0x0]	492329	1			T1	1		T2	1		T4	1
all_pins[9]	values[0x0]	243349	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	492341	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	492324	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	53	1			T24	2		T25	1		T31	1
all_pins[10]	values[0x0]	735620	1			T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	70	1			T24	4		T25	2		T31	1
all_pins[10]	transitions[0x0=>0x1]	57	1			T24	4		T25	2		T31	1
all_pins[10]	transitions[0x1=>0x0]	729217	1			T1	2		T2	1		T3	1
all_pins[11]	values[0x0]	6460	1			T1	1		T2	2		T3	1
all_pins[11]	values[0x1]	729230	1			T1	2		T2	1		T3	1
all_pins[11]	transitions[0x0=>0x1]	729196	1			T1	2		T2	1		T3	1
all_pins[11]	transitions[0x1=>0x0]	103	1			T3	1		T24	4		T70	1
all_pins[12]	values[0x0]	735553	1			T1	3		T2	3		T3	1
all_pins[12]	values[0x1]	137	1			T3	1		T24	4		T70	1
all_pins[12]	transitions[0x0=>0x1]	117	1			T3	1		T24	3		T70	1
all_pins[12]	transitions[0x1=>0x0]	71	1			T24	1		T25	2		T235	1
all_pins[13]	values[0x0]	735599	1			T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	91	1			T24	2		T25	2		T31	1
all_pins[13]	transitions[0x0=>0x1]	70	1			T24	2		T25	2		T31	1
all_pins[13]	transitions[0x1=>0x0]	61	1			T272	3		T126	1		T127	2
all_pins[14]	values[0x0]	735608	1			T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	82	1			T272	3		T126	3		T127	2
all_pins[14]	transitions[0x0=>0x1]	58	1			T272	3		T126	3		T127	2
all_pins[14]	transitions[0x1=>0x0]	592413	1			T1	1		T2	2		T3	1