Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	373	1			T24	11		T25	7		T31	4
all_values[1]	373	1			T24	11		T25	7		T31	4
all_values[2]	373	1			T24	11		T25	7		T31	4
all_values[3]	373	1			T24	11		T25	7		T31	4
all_values[4]	373	1			T24	11		T25	7		T31	4
all_values[5]	373	1			T24	11		T25	7		T31	4
all_values[6]	373	1			T24	11		T25	7		T31	4
all_values[7]	373	1			T24	11		T25	7		T31	4
all_values[8]	373	1			T24	11		T25	7		T31	4
all_values[9]	373	1			T24	11		T25	7		T31	4
all_values[10]	373	1			T24	11		T25	7		T31	4
all_values[11]	373	1			T24	11		T25	7		T31	4
all_values[12]	373	1			T24	11		T25	7		T31	4
all_values[13]	373	1			T24	11		T25	7		T31	4
all_values[14]	373	1			T24	11		T25	7		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3051

1

T24

102

T25

63

T31

28

auto[1]

2544

1

T24

63

T25

42

T31

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963

1

T24

19

T25

9

T31

5

auto[1]

4632

1

T24

146

T25

96

T31

55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3329

1

T24

99

T25

51

T31

32

auto[1]

2266

1

T24

66

T25

54

T31

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1			T24	1		T272	1		T128	1
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T24	2		T25	1		T31	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1			T128	1		T273	1		T131	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T24	2		T25	3		T31	1
all_values[0]	auto[1]	auto[0]	auto[1]	92	1			T24	4		T25	3		T31	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1			T24	2		T31	1		T126	1
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T25	1		T272	3		T274	1
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T24	5		T25	1		T31	2
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T272	2		T274	3		T131	1
all_values[1]	auto[0]	auto[1]	auto[1]	72	1			T24	2		T25	1		T235	1
all_values[1]	auto[1]	auto[0]	auto[1]	84	1			T24	3		T25	1		T31	2
all_values[1]	auto[1]	auto[1]	auto[1]	59	1			T24	1		T25	3		T272	1
all_values[2]	auto[0]	auto[0]	auto[0]	33	1			T235	1		T128	2		T130	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T24	6		T25	2		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T24	1		T235	1		T272	1
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T24	1		T25	1		T272	3
all_values[2]	auto[1]	auto[0]	auto[1]	71	1			T24	1		T25	3		T31	1
all_values[2]	auto[1]	auto[1]	auto[1]	75	1			T24	2		T25	1		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T272	2		T126	1		T128	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T24	1		T25	2		T235	1
all_values[3]	auto[0]	auto[1]	auto[0]	20	1			T31	1		T272	1		T273	1
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T24	4		T25	3		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	84	1			T24	2		T25	2		T235	1
all_values[3]	auto[1]	auto[1]	auto[1]	66	1			T24	4		T31	1		T272	2
all_values[4]	auto[0]	auto[0]	auto[0]	35	1			T235	1		T128	4		T130	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T24	3		T25	3		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	10	1			T24	1		T235	1		T129	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T24	2		T272	3		T126	4
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T24	3		T25	3		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	69	1			T24	2		T25	1		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T25	1		T235	2		T126	1
all_values[5]	auto[0]	auto[0]	auto[1]	90	1			T24	3		T31	1		T235	1
all_values[5]	auto[0]	auto[1]	auto[0]	24	1			T24	1		T25	2		T31	2
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T24	5		T25	1		T272	4
all_values[5]	auto[1]	auto[0]	auto[1]	71	1			T24	1		T31	1		T127	2
all_values[5]	auto[1]	auto[1]	auto[1]	70	1			T24	1		T25	3		T235	1
all_values[6]	auto[0]	auto[0]	auto[0]	43	1			T24	2		T25	1		T272	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T24	5		T235	1		T272	1
all_values[6]	auto[0]	auto[1]	auto[0]	19	1			T131	1		T275	3		T276	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T24	1		T25	2		T31	2
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T24	2		T25	2		T235	1
all_values[6]	auto[1]	auto[1]	auto[1]	73	1			T24	1		T25	2		T31	2
all_values[7]	auto[0]	auto[0]	auto[0]	46	1			T24	2		T25	1		T235	3
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T24	1		T25	1		T31	2
all_values[7]	auto[0]	auto[1]	auto[0]	37	1			T24	5		T235	1		T272	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T126	1		T128	1		T273	4
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T24	3		T25	4		T31	2
all_values[7]	auto[1]	auto[1]	auto[1]	62	1			T25	1		T272	2		T126	1
all_values[8]	auto[0]	auto[0]	auto[0]	51	1			T235	1		T126	5		T128	1
all_values[8]	auto[0]	auto[0]	auto[1]	79	1			T24	5		T25	2		T31	1
all_values[8]	auto[0]	auto[1]	auto[0]	35	1			T24	1		T126	2		T128	3
all_values[8]	auto[0]	auto[1]	auto[1]	60	1			T272	1		T129	2		T273	1
all_values[8]	auto[1]	auto[0]	auto[1]	96	1			T24	2		T25	5		T31	3
all_values[8]	auto[1]	auto[1]	auto[1]	52	1			T24	3		T235	1		T272	4
all_values[9]	auto[0]	auto[0]	auto[0]	39	1			T24	1		T25	1		T235	1
all_values[9]	auto[0]	auto[0]	auto[1]	75	1			T24	4		T25	1		T235	1
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T31	1		T272	2		T128	2
all_values[9]	auto[0]	auto[1]	auto[1]	73	1			T25	1		T31	1		T235	1
all_values[9]	auto[1]	auto[0]	auto[1]	93	1			T24	5		T25	1		T272	2
all_values[9]	auto[1]	auto[1]	auto[1]	67	1			T24	1		T25	3		T31	2
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T24	1		T25	1		T128	1
all_values[10]	auto[0]	auto[0]	auto[1]	88	1			T24	3		T25	1		T31	2
all_values[10]	auto[0]	auto[1]	auto[0]	14	1			T129	2		T274	1		T277	1
all_values[10]	auto[0]	auto[1]	auto[1]	77	1			T24	2		T25	2		T31	1
all_values[10]	auto[1]	auto[0]	auto[1]	95	1			T24	2		T25	1		T235	2
all_values[10]	auto[1]	auto[1]	auto[1]	60	1			T24	3		T25	2		T31	1
all_values[11]	auto[0]	auto[0]	auto[0]	27	1			T24	1		T31	1		T128	1
all_values[11]	auto[0]	auto[0]	auto[1]	73	1			T24	4		T25	3		T31	2
all_values[11]	auto[0]	auto[1]	auto[0]	39	1			T127	1		T129	4		T274	1
all_values[11]	auto[0]	auto[1]	auto[1]	81	1			T24	2		T25	2		T235	1
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T24	4		T25	1		T31	1
all_values[11]	auto[1]	auto[1]	auto[1]	73	1			T25	1		T272	1		T126	1
all_values[12]	auto[0]	auto[0]	auto[0]	37	1			T235	1		T127	2		T128	1
all_values[12]	auto[0]	auto[0]	auto[1]	77	1			T24	1		T25	2		T235	2
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T272	3		T129	3		T278	1
all_values[12]	auto[0]	auto[1]	auto[1]	85	1			T24	4		T31	2		T272	1
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T24	4		T25	3		T235	1
all_values[12]	auto[1]	auto[1]	auto[1]	70	1			T24	2		T25	2		T31	2
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T25	1		T126	2		T128	1
all_values[13]	auto[0]	auto[0]	auto[1]	88	1			T24	5		T25	2		T235	2
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T272	1		T126	3		T127	1
all_values[13]	auto[0]	auto[1]	auto[1]	67	1			T24	1		T25	1		T31	3
all_values[13]	auto[1]	auto[0]	auto[1]	91	1			T24	2		T25	2		T235	1
all_values[13]	auto[1]	auto[1]	auto[1]	66	1			T24	3		T25	1		T31	1
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T272	1		T126	2		T128	1
all_values[14]	auto[0]	auto[0]	auto[1]	70	1			T24	5		T25	1		T235	1
all_values[14]	auto[0]	auto[1]	auto[0]	36	1			T24	2		T126	1		T127	1
all_values[14]	auto[0]	auto[1]	auto[1]	78	1			T24	1		T25	3		T31	2
all_values[14]	auto[1]	auto[0]	auto[1]	77	1			T24	3		T25	3		T31	2
all_values[14]	auto[1]	auto[1]	auto[1]	67	1			T272	3		T126	1		T127	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal